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-- Btrace 448
-- Controller
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.btrace_pack.all;
entity controller is
port(clk, rst: in std_logic;
-- Control outputs
init_x, init_y, inc_x, inc_y: out std_logic;
set_vector, set_org: out std_logic;
next_obj, start_search: out std_logic;
clr_z_reg, clr_hit: out std_logic;
store: out std_logic;
paint: out std_logic;
done: out std_logic;
-- Status inputs
last_x, last_y, last_obj, obj_valid, start: in std_logic);
end controller;
architecture arch of controller is
-- Controller states
type states_t is (s_idle, s_start, s_set, s_wait, s_next, s_done);
signal controller_state: states_t := s_idle;
begin
process(clk, rst)
begin
if rst = '1' then
controller_state <= s_idle;
elsif rising_edge(clk) then
case controller_state is
when s_idle =>
if start = '1' then
controller_state <= s_start;
end if;
when s_start =>
controller_state <= s_set;
when s_set =>
controller_state <= s_wait;
when s_wait =>
controller_state <= s_next;
when s_next =>
if last_obj = '0' then
controller_state <= s_wait;
else
if last_x = '0' then
controller_state <= s_start;
else
if last_y = '0' then
controller_state <= s_start;
else
controller_state <= s_done;
end if;
end if;
end if;
when others =>
if start = '1' then
controller_state <= s_done;
else
controller_state <= s_idle;
end if;
end case;
end if;
end process;
clr_hit <= '1' when controller_state = s_start else '0';
clr_z_reg <= '1' when controller_state = s_start else '0';
init_x <= '1' when (controller_state = s_idle) or ((controller_state = s_next) and ((last_obj and last_x) = '1') and (last_y = '0')) else '0';
inc_y <= '1' when ((controller_state = s_next) and ((last_obj and last_x) = '1') and (last_y = '0')) else '0';
inc_x <= '1' when ((controller_state = s_next) and (last_obj = '1') and (last_x = '0')) else '0';
init_y <= '1' when (controller_state = s_idle) else '0';
set_vector <= '1' when controller_state = s_set else '0';
set_org <= '1' when controller_state = s_set else '0';
store <= '1' when (controller_state = s_wait) and (obj_valid = '1') else '0';
paint <= '1' when (controller_state = s_next) and (last_obj = '1') else '0';
next_obj <= '1' when (controller_state = s_next) else '0';
start_search <= '1' when (controller_state = s_start) else '0';
done <= '1' when (controller_state = s_done) else '0';
end arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 0;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_7_full_dsp_32_u : component convolve_kernel_ap_fadd_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- LEDS.VHD (a peripheral module for SCOMP)
-- 2006.10.08
--
-- This module drives the UP3 board LEDs and latches data on the rising edge of CS.
LIBRARY IEEE;
LIBRARY LPM;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE LPM.LPM_COMPONENTS.ALL;
ENTITY LEDS IS
PORT(
RESETN : IN STD_LOGIC;
CS : IN STD_LOGIC;
LED : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
IO_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END LEDS;
ARCHITECTURE a OF LEDS IS
SIGNAL BLED : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
LED <= BLED;
PROCESS (RESETN, CS)
BEGIN
IF (RESETN = '0') THEN
BLED <= x"0000";
ELSIF (RISING_EDGE(CS)) THEN
BLED <= IO_DATA;
END IF;
END PROCESS;
END a;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multi_oc is
port (
si : in std_logic_vector (3 downto 0);
se : in std_logic_vector (1 downto 0);
so : out std_logic
);
end entity;
architecture behav of multi_oc is
signal s0, s1, s2, s3 : std_logic;
signal sen : std_logic_vector(1 downto 0);
begin
sen <= not se;
s0 <= 'X' when (sen(0)='1' and sen(1)='1' and si(0) = '1') else '0';
s1 <= 'X' when (se(0)='1' and sen(1)='1' and si(2) = '1') else '0';
s2 <= 'X' when (sen(0)='1' and se(1)='1' and si(2) = '1') else '0';
s3 <= 'X' when (se(0)='1' and se(1)='1' and si(3) = '1') else '0';
so <= s0;
so <= s1;
s0 <= s2;
s0 <= s3;
end architecture;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_tb
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use std.env.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library bitvis_vip_sbi;
use bitvis_vip_sbi.sbi_bfm_pkg.all;
use work.irqc_pif_pkg.all;
-- Test case entity
entity irqc_tb is
end entity;
-- Test case architecture
architecture func of irqc_tb is
-- DSP interface and general control signals
signal clk : std_logic := '0';
signal arst : std_logic := '0';
-- CPU interface
signal sbi_if : t_sbi_if(addr(2 downto 0), wdata(7 downto 0), rdata(7 downto 0)) := init_sbi_if_signals(3, 8);
-- Interrupt related signals
signal irq_source : std_logic_vector(C_NUM_SOURCES-1 downto 0) := (others => '0');
signal irq2cpu : std_logic := '0';
signal irq2cpu_ack : std_logic := '0';
signal clock_ena : boolean := false;
constant C_CLK_PERIOD : time := 10 ns;
procedure clock_gen(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time
) is
variable v_first_half_clk_period : time := C_CLK_PERIOD / 2;
begin
loop
if not clock_ena then
wait until clock_ena;
end if;
wait for v_first_half_clk_period;
clock_signal <= not clock_signal;
wait for (clock_period - v_first_half_clk_period);
clock_signal <= not clock_signal;
end loop;
end;
subtype t_irq_source is std_logic_vector(C_NUM_SOURCES-1 downto 0);
-- Trim (cut) a given vector to fit the number of irq sources (i.e. pot. reduce width)
function trim(
constant source : std_logic_vector;
constant num_bits : positive := C_NUM_SOURCES)
return t_irq_source is
variable v_result : std_logic_vector(source'length-1 downto 0) := source;
begin
return v_result(num_bits-1 downto 0);
end;
-- Fit a given vector to the number of irq sources by masking with zeros above irq width
function fit(
constant source : std_logic_vector;
constant num_bits : positive := C_NUM_SOURCES)
return std_logic_vector is
variable v_result : std_logic_vector(source'length-1 downto 0) := (others => '0');
variable v_source : std_logic_vector(source'length-1 downto 0) := source;
begin
v_result(num_bits-1 downto 0) := v_source(num_bits-1 downto 0);
return v_result;
end;
begin
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_irqc: entity work.irqc
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => sbi_if.cs,
addr => sbi_if.addr,
wr => sbi_if.wena,
rd => sbi_if.rena,
din => sbi_if.wdata,
dout => sbi_if.rdata,
-- Interrupt related signals
irq_source => irq_source,
irq2cpu => irq2cpu,
irq2cpu_ack => irq2cpu_ack
);
sbi_if.ready <= '1'; -- always ready in the same clock cycle.
-- Set upt clock generator
clock_gen(clk, clock_ena, 10 ns);
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
procedure pulse(
signal target : inout std_logic;
signal clock_signal : in std_logic;
constant num_periods : in natural;
constant msg : in string
) is
begin
if num_periods > 0 then
wait until falling_edge(clock_signal);
target <= '1';
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else
target <= '1';
wait for 0 ns; -- Delta cycle only
end if;
target <= '0';
log(ID_SEQUENCER_SUB, msg, C_SCOPE);
end;
procedure pulse(
signal target : inout std_logic_vector;
constant pulse_value : in std_logic_vector;
signal clock_signal : in std_logic;
constant num_periods : in natural;
constant msg : in string) is
begin
if num_periods > 0 then
wait until falling_edge(clock_signal);
target <= pulse_value;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else
target <= pulse_value;
wait for 0 ns; -- Delta cycle only
end if;
target(target'range) <= (others => '0');
log(ID_SEQUENCER_SUB, "Pulsed to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) & ". " & add_msg_delimiter(msg), C_SCOPE);
end;
-- Log overloads for simplification
procedure log(
msg : string) is
begin
log(ID_SEQUENCER, msg, C_SCOPE);
end;
-- Overloads for PIF BFMs for SBI (Simple Bus Interface)
procedure write(
constant addr_value : in natural;
constant data_value : in std_logic_vector;
constant msg : in string) is
begin
sbi_write(to_unsigned(addr_value, sbi_if.addr'length), data_value, msg,
clk, sbi_if, C_SCOPE);
end;
procedure check(
constant addr_value : in natural;
constant data_exp : in std_logic_vector;
constant alert_level : in t_alert_level;
constant msg : in string) is
begin
sbi_check(to_unsigned(addr_value, sbi_if.addr'length), data_exp, msg,
clk, sbi_if, alert_level, C_SCOPE);
end;
procedure set_inputs_passive(
dummy : t_void) is
begin
sbi_if.cs <= '0';
sbi_if.addr <= (others => '0');
sbi_if.wena <= '0';
sbi_if.rena <= '0';
sbi_if.wdata <= (others => '0');
irq_source <= (others => '0');
irq2cpu_ack <= '0';
log(ID_SEQUENCER_SUB, "All inputs set passive", C_SCOPE);
end;
variable v_time_stamp : time := 0 ns;
variable v_irq_mask : std_logic_vector(7 downto 0);
variable v_irq_mask_inv : std_logic_vector(7 downto 0);
begin
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
enable_log_msg(ALL_MESSAGES);
--disable_log_msg(ALL_MESSAGES);
--enable_log_msg(ID_LOG_HDR);
log(ID_LOG_HDR, "Start Simulation of TB for IRQC", C_SCOPE);
------------------------------------------------------------
set_inputs_passive(VOID);
clock_ena <= true; -- to start clock generator
pulse(arst, clk, 10, "Pulsed reset-signal - active for 10T");
v_time_stamp := now; -- time from which irq2cpu should be stable off until triggered
check_value(C_NUM_SOURCES > 0, FAILURE, "Must be at least 1 interrupt source", C_SCOPE);
check_value(C_NUM_SOURCES <= 8, TB_WARNING, "This TB is only checking IRQC with up to 8 interrupt sources", C_SCOPE);
log(ID_LOG_HDR, "Check defaults on output ports", C_SCOPE);
------------------------------------------------------------
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must be default inactive", C_SCOPE);
check_value(sbi_if.rdata, x"00", ERROR, "Register data bus output must be default passive");
log(ID_LOG_HDR, "Check register defaults and access (write + read)", C_SCOPE);
------------------------------------------------------------
log("\nChecking Register defaults");
check(C_ADDR_IRR, x"00", ERROR, "IRR default");
check(C_ADDR_IER, x"00", ERROR, "IER default");
check(C_ADDR_IPR, x"00", ERROR, "IPR default");
check(C_ADDR_IRQ2CPU_ALLOWED, x"00", ERROR, "IRQ2CPU_ALLOWED default");
log("\nChecking Register Write/Read");
write(C_ADDR_IER, fit(x"55"), "IER");
check(C_ADDR_IER, fit(x"55"), ERROR, "IER pure readback");
write(C_ADDR_IER, fit(x"AA"), "IER");
check(C_ADDR_IER, fit(x"AA"), ERROR, "IER pure readback");
write(C_ADDR_IER, fit(x"00"), "IER");
check(C_ADDR_IER, fit(x"00"), ERROR, "IER pure readback");
log(ID_LOG_HDR, "Check register trigger/clear mechanism", C_SCOPE);
------------------------------------------------------------
write(C_ADDR_ITR, fit(x"AA"), "ITR : Set interrupts");
check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR");
write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts");
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR");
write(C_ADDR_ICR, fit(x"71"), "ICR : Clear interrupts");
check(C_ADDR_IRR, fit(x"8E"), ERROR, "IRR");
write(C_ADDR_ICR, fit(x"85"), "ICR : Clear interrupts");
check(C_ADDR_IRR, fit(x"0A"), ERROR, "IRR");
write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts");
check(C_ADDR_IRR, fit(x"5F"), ERROR, "IRR");
write(C_ADDR_ICR, fit(x"5F"), "ICR : Clear interrupts");
check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR");
log(ID_LOG_HDR, "Check interrupt sources, IER, IPR and irq2cpu", C_SCOPE);
------------------------------------------------------------
log("\nChecking interrupts and IRR");
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
pulse(irq_source, trim(x"AA"), clk, 1, "Pulse irq_source 1T");
check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR after irq pulses");
pulse(irq_source, trim(x"01"), clk, 1, "Add more interrupts");
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses");
pulse(irq_source, trim(x"A1"), clk, 1, "Repeat same interrupts");
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses");
pulse(irq_source, trim(x"54"), clk, 1, "Add remaining interrupts");
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR after irq pulses");
write(C_ADDR_ICR, fit(x"AA"), "ICR : Clear half the interrupts");
pulse(irq_source, trim(x"A0"), clk, 1, "Add more interrupts");
check(C_ADDR_IRR, fit(x"F5"), ERROR, "IRR after irq pulses");
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR after clearing all");
log("\nChecking IER, IPR and irq2cpu");
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
write(C_ADDR_IER, fit(x"55"), "IER : Enable some interrupts");
write(C_ADDR_ITR, fit(x"AA"), "ITR : Trigger non-enable interrupts");
check(C_ADDR_IPR, fit(x"00"), ERROR, "IPR should not be active");
check(C_ADDR_IRQ2CPU_ALLOWED, x"00", ERROR, "IRQ2CPU_ALLOWED should not be active");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Enable main interrupt to CPU");
check(C_ADDR_IRQ2CPU_ALLOWED, x"01", ERROR, "IRQ2CPU_ALLOWED should now be active");
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must still be inactive", C_SCOPE);
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu", C_SCOPE);
pulse(irq_source, trim(x"01"), clk, 1, "Add a single enabled interrupt");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt expected immediately", C_SCOPE);
v_time_stamp := now; -- from time of stable active irq2cpu
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR should now be active");
check(C_ADDR_IPR, fit(x"01"), ERROR, "IPR should now be active");
log("\nMore details checked in the autonomy section below");
check_value(irq2cpu, '1', ERROR, "Interrupt to CPU must still be active", C_SCOPE);
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu", C_SCOPE);
log(ID_LOG_HDR, "Check autonomy for all interrupts", C_SCOPE);
------------------------------------------------------------
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
write(C_ADDR_IER, fit(x"FF"), "IER : Disable all interrupts");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU");
for i in 0 to C_NUM_SOURCES-1 loop
log(" ");
log("- Checking irq_source(" & to_string(i) & ") and all corresponding functionality");
log("- - Check interrupt activation not affected by non related interrupts or registers");
v_time_stamp := now; -- from time of stable inactive irq2cpu
v_irq_mask := (others => '0');
v_irq_mask(i) := '1';
v_irq_mask_inv := (others => '1');
v_irq_mask_inv(i) := '0';
write(C_ADDR_IER, v_irq_mask, "IER : Enable selected interrupt");
pulse(irq_source, trim(v_irq_mask_inv), clk, 1, "Pulse all non-enabled interrupts");
write(C_ADDR_ITR, v_irq_mask_inv, "ITR : Trigger all non-enabled interrupts");
check(C_ADDR_IRR, fit(v_irq_mask_inv), ERROR, "IRR not yet triggered");
check(C_ADDR_IPR, x"00", ERROR, "IPR not yet triggered");
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must still be inactive", C_SCOPE);
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu", C_SCOPE);
pulse(irq_source, trim(v_irq_mask), clk, 1, "Pulse the enabled interrupt");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt expected immediately", C_SCOPE);
check(C_ADDR_IRR, fit(x"FF"), ERROR, "All IRR triggered");
check(C_ADDR_IPR, v_irq_mask, ERROR, "IPR triggered for selected");
log("\n- - Check interrupt deactivation not affected by non related interrupts or registers");
v_time_stamp := now; -- from time of stable active irq2cpu
write(C_ADDR_ICR, v_irq_mask_inv, "ICR : Clear all non-enabled interrupts");
write(C_ADDR_IER, fit(x"FF"), "IER : Enable all interrupts");
write(C_ADDR_IER, v_irq_mask, "IER : Disable non-selected interrupts");
pulse(irq_source, trim(x"FF"), clk, 1, "Pulse all interrupts");
write(C_ADDR_ITR, x"FF", "ITR : Trigger all interrupts");
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu (='1')", C_SCOPE);
write(C_ADDR_IER, v_irq_mask_inv, "IER : Enable all interrupts but disable selected");
check_value(irq2cpu, '1', ERROR, "Interrupt to CPU still active", C_SCOPE);
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR still active for all");
write(C_ADDR_ICR, v_irq_mask_inv, "ICR : Clear all non-enabled interrupts");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation expected immediately", C_SCOPE);
write(C_ADDR_IER, v_irq_mask, "IER : Re-enable selected interrupt");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt reactivation expected immediately", C_SCOPE);
check(C_ADDR_IPR, v_irq_mask, ERROR, "IPR still active for selected");
write(C_ADDR_ICR, v_irq_mask, "ICR : Clear selected interrupt");
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must go inactive", C_SCOPE);
check(C_ADDR_IRR, x"00", ERROR, "IRR all inactive");
check(C_ADDR_IPR, x"00", ERROR, "IPR all inactive");
write(C_ADDR_IER, x"00", "IER : Disable all interrupts");
end loop;
report_alert_counters(INTERMEDIATE); -- Report intermediate counters
log(ID_LOG_HDR, "Check irq acknowledge and re-enable", C_SCOPE);
------------------------------------------------------------
log("- Activate interrupt");
write(C_ADDR_ITR, v_irq_mask, "ICR : Set single upper interrupt");
write(C_ADDR_IER, v_irq_mask, "IER : Enable single upper interrupts");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt activation expected", C_SCOPE);
v_time_stamp := now; -- from time of stable active irq2cpu
log("\n- Try potential malfunction");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU again - should not affect anything");
write(C_ADDR_IRQ2CPU_ENA, x"00", "IRQ2CPU_ENA : Set to 0 - should not affect anything");
write(C_ADDR_IRQ2CPU_DISABLE, x"00", "IRQ2CPU_DISABLE : Set to 0 - should not affect anything");
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu (='1')", C_SCOPE);
log("\n- Acknowledge and deactivate interrupt");
pulse(irq2cpu_ack, clk, 1, "Pulse irq2cpu_ack");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation expected", C_SCOPE);
v_time_stamp := now; -- from time of stable inactive irq2cpu
log("\n- Test for potential malfunction");
write(C_ADDR_IRQ2CPU_DISABLE, x"01", "IRQ2CPU_DISABLE : Disable interrupt to CPU again - should not affect anything");
write(C_ADDR_IRQ2CPU_DISABLE, x"00", "IRQ2CPU_DISABLE : Set to 0 - should not affect anything");
write(C_ADDR_IRQ2CPU_ENA, x"00", "IRQ2CPU_ENA : Set to 0 - should not affect anything");
write(C_ADDR_ITR, x"FF", "ICR : Trigger all interrupts");
write(C_ADDR_IER, x"FF", "IER : Enable all interrupts");
pulse(irq_source, trim(x"FF"), clk, 1, "Pulse all interrupts");
pulse(irq2cpu_ack, clk, 1, "Pulse irq2cpu_ack");
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu (='0')", C_SCOPE);
log("\n- Re-/de-activation");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Reactivate interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt reactivation expected", C_SCOPE);
write(C_ADDR_IRQ2CPU_DISABLE, x"01", "IRQ2CPU_DISABLE : Deactivate interrupt to CPU");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation expected", C_SCOPE);
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Reactivate interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt reactivation expected", C_SCOPE);
log(ID_LOG_HDR, "Check Reset", C_SCOPE);
------------------------------------------------------------
log("- Activate all interrupts");
write(C_ADDR_ITR, x"FF", "ICR : Set all interrupts");
write(C_ADDR_IER, x"FF", "IER : Enable all interrupts");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt activation expected", C_SCOPE);
pulse(arst, clk, 1, "Pulse reset");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation", C_SCOPE);
check(C_ADDR_IER, x"00", ERROR, "IER all inactive");
check(C_ADDR_IRR, x"00", ERROR, "IRR all inactive");
check(C_ADDR_IPR, x"00", ERROR, "IPR all inactive");
--==================================================================================================
-- Ending the simulation
--------------------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_main;
end func;
|
-------------------------------------------------------------------------------
--
-- ROM core VHDL template. See the macro description included
-- behind this frame.
--
-- Copyright (C) 2000 Rudolf Matousek <[email protected]>
--
-- Modified by Jiri Gaisler <[email protected]> for LEON boot prom.
--
-- This code may be used under the terms of Version 2 of the GPL,
-- read the file COPYING for details.
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity gen_bprom is
port(
clk : in std_logic;
csn : in std_logic;
addr : in std_logic_vector (29 downto 0);
data : out std_logic_vector (31 downto 0)
);
end;
architecture rtl of gen_bprom is
signal raddr : std_logic_vector(9 downto 0);
signal d : std_logic_vector(31 downto 0);
attribute syn_romstyle : string;
attribute syn_romstyle of d : signal is "select_rom";
begin
p : process(raddr)
begin
case raddr is
when "0000000000" => d <= "10000001100010000010000011100000";
when "0000000001" => d <= "10000001100100000010000000000010";
when "0000000010" => d <= "10000001110110000010000000000000";
when "0000000011" => d <= "00000011000000000000000001000000";
when "0000000100" => d <= "10000010000100000110000000001111";
when "0000000101" => d <= "00010001001000000000000000000000";
when "0000000110" => d <= "10001000001000100010000000010000";
when "0000000111" => d <= "11000010001000100010000000010100";
when "0000001000" => d <= "11010010000000100010000000100100";
when "0000001001" => d <= "10010010000010100110000000010000";
when "0000001010" => d <= "10010011001010100110000000001000";
when "0000001011" => d <= "10000001100010100110000011100000";
when "0000001100" => d <= "00010011000000000000000000101010";
when "0000001101" => d <= "10010010000100100110001000000000";
when "0000001110" => d <= "11010010001000100010000010100100";
when "0000001111" => d <= "11000000001000100010000001110100";
when "0000010000" => d <= "11000000001000100010000010000100";
when "0000010001" => d <= "10010010000100000010000000000011";
when "0000010010" => d <= "11010010001000100010000001111000";
when "0000010011" => d <= "11010010001000100010000010001000";
when "0000010100" => d <= "10010010000100000011111111111111";
when "0000010101" => d <= "11010010001000100010000001000100";
when "0000010110" => d <= "10010010000100000010000000000111";
when "0000010111" => d <= "11010010001000100010000001001000";
when "0000011000" => d <= "00010011000100000000000000000000";
when "0000011001" => d <= "00010101000000000000000000000111";
when "0000011010" => d <= "10010100000100101010001000100000";
when "0000011011" => d <= "11010100001000100010000000000100";
when "0000011100" => d <= "00010111000000000100100011010001";
when "0000011101" => d <= "10010110000100101110000101100111";
when "0000011110" => d <= "11010110001000100100000000000000";
when "0000011111" => d <= "11000000001000100110000000000100";
when "0000100000" => d <= "11011000100000100100000000000000";
when "0000100001" => d <= "10000000101000101100000000001100";
when "0000100010" => d <= "00000010100000000000000000001101";
when "0000100011" => d <= "11000000001000100100000000000000";
when "0000100100" => d <= "10010100001000101010000000010000";
when "0000100101" => d <= "11010100001000100010000000000100";
when "0000100110" => d <= "11010110001000100100000000000000";
when "0000100111" => d <= "11000000001000100110000000000100";
when "0000101000" => d <= "11011000100000100100000000000000";
when "0000101001" => d <= "10000000101000101100000000001100";
when "0000101010" => d <= "00000010100000000000000000000101";
when "0000101011" => d <= "00000001000000000000000000000000";
when "0000101100" => d <= "10010100001000101010000000010000";
when "0000101101" => d <= "00010000100000000000000000001010";
when "0000101110" => d <= "11010100001000100010000000000100";
when "0000101111" => d <= "11010110001000100100000000000000";
when "0000110000" => d <= "11000000001010100110000000000011";
when "0000110001" => d <= "11011000100000100100000000000000";
when "0000110010" => d <= "10000000101000101100000000001100";
when "0000110011" => d <= "00010010100000000000000000000100";
when "0000110100" => d <= "00000001000000000000000000000000";
when "0000110101" => d <= "10010100000100101010000001000000";
when "0000110110" => d <= "11010100001000100010000000000100";
when "0000110111" => d <= "00000101000001000000000000000000";
when "0000111000" => d <= "11010110001000010000000000000000";
when "0000111001" => d <= "11000000001000010011111111111100";
when "0000111010" => d <= "11011010100000010000000000000000";
when "0000111011" => d <= "10000000101000110100000000001011";
when "0000111100" => d <= "00110010101111111111111111111100";
when "0000111101" => d <= "10001000101000010000000000000010";
when "0000111110" => d <= "10001011001100010010000000011100";
when "0000111111" => d <= "10001010001000010110000000000100";
when "0001000000" => d <= "10010010000000001000000000001001";
when "0001000001" => d <= "10010010001000100110000000010000";
when "0001000010" => d <= "11010110001000100100000000000000";
when "0001000011" => d <= "10000101001100001010000000000001";
when "0001000100" => d <= "10010100001000101010001000000000";
when "0001000101" => d <= "11010100001000100010000000000100";
when "0001000110" => d <= "10010010001000100100000000000010";
when "0001000111" => d <= "11011010100000100100000000000000";
when "0001001000" => d <= "10000000101000110100000000001011";
when "0001001001" => d <= "00000010101111111111111111111010";
when "0001001010" => d <= "00000001000000000000000000000000";
when "0001001011" => d <= "10010100000000101010001000000000";
when "0001001100" => d <= "11010100001000100010000000000100";
when "0001001101" => d <= "00001001000100000000000000000000";
when "0001001110" => d <= "10010010000000100100000000000010";
when "0001001111" => d <= "10010010001010100100000000000100";
when "0001010000" => d <= "10010011001010100100000000000101";
when "0001010001" => d <= "10011100000100100100000000000100";
when "0001010010" => d <= "10010111001010010110000000000001";
when "0001010011" => d <= "01000000000000000000000000011011";
when "0001010100" => d <= "10010000000100000010001101101000";
when "0001010101" => d <= "10010010000100000010001101100000";
when "0001010110" => d <= "01000000000000000000000000011000";
when "0001010111" => d <= "10010000000000101100000000001001";
when "0001011000" => d <= "10010010000100000010001100110000";
when "0001011001" => d <= "10001011001100101010000000000110";
when "0001011010" => d <= "10001010001000010110000000100000";
when "0001011011" => d <= "10001010001010010110000000000001";
when "0001011100" => d <= "01000000000000000000000000010010";
when "0001011101" => d <= "10010000000000100100000000000101";
when "0001011110" => d <= "10010010000100000010001100100100";
when "0001011111" => d <= "10001011001100101010000000000010";
when "0001100000" => d <= "10001010000010010110000000001100";
when "0001100001" => d <= "01000000000000000000000000001101";
when "0001100010" => d <= "10010000000000100100000000000101";
when "0001100011" => d <= "01000000000000000000000000001011";
when "0001100100" => d <= "10010000000100000010001101110001";
when "0001100101" => d <= "10000000100010101010000001000000";
when "0001100110" => d <= "00000010100000000000000000000100";
when "0001100111" => d <= "00000001000000000000000000000000";
when "0001101000" => d <= "01000000000000000000000000000110";
when "0001101001" => d <= "10010000000100000010001101111100";
when "0001101010" => d <= "01000000000000000000000000000100";
when "0001101011" => d <= "10010000000100000010001110000010";
when "0001101100" => d <= "01000000000000000000000000100101";
when "0001101101" => d <= "00000001000000000000000000000000";
when "0001101110" => d <= "11000100000010100000000000000000";
when "0001101111" => d <= "10000000101000001010000000000000";
when "0001110000" => d <= "00000010100000000000000000001101";
when "0001110001" => d <= "00010011001000000000000000000000";
when "0001110010" => d <= "11000110000010100000000000000000";
when "0001110011" => d <= "10010000000000100010000000000001";
when "0001110100" => d <= "11000100000000100110000001110100";
when "0001110101" => d <= "10000000100010001010000000000100";
when "0001110110" => d <= "00000010101111111111111111111110";
when "0001110111" => d <= "10000100000010001110000011111111";
when "0001111000" => d <= "11000100001000100110000001110000";
when "0001111001" => d <= "11000100000010100000000000000000";
when "0001111010" => d <= "10000000101000001010000000000000";
when "0001111011" => d <= "00110010101111111111111111111000";
when "0001111100" => d <= "11000110000010100000000000000000";
when "0001111101" => d <= "10000001110000111110000000001000";
when "0001111110" => d <= "00000001000000000000000000000000";
when "0001111111" => d <= "10010110000100000000000000001000";
when "0010000000" => d <= "10010000000100000010000000000000";
when "0010000001" => d <= "10000000101000100000000000001011";
when "0010000010" => d <= "00011010100000000000000000001101";
when "0010000011" => d <= "10010100000100000010000000000000";
when "0010000100" => d <= "11000100000010100100000000001010";
when "0010000101" => d <= "10000000101000001010000001000000";
when "0010000110" => d <= "00101000100000000000000000000011";
when "0010000111" => d <= "10000100000000001011111111010000";
when "0010001000" => d <= "10000100000000001011111111001001";
when "0010001001" => d <= "10000111001010100010000000000100";
when "0010001010" => d <= "10000100000010001010000011111111";
when "0010001011" => d <= "10010100000000101010000000000001";
when "0010001100" => d <= "10000000101000101000000000001011";
when "0010001101" => d <= "00001010101111111111111111110111";
when "0010001110" => d <= "10010000000100001100000000000010";
when "0010001111" => d <= "10000001110000111110000000001000";
when "0010010000" => d <= "00000001000000000000000000000000";
when "0010010001" => d <= "10011101111000111011111010011000";
when "0010010010" => d <= "00101001001000000000000000000000";
when "0010010011" => d <= "10101100000001111011111011111100";
when "0010010100" => d <= "10101010000001111011111100000100";
when "0010010101" => d <= "10010100000001111011111011111000";
when "0010010110" => d <= "11010000000001010010000001110100";
when "0010010111" => d <= "10000000100010100010000000000001";
when "0010011000" => d <= "00000010101111111111111111111110";
when "0010011001" => d <= "00000001000000000000000000000000";
when "0010011010" => d <= "11010000000001010010000001110000";
when "0010011011" => d <= "10010010000010100010000011111111";
when "0010011100" => d <= "10000000101000100110000000001101";
when "0010011101" => d <= "00000010100000000000000000000101";
when "0010011110" => d <= "11010000001010101000000000000000";
when "0010011111" => d <= "10000000101000100110000000001010";
when "0010100000" => d <= "00010010101111111111111111110110";
when "0010100001" => d <= "10010100000000101010000000000001";
when "0010100010" => d <= "11010000000011111011111011111000";
when "0010100011" => d <= "10000000101000100010000001010011";
when "0010100100" => d <= "00010010101111111111111111110010";
when "0010100101" => d <= "10010100000001111011111011111000";
when "0010100110" => d <= "10010000000100000010000000001000";
when "0010100111" => d <= "01111111111111111111111111011000";
when "0010101000" => d <= "10010010000100000000000000010110";
when "0010101001" => d <= "10100110000100000000000000001000";
when "0010101010" => d <= "11010000000011111011111011111001";
when "0010101011" => d <= "10000000101000100010000000110011";
when "0010101100" => d <= "00010010100000000000000000010111";
when "0010101101" => d <= "10000000101000100010000000110111";
when "0010101110" => d <= "10010000000100000010000000000010";
when "0010101111" => d <= "01111111111111111111111111010000";
when "0010110000" => d <= "10010010000001111011111011111010";
when "0010110001" => d <= "10010001001010100010000000000001";
when "0010110010" => d <= "10010000000000100011111111110110";
when "0010110011" => d <= "10100101001100100010000000000001";
when "0010110100" => d <= "10100010000100000010000000000000";
when "0010110101" => d <= "10000000101001000100000000010010";
when "0010110110" => d <= "00010110101111111111111111100000";
when "0010110111" => d <= "10010100000001111011111011111000";
when "0010111000" => d <= "10100000000100000000000000010101";
when "0010111001" => d <= "10010010000100000000000000010000";
when "0010111010" => d <= "01111111111111111111111111000101";
when "0010111011" => d <= "10010000000100000010000000000010";
when "0010111100" => d <= "11010000001011001100000000010001";
when "0010111101" => d <= "10100010000001000110000000000001";
when "0010111110" => d <= "10000000101001000100000000010010";
when "0010111111" => d <= "00000110101111111111111111111010";
when "0011000000" => d <= "10100000000001000010000000000010";
when "0011000001" => d <= "00010000101111111111111111010101";
when "0011000010" => d <= "10010100000001111011111011111000";
when "0011000011" => d <= "00010010101111111111111111010011";
when "0011000100" => d <= "10010100000001111011111011111000";
when "0011000101" => d <= "10011111110001001100000000000000";
when "0011000110" => d <= "00000001000000000000000000000000";
when "0011000111" => d <= "00010000101111111111111111001111";
when "0011001000" => d <= "10010100000001111011111011111000";
when "0011001001" => d <= "00100000001110000010110100000000";
when "0011001010" => d <= "00110001001101100010110100000000";
when "0011001011" => d <= "00110011001100100010110100000000";
when "0011001100" => d <= "00101010001100010011001000111000";
when "0011001101" => d <= "01001011001000000000000000000000";
when "0011001110" => d <= "00101010001100100011010100110110";
when "0011001111" => d <= "01001011001000000000000000000000";
when "0011010000" => d <= "00101010001101010011000100110010";
when "0011010001" => d <= "01001011001000000000000000000000";
when "0011010010" => d <= "00101010001100010011000000110010";
when "0011010011" => d <= "00110100010010110010000000000000";
when "0011010100" => d <= "00101010001100100011000000110100";
when "0011010101" => d <= "00111000010010110010000000000000";
when "0011010110" => d <= "00101010001101000011000000111001";
when "0011010111" => d <= "00110110010010110010000000000000";
when "0011011000" => d <= "00110001000000000011001000000000";
when "0011011001" => d <= "00110011000000000011010000000000";
when "0011011010" => d <= "01001100010001010100111101001110";
when "0011011011" => d <= "00101101001100010011101000100000";
when "0011011100" => d <= "00000000011000100110100101110100";
when "0011011101" => d <= "00100000011011010110010101101101";
when "0011011110" => d <= "01101111011100100111100100000000";
when "0011011111" => d <= "00101100001000000111001001101101";
when "0011100000" => d <= "01110111000000000000101000001010";
when "0011100001" => d <= "00001101001111100010000000000000";
when "0011100010" => d <= "00000000000000000000000000000000";
when others => d <= (others => '-');
end case;
end process;
r : process (clk)
begin
if rising_edge(clk) then
if csn = '0' then raddr <= addr(9 downto 0); end if;
end if;
end process;
data <= d;
end rtl;
|
-------------------------------------------------------------------------------
--
-- ROM core VHDL template. See the macro description included
-- behind this frame.
--
-- Copyright (C) 2000 Rudolf Matousek <[email protected]>
--
-- Modified by Jiri Gaisler <[email protected]> for LEON boot prom.
--
-- This code may be used under the terms of Version 2 of the GPL,
-- read the file COPYING for details.
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity gen_bprom is
port(
clk : in std_logic;
csn : in std_logic;
addr : in std_logic_vector (29 downto 0);
data : out std_logic_vector (31 downto 0)
);
end;
architecture rtl of gen_bprom is
signal raddr : std_logic_vector(9 downto 0);
signal d : std_logic_vector(31 downto 0);
attribute syn_romstyle : string;
attribute syn_romstyle of d : signal is "select_rom";
begin
p : process(raddr)
begin
case raddr is
when "0000000000" => d <= "10000001100010000010000011100000";
when "0000000001" => d <= "10000001100100000010000000000010";
when "0000000010" => d <= "10000001110110000010000000000000";
when "0000000011" => d <= "00000011000000000000000001000000";
when "0000000100" => d <= "10000010000100000110000000001111";
when "0000000101" => d <= "00010001001000000000000000000000";
when "0000000110" => d <= "10001000001000100010000000010000";
when "0000000111" => d <= "11000010001000100010000000010100";
when "0000001000" => d <= "11010010000000100010000000100100";
when "0000001001" => d <= "10010010000010100110000000010000";
when "0000001010" => d <= "10010011001010100110000000001000";
when "0000001011" => d <= "10000001100010100110000011100000";
when "0000001100" => d <= "00010011000000000000000000101010";
when "0000001101" => d <= "10010010000100100110001000000000";
when "0000001110" => d <= "11010010001000100010000010100100";
when "0000001111" => d <= "11000000001000100010000001110100";
when "0000010000" => d <= "11000000001000100010000010000100";
when "0000010001" => d <= "10010010000100000010000000000011";
when "0000010010" => d <= "11010010001000100010000001111000";
when "0000010011" => d <= "11010010001000100010000010001000";
when "0000010100" => d <= "10010010000100000011111111111111";
when "0000010101" => d <= "11010010001000100010000001000100";
when "0000010110" => d <= "10010010000100000010000000000111";
when "0000010111" => d <= "11010010001000100010000001001000";
when "0000011000" => d <= "00010011000100000000000000000000";
when "0000011001" => d <= "00010101000000000000000000000111";
when "0000011010" => d <= "10010100000100101010001000100000";
when "0000011011" => d <= "11010100001000100010000000000100";
when "0000011100" => d <= "00010111000000000100100011010001";
when "0000011101" => d <= "10010110000100101110000101100111";
when "0000011110" => d <= "11010110001000100100000000000000";
when "0000011111" => d <= "11000000001000100110000000000100";
when "0000100000" => d <= "11011000100000100100000000000000";
when "0000100001" => d <= "10000000101000101100000000001100";
when "0000100010" => d <= "00000010100000000000000000001101";
when "0000100011" => d <= "11000000001000100100000000000000";
when "0000100100" => d <= "10010100001000101010000000010000";
when "0000100101" => d <= "11010100001000100010000000000100";
when "0000100110" => d <= "11010110001000100100000000000000";
when "0000100111" => d <= "11000000001000100110000000000100";
when "0000101000" => d <= "11011000100000100100000000000000";
when "0000101001" => d <= "10000000101000101100000000001100";
when "0000101010" => d <= "00000010100000000000000000000101";
when "0000101011" => d <= "00000001000000000000000000000000";
when "0000101100" => d <= "10010100001000101010000000010000";
when "0000101101" => d <= "00010000100000000000000000001010";
when "0000101110" => d <= "11010100001000100010000000000100";
when "0000101111" => d <= "11010110001000100100000000000000";
when "0000110000" => d <= "11000000001010100110000000000011";
when "0000110001" => d <= "11011000100000100100000000000000";
when "0000110010" => d <= "10000000101000101100000000001100";
when "0000110011" => d <= "00010010100000000000000000000100";
when "0000110100" => d <= "00000001000000000000000000000000";
when "0000110101" => d <= "10010100000100101010000001000000";
when "0000110110" => d <= "11010100001000100010000000000100";
when "0000110111" => d <= "00000101000001000000000000000000";
when "0000111000" => d <= "11010110001000010000000000000000";
when "0000111001" => d <= "11000000001000010011111111111100";
when "0000111010" => d <= "11011010100000010000000000000000";
when "0000111011" => d <= "10000000101000110100000000001011";
when "0000111100" => d <= "00110010101111111111111111111100";
when "0000111101" => d <= "10001000101000010000000000000010";
when "0000111110" => d <= "10001011001100010010000000011100";
when "0000111111" => d <= "10001010001000010110000000000100";
when "0001000000" => d <= "10010010000000001000000000001001";
when "0001000001" => d <= "10010010001000100110000000010000";
when "0001000010" => d <= "11010110001000100100000000000000";
when "0001000011" => d <= "10000101001100001010000000000001";
when "0001000100" => d <= "10010100001000101010001000000000";
when "0001000101" => d <= "11010100001000100010000000000100";
when "0001000110" => d <= "10010010001000100100000000000010";
when "0001000111" => d <= "11011010100000100100000000000000";
when "0001001000" => d <= "10000000101000110100000000001011";
when "0001001001" => d <= "00000010101111111111111111111010";
when "0001001010" => d <= "00000001000000000000000000000000";
when "0001001011" => d <= "10010100000000101010001000000000";
when "0001001100" => d <= "11010100001000100010000000000100";
when "0001001101" => d <= "00001001000100000000000000000000";
when "0001001110" => d <= "10010010000000100100000000000010";
when "0001001111" => d <= "10010010001010100100000000000100";
when "0001010000" => d <= "10010011001010100100000000000101";
when "0001010001" => d <= "10011100000100100100000000000100";
when "0001010010" => d <= "10010111001010010110000000000001";
when "0001010011" => d <= "01000000000000000000000000011011";
when "0001010100" => d <= "10010000000100000010001101101000";
when "0001010101" => d <= "10010010000100000010001101100000";
when "0001010110" => d <= "01000000000000000000000000011000";
when "0001010111" => d <= "10010000000000101100000000001001";
when "0001011000" => d <= "10010010000100000010001100110000";
when "0001011001" => d <= "10001011001100101010000000000110";
when "0001011010" => d <= "10001010001000010110000000100000";
when "0001011011" => d <= "10001010001010010110000000000001";
when "0001011100" => d <= "01000000000000000000000000010010";
when "0001011101" => d <= "10010000000000100100000000000101";
when "0001011110" => d <= "10010010000100000010001100100100";
when "0001011111" => d <= "10001011001100101010000000000010";
when "0001100000" => d <= "10001010000010010110000000001100";
when "0001100001" => d <= "01000000000000000000000000001101";
when "0001100010" => d <= "10010000000000100100000000000101";
when "0001100011" => d <= "01000000000000000000000000001011";
when "0001100100" => d <= "10010000000100000010001101110001";
when "0001100101" => d <= "10000000100010101010000001000000";
when "0001100110" => d <= "00000010100000000000000000000100";
when "0001100111" => d <= "00000001000000000000000000000000";
when "0001101000" => d <= "01000000000000000000000000000110";
when "0001101001" => d <= "10010000000100000010001101111100";
when "0001101010" => d <= "01000000000000000000000000000100";
when "0001101011" => d <= "10010000000100000010001110000010";
when "0001101100" => d <= "01000000000000000000000000100101";
when "0001101101" => d <= "00000001000000000000000000000000";
when "0001101110" => d <= "11000100000010100000000000000000";
when "0001101111" => d <= "10000000101000001010000000000000";
when "0001110000" => d <= "00000010100000000000000000001101";
when "0001110001" => d <= "00010011001000000000000000000000";
when "0001110010" => d <= "11000110000010100000000000000000";
when "0001110011" => d <= "10010000000000100010000000000001";
when "0001110100" => d <= "11000100000000100110000001110100";
when "0001110101" => d <= "10000000100010001010000000000100";
when "0001110110" => d <= "00000010101111111111111111111110";
when "0001110111" => d <= "10000100000010001110000011111111";
when "0001111000" => d <= "11000100001000100110000001110000";
when "0001111001" => d <= "11000100000010100000000000000000";
when "0001111010" => d <= "10000000101000001010000000000000";
when "0001111011" => d <= "00110010101111111111111111111000";
when "0001111100" => d <= "11000110000010100000000000000000";
when "0001111101" => d <= "10000001110000111110000000001000";
when "0001111110" => d <= "00000001000000000000000000000000";
when "0001111111" => d <= "10010110000100000000000000001000";
when "0010000000" => d <= "10010000000100000010000000000000";
when "0010000001" => d <= "10000000101000100000000000001011";
when "0010000010" => d <= "00011010100000000000000000001101";
when "0010000011" => d <= "10010100000100000010000000000000";
when "0010000100" => d <= "11000100000010100100000000001010";
when "0010000101" => d <= "10000000101000001010000001000000";
when "0010000110" => d <= "00101000100000000000000000000011";
when "0010000111" => d <= "10000100000000001011111111010000";
when "0010001000" => d <= "10000100000000001011111111001001";
when "0010001001" => d <= "10000111001010100010000000000100";
when "0010001010" => d <= "10000100000010001010000011111111";
when "0010001011" => d <= "10010100000000101010000000000001";
when "0010001100" => d <= "10000000101000101000000000001011";
when "0010001101" => d <= "00001010101111111111111111110111";
when "0010001110" => d <= "10010000000100001100000000000010";
when "0010001111" => d <= "10000001110000111110000000001000";
when "0010010000" => d <= "00000001000000000000000000000000";
when "0010010001" => d <= "10011101111000111011111010011000";
when "0010010010" => d <= "00101001001000000000000000000000";
when "0010010011" => d <= "10101100000001111011111011111100";
when "0010010100" => d <= "10101010000001111011111100000100";
when "0010010101" => d <= "10010100000001111011111011111000";
when "0010010110" => d <= "11010000000001010010000001110100";
when "0010010111" => d <= "10000000100010100010000000000001";
when "0010011000" => d <= "00000010101111111111111111111110";
when "0010011001" => d <= "00000001000000000000000000000000";
when "0010011010" => d <= "11010000000001010010000001110000";
when "0010011011" => d <= "10010010000010100010000011111111";
when "0010011100" => d <= "10000000101000100110000000001101";
when "0010011101" => d <= "00000010100000000000000000000101";
when "0010011110" => d <= "11010000001010101000000000000000";
when "0010011111" => d <= "10000000101000100110000000001010";
when "0010100000" => d <= "00010010101111111111111111110110";
when "0010100001" => d <= "10010100000000101010000000000001";
when "0010100010" => d <= "11010000000011111011111011111000";
when "0010100011" => d <= "10000000101000100010000001010011";
when "0010100100" => d <= "00010010101111111111111111110010";
when "0010100101" => d <= "10010100000001111011111011111000";
when "0010100110" => d <= "10010000000100000010000000001000";
when "0010100111" => d <= "01111111111111111111111111011000";
when "0010101000" => d <= "10010010000100000000000000010110";
when "0010101001" => d <= "10100110000100000000000000001000";
when "0010101010" => d <= "11010000000011111011111011111001";
when "0010101011" => d <= "10000000101000100010000000110011";
when "0010101100" => d <= "00010010100000000000000000010111";
when "0010101101" => d <= "10000000101000100010000000110111";
when "0010101110" => d <= "10010000000100000010000000000010";
when "0010101111" => d <= "01111111111111111111111111010000";
when "0010110000" => d <= "10010010000001111011111011111010";
when "0010110001" => d <= "10010001001010100010000000000001";
when "0010110010" => d <= "10010000000000100011111111110110";
when "0010110011" => d <= "10100101001100100010000000000001";
when "0010110100" => d <= "10100010000100000010000000000000";
when "0010110101" => d <= "10000000101001000100000000010010";
when "0010110110" => d <= "00010110101111111111111111100000";
when "0010110111" => d <= "10010100000001111011111011111000";
when "0010111000" => d <= "10100000000100000000000000010101";
when "0010111001" => d <= "10010010000100000000000000010000";
when "0010111010" => d <= "01111111111111111111111111000101";
when "0010111011" => d <= "10010000000100000010000000000010";
when "0010111100" => d <= "11010000001011001100000000010001";
when "0010111101" => d <= "10100010000001000110000000000001";
when "0010111110" => d <= "10000000101001000100000000010010";
when "0010111111" => d <= "00000110101111111111111111111010";
when "0011000000" => d <= "10100000000001000010000000000010";
when "0011000001" => d <= "00010000101111111111111111010101";
when "0011000010" => d <= "10010100000001111011111011111000";
when "0011000011" => d <= "00010010101111111111111111010011";
when "0011000100" => d <= "10010100000001111011111011111000";
when "0011000101" => d <= "10011111110001001100000000000000";
when "0011000110" => d <= "00000001000000000000000000000000";
when "0011000111" => d <= "00010000101111111111111111001111";
when "0011001000" => d <= "10010100000001111011111011111000";
when "0011001001" => d <= "00100000001110000010110100000000";
when "0011001010" => d <= "00110001001101100010110100000000";
when "0011001011" => d <= "00110011001100100010110100000000";
when "0011001100" => d <= "00101010001100010011001000111000";
when "0011001101" => d <= "01001011001000000000000000000000";
when "0011001110" => d <= "00101010001100100011010100110110";
when "0011001111" => d <= "01001011001000000000000000000000";
when "0011010000" => d <= "00101010001101010011000100110010";
when "0011010001" => d <= "01001011001000000000000000000000";
when "0011010010" => d <= "00101010001100010011000000110010";
when "0011010011" => d <= "00110100010010110010000000000000";
when "0011010100" => d <= "00101010001100100011000000110100";
when "0011010101" => d <= "00111000010010110010000000000000";
when "0011010110" => d <= "00101010001101000011000000111001";
when "0011010111" => d <= "00110110010010110010000000000000";
when "0011011000" => d <= "00110001000000000011001000000000";
when "0011011001" => d <= "00110011000000000011010000000000";
when "0011011010" => d <= "01001100010001010100111101001110";
when "0011011011" => d <= "00101101001100010011101000100000";
when "0011011100" => d <= "00000000011000100110100101110100";
when "0011011101" => d <= "00100000011011010110010101101101";
when "0011011110" => d <= "01101111011100100111100100000000";
when "0011011111" => d <= "00101100001000000111001001101101";
when "0011100000" => d <= "01110111000000000000101000001010";
when "0011100001" => d <= "00001101001111100010000000000000";
when "0011100010" => d <= "00000000000000000000000000000000";
when others => d <= (others => '-');
end case;
end process;
r : process (clk)
begin
if rising_edge(clk) then
if csn = '0' then raddr <= addr(9 downto 0); end if;
end if;
end process;
data <= d;
end rtl;
|
-------------------------------------------------------------------------------
--
-- ROM core VHDL template. See the macro description included
-- behind this frame.
--
-- Copyright (C) 2000 Rudolf Matousek <[email protected]>
--
-- Modified by Jiri Gaisler <[email protected]> for LEON boot prom.
--
-- This code may be used under the terms of Version 2 of the GPL,
-- read the file COPYING for details.
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity gen_bprom is
port(
clk : in std_logic;
csn : in std_logic;
addr : in std_logic_vector (29 downto 0);
data : out std_logic_vector (31 downto 0)
);
end;
architecture rtl of gen_bprom is
signal raddr : std_logic_vector(9 downto 0);
signal d : std_logic_vector(31 downto 0);
attribute syn_romstyle : string;
attribute syn_romstyle of d : signal is "select_rom";
begin
p : process(raddr)
begin
case raddr is
when "0000000000" => d <= "10000001100010000010000011100000";
when "0000000001" => d <= "10000001100100000010000000000010";
when "0000000010" => d <= "10000001110110000010000000000000";
when "0000000011" => d <= "00000011000000000000000001000000";
when "0000000100" => d <= "10000010000100000110000000001111";
when "0000000101" => d <= "00010001001000000000000000000000";
when "0000000110" => d <= "10001000001000100010000000010000";
when "0000000111" => d <= "11000010001000100010000000010100";
when "0000001000" => d <= "11010010000000100010000000100100";
when "0000001001" => d <= "10010010000010100110000000010000";
when "0000001010" => d <= "10010011001010100110000000001000";
when "0000001011" => d <= "10000001100010100110000011100000";
when "0000001100" => d <= "00010011000000000000000000101010";
when "0000001101" => d <= "10010010000100100110001000000000";
when "0000001110" => d <= "11010010001000100010000010100100";
when "0000001111" => d <= "11000000001000100010000001110100";
when "0000010000" => d <= "11000000001000100010000010000100";
when "0000010001" => d <= "10010010000100000010000000000011";
when "0000010010" => d <= "11010010001000100010000001111000";
when "0000010011" => d <= "11010010001000100010000010001000";
when "0000010100" => d <= "10010010000100000011111111111111";
when "0000010101" => d <= "11010010001000100010000001000100";
when "0000010110" => d <= "10010010000100000010000000000111";
when "0000010111" => d <= "11010010001000100010000001001000";
when "0000011000" => d <= "00010011000100000000000000000000";
when "0000011001" => d <= "00010101000000000000000000000111";
when "0000011010" => d <= "10010100000100101010001000100000";
when "0000011011" => d <= "11010100001000100010000000000100";
when "0000011100" => d <= "00010111000000000100100011010001";
when "0000011101" => d <= "10010110000100101110000101100111";
when "0000011110" => d <= "11010110001000100100000000000000";
when "0000011111" => d <= "11000000001000100110000000000100";
when "0000100000" => d <= "11011000100000100100000000000000";
when "0000100001" => d <= "10000000101000101100000000001100";
when "0000100010" => d <= "00000010100000000000000000001101";
when "0000100011" => d <= "11000000001000100100000000000000";
when "0000100100" => d <= "10010100001000101010000000010000";
when "0000100101" => d <= "11010100001000100010000000000100";
when "0000100110" => d <= "11010110001000100100000000000000";
when "0000100111" => d <= "11000000001000100110000000000100";
when "0000101000" => d <= "11011000100000100100000000000000";
when "0000101001" => d <= "10000000101000101100000000001100";
when "0000101010" => d <= "00000010100000000000000000000101";
when "0000101011" => d <= "00000001000000000000000000000000";
when "0000101100" => d <= "10010100001000101010000000010000";
when "0000101101" => d <= "00010000100000000000000000001010";
when "0000101110" => d <= "11010100001000100010000000000100";
when "0000101111" => d <= "11010110001000100100000000000000";
when "0000110000" => d <= "11000000001010100110000000000011";
when "0000110001" => d <= "11011000100000100100000000000000";
when "0000110010" => d <= "10000000101000101100000000001100";
when "0000110011" => d <= "00010010100000000000000000000100";
when "0000110100" => d <= "00000001000000000000000000000000";
when "0000110101" => d <= "10010100000100101010000001000000";
when "0000110110" => d <= "11010100001000100010000000000100";
when "0000110111" => d <= "00000101000001000000000000000000";
when "0000111000" => d <= "11010110001000010000000000000000";
when "0000111001" => d <= "11000000001000010011111111111100";
when "0000111010" => d <= "11011010100000010000000000000000";
when "0000111011" => d <= "10000000101000110100000000001011";
when "0000111100" => d <= "00110010101111111111111111111100";
when "0000111101" => d <= "10001000101000010000000000000010";
when "0000111110" => d <= "10001011001100010010000000011100";
when "0000111111" => d <= "10001010001000010110000000000100";
when "0001000000" => d <= "10010010000000001000000000001001";
when "0001000001" => d <= "10010010001000100110000000010000";
when "0001000010" => d <= "11010110001000100100000000000000";
when "0001000011" => d <= "10000101001100001010000000000001";
when "0001000100" => d <= "10010100001000101010001000000000";
when "0001000101" => d <= "11010100001000100010000000000100";
when "0001000110" => d <= "10010010001000100100000000000010";
when "0001000111" => d <= "11011010100000100100000000000000";
when "0001001000" => d <= "10000000101000110100000000001011";
when "0001001001" => d <= "00000010101111111111111111111010";
when "0001001010" => d <= "00000001000000000000000000000000";
when "0001001011" => d <= "10010100000000101010001000000000";
when "0001001100" => d <= "11010100001000100010000000000100";
when "0001001101" => d <= "00001001000100000000000000000000";
when "0001001110" => d <= "10010010000000100100000000000010";
when "0001001111" => d <= "10010010001010100100000000000100";
when "0001010000" => d <= "10010011001010100100000000000101";
when "0001010001" => d <= "10011100000100100100000000000100";
when "0001010010" => d <= "10010111001010010110000000000001";
when "0001010011" => d <= "01000000000000000000000000011011";
when "0001010100" => d <= "10010000000100000010001101101000";
when "0001010101" => d <= "10010010000100000010001101100000";
when "0001010110" => d <= "01000000000000000000000000011000";
when "0001010111" => d <= "10010000000000101100000000001001";
when "0001011000" => d <= "10010010000100000010001100110000";
when "0001011001" => d <= "10001011001100101010000000000110";
when "0001011010" => d <= "10001010001000010110000000100000";
when "0001011011" => d <= "10001010001010010110000000000001";
when "0001011100" => d <= "01000000000000000000000000010010";
when "0001011101" => d <= "10010000000000100100000000000101";
when "0001011110" => d <= "10010010000100000010001100100100";
when "0001011111" => d <= "10001011001100101010000000000010";
when "0001100000" => d <= "10001010000010010110000000001100";
when "0001100001" => d <= "01000000000000000000000000001101";
when "0001100010" => d <= "10010000000000100100000000000101";
when "0001100011" => d <= "01000000000000000000000000001011";
when "0001100100" => d <= "10010000000100000010001101110001";
when "0001100101" => d <= "10000000100010101010000001000000";
when "0001100110" => d <= "00000010100000000000000000000100";
when "0001100111" => d <= "00000001000000000000000000000000";
when "0001101000" => d <= "01000000000000000000000000000110";
when "0001101001" => d <= "10010000000100000010001101111100";
when "0001101010" => d <= "01000000000000000000000000000100";
when "0001101011" => d <= "10010000000100000010001110000010";
when "0001101100" => d <= "01000000000000000000000000100101";
when "0001101101" => d <= "00000001000000000000000000000000";
when "0001101110" => d <= "11000100000010100000000000000000";
when "0001101111" => d <= "10000000101000001010000000000000";
when "0001110000" => d <= "00000010100000000000000000001101";
when "0001110001" => d <= "00010011001000000000000000000000";
when "0001110010" => d <= "11000110000010100000000000000000";
when "0001110011" => d <= "10010000000000100010000000000001";
when "0001110100" => d <= "11000100000000100110000001110100";
when "0001110101" => d <= "10000000100010001010000000000100";
when "0001110110" => d <= "00000010101111111111111111111110";
when "0001110111" => d <= "10000100000010001110000011111111";
when "0001111000" => d <= "11000100001000100110000001110000";
when "0001111001" => d <= "11000100000010100000000000000000";
when "0001111010" => d <= "10000000101000001010000000000000";
when "0001111011" => d <= "00110010101111111111111111111000";
when "0001111100" => d <= "11000110000010100000000000000000";
when "0001111101" => d <= "10000001110000111110000000001000";
when "0001111110" => d <= "00000001000000000000000000000000";
when "0001111111" => d <= "10010110000100000000000000001000";
when "0010000000" => d <= "10010000000100000010000000000000";
when "0010000001" => d <= "10000000101000100000000000001011";
when "0010000010" => d <= "00011010100000000000000000001101";
when "0010000011" => d <= "10010100000100000010000000000000";
when "0010000100" => d <= "11000100000010100100000000001010";
when "0010000101" => d <= "10000000101000001010000001000000";
when "0010000110" => d <= "00101000100000000000000000000011";
when "0010000111" => d <= "10000100000000001011111111010000";
when "0010001000" => d <= "10000100000000001011111111001001";
when "0010001001" => d <= "10000111001010100010000000000100";
when "0010001010" => d <= "10000100000010001010000011111111";
when "0010001011" => d <= "10010100000000101010000000000001";
when "0010001100" => d <= "10000000101000101000000000001011";
when "0010001101" => d <= "00001010101111111111111111110111";
when "0010001110" => d <= "10010000000100001100000000000010";
when "0010001111" => d <= "10000001110000111110000000001000";
when "0010010000" => d <= "00000001000000000000000000000000";
when "0010010001" => d <= "10011101111000111011111010011000";
when "0010010010" => d <= "00101001001000000000000000000000";
when "0010010011" => d <= "10101100000001111011111011111100";
when "0010010100" => d <= "10101010000001111011111100000100";
when "0010010101" => d <= "10010100000001111011111011111000";
when "0010010110" => d <= "11010000000001010010000001110100";
when "0010010111" => d <= "10000000100010100010000000000001";
when "0010011000" => d <= "00000010101111111111111111111110";
when "0010011001" => d <= "00000001000000000000000000000000";
when "0010011010" => d <= "11010000000001010010000001110000";
when "0010011011" => d <= "10010010000010100010000011111111";
when "0010011100" => d <= "10000000101000100110000000001101";
when "0010011101" => d <= "00000010100000000000000000000101";
when "0010011110" => d <= "11010000001010101000000000000000";
when "0010011111" => d <= "10000000101000100110000000001010";
when "0010100000" => d <= "00010010101111111111111111110110";
when "0010100001" => d <= "10010100000000101010000000000001";
when "0010100010" => d <= "11010000000011111011111011111000";
when "0010100011" => d <= "10000000101000100010000001010011";
when "0010100100" => d <= "00010010101111111111111111110010";
when "0010100101" => d <= "10010100000001111011111011111000";
when "0010100110" => d <= "10010000000100000010000000001000";
when "0010100111" => d <= "01111111111111111111111111011000";
when "0010101000" => d <= "10010010000100000000000000010110";
when "0010101001" => d <= "10100110000100000000000000001000";
when "0010101010" => d <= "11010000000011111011111011111001";
when "0010101011" => d <= "10000000101000100010000000110011";
when "0010101100" => d <= "00010010100000000000000000010111";
when "0010101101" => d <= "10000000101000100010000000110111";
when "0010101110" => d <= "10010000000100000010000000000010";
when "0010101111" => d <= "01111111111111111111111111010000";
when "0010110000" => d <= "10010010000001111011111011111010";
when "0010110001" => d <= "10010001001010100010000000000001";
when "0010110010" => d <= "10010000000000100011111111110110";
when "0010110011" => d <= "10100101001100100010000000000001";
when "0010110100" => d <= "10100010000100000010000000000000";
when "0010110101" => d <= "10000000101001000100000000010010";
when "0010110110" => d <= "00010110101111111111111111100000";
when "0010110111" => d <= "10010100000001111011111011111000";
when "0010111000" => d <= "10100000000100000000000000010101";
when "0010111001" => d <= "10010010000100000000000000010000";
when "0010111010" => d <= "01111111111111111111111111000101";
when "0010111011" => d <= "10010000000100000010000000000010";
when "0010111100" => d <= "11010000001011001100000000010001";
when "0010111101" => d <= "10100010000001000110000000000001";
when "0010111110" => d <= "10000000101001000100000000010010";
when "0010111111" => d <= "00000110101111111111111111111010";
when "0011000000" => d <= "10100000000001000010000000000010";
when "0011000001" => d <= "00010000101111111111111111010101";
when "0011000010" => d <= "10010100000001111011111011111000";
when "0011000011" => d <= "00010010101111111111111111010011";
when "0011000100" => d <= "10010100000001111011111011111000";
when "0011000101" => d <= "10011111110001001100000000000000";
when "0011000110" => d <= "00000001000000000000000000000000";
when "0011000111" => d <= "00010000101111111111111111001111";
when "0011001000" => d <= "10010100000001111011111011111000";
when "0011001001" => d <= "00100000001110000010110100000000";
when "0011001010" => d <= "00110001001101100010110100000000";
when "0011001011" => d <= "00110011001100100010110100000000";
when "0011001100" => d <= "00101010001100010011001000111000";
when "0011001101" => d <= "01001011001000000000000000000000";
when "0011001110" => d <= "00101010001100100011010100110110";
when "0011001111" => d <= "01001011001000000000000000000000";
when "0011010000" => d <= "00101010001101010011000100110010";
when "0011010001" => d <= "01001011001000000000000000000000";
when "0011010010" => d <= "00101010001100010011000000110010";
when "0011010011" => d <= "00110100010010110010000000000000";
when "0011010100" => d <= "00101010001100100011000000110100";
when "0011010101" => d <= "00111000010010110010000000000000";
when "0011010110" => d <= "00101010001101000011000000111001";
when "0011010111" => d <= "00110110010010110010000000000000";
when "0011011000" => d <= "00110001000000000011001000000000";
when "0011011001" => d <= "00110011000000000011010000000000";
when "0011011010" => d <= "01001100010001010100111101001110";
when "0011011011" => d <= "00101101001100010011101000100000";
when "0011011100" => d <= "00000000011000100110100101110100";
when "0011011101" => d <= "00100000011011010110010101101101";
when "0011011110" => d <= "01101111011100100111100100000000";
when "0011011111" => d <= "00101100001000000111001001101101";
when "0011100000" => d <= "01110111000000000000101000001010";
when "0011100001" => d <= "00001101001111100010000000000000";
when "0011100010" => d <= "00000000000000000000000000000000";
when others => d <= (others => '-');
end case;
end process;
r : process (clk)
begin
if rising_edge(clk) then
if csn = '0' then raddr <= addr(9 downto 0); end if;
end if;
end process;
data <= d;
end rtl;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.net.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000; -- frequency of main clock (used for PLLs)
dbits : integer := CFG_DDR2SP_DATAWIDTH
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
clk125 : in std_ulogic;
errorn : out std_ulogic;
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console/debug UART
--rxd1 : in std_logic;
--txd1 : out std_logic;
gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
-- flash/ssram bus
address : out std_logic_vector(24 downto 0);
data : inout std_logic_vector(31 downto 0);
rstoutn : out std_ulogic;
sram_advn : out std_ulogic;
sram_csn : out std_logic;
sram_wen : out std_logic;
sram_ben : out std_logic_vector (0 to 3);
sram_oen : out std_ulogic;
sram_clk : out std_ulogic;
sram_psn : out std_ulogic;
sram_wait : in std_logic_vector(1 downto 0);
flash_clk : out std_ulogic;
flash_advn : out std_logic;
flash_cen : out std_logic;
flash_oen : out std_logic;
flash_resetn: out std_logic;
flash_wen : out std_logic;
max_csn : out std_logic;
-- sram_adsp_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (8 downto 0); -- ddr dm
ddr_dqsp : inout std_logic_vector (8 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (8 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (15 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (71 downto 0); -- ddr data
-- ddra_cke : out std_logic;
ddra_csb : out std_logic;
-- ddra_web : out std_ulogic; -- ddr write enable
-- ddra_rasb : out std_ulogic; -- ddr ras
-- ddra_casb : out std_ulogic; -- ddr cas
-- ddra_ad : out std_logic_vector (14 downto 0); -- ddr address
-- ddra_ba : out std_logic_vector (2 downto 0); -- ddr bank address
--
-- ddrb_cke : out std_logic;
ddrb_csb : out std_logic;
-- ddrb_web : out std_ulogic; -- ddr write enable
-- ddrb_rasb : out std_ulogic; -- ddr ras
-- ddrb_casb : out std_ulogic; -- ddr cas
-- ddrb_ad : out std_logic_vector (14 downto 0); -- ddr address
-- ddrb_ba : out std_logic_vector (2 downto 0); -- ddr bank address
--
-- ddrab_clk : inout std_logic_vector(1 downto 0);
-- ddrab_clkb : inout std_logic_vector(1 downto 0);
-- ddrab_odt : out std_logic_vector(1 downto 0);
-- ddrab_dqsp : inout std_logic_vector(1 downto 0); -- ddr dqs
-- ddrab_dqsn : inout std_logic_vector(1 downto 0); -- ddr dqs
-- ddrab_dm : out std_logic_vector(1 downto 0); -- ddr dm
-- ddrab_dq : inout std_logic_vector (15 downto 0);-- ddr data
phy_gtx_clk : out std_logic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal ddr_clk_fb : std_ulogic;
-- -- DDR2 Device A&B
-- signal ddrab_clkv : std_logic_vector(2 downto 0);
-- signal ddrab_clkbv : std_logic_vector(2 downto 0);
-- signal ddra_ckev : std_logic_vector(1 downto 0);
-- signal ddra_csbv : std_logic_vector(1 downto 0);
-- signal ddrb_ckev : std_logic_vector(1 downto 0);
-- signal ddrb_csbv : std_logic_vector(1 downto 0);
-- signal lockab : std_logic;
-- signal clkmlab : std_logic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sram_clkl : std_ulogic;
signal cgi,cgi2 : clkgen_in_type;
signal cgo,cgo2 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal ethclk, egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal lclk, lclkout, lclk125, clkm125 : std_ulogic;
signal dsubre : std_ulogic;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
cgi2.pllctrl <= "00"; cgi2.pllrst <= not resetn; cgi2.pllref <= '0';
clklock <= cgo.clklock and lock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clk125_pad : clkpad generic map (tech => padtech) port map (clk125, lclk125);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => 1,
freq => freq)
port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => sram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
clkm125 <= lclk125;
phy_gtx_clk <= lclk125;
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, sram_clkl);
flashclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (flash_clk, sram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
rstoutn <= resetn;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- dcomgen : if CFG_AHB_UART = 1 generate
-- dcom0 : ahbuart -- Debug UART
-- generic map (hindex => NCPU, pindex => 4, paddr => 7)
-- port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
-- end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#a00#, rammask =>16#F00#, srbanks => 1,
sden => 0, ram16 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
srams_pad : outpad generic map ( tech => padtech)
port map (sram_csn, vcc(0));
flash_cen_pad : outpad generic map (tech => padtech)
port map (flash_cen, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(25 downto 1));
srams_pad : outpad generic map ( tech => padtech)
port map (sram_csn, memo.ramsn(0));
sram_oen_pad : outpad generic map (tech => padtech)
port map (sram_oen, memo.oen);
sram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (sram_ben, memo.wrn);
sram_wri_pad : outpad generic map (tech => padtech)
port map (sram_wen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, memi.data(31 downto 0));
sram_advn_pad : outpad generic map (tech => padtech)
port map (sram_advn, gnd(0));
sram_psn_pad : outpad generic map (tech => padtech)
port map (sram_psn, vcc(0));
flash_advn_pad : outpad generic map (tech => padtech)
port map (flash_advn, gnd(0));
flash_cen_pad : outpad generic map (tech => padtech)
port map (flash_cen, memo.romsn(0));
flash_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
flash_wri_pad : outpad generic map (tech => padtech)
port map (flash_wen, memo.writen);
flash_reset_pad : outpad generic map (tech => padtech)
port map (flash_resetn, resetn);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
end generate;
max_csn_pad : outpad generic map (tech => padtech)
port map (max_csn, vcc(0));
ddrsp0 : if (CFG_DDR2SP /= 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech,
memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => 125000/1000, rskew => 0, TRFC => CFG_DDR2SP_TRFC,
clkmul => (CFG_DDR2SP_FREQ*5)/125, clkdiv => 5, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => dbits,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
odten => 3, octen => 1, readdly => 1)
port map ( resetn, rstn, clkm125, clkm, clkm125, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, ddr_clk_fb, ddr_clk_fb, ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm(dbits/8-1 downto 0), ddr_dqsp(dbits/8-1 downto 0), ddr_dqsn(dbits/8-1 downto 0),
ddr_ad(13 downto 0), ddr_ba(1 downto 0), ddr_dq(dbits-1 downto 0), ddr_odt);
ddr_clk <= ddr_clkv(2 downto 0); ddr_clkb <= ddr_clkbv(2 downto 0);
ddr_cke <= ddr_ckev(1 downto 0); ddr_csb <= ddr_csbv(1 downto 0);
ddr_ad(15 downto 14) <= (others => '0');
ddr_ba(2) <= '0';
end generate;
noddr : if (CFG_DDR2SP = 0) generate lock <= '1'; end generate;
-- Disable DDR2 Device A and B
ddra_csb <= '1';
ddrb_csb <= '1';
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 18,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
ethi.gtx_clk <= egtx_clk;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
-- loopback
u1i.rxd <= u1o.txd;
--upads : if CFG_AHB_UART = 0 generate
-- u1i.rxd <= rxd1; txd1 <= u1o.txd;
--end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
gpioi.din(i) <= gpio(i);
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP3SL150 PSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1
);
-- pragma translate_on
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lzw_tb is
end lzw_tb;
architecture Behavioral of lzw_tb is
--the rain in Spain falls mainly on the plain
constant str_len : integer := 43;
signal test_vector : std_logic_vector(str_len*8-1 downto 0) := x"746865207261696e20696e20537061696e2066616c6c73206d61696e6c79206f6e2074686520706c61696e";
constant result_len : integer := 33;
signal result_vector : std_logic_vector(result_len*12-1 downto 0) := x"07406806502007206106906E02010602005307010510706606106C06C07302006D10D06C07902006F10710010207006C10D";
signal clk : std_logic;
signal rst : std_logic;
signal char_in : std_logic_vector(7 downto 0) := x"00";
signal input_valid : std_logic := '0';
signal input_rd : std_logic;
signal prefix_out : std_logic_vector(11 downto 0);
signal expected : std_logic_vector(11 downto 0);
signal output_valid : std_logic;
signal done : std_logic;
signal file_size : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(str_len,16));
begin
UUT : entity work.lzw
port map(
clk => clk,
rst => rst,
char_in => char_in,
input_valid => input_valid,
input_rd => input_rd,
file_size => file_size,
prefix_out => prefix_out,
done => done,
output_valid => output_valid);
clk_proc: process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;
input_proc: process
variable i : integer := str_len-1;
begin
rst <= '1';
wait for 30 ns;
rst <= '0';
input_valid <= '1';
char_in <= test_vector(str_len*8-1 downto (str_len-1)*8);
while i /= 0 loop
if input_rd = '1' then
char_in <= test_vector(i*8-1 downto (i-1)*8);
i := i-1;
end if;
wait for 10 ns;
end loop;
char_in <= test_vector(7 downto 0);
wait until input_rd = '1';
input_valid <= '0';
wait for 10 ns;
char_in <= x"00";
wait;
end process;
output_proc : process
variable i : integer := result_len;
begin
wait for 10 ns;
expected <= result_vector(i*12-1 downto (i-1)*12);
if output_valid = '1' then
assert result_vector(i*12-1 downto (i-1)*12) = prefix_out report "Output prefix does not match." severity warning;
i := i-1;
end if;
if i = 1 then
report "Testbench completed." severity note;
wait;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity ram is
generic
(
width : integer;
ram_select : integer
);
port
(
input1 : in std_logic_vector((width - 1) downto 0);
input2 : in std_logic_vector((ram_select - 1) downto 0);
wr, rd, clock : in std_logic;
output : out std_logic_vector((width - 1) downto 0)
);
end ram;
architecture behavior of ram is
function bits_to_int (input : std_logic_vector)return integer is
variable ret_val : integer := 0;
begin
for i in input'range loop
if input(i) = '1' then
ret_val := 2 ** i + ret_val;
end if;
end loop; return ret_val;
end bits_to_int;
type mem_type is array(0 to (2 ** ram_select - 1)) of
std_logic_vector((width - 1) downto 0);
signal mem_storage : mem_type;
begin
P0 : process (rd, wr, input1, input2, clock)
begin
if (clock = '1' and clock'EVENT) then
if (rd = '1') then
output <= mem_storage(bits_to_int(input2));
end if;
if (wr = '1') then
mem_storage(bits_to_int(input2)) <= input1;
end if;
end if;
end process P0;
end behavior; |
architecture RTL of FIFO is
function func1 (
a : integer;
b: integer
) return integer;
function func1 (
a : integer;
b: integer
) return integer;
function func1 (a : integer;b: integer) return integer;
begin
end architecture RTL;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdog : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_logic;
constant lresp : boolean := false;
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal pllref : std_logic;
signal spw_rxd : std_logic_vector(0 to 1) := "00";
signal spw_rxs : std_logic_vector(0 to 1) := "00";
signal spw_txd : std_logic_vector(0 to 1);
signal spw_txs : std_logic_vector(0 to 1);
begin
-- clock and reset
spw_rxd(0) <= spw_txd(0);
spw_rxs(0) <= spw_txs(0);
spw_rxd(1) <= spw_txd(1);
spw_rxs(1) <= spw_txs(1);
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
pllref <= sdclk;
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, pllref, error, address(27 downto 0), data,
sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
spw_rxd, spw_rxs, spw_txd, spw_txs);
-- sdram
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity shift_register_tb is
end entity;
architecture shift_register_tb_arq of shift_register_tb is
signal d_in : std_logic_vector(31 downto 0) := (others => '0');
signal rst_in: std_logic:='0';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal q_out: std_logic_vector(31 downto 0) := (others => '0');
component shift_register is
generic(REGISTRY_BITS : integer := 32;
STEPS : integer := 4);
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
D: in std_logic_vector(REGISTRY_BITS - 1 downto 0);
Q: out std_logic_vector(REGISTRY_BITS - 1 downto 0)
);
end component;
for shift_register_0: shift_register use entity work.shift_register;
begin
shift_register_0: shift_register
generic map(REGISTRY_BITS => 32, STEPS => 4)
port map(
enable => enable_in,
reset => rst_in,
clk => clk_in,
D => d_in,
Q => q_out
);
process
type pattern_type is record
en : std_logic;
r: std_logic;
clk: std_logic;
d: std_logic_vector(31 downto 0);
q: std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
('1', '0','1', "00000000000000000000000000000001", "00000000000000000000000000000000"),
('1', '0','1', "00000000000000000000000000000010", "00000000000000000000000000000000"),
('1', '0','1', "00000000000000000000000000000011", "00000000000000000000000000000000"),
('1', '0','1', "00000000000000000000000000000100", "00000000000000000000000000000001"),
('1', '0','1', "00000000000000000000000000000000", "00000000000000000000000000000010"),
('1', '0','1', "00000000000000000000000000000000", "00000000000000000000000000000011"),
('1', '0','1', "00000000000000000000000000000000", "00000000000000000000000000000100"),
('1', '0','1', "00000000000000000000000000000000", "00000000000000000000000000000000")
);
begin
for i in patterns'range loop
d_in <= patterns(i).d;
enable_in <= patterns(i).en;
rst_in <= patterns(i).r;
clk_in <= patterns(i).clk;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert q_out = patterns(i).q report "BAD Q, EXPECTED " & integer'image(to_integer(unsigned(patterns(i).q))) & " GOT: " & integer'image(to_integer(unsigned(q_out)));
clk_in <= '0'; --reset clock
wait for 1 ns;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix4;
constant CFG_MEMTECH : integer := stratix4;
constant CFG_PADTECH : integer := stratix4;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix4;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := 0;
constant CFG_GRETH21G : integer := 0;
constant CFG_ETH2_FIFO : integer := 8;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (2);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 1;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 1;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 1;
constant CFG_SPICTRL_FT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-a.vhd,v 1.1 2004/04/06 10:49:52 wig Exp $
-- $Date: 2004/04/06 10:49:52 $
-- $Log: inst_b_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:49:52 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_b_e
--
architecture rtl of inst_b_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNOYUTXDOZ is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000001000000";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNOYUTXDOZ is
Begin
-- Constant
output <= "0000000001000000";
end architecture; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.05.2016 21:14:53
-- Design Name:
-- Module Name: tb_main_design - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_main_design_tcp is
end tb_main_design_tcp;
architecture Behavioral of tb_main_design_tcp is
signal clk125Mhz : STD_LOGIC := '0';
signal clk125Mhz90 : STD_LOGIC := '0';
signal phy_ready : STD_LOGIC := '1';
signal status : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal input_empty : STD_LOGIC := '0';
signal input_read : STD_LOGIC := '0';
signal input_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal input_data_present : STD_LOGIC := '0';
signal input_data_error : STD_LOGIC := '0';
component main_design is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_netmask : std_logic_vector(31 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
Port (
clk125Mhz : in STD_LOGIC;
clk125Mhz90 : in STD_LOGIC;
input_empty : in STD_LOGIC;
input_read : out STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
phy_ready : in STD_LOGIC;
status : out STD_LOGIC_VECTOR (3 downto 0);
-- data received over UDP
udp_rx_valid : out std_logic := '0';
udp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
udp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
udp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
udp_rx_dst_broadcast : out std_logic := '0';
udp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over UDP
udp_tx_busy : out std_logic := '1';
udp_tx_valid : in std_logic := '0';
udp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
udp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
udp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
udp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
udp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
-- data received over TCP/IP
tcp_rx_data_valid : out std_logic := '0';
tcp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : out std_logic := '0';
tcp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_checksum : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : out std_logic := '0';
tcp_rx_flag_ack : out std_logic := '0';
tcp_rx_flag_psh : out std_logic := '0';
tcp_rx_flag_rst : out std_logic := '0';
tcp_rx_flag_syn : out std_logic := '0';
tcp_rx_flag_fin : out std_logic := '0';
tcp_rx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over TCP/IP
tcp_tx_busy : out std_logic := '0';
tcp_tx_data_valid : in std_logic := '0';
tcp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : in std_logic := '0';
tcp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
tcp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_checksum : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : in std_logic := '0';
tcp_tx_flag_ack : in std_logic := '0';
tcp_tx_flag_psh : in std_logic := '0';
tcp_tx_flag_rst : in std_logic := '0';
tcp_tx_flag_syn : in std_logic := '0';
tcp_tx_flag_fin : in std_logic := '0';
tcp_tx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
eth_txck : out std_logic := '0';
eth_txctl : out std_logic := '0';
eth_txd : out std_logic_vector(3 downto 0) := (others => '0'));
end component;
signal udp_rx_valid : std_logic := '0';
signal udp_rx_data : std_logic_vector(7 downto 0) := (others => '0');
signal udp_rx_src_ip : std_logic_vector(31 downto 0) := (others => '0');
signal udp_rx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal udp_rx_dst_broadcast : std_logic := '0';
signal udp_rx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal udp_rx_valid_last : std_logic := '0';
signal udp_tx_busy : std_logic := '0';
signal udp_tx_valid : std_logic := '0';
signal udp_tx_data : std_logic_vector(7 downto 0) := (others => '0');
signal udp_tx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal udp_tx_dst_mac : std_logic_vector(47 downto 0) := (others => '0');
signal udp_tx_dst_ip : std_logic_vector(31 downto 0) := (others => '0');
signal udp_tx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
-- data received over TCP/IP
signal tcp_rx_data_valid : std_logic := '0';
signal tcp_rx_data : std_logic_vector(7 downto 0) := (others => '0');
signal tcp_rx_hdr_valid : std_logic := '0';
signal tcp_rx_src_ip : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_rx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_rx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_rx_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_rx_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_rx_window : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_rx_checksum : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_rx_flag_urg : std_logic := '0';
signal tcp_rx_flag_ack : std_logic := '0';
signal tcp_rx_flag_psh : std_logic := '0';
signal tcp_rx_flag_rst : std_logic := '0';
signal tcp_rx_flag_syn : std_logic := '0';
signal tcp_rx_flag_fin : std_logic := '0';
signal tcp_rx_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over TCP/IP
signal tcp_tx_busy : std_logic := '0';
signal tcp_tx_data_valid : std_logic := '0';
signal tcp_tx_data : std_logic_vector(7 downto 0) := (others => '0');
signal tcp_tx_hdr_valid : std_logic := '0';
signal tcp_tx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_dst_ip : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_tx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_tx_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_tx_window : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_checksum : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_flag_urg : std_logic := '0';
signal tcp_tx_flag_ack : std_logic := '0';
signal tcp_tx_flag_psh : std_logic := '0';
signal tcp_tx_flag_rst : std_logic := '0';
signal tcp_tx_flag_syn : std_logic := '0';
signal tcp_tx_flag_fin : std_logic := '0';
signal tcp_tx_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
signal eth_txck : std_logic := '0';
signal eth_txctl : std_logic := '0';
signal eth_txd : std_logic_vector(3 downto 0) := (others => '0');
signal count : integer := 999;
signal count2 : integer := 180;
signal arp_src_hw : std_logic_vector(47 downto 0) := x"A0B3CC4CF9EF";
signal arp_src_ip : std_logic_vector(31 downto 0) := x"0A000001";
signal arp_tgt_hw : std_logic_vector(47 downto 0) := x"000000000000";
signal arp_tgt_ip : std_logic_vector(31 downto 0) := x"0A00000A";
constant our_mac : std_logic_vector(47 downto 0) := x"AB_89_67_45_23_02"; -- NOTE this is 02:23:45:67:89:AB
constant our_ip : std_logic_vector(31 downto 0) := x"0A_00_00_0A";
constant our_netmask : std_logic_vector(31 downto 0) := x"00_FF_FF_FF";
component tcp_engine is
port ( clk : in STD_LOGIC;
-- data received over TCP/IP
tcp_rx_data_valid : in std_logic := '0';
tcp_rx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : in std_logic := '0';
tcp_rx_src_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_broadcast : in std_logic := '0';
tcp_rx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : in std_logic := '0';
tcp_rx_flag_ack : in std_logic := '0';
tcp_rx_flag_psh : in std_logic := '0';
tcp_rx_flag_rst : in std_logic := '0';
tcp_rx_flag_syn : in std_logic := '0';
tcp_rx_flag_fin : in std_logic := '0';
tcp_rx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over TP
tcp_tx_busy : in std_logic := '0';
tcp_tx_data_valid : out std_logic := '0';
tcp_tx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : out std_logic := '0';
tcp_tx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : out std_logic := '0';
tcp_tx_flag_ack : out std_logic := '0';
tcp_tx_flag_psh : out std_logic := '0';
tcp_tx_flag_rst : out std_logic := '0';
tcp_tx_flag_syn : out std_logic := '0';
tcp_tx_flag_fin : out std_logic := '0';
tcp_tx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0'));
end component;
begin
process
begin
clk125Mhz <= '1';
wait for 2 ns;
clk125Mhz90 <= '1';
wait for 2 ns;
clk125Mhz <= '0';
wait for 2 ns;
clk125Mhz90 <= '0';
wait for 2 ns;
end process;
i_main_design: main_design generic map (
our_mac => our_mac,
our_netmask => our_netmask,
our_ip => our_ip
) port map (
clk125Mhz => clk125Mhz,
clk125Mhz90 => clk125Mhz90,
input_empty => input_empty,
input_read => input_read,
input_data => input_data,
input_data_present => input_data_present,
input_data_error => input_data_error,
phy_ready => phy_ready,
status => status,
-- data received over UDP
udp_rx_valid => udp_rx_valid,
udp_rx_data => udp_rx_data,
udp_rx_src_ip => udp_rx_src_ip,
udp_rx_src_port => udp_rx_src_port,
udp_rx_dst_broadcast => udp_rx_dst_broadcast,
udp_rx_dst_port => udp_rx_dst_port,
udp_tx_busy => udp_tx_busy,
udp_tx_valid => udp_tx_valid,
udp_tx_data => udp_tx_data,
udp_tx_src_port => udp_tx_src_port,
udp_tx_dst_mac => udp_tx_dst_mac,
udp_tx_dst_ip => udp_tx_dst_ip,
udp_tx_dst_port => udp_tx_dst_port,
-- data received over TCP/IP
tcp_tx_busy => tcp_tx_busy,
tcp_rx_data_valid => tcp_rx_data_valid,
tcp_rx_data => tcp_rx_data,
tcp_rx_hdr_valid => tcp_rx_hdr_valid,
tcp_rx_src_ip => tcp_rx_src_ip,
tcp_rx_src_port => tcp_rx_src_port,
tcp_rx_dst_port => tcp_rx_dst_port,
tcp_rx_seq_num => tcp_rx_seq_num,
tcp_rx_ack_num => tcp_rx_ack_num,
tcp_rx_window => tcp_rx_window,
tcp_rx_checksum => tcp_rx_checksum,
tcp_rx_flag_urg => tcp_rx_flag_urg,
tcp_rx_flag_ack => tcp_rx_flag_ack,
tcp_rx_flag_psh => tcp_rx_flag_psh,
tcp_rx_flag_rst => tcp_rx_flag_rst,
tcp_rx_flag_syn => tcp_rx_flag_syn,
tcp_rx_flag_fin => tcp_rx_flag_fin,
tcp_rx_urgent_ptr => tcp_rx_urgent_ptr,
-- data to be sent over TCP/IP
tcp_tx_data_valid => tcp_tx_data_valid,
tcp_tx_data => tcp_tx_data,
tcp_tx_hdr_valid => tcp_tx_hdr_valid,
tcp_tx_src_port => tcp_tx_src_port,
tcp_tx_dst_ip => tcp_tx_dst_ip,
tcp_tx_dst_port => tcp_tx_dst_port,
tcp_tx_seq_num => tcp_tx_seq_num,
tcp_tx_ack_num => tcp_tx_ack_num,
tcp_tx_window => tcp_tx_window,
tcp_tx_checksum => tcp_tx_checksum,
tcp_tx_flag_urg => tcp_tx_flag_urg,
tcp_tx_flag_ack => tcp_tx_flag_ack,
tcp_tx_flag_psh => tcp_tx_flag_psh,
tcp_tx_flag_rst => tcp_tx_flag_rst,
tcp_tx_flag_syn => tcp_tx_flag_syn,
tcp_tx_flag_fin => tcp_tx_flag_fin,
tcp_tx_urgent_ptr => tcp_tx_urgent_ptr,
eth_txck => eth_txck,
eth_txctl => eth_txctl,
eth_txd => eth_txd);
i_tcp_engine: tcp_engine port map (
clk => clk125MHz,
-- data received over TCP/IP
tcp_rx_data_valid => tcp_rx_data_valid,
tcp_rx_data => tcp_rx_data,
tcp_rx_hdr_valid => tcp_rx_hdr_valid,
tcp_rx_src_ip => tcp_rx_src_ip,
tcp_rx_src_port => tcp_rx_src_port,
tcp_rx_dst_port => tcp_rx_dst_port,
tcp_rx_seq_num => tcp_rx_seq_num,
tcp_rx_ack_num => tcp_rx_ack_num,
tcp_rx_window => tcp_rx_window,
tcp_rx_flag_urg => tcp_rx_flag_urg,
tcp_rx_flag_ack => tcp_rx_flag_ack,
tcp_rx_flag_psh => tcp_rx_flag_psh,
tcp_rx_flag_rst => tcp_rx_flag_rst,
tcp_rx_flag_syn => tcp_rx_flag_syn,
tcp_rx_flag_fin => tcp_rx_flag_fin,
tcp_rx_urgent_ptr => tcp_rx_urgent_ptr,
-- data to be sent over TCP/IP
tcp_tx_busy => tcp_tx_busy,
tcp_tx_data_valid => tcp_tx_data_valid,
tcp_tx_data => tcp_tx_data,
tcp_tx_hdr_valid => tcp_tx_hdr_valid,
tcp_tx_src_port => tcp_tx_src_port,
tcp_tx_dst_ip => tcp_tx_dst_ip,
tcp_tx_dst_port => tcp_tx_dst_port,
tcp_tx_seq_num => tcp_tx_seq_num,
tcp_tx_ack_num => tcp_tx_ack_num,
tcp_tx_window => tcp_tx_window,
tcp_tx_flag_urg => tcp_tx_flag_urg,
tcp_tx_flag_ack => tcp_tx_flag_ack,
tcp_tx_flag_psh => tcp_tx_flag_psh,
tcp_tx_flag_rst => tcp_tx_flag_rst,
tcp_tx_flag_syn => tcp_tx_flag_syn,
tcp_tx_flag_fin => tcp_tx_flag_fin,
tcp_tx_urgent_ptr => tcp_tx_urgent_ptr);
process(clk125MHz)
begin
if rising_edge(clk125MHz) then
if count < 86 then
input_empty <= '0';
else
input_empty <= '1';
end if;
if count2 = 2000 then
count <= 0;
count2 <= 0;
else
count2 <= count2+1;
end if;
if input_read = '1' then
if count = 87 then
count <= 0;
else
count <= count + 1;
end if;
case count is
when 0 => input_data <= x"55"; input_data_present <= '1';
when 1 => input_data <= x"55";
when 2 => input_data <= x"55";
when 3 => input_data <= x"55";
when 4 => input_data <= x"55";
when 5 => input_data <= x"55";
when 6 => input_data <= x"55";
when 7 => input_data <= x"D5";
-----------------------------
-- Ethernet Header
-----------------------------
-- Destination MAC address
when 8 => input_data <= x"02";
when 9 => input_data <= x"23";
when 10 => input_data <= x"45";
when 11 => input_data <= x"67";
when 12 => input_data <= x"89";
when 13 => input_data <= x"ab";
-- Source MAC address
when 14 => input_data <= x"A0";
when 15 => input_data <= x"B3";
--
when 16 => input_data <= x"CC";
when 17 => input_data <= x"4C";
when 18 => input_data <= x"F9";
when 19 => input_data <= x"EF";
-- Ether Type 08:06 << ARP!
when 20 => input_data <= x"08";
when 21 => input_data <= x"00";
------------------------
-- TCP packet
------------------------
-- IP Header
when 22 => input_data <= x"45";
when 23 => input_data <= x"00";
--
when 24 => input_data <= x"00";
when 25 => input_data <= x"34";
when 26 => input_data <= x"23";
when 27 => input_data <= x"93";
when 28 => input_data <= x"40";
when 29 => input_data <= x"00";
when 30 => input_data <= x"80";
when 31 => input_data <= x"06";
--
when 32 => input_data <= x"00";
when 33 => input_data <= x"00";
when 34 => input_data <= x"0a";
when 35 => input_data <= x"00";
when 36 => input_data <= x"00";
when 37 => input_data <= x"01";
when 38 => input_data <= x"0a";
when 39 => input_data <= x"00";
--
when 40 => input_data <= x"00";
when 41 => input_data <= x"0a";
-- TCP Header
when 42 => input_data <= x"c5";
when 43 => input_data <= x"81";
when 44 => input_data <= x"00";
when 45 => input_data <= x"50";
when 46 => input_data <= x"6f";
when 47 => input_data <= x"22";
--
when 48 => input_data <= x"be";
when 49 => input_data <= x"2c";
when 50 => input_data <= x"00";
when 51 => input_data <= x"00";
when 52 => input_data <= x"00";
when 53 => input_data <= x"00";
when 54 => input_data <= x"80";
when 55 => input_data <= x"02";
when 56 => input_data <= x"20";
when 57 => input_data <= x"00";
when 58 => input_data <= x"48";
when 59 => input_data <= x"1F";
when 60 => input_data <= x"00";
when 61 => input_data <= x"00";
when 62 => input_data <= x"02";
when 63 => input_data <= x"04";
when 64 => input_data <= x"05";
when 65 => input_data <= x"b4";
when 66 => input_data <= x"01";
when 67 => input_data <= x"03";
when 68 => input_data <= x"03";
when 69 => input_data <= x"08";
when 70 => input_data <= x"01";
when 71 => input_data <= x"01";
when 72 => input_data <= x"04";
when 73 => input_data <= x"02";
-- Misc padding
when 74 => input_data <= x"FF";
when 75 => input_data <= x"FF";
when 76 => input_data <= x"FF";
when 77 => input_data <= x"FF";
when 78 => input_data <= x"FF";
when 79 => input_data <= x"FF";
when 80 => input_data <= x"FF";
when 81 => input_data <= x"FF";
--- FCS
when 82 => input_data <= x"01";
when 83 => input_data <= x"01";
when 84 => input_data <= x"04";
when 85 => input_data <= x"02";
when 86 => input_data <= x"DD"; input_data_present <= '0';
when others => input_data <= x"DD"; input_data_present <= '0';
end case;
count2 <= 0;
end if;
end if;
end process;
end Behavioral;
|
entity sub2 is
generic (
VALUE : integer );
port (
x : out integer );
end entity;
architecture test of sub2 is
begin
x <= VALUE;
end architecture;
-------------------------------------------------------------------------------
entity sub1 is
generic (
ENABLE : boolean );
port (
y : out integer );
end entity;
architecture test of sub1 is
begin
value7_g: if ENABLE generate
sub: entity work.sub2
generic map ( VALUE => 7 )
port map ( x => y );
end generate;
value5_g: if not ENABLE generate
sub: entity work.sub2
generic map ( VALUE => 5 )
port map ( x => y );
end generate;
end architecture;
-------------------------------------------------------------------------------
entity elab7 is
end entity;
architecture test of elab7 is
signal a, b : integer;
begin
sa: entity work.sub1
generic map ( ENABLE => true )
port map ( y => a );
sb: entity work.sub1
generic map ( ENABLE => false )
port map ( y => b );
process is
begin
wait for 1 ns;
assert a = 7;
assert b = 5;
wait;
end process;
end architecture;
|
entity sub2 is
generic (
VALUE : integer );
port (
x : out integer );
end entity;
architecture test of sub2 is
begin
x <= VALUE;
end architecture;
-------------------------------------------------------------------------------
entity sub1 is
generic (
ENABLE : boolean );
port (
y : out integer );
end entity;
architecture test of sub1 is
begin
value7_g: if ENABLE generate
sub: entity work.sub2
generic map ( VALUE => 7 )
port map ( x => y );
end generate;
value5_g: if not ENABLE generate
sub: entity work.sub2
generic map ( VALUE => 5 )
port map ( x => y );
end generate;
end architecture;
-------------------------------------------------------------------------------
entity elab7 is
end entity;
architecture test of elab7 is
signal a, b : integer;
begin
sa: entity work.sub1
generic map ( ENABLE => true )
port map ( y => a );
sb: entity work.sub1
generic map ( ENABLE => false )
port map ( y => b );
process is
begin
wait for 1 ns;
assert a = 7;
assert b = 5;
wait;
end process;
end architecture;
|
entity sub2 is
generic (
VALUE : integer );
port (
x : out integer );
end entity;
architecture test of sub2 is
begin
x <= VALUE;
end architecture;
-------------------------------------------------------------------------------
entity sub1 is
generic (
ENABLE : boolean );
port (
y : out integer );
end entity;
architecture test of sub1 is
begin
value7_g: if ENABLE generate
sub: entity work.sub2
generic map ( VALUE => 7 )
port map ( x => y );
end generate;
value5_g: if not ENABLE generate
sub: entity work.sub2
generic map ( VALUE => 5 )
port map ( x => y );
end generate;
end architecture;
-------------------------------------------------------------------------------
entity elab7 is
end entity;
architecture test of elab7 is
signal a, b : integer;
begin
sa: entity work.sub1
generic map ( ENABLE => true )
port map ( y => a );
sb: entity work.sub1
generic map ( ENABLE => false )
port map ( y => b );
process is
begin
wait for 1 ns;
assert a = 7;
assert b = 5;
wait;
end process;
end architecture;
|
entity sub2 is
generic (
VALUE : integer );
port (
x : out integer );
end entity;
architecture test of sub2 is
begin
x <= VALUE;
end architecture;
-------------------------------------------------------------------------------
entity sub1 is
generic (
ENABLE : boolean );
port (
y : out integer );
end entity;
architecture test of sub1 is
begin
value7_g: if ENABLE generate
sub: entity work.sub2
generic map ( VALUE => 7 )
port map ( x => y );
end generate;
value5_g: if not ENABLE generate
sub: entity work.sub2
generic map ( VALUE => 5 )
port map ( x => y );
end generate;
end architecture;
-------------------------------------------------------------------------------
entity elab7 is
end entity;
architecture test of elab7 is
signal a, b : integer;
begin
sa: entity work.sub1
generic map ( ENABLE => true )
port map ( y => a );
sb: entity work.sub1
generic map ( ENABLE => false )
port map ( y => b );
process is
begin
wait for 1 ns;
assert a = 7;
assert b = 5;
wait;
end process;
end architecture;
|
entity sub2 is
generic (
VALUE : integer );
port (
x : out integer );
end entity;
architecture test of sub2 is
begin
x <= VALUE;
end architecture;
-------------------------------------------------------------------------------
entity sub1 is
generic (
ENABLE : boolean );
port (
y : out integer );
end entity;
architecture test of sub1 is
begin
value7_g: if ENABLE generate
sub: entity work.sub2
generic map ( VALUE => 7 )
port map ( x => y );
end generate;
value5_g: if not ENABLE generate
sub: entity work.sub2
generic map ( VALUE => 5 )
port map ( x => y );
end generate;
end architecture;
-------------------------------------------------------------------------------
entity elab7 is
end entity;
architecture test of elab7 is
signal a, b : integer;
begin
sa: entity work.sub1
generic map ( ENABLE => true )
port map ( y => a );
sb: entity work.sub1
generic map ( ENABLE => false )
port map ( y => b );
process is
begin
wait for 1 ns;
assert a = 7;
assert b = 5;
wait;
end process;
end architecture;
|
entity Time_test is
end Time_test;
architecture Behavioral of Time_test is
constant c_CLOCK_FREQUENCY : natural := 32000000;
constant c_SWITCH_ON_TIME_ms : time := 200 ms;
constant c_SWITCH_COUNT_CYCLES : integer := integer(real(c_CLOCK_FREQUENCY *
(c_SWITCH_ON_TIME_ms / 1 ms)) / 1000.0);
begin
process is
begin
report " Switch ON time " & time'image(c_SWITCH_ON_TIME_ms) severity NOTE;
report " Switch count " & natural'image(c_SWITCH_COUNT_CYCLES) severity NOTE;
-- sanity checks on time constraints
report "Clock frequency = " & natural'image(c_CLOCK_FREQUENCY) & " Hz" severity NOTE;
report "Clock period = " & time'image( 1 sec / c_CLOCK_FREQUENCY) severity NOTE;
report "Switch period = " & time'image ( 1 sec / c_CLOCK_FREQUENCY * c_SWITCH_COUNT_CYCLES) severity NOTE;
Assert c_SWITCH_ON_TIME_ms = 1 sec / c_CLOCK_FREQUENCY * c_SWITCH_COUNT_CYCLES
report "Wrong Switch ON time = " & time'image ( 1 sec / c_CLOCK_FREQUENCY * c_SWITCH_COUNT_CYCLES) severity ERROR;
wait;
end process;
end Behavioral;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity prioritizer_inferred is
generic (
input_bits : natural := 2
);
port (
datain : in std_ulogic_vector(input_bits-1 downto 0);
dataout : out std_ulogic_vector(input_bits-1 downto 0)
);
end;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM_Bank
-- Module Name: RAM_Bank_File
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of a memory RAM bank. Only used for tests.
-- In this bank all memories are accessed at the same time, therefore it is like
-- to access one big memory with memory word multiplied by number of memories in the bank.
-- It is useful when you want to access more than one location at the same time.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- The total number of memories inside of the memory bank.
--
-- ram_address_size :
--
-- Address size of each RAM in the RAM bank used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word of each RAM in the RAM bank.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on each RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
--
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
architecture file_load of ram_bank is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
pure function load_ram (ram_file_name : in string) return ramtype is
FILE ram_file : text is in ram_file_name;
variable line_n : line;
variable memory_ram : ramtype;
variable file_read_buffer : std_logic_vector((file_ram_word_size - 1) downto 0);
variable file_buffer_amount : integer;
variable ram_buffer_amount : integer;
begin
file_buffer_amount := file_ram_word_size;
for I in ramtype'range loop
ram_buffer_amount := 0;
if (not endfile(ram_file) or (file_buffer_amount /= file_ram_word_size)) then
while ram_buffer_amount /= ram_word_size loop
if file_buffer_amount = file_ram_word_size then
if (not endfile(ram_file)) then
readline (ram_file, line_n);
read (line_n, file_read_buffer);
else
file_read_buffer := (others => '0');
end if;
file_buffer_amount := 0;
end if;
memory_ram(I)(ram_buffer_amount) := file_read_buffer(file_buffer_amount);
ram_buffer_amount := ram_buffer_amount + 1;
file_buffer_amount := file_buffer_amount + 1;
end loop;
else
memory_ram(I) := (others => '0');
end if;
end loop;
return memory_ram;
end function;
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype := load_ram(load_file_name);
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
memory_ram <= load_ram(load_file_name);
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address)) + index) <= data_in(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address)) + index);
end loop;
end if;
end process;
end file_load;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dexp_64ns_64ns_64_18_full_dsp is
generic (
ID : integer := 8;
NUM_STAGE : integer := 18;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dexp_64ns_64ns_64_18_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_dexp_16_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dexp_16_full_dsp_64_u : component feedforward_ap_dexp_16_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dexp_64ns_64ns_64_18_full_dsp is
generic (
ID : integer := 8;
NUM_STAGE : integer := 18;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dexp_64ns_64ns_64_18_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_dexp_16_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dexp_16_full_dsp_64_u : component feedforward_ap_dexp_16_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dexp_64ns_64ns_64_18_full_dsp is
generic (
ID : integer := 8;
NUM_STAGE : integer := 18;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dexp_64ns_64ns_64_18_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_dexp_16_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dexp_16_full_dsp_64_u : component feedforward_ap_dexp_16_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dexp_64ns_64ns_64_18_full_dsp is
generic (
ID : integer := 8;
NUM_STAGE : integer := 18;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dexp_64ns_64ns_64_18_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_dexp_16_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dexp_16_full_dsp_64_u : component feedforward_ap_dexp_16_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Declaration types_buf package components.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Technology constants definition.
library techmap;
use techmap.gencomp.all;
--! @brief Declaration of 'virtual' Buffers components.
package types_buf is
--! @brief Clock signals multiplexer.
--! @param[in] tech Technology selector.
--! @param[out] O Output clock signal.
--! @param[in] I1 Input clock signal 1.
--! @param[in] I2 Input clock signal 2.
--! @param[in] S Input signals switcher:
--! 0 = I1; 1 = I2.
component bufgmux_tech is
generic (
tech : integer := 0;
tmode_always_ena : boolean := false
);
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic);
end component;
--! @brief Input PAD buffer.
--! @details This buffer makes sense only for ASIC implementation.
--! @param[in] tech Technology selector.
--! @param[out] o Output buffered signal.
--! @param[in] i Input unbuffered signal.
component ibuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
i : in std_logic
);
end component;
--! @brief Output PAD buffer.
--! @details This buffer makes sense only for ASIC implementation.
--! @param[in] tech Technology selector.
--! @param[out] o Output signal directly connected to the ASIC output pin.
--! @param[in] i Input signal.
component obuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
i : in std_logic
);
end component;
--! @brief Input/Output PAD buffer.
--! @param[in] tech Technology selector.
--! @param[out] o Output signal
--! @param[inout] io Bi-directional signal.
--! @param[in] i Input signal
--! @param[in] t Controlling signal: 0 = in; 1=out
--!
--! Example:
--! @code
--! entity foo is port (
--! io_gpio : inout std_logic
--! )
--! end foo;
--! architecture rtl of foo is
--! signal ob_gpio_direction : std_logic;
--! signal ob_gpio_opins : std_logic;
--! signal ib_gpio_ipins : std_logic;
--! ...
--! begin
--! ob_gpio_direction <= '1';
--!
--! iob : iobuf_tech generic map(kintex7)
--! port map (ib_gpio_ipins, io_gpio, ob_gpio_opins, ob_gpio_direction);
--!
--! reg : process(clk, nrst) begin
--! if rising_edge(clk) then
--! reg1 <= ib_gpio_ipins;
--! ob_gpio_opins <= reg2;
--! end;
--! end process;
--! end;
--! @endcode
component iobuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
--! @brief Gigabit buffer with differential inputs.
--! @param[in] gclk_p Differential clock input.
--! @param[in] gclk_n Differential clock inversed input.
--! @param[out] o_clk Unbuffered clock output.
component igdsbuf_tech is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end component;
end;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Declaration types_buf package components.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Technology constants definition.
library techmap;
use techmap.gencomp.all;
--! @brief Declaration of 'virtual' Buffers components.
package types_buf is
--! @brief Clock signals multiplexer.
--! @param[in] tech Technology selector.
--! @param[out] O Output clock signal.
--! @param[in] I1 Input clock signal 1.
--! @param[in] I2 Input clock signal 2.
--! @param[in] S Input signals switcher:
--! 0 = I1; 1 = I2.
component bufgmux_tech is
generic (
tech : integer := 0;
tmode_always_ena : boolean := false
);
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic);
end component;
--! @brief Input PAD buffer.
--! @details This buffer makes sense only for ASIC implementation.
--! @param[in] tech Technology selector.
--! @param[out] o Output buffered signal.
--! @param[in] i Input unbuffered signal.
component ibuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
i : in std_logic
);
end component;
--! @brief Output PAD buffer.
--! @details This buffer makes sense only for ASIC implementation.
--! @param[in] tech Technology selector.
--! @param[out] o Output signal directly connected to the ASIC output pin.
--! @param[in] i Input signal.
component obuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
i : in std_logic
);
end component;
--! @brief Input/Output PAD buffer.
--! @param[in] tech Technology selector.
--! @param[out] o Output signal
--! @param[inout] io Bi-directional signal.
--! @param[in] i Input signal
--! @param[in] t Controlling signal: 0 = in; 1=out
--!
--! Example:
--! @code
--! entity foo is port (
--! io_gpio : inout std_logic
--! )
--! end foo;
--! architecture rtl of foo is
--! signal ob_gpio_direction : std_logic;
--! signal ob_gpio_opins : std_logic;
--! signal ib_gpio_ipins : std_logic;
--! ...
--! begin
--! ob_gpio_direction <= '1';
--!
--! iob : iobuf_tech generic map(kintex7)
--! port map (ib_gpio_ipins, io_gpio, ob_gpio_opins, ob_gpio_direction);
--!
--! reg : process(clk, nrst) begin
--! if rising_edge(clk) then
--! reg1 <= ib_gpio_ipins;
--! ob_gpio_opins <= reg2;
--! end;
--! end process;
--! end;
--! @endcode
component iobuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
--! @brief Gigabit buffer with differential inputs.
--! @param[in] gclk_p Differential clock input.
--! @param[in] gclk_n Differential clock inversed input.
--! @param[out] o_clk Unbuffered clock output.
component igdsbuf_tech is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end component;
end;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package types_pkg is
file ALERT_FILE : text;
file LOG_FILE : text;
constant C_LOG_HDR_FOR_WAVEVIEW_WIDTH : natural := 100; -- For string in waveview indicating last log header
constant C_NUM_SYNC_FLAGS : positive := 10;
constant C_FLAG_NAME_LENGTH : positive := 20;
type t_void is (VOID);
type t_natural_array is array (natural range <>) of natural;
type t_integer_array is array (natural range <>) of integer;
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
type t_slv_array is array (natural range <>) of std_logic_vector;
type t_signed_array is array (natural range <>) of signed;
type t_unsigned_array is array (natural range <>) of unsigned;
-- Additions to predefined vector types
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
-- Note: Most types below have a matching to_string() in 'string_methods_pkg.vhd'
type t_info_target is (LOG_INFO, ALERT_INFO, USER_INFO);
type t_alert_level is (NO_ALERT, NOTE, TB_NOTE, WARNING, TB_WARNING, MANUAL_CHECK, ERROR, TB_ERROR, FAILURE, TB_FAILURE);
type t_enabled is (ENABLED, DISABLED);
type t_attention is (REGARD, EXPECT, IGNORE);
type t_radix is (BIN, HEX, DEC, HEX_BIN_IF_INVALID);
type t_radix_prefix is (EXCL_RADIX, INCL_RADIX);
type t_order is (INTERMEDIATE, FINAL);
type t_ascii_allow is (ALLOW_ALL, ALLOW_PRINTABLE_ONLY);
type t_blocking_mode is (BLOCKING, NON_BLOCKING);
type t_from_point_in_time is (FROM_NOW, FROM_LAST_EVENT);
type t_format_zeros is (AS_IS, KEEP_LEADING_0, SKIP_LEADING_0); -- AS_IS is deprecated and will be removed. Use KEEP_LEADING_0.
type t_format_string is (AS_IS, TRUNCATE, SKIP_LEADING_SPACE); -- Deprecated, will be removed.
type t_format_spaces is (KEEP_LEADING_SPACE, SKIP_LEADING_SPACE);
type t_truncate_string is (ALLOW_TRUNCATE, DISALLOW_TRUNCATE);
type t_log_format is (FORMATTED, UNFORMATTED);
type t_log_if_block_empty is (WRITE_HDR_IF_BLOCK_EMPTY, SKIP_LOG_IF_BLOCK_EMPTY, NOTIFY_IF_BLOCK_EMPTY);
type t_log_destination is (CONSOLE_AND_LOG, CONSOLE_ONLY, LOG_ONLY);
type t_match_strictness is (MATCH_STD, MATCH_STD_INCL_Z, MATCH_EXACT);
type t_alert_counters is array (NOTE to t_alert_level'right) of natural;
type t_alert_attention is array (NOTE to t_alert_level'right) of t_attention;
type t_attention_counters is array (t_attention'left to t_attention'right) of natural; -- Only used to build below type
type t_alert_attention_counters is array (NOTE to t_alert_level'right) of t_attention_counters;
type t_quietness is (NON_QUIET, QUIET);
type t_deprecate_setting is (NO_DEPRECATE, DEPRECATE_ONCE, ALWAYS_DEPRECATE);
type t_deprecate_list is array(0 to 9) of string(1 to 100);
type t_action_when_transfer_is_done is (RELEASE_LINE_AFTER_TRANSFER, HOLD_LINE_AFTER_TRANSFER);
type t_when_to_start_transfer is (START_TRANSFER_IMMEDIATE, START_TRANSFER_ON_NEXT_SS);
type t_action_between_words is (RELEASE_LINE_BETWEEN_WORDS, HOLD_LINE_BETWEEN_WORDS);
type t_byte_endianness is (FIRST_BYTE_LEFT, FIRST_BYTE_RIGHT);
type t_pulse_continuation is (ALLOW_PULSE_CONTINUATION, NO_PULSE_CONTINUATION_ALLOWED);
type t_global_ctrl is record
attention : t_alert_attention;
stop_limit : t_alert_counters;
end record;
type t_current_log_hdr is record
normal : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
large : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
xl : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
end record;
-- type for await_unblock_flag whether the method should set the flag back to blocked or not
type t_flag_returning is (KEEP_UNBLOCKED, RETURN_TO_BLOCK); -- value after unblock
type t_sync_flag_record is record
flag_name : string(1 to C_FLAG_NAME_LENGTH);
is_active : boolean;
end record;
constant C_SYNC_FLAG_DEFAULT : t_sync_flag_record := (
flag_name => (others => ' '),
is_active => true
);
type t_sync_flag_record_array is array (1 to C_NUM_SYNC_FLAGS) of t_sync_flag_record;
-- type for identifying VVC and command index finishing await_any_completion()
type t_info_on_finishing_await_any_completion is record
vvc_name : string(1 to 100); -- VVC name should not exceed this length
vvc_cmd_idx : natural; -- VVC command index
vvc_time_of_completion : time; -- time of completion
end record;
type t_uvvm_status is record
found_unexpected_simulation_warnings_or_worse : natural range 0 to 1; -- simulation end status: 0=no unexpected, 1=unexpected
found_unexpected_simulation_errors_or_worse : natural range 0 to 1; -- simulation end status: 0=no unexpected, 1=unexpected
mismatch_on_expected_simulation_warnings_or_worse : natural range 0 to 1; -- simulation status: 0=no mismatch, 1=mismatch
mismatch_on_expected_simulation_errors_or_worse : natural range 0 to 1; -- simulation status: 0=no mismatch, 1=mismatch
info_on_finishing_await_any_completion : t_info_on_finishing_await_any_completion; -- await_any_completion() trigger identifyer
end record t_uvvm_status;
-- defaults for t_uvvm_status and t_info_on_finishing_await_any_completion
constant C_INFO_ON_FINISHING_AWAIT_ANY_COMPLETION_VVC_NAME_DEFAULT : string := "no await_any_completion() finshed yet\n";
constant C_UVVM_STATUS_DEFAULT : t_uvvm_status := (
found_unexpected_simulation_warnings_or_worse => 0,
found_unexpected_simulation_errors_or_worse => 0,
mismatch_on_expected_simulation_warnings_or_worse => 0,
mismatch_on_expected_simulation_errors_or_worse => 0,
info_on_finishing_await_any_completion => (vvc_name => (C_INFO_ON_FINISHING_AWAIT_ANY_COMPLETION_VVC_NAME_DEFAULT, others => ' '),
vvc_cmd_idx => 0,
vvc_time_of_completion => 0 ns)
);
type t_justify_center is (center);
-------------------------------------
-- BFMs and above
-------------------------------------
type t_transaction_result is (ACK, NAK, ERROR); -- add more when needed
type t_hierarchy_alert_level_print is array (NOTE to t_alert_level'right) of boolean;
constant C_HIERARCHY_NODE_NAME_LENGTH : natural := 20;
type t_hierarchy_node is
record
name : string(1 to C_HIERARCHY_NODE_NAME_LENGTH);
alert_attention_counters : t_alert_attention_counters;
alert_stop_limit : t_alert_counters;
alert_level_print : t_hierarchy_alert_level_print;
end record;
type t_bfm_delay_type is (NO_DELAY, TIME_FINISH2START, TIME_START2START);
type t_inter_bfm_delay is
record
delay_type : t_bfm_delay_type;
delay_in_time : time;
inter_bfm_delay_violation_severity : t_alert_level;
end record;
type t_void_bfm_config is (VOID);
constant C_VOID_BFM_CONFIG : t_void_bfm_config := VOID;
-------------------------------------
-- SB
-------------------------------------
-- Identifier_option: Typically describes what the next parameter means.
-- - ENTRY_NUM :
-- Incremented for each entry added to the queue.
-- Unlike POSITION, the ENTRY_NUMBER will stay the same for this entry, even if entries are inserted before this entry
-- - POSITION :
-- Position of entry in queue, independent of when the entry was inserted.
type t_identifier_option is (ENTRY_NUM, POSITION);
type t_range_option is (SINGLE, AND_LOWER, AND_HIGHER);
type t_tag_usage is (TAG, NO_TAG);
end package types_pkg;
package body types_pkg is
end package body types_pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2595.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02595ent IS
END c13s03b01x00p02n01i02595ent;
ARCHITECTURE c13s03b01x00p02n01i02595arch OF c13s03b01x00p02n01i02595ent IS
BEGIN
TESTING: PROCESS
variable k} : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02595 - Identifier can not end with '}'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02595arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2595.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02595ent IS
END c13s03b01x00p02n01i02595ent;
ARCHITECTURE c13s03b01x00p02n01i02595arch OF c13s03b01x00p02n01i02595ent IS
BEGIN
TESTING: PROCESS
variable k} : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02595 - Identifier can not end with '}'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02595arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2595.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02595ent IS
END c13s03b01x00p02n01i02595ent;
ARCHITECTURE c13s03b01x00p02n01i02595arch OF c13s03b01x00p02n01i02595ent IS
BEGIN
TESTING: PROCESS
variable k} : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02595 - Identifier can not end with '}'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02595arch;
|
-- data slicer test bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity data_slicer_tb is
end data_slicer_tb;
architecture behav of data_slicer_tb is
component data_slicer
generic (
width : positive;
sam_per_bit : positive
);
port (
clk : in std_logic;
inclk : in std_logic;
outclk : out std_logic;
rst : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic
);
end component;
signal clk : std_logic := '0';
signal inclk : std_logic := '0';
signal outclk : std_logic;
signal rst : std_logic := '1';
signal d : std_logic_vector(7 downto 0) := (others => '0');
signal q : std_logic;
begin
dut : data_slicer
generic map (width => 8, sam_per_bit => 8)
port map (clk, inclk, outclk, rst, d, q);
clk <= not clk after 50 ns;
rst <= '0' after 200 ns;
in_file : process
variable input : integer;
variable l : line;
file vector_file : text is in "data_slicer_test.txt";
begin
wait until rst <= '0';
while not endfile(vector_file) loop
readline(vector_file, l);
read(l, input);
wait until rising_edge(clk);
inclk <= '1';
d <= std_logic_vector(to_unsigned(input, 8));
end loop;
end process;
end behav;
|
--
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
|
--
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
|
--
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
|
--
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
|
--
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
|
--
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
|
--
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
|
--
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
|
--
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
|
--
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
|
--
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
|
--
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
|
--
-- Timers for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_timers is
generic (
A_TSCENABLED: boolean := false;
A_PWMCOUNT: integer range 1 to 8 := 2;
A_WIDTH: integer range 1 to 32 := 16;
A_PRESCALER_ENABLED: boolean := true;
A_BUFFERS: boolean :=true;
B_TSCENABLED: boolean := false;
B_PWMCOUNT: integer range 1 to 8 := 2;
B_WIDTH: integer range 1 to 32 := 16;
B_PRESCALER_ENABLED: boolean := false;
B_BUFFERS: boolean := false
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
wb_intb_o:out std_logic;
pwm_A_out: out std_logic_vector(A_PWMCOUNT-1 downto 0);
pwm_B_out: out std_logic_vector(B_PWMCOUNT-1 downto 0)
);
end entity zpuino_timers;
architecture behave of zpuino_timers is
component timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end component timer;
signal timer0_read: std_logic_vector(wordSize-1 downto 0);
signal timer0_stb: std_logic;
signal timer0_cyc: std_logic;
signal timer0_we: std_logic;
signal timer0_interrupt: std_logic;
signal timer0_ack: std_logic;
signal timer1_read: std_logic_vector(wordSize-1 downto 0);
signal timer1_stb: std_logic;
signal timer1_cyc: std_logic;
signal timer1_we: std_logic;
signal timer1_interrupt: std_logic;
signal timer1_ack: std_logic;
begin
wb_inta_o <= timer0_interrupt;
wb_intb_o <= timer1_interrupt;
--comp <= timer0_comp;
timer0_inst: timer
generic map (
TSCENABLED => A_TSCENABLED,
PWMCOUNT => A_PWMCOUNT,
WIDTH => A_WIDTH,
PRESCALER_ENABLED => A_PRESCALER_ENABLED,
BUFFERS => A_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer0_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer0_cyc,
wb_stb_i => timer0_stb,
wb_we_i => timer0_we,
wb_ack_o => timer0_ack,
wb_inta_o => timer0_interrupt,
pwm_out => pwm_A_out
);
timer1_inst: timer
generic map (
TSCENABLED => B_TSCENABLED,
PWMCOUNT => B_PWMCOUNT,
WIDTH => B_WIDTH,
PRESCALER_ENABLED => B_PRESCALER_ENABLED,
BUFFERS => B_BUFFERS
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => timer1_read,
wb_dat_i => wb_dat_i,
wb_adr_i => wb_adr_i(7 downto 2),
wb_cyc_i => timer1_cyc,
wb_stb_i => timer1_stb,
wb_we_i => timer1_we,
wb_ack_o => timer1_ack,
wb_inta_o => timer1_interrupt,
pwm_out => pwm_B_out
);
process(wb_adr_i,timer0_read,timer1_read)
begin
wb_dat_o <= (others => '0');
case wb_adr_i(8) is
when '0' =>
wb_dat_o <= timer0_read;
when '1' =>
wb_dat_o <= timer1_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
timer0_cyc <= wb_cyc_i when wb_adr_i(8)='0' else '0';
timer1_cyc <= wb_cyc_i when wb_adr_i(8)='1' else '0';
timer0_stb <= wb_stb_i when wb_adr_i(8)='0' else '0';
timer1_stb <= wb_stb_i when wb_adr_i(8)='1' else '0';
timer0_we <= wb_we_i when wb_adr_i(8)='0' else '0';
timer1_we <= wb_we_i when wb_adr_i(8)='1' else '0';
wb_ack_o <= timer0_ack or timer1_ack;
--spp_data(0) <= timer0_spp_data;
--spp_data(1) <= timer1_spp_data;
--spp_en(0) <= timer0_spp_en;
--spp_en(1) <= timer1_spp_en;
end behave;
|
-- A simple 0-23 up counter.
--
-- entity name: g23_mars_timer
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 14/03/2014
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY g23_count_to_23 IS
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
sec_msd : out STD_LOGIC_VECTOR(2 downto 0);
sec_lsd : out STD_LOGIC_VECTOR(3 downto 0)
);
END g23_count_to_23;
ARCHITECTURE alpha OF g23_count_to_23 IS
signal decade_reached : STD_LOGIC;
signal seconds_msd : STD_LOGIC_VECTOR (2 downto 0);
signal seconds_lsd : STD_LOGIC_VECTOR (3 downto 0);
BEGIN
decade_reached <= '1' when (seconds_lsd = "1001") else '0';
sec_msd <= seconds_msd;
sec_lsd <= seconds_lsd;
count_to_9 : lpm_counter
GENERIC MAP (
lpm_modulus => 10,
lpm_width => 4
)
PORT MAP (
clock => clk,
aclr => reset,
q => seconds_lsd
);
count_to_2 : lpm_counter
GENERIC MAP(
lpm_modulus => 3,
lpm_width => 3
)
PORT MAP(
cnt_en => decade_reached,
clock => clk,
aclr => reset,
q => seconds_msd
);
END alpha;
|
library ieee;
use ieee.std_logic_1164.all;
entity test_slv is
end test_slv;
architecture behavioural of test_slv is
signal input : std_logic_vector(5 downto 0);
function popcnt(vector : std_logic_vector) return natural is
variable result : natural range 0 to vector'length := 0;
begin
for i in vector'range loop
if vector(i) = '1' then
result := result + 1;
end if;
end loop;
return result;
end function popcnt;
signal test_offsets_1 : std_logic_vector (7 downto 0) := "11110000";
signal test_offsets_2 : std_logic_vector (8 downto 1);
begin
process
variable result : natural range 0 to 6;
begin
input <= "000000";
result := popcnt(input);
assert result = 0
report "Result should be 0 for 000000" severity error;
input <= "000001";
wait for 1 ns;
result := popcnt(input);
assert result = 1
report "Result should be 1 for 000001" severity error;
input <= "111110";
wait for 1 ns;
result := popcnt(input);
assert result = 5
report "Result should be 5 for 111110" severity error;
test_offsets_2 <= test_offsets_1;
wait for 1 ns;
assert test_offsets_2 = "11110000"
report "can mix and match non-zero offsets" severity error;
wait;
end process;
end behavioural;
|
-- SIMON_CIPHER_TB.vhd
-- Copyright 2016 Michael Calvin McCoy
-- [email protected]
-- see LICENSE.md
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:00:46 10/04/2015
-- Design Name:
-- Module Name: D:/Work/Code/Simon_Speck_Ciphers/VHDL/SIMON_CIPHER_TB.vhd
-- Project Name: Simon
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SIMON_CIPHER
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.SIMON_CONSTANTS.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY SIMON_CIPHER_TB IS
END SIMON_CIPHER_TB;
ARCHITECTURE behavior OF SIMON_CIPHER_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SIMON_CIPHER
GENERIC(KEY_SIZE : integer range 0 to 256;
BLOCK_SIZE : integer range 0 to 128;
ROUND_LIMIT: integer range 0 to 72);
PORT(
SYS_CLK : IN std_logic;
RST : IN std_logic;
BUSY : OUT std_logic;
CONTROL : IN std_logic_vector(1 downto 0);
KEY : IN std_logic_vector(KEY_SIZE - 1 downto 0);
BLOCK_INPUT : IN std_logic_vector(BLOCK_SIZE - 1 downto 0);
BLOCK_OUTPUT : OUT std_logic_vector(BLOCK_SIZE - 1 downto 0)
);
END COMPONENT;
--Global Inputs
signal SYS_CLK : std_logic := '0';
signal RST : std_logic := '0';
signal CONTROL : std_logic_vector(1 downto 0) := (others => '0');
--UUT 1
signal KEY_1 : std_logic_vector(63 downto 0) := (others => '0');
signal BLOCK_INPUT_1 : std_logic_vector(31 downto 0) := (others => '0');
signal BUSY_1 : std_logic;
signal BLOCK_OUTPUT_1 : std_logic_vector(31 downto 0);
--UUT 2
signal KEY_2 : std_logic_vector(71 downto 0) := (others => '0');
signal BLOCK_INPUT_2 : std_logic_vector(47 downto 0) := (others => '0');
signal BUSY_2 : std_logic;
signal BLOCK_OUTPUT_2 : std_logic_vector(47 downto 0);
--UUT 3
signal KEY_3 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_3 : std_logic_vector(47 downto 0) := (others => '0');
signal BUSY_3 : std_logic;
signal BLOCK_OUTPUT_3 : std_logic_vector(47 downto 0);
--UUT 4
signal KEY_4 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_4 : std_logic_vector(63 downto 0) := (others => '0');
signal BUSY_4 : std_logic;
signal BLOCK_OUTPUT_4 : std_logic_vector(63 downto 0);
--UUT 5
signal KEY_5 : std_logic_vector(127 downto 0) := (others => '0');
signal BLOCK_INPUT_5 : std_logic_vector(63 downto 0) := (others => '0');
signal BUSY_5 : std_logic;
signal BLOCK_OUTPUT_5 : std_logic_vector(63 downto 0);
--UUT 6
signal KEY_6 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_6 : std_logic_vector(95 downto 0) := (others => '0');
signal BUSY_6 : std_logic;
signal BLOCK_OUTPUT_6 : std_logic_vector(95 downto 0);
--UUT 7
signal KEY_7 : std_logic_vector(143 downto 0) := (others => '0');
signal BLOCK_INPUT_7 : std_logic_vector(95 downto 0) := (others => '0');
signal BUSY_7 : std_logic;
signal BLOCK_OUTPUT_7 : std_logic_vector(95 downto 0);
--UUT 8
signal KEY_8 : std_logic_vector(127 downto 0) := (others => '0');
signal BLOCK_INPUT_8 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_8 : std_logic;
signal BLOCK_OUTPUT_8 : std_logic_vector(127 downto 0);
--UUT 9
signal KEY_9 : std_logic_vector(191 downto 0) := (others => '0');
signal BLOCK_INPUT_9 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_9 : std_logic;
signal BLOCK_OUTPUT_9 : std_logic_vector(127 downto 0);
--UUT 10
signal KEY_10 : std_logic_vector(255 downto 0) := (others => '0');
signal BLOCK_INPUT_10 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_10 : std_logic;
signal BLOCK_OUTPUT_10 : std_logic_vector(127 downto 0);
-- Clock period definitions
constant SYS_CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut_1: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 64,
BLOCK_SIZE => 32,
ROUND_LIMIT => Round_Count_Lookup(64, 32))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_1,
CONTROL => CONTROL,
KEY => KEY_1,
BLOCK_INPUT => BLOCK_INPUT_1,
BLOCK_OUTPUT => BLOCK_OUTPUT_1
);
uut_2: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 72,
BLOCK_SIZE => 48,
ROUND_LIMIT => Round_Count_Lookup(72, 48))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_2,
CONTROL => CONTROL,
KEY => KEY_2,
BLOCK_INPUT => BLOCK_INPUT_2,
BLOCK_OUTPUT => BLOCK_OUTPUT_2
);
uut_3: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 48,
ROUND_LIMIT => Round_Count_Lookup(96, 48))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_3,
CONTROL => CONTROL,
KEY => KEY_3,
BLOCK_INPUT => BLOCK_INPUT_3,
BLOCK_OUTPUT => BLOCK_OUTPUT_3
);
uut_4: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 64,
ROUND_LIMIT => Round_Count_Lookup(96, 64))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_4,
CONTROL => CONTROL,
KEY => KEY_4,
BLOCK_INPUT => BLOCK_INPUT_4,
BLOCK_OUTPUT => BLOCK_OUTPUT_4
);
uut_5: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 128,
BLOCK_SIZE => 64,
ROUND_LIMIT => Round_Count_Lookup(128, 64))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_5,
CONTROL => CONTROL,
KEY => KEY_5,
BLOCK_INPUT => BLOCK_INPUT_5,
BLOCK_OUTPUT => BLOCK_OUTPUT_5
);
uut_6: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 96,
ROUND_LIMIT => Round_Count_Lookup(96, 96))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_6,
CONTROL => CONTROL,
KEY => KEY_6,
BLOCK_INPUT => BLOCK_INPUT_6,
BLOCK_OUTPUT => BLOCK_OUTPUT_6
);
uut_7: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 144,
BLOCK_SIZE => 96,
ROUND_LIMIT => Round_Count_Lookup(144, 96))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_7,
CONTROL => CONTROL,
KEY => KEY_7,
BLOCK_INPUT => BLOCK_INPUT_7,
BLOCK_OUTPUT => BLOCK_OUTPUT_7
);
uut_8: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 128,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(128, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_8,
CONTROL => CONTROL,
KEY => KEY_8,
BLOCK_INPUT => BLOCK_INPUT_8,
BLOCK_OUTPUT => BLOCK_OUTPUT_8
);
uut_9: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 192,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(192, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_9,
CONTROL => CONTROL,
KEY => KEY_9,
BLOCK_INPUT => BLOCK_INPUT_9,
BLOCK_OUTPUT => BLOCK_OUTPUT_9
);
uut_10: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 256,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(256, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_10,
CONTROL => CONTROL,
KEY => KEY_10,
BLOCK_INPUT => BLOCK_INPUT_10,
BLOCK_OUTPUT => BLOCK_OUTPUT_10
);
-- Clock process definitions
SYS_CLK_process :process
begin
for i in 0 to 500 loop
SYS_CLK <= '0';
wait for SYS_CLK_period/2;
SYS_CLK <= '1';
wait for SYS_CLK_period/2;
end loop ;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for SYS_CLK_period*10;
KEY_1 <= X"1918111009080100";
KEY_2 <= X"1211100a0908020100";
KEY_3 <= X"1a19181211100a0908020100";
KEY_4 <= X"131211100b0a090803020100";
KEY_5 <= X"1b1a1918131211100b0a090803020100";
KEY_6 <= X"0d0c0b0a0908050403020100";
KEY_7 <= X"1514131211100d0c0b0a0908050403020100";
KEY_8 <= X"0f0e0d0c0b0a09080706050403020100";
KEY_9 <= X"17161514131211100f0e0d0c0b0a09080706050403020100";
KEY_10 <= X"1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020100";
CONTROL <= "01";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
BLOCK_INPUT_1 <= X"65656877";
BLOCK_INPUT_2 <= X"6120676e696c";
BLOCK_INPUT_3 <= X"72696320646e";
BLOCK_INPUT_4 <= X"6f7220676e696c63";
BLOCK_INPUT_5 <= X"656b696c20646e75";
BLOCK_INPUT_6 <= X"2072616c6c69702065687420";
BLOCK_INPUT_7 <= X"74616874207473756420666f";
BLOCK_INPUT_8 <= X"63736564207372656c6c657661727420";
BLOCK_INPUT_9 <= X"206572656874206e6568772065626972";
BLOCK_INPUT_10 <= X"74206e69206d6f6f6d69732061207369";
CONTROL <= "11";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
assert BLOCK_OUTPUT_1 /= X"c69be9bb" report "UUT1 Encryption Success" severity note;
assert BLOCK_OUTPUT_1 = X"c69be9bb" report "UUT1 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_2 /= X"dae5ac292cac" report "UUT2 Encryption Success" severity note;
assert BLOCK_OUTPUT_2 = X"dae5ac292cac" report "UUT2 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_3 /= X"6e06a5acf156" report "UUT3 Encryption Success" severity note;
assert BLOCK_OUTPUT_3 = X"6e06a5acf156" report "UUT3 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_4 /= X"5ca2e27f111a8fc8" report "UUT4 Encryption Success" severity note;
assert BLOCK_OUTPUT_4 = X"5ca2e27f111a8fc8" report "UUT4 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_5 /= X"44c8fc20b9dfa07a" report "UUT5 Encryption Success" severity note;
assert BLOCK_OUTPUT_5 = X"44c8fc20b9dfa07a" report "UUT5 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_6 /= X"602807a462b469063d8ff082" report "UUT6 Encryption Success" severity note;
assert BLOCK_OUTPUT_6 = X"602807a462b469063d8ff082" report "UUT6 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_7 /= X"ecad1c6c451e3f59c5db1ae9" report "UUT7 Encryption Success" severity note;
assert BLOCK_OUTPUT_7 = X"ecad1c6c451e3f59c5db1ae9" report "UUT7 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_8 /= X"49681b1e1e54fe3f65aa832af84e0bbc" report "UUT8 Encryption Success" severity note;
assert BLOCK_OUTPUT_8 = X"49681b1e1e54fe3f65aa832af84e0bbc" report "UUT8 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_9 /= X"c4ac61effcdc0d4f6c9c8d6e2597b85b" report "UUT9 Encryption Success" severity note;
assert BLOCK_OUTPUT_9 = X"c4ac61effcdc0d4f6c9c8d6e2597b85b" report "UUT9 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_10 /= X"8d2b5579afc8a3a03bf72a87efe7b868" report "UUT10 Encryption Success" severity note;
assert BLOCK_OUTPUT_10 = X"8d2b5579afc8a3a03bf72a87efe7b868" report "UUT10 Encryption Failed" severity failure;
BLOCK_INPUT_1 <= X"c69be9bb";
BLOCK_INPUT_2 <= X"dae5ac292cac";
BLOCK_INPUT_3 <= X"6e06a5acf156";
BLOCK_INPUT_4 <= X"5ca2e27f111a8fc8";
BLOCK_INPUT_5 <= X"44c8fc20b9dfa07a";
BLOCK_INPUT_6 <= X"602807a462b469063d8ff082";
BLOCK_INPUT_7 <= X"ecad1c6c451e3f59c5db1ae9";
BLOCK_INPUT_8 <= X"49681b1e1e54fe3f65aa832af84e0bbc";
BLOCK_INPUT_9 <= X"c4ac61effcdc0d4f6c9c8d6e2597b85b";
BLOCK_INPUT_10 <= X"8d2b5579afc8a3a03bf72a87efe7b868";
CONTROL <= "10";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
assert BLOCK_OUTPUT_1 /= X"65656877" report "UUT1 Decryption Success" severity note;
assert BLOCK_OUTPUT_1 = X"65656877" report "UUT1 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_2 /= X"6120676e696c" report "UUT2 Decryption Success" severity note;
assert BLOCK_OUTPUT_2 = X"6120676e696c" report "UUT2 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_3 /= X"72696320646e" report "UUT3 Decryption Success" severity note;
assert BLOCK_OUTPUT_3 = X"72696320646e" report "UUT3 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_4 /= X"6f7220676e696c63" report "UUT4 Decryption Success" severity note;
assert BLOCK_OUTPUT_4 = X"6f7220676e696c63" report "UUT4 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_5 /= X"656b696c20646e75" report "UUT5 Decryption Success" severity note;
assert BLOCK_OUTPUT_5 = X"656b696c20646e75" report "UUT5 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_6 /= X"2072616c6c69702065687420" report "UUT6 Decryption Success" severity note;
assert BLOCK_OUTPUT_6 = X"2072616c6c69702065687420" report "UUT6 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_7 /= X"74616874207473756420666f" report "UUT7 Decryption Success" severity note;
assert BLOCK_OUTPUT_7 = X"74616874207473756420666f" report "UUT7 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_8 /= X"63736564207372656c6c657661727420" report "UUT8 Decryption Success" severity note;
assert BLOCK_OUTPUT_8 = X"63736564207372656c6c657661727420" report "UUT8 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_9 /= X"206572656874206e6568772065626972" report "UUT9 Decryption Success" severity note;
assert BLOCK_OUTPUT_9 = X"206572656874206e6568772065626972" report "UUT9 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_10 /= X"74206e69206d6f6f6d69732061207369" report "UUT10 Decryption Success" severity note;
assert BLOCK_OUTPUT_10 = X"74206e69206d6f6f6d69732061207369" report "UUT10 Decryption Failed" severity failure;
wait;
end process;
END behavior;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.transaction_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_cmd_pkg is
alias t_operation is work.transaction_pkg.t_operation;
--========================================================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--========================================================================================================================
type t_vvc_cmd_record is record
-- Common UVVM fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
data_routing : t_data_routing;
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
parent_msg_id_panel : t_msg_id_panel;
-- VVC dedicated fields
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
stable_req : time;
stable_req_from : t_from_point_in_time;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
-- Common VVC fields
operation => NO_OPERATION, -- Default unless overwritten by a common operation
alert_level => failure,
proc_call => (others => NUL),
msg => (others => NUL),
data_routing => NA,
cmd_idx => 0,
command_type => NO_command_type,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
delay => 0 ns,
quietness => NON_QUIET,
parent_msg_id_panel => C_UNUSED_MSG_ID_PANEL,
-- VVC dedicated fields
data => (others => '0'),
data_exp => (others => '0'),
stable_req => 0 ns,
stable_req_from => FROM_NOW
);
--========================================================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--========================================================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - These are used for storing the result of the read/receive BFM commands issued by the VVC,
-- - so that the result can be transported from the VVC to the sequencer via a
-- a fetch_result() call as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result matches the return value of read/receive procedure in the BFM.
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>, natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => -1));
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
entity hazard_control_block is
port (
dest_reg_en : in std_logic;
dest_reg : in std_logic_vector(3 downto 0);
src_reg1_en : std_logic;
src_reg1 : in std_logic_vector(3 downto 0);
src_reg2_en : in std_logic;
src_reg2 : in std_logic_vector(3 downto 0);
handlerPC : in std_logic_vector(7 downto 0);
nop : inout std_logic;
interrupt_happened : in std_logic;
interrupt_handled : in std_logic;
src_select : out std_logic_vector(1 downto 0);
PC : inout std_logic_vector(7 downto 0);
branch : in std_logic;
branch_addr : in std_logic_vector(7 downto 0);
operation : in std_logic_vector(4 downto 0);
clk, rst : in std_logic;
PC2handler : out std_logic_vector(7 downto 0)
);
end entity;
architecture behav of hazard_control_block is
signal prev_dest_reg_en : std_logic;
signal prev_dest_reg : std_logic_vector(3 downto 0);
signal state : std_logic_vector(1 downto 0);
signal temp_pc : std_logic_vector(7 downto 0);
begin
process(clk, rst)
begin
if (rst = '1') then
report "Control Block Reset";
PC <= X"00";
nop <= '0';
prev_dest_reg_en <= '0';
state <= "00";
elsif (rising_edge(clk)) then
if (state = "00") then
if (branch = '1') then
PC <= branch_addr;
elsif (nop = '1') then
PC <= PC - 1;
else
PC <= PC + 1;
end if;
else
PC <= X"00";
temp_pc <= handlerPC;
end if;
elsif falling_edge(clk) then
report "prev_dest_reg_en: " & integer'image(conv_integer(prev_dest_reg_en)) & "prev_dest_reg: " & integer'image(conv_integer(prev_dest_reg));
report "src_reg1_en: " & integer'image(conv_integer(src_reg1_en)) & "src_reg1: " & integer'image(conv_integer(src_reg1));
report "src_reg2_en: " & integer'image(conv_integer(src_reg2_en)) & "src_reg2: " & integer'image(conv_integer(src_reg2));
if (state = "00") then
nop <= '0';
src_select <= "00";
if ((src_reg1_en = '1') and (prev_dest_reg_en = '1')) then
report "Source reg 1 enable & Prev dest reg en";
if (src_reg1 = prev_dest_reg) then
report "Src reg 1, prev dest reg 1";
src_select(0) <= '1';
end if;
end if;
if ((src_reg2_en = '1') and (prev_dest_reg_en = '1')) then
report "Source reg 2 enable & prev dest reg enable";
if (src_reg2 = prev_dest_reg) then
report "Source reg 2, prev dest reg 2";
src_select(1) <= '1';
end if;
end if;
if (dest_reg_en = '1') then
report "dest reg enable1";
prev_dest_reg_en <= '1';
prev_dest_reg <= dest_reg;
else
prev_dest_reg_en <= '0';
end if;
if (branch = '1') then
nop <= '1';
end if;
if (interrupt_happened = '1' and interrupt_handled = '0') then
state <= "01";
nop <= '1';
end if;
PC2handler <= PC;
else
PC <= X"00";
nop <= '0';
if (interrupt_happened = '0' and interrupt_handled = '1') then
PC <= temp_pc;
state <= "00";
end if;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
entity cocotb_wb_loopback is
port (
clk: in std_logic;
reset_n : in std_logic;
clk2 : in std_logic;
reset_n2 : in std_logic;
wbm_cyc : in std_logic;
wbm_stb : in std_logic;
wbm_we : in std_logic;
wbm_sel : in std_logic_vector(3 downto 0);
wbm_adr : in std_logic_vector(31 downto 0);
wbm_datrd : out std_logic_vector(31 downto 0);
wbm_datwr : in std_logic_vector(31 downto 0);
wbm_stall: out std_logic;
wbm_ack: out std_logic;
wbm_err: out std_logic;
wbmo_cyc : out std_logic;
wbmo_stb : out std_logic;
wbmo_we : out std_logic;
wbmo_sel : out std_logic_vector(3 downto 0);
wbmo_adr : out std_logic_vector(31 downto 0);
wbmo_datrd : in std_logic_vector(31 downto 0);
wbmo_datwr : out std_logic_vector(31 downto 0);
wbmo_err: in std_logic;
wbmo_stall: in std_logic;
wbmo_ack: in std_logic
);
end entity;
architecture rtl of cocotb_wb_loopback is
signal s_master_in : t_wishbone_master_in;
signal s_master_out : t_wishbone_master_out;
signal reg : std_logic_vector(31 downto 0);
begin
s_master_out.we <= wbm_we;
s_master_out.stb <= wbm_stb;
s_master_out.dat <= wbm_datwr;
s_master_out.adr <= wbm_adr;
s_master_out.sel <= x"f";
s_master_out.cyc <= wbm_cyc;
-- s_master_in.dat <= reg;
wbm_datrd <= s_master_in.dat;
wbm_ack <= s_master_in.ack;
wbm_stall <= s_master_in.stall;
wbm_err <= s_master_in.err;
wbmo_we <= s_master_out.we;
wbmo_stb <= s_master_out.stb;
wbmo_datwr <= s_master_out.dat;
wbmo_adr <= s_master_out.adr;
wbmo_sel <= s_master_out.sel;
wbmo_cyc <= s_master_out.cyc;
s_master_in.dat <= wbmo_datrd;
s_master_in.ack <= wbmo_ack;
s_master_in.err <= wbmo_err;
s_master_in.stall <= wbmo_stall;
-- main : process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(reset_n = '0') then
-- s_master_in.stall <= '0';
-- s_master_in.ack <= '0';
-- s_master_in.err <= '0';
-- reg <= (others => '0');
-- else
-- s_master_in.ack <= '0';
-- if((s_master_out.cyc and s_master_out.stb and not s_master_in.stall) = '1') then
-- if(s_master_out.we = '1') then
-- reg <= s_master_out.dat;
-- end if;
-- s_master_in.ack <= '1';
-- end if;
-- end if;
-- end if;
-- end process;
end architecture;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (3);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (2);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#FC0#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 1;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:52:04 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_ov7670_controller_1_0 -prefix
-- system_ov7670_controller_1_0_ system_ov7670_controller_0_0_stub.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_controller_1_0 is
Port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end system_ov7670_controller_1_0;
architecture stub of system_ov7670_controller_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,resend,config_finished,sioc,siod,reset,pwdn,xclk";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_controller,Vivado 2016.4";
begin
end;
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo_disposer.vhd
--
-- Version: v1.01.a
-- Description: This
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo_disposer is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_10 : in std_logic;
Rx_100 : in std_logic;
Rmii_rx_eop : in std_logic_vector(1 downto 0);
Rmii_rx_crs : in std_logic_vector(1 downto 0);
Rmii_rx_er : in std_logic_vector(1 downto 0);
Rmii_rx_dv : in std_logic_vector(1 downto 0);
Rmii_rx_data : in std_logic_vector(7 downto 0);
Rx_fifo_mt_n : in std_logic;
Rx_fifo_rd_en : out std_logic;
Rmii2mac_crs : out std_logic;
Rmii2mac_rx_clk : out std_logic;
Rmii2mac_rx_er : out std_logic;
Rmii2mac_rx_dv : out std_logic;
Rmii2mac_rxd : out std_logic_vector(3 downto 0)
);
end rx_fifo_disposer;
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_RESET_ACTIVE -- Assertion level for Reset signal.
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo_disposer is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
-- Signal names begin with a lowercase letter. User defined types and the
-- enumerated values with a type are all uppercase letters.
-- Signals of a user-defined type should be declared after the type declaration
-- Group signals by interfaces
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_ClK_L,
IDLE_ClK_H,
RX_100_RD_FIFO_ClK_L,
RX_100_NIB_0_CLK_L,
RX_100_NIB_0_CLK_H,
RX_100_NIB_1_CLK_L,
RX_100_NIB_1_CLK_H,
RX_100_NIB_1_RD_FIFO_CLK_H,
RX_10_RD_FIFO_CLK_L,
RX_10_NIB_0_00_CLK_L,
RX_10_NIB_0_01_CLK_L,
RX_10_NIB_0_02_CLK_L,
RX_10_NIB_0_03_CLK_L,
RX_10_NIB_0_04_CLK_L,
RX_10_NIB_0_05_CLK_L,
RX_10_NIB_0_06_CLK_L,
RX_10_NIB_0_07_CLK_L,
RX_10_NIB_0_08_CLK_L,
RX_10_NIB_0_09_CLK_L,
RX_10_NIB_0_00_CLK_H,
RX_10_NIB_0_01_CLK_H,
RX_10_NIB_0_02_CLK_H,
RX_10_NIB_0_03_CLK_H,
RX_10_NIB_0_04_CLK_H,
RX_10_NIB_0_05_CLK_H,
RX_10_NIB_0_06_CLK_H,
RX_10_NIB_0_07_CLK_H,
RX_10_NIB_0_08_CLK_H,
RX_10_NIB_0_09_CLK_H,
RX_10_NIB_1_00_CLK_L,
RX_10_NIB_1_01_CLK_L,
RX_10_NIB_1_02_CLK_L,
RX_10_NIB_1_03_CLK_L,
RX_10_NIB_1_04_CLK_L,
RX_10_NIB_1_05_CLK_L,
RX_10_NIB_1_06_CLK_L,
RX_10_NIB_1_07_CLK_L,
RX_10_NIB_1_08_CLK_L,
RX_10_NIB_1_09_CLK_L,
RX_10_NIB_1_00_CLK_H,
RX_10_NIB_1_01_CLK_H,
RX_10_NIB_1_02_CLK_H,
RX_10_NIB_1_03_CLK_H,
RX_10_NIB_1_04_CLK_H,
RX_10_NIB_1_05_CLK_H,
RX_10_NIB_1_06_CLK_H,
RX_10_NIB_1_07_CLK_H,
RX_10_NIB_1_08_CLK_H,
RX_10_NIB_1_09_CLK_H,
RX_10_NIB_1_09_RD_FIFO_CLK_H
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
begin
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
-- No Concurrent Signal Assignments
------------------------------------------------------------------------------
-- State Machine SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_ClK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine NEXT_STATE_PROCESS
------------------------------------------------------------------------------
NEXT_STATE_PROCESS : process (
present_state,
Rx_100,
Rx_10,
RMII_rx_EOP,
Rmii_rx_er,
Rmii_rx_crs,
Rmii_rx_dv,
Rmii_rx_data,
Rx_fifo_mt_n--new addition of signal
)
begin
case present_state is
when IDLE_ClK_L =>
if (Rx_100 = '1') then
next_state <= RX_100_RD_FIFO_ClK_L;
elsif (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when IDLE_ClK_H =>
if (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_L;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_RD_FIFO_ClK_L =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_NIB_0_CLK_L =>
next_state <= RX_100_NIB_0_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_0_CLK_H =>
next_state <= RX_100_NIB_1_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_1_CLK_L =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1')) then
next_state <= RX_100_NIB_1_CLK_H;
else
next_state <= RX_100_NIB_1_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_RD_FIFO_CLK_H =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_RD_FIFO_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_10_NIB_0_00_CLK_L =>
next_state <= RX_10_NIB_0_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_L =>
next_state <= RX_10_NIB_0_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_L =>
next_state <= RX_10_NIB_0_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_L =>
next_state <= RX_10_NIB_0_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_L =>
next_state <= RX_10_NIB_0_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_L =>
next_state <= RX_10_NIB_0_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_L =>
next_state <= RX_10_NIB_0_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_L =>
next_state <= RX_10_NIB_0_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_L =>
next_state <= RX_10_NIB_0_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_00_CLK_H =>
next_state <= RX_10_NIB_0_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_H =>
next_state <= RX_10_NIB_0_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_H =>
next_state <= RX_10_NIB_0_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_H =>
next_state <= RX_10_NIB_0_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_H =>
next_state <= RX_10_NIB_0_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_H =>
next_state <= RX_10_NIB_0_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_H =>
next_state <= RX_10_NIB_0_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_H =>
next_state <= RX_10_NIB_0_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_H =>
next_state <= RX_10_NIB_0_09_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_H =>
next_state <= RX_10_NIB_1_00_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_1_00_CLK_L =>
next_state <= RX_10_NIB_1_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_L =>
next_state <= RX_10_NIB_1_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_L =>
next_state <= RX_10_NIB_1_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_L =>
next_state <= RX_10_NIB_1_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_L =>
next_state <= RX_10_NIB_1_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_L =>
next_state <= RX_10_NIB_1_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_L =>
next_state <= RX_10_NIB_1_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_L =>
next_state <= RX_10_NIB_1_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_L =>
next_state <= RX_10_NIB_1_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_L =>
next_state <= RX_10_NIB_1_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_00_CLK_H =>
next_state <= RX_10_NIB_1_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_H =>
next_state <= RX_10_NIB_1_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_H =>
next_state <= RX_10_NIB_1_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_H =>
next_state <= RX_10_NIB_1_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_H =>
next_state <= RX_10_NIB_1_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_H =>
next_state <= RX_10_NIB_1_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_H =>
next_state <= RX_10_NIB_1_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_H =>
next_state <= RX_10_NIB_1_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_H =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1') or (Rx_fifo_mt_n = '0')) then
next_state <= RX_10_NIB_1_09_CLK_H;
else
next_state <= RX_10_NIB_1_09_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_RD_FIFO_CLK_H =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
end case;
end process;
end simulation;
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo_disposer.vhd
--
-- Version: v1.01.a
-- Description: This
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo_disposer is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_10 : in std_logic;
Rx_100 : in std_logic;
Rmii_rx_eop : in std_logic_vector(1 downto 0);
Rmii_rx_crs : in std_logic_vector(1 downto 0);
Rmii_rx_er : in std_logic_vector(1 downto 0);
Rmii_rx_dv : in std_logic_vector(1 downto 0);
Rmii_rx_data : in std_logic_vector(7 downto 0);
Rx_fifo_mt_n : in std_logic;
Rx_fifo_rd_en : out std_logic;
Rmii2mac_crs : out std_logic;
Rmii2mac_rx_clk : out std_logic;
Rmii2mac_rx_er : out std_logic;
Rmii2mac_rx_dv : out std_logic;
Rmii2mac_rxd : out std_logic_vector(3 downto 0)
);
end rx_fifo_disposer;
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_RESET_ACTIVE -- Assertion level for Reset signal.
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo_disposer is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
-- Signal names begin with a lowercase letter. User defined types and the
-- enumerated values with a type are all uppercase letters.
-- Signals of a user-defined type should be declared after the type declaration
-- Group signals by interfaces
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_ClK_L,
IDLE_ClK_H,
RX_100_RD_FIFO_ClK_L,
RX_100_NIB_0_CLK_L,
RX_100_NIB_0_CLK_H,
RX_100_NIB_1_CLK_L,
RX_100_NIB_1_CLK_H,
RX_100_NIB_1_RD_FIFO_CLK_H,
RX_10_RD_FIFO_CLK_L,
RX_10_NIB_0_00_CLK_L,
RX_10_NIB_0_01_CLK_L,
RX_10_NIB_0_02_CLK_L,
RX_10_NIB_0_03_CLK_L,
RX_10_NIB_0_04_CLK_L,
RX_10_NIB_0_05_CLK_L,
RX_10_NIB_0_06_CLK_L,
RX_10_NIB_0_07_CLK_L,
RX_10_NIB_0_08_CLK_L,
RX_10_NIB_0_09_CLK_L,
RX_10_NIB_0_00_CLK_H,
RX_10_NIB_0_01_CLK_H,
RX_10_NIB_0_02_CLK_H,
RX_10_NIB_0_03_CLK_H,
RX_10_NIB_0_04_CLK_H,
RX_10_NIB_0_05_CLK_H,
RX_10_NIB_0_06_CLK_H,
RX_10_NIB_0_07_CLK_H,
RX_10_NIB_0_08_CLK_H,
RX_10_NIB_0_09_CLK_H,
RX_10_NIB_1_00_CLK_L,
RX_10_NIB_1_01_CLK_L,
RX_10_NIB_1_02_CLK_L,
RX_10_NIB_1_03_CLK_L,
RX_10_NIB_1_04_CLK_L,
RX_10_NIB_1_05_CLK_L,
RX_10_NIB_1_06_CLK_L,
RX_10_NIB_1_07_CLK_L,
RX_10_NIB_1_08_CLK_L,
RX_10_NIB_1_09_CLK_L,
RX_10_NIB_1_00_CLK_H,
RX_10_NIB_1_01_CLK_H,
RX_10_NIB_1_02_CLK_H,
RX_10_NIB_1_03_CLK_H,
RX_10_NIB_1_04_CLK_H,
RX_10_NIB_1_05_CLK_H,
RX_10_NIB_1_06_CLK_H,
RX_10_NIB_1_07_CLK_H,
RX_10_NIB_1_08_CLK_H,
RX_10_NIB_1_09_CLK_H,
RX_10_NIB_1_09_RD_FIFO_CLK_H
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
begin
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
-- No Concurrent Signal Assignments
------------------------------------------------------------------------------
-- State Machine SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_ClK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine NEXT_STATE_PROCESS
------------------------------------------------------------------------------
NEXT_STATE_PROCESS : process (
present_state,
Rx_100,
Rx_10,
RMII_rx_EOP,
Rmii_rx_er,
Rmii_rx_crs,
Rmii_rx_dv,
Rmii_rx_data,
Rx_fifo_mt_n--new addition of signal
)
begin
case present_state is
when IDLE_ClK_L =>
if (Rx_100 = '1') then
next_state <= RX_100_RD_FIFO_ClK_L;
elsif (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when IDLE_ClK_H =>
if (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_L;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_RD_FIFO_ClK_L =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_NIB_0_CLK_L =>
next_state <= RX_100_NIB_0_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_0_CLK_H =>
next_state <= RX_100_NIB_1_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_1_CLK_L =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1')) then
next_state <= RX_100_NIB_1_CLK_H;
else
next_state <= RX_100_NIB_1_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_RD_FIFO_CLK_H =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_RD_FIFO_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_10_NIB_0_00_CLK_L =>
next_state <= RX_10_NIB_0_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_L =>
next_state <= RX_10_NIB_0_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_L =>
next_state <= RX_10_NIB_0_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_L =>
next_state <= RX_10_NIB_0_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_L =>
next_state <= RX_10_NIB_0_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_L =>
next_state <= RX_10_NIB_0_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_L =>
next_state <= RX_10_NIB_0_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_L =>
next_state <= RX_10_NIB_0_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_L =>
next_state <= RX_10_NIB_0_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_00_CLK_H =>
next_state <= RX_10_NIB_0_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_H =>
next_state <= RX_10_NIB_0_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_H =>
next_state <= RX_10_NIB_0_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_H =>
next_state <= RX_10_NIB_0_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_H =>
next_state <= RX_10_NIB_0_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_H =>
next_state <= RX_10_NIB_0_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_H =>
next_state <= RX_10_NIB_0_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_H =>
next_state <= RX_10_NIB_0_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_H =>
next_state <= RX_10_NIB_0_09_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_H =>
next_state <= RX_10_NIB_1_00_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_1_00_CLK_L =>
next_state <= RX_10_NIB_1_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_L =>
next_state <= RX_10_NIB_1_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_L =>
next_state <= RX_10_NIB_1_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_L =>
next_state <= RX_10_NIB_1_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_L =>
next_state <= RX_10_NIB_1_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_L =>
next_state <= RX_10_NIB_1_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_L =>
next_state <= RX_10_NIB_1_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_L =>
next_state <= RX_10_NIB_1_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_L =>
next_state <= RX_10_NIB_1_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_L =>
next_state <= RX_10_NIB_1_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_00_CLK_H =>
next_state <= RX_10_NIB_1_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_H =>
next_state <= RX_10_NIB_1_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_H =>
next_state <= RX_10_NIB_1_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_H =>
next_state <= RX_10_NIB_1_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_H =>
next_state <= RX_10_NIB_1_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_H =>
next_state <= RX_10_NIB_1_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_H =>
next_state <= RX_10_NIB_1_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_H =>
next_state <= RX_10_NIB_1_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_H =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1') or (Rx_fifo_mt_n = '0')) then
next_state <= RX_10_NIB_1_09_CLK_H;
else
next_state <= RX_10_NIB_1_09_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_RD_FIFO_CLK_H =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
end case;
end process;
end simulation;
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo_disposer.vhd
--
-- Version: v1.01.a
-- Description: This
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo_disposer is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_10 : in std_logic;
Rx_100 : in std_logic;
Rmii_rx_eop : in std_logic_vector(1 downto 0);
Rmii_rx_crs : in std_logic_vector(1 downto 0);
Rmii_rx_er : in std_logic_vector(1 downto 0);
Rmii_rx_dv : in std_logic_vector(1 downto 0);
Rmii_rx_data : in std_logic_vector(7 downto 0);
Rx_fifo_mt_n : in std_logic;
Rx_fifo_rd_en : out std_logic;
Rmii2mac_crs : out std_logic;
Rmii2mac_rx_clk : out std_logic;
Rmii2mac_rx_er : out std_logic;
Rmii2mac_rx_dv : out std_logic;
Rmii2mac_rxd : out std_logic_vector(3 downto 0)
);
end rx_fifo_disposer;
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_RESET_ACTIVE -- Assertion level for Reset signal.
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo_disposer is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
-- Signal names begin with a lowercase letter. User defined types and the
-- enumerated values with a type are all uppercase letters.
-- Signals of a user-defined type should be declared after the type declaration
-- Group signals by interfaces
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_ClK_L,
IDLE_ClK_H,
RX_100_RD_FIFO_ClK_L,
RX_100_NIB_0_CLK_L,
RX_100_NIB_0_CLK_H,
RX_100_NIB_1_CLK_L,
RX_100_NIB_1_CLK_H,
RX_100_NIB_1_RD_FIFO_CLK_H,
RX_10_RD_FIFO_CLK_L,
RX_10_NIB_0_00_CLK_L,
RX_10_NIB_0_01_CLK_L,
RX_10_NIB_0_02_CLK_L,
RX_10_NIB_0_03_CLK_L,
RX_10_NIB_0_04_CLK_L,
RX_10_NIB_0_05_CLK_L,
RX_10_NIB_0_06_CLK_L,
RX_10_NIB_0_07_CLK_L,
RX_10_NIB_0_08_CLK_L,
RX_10_NIB_0_09_CLK_L,
RX_10_NIB_0_00_CLK_H,
RX_10_NIB_0_01_CLK_H,
RX_10_NIB_0_02_CLK_H,
RX_10_NIB_0_03_CLK_H,
RX_10_NIB_0_04_CLK_H,
RX_10_NIB_0_05_CLK_H,
RX_10_NIB_0_06_CLK_H,
RX_10_NIB_0_07_CLK_H,
RX_10_NIB_0_08_CLK_H,
RX_10_NIB_0_09_CLK_H,
RX_10_NIB_1_00_CLK_L,
RX_10_NIB_1_01_CLK_L,
RX_10_NIB_1_02_CLK_L,
RX_10_NIB_1_03_CLK_L,
RX_10_NIB_1_04_CLK_L,
RX_10_NIB_1_05_CLK_L,
RX_10_NIB_1_06_CLK_L,
RX_10_NIB_1_07_CLK_L,
RX_10_NIB_1_08_CLK_L,
RX_10_NIB_1_09_CLK_L,
RX_10_NIB_1_00_CLK_H,
RX_10_NIB_1_01_CLK_H,
RX_10_NIB_1_02_CLK_H,
RX_10_NIB_1_03_CLK_H,
RX_10_NIB_1_04_CLK_H,
RX_10_NIB_1_05_CLK_H,
RX_10_NIB_1_06_CLK_H,
RX_10_NIB_1_07_CLK_H,
RX_10_NIB_1_08_CLK_H,
RX_10_NIB_1_09_CLK_H,
RX_10_NIB_1_09_RD_FIFO_CLK_H
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
begin
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
-- No Concurrent Signal Assignments
------------------------------------------------------------------------------
-- State Machine SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_ClK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine NEXT_STATE_PROCESS
------------------------------------------------------------------------------
NEXT_STATE_PROCESS : process (
present_state,
Rx_100,
Rx_10,
RMII_rx_EOP,
Rmii_rx_er,
Rmii_rx_crs,
Rmii_rx_dv,
Rmii_rx_data,
Rx_fifo_mt_n--new addition of signal
)
begin
case present_state is
when IDLE_ClK_L =>
if (Rx_100 = '1') then
next_state <= RX_100_RD_FIFO_ClK_L;
elsif (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when IDLE_ClK_H =>
if (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_L;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_RD_FIFO_ClK_L =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_NIB_0_CLK_L =>
next_state <= RX_100_NIB_0_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_0_CLK_H =>
next_state <= RX_100_NIB_1_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_1_CLK_L =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1')) then
next_state <= RX_100_NIB_1_CLK_H;
else
next_state <= RX_100_NIB_1_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_RD_FIFO_CLK_H =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_RD_FIFO_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_10_NIB_0_00_CLK_L =>
next_state <= RX_10_NIB_0_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_L =>
next_state <= RX_10_NIB_0_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_L =>
next_state <= RX_10_NIB_0_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_L =>
next_state <= RX_10_NIB_0_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_L =>
next_state <= RX_10_NIB_0_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_L =>
next_state <= RX_10_NIB_0_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_L =>
next_state <= RX_10_NIB_0_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_L =>
next_state <= RX_10_NIB_0_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_L =>
next_state <= RX_10_NIB_0_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_00_CLK_H =>
next_state <= RX_10_NIB_0_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_H =>
next_state <= RX_10_NIB_0_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_H =>
next_state <= RX_10_NIB_0_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_H =>
next_state <= RX_10_NIB_0_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_H =>
next_state <= RX_10_NIB_0_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_H =>
next_state <= RX_10_NIB_0_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_H =>
next_state <= RX_10_NIB_0_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_H =>
next_state <= RX_10_NIB_0_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_H =>
next_state <= RX_10_NIB_0_09_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_H =>
next_state <= RX_10_NIB_1_00_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_1_00_CLK_L =>
next_state <= RX_10_NIB_1_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_L =>
next_state <= RX_10_NIB_1_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_L =>
next_state <= RX_10_NIB_1_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_L =>
next_state <= RX_10_NIB_1_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_L =>
next_state <= RX_10_NIB_1_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_L =>
next_state <= RX_10_NIB_1_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_L =>
next_state <= RX_10_NIB_1_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_L =>
next_state <= RX_10_NIB_1_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_L =>
next_state <= RX_10_NIB_1_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_L =>
next_state <= RX_10_NIB_1_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_00_CLK_H =>
next_state <= RX_10_NIB_1_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_H =>
next_state <= RX_10_NIB_1_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_H =>
next_state <= RX_10_NIB_1_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_H =>
next_state <= RX_10_NIB_1_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_H =>
next_state <= RX_10_NIB_1_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_H =>
next_state <= RX_10_NIB_1_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_H =>
next_state <= RX_10_NIB_1_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_H =>
next_state <= RX_10_NIB_1_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_H =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1') or (Rx_fifo_mt_n = '0')) then
next_state <= RX_10_NIB_1_09_CLK_H;
else
next_state <= RX_10_NIB_1_09_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_RD_FIFO_CLK_H =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
end case;
end process;
end simulation;
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo_disposer.vhd
--
-- Version: v1.01.a
-- Description: This
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo_disposer is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_10 : in std_logic;
Rx_100 : in std_logic;
Rmii_rx_eop : in std_logic_vector(1 downto 0);
Rmii_rx_crs : in std_logic_vector(1 downto 0);
Rmii_rx_er : in std_logic_vector(1 downto 0);
Rmii_rx_dv : in std_logic_vector(1 downto 0);
Rmii_rx_data : in std_logic_vector(7 downto 0);
Rx_fifo_mt_n : in std_logic;
Rx_fifo_rd_en : out std_logic;
Rmii2mac_crs : out std_logic;
Rmii2mac_rx_clk : out std_logic;
Rmii2mac_rx_er : out std_logic;
Rmii2mac_rx_dv : out std_logic;
Rmii2mac_rxd : out std_logic_vector(3 downto 0)
);
end rx_fifo_disposer;
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_RESET_ACTIVE -- Assertion level for Reset signal.
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo_disposer is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
-- Signal names begin with a lowercase letter. User defined types and the
-- enumerated values with a type are all uppercase letters.
-- Signals of a user-defined type should be declared after the type declaration
-- Group signals by interfaces
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_ClK_L,
IDLE_ClK_H,
RX_100_RD_FIFO_ClK_L,
RX_100_NIB_0_CLK_L,
RX_100_NIB_0_CLK_H,
RX_100_NIB_1_CLK_L,
RX_100_NIB_1_CLK_H,
RX_100_NIB_1_RD_FIFO_CLK_H,
RX_10_RD_FIFO_CLK_L,
RX_10_NIB_0_00_CLK_L,
RX_10_NIB_0_01_CLK_L,
RX_10_NIB_0_02_CLK_L,
RX_10_NIB_0_03_CLK_L,
RX_10_NIB_0_04_CLK_L,
RX_10_NIB_0_05_CLK_L,
RX_10_NIB_0_06_CLK_L,
RX_10_NIB_0_07_CLK_L,
RX_10_NIB_0_08_CLK_L,
RX_10_NIB_0_09_CLK_L,
RX_10_NIB_0_00_CLK_H,
RX_10_NIB_0_01_CLK_H,
RX_10_NIB_0_02_CLK_H,
RX_10_NIB_0_03_CLK_H,
RX_10_NIB_0_04_CLK_H,
RX_10_NIB_0_05_CLK_H,
RX_10_NIB_0_06_CLK_H,
RX_10_NIB_0_07_CLK_H,
RX_10_NIB_0_08_CLK_H,
RX_10_NIB_0_09_CLK_H,
RX_10_NIB_1_00_CLK_L,
RX_10_NIB_1_01_CLK_L,
RX_10_NIB_1_02_CLK_L,
RX_10_NIB_1_03_CLK_L,
RX_10_NIB_1_04_CLK_L,
RX_10_NIB_1_05_CLK_L,
RX_10_NIB_1_06_CLK_L,
RX_10_NIB_1_07_CLK_L,
RX_10_NIB_1_08_CLK_L,
RX_10_NIB_1_09_CLK_L,
RX_10_NIB_1_00_CLK_H,
RX_10_NIB_1_01_CLK_H,
RX_10_NIB_1_02_CLK_H,
RX_10_NIB_1_03_CLK_H,
RX_10_NIB_1_04_CLK_H,
RX_10_NIB_1_05_CLK_H,
RX_10_NIB_1_06_CLK_H,
RX_10_NIB_1_07_CLK_H,
RX_10_NIB_1_08_CLK_H,
RX_10_NIB_1_09_CLK_H,
RX_10_NIB_1_09_RD_FIFO_CLK_H
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
begin
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
-- No Concurrent Signal Assignments
------------------------------------------------------------------------------
-- State Machine SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_ClK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine NEXT_STATE_PROCESS
------------------------------------------------------------------------------
NEXT_STATE_PROCESS : process (
present_state,
Rx_100,
Rx_10,
RMII_rx_EOP,
Rmii_rx_er,
Rmii_rx_crs,
Rmii_rx_dv,
Rmii_rx_data,
Rx_fifo_mt_n--new addition of signal
)
begin
case present_state is
when IDLE_ClK_L =>
if (Rx_100 = '1') then
next_state <= RX_100_RD_FIFO_ClK_L;
elsif (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when IDLE_ClK_H =>
if (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_L;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_RD_FIFO_ClK_L =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_NIB_0_CLK_L =>
next_state <= RX_100_NIB_0_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_0_CLK_H =>
next_state <= RX_100_NIB_1_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_1_CLK_L =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1')) then
next_state <= RX_100_NIB_1_CLK_H;
else
next_state <= RX_100_NIB_1_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_RD_FIFO_CLK_H =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_RD_FIFO_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_10_NIB_0_00_CLK_L =>
next_state <= RX_10_NIB_0_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_L =>
next_state <= RX_10_NIB_0_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_L =>
next_state <= RX_10_NIB_0_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_L =>
next_state <= RX_10_NIB_0_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_L =>
next_state <= RX_10_NIB_0_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_L =>
next_state <= RX_10_NIB_0_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_L =>
next_state <= RX_10_NIB_0_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_L =>
next_state <= RX_10_NIB_0_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_L =>
next_state <= RX_10_NIB_0_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_00_CLK_H =>
next_state <= RX_10_NIB_0_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_H =>
next_state <= RX_10_NIB_0_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_H =>
next_state <= RX_10_NIB_0_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_H =>
next_state <= RX_10_NIB_0_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_H =>
next_state <= RX_10_NIB_0_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_H =>
next_state <= RX_10_NIB_0_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_H =>
next_state <= RX_10_NIB_0_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_H =>
next_state <= RX_10_NIB_0_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_H =>
next_state <= RX_10_NIB_0_09_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_H =>
next_state <= RX_10_NIB_1_00_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_1_00_CLK_L =>
next_state <= RX_10_NIB_1_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_L =>
next_state <= RX_10_NIB_1_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_L =>
next_state <= RX_10_NIB_1_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_L =>
next_state <= RX_10_NIB_1_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_L =>
next_state <= RX_10_NIB_1_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_L =>
next_state <= RX_10_NIB_1_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_L =>
next_state <= RX_10_NIB_1_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_L =>
next_state <= RX_10_NIB_1_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_L =>
next_state <= RX_10_NIB_1_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_L =>
next_state <= RX_10_NIB_1_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_00_CLK_H =>
next_state <= RX_10_NIB_1_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_H =>
next_state <= RX_10_NIB_1_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_H =>
next_state <= RX_10_NIB_1_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_H =>
next_state <= RX_10_NIB_1_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_H =>
next_state <= RX_10_NIB_1_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_H =>
next_state <= RX_10_NIB_1_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_H =>
next_state <= RX_10_NIB_1_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_H =>
next_state <= RX_10_NIB_1_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_H =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1') or (Rx_fifo_mt_n = '0')) then
next_state <= RX_10_NIB_1_09_CLK_H;
else
next_state <= RX_10_NIB_1_09_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_RD_FIFO_CLK_H =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
end case;
end process;
end simulation;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_4 is
port(
clock : in std_logic;
--clock_vga : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0);
--VGA_hs : out std_logic; -- horisontal vga syncr.
-- VGA_vs : out std_logic; -- vertical vga syncr.
--iter : out std_logic_vector(3 downto 0) -- red output
data_write :out std_logic;
ADDR : out std_logic_vector(16 downto 0);
data_out : out std_logic_vector(11 downto 0)
-- VGA_green : out std_logic_vector(3 downto 0); -- green output
-- VGA_blue : out std_logic_vector(3 downto 0) -- blue output
);
end; --comb_alu_1
architecture logic of coproc_4 is
SIGNAL mem : UNSIGNED(31 downto 0);
signal tmp_addr : std_logic_vector(16 downto 0);
signal pixel : std_logic_vector(11 downto 0);
--signal tmp_out : std_logic_vector(10 downto 0);
signal counter : integer range 0 to 76799:= 0;
begin
--tmp_addr <= INPUT_1(31 downto 13);
--pixel <= INPUT_1(7 downto 0);
--
process (clock)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
counter <= 0;
ELSE
IF INPUT_1_valid = '1' THEN
IF counter < 76799 THEN
counter <= counter + 1;
ELSE
counter <= 0;
END IF;
END IF;
END IF;
END IF;
end process;
--
--
-- process (clock, reset)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- tmp_addr <= (others => '1');
-- pixel <= (others => '0');
-- data_write <= '0';
-- ELSE
-- IF INPUT_1_valid = '1' THEN
-- tmp_addr <= INPUT_1(31 downto 13);
-- pixel <= INPUT_1(7 downto 0);
-- data_write <= '1';
-- else
-- data_write <= '0';
-- END IF;
-- END IF;
-- END IF;
-- end process;
--
tmp_addr <= std_logic_vector(to_signed(counter, 17));
--
data_write <=INPUT_1_valid;
data_out <=INPUT_1(11 downto 0);
ADDR <= tmp_addr;
OUTPUT_1 <= "000000000000000"&tmp_addr;
-- process (clock)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- mem <= TO_UNSIGNED( 0, 32);
-- ELSE
-- IF INPUT_1_valid = '1' THEN
---- assert INPUT_1_valid /= '1' severity failure;
-- mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 3, 32);
-- ELSE
-- mem <= mem;
-- END IF;
-- END IF;
-- END IF;
-- end process;
-------------------------------------------------------------------------
-- OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
-------------------------------------------------------------------------
-- process (clock, reset)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- mem <= TO_UNSIGNED( 0, 32);
-- ELSE
-- IF INPUT_1_valid = '1' THEN
-- mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 4, 32);
-- ELSE
-- mem <= mem;
-- END IF;
-- END IF;
-- END IF;
-- end process;
-- -------------------------------------------------------------------------
--
-- OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
end; --architecture logic
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2016 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
entity tb_soc_uart is
end entity tb_soc_uart;
architecture testbench of tb_soc_uart is
-- Clock signal:
signal clk : std_logic := '0';
constant clk_period : time := 10 ns;
-- Reset signal:
signal reset : std_logic := '1';
-- UART ports:
signal txd : std_logic;
signal rxd : std_logic := '1';
-- interrupt signals:
signal irq : std_logic;
-- Wishbone ports:
signal wb_adr_in : std_logic_vector(11 downto 0) := (others => '0');
signal wb_dat_in : std_logic_vector( 7 downto 0) := (others => '0');
signal wb_dat_out : std_logic_vector( 7 downto 0);
signal wb_we_in : std_logic := '0';
signal wb_cyc_in : std_logic := '0';
signal wb_stb_in : std_logic := '0';
signal wb_ack_out : std_logic;
begin
uut: entity work.pp_soc_uart
port map(
clk => clk,
reset => reset,
txd => txd,
rxd => rxd,
irq => irq,
wb_adr_in => wb_adr_in,
wb_dat_in => wb_dat_in,
wb_dat_out => wb_dat_out,
wb_we_in => wb_we_in,
wb_cyc_in => wb_cyc_in,
wb_stb_in => wb_stb_in,
wb_ack_out => wb_ack_out
);
clock: process
begin
clk <= '1';
wait for clk_period / 2;
clk <= '0';
wait for clk_period / 2;
end process clock;
stimulus: process
procedure uart_write(address : in std_logic_vector(11 downto 0); data : in std_logic_vector(7 downto 0)) is
begin
wb_adr_in <= address;
wb_dat_in <= data;
wb_we_in <= '1';
wb_cyc_in <= '1';
wb_stb_in <= '1';
wait until wb_ack_out = '1';
wait for clk_period;
wb_stb_in <= '0';
wb_cyc_in <= '0';
wait for clk_period;
end procedure uart_write;
begin
wait for clk_period * 2;
reset <= '0';
-- Set the sample clock to obtain a 1 Mbps transfer rate:
uart_write(x"00c", x"06");
-- Enable the data received interrupt:
uart_write(x"010", x"01");
-- Send a byte on the UART:
rxd <= '0'; -- Start bit
wait for 1 us;
rxd <= '0';
wait for 1 us;
rxd <= '1';
wait for 1 us;
rxd <= '0';
wait for 1 us;
rxd <= '1';
wait for 1 us;
rxd <= '0';
wait for 1 us;
rxd <= '0';
wait for 1 us;
rxd <= '0';
wait for 1 us;
rxd <= '0';
wait for 1 us;
rxd <= '1'; -- Stop bit
wait for 1 us;
wait until irq = '1';
-- Disable the IRQ:
uart_write(x"010", x"00");
wait until irq = '0';
-- Output a "Potato" on the UART:
uart_write(x"000", x"50");
uart_write(x"000", x"6f");
uart_write(x"000", x"74");
uart_write(x"000", x"61");
uart_write(x"000", x"74");
uart_write(x"000", x"6f");
wait;
end process stimulus;
end architecture testbench;
|
architecture rtl of fifo is
type t_some_record is record
element_1 : natural;
some_other_element : natural;
yet_another_element : natural;
end record;
--Violations below
type t_some_record is record
element_1 : natural;
some_other_element : natural;
yet_another_element : natural;
end record;
type t_some_record is record
element_1 : natural;
some_other_element : natural;
yet_another_element : natural;
end record;
begin
end architecture rtl;
|
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T65_Pack is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
component T65_MCode
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out std_logic_vector(3 downto 0);
Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end component;
component T65_ALU
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end component;
end;
|
-- $Id: pdp11_psr.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_psr - syn
-- Description: pdp11: processor status word register
--
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 use ib_sel
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented)
-- 2008-08-22 161 1.1.3 rename ubf_ -> ibf_; use iblib
-- 2008-03-02 121 1.1.2 remove snoopers
-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_psr is -- processor status word register
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
DIN : in slv16; -- input data
CCIN : in slv4; -- cc input
CCWE : in slbit; -- enable update cc
WE : in slbit; -- write enable (from DIN)
FUNC : in slv3; -- write function (from DIN)
PSW : out psw_type; -- current psw
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_psr;
architecture syn of pdp11_psr is
constant ibaddr_psr : slv16 := slv(to_unsigned(8#177776#,16));
signal IBSEL_PSR : slbit := '0';
signal R_PSW : psw_type := psw_init; -- ps register
begin
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_psr)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_PSR
);
proc_ibres: process (IBSEL_PSR, IB_MREQ, R_PSW)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_PSR = '1' then
idout(psw_ibf_cmode) := R_PSW.cmode;
idout(psw_ibf_pmode) := R_PSW.pmode;
idout(psw_ibf_rset) := R_PSW.rset;
idout(psw_ibf_pri) := R_PSW.pri;
idout(psw_ibf_tflag) := R_PSW.tflag;
idout(psw_ibf_cc) := R_PSW.cc;
end if;
IB_SRES.dout <= idout;
IB_SRES.ack <= IBSEL_PSR and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
proc_psw : process (CLK)
begin
if rising_edge(CLK) then
if CRESET = '1' then
R_PSW <= psw_init;
else
if CCWE = '1' then
R_PSW.cc <= CCIN;
end if;
if WE = '1' then
case FUNC is
when c_psr_func_wspl => -- wspl
R_PSW.pri <= DIN(2 downto 0);
when c_psr_func_wcc => -- wcc
if DIN(4) = '1' then -- set cc opcodes
R_PSW.cc <= R_PSW.cc or DIN(3 downto 0);
else -- clear cc opcodes
R_PSW.cc <= R_PSW.cc and not DIN(3 downto 0);
end if;
when c_psr_func_wint => -- wint (interupt handling)
R_PSW.cmode <= DIN(psw_ibf_cmode);
R_PSW.pmode <= R_PSW.cmode; -- save current mode
R_PSW.rset <= DIN(psw_ibf_rset);
R_PSW.pri <= DIN(psw_ibf_pri);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
when c_psr_func_wrti => -- wrti (rti/rtt in non-kernel mode)
R_PSW.cmode <= R_PSW.cmode or DIN(psw_ibf_cmode);
R_PSW.pmode <= R_PSW.pmode or DIN(psw_ibf_pmode) or
R_PSW.cmode or DIN(psw_ibf_cmode);
R_PSW.rset <= R_PSW.rset or DIN(psw_ibf_rset);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
when c_psr_func_wall => -- wall (rti/rtt kernel mode)
R_PSW.cmode <= DIN(psw_ibf_cmode);
R_PSW.pmode <= DIN(psw_ibf_pmode);
R_PSW.rset <= DIN(psw_ibf_rset);
R_PSW.pri <= DIN(psw_ibf_pri);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
when others => null;
end case;
end if;
end if;
if IBSEL_PSR='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
R_PSW.cmode <= IB_MREQ.din(psw_ibf_cmode);
R_PSW.pmode <= IB_MREQ.din(psw_ibf_pmode);
R_PSW.rset <= IB_MREQ.din(psw_ibf_rset);
end if;
if IB_MREQ.be0 = '1' then
R_PSW.pri <= IB_MREQ.din(psw_ibf_pri);
R_PSW.cc <= IB_MREQ.din(psw_ibf_cc);
end if;
end if;
end if;
end process proc_psw;
PSW <= R_PSW;
end syn;
|
-- $Id: pdp11_psr.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_psr - syn
-- Description: pdp11: processor status word register
--
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 use ib_sel
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented)
-- 2008-08-22 161 1.1.3 rename ubf_ -> ibf_; use iblib
-- 2008-03-02 121 1.1.2 remove snoopers
-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_psr is -- processor status word register
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
DIN : in slv16; -- input data
CCIN : in slv4; -- cc input
CCWE : in slbit; -- enable update cc
WE : in slbit; -- write enable (from DIN)
FUNC : in slv3; -- write function (from DIN)
PSW : out psw_type; -- current psw
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_psr;
architecture syn of pdp11_psr is
constant ibaddr_psr : slv16 := slv(to_unsigned(8#177776#,16));
signal IBSEL_PSR : slbit := '0';
signal R_PSW : psw_type := psw_init; -- ps register
begin
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_psr)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_PSR
);
proc_ibres: process (IBSEL_PSR, IB_MREQ, R_PSW)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_PSR = '1' then
idout(psw_ibf_cmode) := R_PSW.cmode;
idout(psw_ibf_pmode) := R_PSW.pmode;
idout(psw_ibf_rset) := R_PSW.rset;
idout(psw_ibf_pri) := R_PSW.pri;
idout(psw_ibf_tflag) := R_PSW.tflag;
idout(psw_ibf_cc) := R_PSW.cc;
end if;
IB_SRES.dout <= idout;
IB_SRES.ack <= IBSEL_PSR and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
proc_psw : process (CLK)
begin
if rising_edge(CLK) then
if CRESET = '1' then
R_PSW <= psw_init;
else
if CCWE = '1' then
R_PSW.cc <= CCIN;
end if;
if WE = '1' then
case FUNC is
when c_psr_func_wspl => -- wspl
R_PSW.pri <= DIN(2 downto 0);
when c_psr_func_wcc => -- wcc
if DIN(4) = '1' then -- set cc opcodes
R_PSW.cc <= R_PSW.cc or DIN(3 downto 0);
else -- clear cc opcodes
R_PSW.cc <= R_PSW.cc and not DIN(3 downto 0);
end if;
when c_psr_func_wint => -- wint (interupt handling)
R_PSW.cmode <= DIN(psw_ibf_cmode);
R_PSW.pmode <= R_PSW.cmode; -- save current mode
R_PSW.rset <= DIN(psw_ibf_rset);
R_PSW.pri <= DIN(psw_ibf_pri);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
when c_psr_func_wrti => -- wrti (rti/rtt in non-kernel mode)
R_PSW.cmode <= R_PSW.cmode or DIN(psw_ibf_cmode);
R_PSW.pmode <= R_PSW.pmode or DIN(psw_ibf_pmode) or
R_PSW.cmode or DIN(psw_ibf_cmode);
R_PSW.rset <= R_PSW.rset or DIN(psw_ibf_rset);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
when c_psr_func_wall => -- wall (rti/rtt kernel mode)
R_PSW.cmode <= DIN(psw_ibf_cmode);
R_PSW.pmode <= DIN(psw_ibf_pmode);
R_PSW.rset <= DIN(psw_ibf_rset);
R_PSW.pri <= DIN(psw_ibf_pri);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
when others => null;
end case;
end if;
end if;
if IBSEL_PSR='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
R_PSW.cmode <= IB_MREQ.din(psw_ibf_cmode);
R_PSW.pmode <= IB_MREQ.din(psw_ibf_pmode);
R_PSW.rset <= IB_MREQ.din(psw_ibf_rset);
end if;
if IB_MREQ.be0 = '1' then
R_PSW.pri <= IB_MREQ.din(psw_ibf_pri);
R_PSW.cc <= IB_MREQ.din(psw_ibf_cc);
end if;
end if;
end if;
end process proc_psw;
PSW <= R_PSW;
end syn;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:40:45 08/31/2016
-- Design Name:
-- Module Name: /home/arthur/Documents/SD_SS/rel/3/projetos/aula3/complemento4_teste.vhd
-- Project Name: aula3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: complemento4
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY complemento4_teste IS
END complemento4_teste;
ARCHITECTURE behavior OF complemento4_teste IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT complemento4
PORT(
entrada : IN std_logic_vector(3 downto 0);
sel : IN std_logic;
saida : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal entrada : std_logic_vector(3 downto 0) := (others => '0');
signal sel : std_logic := '0';
--Outputs
signal saida : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: complemento4 PORT MAP (
entrada => entrada,
sel => sel,
saida => saida
);
-- Clock process definitions
<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for <clock>_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 11;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 1;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 8;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 1;
-- implement global atomic operations
constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant MAX_FPU_DELAY : integer := FSQRT_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 4;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_ok_5_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_ok_5_e-e.vhd,v 1.1 2006/11/22 10:40:10 wig Exp $
-- $Date: 2006/11/22 10:40:10 $
-- $Log: inst_shadow_ok_5_e-e.vhd,v $
-- Revision 1.1 2006/11/22 10:40:10 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_shadow_ok_5_e
--
entity inst_shadow_ok_5_e is
-- Generics:
-- No Generated Generics for Entity inst_shadow_ok_5_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_shadow_ok_5_e
end inst_shadow_ok_5_e;
--
-- End of Generated Entity inst_shadow_ok_5_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity registrador_mensagem is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
jogador_vencedor : in std_logic;
empate : in std_logic;
saida : out std_logic_vector(48 downto 0)
);
end registrador_mensagem;
architecture comportamental of registrador_mensagem is
signal s_vitoria: std_logic_vector(48 downto 0) := "1010110110100111101001101111111001011010011100001"; -- mensagem "vitoria"
signal s_derrota: std_logic_vector(48 downto 0) := "1000100110010111100101110010110111111101001100001"; -- mensagem "derrota"
signal s_empate : std_logic_vector(48 downto 0) := "1000101110110111100001100001111010011001010100000"; -- mensagem "empate "
begin
process(clock, reset, empate, jogador_vencedor)
begin
if reset='1' then
saida <= "0100000010000001000000100000010000001000000100000"; -- saida recebe 7 caracteres 'espaco'
elsif clock'event and clock='1' then
if enable='1' then
if empate='1' then
saida <= s_empate; -- saida recebe a palavra 'empate' + 1 caractere 'espaco'
elsif jogador_vencedor='0' then
saida <= s_vitoria; -- saida recebe a palavra 'vitoria'
else
saida <= s_derrota; -- saida recebe a palavra 'derrota'
end if;
end if;
end if;
end process;
end comportamental;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:48:09 02/19/2017
-- Design Name:
-- Module Name: tinycpu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use work.tinycpu_common.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tinycpu is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
a : out STD_LOGIC_VECTOR (9 downto 0);
i : in STD_LOGIC_VECTOR (7 downto 0);
io_data : inout STD_LOGIC_VECTOR (3 downto 0);
nIo_read : buffer STD_LOGIC;
nIo_write : buffer STD_LOGIC;
io_address : buffer STD_LOGIC_VECTOR (3 downto 0);
status : out STD_LOGIC_VECTOR (7 downto 0);
step: in STD_LOGIC;
debug_port : out STD_LOGIC_VECTOR (15 downto 0));
end tinycpu;
architecture Behavioral of tinycpu is
component gal_datamux is
Port ( i : in STD_LOGIC_VECTOR (7 downto 0);
data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (3 downto 0);
nRead : out STD_LOGIC;
nWrite : out STD_LOGIC);
end component;
component gal_instrmapper is
Port ( macro_i : in STD_LOGIC_VECTOR (7 downto 0);
execute : in STD_LOGIC;
micro_i : out STD_LOGIC_VECTOR (9 downto 0));
end component;
component gal_indexreg is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
sel : in STD_LOGIC;
macro_i : in STD_LOGIC_VECTOR (7 downto 0);
data: in STD_LOGIC_VECTOR(3 downto 0);
index : out STD_LOGIC_VECTOR (3 downto 0);
isZero : out STD_LOGIC);
end component;
component gal_brancher is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
i : in STD_LOGIC_VECTOR (7 downto 0);
condition : in STD_LOGIC_VECTOR (7 downto 0);
execute : buffer STD_LOGIC;
branch : buffer STD_LOGIC;
callorreturn: buffer STD_LOGIC);
end component;
component gal_progcounter is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
macro_i : in STD_LOGIC_VECTOR (7 downto 0);
execute : in STD_LOGIC;
branch : in STD_LOGIC;
callorreturn: in STD_LOGIC;
pc : buffer STD_LOGIC_VECTOR (9 downto 0));
end component;
component gal_conditionreg is
Port ( clock : in STD_LOGIC;
execute : in STD_LOGIC;
i : in STD_LOGIC_VECTOR (7 downto 0);
alu_c : in STD_LOGIC;
alu_z : in STD_LOGIC;
alu_v : in STD_LOGIC;
alu_n : in STD_LOGIC;
alu_x3 : inout STD_LOGIC;
alu_x0 : inout STD_LOGIC;
flags : buffer STD_LOGIC_VECTOR (7 downto 0));
end component;
component gal_glue is
Port (
reset: in STD_LOGIC;
clock: in STD_LOGIC;
i : in STD_LOGIC_VECTOR (7 downto 0);
nRead: in STD_LOGIC;
nWrite: in STD_LOGIC;
nIo_Read: out STD_LOGIC;
nIo_Write: out STD_LOGIC;
carry_in : in STD_LOGIC;
carry_out : out STD_LOGIC;
execute: in STD_LOGIC;
ss_mode: in STD_LOGIC;
step: in STD_LOGIC;
ss_clock: out STD_LOGIC);
end component;
component gal_addrmux is
Port ( i : in STD_LOGIC_VECTOR (7 downto 0);
addrA : in STD_LOGIC_VECTOR (3 downto 0);
addrB : in STD_LOGIC_VECTOR (3 downto 0);
addr_bus : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component am2901 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
a : in std_logic_vector (3 downto 0);----address inputs
b : in STD_LOGIC_VECTOR (3 downto 0);----address inputs
d : in STD_LOGIC_VECTOR (3 downto 0);----direct data
i : in STD_LOGIC_VECTOR (8 downto 0);---micro instruction
c_n : in STD_LOGIC;---------------------carry in
oe : in STD_LOGIC;----------------------output enable
ram0 : inout STD_LOGIC;-----------------shift lines to ram
ram3 : inout STD_LOGIC;-----------------shift lines to ram
qs0 : inout STD_LOGIC;------------------shift lines to q
qs3 : inout STD_LOGIC;------------------shift lines to q
y : inout STD_LOGIC_VECTOR (3 downto 0);-------data outputs(3-state)
g_bar : buffer STD_LOGIC;---------------carry generate
p_bar : buffer STD_LOGIC;---------------carry propagate
ovr : buffer STD_LOGIC;-----------------overflow
c_n4 : buffer STD_LOGIC;----------------carry out
f_0 : buffer STD_LOGIC;-----------------f = 0
f3 : buffer STD_LOGIC);-----------------f(3) w/o 3-state
end component;
signal pc: std_logic_vector(9 downto 0);
signal nRead, nWrite: std_logic := '1';
signal microinstruction: std_logic_vector(8 downto 0);
alias current_opcode: std_logic_vector(3 downto 0) is i(7 downto 4);
alias current_immediate: std_logic_vector(3 downto 0) is i(3 downto 0);
signal addrA, addrB: std_logic_vector(3 downto 0);
signal addrAIsZero, addrBIsZero: std_logic;
signal execute, callorreturn, branch: std_logic;
signal data_bus: std_logic_vector(3 downto 0);
signal addr_bus: std_logic_vector(3 downto 0);
signal flags: std_logic_vector(7 downto 0);
signal f_0: std_logic;
signal am2901_cin, am2901_cout, am2901_v, am2901_z, am2901_n, am2901_r3, am2901_r0: std_logic;
signal nOutputEnable: std_logic;
signal ss_clock: std_logic;
begin
-- connect i/o address
io_address <= addr_bus;
-- status outputs
status(4 downto 0) <= flags(4 downto 0); -- X N V Z C
--status(0) <= clock;
--status(1) <= flags(7);
--status(2) <= step;
--status(3) <= ss_clock;
status(5) <= branch;
status(6) <= execute;
status(7) <= flags(7); -- Single step
-- debug output
debug_port(2 downto 0) <= microinstruction(2 downto 0);
debug_port(3) <= '0';
debug_port(6 downto 4) <= microinstruction(5 downto 3);
debug_port(7) <= '0';
debug_port(10 downto 8) <= microinstruction(8 downto 6);
debug_port(15 downto 12) <= addr_bus;
-- f_0 is "open collector" but actually it implemented as tri-state or pull low
am2901_z <= '1' when f_0 = '0' else '0';
glue: gal_glue port map
(
reset => reset,
clock => clock,
i => i,
nRead => nRead,
nWrite => nWrite,
nIo_Read => nIo_Read,
nIo_Write => nIo_Write,
carry_in => flags(0), -- carry flag bit from status register
carry_out => am2901_cin, -- carry into Am2901
execute => execute,
ss_mode => flags(7),
step => step,
ss_clock => ss_clock
);
addrmux: gal_addrmux port map
(
i => i,
addrA => addrA,
addrB => addrB,
addr_bus => addr_bus
);
progcounter: gal_progcounter port map
(
reset => reset,
clock => ss_clock,
macro_i => i,
execute => execute,
branch => branch,
callorreturn => callorreturn,
pc => a
);
instrmapper: gal_instrmapper port map
(
macro_i => i,
execute => execute,
micro_i(8 downto 0) => microinstruction,
micro_i(9) => nOutputEnable
);
data_mux: gal_datamux port map
(
i => i,
data_in => io_data,
data_out => data_bus,
nRead => nRead,
nWrite => nWrite
);
indexreg_a: gal_indexreg port map
(
reset => reset,
clock => ss_clock,
sel => '0',
macro_i => i,
data => io_data,
index => addrA,
isZero => addrAisZero
);
indexreg_b: gal_indexreg port map
(
reset => reset,
clock => ss_clock,
sel => '1',
macro_i => i,
data => io_data,
index => addrB,
isZero => addrBIsZero
);
brancher: gal_brancher Port map
(
reset => reset,
clock => ss_clock,
i => i,
condition(0) => flags(0), --F0: C, F8: !C
condition(1) => flags(1), --F1: Z, F9: !Z
condition(2) => flags(2), --F2: V, FA: !V
condition(3) => flags(3), --F3: N, FB: !N
condition(4) => flags(4), --F4: X, FC: !X
condition(5) => addrAIsZero, --F5: A = 0, FD: A != 0
condition(6) => addrBIsZero, --F6: B = 0, FE: B != 0
condition(7) => '0', --F7: RETURN, FF: CALL
execute => execute,
branch => branch,
callorreturn => callorreturn
);
conditionreg: gal_conditionreg port map
(
clock => ss_clock,
execute => execute,
i => i,
alu_c => am2901_cout,
alu_z => am2901_z,
alu_v => am2901_v,
alu_n => am2901_n,
alu_x3 => am2901_r3,
alu_x0 => am2901_r0,
flags => flags
);
slice: am2901 port map
(
clk => ss_clock,
rst => reset,
a => addr_bus, --addrA,
b => addr_bus, --addrB,
d => data_bus, --io_data,
i => microinstruction(8 downto 0),
c_n => am2901_cin,
oe => nOutputEnable,
ram0 => am2901_r0,
ram3 => am2901_r3,
--qs0 => nc,
--qs3 => nc,
y => io_data,
--g_bar => nc,
--p_bar => nc,
ovr => am2901_v,
c_n4 => am2901_cout,
f_0 => f_0,
f3 => am2901_n
);-----------------f(3) w/o 3-state
end Behavioral;
|
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_n_to_1_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic n:1 transmitter module
-- Takes in n bits of data and serialises this to 1 bit
-- data is transmitted LSB first
-- Parallel input word
-- DS, DS-1 ..... 1, 0
-- Serial output words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Data inversion can be accomplished via the TX_SWAP_MASK
-- parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_n_to_1_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
gclk : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0) ; -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end serdes_n_to_1_s8_diff ;
architecture arch_serdes_n_to_1_s8_diff of serdes_n_to_1_s8_diff is
signal cascade_di : std_logic_vector(D-1 downto 0) ;
signal cascade_do : std_logic_vector(D-1 downto 0) ;
signal cascade_ti : std_logic_vector(D-1 downto 0) ;
signal cascade_to : std_logic_vector(D-1 downto 0) ;
signal mdataina : std_logic_vector(D*8 downto 0) ;
signal mdatainb : std_logic_vector(D*4 downto 0) ;
signal tx_data_out : std_logic_vector(D-1 downto 0) ;
constant TX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
loop0 : for i in 0 to (D - 1) generate
io_clk_out : obufds port map (
O => dataout_p(i),
OB => dataout_n(i),
I => tx_data_out(i));
loop1 : if (S > 4) generate -- Two oserdes are needed
loop2 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdataina((8*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i) ;
end generate ;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+7),
D3 => mdataina((8*i)+6),
D2 => mdataina((8*i)+5),
D1 => mdataina((8*i)+4),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- Dummy input in Master
SHIFTIN2 => '1', -- Dummy input in Master
SHIFTIN3 => cascade_do(i), -- Cascade output D data from slave
SHIFTIN4 => cascade_to(i), -- Cascade output T data from slave
SHIFTOUT1 => cascade_di(i), -- Cascade input D data to slave
SHIFTOUT2 => cascade_ti(i), -- Cascade input T data to slave
SHIFTOUT3 => open, -- Dummy output in Master
SHIFTOUT4 => open) ; -- Dummy output in Master
oserdes_s : OSERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => open,
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+3),
D3 => mdataina((8*i)+2),
D2 => mdataina((8*i)+1),
D1 => mdataina((8*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => cascade_di(i), -- Cascade input D from Master
SHIFTIN2 => cascade_ti(i), -- Cascade input T from Master
SHIFTIN3 => '1', -- Dummy input in Slave
SHIFTIN4 => '1', -- Dummy input in Slave
SHIFTOUT1 => open, -- Dummy output in Slave
SHIFTOUT2 => open, -- Dummy output in Slave
SHIFTOUT3 => cascade_do(i), -- Cascade output D data to Master
SHIFTOUT4 => cascade_to(i)) ; -- Cascade output T data to Master
end generate ;
loop3 : if (S < 5) generate -- Only one oserdes needed
loop4 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdatainb((4*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i) ;
end generate ;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR") -- <SDR>, DDR
-- SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
-- OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdatainb((4*i)+3),
D3 => mdatainb((4*i)+2),
D2 => mdatainb((4*i)+1),
D1 => mdatainb((4*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- No cascades needed
SHIFTIN2 => '1', -- No cascades needed
SHIFTIN3 => '1', -- No cascades needed
SHIFTIN4 => '1', -- No cascades needed
SHIFTOUT1 => open, -- No cascades needed
SHIFTOUT2 => open, -- No cascades needed
SHIFTOUT3 => open, -- No cascades needed
SHIFTOUT4 => open) ; -- No cascades needed
end generate ;
end generate ;
end arch_serdes_n_to_1_s8_diff ;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: system_monitor
-- File: system_monitor.vhd
-- Author: Jan Andersson, Jiri Gaisler - Gaisler Research
-- Description: System monitor wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity system_monitor is
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end system_monitor;
architecture struct of system_monitor is
component sysmon_virtex5
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
component sysmon
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_DEVICE : string := "VIRTEX5";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
begin -- struct
gen: if not ((tech = virtex5) or (tech = virtex6) or (tech = virtex7) or (tech = kintex7)) generate
alm <= (others => '0');
busy <= '0';
channel <= (others => '0');
do <= (others => '0');
drdy <= '0';
eoc <= '0';
eos <= '0';
jtagbusy <= '0';
jtaglocked <= '0';
jtagmodified <= '0';
ot <= '0';
end generate gen;
v5: if tech = virtex5 generate
v50 : sysmon_virtex5
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v5;
v6: if tech = virtex6 generate
v60 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "VIRTEX6",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v6;
v7: if tech = virtex7 generate
v70 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "VIRTEX7",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v7;
k7: if tech = kintex7 generate
k70 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "KINTEX7",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate k7;
end struct;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:47 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_timer_0_0/system_axi_timer_0_0_stub.vhdl
-- Design : system_axi_timer_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_axi_timer_0_0 is
Port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
end system_axi_timer_0_0;
architecture stub of system_axi_timer_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "capturetrig0,capturetrig1,generateout0,generateout1,pwm0,interrupt,freeze,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[4:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[4:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_timer,Vivado 2016.4";
begin
end;
|
-- LEON3 processor core
constant CFG_LEON3 : integer := CONFIG_LEON3;
constant CFG_NCPU : integer := CONFIG_PROC_NUM;
constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
constant CFG_BP : integer := CONFIG_IU_BP;
constant CFG_SVT : integer := CONFIG_IU_SVT;
constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
constant CFG_NOTAG : integer := CONFIG_NOTAG;
constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
constant CFG_PWD : integer := CONFIG_PWD*2;
constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
constant CFG_ISETS : integer := CFG_IU_ISETS;
constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
constant CFG_ILINE : integer := CFG_ILINE_SZ;
constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
constant CFG_DSETS : integer := CFG_IU_DSETS;
constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
constant CFG_DLINE : integer := CFG_DLINE_SZ;
constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP_SP + CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
constant CFG_MMUEN : integer := CONFIG_MMUEN;
constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
constant CFG_ITBSZ : integer := CFG_DSU_ITB + 64*CONFIG_DSU_ITRACE_2P;
constant CFG_ATBSZ : integer := CFG_DSU_ATB;
constant CFG_AHBPF : integer := CFG_DSU_AHBPF;
constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
constant CFG_STAT_ENABLE : integer := CONFIG_STAT_ENABLE;
constant CFG_STAT_CNT : integer := CONFIG_STAT_CNT;
constant CFG_STAT_NMAX : integer := CONFIG_STAT_NMAX;
constant CFG_STAT_DSUEN : integer := CONFIG_STAT_DSUEN;
constant CFG_NP_ASI : integer := CONFIG_NP_ASI;
constant CFG_WRPSR : integer := CONFIG_WRPSR;
constant CFG_ALTWIN : integer := CONFIG_ALTWIN;
constant CFG_REX : integer := CONFIG_REX;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 1 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80se;
architecture rtl of T80se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
t80mode => Mode
)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_sequencer is
constant ADDR_BITS: natural := 3;
constant ROWS: natural := 8;
type input_deck is array(integer range <>) of std_logic_vector(9 downto 0);
type output_deck is array(integer range <>) of std_logic_vector(7 downto 0);
end test_sequencer;
architecture behavioural of test_sequencer is
component sequencer is
generic (
rows : natural;
addr_bits : natural
);
port (
clock : in std_logic;
input : in std_logic_vector(9 downto 0);
output: out std_logic_vector(8 downto 1);
address : out std_logic_vector(addr_bits-1 downto 0);
write_enable : out std_logic
);
end component sequencer;
constant test_input : input_deck(0 to 7) := (
0 => "1110000111",
1 => "0000000001",
2 => "0000000010",
3 => "0000000011",
4 => "1110001000",
5 => "1010011100",
6 => "1110001000",
7 => "0000000000"
);
constant test_output: output_deck(2 to 9) := (
2 => "10000001",
3 => "10000001",
4 => "10000010",
5 => "00000001",
6 => "10000011",
7 => "01001101",
8 => "00101010",
9 => "01001110"
);
signal clock : std_logic;
signal write_enable : std_logic;
signal input : std_logic_vector(9 downto 0);
signal output : std_logic_vector(8 downto 1);
signal address : std_logic_vector(ADDR_BITS-1 downto 0);
begin
SEQ: sequencer generic map(rows => ROWS, addr_bits => ADDR_BITS)
port map(clock, input, output, address, write_enable);
process
begin
wait for 1 ns;
assert address = "111"
report "T0 read address should be last row of RAM" severity error;
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
input <= test_input(to_integer(unsigned(address)));
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_INIT -> SEQ_FIRST_ROW
wait for 1 ns; -- Here, the data_in will match the last line of the GOL strip
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
assert address = "000"
report "T1 read address should be row 0 of RAM" severity error;
input <= test_input(to_integer(unsigned(address)));
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_FIRST_ROW -> SEQ_UPDATE
wait for 1 ns; -- Here, data_in will match line 0 of the GOL strip
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
assert address = "001"
report "T2 read address should be row 1 of RAM" severity error;
input <= test_input(to_integer(unsigned(address)));
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_UPDATE -> SEQ advance
wait for 1 ns;
assert write_enable = '1'
report "T3 should write out the first calculation" severity error;
assert address = "000"
report "T3 should write to row 0" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_advance -> SEQ_update
wait for 1 ns;
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
assert address = "010"
report "T4 read address should be row 2 of RAM" severity error;
for i in 1 to 5 loop
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert write_enable = '1'
report "Update should write out a result" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert write_enable = '0'
report "Advance should schedule input" severity error;
end loop;
-- This is the interesting bit
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_UPDATE -> SEQ_FLUSH
wait for 1 ns;
assert write_enable = '1'
report "Tn should write out the nnd calculation" severity error;
assert address = "110"
report "Tn should write to row 3" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_FLUSH -> SEQ_INIT
wait for 1 ns;
assert write_enable = '1'
report "Write should be enabled for the final flush" severity error;
assert address = "111"
report "The final flush should write to the final row" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_INIT -> SEQ_FIRST_ROW
wait for 1 ns; -- Here, the data_in will match the last line of the GOL strip
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
assert address = "000"
report "T1 read address should be row 0 of RAM" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_FIRST_ROW -> SEQ_UPDATE
wait for 1 ns; -- Here, data_in will match line 0 of the GOL strip
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
assert address = "001"
report "T2 read address should be row 1 of RAM" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_UPDATE -> SEQ advance
wait for 1 ns;
assert write_enable = '1'
report "T3 should write out the first calculation" severity error;
assert address = "000"
report "T3 should write to row 0" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_advance -> SEQ_update
wait for 1 ns;
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
assert address = "010"
report "T4 read address should be row 2 of RAM" severity error;
wait;
end process;
end behavioural;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity DualPortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
-- Port A
a_we_i : in std_logic;
a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
a_write_i : in unsigned(WORD_SIZE-1 downto 0);
a_read_o : out unsigned(WORD_SIZE-1 downto 0);
-- Port B
b_we_i : in std_logic;
b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
b_write_i : in unsigned(WORD_SIZE-1 downto 0);
b_read_o : out unsigned(WORD_SIZE-1 downto 0));
end entity DualPortRAM;
architecture DualPort_Arch of DualPortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
shared variable ram : ram_type:=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80cd800c",
3 => x"3a0b0b80",
4 => x"c58f0400",
5 => x"00000000",
6 => x"00000000",
7 => x"00000000",
8 => x"80088408",
9 => x"88080b0b",
10 => x"80c5d62d",
11 => x"880c840c",
12 => x"800c0400",
13 => x"00000000",
14 => x"00000000",
15 => x"00000000",
16 => x"71fd0608",
17 => x"72830609",
18 => x"81058205",
19 => x"832b2a83",
20 => x"ffff0652",
21 => x"04000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"83ffff73",
26 => x"83060981",
27 => x"05820583",
28 => x"2b2b0906",
29 => x"7383ffff",
30 => x"0b0b0b0b",
31 => x"83a70400",
32 => x"72098105",
33 => x"72057373",
34 => x"09060906",
35 => x"73097306",
36 => x"070a8106",
37 => x"53510400",
38 => x"00000000",
39 => x"00000000",
40 => x"72722473",
41 => x"732e0753",
42 => x"51040000",
43 => x"00000000",
44 => x"00000000",
45 => x"00000000",
46 => x"00000000",
47 => x"00000000",
48 => x"71737109",
49 => x"71068106",
50 => x"30720a10",
51 => x"0a720a10",
52 => x"0a31050a",
53 => x"81065151",
54 => x"53510400",
55 => x"00000000",
56 => x"72722673",
57 => x"732e0753",
58 => x"51040000",
59 => x"00000000",
60 => x"00000000",
61 => x"00000000",
62 => x"00000000",
63 => x"00000000",
64 => x"00000000",
65 => x"00000000",
66 => x"00000000",
67 => x"00000000",
68 => x"00000000",
69 => x"00000000",
70 => x"00000000",
71 => x"00000000",
72 => x"0b0b0b88",
73 => x"c4040000",
74 => x"00000000",
75 => x"00000000",
76 => x"00000000",
77 => x"00000000",
78 => x"00000000",
79 => x"00000000",
80 => x"720a722b",
81 => x"0a535104",
82 => x"00000000",
83 => x"00000000",
84 => x"00000000",
85 => x"00000000",
86 => x"00000000",
87 => x"00000000",
88 => x"72729f06",
89 => x"0981050b",
90 => x"0b0b88a7",
91 => x"05040000",
92 => x"00000000",
93 => x"00000000",
94 => x"00000000",
95 => x"00000000",
96 => x"72722aff",
97 => x"739f062a",
98 => x"0974090a",
99 => x"8106ff05",
100 => x"06075351",
101 => x"04000000",
102 => x"00000000",
103 => x"00000000",
104 => x"71715351",
105 => x"020d0406",
106 => x"73830609",
107 => x"81058205",
108 => x"832b0b2b",
109 => x"0772fc06",
110 => x"0c515104",
111 => x"00000000",
112 => x"72098105",
113 => x"72050970",
114 => x"81050906",
115 => x"0a810653",
116 => x"51040000",
117 => x"00000000",
118 => x"00000000",
119 => x"00000000",
120 => x"72098105",
121 => x"72050970",
122 => x"81050906",
123 => x"0a098106",
124 => x"53510400",
125 => x"00000000",
126 => x"00000000",
127 => x"00000000",
128 => x"71098105",
129 => x"52040000",
130 => x"00000000",
131 => x"00000000",
132 => x"00000000",
133 => x"00000000",
134 => x"00000000",
135 => x"00000000",
136 => x"72720981",
137 => x"05055351",
138 => x"04000000",
139 => x"00000000",
140 => x"00000000",
141 => x"00000000",
142 => x"00000000",
143 => x"00000000",
144 => x"72097206",
145 => x"73730906",
146 => x"07535104",
147 => x"00000000",
148 => x"00000000",
149 => x"00000000",
150 => x"00000000",
151 => x"00000000",
152 => x"71fc0608",
153 => x"72830609",
154 => x"81058305",
155 => x"1010102a",
156 => x"81ff0652",
157 => x"04000000",
158 => x"00000000",
159 => x"00000000",
160 => x"71fc0608",
161 => x"0b0b80cc",
162 => x"ec738306",
163 => x"10100508",
164 => x"060b0b0b",
165 => x"88aa0400",
166 => x"00000000",
167 => x"00000000",
168 => x"80088408",
169 => x"88087575",
170 => x"0b0b0b8b",
171 => x"8a2d5050",
172 => x"80085688",
173 => x"0c840c80",
174 => x"0c510400",
175 => x"00000000",
176 => x"80088408",
177 => x"88087575",
178 => x"0b0b0b8c",
179 => x"bc2d5050",
180 => x"80085688",
181 => x"0c840c80",
182 => x"0c510400",
183 => x"00000000",
184 => x"72097081",
185 => x"0509060a",
186 => x"8106ff05",
187 => x"70547106",
188 => x"73097274",
189 => x"05ff0506",
190 => x"07515151",
191 => x"04000000",
192 => x"72097081",
193 => x"0509060a",
194 => x"098106ff",
195 => x"05705471",
196 => x"06730972",
197 => x"7405ff05",
198 => x"06075151",
199 => x"51040000",
200 => x"05ff0504",
201 => x"00000000",
202 => x"00000000",
203 => x"00000000",
204 => x"00000000",
205 => x"00000000",
206 => x"00000000",
207 => x"00000000",
208 => x"810b0b0b",
209 => x"80ccfc0c",
210 => x"51040000",
211 => x"00000000",
212 => x"00000000",
213 => x"00000000",
214 => x"00000000",
215 => x"00000000",
216 => x"71810552",
217 => x"04000000",
218 => x"00000000",
219 => x"00000000",
220 => x"00000000",
221 => x"00000000",
222 => x"00000000",
223 => x"00000000",
224 => x"00000000",
225 => x"00000000",
226 => x"00000000",
227 => x"00000000",
228 => x"00000000",
229 => x"00000000",
230 => x"00000000",
231 => x"00000000",
232 => x"02840572",
233 => x"10100552",
234 => x"04000000",
235 => x"00000000",
236 => x"00000000",
237 => x"00000000",
238 => x"00000000",
239 => x"00000000",
240 => x"00000000",
241 => x"00000000",
242 => x"00000000",
243 => x"00000000",
244 => x"00000000",
245 => x"00000000",
246 => x"00000000",
247 => x"00000000",
248 => x"717105ff",
249 => x"05715351",
250 => x"020d0400",
251 => x"00000000",
252 => x"00000000",
253 => x"00000000",
254 => x"00000000",
255 => x"00000000",
256 => x"82c73f80",
257 => x"c4913f04",
258 => x"10101010",
259 => x"10101010",
260 => x"10101010",
261 => x"10101010",
262 => x"10101010",
263 => x"10101010",
264 => x"10101010",
265 => x"10101053",
266 => x"51047381",
267 => x"ff067383",
268 => x"06098105",
269 => x"83051010",
270 => x"102b0772",
271 => x"fc060c51",
272 => x"51043c04",
273 => x"72728072",
274 => x"8106ff05",
275 => x"09720605",
276 => x"71105272",
277 => x"0a100a53",
278 => x"72ed3851",
279 => x"51535104",
280 => x"fe3d0d0b",
281 => x"0b80dce8",
282 => x"08538413",
283 => x"0870882a",
284 => x"70810651",
285 => x"52527080",
286 => x"2ef03871",
287 => x"81ff0680",
288 => x"0c843d0d",
289 => x"04ff3d0d",
290 => x"0b0b80dc",
291 => x"e8085271",
292 => x"0870882a",
293 => x"81327081",
294 => x"06515151",
295 => x"70f13873",
296 => x"720c833d",
297 => x"0d0480cc",
298 => x"fc08802e",
299 => x"a43880cd",
300 => x"8008822e",
301 => x"bd388380",
302 => x"800b0b0b",
303 => x"80dce80c",
304 => x"82a0800b",
305 => x"80dcec0c",
306 => x"8290800b",
307 => x"80dcf00c",
308 => x"04f88080",
309 => x"80a40b0b",
310 => x"0b80dce8",
311 => x"0cf88080",
312 => x"82800b80",
313 => x"dcec0cf8",
314 => x"80808480",
315 => x"0b80dcf0",
316 => x"0c0480c0",
317 => x"a8808c0b",
318 => x"0b0b80dc",
319 => x"e80c80c0",
320 => x"a880940b",
321 => x"80dcec0c",
322 => x"0b0b80cc",
323 => x"c40b80dc",
324 => x"f00c04ff",
325 => x"3d0d80dc",
326 => x"f4335170",
327 => x"a73880cd",
328 => x"88087008",
329 => x"52527080",
330 => x"2e943884",
331 => x"1280cd88",
332 => x"0c702d80",
333 => x"cd880870",
334 => x"08525270",
335 => x"ee38810b",
336 => x"80dcf434",
337 => x"833d0d04",
338 => x"04803d0d",
339 => x"0b0b80dc",
340 => x"e408802e",
341 => x"8e380b0b",
342 => x"0b0b800b",
343 => x"802e0981",
344 => x"06853882",
345 => x"3d0d040b",
346 => x"0b80dce4",
347 => x"510b0b0b",
348 => x"f58e3f82",
349 => x"3d0d0404",
350 => x"803d0d80",
351 => x"ccc85185",
352 => x"de3f800b",
353 => x"800c823d",
354 => x"0d048c08",
355 => x"028c0cf9",
356 => x"3d0d800b",
357 => x"8c08fc05",
358 => x"0c8c0888",
359 => x"05088025",
360 => x"ab388c08",
361 => x"88050830",
362 => x"8c088805",
363 => x"0c800b8c",
364 => x"08f4050c",
365 => x"8c08fc05",
366 => x"08883881",
367 => x"0b8c08f4",
368 => x"050c8c08",
369 => x"f405088c",
370 => x"08fc050c",
371 => x"8c088c05",
372 => x"088025ab",
373 => x"388c088c",
374 => x"0508308c",
375 => x"088c050c",
376 => x"800b8c08",
377 => x"f0050c8c",
378 => x"08fc0508",
379 => x"8838810b",
380 => x"8c08f005",
381 => x"0c8c08f0",
382 => x"05088c08",
383 => x"fc050c80",
384 => x"538c088c",
385 => x"0508528c",
386 => x"08880508",
387 => x"5181a73f",
388 => x"8008708c",
389 => x"08f8050c",
390 => x"548c08fc",
391 => x"0508802e",
392 => x"8c388c08",
393 => x"f8050830",
394 => x"8c08f805",
395 => x"0c8c08f8",
396 => x"05087080",
397 => x"0c54893d",
398 => x"0d8c0c04",
399 => x"8c08028c",
400 => x"0cfb3d0d",
401 => x"800b8c08",
402 => x"fc050c8c",
403 => x"08880508",
404 => x"80259338",
405 => x"8c088805",
406 => x"08308c08",
407 => x"88050c81",
408 => x"0b8c08fc",
409 => x"050c8c08",
410 => x"8c050880",
411 => x"258c388c",
412 => x"088c0508",
413 => x"308c088c",
414 => x"050c8153",
415 => x"8c088c05",
416 => x"08528c08",
417 => x"88050851",
418 => x"ad3f8008",
419 => x"708c08f8",
420 => x"050c548c",
421 => x"08fc0508",
422 => x"802e8c38",
423 => x"8c08f805",
424 => x"08308c08",
425 => x"f8050c8c",
426 => x"08f80508",
427 => x"70800c54",
428 => x"873d0d8c",
429 => x"0c048c08",
430 => x"028c0cfd",
431 => x"3d0d810b",
432 => x"8c08fc05",
433 => x"0c800b8c",
434 => x"08f8050c",
435 => x"8c088c05",
436 => x"088c0888",
437 => x"050827ac",
438 => x"388c08fc",
439 => x"0508802e",
440 => x"a338800b",
441 => x"8c088c05",
442 => x"08249938",
443 => x"8c088c05",
444 => x"08108c08",
445 => x"8c050c8c",
446 => x"08fc0508",
447 => x"108c08fc",
448 => x"050cc939",
449 => x"8c08fc05",
450 => x"08802e80",
451 => x"c9388c08",
452 => x"8c05088c",
453 => x"08880508",
454 => x"26a1388c",
455 => x"08880508",
456 => x"8c088c05",
457 => x"08318c08",
458 => x"88050c8c",
459 => x"08f80508",
460 => x"8c08fc05",
461 => x"08078c08",
462 => x"f8050c8c",
463 => x"08fc0508",
464 => x"812a8c08",
465 => x"fc050c8c",
466 => x"088c0508",
467 => x"812a8c08",
468 => x"8c050cff",
469 => x"af398c08",
470 => x"90050880",
471 => x"2e8f388c",
472 => x"08880508",
473 => x"708c08f4",
474 => x"050c518d",
475 => x"398c08f8",
476 => x"0508708c",
477 => x"08f4050c",
478 => x"518c08f4",
479 => x"0508800c",
480 => x"853d0d8c",
481 => x"0c04fc3d",
482 => x"0d767079",
483 => x"7b555555",
484 => x"558f7227",
485 => x"8c387275",
486 => x"07830651",
487 => x"70802ea7",
488 => x"38ff1252",
489 => x"71ff2e98",
490 => x"38727081",
491 => x"05543374",
492 => x"70810556",
493 => x"34ff1252",
494 => x"71ff2e09",
495 => x"8106ea38",
496 => x"74800c86",
497 => x"3d0d0474",
498 => x"51727084",
499 => x"05540871",
500 => x"70840553",
501 => x"0c727084",
502 => x"05540871",
503 => x"70840553",
504 => x"0c727084",
505 => x"05540871",
506 => x"70840553",
507 => x"0c727084",
508 => x"05540871",
509 => x"70840553",
510 => x"0cf01252",
511 => x"718f26c9",
512 => x"38837227",
513 => x"95387270",
514 => x"84055408",
515 => x"71708405",
516 => x"530cfc12",
517 => x"52718326",
518 => x"ed387054",
519 => x"ff8339f7",
520 => x"3d0d7c70",
521 => x"525380c8",
522 => x"3f725480",
523 => x"085580cc",
524 => x"d8568157",
525 => x"80088105",
526 => x"5a8b3de4",
527 => x"11595382",
528 => x"59f41352",
529 => x"7b881108",
530 => x"52538183",
531 => x"3f800830",
532 => x"70800807",
533 => x"9f2c8a07",
534 => x"800c538b",
535 => x"3d0d04ff",
536 => x"3d0d7352",
537 => x"80cd8c08",
538 => x"51ffb43f",
539 => x"833d0d04",
540 => x"fd3d0d75",
541 => x"70718306",
542 => x"53555270",
543 => x"b8387170",
544 => x"087009f7",
545 => x"fbfdff12",
546 => x"0670f884",
547 => x"82818006",
548 => x"51515253",
549 => x"709d3884",
550 => x"13700870",
551 => x"09f7fbfd",
552 => x"ff120670",
553 => x"f8848281",
554 => x"80065151",
555 => x"52537080",
556 => x"2ee53872",
557 => x"52713351",
558 => x"70802e8a",
559 => x"38811270",
560 => x"33525270",
561 => x"f8387174",
562 => x"31800c85",
563 => x"3d0d04f2",
564 => x"3d0d6062",
565 => x"88110870",
566 => x"57575f5a",
567 => x"74802e81",
568 => x"90388c1a",
569 => x"2270832a",
570 => x"81327081",
571 => x"06515558",
572 => x"73863890",
573 => x"1a089138",
574 => x"795190a2",
575 => x"3fff5480",
576 => x"0880ee38",
577 => x"8c1a2258",
578 => x"7d085780",
579 => x"7883ffff",
580 => x"06700a10",
581 => x"0a708106",
582 => x"51565755",
583 => x"73752e80",
584 => x"d7387490",
585 => x"38760884",
586 => x"18088819",
587 => x"59565974",
588 => x"802ef238",
589 => x"74548880",
590 => x"75278438",
591 => x"88805473",
592 => x"5378529c",
593 => x"1a0851a4",
594 => x"1a085473",
595 => x"2d800b80",
596 => x"082582e6",
597 => x"38800819",
598 => x"75800831",
599 => x"7f880508",
600 => x"80083170",
601 => x"6188050c",
602 => x"56565973",
603 => x"ffb43880",
604 => x"5473800c",
605 => x"903d0d04",
606 => x"75813270",
607 => x"81067641",
608 => x"51547380",
609 => x"2e81c138",
610 => x"74903876",
611 => x"08841808",
612 => x"88195956",
613 => x"5974802e",
614 => x"f238881a",
615 => x"087883ff",
616 => x"ff067089",
617 => x"2a708106",
618 => x"51565956",
619 => x"73802e82",
620 => x"fa387575",
621 => x"278d3877",
622 => x"872a7081",
623 => x"06515473",
624 => x"82b53874",
625 => x"76278338",
626 => x"74567553",
627 => x"78527908",
628 => x"5185823f",
629 => x"881a0876",
630 => x"31881b0c",
631 => x"7908167a",
632 => x"0c745675",
633 => x"19757731",
634 => x"7f880508",
635 => x"78317061",
636 => x"88050c56",
637 => x"56597380",
638 => x"2efef438",
639 => x"8c1a2258",
640 => x"ff863977",
641 => x"78547953",
642 => x"7b525684",
643 => x"c83f881a",
644 => x"08783188",
645 => x"1b0c7908",
646 => x"187a0c7c",
647 => x"76315d7c",
648 => x"8e387951",
649 => x"8fdc3f80",
650 => x"08818f38",
651 => x"80085f75",
652 => x"19757731",
653 => x"7f880508",
654 => x"78317061",
655 => x"88050c56",
656 => x"56597380",
657 => x"2efea838",
658 => x"74818338",
659 => x"76088418",
660 => x"08881959",
661 => x"56597480",
662 => x"2ef23874",
663 => x"538a5278",
664 => x"5182d33f",
665 => x"80087931",
666 => x"81055d80",
667 => x"08843881",
668 => x"155d815f",
669 => x"7c58747d",
670 => x"27833874",
671 => x"58941a08",
672 => x"881b0811",
673 => x"575c807a",
674 => x"085c5490",
675 => x"1a087b27",
676 => x"83388154",
677 => x"75782584",
678 => x"3873ba38",
679 => x"7b7824fe",
680 => x"e2387b53",
681 => x"78529c1a",
682 => x"0851a41a",
683 => x"0854732d",
684 => x"80085680",
685 => x"088024fe",
686 => x"e2388c1a",
687 => x"2280c007",
688 => x"54738c1b",
689 => x"23ff5473",
690 => x"800c903d",
691 => x"0d047eff",
692 => x"a338ff87",
693 => x"39755378",
694 => x"527a5182",
695 => x"f83f7908",
696 => x"167a0c79",
697 => x"518e9b3f",
698 => x"8008cf38",
699 => x"7c76315d",
700 => x"7cfebc38",
701 => x"feac3990",
702 => x"1a087a08",
703 => x"71317611",
704 => x"70565a57",
705 => x"5280cd8c",
706 => x"0851848c",
707 => x"3f800880",
708 => x"2effa738",
709 => x"8008901b",
710 => x"0c800816",
711 => x"7a0c7794",
712 => x"1b0c7488",
713 => x"1b0c7456",
714 => x"fd993979",
715 => x"0858901a",
716 => x"08782783",
717 => x"38815475",
718 => x"75278438",
719 => x"73b33894",
720 => x"1a085675",
721 => x"752680d3",
722 => x"38755378",
723 => x"529c1a08",
724 => x"51a41a08",
725 => x"54732d80",
726 => x"08568008",
727 => x"8024fd83",
728 => x"388c1a22",
729 => x"80c00754",
730 => x"738c1b23",
731 => x"ff54fed7",
732 => x"39755378",
733 => x"52775181",
734 => x"dc3f7908",
735 => x"167a0c79",
736 => x"518cff3f",
737 => x"8008802e",
738 => x"fcd9388c",
739 => x"1a2280c0",
740 => x"0754738c",
741 => x"1b23ff54",
742 => x"fead3974",
743 => x"75547953",
744 => x"78525681",
745 => x"b03f881a",
746 => x"08753188",
747 => x"1b0c7908",
748 => x"157a0cfc",
749 => x"ae39fa3d",
750 => x"0d7a7902",
751 => x"8805a705",
752 => x"33565253",
753 => x"8373278a",
754 => x"38708306",
755 => x"5271802e",
756 => x"a838ff13",
757 => x"5372ff2e",
758 => x"97387033",
759 => x"5273722e",
760 => x"91388111",
761 => x"ff145451",
762 => x"72ff2e09",
763 => x"8106eb38",
764 => x"80517080",
765 => x"0c883d0d",
766 => x"04707257",
767 => x"55835175",
768 => x"82802914",
769 => x"ff125256",
770 => x"708025f3",
771 => x"38837327",
772 => x"bf387408",
773 => x"76327009",
774 => x"f7fbfdff",
775 => x"120670f8",
776 => x"84828180",
777 => x"06515151",
778 => x"70802e99",
779 => x"38745180",
780 => x"52703357",
781 => x"73772eff",
782 => x"b9388111",
783 => x"81135351",
784 => x"837227ed",
785 => x"38fc1384",
786 => x"16565372",
787 => x"8326c338",
788 => x"7451fefe",
789 => x"39fa3d0d",
790 => x"787a7c72",
791 => x"72725757",
792 => x"57595656",
793 => x"747627b2",
794 => x"38761551",
795 => x"757127aa",
796 => x"38707717",
797 => x"ff145455",
798 => x"5371ff2e",
799 => x"9638ff14",
800 => x"ff145454",
801 => x"72337434",
802 => x"ff125271",
803 => x"ff2e0981",
804 => x"06ec3875",
805 => x"800c883d",
806 => x"0d04768f",
807 => x"269738ff",
808 => x"125271ff",
809 => x"2eed3872",
810 => x"70810554",
811 => x"33747081",
812 => x"055634eb",
813 => x"39747607",
814 => x"83065170",
815 => x"e2387575",
816 => x"54517270",
817 => x"84055408",
818 => x"71708405",
819 => x"530c7270",
820 => x"84055408",
821 => x"71708405",
822 => x"530c7270",
823 => x"84055408",
824 => x"71708405",
825 => x"530c7270",
826 => x"84055408",
827 => x"71708405",
828 => x"530cf012",
829 => x"52718f26",
830 => x"c9388372",
831 => x"27953872",
832 => x"70840554",
833 => x"08717084",
834 => x"05530cfc",
835 => x"12527183",
836 => x"26ed3870",
837 => x"54ff8839",
838 => x"ef3d0d63",
839 => x"6567405d",
840 => x"427b802e",
841 => x"84fa3861",
842 => x"51a5b63f",
843 => x"f81c7084",
844 => x"120870fc",
845 => x"0670628b",
846 => x"0570f806",
847 => x"4159455b",
848 => x"5c415796",
849 => x"742782c3",
850 => x"38807b24",
851 => x"7e7c2607",
852 => x"59805478",
853 => x"742e0981",
854 => x"0682a938",
855 => x"777b2581",
856 => x"fc387717",
857 => x"80d4c80b",
858 => x"8805085e",
859 => x"567c762e",
860 => x"84bd3884",
861 => x"160870fe",
862 => x"06178411",
863 => x"08810651",
864 => x"55557382",
865 => x"8b3874fc",
866 => x"06597c76",
867 => x"2e84dd38",
868 => x"77195f7e",
869 => x"7b2581fd",
870 => x"38798106",
871 => x"547382bf",
872 => x"38767708",
873 => x"31841108",
874 => x"fc06565a",
875 => x"75802e91",
876 => x"387c762e",
877 => x"84ea3874",
878 => x"19185978",
879 => x"7b258489",
880 => x"3879802e",
881 => x"82993877",
882 => x"15567a76",
883 => x"24829038",
884 => x"8c1a0888",
885 => x"1b08718c",
886 => x"120c8812",
887 => x"0c557976",
888 => x"59578817",
889 => x"61fc0557",
890 => x"5975a426",
891 => x"85ef387b",
892 => x"79555593",
893 => x"762780c9",
894 => x"387b7084",
895 => x"055d087c",
896 => x"56790c74",
897 => x"70840556",
898 => x"088c180c",
899 => x"9017549b",
900 => x"7627ae38",
901 => x"74708405",
902 => x"5608740c",
903 => x"74708405",
904 => x"56089418",
905 => x"0c981754",
906 => x"a3762795",
907 => x"38747084",
908 => x"05560874",
909 => x"0c747084",
910 => x"0556089c",
911 => x"180ca017",
912 => x"54747084",
913 => x"05560874",
914 => x"70840556",
915 => x"0c747084",
916 => x"05560874",
917 => x"70840556",
918 => x"0c740874",
919 => x"0c777b31",
920 => x"56758f26",
921 => x"80c93884",
922 => x"17088106",
923 => x"78078418",
924 => x"0c771784",
925 => x"11088107",
926 => x"84120c54",
927 => x"6151a2e2",
928 => x"3f881754",
929 => x"73800c93",
930 => x"3d0d0490",
931 => x"5bfdba39",
932 => x"7856fe85",
933 => x"398c1608",
934 => x"88170871",
935 => x"8c120c88",
936 => x"120c557e",
937 => x"707c3157",
938 => x"588f7627",
939 => x"ffb9387a",
940 => x"17841808",
941 => x"81067c07",
942 => x"84190c76",
943 => x"81078412",
944 => x"0c761184",
945 => x"11088107",
946 => x"84120c55",
947 => x"88055261",
948 => x"518cf73f",
949 => x"6151a28a",
950 => x"3f881754",
951 => x"ffa6397d",
952 => x"52615194",
953 => x"f73f8008",
954 => x"59800880",
955 => x"2e81a338",
956 => x"8008f805",
957 => x"60840508",
958 => x"fe066105",
959 => x"55577674",
960 => x"2e83e638",
961 => x"fc185675",
962 => x"a42681aa",
963 => x"387b8008",
964 => x"55559376",
965 => x"2780d838",
966 => x"74708405",
967 => x"56088008",
968 => x"70840580",
969 => x"0c0c8008",
970 => x"75708405",
971 => x"57087170",
972 => x"8405530c",
973 => x"549b7627",
974 => x"b6387470",
975 => x"84055608",
976 => x"74708405",
977 => x"560c7470",
978 => x"84055608",
979 => x"74708405",
980 => x"560ca376",
981 => x"27993874",
982 => x"70840556",
983 => x"08747084",
984 => x"05560c74",
985 => x"70840556",
986 => x"08747084",
987 => x"05560c74",
988 => x"70840556",
989 => x"08747084",
990 => x"05560c74",
991 => x"70840556",
992 => x"08747084",
993 => x"05560c74",
994 => x"08740c7b",
995 => x"5261518b",
996 => x"b93f6151",
997 => x"a0cc3f78",
998 => x"5473800c",
999 => x"933d0d04",
1000 => x"7d526151",
1001 => x"93b63f80",
1002 => x"08800c93",
1003 => x"3d0d0484",
1004 => x"160855fb",
1005 => x"d1397553",
1006 => x"7b528008",
1007 => x"51efc73f",
1008 => x"7b526151",
1009 => x"8b843fca",
1010 => x"398c1608",
1011 => x"88170871",
1012 => x"8c120c88",
1013 => x"120c558c",
1014 => x"1a08881b",
1015 => x"08718c12",
1016 => x"0c88120c",
1017 => x"55797959",
1018 => x"57fbf739",
1019 => x"7719901c",
1020 => x"55557375",
1021 => x"24fba238",
1022 => x"7a177080",
1023 => x"d4c80b88",
1024 => x"050c757c",
1025 => x"31810784",
1026 => x"120c5d84",
1027 => x"17088106",
1028 => x"7b078418",
1029 => x"0c61519f",
1030 => x"c93f8817",
1031 => x"54fce539",
1032 => x"74191890",
1033 => x"1c555d73",
1034 => x"7d24fb95",
1035 => x"388c1a08",
1036 => x"881b0871",
1037 => x"8c120c88",
1038 => x"120c5588",
1039 => x"1a61fc05",
1040 => x"575975a4",
1041 => x"2681ae38",
1042 => x"7b795555",
1043 => x"93762780",
1044 => x"c9387b70",
1045 => x"84055d08",
1046 => x"7c56790c",
1047 => x"74708405",
1048 => x"56088c1b",
1049 => x"0c901a54",
1050 => x"9b7627ae",
1051 => x"38747084",
1052 => x"05560874",
1053 => x"0c747084",
1054 => x"05560894",
1055 => x"1b0c981a",
1056 => x"54a37627",
1057 => x"95387470",
1058 => x"84055608",
1059 => x"740c7470",
1060 => x"84055608",
1061 => x"9c1b0ca0",
1062 => x"1a547470",
1063 => x"84055608",
1064 => x"74708405",
1065 => x"560c7470",
1066 => x"84055608",
1067 => x"74708405",
1068 => x"560c7408",
1069 => x"740c7a1a",
1070 => x"7080d4c8",
1071 => x"0b88050c",
1072 => x"7d7c3181",
1073 => x"0784120c",
1074 => x"54841a08",
1075 => x"81067b07",
1076 => x"841b0c61",
1077 => x"519e8b3f",
1078 => x"7854fdbd",
1079 => x"3975537b",
1080 => x"527851ed",
1081 => x"a13ffaf5",
1082 => x"39841708",
1083 => x"fc061860",
1084 => x"5858fae9",
1085 => x"3975537b",
1086 => x"527851ed",
1087 => x"893f7a1a",
1088 => x"7080d4c8",
1089 => x"0b88050c",
1090 => x"7d7c3181",
1091 => x"0784120c",
1092 => x"54841a08",
1093 => x"81067b07",
1094 => x"841b0cff",
1095 => x"b639fa3d",
1096 => x"0d7880cd",
1097 => x"8c085455",
1098 => x"b8130880",
1099 => x"2e81b638",
1100 => x"8c152270",
1101 => x"83ffff06",
1102 => x"70832a81",
1103 => x"32708106",
1104 => x"51555556",
1105 => x"72802e80",
1106 => x"dc387384",
1107 => x"2a813281",
1108 => x"0657ff53",
1109 => x"7680f738",
1110 => x"73822a70",
1111 => x"81065153",
1112 => x"72802eb9",
1113 => x"38b01508",
1114 => x"5473802e",
1115 => x"9c3880c0",
1116 => x"15537373",
1117 => x"2e8f3873",
1118 => x"5280cd8c",
1119 => x"085187ca",
1120 => x"3f8c1522",
1121 => x"5676b016",
1122 => x"0c75db06",
1123 => x"53728c16",
1124 => x"23800b84",
1125 => x"160c9015",
1126 => x"08750c72",
1127 => x"56758807",
1128 => x"53728c16",
1129 => x"23901508",
1130 => x"802e80c1",
1131 => x"388c1522",
1132 => x"70810655",
1133 => x"53739e38",
1134 => x"720a100a",
1135 => x"70810651",
1136 => x"53728538",
1137 => x"94150854",
1138 => x"7388160c",
1139 => x"80537280",
1140 => x"0c883d0d",
1141 => x"04800b88",
1142 => x"160c9415",
1143 => x"08309816",
1144 => x"0c8053ea",
1145 => x"39725182",
1146 => x"fb3ffec4",
1147 => x"3974518c",
1148 => x"e83f8c15",
1149 => x"22708106",
1150 => x"55537380",
1151 => x"2effb938",
1152 => x"d439f83d",
1153 => x"0d7a5877",
1154 => x"802e8199",
1155 => x"3880cd8c",
1156 => x"0854b814",
1157 => x"08802e80",
1158 => x"ed388c18",
1159 => x"2270902b",
1160 => x"70902c70",
1161 => x"832a8132",
1162 => x"81065c51",
1163 => x"57547880",
1164 => x"cd389018",
1165 => x"08577680",
1166 => x"2e80c338",
1167 => x"77087731",
1168 => x"77790c76",
1169 => x"83067a58",
1170 => x"55557385",
1171 => x"38941808",
1172 => x"56758819",
1173 => x"0c807525",
1174 => x"a5387453",
1175 => x"76529c18",
1176 => x"0851a418",
1177 => x"0854732d",
1178 => x"800b8008",
1179 => x"2580c938",
1180 => x"80081775",
1181 => x"80083156",
1182 => x"57748024",
1183 => x"dd38800b",
1184 => x"800c8a3d",
1185 => x"0d047351",
1186 => x"81da3f8c",
1187 => x"18227090",
1188 => x"2b70902c",
1189 => x"70832a81",
1190 => x"3281065c",
1191 => x"51575478",
1192 => x"dd38ff8e",
1193 => x"39a48252",
1194 => x"80cd8c08",
1195 => x"5189f13f",
1196 => x"8008800c",
1197 => x"8a3d0d04",
1198 => x"8c182280",
1199 => x"c0075473",
1200 => x"8c1923ff",
1201 => x"0b800c8a",
1202 => x"3d0d0480",
1203 => x"3d0d7251",
1204 => x"80710c80",
1205 => x"0b84120c",
1206 => x"800b8812",
1207 => x"0c028e05",
1208 => x"228c1223",
1209 => x"02920522",
1210 => x"8e122380",
1211 => x"0b90120c",
1212 => x"800b9412",
1213 => x"0c800b98",
1214 => x"120c709c",
1215 => x"120c80c0",
1216 => x"970ba012",
1217 => x"0c80c0e3",
1218 => x"0ba4120c",
1219 => x"80c1df0b",
1220 => x"a8120c80",
1221 => x"c2b00bac",
1222 => x"120c823d",
1223 => x"0d04fa3d",
1224 => x"0d797080",
1225 => x"dc298c11",
1226 => x"547a5356",
1227 => x"578cad3f",
1228 => x"80088008",
1229 => x"55568008",
1230 => x"802ea238",
1231 => x"80088c05",
1232 => x"54800b80",
1233 => x"080c7680",
1234 => x"0884050c",
1235 => x"73800888",
1236 => x"050c7453",
1237 => x"80527351",
1238 => x"97f83f75",
1239 => x"5473800c",
1240 => x"883d0d04",
1241 => x"fc3d0d76",
1242 => x"a8f70bbc",
1243 => x"120c5581",
1244 => x"0bb8160c",
1245 => x"800b84dc",
1246 => x"160c830b",
1247 => x"84e0160c",
1248 => x"84e81584",
1249 => x"e4160c74",
1250 => x"54805384",
1251 => x"52841508",
1252 => x"51feb83f",
1253 => x"74548153",
1254 => x"89528815",
1255 => x"0851feab",
1256 => x"3f745482",
1257 => x"538a528c",
1258 => x"150851fe",
1259 => x"9e3f863d",
1260 => x"0d04f93d",
1261 => x"0d7980cd",
1262 => x"8c085457",
1263 => x"b8130880",
1264 => x"2e80c838",
1265 => x"84dc1356",
1266 => x"88160884",
1267 => x"1708ff05",
1268 => x"55558074",
1269 => x"249f388c",
1270 => x"15227090",
1271 => x"2b70902c",
1272 => x"51545872",
1273 => x"802e80ca",
1274 => x"3880dc15",
1275 => x"ff155555",
1276 => x"738025e3",
1277 => x"38750853",
1278 => x"72802e9f",
1279 => x"38725688",
1280 => x"16088417",
1281 => x"08ff0555",
1282 => x"55c83972",
1283 => x"51fed53f",
1284 => x"80cd8c08",
1285 => x"84dc0556",
1286 => x"ffae3984",
1287 => x"527651fd",
1288 => x"fd3f8008",
1289 => x"760c8008",
1290 => x"802e80c0",
1291 => x"38800856",
1292 => x"ce39810b",
1293 => x"8c162372",
1294 => x"750c7288",
1295 => x"160c7284",
1296 => x"160c7290",
1297 => x"160c7294",
1298 => x"160c7298",
1299 => x"160cff0b",
1300 => x"8e162372",
1301 => x"b0160c72",
1302 => x"b4160c72",
1303 => x"80c4160c",
1304 => x"7280c816",
1305 => x"0c74800c",
1306 => x"893d0d04",
1307 => x"8c770c80",
1308 => x"0b800c89",
1309 => x"3d0d04ff",
1310 => x"3d0da482",
1311 => x"52735186",
1312 => x"9f3f833d",
1313 => x"0d04803d",
1314 => x"0d80cd8c",
1315 => x"0851e83f",
1316 => x"823d0d04",
1317 => x"fb3d0d77",
1318 => x"70525696",
1319 => x"c43f80d4",
1320 => x"c80b8805",
1321 => x"08841108",
1322 => x"fc06707b",
1323 => x"319fef05",
1324 => x"e08006e0",
1325 => x"80055656",
1326 => x"53a08074",
1327 => x"24943880",
1328 => x"52755196",
1329 => x"9e3f80d4",
1330 => x"d0081553",
1331 => x"7280082e",
1332 => x"8f387551",
1333 => x"968c3f80",
1334 => x"5372800c",
1335 => x"873d0d04",
1336 => x"73305275",
1337 => x"5195fc3f",
1338 => x"8008ff2e",
1339 => x"a83880d4",
1340 => x"c80b8805",
1341 => x"08757531",
1342 => x"81078412",
1343 => x"0c5380d4",
1344 => x"8c087431",
1345 => x"80d48c0c",
1346 => x"755195d6",
1347 => x"3f810b80",
1348 => x"0c873d0d",
1349 => x"04805275",
1350 => x"5195c83f",
1351 => x"80d4c80b",
1352 => x"88050880",
1353 => x"08713156",
1354 => x"538f7525",
1355 => x"ffa43880",
1356 => x"0880d4bc",
1357 => x"083180d4",
1358 => x"8c0c7481",
1359 => x"0784140c",
1360 => x"7551959e",
1361 => x"3f8053ff",
1362 => x"9039f63d",
1363 => x"0d7c7e54",
1364 => x"5b72802e",
1365 => x"8283387a",
1366 => x"5195863f",
1367 => x"f8138411",
1368 => x"0870fe06",
1369 => x"70138411",
1370 => x"08fc065d",
1371 => x"58595458",
1372 => x"80d4d008",
1373 => x"752e82de",
1374 => x"38788416",
1375 => x"0c807381",
1376 => x"06545a72",
1377 => x"7a2e81d5",
1378 => x"38781584",
1379 => x"11088106",
1380 => x"515372a0",
1381 => x"38781757",
1382 => x"7981e638",
1383 => x"88150853",
1384 => x"7280d4d0",
1385 => x"2e82f938",
1386 => x"8c150870",
1387 => x"8c150c73",
1388 => x"88120c56",
1389 => x"76810784",
1390 => x"190c7618",
1391 => x"77710c53",
1392 => x"79819138",
1393 => x"83ff7727",
1394 => x"81c83876",
1395 => x"892a7783",
1396 => x"2a565372",
1397 => x"802ebf38",
1398 => x"76862ab8",
1399 => x"05558473",
1400 => x"27b43880",
1401 => x"db135594",
1402 => x"7327ab38",
1403 => x"768c2a80",
1404 => x"ee055580",
1405 => x"d473279e",
1406 => x"38768f2a",
1407 => x"80f70555",
1408 => x"82d47327",
1409 => x"91387692",
1410 => x"2a80fc05",
1411 => x"558ad473",
1412 => x"27843880",
1413 => x"fe557410",
1414 => x"101080d4",
1415 => x"c8058811",
1416 => x"08555673",
1417 => x"762e82b3",
1418 => x"38841408",
1419 => x"fc065376",
1420 => x"73278d38",
1421 => x"88140854",
1422 => x"73762e09",
1423 => x"8106ea38",
1424 => x"8c140870",
1425 => x"8c1a0c74",
1426 => x"881a0c78",
1427 => x"88120c56",
1428 => x"778c150c",
1429 => x"7a51938a",
1430 => x"3f8c3d0d",
1431 => x"04770878",
1432 => x"71315977",
1433 => x"05881908",
1434 => x"54577280",
1435 => x"d4d02e80",
1436 => x"e0388c18",
1437 => x"08708c15",
1438 => x"0c738812",
1439 => x"0c56fe89",
1440 => x"39881508",
1441 => x"8c160870",
1442 => x"8c130c57",
1443 => x"88170cfe",
1444 => x"a3397683",
1445 => x"2a705455",
1446 => x"80752481",
1447 => x"98387282",
1448 => x"2c81712b",
1449 => x"80d4cc08",
1450 => x"0780d4c8",
1451 => x"0b84050c",
1452 => x"53741010",
1453 => x"1080d4c8",
1454 => x"05881108",
1455 => x"5556758c",
1456 => x"190c7388",
1457 => x"190c7788",
1458 => x"170c778c",
1459 => x"150cff84",
1460 => x"39815afd",
1461 => x"b4397817",
1462 => x"73810654",
1463 => x"57729838",
1464 => x"77087871",
1465 => x"31597705",
1466 => x"8c190888",
1467 => x"1a08718c",
1468 => x"120c8812",
1469 => x"0c575776",
1470 => x"81078419",
1471 => x"0c7780d4",
1472 => x"c80b8805",
1473 => x"0c80d4c4",
1474 => x"087726fe",
1475 => x"c73880d4",
1476 => x"c008527a",
1477 => x"51fafd3f",
1478 => x"7a5191c6",
1479 => x"3ffeba39",
1480 => x"81788c15",
1481 => x"0c788815",
1482 => x"0c738c1a",
1483 => x"0c73881a",
1484 => x"0c5afd80",
1485 => x"39831570",
1486 => x"822c8171",
1487 => x"2b80d4cc",
1488 => x"080780d4",
1489 => x"c80b8405",
1490 => x"0c515374",
1491 => x"10101080",
1492 => x"d4c80588",
1493 => x"11085556",
1494 => x"fee43974",
1495 => x"53807524",
1496 => x"a7387282",
1497 => x"2c81712b",
1498 => x"80d4cc08",
1499 => x"0780d4c8",
1500 => x"0b84050c",
1501 => x"53758c19",
1502 => x"0c738819",
1503 => x"0c778817",
1504 => x"0c778c15",
1505 => x"0cfdcd39",
1506 => x"83157082",
1507 => x"2c81712b",
1508 => x"80d4cc08",
1509 => x"0780d4c8",
1510 => x"0b84050c",
1511 => x"5153d639",
1512 => x"f93d0d79",
1513 => x"7b585380",
1514 => x"0b80cd8c",
1515 => x"08535672",
1516 => x"722e80c0",
1517 => x"3884dc13",
1518 => x"5574762e",
1519 => x"b7388815",
1520 => x"08841608",
1521 => x"ff055454",
1522 => x"8073249d",
1523 => x"388c1422",
1524 => x"70902b70",
1525 => x"902c5153",
1526 => x"587180d8",
1527 => x"3880dc14",
1528 => x"ff145454",
1529 => x"728025e5",
1530 => x"38740855",
1531 => x"74d03880",
1532 => x"cd8c0852",
1533 => x"84dc1255",
1534 => x"74802eb1",
1535 => x"38881508",
1536 => x"841608ff",
1537 => x"05545480",
1538 => x"73249c38",
1539 => x"8c142270",
1540 => x"902b7090",
1541 => x"2c515358",
1542 => x"71ad3880",
1543 => x"dc14ff14",
1544 => x"54547280",
1545 => x"25e63874",
1546 => x"085574d1",
1547 => x"3875800c",
1548 => x"893d0d04",
1549 => x"7351762d",
1550 => x"75800807",
1551 => x"80dc15ff",
1552 => x"15555556",
1553 => x"ff9e3973",
1554 => x"51762d75",
1555 => x"80080780",
1556 => x"dc15ff15",
1557 => x"555556ca",
1558 => x"39ea3d0d",
1559 => x"688c1122",
1560 => x"700a100a",
1561 => x"81065758",
1562 => x"567480e4",
1563 => x"388e1622",
1564 => x"70902b70",
1565 => x"902c5155",
1566 => x"58807424",
1567 => x"b138983d",
1568 => x"c4055373",
1569 => x"5280cd8c",
1570 => x"085192ac",
1571 => x"3f800b80",
1572 => x"08249738",
1573 => x"7983e080",
1574 => x"06547380",
1575 => x"c0802e81",
1576 => x"8f387382",
1577 => x"80802e81",
1578 => x"91388c16",
1579 => x"22577690",
1580 => x"80075473",
1581 => x"8c172388",
1582 => x"805280cd",
1583 => x"8c085181",
1584 => x"9b3f8008",
1585 => x"9d388c16",
1586 => x"22820754",
1587 => x"738c1723",
1588 => x"80c31670",
1589 => x"770c9017",
1590 => x"0c810b94",
1591 => x"170c983d",
1592 => x"0d0480cd",
1593 => x"8c08a8f7",
1594 => x"0bbc120c",
1595 => x"548c1622",
1596 => x"81800754",
1597 => x"738c1723",
1598 => x"8008760c",
1599 => x"80089017",
1600 => x"0c88800b",
1601 => x"94170c74",
1602 => x"802ed338",
1603 => x"8e162270",
1604 => x"902b7090",
1605 => x"2c535558",
1606 => x"98a23f80",
1607 => x"08802eff",
1608 => x"bd388c16",
1609 => x"22810754",
1610 => x"738c1723",
1611 => x"983d0d04",
1612 => x"810b8c17",
1613 => x"225855fe",
1614 => x"f539a816",
1615 => x"0880c1df",
1616 => x"2e098106",
1617 => x"fee4388c",
1618 => x"16228880",
1619 => x"0754738c",
1620 => x"17238880",
1621 => x"0b80cc17",
1622 => x"0cfedc39",
1623 => x"f33d0d7f",
1624 => x"618b1170",
1625 => x"f8065c55",
1626 => x"555e7296",
1627 => x"26833890",
1628 => x"59807924",
1629 => x"747a2607",
1630 => x"53805472",
1631 => x"742e0981",
1632 => x"0680cb38",
1633 => x"7d518cd9",
1634 => x"3f7883f7",
1635 => x"2680c638",
1636 => x"78832a70",
1637 => x"10101080",
1638 => x"d4c8058c",
1639 => x"11085959",
1640 => x"5a76782e",
1641 => x"83b03884",
1642 => x"1708fc06",
1643 => x"568c1708",
1644 => x"88180871",
1645 => x"8c120c88",
1646 => x"120c5875",
1647 => x"17841108",
1648 => x"81078412",
1649 => x"0c537d51",
1650 => x"8c983f88",
1651 => x"17547380",
1652 => x"0c8f3d0d",
1653 => x"0478892a",
1654 => x"79832a5b",
1655 => x"5372802e",
1656 => x"bf387886",
1657 => x"2ab8055a",
1658 => x"847327b4",
1659 => x"3880db13",
1660 => x"5a947327",
1661 => x"ab38788c",
1662 => x"2a80ee05",
1663 => x"5a80d473",
1664 => x"279e3878",
1665 => x"8f2a80f7",
1666 => x"055a82d4",
1667 => x"73279138",
1668 => x"78922a80",
1669 => x"fc055a8a",
1670 => x"d4732784",
1671 => x"3880fe5a",
1672 => x"79101010",
1673 => x"80d4c805",
1674 => x"8c110858",
1675 => x"5576752e",
1676 => x"a3388417",
1677 => x"08fc0670",
1678 => x"7a315556",
1679 => x"738f2488",
1680 => x"d5387380",
1681 => x"25fee638",
1682 => x"8c170857",
1683 => x"76752e09",
1684 => x"8106df38",
1685 => x"811a5a80",
1686 => x"d4d80857",
1687 => x"7680d4d0",
1688 => x"2e82c038",
1689 => x"841708fc",
1690 => x"06707a31",
1691 => x"5556738f",
1692 => x"2481f938",
1693 => x"80d4d00b",
1694 => x"80d4dc0c",
1695 => x"80d4d00b",
1696 => x"80d4d80c",
1697 => x"738025fe",
1698 => x"b23883ff",
1699 => x"762783df",
1700 => x"3875892a",
1701 => x"76832a55",
1702 => x"5372802e",
1703 => x"bf387586",
1704 => x"2ab80554",
1705 => x"847327b4",
1706 => x"3880db13",
1707 => x"54947327",
1708 => x"ab38758c",
1709 => x"2a80ee05",
1710 => x"5480d473",
1711 => x"279e3875",
1712 => x"8f2a80f7",
1713 => x"055482d4",
1714 => x"73279138",
1715 => x"75922a80",
1716 => x"fc05548a",
1717 => x"d4732784",
1718 => x"3880fe54",
1719 => x"73101010",
1720 => x"80d4c805",
1721 => x"88110856",
1722 => x"5874782e",
1723 => x"86cf3884",
1724 => x"1508fc06",
1725 => x"53757327",
1726 => x"8d388815",
1727 => x"08557478",
1728 => x"2e098106",
1729 => x"ea388c15",
1730 => x"0880d4c8",
1731 => x"0b840508",
1732 => x"718c1a0c",
1733 => x"76881a0c",
1734 => x"7888130c",
1735 => x"788c180c",
1736 => x"5d587953",
1737 => x"807a2483",
1738 => x"e6387282",
1739 => x"2c81712b",
1740 => x"5c537a7c",
1741 => x"26819838",
1742 => x"7b7b0653",
1743 => x"7282f138",
1744 => x"79fc0684",
1745 => x"055a7a10",
1746 => x"707d0654",
1747 => x"5b7282e0",
1748 => x"38841a5a",
1749 => x"f1398817",
1750 => x"8c110858",
1751 => x"5876782e",
1752 => x"098106fc",
1753 => x"c238821a",
1754 => x"5afdec39",
1755 => x"78177981",
1756 => x"0784190c",
1757 => x"7080d4dc",
1758 => x"0c7080d4",
1759 => x"d80c80d4",
1760 => x"d00b8c12",
1761 => x"0c8c1108",
1762 => x"88120c74",
1763 => x"81078412",
1764 => x"0c741175",
1765 => x"710c5153",
1766 => x"7d5188c6",
1767 => x"3f881754",
1768 => x"fcac3980",
1769 => x"d4c80b84",
1770 => x"05087a54",
1771 => x"5c798025",
1772 => x"fef83882",
1773 => x"da397a09",
1774 => x"7c067080",
1775 => x"d4c80b84",
1776 => x"050c5c7a",
1777 => x"105b7a7c",
1778 => x"2685387a",
1779 => x"85b83880",
1780 => x"d4c80b88",
1781 => x"05087084",
1782 => x"1208fc06",
1783 => x"707c317c",
1784 => x"72268f72",
1785 => x"25075757",
1786 => x"5c5d5572",
1787 => x"802e80db",
1788 => x"38797a16",
1789 => x"80d4c008",
1790 => x"1b90115a",
1791 => x"55575b80",
1792 => x"d4bc08ff",
1793 => x"2e8838a0",
1794 => x"8f13e080",
1795 => x"06577652",
1796 => x"7d5187cf",
1797 => x"3f800854",
1798 => x"8008ff2e",
1799 => x"90388008",
1800 => x"76278299",
1801 => x"387480d4",
1802 => x"c82e8291",
1803 => x"3880d4c8",
1804 => x"0b880508",
1805 => x"55841508",
1806 => x"fc06707a",
1807 => x"317a7226",
1808 => x"8f722507",
1809 => x"52555372",
1810 => x"83e63874",
1811 => x"79810784",
1812 => x"170c7916",
1813 => x"7080d4c8",
1814 => x"0b88050c",
1815 => x"75810784",
1816 => x"120c547e",
1817 => x"525786fa",
1818 => x"3f881754",
1819 => x"fae03975",
1820 => x"832a7054",
1821 => x"54807424",
1822 => x"819b3872",
1823 => x"822c8171",
1824 => x"2b80d4cc",
1825 => x"08077080",
1826 => x"d4c80b84",
1827 => x"050c7510",
1828 => x"101080d4",
1829 => x"c8058811",
1830 => x"08585a5d",
1831 => x"53778c18",
1832 => x"0c748818",
1833 => x"0c768819",
1834 => x"0c768c16",
1835 => x"0cfcf339",
1836 => x"797a1010",
1837 => x"1080d4c8",
1838 => x"05705759",
1839 => x"5d8c1508",
1840 => x"5776752e",
1841 => x"a3388417",
1842 => x"08fc0670",
1843 => x"7a315556",
1844 => x"738f2483",
1845 => x"ca387380",
1846 => x"25848138",
1847 => x"8c170857",
1848 => x"76752e09",
1849 => x"8106df38",
1850 => x"8815811b",
1851 => x"70830655",
1852 => x"5b5572c9",
1853 => x"387c8306",
1854 => x"5372802e",
1855 => x"fdb838ff",
1856 => x"1df81959",
1857 => x"5d881808",
1858 => x"782eea38",
1859 => x"fdb53983",
1860 => x"1a53fc96",
1861 => x"39831470",
1862 => x"822c8171",
1863 => x"2b80d4cc",
1864 => x"08077080",
1865 => x"d4c80b84",
1866 => x"050c7610",
1867 => x"101080d4",
1868 => x"c8058811",
1869 => x"08595b5e",
1870 => x"5153fee1",
1871 => x"3980d48c",
1872 => x"08175880",
1873 => x"08762e81",
1874 => x"8d3880d4",
1875 => x"bc08ff2e",
1876 => x"83ec3873",
1877 => x"76311880",
1878 => x"d48c0c73",
1879 => x"87067057",
1880 => x"5372802e",
1881 => x"88388873",
1882 => x"31701555",
1883 => x"5676149f",
1884 => x"ff06a080",
1885 => x"71311770",
1886 => x"547f5357",
1887 => x"5384e43f",
1888 => x"80085380",
1889 => x"08ff2e81",
1890 => x"a03880d4",
1891 => x"8c081670",
1892 => x"80d48c0c",
1893 => x"747580d4",
1894 => x"c80b8805",
1895 => x"0c747631",
1896 => x"18708107",
1897 => x"51555658",
1898 => x"7b80d4c8",
1899 => x"2e839c38",
1900 => x"798f2682",
1901 => x"cb38810b",
1902 => x"84150c84",
1903 => x"1508fc06",
1904 => x"707a317a",
1905 => x"72268f72",
1906 => x"25075255",
1907 => x"5372802e",
1908 => x"fcf93880",
1909 => x"db398008",
1910 => x"9fff0653",
1911 => x"72feeb38",
1912 => x"7780d48c",
1913 => x"0c80d4c8",
1914 => x"0b880508",
1915 => x"7b188107",
1916 => x"84120c55",
1917 => x"80d4b808",
1918 => x"78278638",
1919 => x"7780d4b8",
1920 => x"0c80d4b4",
1921 => x"087827fc",
1922 => x"ac387780",
1923 => x"d4b40c84",
1924 => x"1508fc06",
1925 => x"707a317a",
1926 => x"72268f72",
1927 => x"25075255",
1928 => x"5372802e",
1929 => x"fca53888",
1930 => x"39807454",
1931 => x"56fedb39",
1932 => x"7d5183ae",
1933 => x"3f800b80",
1934 => x"0c8f3d0d",
1935 => x"04735380",
1936 => x"7424a938",
1937 => x"72822c81",
1938 => x"712b80d4",
1939 => x"cc080770",
1940 => x"80d4c80b",
1941 => x"84050c5d",
1942 => x"53778c18",
1943 => x"0c748818",
1944 => x"0c768819",
1945 => x"0c768c16",
1946 => x"0cf9b739",
1947 => x"83147082",
1948 => x"2c81712b",
1949 => x"80d4cc08",
1950 => x"077080d4",
1951 => x"c80b8405",
1952 => x"0c5e5153",
1953 => x"d4397b7b",
1954 => x"065372fc",
1955 => x"a338841a",
1956 => x"7b105c5a",
1957 => x"f139ff1a",
1958 => x"8111515a",
1959 => x"f7b93978",
1960 => x"17798107",
1961 => x"84190c8c",
1962 => x"18088819",
1963 => x"08718c12",
1964 => x"0c88120c",
1965 => x"597080d4",
1966 => x"dc0c7080",
1967 => x"d4d80c80",
1968 => x"d4d00b8c",
1969 => x"120c8c11",
1970 => x"0888120c",
1971 => x"74810784",
1972 => x"120c7411",
1973 => x"75710c51",
1974 => x"53f9bd39",
1975 => x"75178411",
1976 => x"08810784",
1977 => x"120c538c",
1978 => x"17088818",
1979 => x"08718c12",
1980 => x"0c88120c",
1981 => x"587d5181",
1982 => x"e93f8817",
1983 => x"54f5cf39",
1984 => x"7284150c",
1985 => x"f41af806",
1986 => x"70841e08",
1987 => x"81060784",
1988 => x"1e0c701d",
1989 => x"545b850b",
1990 => x"84140c85",
1991 => x"0b88140c",
1992 => x"8f7b27fd",
1993 => x"cf38881c",
1994 => x"527d51ec",
1995 => x"9d3f80d4",
1996 => x"c80b8805",
1997 => x"0880d48c",
1998 => x"085955fd",
1999 => x"b7397780",
2000 => x"d48c0c73",
2001 => x"80d4bc0c",
2002 => x"fc913972",
2003 => x"84150cfd",
2004 => x"a339fc3d",
2005 => x"0d767971",
2006 => x"028c059f",
2007 => x"05335755",
2008 => x"53558372",
2009 => x"278a3874",
2010 => x"83065170",
2011 => x"802ea238",
2012 => x"ff125271",
2013 => x"ff2e9338",
2014 => x"73737081",
2015 => x"055534ff",
2016 => x"125271ff",
2017 => x"2e098106",
2018 => x"ef387480",
2019 => x"0c863d0d",
2020 => x"04747488",
2021 => x"2b750770",
2022 => x"71902b07",
2023 => x"5154518f",
2024 => x"7227a538",
2025 => x"72717084",
2026 => x"05530c72",
2027 => x"71708405",
2028 => x"530c7271",
2029 => x"70840553",
2030 => x"0c727170",
2031 => x"8405530c",
2032 => x"f0125271",
2033 => x"8f26dd38",
2034 => x"83722790",
2035 => x"38727170",
2036 => x"8405530c",
2037 => x"fc125271",
2038 => x"8326f238",
2039 => x"7053ff90",
2040 => x"390404fd",
2041 => x"3d0d800b",
2042 => x"80dd800c",
2043 => x"765184ee",
2044 => x"3f800853",
2045 => x"8008ff2e",
2046 => x"88387280",
2047 => x"0c853d0d",
2048 => x"0480dd80",
2049 => x"08547380",
2050 => x"2ef03875",
2051 => x"74710c52",
2052 => x"72800c85",
2053 => x"3d0d04f9",
2054 => x"3d0d797c",
2055 => x"557b548e",
2056 => x"11227090",
2057 => x"2b70902c",
2058 => x"555780cd",
2059 => x"8c085358",
2060 => x"5683f33f",
2061 => x"80085780",
2062 => x"0b800824",
2063 => x"933880d0",
2064 => x"16088008",
2065 => x"0580d017",
2066 => x"0c76800c",
2067 => x"893d0d04",
2068 => x"8c162283",
2069 => x"dfff0655",
2070 => x"748c1723",
2071 => x"76800c89",
2072 => x"3d0d04fa",
2073 => x"3d0d788c",
2074 => x"11227088",
2075 => x"2a708106",
2076 => x"51575856",
2077 => x"74a9388c",
2078 => x"162283df",
2079 => x"ff065574",
2080 => x"8c17237a",
2081 => x"5479538e",
2082 => x"16227090",
2083 => x"2b70902c",
2084 => x"545680cd",
2085 => x"8c085256",
2086 => x"81b23f88",
2087 => x"3d0d0482",
2088 => x"5480538e",
2089 => x"16227090",
2090 => x"2b70902c",
2091 => x"545680cd",
2092 => x"8c085257",
2093 => x"82b83f8c",
2094 => x"162283df",
2095 => x"ff065574",
2096 => x"8c17237a",
2097 => x"5479538e",
2098 => x"16227090",
2099 => x"2b70902c",
2100 => x"545680cd",
2101 => x"8c085256",
2102 => x"80f23f88",
2103 => x"3d0d04f9",
2104 => x"3d0d797c",
2105 => x"557b548e",
2106 => x"11227090",
2107 => x"2b70902c",
2108 => x"555780cd",
2109 => x"8c085358",
2110 => x"5681f33f",
2111 => x"80085780",
2112 => x"08ff2e99",
2113 => x"388c1622",
2114 => x"a0800755",
2115 => x"748c1723",
2116 => x"800880d0",
2117 => x"170c7680",
2118 => x"0c893d0d",
2119 => x"048c1622",
2120 => x"83dfff06",
2121 => x"55748c17",
2122 => x"2376800c",
2123 => x"893d0d04",
2124 => x"fe3d0d74",
2125 => x"8e112270",
2126 => x"902b7090",
2127 => x"2c555151",
2128 => x"5380cd8c",
2129 => x"0851bd3f",
2130 => x"843d0d04",
2131 => x"fb3d0d80",
2132 => x"0b80dd80",
2133 => x"0c7a5379",
2134 => x"52785182",
2135 => x"fc3f8008",
2136 => x"558008ff",
2137 => x"2e883874",
2138 => x"800c873d",
2139 => x"0d0480dd",
2140 => x"80085675",
2141 => x"802ef038",
2142 => x"7776710c",
2143 => x"5474800c",
2144 => x"873d0d04",
2145 => x"fd3d0d80",
2146 => x"0b80dd80",
2147 => x"0c765184",
2148 => x"c63f8008",
2149 => x"538008ff",
2150 => x"2e883872",
2151 => x"800c853d",
2152 => x"0d0480dd",
2153 => x"80085473",
2154 => x"802ef038",
2155 => x"7574710c",
2156 => x"5272800c",
2157 => x"853d0d04",
2158 => x"fc3d0d80",
2159 => x"0b80dd80",
2160 => x"0c785277",
2161 => x"5186ac3f",
2162 => x"80085480",
2163 => x"08ff2e88",
2164 => x"3873800c",
2165 => x"863d0d04",
2166 => x"80dd8008",
2167 => x"5574802e",
2168 => x"f0387675",
2169 => x"710c5373",
2170 => x"800c863d",
2171 => x"0d04fb3d",
2172 => x"0d800b80",
2173 => x"dd800c7a",
2174 => x"53795278",
2175 => x"5184893f",
2176 => x"80085580",
2177 => x"08ff2e88",
2178 => x"3874800c",
2179 => x"873d0d04",
2180 => x"80dd8008",
2181 => x"5675802e",
2182 => x"f0387776",
2183 => x"710c5474",
2184 => x"800c873d",
2185 => x"0d04fb3d",
2186 => x"0d800b80",
2187 => x"dd800c7a",
2188 => x"53795278",
2189 => x"5182963f",
2190 => x"80085580",
2191 => x"08ff2e88",
2192 => x"3874800c",
2193 => x"873d0d04",
2194 => x"80dd8008",
2195 => x"5675802e",
2196 => x"f0387776",
2197 => x"710c5474",
2198 => x"800c873d",
2199 => x"0d04fe3d",
2200 => x"0d80dcf8",
2201 => x"0851708a",
2202 => x"3880dd84",
2203 => x"7080dcf8",
2204 => x"0c517075",
2205 => x"125252ff",
2206 => x"537087fb",
2207 => x"80802688",
2208 => x"387080dc",
2209 => x"f80c7153",
2210 => x"72800c84",
2211 => x"3d0d04fd",
2212 => x"3d0d800b",
2213 => x"80cd8008",
2214 => x"54547281",
2215 => x"2e9b3873",
2216 => x"80dcfc0c",
2217 => x"c4803fc2",
2218 => x"d73f80dc",
2219 => x"d0528151",
2220 => x"c5c63f80",
2221 => x"085185bb",
2222 => x"3f7280dc",
2223 => x"fc0cc3e6",
2224 => x"3fc2bd3f",
2225 => x"80dcd052",
2226 => x"8151c5ac",
2227 => x"3f800851",
2228 => x"85a13f00",
2229 => x"ff3900ff",
2230 => x"39f53d0d",
2231 => x"7e6080dc",
2232 => x"fc08705b",
2233 => x"585b5b75",
2234 => x"80c23877",
2235 => x"7a25a138",
2236 => x"771b7033",
2237 => x"7081ff06",
2238 => x"58585975",
2239 => x"8a2e9838",
2240 => x"7681ff06",
2241 => x"51c2fe3f",
2242 => x"81185879",
2243 => x"7824e138",
2244 => x"79800c8d",
2245 => x"3d0d048d",
2246 => x"51c2ea3f",
2247 => x"78337081",
2248 => x"ff065257",
2249 => x"c2df3f81",
2250 => x"1858e039",
2251 => x"79557a54",
2252 => x"7d538552",
2253 => x"8d3dfc05",
2254 => x"51c2873f",
2255 => x"80085684",
2256 => x"ab3f7b80",
2257 => x"080c7580",
2258 => x"0c8d3d0d",
2259 => x"04f63d0d",
2260 => x"7d7f80dc",
2261 => x"fc08705b",
2262 => x"585a5a75",
2263 => x"80c13877",
2264 => x"7925b338",
2265 => x"c1fa3f80",
2266 => x"0881ff06",
2267 => x"708d3270",
2268 => x"30709f2a",
2269 => x"51515757",
2270 => x"768a2e80",
2271 => x"c3387580",
2272 => x"2ebe3877",
2273 => x"1a567676",
2274 => x"347651c1",
2275 => x"f83f8118",
2276 => x"58787824",
2277 => x"cf387756",
2278 => x"75800c8c",
2279 => x"3d0d0478",
2280 => x"5579547c",
2281 => x"5384528c",
2282 => x"3dfc0551",
2283 => x"c1943f80",
2284 => x"085683b8",
2285 => x"3f7a8008",
2286 => x"0c75800c",
2287 => x"8c3d0d04",
2288 => x"771a568a",
2289 => x"76348118",
2290 => x"588d51c1",
2291 => x"b83f8a51",
2292 => x"c1b33f77",
2293 => x"56c239fb",
2294 => x"3d0d80dc",
2295 => x"fc087056",
2296 => x"54738838",
2297 => x"74800c87",
2298 => x"3d0d0477",
2299 => x"53835287",
2300 => x"3dfc0551",
2301 => x"c0cc3f80",
2302 => x"085482f0",
2303 => x"3f758008",
2304 => x"0c73800c",
2305 => x"873d0d04",
2306 => x"fa3d0d80",
2307 => x"dcfc0880",
2308 => x"2ea2387a",
2309 => x"55795478",
2310 => x"53865288",
2311 => x"3dfc0551",
2312 => x"c0a03f80",
2313 => x"085682c4",
2314 => x"3f768008",
2315 => x"0c75800c",
2316 => x"883d0d04",
2317 => x"82b63f9d",
2318 => x"0b80080c",
2319 => x"ff0b800c",
2320 => x"883d0d04",
2321 => x"fb3d0d77",
2322 => x"79565680",
2323 => x"70545473",
2324 => x"75259f38",
2325 => x"74101010",
2326 => x"f8055272",
2327 => x"16703370",
2328 => x"742b7607",
2329 => x"8116f816",
2330 => x"56565651",
2331 => x"51747324",
2332 => x"ea387380",
2333 => x"0c873d0d",
2334 => x"04fc3d0d",
2335 => x"76785555",
2336 => x"bc538052",
2337 => x"7351f5ca",
2338 => x"3f845274",
2339 => x"51ffb53f",
2340 => x"80087423",
2341 => x"84528415",
2342 => x"51ffa93f",
2343 => x"80088215",
2344 => x"23845288",
2345 => x"1551ff9c",
2346 => x"3f800884",
2347 => x"150c8452",
2348 => x"8c1551ff",
2349 => x"8f3f8008",
2350 => x"88152384",
2351 => x"52901551",
2352 => x"ff823f80",
2353 => x"088a1523",
2354 => x"84529415",
2355 => x"51fef53f",
2356 => x"80088c15",
2357 => x"23845298",
2358 => x"1551fee8",
2359 => x"3f80088e",
2360 => x"15238852",
2361 => x"9c1551fe",
2362 => x"db3f8008",
2363 => x"90150c86",
2364 => x"3d0d04e9",
2365 => x"3d0d6a80",
2366 => x"dcfc0857",
2367 => x"57759338",
2368 => x"80c0800b",
2369 => x"84180c75",
2370 => x"ac180c75",
2371 => x"800c993d",
2372 => x"0d04893d",
2373 => x"70556a54",
2374 => x"558a5299",
2375 => x"3dffbc05",
2376 => x"51ffbe9e",
2377 => x"3f800877",
2378 => x"53755256",
2379 => x"fecb3fbc",
2380 => x"3f778008",
2381 => x"0c75800c",
2382 => x"993d0d04",
2383 => x"fc3d0d81",
2384 => x"5480dcfc",
2385 => x"08883873",
2386 => x"800c863d",
2387 => x"0d047653",
2388 => x"97b95286",
2389 => x"3dfc0551",
2390 => x"ffbde73f",
2391 => x"8008548c",
2392 => x"3f748008",
2393 => x"0c73800c",
2394 => x"863d0d04",
2395 => x"80cd8c08",
2396 => x"800c04f7",
2397 => x"3d0d7b80",
2398 => x"cd8c0882",
2399 => x"c811085a",
2400 => x"545a7780",
2401 => x"2e80da38",
2402 => x"81881884",
2403 => x"1908ff05",
2404 => x"81712b59",
2405 => x"55598074",
2406 => x"2480ea38",
2407 => x"807424b5",
2408 => x"3873822b",
2409 => x"78118805",
2410 => x"56568180",
2411 => x"19087706",
2412 => x"5372802e",
2413 => x"b6387816",
2414 => x"70085353",
2415 => x"79517408",
2416 => x"53722dff",
2417 => x"14fc17fc",
2418 => x"1779812c",
2419 => x"5a575754",
2420 => x"738025d6",
2421 => x"38770858",
2422 => x"77ffad38",
2423 => x"80cd8c08",
2424 => x"53bc1308",
2425 => x"a5387951",
2426 => x"f9e93f74",
2427 => x"0853722d",
2428 => x"ff14fc17",
2429 => x"fc177981",
2430 => x"2c5a5757",
2431 => x"54738025",
2432 => x"ffa838d1",
2433 => x"398057ff",
2434 => x"93397251",
2435 => x"bc130853",
2436 => x"722d7951",
2437 => x"f9bd3fff",
2438 => x"3d0d80dc",
2439 => x"d80bfc05",
2440 => x"70085252",
2441 => x"70ff2e91",
2442 => x"38702dfc",
2443 => x"12700852",
2444 => x"5270ff2e",
2445 => x"098106f1",
2446 => x"38833d0d",
2447 => x"0404ffbd",
2448 => x"d23f0400",
2449 => x"00000040",
2450 => x"48656c6c",
2451 => x"6f20776f",
2452 => x"726c6421",
2453 => x"00000000",
2454 => x"0a000000",
2455 => x"43000000",
2456 => x"64756d6d",
2457 => x"792e6578",
2458 => x"65000000",
2459 => x"00ffffff",
2460 => x"ff00ffff",
2461 => x"ffff00ff",
2462 => x"ffffff00",
2463 => x"00000000",
2464 => x"00000000",
2465 => x"00000000",
2466 => x"00002e60",
2467 => x"00002690",
2468 => x"00000000",
2469 => x"000028f8",
2470 => x"00002954",
2471 => x"000029b0",
2472 => x"00000000",
2473 => x"00000000",
2474 => x"00000000",
2475 => x"00000000",
2476 => x"00000000",
2477 => x"00000000",
2478 => x"00000000",
2479 => x"00000000",
2480 => x"00000000",
2481 => x"0000265c",
2482 => x"00000000",
2483 => x"00000000",
2484 => x"00000000",
2485 => x"00000000",
2486 => x"00000000",
2487 => x"00000000",
2488 => x"00000000",
2489 => x"00000000",
2490 => x"00000000",
2491 => x"00000000",
2492 => x"00000000",
2493 => x"00000000",
2494 => x"00000000",
2495 => x"00000000",
2496 => x"00000000",
2497 => x"00000000",
2498 => x"00000000",
2499 => x"00000000",
2500 => x"00000000",
2501 => x"00000000",
2502 => x"00000000",
2503 => x"00000000",
2504 => x"00000000",
2505 => x"00000000",
2506 => x"00000000",
2507 => x"00000000",
2508 => x"00000000",
2509 => x"00000000",
2510 => x"00000001",
2511 => x"330eabcd",
2512 => x"1234e66d",
2513 => x"deec0005",
2514 => x"000b0000",
2515 => x"00000000",
2516 => x"00000000",
2517 => x"00000000",
2518 => x"00000000",
2519 => x"00000000",
2520 => x"00000000",
2521 => x"00000000",
2522 => x"00000000",
2523 => x"00000000",
2524 => x"00000000",
2525 => x"00000000",
2526 => x"00000000",
2527 => x"00000000",
2528 => x"00000000",
2529 => x"00000000",
2530 => x"00000000",
2531 => x"00000000",
2532 => x"00000000",
2533 => x"00000000",
2534 => x"00000000",
2535 => x"00000000",
2536 => x"00000000",
2537 => x"00000000",
2538 => x"00000000",
2539 => x"00000000",
2540 => x"00000000",
2541 => x"00000000",
2542 => x"00000000",
2543 => x"00000000",
2544 => x"00000000",
2545 => x"00000000",
2546 => x"00000000",
2547 => x"00000000",
2548 => x"00000000",
2549 => x"00000000",
2550 => x"00000000",
2551 => x"00000000",
2552 => x"00000000",
2553 => x"00000000",
2554 => x"00000000",
2555 => x"00000000",
2556 => x"00000000",
2557 => x"00000000",
2558 => x"00000000",
2559 => x"00000000",
2560 => x"00000000",
2561 => x"00000000",
2562 => x"00000000",
2563 => x"00000000",
2564 => x"00000000",
2565 => x"00000000",
2566 => x"00000000",
2567 => x"00000000",
2568 => x"00000000",
2569 => x"00000000",
2570 => x"00000000",
2571 => x"00000000",
2572 => x"00000000",
2573 => x"00000000",
2574 => x"00000000",
2575 => x"00000000",
2576 => x"00000000",
2577 => x"00000000",
2578 => x"00000000",
2579 => x"00000000",
2580 => x"00000000",
2581 => x"00000000",
2582 => x"00000000",
2583 => x"00000000",
2584 => x"00000000",
2585 => x"00000000",
2586 => x"00000000",
2587 => x"00000000",
2588 => x"00000000",
2589 => x"00000000",
2590 => x"00000000",
2591 => x"00000000",
2592 => x"00000000",
2593 => x"00000000",
2594 => x"00000000",
2595 => x"00000000",
2596 => x"00000000",
2597 => x"00000000",
2598 => x"00000000",
2599 => x"00000000",
2600 => x"00000000",
2601 => x"00000000",
2602 => x"00000000",
2603 => x"00000000",
2604 => x"00000000",
2605 => x"00000000",
2606 => x"00000000",
2607 => x"00000000",
2608 => x"00000000",
2609 => x"00000000",
2610 => x"00000000",
2611 => x"00000000",
2612 => x"00000000",
2613 => x"00000000",
2614 => x"00000000",
2615 => x"00000000",
2616 => x"00000000",
2617 => x"00000000",
2618 => x"00000000",
2619 => x"00000000",
2620 => x"00000000",
2621 => x"00000000",
2622 => x"00000000",
2623 => x"00000000",
2624 => x"00000000",
2625 => x"00000000",
2626 => x"00000000",
2627 => x"00000000",
2628 => x"00000000",
2629 => x"00000000",
2630 => x"00000000",
2631 => x"00000000",
2632 => x"00000000",
2633 => x"00000000",
2634 => x"00000000",
2635 => x"00000000",
2636 => x"00000000",
2637 => x"00000000",
2638 => x"00000000",
2639 => x"00000000",
2640 => x"00000000",
2641 => x"00000000",
2642 => x"00000000",
2643 => x"00000000",
2644 => x"00000000",
2645 => x"00000000",
2646 => x"00000000",
2647 => x"00000000",
2648 => x"00000000",
2649 => x"00000000",
2650 => x"00000000",
2651 => x"00000000",
2652 => x"00000000",
2653 => x"00000000",
2654 => x"00000000",
2655 => x"00000000",
2656 => x"00000000",
2657 => x"00000000",
2658 => x"00000000",
2659 => x"00000000",
2660 => x"00000000",
2661 => x"00000000",
2662 => x"00000000",
2663 => x"00000000",
2664 => x"00000000",
2665 => x"00000000",
2666 => x"00000000",
2667 => x"00000000",
2668 => x"00000000",
2669 => x"00000000",
2670 => x"00000000",
2671 => x"00000000",
2672 => x"00000000",
2673 => x"00000000",
2674 => x"00000000",
2675 => x"00000000",
2676 => x"00000000",
2677 => x"00000000",
2678 => x"00000000",
2679 => x"00000000",
2680 => x"00000000",
2681 => x"00000000",
2682 => x"00000000",
2683 => x"00000000",
2684 => x"00000000",
2685 => x"00000000",
2686 => x"00000000",
2687 => x"00000000",
2688 => x"00000000",
2689 => x"00000000",
2690 => x"00000000",
2691 => x"00000000",
2692 => x"00000000",
2693 => x"00000000",
2694 => x"00000000",
2695 => x"00000000",
2696 => x"00000000",
2697 => x"00000000",
2698 => x"00000000",
2699 => x"00000000",
2700 => x"00000000",
2701 => x"00000000",
2702 => x"00000000",
2703 => x"ffffffff",
2704 => x"00000000",
2705 => x"00020000",
2706 => x"00000000",
2707 => x"00000000",
2708 => x"00002a48",
2709 => x"00002a48",
2710 => x"00002a50",
2711 => x"00002a50",
2712 => x"00002a58",
2713 => x"00002a58",
2714 => x"00002a60",
2715 => x"00002a60",
2716 => x"00002a68",
2717 => x"00002a68",
2718 => x"00002a70",
2719 => x"00002a70",
2720 => x"00002a78",
2721 => x"00002a78",
2722 => x"00002a80",
2723 => x"00002a80",
2724 => x"00002a88",
2725 => x"00002a88",
2726 => x"00002a90",
2727 => x"00002a90",
2728 => x"00002a98",
2729 => x"00002a98",
2730 => x"00002aa0",
2731 => x"00002aa0",
2732 => x"00002aa8",
2733 => x"00002aa8",
2734 => x"00002ab0",
2735 => x"00002ab0",
2736 => x"00002ab8",
2737 => x"00002ab8",
2738 => x"00002ac0",
2739 => x"00002ac0",
2740 => x"00002ac8",
2741 => x"00002ac8",
2742 => x"00002ad0",
2743 => x"00002ad0",
2744 => x"00002ad8",
2745 => x"00002ad8",
2746 => x"00002ae0",
2747 => x"00002ae0",
2748 => x"00002ae8",
2749 => x"00002ae8",
2750 => x"00002af0",
2751 => x"00002af0",
2752 => x"00002af8",
2753 => x"00002af8",
2754 => x"00002b00",
2755 => x"00002b00",
2756 => x"00002b08",
2757 => x"00002b08",
2758 => x"00002b10",
2759 => x"00002b10",
2760 => x"00002b18",
2761 => x"00002b18",
2762 => x"00002b20",
2763 => x"00002b20",
2764 => x"00002b28",
2765 => x"00002b28",
2766 => x"00002b30",
2767 => x"00002b30",
2768 => x"00002b38",
2769 => x"00002b38",
2770 => x"00002b40",
2771 => x"00002b40",
2772 => x"00002b48",
2773 => x"00002b48",
2774 => x"00002b50",
2775 => x"00002b50",
2776 => x"00002b58",
2777 => x"00002b58",
2778 => x"00002b60",
2779 => x"00002b60",
2780 => x"00002b68",
2781 => x"00002b68",
2782 => x"00002b70",
2783 => x"00002b70",
2784 => x"00002b78",
2785 => x"00002b78",
2786 => x"00002b80",
2787 => x"00002b80",
2788 => x"00002b88",
2789 => x"00002b88",
2790 => x"00002b90",
2791 => x"00002b90",
2792 => x"00002b98",
2793 => x"00002b98",
2794 => x"00002ba0",
2795 => x"00002ba0",
2796 => x"00002ba8",
2797 => x"00002ba8",
2798 => x"00002bb0",
2799 => x"00002bb0",
2800 => x"00002bb8",
2801 => x"00002bb8",
2802 => x"00002bc0",
2803 => x"00002bc0",
2804 => x"00002bc8",
2805 => x"00002bc8",
2806 => x"00002bd0",
2807 => x"00002bd0",
2808 => x"00002bd8",
2809 => x"00002bd8",
2810 => x"00002be0",
2811 => x"00002be0",
2812 => x"00002be8",
2813 => x"00002be8",
2814 => x"00002bf0",
2815 => x"00002bf0",
2816 => x"00002bf8",
2817 => x"00002bf8",
2818 => x"00002c00",
2819 => x"00002c00",
2820 => x"00002c08",
2821 => x"00002c08",
2822 => x"00002c10",
2823 => x"00002c10",
2824 => x"00002c18",
2825 => x"00002c18",
2826 => x"00002c20",
2827 => x"00002c20",
2828 => x"00002c28",
2829 => x"00002c28",
2830 => x"00002c30",
2831 => x"00002c30",
2832 => x"00002c38",
2833 => x"00002c38",
2834 => x"00002c40",
2835 => x"00002c40",
2836 => x"00002c48",
2837 => x"00002c48",
2838 => x"00002c50",
2839 => x"00002c50",
2840 => x"00002c58",
2841 => x"00002c58",
2842 => x"00002c60",
2843 => x"00002c60",
2844 => x"00002c68",
2845 => x"00002c68",
2846 => x"00002c70",
2847 => x"00002c70",
2848 => x"00002c78",
2849 => x"00002c78",
2850 => x"00002c80",
2851 => x"00002c80",
2852 => x"00002c88",
2853 => x"00002c88",
2854 => x"00002c90",
2855 => x"00002c90",
2856 => x"00002c98",
2857 => x"00002c98",
2858 => x"00002ca0",
2859 => x"00002ca0",
2860 => x"00002ca8",
2861 => x"00002ca8",
2862 => x"00002cb0",
2863 => x"00002cb0",
2864 => x"00002cb8",
2865 => x"00002cb8",
2866 => x"00002cc0",
2867 => x"00002cc0",
2868 => x"00002cc8",
2869 => x"00002cc8",
2870 => x"00002cd0",
2871 => x"00002cd0",
2872 => x"00002cd8",
2873 => x"00002cd8",
2874 => x"00002ce0",
2875 => x"00002ce0",
2876 => x"00002ce8",
2877 => x"00002ce8",
2878 => x"00002cf0",
2879 => x"00002cf0",
2880 => x"00002cf8",
2881 => x"00002cf8",
2882 => x"00002d00",
2883 => x"00002d00",
2884 => x"00002d08",
2885 => x"00002d08",
2886 => x"00002d10",
2887 => x"00002d10",
2888 => x"00002d18",
2889 => x"00002d18",
2890 => x"00002d20",
2891 => x"00002d20",
2892 => x"00002d28",
2893 => x"00002d28",
2894 => x"00002d30",
2895 => x"00002d30",
2896 => x"00002d38",
2897 => x"00002d38",
2898 => x"00002d40",
2899 => x"00002d40",
2900 => x"00002d48",
2901 => x"00002d48",
2902 => x"00002d50",
2903 => x"00002d50",
2904 => x"00002d58",
2905 => x"00002d58",
2906 => x"00002d60",
2907 => x"00002d60",
2908 => x"00002d68",
2909 => x"00002d68",
2910 => x"00002d70",
2911 => x"00002d70",
2912 => x"00002d78",
2913 => x"00002d78",
2914 => x"00002d80",
2915 => x"00002d80",
2916 => x"00002d88",
2917 => x"00002d88",
2918 => x"00002d90",
2919 => x"00002d90",
2920 => x"00002d98",
2921 => x"00002d98",
2922 => x"00002da0",
2923 => x"00002da0",
2924 => x"00002da8",
2925 => x"00002da8",
2926 => x"00002db0",
2927 => x"00002db0",
2928 => x"00002db8",
2929 => x"00002db8",
2930 => x"00002dc0",
2931 => x"00002dc0",
2932 => x"00002dc8",
2933 => x"00002dc8",
2934 => x"00002dd0",
2935 => x"00002dd0",
2936 => x"00002dd8",
2937 => x"00002dd8",
2938 => x"00002de0",
2939 => x"00002de0",
2940 => x"00002de8",
2941 => x"00002de8",
2942 => x"00002df0",
2943 => x"00002df0",
2944 => x"00002df8",
2945 => x"00002df8",
2946 => x"00002e00",
2947 => x"00002e00",
2948 => x"00002e08",
2949 => x"00002e08",
2950 => x"00002e10",
2951 => x"00002e10",
2952 => x"00002e18",
2953 => x"00002e18",
2954 => x"00002e20",
2955 => x"00002e20",
2956 => x"00002e28",
2957 => x"00002e28",
2958 => x"00002e30",
2959 => x"00002e30",
2960 => x"00002e38",
2961 => x"00002e38",
2962 => x"00002e40",
2963 => x"00002e40",
2964 => x"00002660",
2965 => x"ffffffff",
2966 => x"00000000",
2967 => x"ffffffff",
2968 => x"00000000",
2969 => x"00000000",
others => x"00000000"
);
begin
do_port_a:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if (a_we_i='1') and (b_we_i='1') and (a_addr_i=b_addr_i) and (a_write_i/=b_write_i) then
report "DualPortRAM write collision" severity failure;
end if;
iaddr:=to_integer(a_addr_i);
if a_we_i='1' then
ram(iaddr):=a_write_i;
a_read_o <= a_write_i;
else
a_read_o <= ram(iaddr);
end if;
end if;
end process do_port_a;
do_port_b:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
iaddr:=to_integer(b_addr_i);
if b_we_i='1' then
ram(iaddr):=b_write_i;
b_read_o <= b_write_i;
else
b_read_o <= ram(iaddr);
end if;
end if;
end process do_port_b;
end architecture DualPort_Arch; -- Entity: DualPortRAM
|
-----------------------------------------------------------------------------
-- Ethernet/PCI bridge Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use work.config.all;
entity netcard is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
emdio : inout std_logic;
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_ulogic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_irq : out std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic
);
end;
architecture rtl of netcard is
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, pciclk : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal dui : uart_in_type;
signal duo : uart_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal tck, tms, tdi, tdo : std_ulogic;
signal irqn, lclk, gnd : std_logic;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahb : integer := CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= resetn; cgi.pllref <= '0';
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0,
0, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK)
port map (lclk, pci_clk, clkm, open, open, open, pciclk, cgi, cgo);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (nahbm => maxahb, nahbs => 4, ioen => 0)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e0 : greth generic map(hindex => log2x(CFG_PCI),
pindex => 0, paddr => 11, pirq => 11, memtech => memtech)
port map( rst => rstn, clk => clk, ahbmi => ahbmi, ahbmo => ahbmo(log2x(CFG_PCI)),
apbi => apbi, apbo => apbo(0), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
irqn <= ahbso(3).hirq(11);
irq_pad : odpad generic map (tech => padtech, level => pci33)
port map (pci_irq, irqn);
----------------------------------------------------------------------
--- AHB/APB Bridge -------------------------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 0, haddr => 16#800#)
port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo );
----------------------------------------------------------------------
--- AHB RAM --------------------------------------------------------
----------------------------------------------------------------------
ram0 : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 2, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(2));
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => 0,
device_id => 16#0210#, vendor_id => 16#16E3#)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(0));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => 0,
fifodepth => 6, device_id => 16#0210#, vendor_id => 16#16E3#,
hslvndx => 1, pindex => 6, paddr => 2, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(6),
ahbmi, ahbmo(0), ahbsi, ahbso(1));
end generate;
pci_dma : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => 1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => 0,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(1),
apbi, apbo(4), ahbmi, ahbmo(0), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (memtech => memtech, pindex => 3,
paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(3));
end generate;
pcipads0 : pcipads generic map (padtech)
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
----------------------------------------------------------------------
--- Optional DSU UARTs ----------------------------------------------
----------------------------------------------------------------------
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => log2x(CFG_PCI)+CFG_GRETH, pindex => 1, paddr => 1)
port map (rstn, clkm, dui, duo, apbi, apbo(1), ahbmi, ahbmo(log2x(CFG_PCI)+CFG_GRETH));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech,
hindex => log2x(CFG_PCI)+CFG_GRETH+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi,
ahbmo(log2x(CFG_PCI)+CFG_GRETH+CFG_AHB_UART), open, open, open,
open, open, open, open, gnd);
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "Ethernet/PCI Network Card Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity computation is
end entity;
architecture foo of computation is
signal size :std_logic_vector (7 downto 0) := "00001001";
-- architecture declarative part
begin
UNLABELLED:
process
variable N: integer := to_integer(unsigned'("00000111")) ; ---WORKING
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "UNLABELLED memory left bound = " &integer'image(N);
wait;
end process;
OTHER:
process
variable N: integer:= to_integer (unsigned(size)) ; -- Not working
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "OTHER memory left bound = " &integer'image(N);
wait;
end process;
size <= "01000010" after 1 ns;
block1: block is
constant N: integer:= to_integer (unsigned(size)) ; -- Error
constant M: integer := size'length; -- OK
constant P: boolean := size'event; -- Error
begin
end block;
end architecture;
architecture bar of computation is
signal N : integer := 5;
signal bad : bit_vector(1 to N); -- Error
signal x : integer range 1 to N; -- Error
begin
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity computation is
end entity;
architecture foo of computation is
signal size :std_logic_vector (7 downto 0) := "00001001";
-- architecture declarative part
begin
UNLABELLED:
process
variable N: integer := to_integer(unsigned'("00000111")) ; ---WORKING
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "UNLABELLED memory left bound = " &integer'image(N);
wait;
end process;
OTHER:
process
variable N: integer:= to_integer (unsigned(size)) ; -- Not working
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "OTHER memory left bound = " &integer'image(N);
wait;
end process;
size <= "01000010" after 1 ns;
block1: block is
constant N: integer:= to_integer (unsigned(size)) ; -- Error
constant M: integer := size'length; -- OK
constant P: boolean := size'event; -- Error
begin
end block;
end architecture;
architecture bar of computation is
signal N : integer := 5;
signal bad : bit_vector(1 to N); -- Error
signal x : integer range 1 to N; -- Error
begin
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity computation is
end entity;
architecture foo of computation is
signal size :std_logic_vector (7 downto 0) := "00001001";
-- architecture declarative part
begin
UNLABELLED:
process
variable N: integer := to_integer(unsigned'("00000111")) ; ---WORKING
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "UNLABELLED memory left bound = " &integer'image(N);
wait;
end process;
OTHER:
process
variable N: integer:= to_integer (unsigned(size)) ; -- Not working
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "OTHER memory left bound = " &integer'image(N);
wait;
end process;
size <= "01000010" after 1 ns;
block1: block is
constant N: integer:= to_integer (unsigned(size)) ; -- Error
constant M: integer := size'length; -- OK
constant P: boolean := size'event; -- Error
begin
end block;
end architecture;
architecture bar of computation is
signal N : integer := 5;
signal bad : bit_vector(1 to N); -- Error
signal x : integer range 1 to N; -- Error
begin
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity computation is
end entity;
architecture foo of computation is
signal size :std_logic_vector (7 downto 0) := "00001001";
-- architecture declarative part
begin
UNLABELLED:
process
variable N: integer := to_integer(unsigned'("00000111")) ; ---WORKING
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "UNLABELLED memory left bound = " &integer'image(N);
wait;
end process;
OTHER:
process
variable N: integer:= to_integer (unsigned(size)) ; -- Not working
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "OTHER memory left bound = " &integer'image(N);
wait;
end process;
size <= "01000010" after 1 ns;
block1: block is
constant N: integer:= to_integer (unsigned(size)) ; -- Error
constant M: integer := size'length; -- OK
constant P: boolean := size'event; -- Error
begin
end block;
end architecture;
architecture bar of computation is
signal N : integer := 5;
signal bad : bit_vector(1 to N); -- Error
signal x : integer range 1 to N; -- Error
begin
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port2 Interface Signals
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0) ;
p2_cmd_bl : in std_logic_vector(5 downto 0) ;
p2_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
--Data Rd Port signals
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0) ;
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0) ;
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
--User Port3 Interface Signals
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0) ;
p3_cmd_bl : in std_logic_vector(5 downto 0) ;
p3_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
--Data Wr Port signals
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0) ;
p3_wr_data : in std_logic_vector(31 downto 0) ;
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0) ;
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "001100";
constant C_PORT_CONFIG : string := "B32_B32_R32_W32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_92_ddr2_s6, Coregen 14.2";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr2_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR2_SDRAM, CLK_PERIOD=3200, MEMORY_PART=mt47h64m16xx-25e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=FULL, RTT_NOM=50OHMS, DQS#_ENABLE=YES, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port2_Port3, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '0',
p0_cmd_clk => '0',
p0_cmd_en => '0',
p0_cmd_instr => (others => '0'),
p0_cmd_bl => (others => '0'),
p0_cmd_byte_addr => (others => '0'),
p0_cmd_empty => open,
p0_cmd_full => open,
p0_rd_clk => '0',
p0_rd_en => '0',
p0_rd_data => open,
p0_rd_full => open,
p0_rd_empty => open,
p0_rd_count => open,
p0_rd_overflow => open,
p0_rd_error => open,
p0_wr_clk => '0',
p0_wr_en => '0',
p0_wr_mask => (others => '0'),
p0_wr_data => (others => '0'),
p0_wr_full => open,
p0_wr_empty => open,
p0_wr_count => open,
p0_wr_underrun => open,
p0_wr_error => open,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '1',
p2_cmd_clk => p2_cmd_clk,
p2_cmd_en => p2_cmd_en,
p2_cmd_instr => p2_cmd_instr,
p2_cmd_bl => p2_cmd_bl,
p2_cmd_byte_addr => p2_cmd_byte_addr,
p2_cmd_empty => p2_cmd_empty,
p2_cmd_full => p2_cmd_full,
p2_rd_clk => p2_rd_clk,
p2_rd_en => p2_rd_en,
p2_rd_data => p2_rd_data,
p2_rd_full => p2_rd_full,
p2_rd_empty => p2_rd_empty,
p2_rd_count => p2_rd_count,
p2_rd_overflow => p2_rd_overflow,
p2_rd_error => p2_rd_error,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '1',
p3_cmd_clk => p3_cmd_clk,
p3_cmd_en => p3_cmd_en,
p3_cmd_instr => p3_cmd_instr,
p3_cmd_bl => p3_cmd_bl,
p3_cmd_byte_addr => p3_cmd_byte_addr,
p3_cmd_empty => p3_cmd_empty,
p3_cmd_full => p3_cmd_full,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => p3_wr_clk,
p3_wr_en => p3_wr_en,
p3_wr_mask => p3_wr_mask,
p3_wr_data => p3_wr_data,
p3_wr_full => p3_wr_full,
p3_wr_empty => p3_wr_empty,
p3_wr_count => p3_wr_count,
p3_wr_underrun => p3_wr_underrun,
p3_wr_error => p3_wr_error,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
--*****************************************************************************
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-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port2 Interface Signals
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0) ;
p2_cmd_bl : in std_logic_vector(5 downto 0) ;
p2_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
--Data Rd Port signals
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0) ;
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0) ;
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
--User Port3 Interface Signals
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0) ;
p3_cmd_bl : in std_logic_vector(5 downto 0) ;
p3_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
--Data Wr Port signals
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0) ;
p3_wr_data : in std_logic_vector(31 downto 0) ;
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0) ;
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "001100";
constant C_PORT_CONFIG : string := "B32_B32_R32_W32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_92_ddr2_s6, Coregen 14.2";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr2_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR2_SDRAM, CLK_PERIOD=3200, MEMORY_PART=mt47h64m16xx-25e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=FULL, RTT_NOM=50OHMS, DQS#_ENABLE=YES, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port2_Port3, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '0',
p0_cmd_clk => '0',
p0_cmd_en => '0',
p0_cmd_instr => (others => '0'),
p0_cmd_bl => (others => '0'),
p0_cmd_byte_addr => (others => '0'),
p0_cmd_empty => open,
p0_cmd_full => open,
p0_rd_clk => '0',
p0_rd_en => '0',
p0_rd_data => open,
p0_rd_full => open,
p0_rd_empty => open,
p0_rd_count => open,
p0_rd_overflow => open,
p0_rd_error => open,
p0_wr_clk => '0',
p0_wr_en => '0',
p0_wr_mask => (others => '0'),
p0_wr_data => (others => '0'),
p0_wr_full => open,
p0_wr_empty => open,
p0_wr_count => open,
p0_wr_underrun => open,
p0_wr_error => open,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '1',
p2_cmd_clk => p2_cmd_clk,
p2_cmd_en => p2_cmd_en,
p2_cmd_instr => p2_cmd_instr,
p2_cmd_bl => p2_cmd_bl,
p2_cmd_byte_addr => p2_cmd_byte_addr,
p2_cmd_empty => p2_cmd_empty,
p2_cmd_full => p2_cmd_full,
p2_rd_clk => p2_rd_clk,
p2_rd_en => p2_rd_en,
p2_rd_data => p2_rd_data,
p2_rd_full => p2_rd_full,
p2_rd_empty => p2_rd_empty,
p2_rd_count => p2_rd_count,
p2_rd_overflow => p2_rd_overflow,
p2_rd_error => p2_rd_error,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '1',
p3_cmd_clk => p3_cmd_clk,
p3_cmd_en => p3_cmd_en,
p3_cmd_instr => p3_cmd_instr,
p3_cmd_bl => p3_cmd_bl,
p3_cmd_byte_addr => p3_cmd_byte_addr,
p3_cmd_empty => p3_cmd_empty,
p3_cmd_full => p3_cmd_full,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => p3_wr_clk,
p3_wr_en => p3_wr_en,
p3_wr_mask => p3_wr_mask,
p3_wr_data => p3_wr_data,
p3_wr_full => p3_wr_full,
p3_wr_empty => p3_wr_empty,
p3_wr_count => p3_wr_count,
p3_wr_underrun => p3_wr_underrun,
p3_wr_error => p3_wr_error,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port2 Interface Signals
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0) ;
p2_cmd_bl : in std_logic_vector(5 downto 0) ;
p2_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
--Data Rd Port signals
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0) ;
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0) ;
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
--User Port3 Interface Signals
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0) ;
p3_cmd_bl : in std_logic_vector(5 downto 0) ;
p3_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
--Data Wr Port signals
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0) ;
p3_wr_data : in std_logic_vector(31 downto 0) ;
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0) ;
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "001100";
constant C_PORT_CONFIG : string := "B32_B32_R32_W32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_92_ddr2_s6, Coregen 14.2";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr2_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR2_SDRAM, CLK_PERIOD=3200, MEMORY_PART=mt47h64m16xx-25e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=FULL, RTT_NOM=50OHMS, DQS#_ENABLE=YES, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port2_Port3, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '0',
p0_cmd_clk => '0',
p0_cmd_en => '0',
p0_cmd_instr => (others => '0'),
p0_cmd_bl => (others => '0'),
p0_cmd_byte_addr => (others => '0'),
p0_cmd_empty => open,
p0_cmd_full => open,
p0_rd_clk => '0',
p0_rd_en => '0',
p0_rd_data => open,
p0_rd_full => open,
p0_rd_empty => open,
p0_rd_count => open,
p0_rd_overflow => open,
p0_rd_error => open,
p0_wr_clk => '0',
p0_wr_en => '0',
p0_wr_mask => (others => '0'),
p0_wr_data => (others => '0'),
p0_wr_full => open,
p0_wr_empty => open,
p0_wr_count => open,
p0_wr_underrun => open,
p0_wr_error => open,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '1',
p2_cmd_clk => p2_cmd_clk,
p2_cmd_en => p2_cmd_en,
p2_cmd_instr => p2_cmd_instr,
p2_cmd_bl => p2_cmd_bl,
p2_cmd_byte_addr => p2_cmd_byte_addr,
p2_cmd_empty => p2_cmd_empty,
p2_cmd_full => p2_cmd_full,
p2_rd_clk => p2_rd_clk,
p2_rd_en => p2_rd_en,
p2_rd_data => p2_rd_data,
p2_rd_full => p2_rd_full,
p2_rd_empty => p2_rd_empty,
p2_rd_count => p2_rd_count,
p2_rd_overflow => p2_rd_overflow,
p2_rd_error => p2_rd_error,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '1',
p3_cmd_clk => p3_cmd_clk,
p3_cmd_en => p3_cmd_en,
p3_cmd_instr => p3_cmd_instr,
p3_cmd_bl => p3_cmd_bl,
p3_cmd_byte_addr => p3_cmd_byte_addr,
p3_cmd_empty => p3_cmd_empty,
p3_cmd_full => p3_cmd_full,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => p3_wr_clk,
p3_wr_en => p3_wr_en,
p3_wr_mask => p3_wr_mask,
p3_wr_data => p3_wr_data,
p3_wr_full => p3_wr_full,
p3_wr_empty => p3_wr_empty,
p3_wr_count => p3_wr_count,
p3_wr_underrun => p3_wr_underrun,
p3_wr_error => p3_wr_error,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port2 Interface Signals
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0) ;
p2_cmd_bl : in std_logic_vector(5 downto 0) ;
p2_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
--Data Rd Port signals
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0) ;
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0) ;
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
--User Port3 Interface Signals
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0) ;
p3_cmd_bl : in std_logic_vector(5 downto 0) ;
p3_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
--Data Wr Port signals
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0) ;
p3_wr_data : in std_logic_vector(31 downto 0) ;
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0) ;
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "001100";
constant C_PORT_CONFIG : string := "B32_B32_R32_W32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_92_ddr2_s6, Coregen 14.2";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr2_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR2_SDRAM, CLK_PERIOD=3200, MEMORY_PART=mt47h64m16xx-25e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=FULL, RTT_NOM=50OHMS, DQS#_ENABLE=YES, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port2_Port3, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '0',
p0_cmd_clk => '0',
p0_cmd_en => '0',
p0_cmd_instr => (others => '0'),
p0_cmd_bl => (others => '0'),
p0_cmd_byte_addr => (others => '0'),
p0_cmd_empty => open,
p0_cmd_full => open,
p0_rd_clk => '0',
p0_rd_en => '0',
p0_rd_data => open,
p0_rd_full => open,
p0_rd_empty => open,
p0_rd_count => open,
p0_rd_overflow => open,
p0_rd_error => open,
p0_wr_clk => '0',
p0_wr_en => '0',
p0_wr_mask => (others => '0'),
p0_wr_data => (others => '0'),
p0_wr_full => open,
p0_wr_empty => open,
p0_wr_count => open,
p0_wr_underrun => open,
p0_wr_error => open,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '1',
p2_cmd_clk => p2_cmd_clk,
p2_cmd_en => p2_cmd_en,
p2_cmd_instr => p2_cmd_instr,
p2_cmd_bl => p2_cmd_bl,
p2_cmd_byte_addr => p2_cmd_byte_addr,
p2_cmd_empty => p2_cmd_empty,
p2_cmd_full => p2_cmd_full,
p2_rd_clk => p2_rd_clk,
p2_rd_en => p2_rd_en,
p2_rd_data => p2_rd_data,
p2_rd_full => p2_rd_full,
p2_rd_empty => p2_rd_empty,
p2_rd_count => p2_rd_count,
p2_rd_overflow => p2_rd_overflow,
p2_rd_error => p2_rd_error,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '1',
p3_cmd_clk => p3_cmd_clk,
p3_cmd_en => p3_cmd_en,
p3_cmd_instr => p3_cmd_instr,
p3_cmd_bl => p3_cmd_bl,
p3_cmd_byte_addr => p3_cmd_byte_addr,
p3_cmd_empty => p3_cmd_empty,
p3_cmd_full => p3_cmd_full,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => p3_wr_clk,
p3_wr_en => p3_wr_en,
p3_wr_mask => p3_wr_mask,
p3_wr_data => p3_wr_data,
p3_wr_full => p3_wr_full,
p3_wr_empty => p3_wr_empty,
p3_wr_count => p3_wr_count,
p3_wr_underrun => p3_wr_underrun,
p3_wr_error => p3_wr_error,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port2 Interface Signals
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0) ;
p2_cmd_bl : in std_logic_vector(5 downto 0) ;
p2_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
--Data Rd Port signals
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0) ;
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0) ;
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
--User Port3 Interface Signals
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0) ;
p3_cmd_bl : in std_logic_vector(5 downto 0) ;
p3_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
--Data Wr Port signals
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0) ;
p3_wr_data : in std_logic_vector(31 downto 0) ;
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0) ;
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "001100";
constant C_PORT_CONFIG : string := "B32_B32_R32_W32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_92_ddr2_s6, Coregen 14.2";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr2_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR2_SDRAM, CLK_PERIOD=3200, MEMORY_PART=mt47h64m16xx-25e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=FULL, RTT_NOM=50OHMS, DQS#_ENABLE=YES, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port2_Port3, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '0',
p0_cmd_clk => '0',
p0_cmd_en => '0',
p0_cmd_instr => (others => '0'),
p0_cmd_bl => (others => '0'),
p0_cmd_byte_addr => (others => '0'),
p0_cmd_empty => open,
p0_cmd_full => open,
p0_rd_clk => '0',
p0_rd_en => '0',
p0_rd_data => open,
p0_rd_full => open,
p0_rd_empty => open,
p0_rd_count => open,
p0_rd_overflow => open,
p0_rd_error => open,
p0_wr_clk => '0',
p0_wr_en => '0',
p0_wr_mask => (others => '0'),
p0_wr_data => (others => '0'),
p0_wr_full => open,
p0_wr_empty => open,
p0_wr_count => open,
p0_wr_underrun => open,
p0_wr_error => open,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '1',
p2_cmd_clk => p2_cmd_clk,
p2_cmd_en => p2_cmd_en,
p2_cmd_instr => p2_cmd_instr,
p2_cmd_bl => p2_cmd_bl,
p2_cmd_byte_addr => p2_cmd_byte_addr,
p2_cmd_empty => p2_cmd_empty,
p2_cmd_full => p2_cmd_full,
p2_rd_clk => p2_rd_clk,
p2_rd_en => p2_rd_en,
p2_rd_data => p2_rd_data,
p2_rd_full => p2_rd_full,
p2_rd_empty => p2_rd_empty,
p2_rd_count => p2_rd_count,
p2_rd_overflow => p2_rd_overflow,
p2_rd_error => p2_rd_error,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '1',
p3_cmd_clk => p3_cmd_clk,
p3_cmd_en => p3_cmd_en,
p3_cmd_instr => p3_cmd_instr,
p3_cmd_bl => p3_cmd_bl,
p3_cmd_byte_addr => p3_cmd_byte_addr,
p3_cmd_empty => p3_cmd_empty,
p3_cmd_full => p3_cmd_full,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => p3_wr_clk,
p3_wr_en => p3_wr_en,
p3_wr_mask => p3_wr_mask,
p3_wr_data => p3_wr_data,
p3_wr_full => p3_wr_full,
p3_wr_empty => p3_wr_empty,
p3_wr_count => p3_wr_count,
p3_wr_underrun => p3_wr_underrun,
p3_wr_error => p3_wr_error,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port2 Interface Signals
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0) ;
p2_cmd_bl : in std_logic_vector(5 downto 0) ;
p2_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
--Data Rd Port signals
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0) ;
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0) ;
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
--User Port3 Interface Signals
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0) ;
p3_cmd_bl : in std_logic_vector(5 downto 0) ;
p3_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
--Data Wr Port signals
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0) ;
p3_wr_data : in std_logic_vector(31 downto 0) ;
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0) ;
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "001100";
constant C_PORT_CONFIG : string := "B32_B32_R32_W32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_92_ddr2_s6, Coregen 14.2";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr2_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR2_SDRAM, CLK_PERIOD=3200, MEMORY_PART=mt47h64m16xx-25e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=FULL, RTT_NOM=50OHMS, DQS#_ENABLE=YES, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port2_Port3, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '0',
p0_cmd_clk => '0',
p0_cmd_en => '0',
p0_cmd_instr => (others => '0'),
p0_cmd_bl => (others => '0'),
p0_cmd_byte_addr => (others => '0'),
p0_cmd_empty => open,
p0_cmd_full => open,
p0_rd_clk => '0',
p0_rd_en => '0',
p0_rd_data => open,
p0_rd_full => open,
p0_rd_empty => open,
p0_rd_count => open,
p0_rd_overflow => open,
p0_rd_error => open,
p0_wr_clk => '0',
p0_wr_en => '0',
p0_wr_mask => (others => '0'),
p0_wr_data => (others => '0'),
p0_wr_full => open,
p0_wr_empty => open,
p0_wr_count => open,
p0_wr_underrun => open,
p0_wr_error => open,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '1',
p2_cmd_clk => p2_cmd_clk,
p2_cmd_en => p2_cmd_en,
p2_cmd_instr => p2_cmd_instr,
p2_cmd_bl => p2_cmd_bl,
p2_cmd_byte_addr => p2_cmd_byte_addr,
p2_cmd_empty => p2_cmd_empty,
p2_cmd_full => p2_cmd_full,
p2_rd_clk => p2_rd_clk,
p2_rd_en => p2_rd_en,
p2_rd_data => p2_rd_data,
p2_rd_full => p2_rd_full,
p2_rd_empty => p2_rd_empty,
p2_rd_count => p2_rd_count,
p2_rd_overflow => p2_rd_overflow,
p2_rd_error => p2_rd_error,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '1',
p3_cmd_clk => p3_cmd_clk,
p3_cmd_en => p3_cmd_en,
p3_cmd_instr => p3_cmd_instr,
p3_cmd_bl => p3_cmd_bl,
p3_cmd_byte_addr => p3_cmd_byte_addr,
p3_cmd_empty => p3_cmd_empty,
p3_cmd_full => p3_cmd_full,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => p3_wr_clk,
p3_wr_en => p3_wr_en,
p3_wr_mask => p3_wr_mask,
p3_wr_data => p3_wr_data,
p3_wr_full => p3_wr_full,
p3_wr_empty => p3_wr_empty,
p3_wr_count => p3_wr_count,
p3_wr_underrun => p3_wr_underrun,
p3_wr_error => p3_wr_error,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2157.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02157ent IS
END c07s02b04x00p21n01i02157ent;
ARCHITECTURE c07s02b04x00p21n01i02157arch OF c07s02b04x00p21n01i02157ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_1 is severity_level_v (1 to 1);
SUBTYPE severity_level_null is severity_level_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : severity_level_1;
variable l_operand : severity_level_null;
variable r_operand : severity_level := NOTE ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1)=NOTE)
report "***PASSED TEST: c07s02b04x00p21n01i02157"
severity NOTE;
assert (result(1)=NOTE)
report "***FAILED TEST: c07s02b04x00p21n01i02157 - Concatenation of null and SEVERITY_LEVEL element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02157arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2157.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02157ent IS
END c07s02b04x00p21n01i02157ent;
ARCHITECTURE c07s02b04x00p21n01i02157arch OF c07s02b04x00p21n01i02157ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_1 is severity_level_v (1 to 1);
SUBTYPE severity_level_null is severity_level_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : severity_level_1;
variable l_operand : severity_level_null;
variable r_operand : severity_level := NOTE ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1)=NOTE)
report "***PASSED TEST: c07s02b04x00p21n01i02157"
severity NOTE;
assert (result(1)=NOTE)
report "***FAILED TEST: c07s02b04x00p21n01i02157 - Concatenation of null and SEVERITY_LEVEL element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02157arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2157.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02157ent IS
END c07s02b04x00p21n01i02157ent;
ARCHITECTURE c07s02b04x00p21n01i02157arch OF c07s02b04x00p21n01i02157ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_1 is severity_level_v (1 to 1);
SUBTYPE severity_level_null is severity_level_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : severity_level_1;
variable l_operand : severity_level_null;
variable r_operand : severity_level := NOTE ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1)=NOTE)
report "***PASSED TEST: c07s02b04x00p21n01i02157"
severity NOTE;
assert (result(1)=NOTE)
report "***FAILED TEST: c07s02b04x00p21n01i02157 - Concatenation of null and SEVERITY_LEVEL element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02157arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spictrl
-- File: spictrl.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Wrapper for SPICTRL core
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.spi.all;
entity spictrl is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0; -- APB address
pmask : integer := 16#fff#; -- APB mask
pirq : integer := 0; -- interrupt index
-- SPI controller configuration
fdepth : integer range 1 to 7 := 1; -- FIFO depth is 2^fdepth
slvselen : integer range 0 to 1 := 0; -- Slave select register enable
slvselsz : integer range 1 to 32 := 1; -- Number of slave select signals
oepol : integer range 0 to 1 := 0; -- Output enable polarity
odmode : integer range 0 to 1 := 0; -- Support open drain mode, only
-- set if pads are i/o or od pads.
automode : integer range 0 to 1 := 0; -- Enable automated transfer mode
acntbits : integer range 1 to 32 := 32; -- # Bits in am period counter
aslvsel : integer range 0 to 1 := 0; -- Automatic slave select
twen : integer range 0 to 1 := 1; -- Enable three wire mode
maxwlen : integer range 0 to 15 := 0; -- Maximum word length
netlist : integer := 0; -- Use netlist (tech)
syncram : integer range 0 to 1 := 1; -- Use SYNCRAM for buffers
memtech : integer := 0; -- Memory technology
ft : integer range 0 to 2 := 0; -- Fault-Tolerance
scantest : integer range 0 to 1 := 0; -- Scan test support
syncrst : integer range 0 to 1 := 0; -- Use only sync reset
automask0 : integer := 0; -- Mask 0 for automated transfers
automask1 : integer := 0; -- Mask 1 for automated transfers
automask2 : integer := 0; -- Mask 2 for automated transfers
automask3 : integer := 0; -- Mask 3 for automated transfers
ignore : integer range 0 to 1 := 0 -- Ignore samples
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
end entity spictrl;
architecture rtl of spictrl is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant SPICTRL_REV : integer := 5;
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPICTRL, 0, SPICTRL_REV, pirq),
1 => apb_iobar(paddr, pmask));
-----------------------------------------------------------------------------
-- Component
-----------------------------------------------------------------------------
component spictrlx
generic (
rev : integer := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
syncram : integer range 0 to 1 := 1;
memtech : integer range 0 to NTECH := 0;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
syncrst : integer range 0 to 1 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0;
ignore : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spii_ignore : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end component;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal apbo_pirq : std_ulogic;
begin
ctrl_rtl : if netlist = 0 generate
rtlc : spictrlx
generic map (
rev => SPICTRL_REV,
fdepth => fdepth,
slvselen => slvselen,
slvselsz => slvselsz,
oepol => oepol,
odmode => odmode,
automode => automode,
acntbits => acntbits,
aslvsel => aslvsel,
twen => twen,
maxwlen => maxwlen,
syncram => syncram,
memtech => memtech,
ft => ft,
scantest => scantest,
syncrst => syncrst,
automask0 => automask0,
automask1 => automask1,
automask2 => automask2,
automask3 => automask3,
ignore => ignore)
port map (
rstn => rstn,
clk => clk,
-- APB signals
apbi_psel => apbi.psel(pindex),
apbi_penable => apbi.penable,
apbi_paddr => apbi.paddr,
apbi_pwrite => apbi.pwrite,
apbi_pwdata => apbi.pwdata,
apbi_testen => apbi.testen,
apbi_testrst => apbi.testrst,
apbi_scanen => apbi.scanen,
apbi_testoen => apbi.testoen,
apbo_prdata => apbo.prdata,
apbo_pirq => apbo_pirq,
-- SPI signals
spii_miso => spii.miso,
spii_mosi => spii.mosi,
spii_sck => spii.sck,
spii_spisel => spii.spisel,
spii_astart => spii.astart,
spii_cstart => spii.cstart,
spii_ignore => spii.ignore,
spio_miso => spio.miso,
spio_misooen => spio.misooen,
spio_mosi => spio.mosi,
spio_mosioen => spio.mosioen,
spio_sck => spio.sck,
spio_sckoen => spio.sckoen,
spio_enable => spio.enable,
spio_astart => spio.astart,
spio_aready => spio.aready,
slvsel => slvsel);
end generate ctrl_rtl;
ctrl_netlist : if netlist /= 0 generate
netlc : spictrl_net
generic map (
tech => netlist,
fdepth => fdepth,
slvselen => slvselen,
slvselsz => slvselsz,
oepol => oepol,
odmode => odmode,
automode => automode,
acntbits => acntbits,
aslvsel => aslvsel,
twen => twen,
maxwlen => maxwlen,
automask0 => automask0,
automask1 => automask1,
automask2 => automask2,
automask3 => automask3)
port map (
rstn => rstn,
clk => clk,
-- APB signals
apbi_psel => apbi.psel(pindex),
apbi_penable => apbi.penable,
apbi_paddr => apbi.paddr,
apbi_pwrite => apbi.pwrite,
apbi_pwdata => apbi.pwdata,
apbi_testen => apbi.testen,
apbi_testrst => apbi.testrst,
apbi_scanen => apbi.scanen,
apbi_testoen => apbi.testoen,
apbo_prdata => apbo.prdata,
apbo_pirq => apbo_pirq,
-- SPI signals
spii_miso => spii.miso,
spii_mosi => spii.mosi,
spii_sck => spii.sck,
spii_spisel => spii.spisel,
spii_astart => spii.astart,
spii_cstart => spii.cstart,
spio_miso => spio.miso,
spio_misooen => spio.misooen,
spio_mosi => spio.mosi,
spio_mosioen => spio.mosioen,
spio_sck => spio.sck,
spio_sckoen => spio.sckoen,
spio_enable => spio.enable,
spio_astart => spio.astart,
spio_aready => spio.aready,
slvsel => slvsel);
end generate ctrl_netlist;
spio.ssn <= (others => '0');
irqgen : process(apbo_pirq)
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
irq := (others => '0'); irq(pirq) := apbo_pirq;
apbo.pirq <= irq;
end process;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"spictrl" & tost(pindex) & ": SPI controller, rev " &
tost(SPICTRL_REV) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
|
-- CTRL_CRLF
-- Carriage Return Line Fed bei Telegrammende in den zu sendenen Datenstrom einfügen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 10.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 10.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_CRLF_VHDL is
Port(BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, zu Daten Input, 8 bit
BYTE_OK : in std_logic; --Eingangsvariable, Byte OK
T_CMPLT : in std_logic; --Eingangsvariabel, Telegramm vollständig
BYTE_SEND : out std_logic_vector (7 downto 0); --Ausgangsvariable, zu sendene Daten, 8 bit
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_CRLF_VHDL;
architecture Behavioral of CTRL_CRLF_VHDL is
type TYPE_STATE is
(ST_CRLF_00, --Zustaende CTRL_CRLF
ST_CRLF_01,
ST_CRLF_02,
ST_CRLF_03);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal BYTE_IN_S : std_logic_vector (7 downto 0); --Eingangsvariable, Zwischengespeichern im Eingangsregister
signal BYTE_OK_S : std_logic; --Eingangsvariable, Zwischengespeichern im Eingangsregister
signal T_CMPLT_S : std_logic; --Eingangsvariabel, Zwischengespeichern im Eingangsregister
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then BYTE_IN_S <= BYTE_IN;
BYTE_OK_S <= BYTE_OK;
T_CMPLT_S <= T_CMPLT;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CRLF_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
else SV_M <= SV_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CRLF_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
end if;
end if;
end process;
CTRL_CRLF_PROC:process (BYTE_IN_S, BYTE_OK_S, T_CMPLT_S, SV) --Wenn Byte ok dann Output=Input, wenn Byte ok und Telegramm komplett dann OUTPUT=CRLF
begin
case SV is
when ST_CRLF_00 =>
if (BYTE_OK_S = '1')
then
--CR01
BYTE_SEND <= BYTE_IN_S; --Output=Input
n_sv <= ST_CRLF_01; --Zustandsübergang
else
--CR00
BYTE_SEND <= BYTE_IN_S; --Output=Input
n_sv <= ST_CRLF_00; --bleibt im Zustand
end if;
when ST_CRLF_01 =>
if (T_CMPLT_S = '1')
then
--CR02
BYTE_SEND <= x"0D"; --Carriage Return
n_SV <= ST_CRLF_02; --Zustandsübergang
else
--CR01
BYTE_SEND <= BYTE_IN_S; --Output=Input
n_sv <= ST_CRLF_01; --Zustandsübergang
end if;
when ST_CRLF_02 =>
--CR03
BYTE_SEND <= x"0A"; --Line Feed
n_SV <= ST_CRLF_00; --Zustandsübergang
when others =>
-- CR00
BYTE_SEND <= BYTE_IN_S; --Output=Input
n_SV <= ST_CRLF_00; --Zustandsübergang
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
--aktuellen Zustand anzeigen
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end process;
end Behavioral;
|
-- CTRL_CRLF
-- Carriage Return Line Fed bei Telegrammende in den zu sendenen Datenstrom einfügen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 10.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 10.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_CRLF_VHDL is
Port(BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, zu Daten Input, 8 bit
BYTE_OK : in std_logic; --Eingangsvariable, Byte OK
T_CMPLT : in std_logic; --Eingangsvariabel, Telegramm vollständig
BYTE_SEND : out std_logic_vector (7 downto 0); --Ausgangsvariable, zu sendene Daten, 8 bit
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_CRLF_VHDL;
architecture Behavioral of CTRL_CRLF_VHDL is
type TYPE_STATE is
(ST_CRLF_00, --Zustaende CTRL_CRLF
ST_CRLF_01,
ST_CRLF_02,
ST_CRLF_03);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal BYTE_IN_S : std_logic_vector (7 downto 0); --Eingangsvariable, Zwischengespeichern im Eingangsregister
signal BYTE_OK_S : std_logic; --Eingangsvariable, Zwischengespeichern im Eingangsregister
signal T_CMPLT_S : std_logic; --Eingangsvariabel, Zwischengespeichern im Eingangsregister
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then BYTE_IN_S <= BYTE_IN;
BYTE_OK_S <= BYTE_OK;
T_CMPLT_S <= T_CMPLT;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CRLF_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
else SV_M <= SV_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CRLF_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
end if;
end if;
end process;
CTRL_CRLF_PROC:process (BYTE_IN_S, BYTE_OK_S, T_CMPLT_S, SV) --Wenn Byte ok dann Output=Input, wenn Byte ok und Telegramm komplett dann OUTPUT=CRLF
begin
case SV is
when ST_CRLF_00 =>
if (BYTE_OK_S = '1')
then
--CR01
BYTE_SEND <= BYTE_IN_S; --Output=Input
n_sv <= ST_CRLF_01; --Zustandsübergang
else
--CR00
BYTE_SEND <= BYTE_IN_S; --Output=Input
n_sv <= ST_CRLF_00; --bleibt im Zustand
end if;
when ST_CRLF_01 =>
if (T_CMPLT_S = '1')
then
--CR02
BYTE_SEND <= x"0D"; --Carriage Return
n_SV <= ST_CRLF_02; --Zustandsübergang
else
--CR01
BYTE_SEND <= BYTE_IN_S; --Output=Input
n_sv <= ST_CRLF_01; --Zustandsübergang
end if;
when ST_CRLF_02 =>
--CR03
BYTE_SEND <= x"0A"; --Line Feed
n_SV <= ST_CRLF_00; --Zustandsübergang
when others =>
-- CR00
BYTE_SEND <= BYTE_IN_S; --Output=Input
n_SV <= ST_CRLF_00; --Zustandsübergang
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
--aktuellen Zustand anzeigen
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end process;
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity finalproject_mm_interconnect_0_router_001 is
port(
clk : in vl_logic;
reset : in vl_logic;
sink_valid : in vl_logic;
sink_data : in vl_logic_vector(104 downto 0);
sink_startofpacket: in vl_logic;
sink_endofpacket: in vl_logic;
sink_ready : out vl_logic;
src_valid : out vl_logic;
src_data : out vl_logic_vector(104 downto 0);
src_channel : out vl_logic_vector(5 downto 0);
src_startofpacket: out vl_logic;
src_endofpacket : out vl_logic;
src_ready : in vl_logic
);
end finalproject_mm_interconnect_0_router_001;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Kofkplusone is
port (
clock : in std_logic;
PofVrefofVrefinv : in std_logic_vector(31 downto 0);
PofVactofVref : in std_logic_vector(31 downto 0);
Kofkplusone : out std_logic_vector(31 downto 0)
);
end k_ukf_Kofkplusone;
architecture struct of k_ukf_Kofkplusone is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
begin
M1 : k_ukf_mult port map
( clock => clock,
dataa => PofVactofVref,
datab => PofVrefofVrefinv,
result => Kofkplusone);
end struct;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
OPC : in STD_LOGIC_VECTOR (3 downto 0);
RA4 : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC;
OP2_SEL : out STD_LOGIC);
end DC_CTL;
architecture Behavioral of DC_CTL is
signal OP1, OP2 : STD_LOGIC := '0';
begin
OP1_SEL <= OP1;
OP2_SEL <= OP2;
process(CLK)
begin
if (CLK'Event and CLK = '1') then
-- case RA is
-- when RA4 => OP1 <= '1';
-- when others => OP1 <= '0';
-- end case;
--
-- case RB is
-- when RA4 => OP2 <= '1';
-- when others => OP2 <= '0';
-- end case;
if (RA4 = RA) then
OP1 <= '1';
OP2 <= '0';
elsif (RA4 = RB) then
OP2 <= '1';
OP1 <= '0';
else
OP1 <= '0';
OP2 <= '0';
end if;
end if;
end process;
end Behavioral;
|
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