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package pack is
function func(x : integer) return integer;
procedure proc(x : integer);
end package;
-------------------------------------------------------------------------------
entity duplicate is
end entity;
use work.pack.all;
architecture test of duplicate is
function func(x : integer) return integer is
begin
return x + 1;
end function;
procedure proc(x : integer) is
begin
end procedure;
begin
process is
begin
assert func(2) = 3; -- OK
assert pack.func(2) = 3; -- OK
proc(2); -- OK
pack.proc(2); -- OK
wait;
end process;
end architecture;
|
package pack is
function func(x : integer) return integer;
procedure proc(x : integer);
end package;
-------------------------------------------------------------------------------
entity duplicate is
end entity;
use work.pack.all;
architecture test of duplicate is
function func(x : integer) return integer is
begin
return x + 1;
end function;
procedure proc(x : integer) is
begin
end procedure;
begin
process is
begin
assert func(2) = 3; -- OK
assert pack.func(2) = 3; -- OK
proc(2); -- OK
pack.proc(2); -- OK
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_138x512_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(138-1 DOWNTO 0);
DOUT : OUT std_logic_vector(138-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
-------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
-------------------------------------------------------------------------------
--
-- unit name: GN4124 core arbiter (arbiter.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 12-08-2010
--
-- version: 0.1
--
-- description: Arbitrates PCIe accesses between Wishbone master,
-- L2P DMA master and P2L DMA master
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Add FF on data path and
-- change valid request logic
-- 26.02.2014 (theim) Changed priority order (swapped LDM <-> PDM)
-- 20.12.2016 (astaux) Apdapted for AXI-Stream bus
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity l2p_arbiter is
generic(
axis_data_width_c : integer := 64
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
wbm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
wbm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
wbm_arb_tlast_i : in std_logic;
wbm_arb_tvalid_i : in std_logic;
wbm_arb_tready_o : out std_logic;
wbm_arb_req_i : in std_logic;
arb_wbm_gnt_o : out std_logic;
---------------------------------------------------------
-- From P2L DMA master (pdm) to arbiter (arb)
pdm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
pdm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
pdm_arb_tlast_i : in std_logic;
pdm_arb_tvalid_i : in std_logic;
pdm_arb_tready_o : out std_logic;
pdm_arb_req_i : in std_logic;
arb_pdm_gnt_o : out std_logic;
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
ldm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
ldm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
ldm_arb_tlast_i : in std_logic;
ldm_arb_tvalid_i : in std_logic;
ldm_arb_tready_o : out std_logic;
ldm_arb_req_i : in std_logic;
arb_ldm_gnt_o : out std_logic;
---------------------------------------------------------
-- From arbiter (arb) to pcie_tx (tx)
axis_tx_tdata_o : out STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
axis_tx_tkeep_o : out STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
axis_tx_tuser_o : out STD_LOGIC_VECTOR (3 downto 0);
axis_tx_tlast_o : out STD_LOGIC;
axis_tx_tvalid_o : out STD_LOGIC;
axis_tx_tready_i : in STD_LOGIC;
---------------------------------------------------------
-- Debug
eop_do : out std_logic
);
end l2p_arbiter;
architecture rtl of l2p_arbiter is
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal wbm_arb_req_valid : std_logic;
signal pdm_arb_req_valid : std_logic;
signal ldm_arb_req_valid : std_logic;
signal arb_wbm_gnt : std_logic;
signal arb_pdm_gnt : std_logic;
signal arb_ldm_gnt : std_logic;
signal eop : std_logic; -- End of packet
signal axis_tx_tvalid_t : std_logic;
signal axis_tx_tlast_t : std_logic;
signal axis_tx_tdata_t : std_logic_vector(axis_data_width_c - 1 downto 0);
signal axis_tx_tkeep_t : std_logic_vector(axis_data_width_c/8 - 1 downto 0);
constant c_RST_ACTIVE : std_logic := '0';
begin
-- A request is valid only if the access not already granted to another source
wbm_arb_req_valid <= wbm_arb_req_i and (not(arb_pdm_gnt) and not(arb_ldm_gnt));
pdm_arb_req_valid <= pdm_arb_req_i and (not(arb_wbm_gnt) and not(arb_ldm_gnt));
ldm_arb_req_valid <= ldm_arb_req_i and (not(arb_wbm_gnt) and not(arb_pdm_gnt));
eop_do <= eop;
-- Detect end of packet to delimit the arbitration phase
-- eop <= ((arb_wbm_gnt and not(wbm_arb_dframe_i) and wbm_arb_valid_i) or
-- (arb_pdm_gnt and not(pdm_arb_dframe_i) and pdm_arb_valid_i) or
-- (arb_ldm_gnt and not(ldm_arb_dframe_i) and ldm_arb_valid_i));
process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
eop <= '0';
elsif rising_edge(clk_i) then
if ((arb_wbm_gnt = '1' and wbm_arb_tlast_i = '1') or
(arb_pdm_gnt = '1' and pdm_arb_tlast_i = '1') or
(arb_ldm_gnt = '1' and ldm_arb_tlast_i = '1')) then
eop <= '1';
else
eop <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Arbitration is started when a valid request is present and ends when the
-- EOP condition is detected
--
-- Strict priority arbitration scheme
-- Highest : WBM request
-- : LDM request
-- Lowest : PDM request
-----------------------------------------------------------------------------
process (clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif rising_edge(clk_i) then
--if (arb_req_valid = '1') then
if (eop = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif (wbm_arb_req_valid = '1') then
arb_wbm_gnt <= '1';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif (ldm_arb_req_valid = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '1';
elsif (pdm_arb_req_valid = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '1';
arb_ldm_gnt <= '0';
end if;
end if;
end process;
process (clk_i, rst_n_i)
begin
if rst_n_i = '0' then
axis_tx_tvalid_t <= '0';
axis_tx_tlast_t <= '0';
axis_tx_tdata_t <= (others => '0');
axis_tx_tkeep_t <= (others => '0');
elsif rising_edge(clk_i) then
if arb_wbm_gnt = '1' then
axis_tx_tvalid_t <= wbm_arb_tvalid_i;
axis_tx_tlast_t <= wbm_arb_tlast_i;
axis_tx_tdata_t <= wbm_arb_tdata_i;
axis_tx_tkeep_t <= wbm_arb_tkeep_i;
elsif arb_pdm_gnt = '1' then
axis_tx_tvalid_t <= pdm_arb_tvalid_i;
axis_tx_tlast_t <= pdm_arb_tlast_i;
axis_tx_tdata_t <= pdm_arb_tdata_i;
axis_tx_tkeep_t <= pdm_arb_tkeep_i;
elsif arb_ldm_gnt = '1' then
axis_tx_tvalid_t <= ldm_arb_tvalid_i;
axis_tx_tlast_t <= ldm_arb_tlast_i;
axis_tx_tdata_t <= ldm_arb_tdata_i;
axis_tx_tkeep_t <= ldm_arb_tkeep_i;
else
axis_tx_tvalid_t <= '0';
axis_tx_tlast_t <= '0';
axis_tx_tdata_t <= (others => '0');
axis_tx_tkeep_t <= (others => '0');
end if;
end if;
end process;
process (clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
axis_tx_tvalid_o <= '0';
axis_tx_tlast_o <= '0';
axis_tx_tdata_o <= (others => '0');
axis_tx_tkeep_o <= (others => '0');
elsif rising_edge(clk_i) then
axis_tx_tvalid_o <= axis_tx_tvalid_t;
axis_tx_tlast_o <= axis_tx_tlast_t;
axis_tx_tdata_o <= axis_tx_tdata_t;
axis_tx_tkeep_o <= axis_tx_tkeep_t;
end if;
end process;
arb_wbm_gnt_o <= arb_wbm_gnt;
arb_pdm_gnt_o <= arb_pdm_gnt;
arb_ldm_gnt_o <= arb_ldm_gnt;
wbm_arb_tready_o <= axis_tx_tready_i and arb_wbm_gnt;
pdm_arb_tready_o <= axis_tx_tready_i and arb_pdm_gnt;
ldm_arb_tready_o <= axis_tx_tready_i and arb_ldm_gnt;
axis_tx_tuser_o <= "0000";
end rtl;
|
-------------------------------------------------------------------------------
-- Model: SOLID CYLINDER for TIME-DOMAIN ANALYSIS
--
-- Author: Vladimir Kolchuzhin, MMT, TU Chemnitz
-- <[email protected]>
-- Date: 01.12.2014
-- Library:
-- kvl in hAMSter
-------------------------------------------------------------------------------
-- IEEE TRANSACTIONS ON MAGNETICS, VOL. 32, NO. I , JANUARY 1996
-- Lawrence J. Giacoletto
-- FREQUENCY AND TIME-DOMAIN ANALYSIS OF SKIN EFFECTS
-- for the cylinder conductor as a series element
-- for the cylinder conductor as a shunt element
-------------------------------------------------------------------------------
-- ID: cyl_cond.vhd
-- Rev. 1.0
-------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY user;
USE ieee.math_real.all;
USE ieee.electrical_systems.ALL;
entity wire is
generic (dc_value,ac_value,freq,phase:real); -- parameters:
port (terminal p,n:electrical); -- pins
end entity wire;
-------------------------------------------------------------------------------
-- for the cylinder conductor as a series element
architecture series_element of cyl_cond is
quantity v across i through p to n;
-- material properties
constant sigma:real:=37.0e-06; -- conductivity CuZr, S/m
constant mu:real:=1.0e-07*4.0*3.14; -- permeability: 4*pi*1e-7 H/m
-- geometry
constant R2:real:=10.0e-03; -- outside radius R2
constant L:real:=1.0; -- length of conductor, m
constant Rdc:real:=L/sigma/(3.14*R2*R2); -- dc resistance of conductor
constant omega_c:real:= 1.0/(sigma*mu*R2*R2); -- characteristic radian frequency
constant c0:real:= 1.0;
constant c1:real:= 0.125/omega_c;
constant c2:real:=-5.208333e-03/(omega_c**2);
constant c3:real:= 3.255208e-04/(omega_c**3);
constant c4:real:=-2.170139e-05/(omega_c**4);
constant c5:real:= 1.469365e-06/(omega_c**5);
constant c6:real:=-9.990874e-08/(omega_c**6);
constant c7:real:= 6.801447e-09/(omega_c**7);
constant c8:real:=-4.631829e-10/(omega_c**8);
constant c9:real:= 3.154634e-11/(omega_c**9);
begin
v == Rdc*(c0*i + c1*i'dot + c2*i'dot'dot + c3*i'dot'dot'dot + c4*i'dot'dot'dot'dot + c5*i'dot'dot'dot'dot'dot +
c6*i'dot'dot'dot'dot'dot'dot + c7*i'dot'dot'dot'dot'dot'dot'dot + c8*i'dot'dot'dot'dot'dot'dot'dot'dot +
c9*i'dot'dot'dot'dot'dot'dot'dot'dot'dot);
end architecture series_element;
-------------------------------------------------------------------------------
-- for the cylinder conductor as a shunt element
architecture shunt_element of cyl_cond is
quantity v across i through p to n;
-- material properties
constant sigma:real:=37.0e-06; -- conductivity CuZr, S/m
constant mu:real:=1.0e-07*4.0*3.14; -- permeability: 4*pi*1e-7 H/m
-- geometry
constant R2:real:=10.0e-03; -- outside radius R2
constant L:real:=1.0; -- length of conductor, m
constant Rdc:real:=L/sigma/(3.14*R2*R2); -- dc resistance of conductor
constant omega_c:real:= 1.0/(sigma*mu*R2*R2); -- characteristic radian frequency
constant d0:real:= 1.0;
constant d1:real:=-0.125/omega_c;
constant d2:real:= 2.083333e-02/(omega_c**2);
constant d3:real:=-3.580734e-03/(omega_c**3);
constant d4:real:= 6.184882e-04/(omega_c**4);
constant d5:real:=-1.069248e-04/(omega_c**5);
constant d6:real:= 1.848816e-05/(omega_c**6);
constant d7:real:=-3.196859e-06/(omega_c**7);
constant d8:real:= 5.527843e-07/(omega_c**8);
constant d9:real:=-9.558471e-08/(omega_c**9);
begin
i == (d0*v + d1*v'dot + d2*v'dot'dot + d3*v'dot'dot'dot + d4*v'dot'dot'dot'dot + d5*v'dot'dot'dot'dot'dot +
d6*v'dot'dot'dot'dot'dot'dot + d7*v'dot'dot'dot'dot'dot'dot'dot + d8*v'dot'dot'dot'dot'dot'dot'dot'dot +
d9*v'dot'dot'dot'dot'dot'dot'dot'dot'dot)/Rdc;
end architecture shunt_element;
-------------------------------------------------------------------------------
|
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Jakub Cabal
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
-- Website: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_PARITY is
Generic (
DATA_WIDTH : integer := 8;
PARITY_TYPE : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
PARITY_OUT : out std_logic
);
end UART_PARITY;
architecture FULL of UART_PARITY is
begin
-- -------------------------------------------------------------------------
-- PARITY BIT GENERATOR
-- -------------------------------------------------------------------------
even_parity_g : if (PARITY_TYPE = "even") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '0';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
odd_parity_g : if (PARITY_TYPE = "odd") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '1';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
mark_parity_g : if (PARITY_TYPE = "mark") generate
PARITY_OUT <= '1';
end generate;
space_parity_g : if (PARITY_TYPE = "space") generate
PARITY_OUT <= '0';
end generate;
end FULL; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--High-Speed D-PHY lane RX PHY for MIPI CSI-2 Rx core
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This entity handles input skew compensation and deserialisation for the
--CSI data input lanes. Output is has arbitrary alignment which must be fixed later on
--in the processing chain
entity csi_rx_hs_lane_phy is
generic(
series : string := "7SERIES"; --FPGA series, 7SERIES or VIRTEX6
invert : boolean := false; --Whether or not to invert output (i.e. if pairs are swapped)
term_en : boolean := true; --Whether or not to enable internal input termination
delay : natural --IDELAY delay value for skew compensation
);
port (
ddr_bit_clock : in STD_LOGIC; --true and complement DDR bit clocks, buffered from D-PHY clock
ddr_bit_clock_b : in STD_LOGIC;
byte_clock : in STD_LOGIC; --byte clock; i.e. input clock /4
enable : in STD_LOGIC; --active high enable for SERDES
reset : in STD_LOGIC; --reset, latched internally to byte clock
dphy_hs : in STD_LOGIC_VECTOR (1 downto 0); --lane input, 1 is P, 0 is N
deser_out : out STD_LOGIC_VECTOR (7 downto 0) --deserialised byte output
);
end csi_rx_hs_lane_phy;
architecture Behavioral of csi_rx_hs_lane_phy is
signal reset_lat : std_logic; --reset synchronised to byte clock
signal in_se : std_logic; --input after differential buffer
signal in_delayed : std_logic; --input after deskew
--for Virtex-6 devices where we cascade two ISERDESs
signal shift_1 : std_logic;
signal shift_2 : std_logic;
signal serdes_out_int : std_logic_vector(7 downto 0);
begin
process(byte_clock)
begin
if rising_edge(byte_clock) then
reset_lat <= reset;
end if;
end process;
inbuf : IBUFDS
generic map(
DIFF_TERM => term_en,
IBUF_LOW_PWR => FALSE,
IOSTANDARD => "DEFAULT")
port map(
O => in_se,
I => dphy_hs(1),
IB => dphy_hs(0));
--7 series specific blocks
gen_7s : if series = "7SERIES" generate
indelay : IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE",
DELAY_SRC => "IDATAIN",
HIGH_PERFORMANCE_MODE => "TRUE",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => delay,
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "DATA",
PIPE_SEL => "FALSE"
)
port map (
DATAOUT => in_delayed,
DATAIN => '0',
C => byte_clock,
CE => '0',
INC => '0',
IDATAIN => in_se,
CNTVALUEIN => "00000",
CNTVALUEOUT => open,
CINVCTRL => '0',
LD => '0',
LDPIPEEN => '0',
REGRST => '0'
);
ideser : ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 8,
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "NETWORKING",
IOBDELAY => "IFD",
NUM_CE => 1,
OFB_USED => "FALSE",
SERDES_MODE => "MASTER",
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0')
port map (
O => open,
--In the ISERDESE2, Q8 is the oldest bit but in the CSI spec
--the MSB is the most recent bit. So we mirror the output
Q1 => serdes_out_int(7),
Q2 => serdes_out_int(6),
Q3 => serdes_out_int(5),
Q4 => serdes_out_int(4),
Q5 => serdes_out_int(3),
Q6 => serdes_out_int(2),
Q7 => serdes_out_int(1),
Q8 => serdes_out_int(0),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => '0',
CE1 => enable,
CE2 => '1',
CLKDIVP => '0',
CLK => ddr_bit_clock,
CLKB => ddr_bit_clock_b,
CLKDIV => byte_clock,
OCLK => '0',
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
D => '0',
DDLY => in_delayed,
OFB => '0',
OCLKB => '0',
RST => reset_lat,
SHIFTIN1 => '0',
SHIFTIN2 => '0'
);
end generate;
--Legacy Virtex-6 specific blocks
gen_v6 : if series = "VIRTEX6" generate
--Input delay for skew compensation
indelay : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "I",
HIGH_PERFORMANCE_MODE => TRUE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => delay,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => in_delayed,
DATAIN => '0',
C => byte_clock,
CE => '0',
INC => '0',
IDATAIN => in_se,
ODATAIN => '0',
RST => '0',
T => '1',
CNTVALUEIN => "00000",
CNTVALUEOUT => open,
CLKIN => '0',
CINVCTRL => '0'
);
--Input deserialisation
ideser1 : ISERDESE1
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 8,
DYN_CLKDIV_INV_EN => FALSE,
DYN_CLK_INV_EN => FALSE,
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "NETWORKING",
IOBDELAY => "IFD",
NUM_CE => 2,
OFB_USED => FALSE,
SERDES_MODE => "MASTER",
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
port map(
O => open,
Q1 => serdes_out_int(7),
Q2 => serdes_out_int(6),
Q3 => serdes_out_int(5),
Q4 => serdes_out_int(4),
Q5 => serdes_out_int(3),
Q6 => serdes_out_int(2),
SHIFTOUT1 => shift_1,
SHIFTOUT2 => shift_2,
BITSLIP => '0',
CE1 => enable,
CE2 => enable,
CLK => ddr_bit_clock,
CLKB => ddr_bit_clock_b,
CLKDIV => byte_clock,
D => '0',
DDLY => in_delayed,
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OCLK => '0',
OFB => '0',
RST => reset_lat,
SHIFTIN1 => '0',
SHIFTIN2 => '0');
ideser2 : ISERDESE1
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 8,
DYN_CLKDIV_INV_EN => FALSE,
DYN_CLK_INV_EN => FALSE,
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "NETWORKING",
IOBDELAY => "IFD",
NUM_CE => 2,
OFB_USED => FALSE,
SERDES_MODE => "SLAVE",
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
port map(
O => open,
Q1 => open,
Q2 => open,
Q3 => serdes_out_int(1),
Q4 => serdes_out_int(0),
Q5 => open,
Q6 => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => '0',
CE1 => enable,
CE2 => enable,
CLK => ddr_bit_clock,
CLKB => ddr_bit_clock_b,
CLKDIV => byte_clock,
D => '0',
DDLY => '0',
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OCLK => '0',
OFB => '0',
RST => reset_lat,
SHIFTIN1 => shift_1,
SHIFTIN2 => shift_2);
end generate;
--Inversion of output based on generic
gen_true : if not invert generate
deser_out <= serdes_out_int;
end generate;
gen_inv : if invert generate
deser_out <= not serdes_out_int;
end generate;
end architecture;
|
architecture rtl of fifo is
type t_record is record
a : std_logic;
b : std_logic;
end record;
type t_record is record
a : std_logic;
b : std_logic;
end record;
type t_record is record a : std_logic; b : std_logic;
end record;
begin
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_978 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_978;
architecture augh of cmp_978 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_978 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_978;
architecture augh of cmp_978 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
--
-- VHDL Architecture lab12_Memory_lib.SRAM.behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 20:20:22 04/22/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
LIBRARY std;
USE std.textio.all;
ENTITY SRAM IS
PORT( Addr, DataIn : IN std_logic_vector(15 DOWNTO 0);
clock, we : IN std_logic;
DataOut : OUT std_logic_vector(15 DOWNTO 0));
END ENTITY SRAM;
ARCHITECTURE behavior OF SRAM IS
CONSTANT Undef : std_logic := 'X';
CONSTANT LoadFileName : string := "memoryinit.txt";
CONSTANT TraceFileName : string := "tracefile.txt";
SUBTYPE ST_MEM_ADDR IS std_logic_vector(15 DOWNTO 0);
SUBTYPE ST_MEM_DATA IS std_logic_vector(15 DOWNTO 0);
CONSTANT Undefined : ST_MEM_DATA := (others => Undef);
TYPE T_MEM_PAGE IS ARRAY(0 TO 1023) OF ST_MEM_DATA; -- Memory Page
TYPE T_MEM_PAGE_P IS ACCESS T_MEM_PAGE; -- Pointer to memory page
TYPE T_MEM_PAGE_TBL IS ARRAY(0 TO 63) OF T_MEM_PAGE_P; -- Table of page pointers
BEGIN
MEM : PROCESS(Addr, clock)
VARIABLE MemTable : T_MEM_PAGE_TBL := (others => NULL);
VARIABLE MemLoaded : BOOLEAN := false;
VARIABLE page : T_MEM_PAGE_P;
VARIABLE pagenumber : INTEGER RANGE 0 TO 63;
VARIABLE wordnumber : INTEGER RANGE 0 to 1023;
VARIABLE maddr : ST_MEM_ADDR;
VARIABLE mdata : ST_MEM_DATA;
VARIABLE invalid_addr : BOOLEAN;
VARIABLE findex : natural;
VARIABLE L : LINE;
VARIABLE BV : bit_vector(15 DOWNTO 0);
VARIABLE IV : integer;
FILE load_file : TEXT OPEN read_mode IS LoadFileName;
FILE trace_file : TEXT OPEN write_mode IS TraceFileName;
BEGIN
IF (NOT MemLoaded) THEN
page := NEW T_MEM_PAGE; -- Allocate a memory page
MemTable(0) := page; -- Save pointer in memory table
MemLoaded := true;
FOR w IN T_MEM_PAGE'RANGE LOOP
page(w) := Undefined; -- Mark data on page undefined
END LOOP;
findex := 0;
WHILE ((NOT ENDFILE(load_file)) AND (findex < 1024)) LOOP -- Load page zero
READLINE(load_file,L);
READ(L,BV);
page(findex) := To_StdLogicVector(BV);
findex := findex + 1;
END LOOP;
-- Page zero initialized
END IF;
maddr := Addr;
invalid_addr := IS_X(maddr);
IF NOT invalid_addr THEN
pagenumber := CONV_INTEGER(maddr(15 DOWNTO 10));
wordnumber := CONV_INTEGER(maddr(9 DOWNTO 0));
END IF;
IF (rising_edge(clock) AND (we = '1') AND NOT invalid_addr) THEN
IF (MemTable(pagenumber) = NULL) THEN -- Allocate page
page := NEW T_MEM_PAGE;
MemTable(pagenumber) := page;
FOR w IN T_MEM_PAGE'RANGE LOOP
page(w) := Undefined; -- Mark data on page undefined
END LOOP;
END IF;
page := MemTable(pagenumber);
mdata := DataIn;
page(wordnumber) := mdata;
write(L, time'image(now));
write(L, string'(": "));
write(L, wordnumber);
write(L, string'(" -> ["));
IV := CONV_INTEGER(mdata);
write(L,IV);
write(L, string'("]"));
writeline(trace_file,L);
END IF;
IF invalid_addr THEN
DataOut <= Undefined;
ELSE
IF (MemTable(pagenumber) = NULL) THEN
DataOut <= Undefined;
ELSE
page := MemTable(pagenumber);
mdata := page(wordnumber);
DataOut <= mdata;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE behavior; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 15;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (reset_in, clk_in, clock)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
gpioa_in(3) <= uart_read;
uart_write <= gpioa_out(2);
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
|
-- VHDL do Fluxo de Dados interface recepcao
library ieee;
use ieee.std_logic_1164.all;
entity fluxo_dados_interface_recepcao is
port(
clock: in std_logic;
enable: in std_logic;
entrada: in std_logic_vector(11 downto 0);
saida: out std_logic_vector(11 downto 0)
);
end fluxo_dados_interface_recepcao;
architecture exemplo of fluxo_dados_interface_recepcao is
component registrador_dado_recebido is
port(
clock: in std_logic;
enable: in std_logic;
clear: in std_logic;
entrada: in std_logic_vector(11 downto 0);
saida: out std_logic_vector(11 downto 0)
);
end component;
begin
registrador_saida: registrador_dado_recebido port map (clock, enable, '0', entrada, saida);
end exemplo;
|
--!
--! @file: full_adder.vhd
--! @brief: full adder
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity full_adder is
port (
a, b: std_logic;
cin: in std_logic;
s: out std_logic;
cout: out std_logic);
end entity adder;
--------------------------------------
architecture circuit of full_adder is
--signals and declarations
begin
s <= a xor b xor cin;
cout <= (a and b) or (b and cin) or (cin and a);
end process proc1;
end architecture circuit;
--------------------------------------
|
-- $Id: tb_pdp11core.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_pdp11core - sim
-- Description: Test bench for pdp11_core
--
-- Dependencies: simlib/simclk
-- tbd_pdp11core [UUT]
-- pdp11_intmap
--
-- To test: pdp11_core
--
-- Target Devices: generic
-- Tool versions: ghdl 0.18-2.0.0; ISim 14.7
--
-- Verified (with tb_pdp11core_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2014-12-23 620 - 0.31 14.7 131013 - u:ok
-- 2010-12-30 351 - 0.29 - - u:ok
-- 2010-12-30 351 _ssim 0.29 12.1 M53d xc3s1000 u:ok
-- 2010-06-20 308 - 0.29 - - u:ok
-- 2009-11-22 252 - 0.26 - - u:ok
-- 2007-12-30 107 - 0.25 - - u:ok
-- 2007-10-26 92 _tsim 0.26 8.1.03 I27 xc3s1000 c:fail -> blog_ghdl
-- 2007-10-26 92 _tsim 0.26 9.2.02 J39 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _tsim 0.26 9.1 J30 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _fsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-26 92 _ssim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 9.1 J30 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 9.2.02 J39 xc3s1000 d:ok
-- 2007-10-07 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
-- 2007-10-07 88 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.5.2 rename _gpr -> _gr
-- 2019-03-17 1123 1.5.1 print header
-- 2015-05-08 675 1.5 start/stop/suspend overhaul
-- 2014-12-26 621 1.4.1 adopt wmembe,ribr,wibr emulation to new 4k window
-- 2011-12-23 444 1.4 use new simclk/simclkcnt
-- 2011-11-18 427 1.3.2 now numeric_std clean
-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
-- 2010-06-13 305 1.2 add CP_CNTL_rnum and CP_ADDR_...; emulate old
-- 'sta' behaviour with new 'stapc' command; rename
-- lal,lah -> wal,wah and implement locally; new
-- output format with cpfunc name
-- 2010-06-05 301 1.1.14 renamed .rpmon -> .rbmon
-- 2010-04-24 281 1.1.13 use direct instatiation for tbd_
-- 2009-11-28 253 1.1.12 add hack for ISim 11.3
-- 2009-05-10 214 1.1.11 add .scntl command (set/clear SB_CNTL bits)
-- 2008-08-29 163 1.1.10 allow, but ignore, the wtlam command
-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust
-- 2008-04-27 140 1.1.8 use cpursta interface, remove cpufail
-- 2008-04-19 137 1.1.7 use SB_CLKCYCLE now
-- 2008-03-24 129 1.1.6 CLK_CYCLE now 31 bits
-- 2008-03-02 121 1.1.5 redo sta,cont,wtgo commands; sta,cont now wait for
-- command completion, wtgo waits for CPU to halt.
-- added .cerr,.merr directive, check cmd(m)err state
-- added .sdef as ignored directive
-- 2008-02-24 119 1.1.4 added lah,rps,wps command
-- 2008-01-26 114 1.1.3 add handling of d=val,msk
-- 2008-01-06 111 1.1.2 remove .eireq, EI's now handled in tbd_pdp11_core
-- 2007-10-26 92 1.0.2 use DONE timestamp at end of execution
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-02 79 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.pdp11_sim.all;
use work.pdp11.all;
entity tb_pdp11core is
end tb_pdp11core;
architecture sim of tb_pdp11core is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal UNUSEDSIGNAL : slbit := '0'; -- FIXME: hack to make ISim 11.3 happy
signal CP_CNTL_req : slbit := '0';
signal CP_CNTL_func : slv5 := (others=>'0');
signal CP_CNTL_rnum : slv3 := (others=>'0');
signal CP_ADDR_addr : slv22_1 := (others=>'0');
signal CP_ADDR_racc : slbit := '0';
signal CP_ADDR_be : slv2 := "11";
signal CP_ADDR_ena_22bit : slbit := '0';
signal CP_ADDR_ena_ubmap : slbit := '0';
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT_cmdbusy : slbit := '0';
signal CP_STAT_cmdack : slbit := '0';
signal CP_STAT_cmderr : slbit := '0';
signal CP_STAT_cmdmerr : slbit := '0';
signal CP_STAT_cpugo : slbit := '0';
signal CP_STAT_cpustep : slbit := '0';
signal CP_STAT_cpuwait : slbit := '0';
signal CP_STAT_cpususp : slbit := '0';
signal CP_STAT_cpurust : slv4 := (others=>'0');
signal CP_STAT_suspint : slbit := '0';
signal CP_STAT_suspext : slbit := '0';
signal CP_DOUT : slv16 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal R_CHKDAT : slv16 := (others=>'0');
signal R_CHKMSK : slv16 := (others=>'0');
signal R_CHKREQ : slbit := '0';
signal R_WAITCMD : slbit := '0';
signal R_WAITSTEP : slbit := '0';
signal R_WAITGO : slbit := '0';
signal R_WAITOK : slbit := '0';
signal R_CP_STAT : cp_stat_type := cp_stat_init;
signal R_CP_DOUT : slv16 := (others=>'0');
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT: entity work.tbd_pdp11core
port map (
CLK => CLK,
RESET => RESET,
CP_CNTL_req => CP_CNTL_req,
CP_CNTL_func => CP_CNTL_func,
CP_CNTL_rnum => CP_CNTL_rnum,
CP_ADDR_addr => CP_ADDR_addr,
CP_ADDR_racc => CP_ADDR_racc,
CP_ADDR_be => CP_ADDR_be,
CP_ADDR_ena_22bit => CP_ADDR_ena_22bit,
CP_ADDR_ena_ubmap => CP_ADDR_ena_ubmap,
CP_DIN => CP_DIN,
CP_STAT_cmdbusy => CP_STAT_cmdbusy,
CP_STAT_cmdack => CP_STAT_cmdack,
CP_STAT_cmderr => CP_STAT_cmderr,
CP_STAT_cmdmerr => CP_STAT_cmdmerr,
CP_STAT_cpugo => CP_STAT_cpugo,
CP_STAT_cpustep => CP_STAT_cpustep,
CP_STAT_cpuwait => CP_STAT_cpuwait,
CP_STAT_cpususp => CP_STAT_cpususp,
CP_STAT_cpurust => CP_STAT_cpurust,
CP_STAT_suspint => CP_STAT_suspint,
CP_STAT_suspext => CP_STAT_suspext,
CP_DOUT => CP_DOUT
);
proc_stim: process
file ifile : text open read_mode is "tb_pdp11core_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable idummy : integer := 0;
variable dcycle : integer := 0;
variable irqline : integer := 0;
variable ireq : boolean := false;
variable ifunc : slv5 := (others=>'0');
variable irnum : slv3 := (others=>'0');
variable idin : slv16 := (others=>'0');
variable imsk : slv16 := (others=>'1');
variable idin3 : slv3 := (others=>'0');
variable ichk : boolean := false;
variable idosta: slbit := '0';
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable rind : integer := 0;
variable nblk : integer := 0;
variable xmicmd : string(1 to 3) := (others=>' ');
variable iwtstp : boolean := false;
variable iwtgo : boolean := false;
variable icerr : integer := 0;
variable imerr : integer := 0;
variable to_cmd : integer := 50;
variable to_stp : integer := 100;
variable to_go : integer := 5000;
variable ien : slbit := '0';
variable ibit : integer := 0;
variable imemi : boolean := false;
variable iaddr : slv16 := (others=>'0');
variable idoibr : boolean := false;
variable r_addr : slv22_1 := (others=>'0');
variable r_ena_22bit : slbit := '0';
variable r_ena_ubmap : slbit := '0';
variable r_membe : slv2 := "11";
variable r_membestick : slbit := '0';
begin
SB_CNTL <= (others=>'L');
wait for clock_offset - setup_time;
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
-- write header
write(oline, string'(" # cycles"));
writeline(output, oline);
write(oline, string'(" | function"));
writeline(output, oline);
write(oline, string'(" | | register"));
writeline(output, oline);
write(oline, string'(" | | | input data"));
writeline(output, oline);
write(oline, string'(" | | | | cmdbusy"));
writeline(output, oline);
write(oline, string'(" | | | | | cmdack"));
writeline(output, oline);
write(oline, string'(" | | | | | | cmderr"));
writeline(output, oline);
write(oline, string'(" | | | | | | | cmdmerr"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | output data"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | cpugo"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | |cpustep"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | ||cpuwait"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | |||cpususp"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | ||||suspint"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | |||||suspext"));
writeline(output, oline);
write(oline,
string'(" | | | | | | | | | |||||| cpurust"));
writeline(output, oline);
write(oline,
string'(" | | | | | | | | | |||||| | Check result"));
writeline(output, oline);
write(oline,
string'(" | | | | | | | | | |||||| | |"));
writeline(output, oline);
file_loop: while not endfile(ifile) loop
-- this logic is a quick hack to implement the 'stapc' command
if idosta = '0' then
readline (ifile, iline);
iwtstp := false;
iwtgo := false;
if nblk>0 and -- outstanding [rw]mi lines ?
iline'length>=3 and -- and 3 leading blanks
iline(iline'left to iline'left+2)=" " then
nblk := nblk - 1; -- than fill [rw]mi command in again
iline(iline'left to iline'left+2) := xmicmd;
end if;
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
else
idosta := '0';
dname := "sta ";
ok := true;
end if;
if ok then
case dname is
when "rsp " => dname := "rr6 "; -- rsp -> rr6
when "rpc " => dname := "rr7 "; -- rpc -> rr7
when "wsp " => dname := "wr6 "; -- wsp -> wr6
when "wpc " => dname := "wr7 "; -- wpc -> wr7
when others => null;
end case;
rind := character'pos(dname(3)) - character'pos('0');
if (dname(1)='r' or dname(1)='w') and -- check for [rw]r[0-7]
dname(2)='r' and
(rind>=0 and rind<=7) then
dname(3) := '|'; -- replace with [rw]r|
end if;
if dname(1) = '.' then
case dname is
when ".mode " => -- .mode
readword_ea(iline, dname);
assert dname="pdpcp "
report "assert .mode == pdpcp" severity failure;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".tocmd" => -- .tocmd
read_ea(iline, idelta);
to_cmd := idelta;
when ".tostp" => -- .tostp
read_ea(iline, idelta);
to_stp := idelta;
when ".togo " => -- .togo
read_ea(iline, idelta);
to_go := idelta;
when ".sdef " => -- .sdef (ignore it)
readempty(iline);
when ".cerr " => -- .cerr
read_ea(iline, icerr);
when ".merr " => -- .merr
read_ea(iline, imerr);
when ".anena" => -- .anena (ignore it)
readempty(iline);
when ".rlmon" => -- .rlmon (ignore it)
readempty(iline);
when ".rbmon" => -- .rbmon (ignore it)
readempty(iline);
when ".scntl" => -- .scntl
read_ea(iline, ibit);
read_ea(iline, ien);
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
report "assert bit number in range of SB_CNTL"
severity failure;
if ien = '1' then
SB_CNTL(ibit) <= 'H';
else
SB_CNTL(ibit) <= 'L';
end if;
when others => -- bad directive
write(oline, string'("-E: unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
testempty_ea(iline);
next file_loop;
else
ireq := true;
ifunc := c_cpfunc_noop;
irnum := "000";
ichk := false;
idin := (others=>'0');
imsk := (others=>'1');
imemi := false;
idoibr := false;
case dname is
when "brm " => -- brm
read_ea(iline, nblk);
xmicmd := "rmi";
next file_loop;
when "bwm " => -- bwm
read_ea(iline, nblk);
xmicmd := "wmi";
next file_loop;
when "rr| " => -- rr[0-7]
ifunc := c_cpfunc_rreg;
irnum := slv(to_unsigned(rind, 3));
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wr| " => -- wr[0-7]
ifunc := c_cpfunc_wreg;
irnum := slv(to_unsigned(rind, 3));
readoct_ea(iline, idin);
-- Note: there are no field definitions for wal, wah, wmembe because
-- there is no corresponding cp command. Therefore the
-- rbus field definitions are used here
when "wal " => -- wal
readoct_ea(iline, idin);
r_addr := (others=>'0'); -- write to al clears ah !!
r_ena_22bit := '0';
r_ena_ubmap := '0';
r_addr(c_al_rbf_addr) := idin(c_al_rbf_addr);
testempty_ea(iline);
next file_loop;
when "wah " => -- wah
readoct_ea(iline, idin);
r_addr(21 downto 16) := idin(c_ah_rbf_addr);
r_ena_22bit := idin(c_ah_rbf_ena_22bit);
r_ena_ubmap := idin(c_ah_rbf_ena_ubmap);
testempty_ea(iline);
next file_loop;
when "wmembe" => -- wmembe
read_ea(iline, idin3);
r_membestick := idin3(c_membe_rbf_stick);
r_membe := idin3(c_membe_rbf_be);
testempty_ea(iline);
next file_loop;
when "rm " => -- rm
ifunc := c_cpfunc_rmem;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "rmi " => -- rmi
ifunc := c_cpfunc_rmem;
imemi := true;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wm " => -- wm
ifunc := c_cpfunc_wmem;
readoct_ea(iline, idin);
when "wmi " => -- wmi
ifunc := c_cpfunc_wmem;
imemi := true;
readoct_ea(iline, idin);
when "ribr " => -- ribr
ifunc := c_cpfunc_rmem;
idoibr := true;
readoct_ea(iline, iaddr);
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wibr " => -- wibr
ifunc := c_cpfunc_wmem;
idoibr := true;
readoct_ea(iline, iaddr);
readoct_ea(iline, idin);
when "rps " => -- rps
ifunc := c_cpfunc_rpsw;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wps " => -- wps
ifunc := c_cpfunc_wpsw;
readoct_ea(iline, idin);
-- Note: in old version 'sta addr' was an atomic operation, loading
-- the pc and starting the cpu. Now this is action is two step
-- first a wpc followed by a 'sta'.
when "stapc " => -- stapc
ifunc := c_cpfunc_wreg;
irnum := c_gr_pc;
readoct_ea(iline, idin);
idosta := '1'; -- request 'sta' to be done next
when "sta " => -- sta
ifunc := c_cpfunc_start;
when "sto " => -- sto
ifunc := c_cpfunc_stop;
when "step " => -- step
ifunc := c_cpfunc_step;
iwtstp := true;
when "cres " => -- cres
ifunc := c_cpfunc_creset;
when "bres " => -- bres
ifunc := c_cpfunc_breset;
when "susp " => -- susp
ifunc := c_cpfunc_suspend;
when "resu " => -- resu
ifunc := c_cpfunc_resume;
when "wtgo " => -- wtgo
iwtgo := true;
ireq := false; -- no cp request !
when "wtlam " => -- wtlam (ignore it)
readempty(iline);
next file_loop;
when others => -- bad directive
write(oline, string'("-E: unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
end if;
testempty_ea(iline);
end if;
CP_ADDR_be <= r_membe;
if idoibr then
CP_ADDR_addr(15 downto 13) <= "111";
CP_ADDR_addr(12 downto 1) <= iaddr(12 downto 1);
CP_ADDR_racc <= '1';
CP_ADDR_ena_22bit <= '0';
CP_ADDR_ena_ubmap <= '0';
else
CP_ADDR_addr <= r_addr;
CP_ADDR_racc <= '0';
CP_ADDR_be <= "11";
CP_ADDR_ena_22bit <= r_ena_22bit;
CP_ADDR_ena_ubmap <= r_ena_ubmap;
end if;
if ireq then
CP_CNTL_req <= '1';
CP_CNTL_func <= ifunc;
CP_CNTL_rnum <= irnum;
end if;
if ichk then
CP_DIN <= (others=>'0');
R_CHKDAT <= idin;
R_CHKMSK <= imsk;
R_CHKREQ <= '1';
else
CP_DIN <= idin;
R_CHKREQ <= '0';
end if;
R_WAITCMD <= '0';
R_WAITSTEP <= '0';
R_WAITGO <= '0';
if iwtgo then
idelta := to_go;
R_WAITGO <= '1';
elsif iwtstp then
idelta := to_stp;
R_WAITSTEP <= '1';
else
idelta := to_cmd;
R_WAITCMD <= '1';
end if;
wait for clock_period;
CP_CNTL_req <= '0';
dcycle := 1;
while idelta>0 and R_WAITOK='0' loop
wait for clock_period;
dcycle := dcycle + 1;
idelta := idelta - 1;
end loop;
if imemi then -- rmi or wmi seen ? then inc ar
r_addr := slv(unsigned(r_addr) + 1);
end if;
if ifunc = c_cpfunc_wmem and -- emulate be sticky logic of rbus iface
r_membestick = '0' then
r_membe := "11";
end if;
write(oline, dcycle, right, 4);
write(oline, string'(" "));
if ireq then
case ifunc is
when c_cpfunc_rreg => write(oline, string'("rreg"));
when c_cpfunc_wreg => write(oline, string'("wreg"));
when c_cpfunc_rpsw => write(oline, string'("rpsw"));
when c_cpfunc_wpsw => write(oline, string'("wpsw"));
when c_cpfunc_rmem =>
if idoibr then
write(oline, string'("ribr"));
else
write(oline, string'("rmem"));
end if;
when c_cpfunc_wmem =>
if idoibr then
write(oline, string'("wibr"));
else
write(oline, string'("wmem"));
end if;
when c_cpfunc_start => write(oline, string'("sta "));
when c_cpfunc_stop => write(oline, string'("sto "));
when c_cpfunc_step => write(oline, string'("step"));
when c_cpfunc_creset => write(oline, string'("cres"));
when c_cpfunc_breset => write(oline, string'("bres"));
when c_cpfunc_suspend => write(oline, string'("susp"));
when c_cpfunc_resume => write(oline, string'("resu"));
when others =>
write(oline, string'("?"));
writeoct(oline, ifunc, right, 2);
write(oline, string'("?"));
end case;
writeoct(oline, irnum, right, 2);
writeoct(oline, idin, right, 8);
else
write(oline, string'("---- - ------"));
end if;
write(oline, R_CP_STAT.cmdbusy, right, 3);
write(oline, R_CP_STAT.cmdack, right, 2);
write(oline, R_CP_STAT.cmderr, right, 2);
write(oline, R_CP_STAT.cmdmerr, right, 2);
writeoct(oline, R_CP_DOUT, right, 8);
write(oline, R_CP_STAT.cpugo, right, 3);
write(oline, R_CP_STAT.cpustep, right, 1);
write(oline, R_CP_STAT.cpuwait, right, 1);
write(oline, R_CP_STAT.cpususp, right, 1);
write(oline, R_CP_STAT.suspint, right, 1);
write(oline, R_CP_STAT.suspext, right, 1);
writeoct(oline, R_CP_STAT.cpurust, right, 3);
if R_WAITOK = '1' then
if R_CP_STAT.cmderr='1' or icerr=1 then
if R_CP_STAT.cmderr='1' and icerr=0 then
write(oline, string'(" FAIL CMDERR"));
elsif R_CP_STAT.cmderr='1' and icerr=1 then
write(oline, string'(" CHECK CMDERR SEEN"));
elsif R_CP_STAT.cmderr='0' and icerr=1 then
write(oline, string'(" FAIL CMDERR EXPECTED,MISSED"));
end if;
elsif R_CP_STAT.cmdmerr='1' or imerr=1 then
if R_CP_STAT.cmdmerr='1' and imerr=0 then
write(oline, string'(" FAIL CMDMERR"));
elsif R_CP_STAT.cmdmerr='1' and imerr=1 then
write(oline, string'(" CHECK CMDMERR SEEN"));
elsif R_CP_STAT.cmdmerr='0' and imerr=1 then
write(oline, string'(" FAIL CMDMERR EXPECTED,MISSED"));
end if;
elsif R_CHKREQ='1' then
if unsigned((R_CP_DOUT xor R_CHKDAT) and (not R_CHKMSK))=0 then
write(oline, string'(" CHECK OK"));
else
write(oline, string'(" CHECK FAILED, d="));
writeoct(oline, R_CHKDAT, right, 7);
if unsigned(R_CHKMSK)/=0 then
write(oline, string'(","));
writeoct(oline, R_CHKMSK, right, 7);
end if;
end if;
end if;
if iwtgo then
write(oline, string'(" WAIT GO OK "));
elsif iwtstp then
write(oline, string'(" WAIT STEP OK"));
end if;
else
write(oline, string'(" WAIT FAILED (will reset)"));
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
end if;
writeline(output, oline);
end loop;
wait for 4*clock_period;
CLK_STOP <= '1';
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
begin
loop
wait until rising_edge(CLK);
wait for c2out_time;
R_WAITOK <= '0';
if R_WAITCMD = '1' then
if CP_STAT_cmdack = '1' then
R_WAITOK <= '1';
end if;
elsif R_WAITGO = '1' then
if CP_STAT_cmdbusy='0' and CP_STAT_cpugo='0' then
R_WAITOK <= '1';
end if;
elsif R_WAITSTEP = '1' then
if CP_STAT_cmdbusy='0' and CP_STAT_cpustep='0' then
R_WAITOK <= '1';
end if;
end if;
R_CP_STAT.cmdbusy <= CP_STAT_cmdbusy;
R_CP_STAT.cmdack <= CP_STAT_cmdack;
R_CP_STAT.cmderr <= CP_STAT_cmderr;
R_CP_STAT.cmdmerr <= CP_STAT_cmdmerr;
R_CP_STAT.cpugo <= CP_STAT_cpugo;
R_CP_STAT.cpustep <= CP_STAT_cpustep;
R_CP_STAT.cpuwait <= CP_STAT_cpuwait;
R_CP_STAT.cpususp <= CP_STAT_cpususp;
R_CP_STAT.cpurust <= CP_STAT_cpurust;
R_CP_STAT.suspint <= CP_STAT_suspint;
R_CP_STAT.suspext <= CP_STAT_suspext;
R_CP_DOUT <= CP_DOUT;
end loop;
end process proc_moni;
end sim;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity io_bus_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_io_req;
resp : in t_io_resp );
end io_bus_bfm;
architecture bfm of io_bus_bfm is
shared variable this : p_io_bus_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, wait_for_response);
signal state : t_state := idle;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_io_bus_bfm(g_name, this);
bound <= true;
wait;
end process;
process(clock)
begin
if rising_edge(clock) then
req <= c_io_req_init;
case state is
when idle =>
if bound then
if this.command = e_io_read then
req.address <= this.address;
req.read <= '1';
state <= wait_for_response;
elsif this.command = e_io_write then
req.address <= this.address;
req.write <= '1';
req.data <= this.data;
state <= wait_for_response;
end if;
end if;
when wait_for_response =>
if resp.ack='1' then
this.data := resp.data;
this.command := e_io_none;
state <= idle;
end if;
when others =>
null;
end case;
end if;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity io_bus_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_io_req;
resp : in t_io_resp );
end io_bus_bfm;
architecture bfm of io_bus_bfm is
shared variable this : p_io_bus_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, wait_for_response);
signal state : t_state := idle;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_io_bus_bfm(g_name, this);
bound <= true;
wait;
end process;
process(clock)
begin
if rising_edge(clock) then
req <= c_io_req_init;
case state is
when idle =>
if bound then
if this.command = e_io_read then
req.address <= this.address;
req.read <= '1';
state <= wait_for_response;
elsif this.command = e_io_write then
req.address <= this.address;
req.write <= '1';
req.data <= this.data;
state <= wait_for_response;
end if;
end if;
when wait_for_response =>
if resp.ack='1' then
this.data := resp.data;
this.command := e_io_none;
state <= idle;
end if;
when others =>
null;
end case;
end if;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity io_bus_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_io_req;
resp : in t_io_resp );
end io_bus_bfm;
architecture bfm of io_bus_bfm is
shared variable this : p_io_bus_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, wait_for_response);
signal state : t_state := idle;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_io_bus_bfm(g_name, this);
bound <= true;
wait;
end process;
process(clock)
begin
if rising_edge(clock) then
req <= c_io_req_init;
case state is
when idle =>
if bound then
if this.command = e_io_read then
req.address <= this.address;
req.read <= '1';
state <= wait_for_response;
elsif this.command = e_io_write then
req.address <= this.address;
req.write <= '1';
req.data <= this.data;
state <= wait_for_response;
end if;
end if;
when wait_for_response =>
if resp.ack='1' then
this.data := resp.data;
this.command := e_io_none;
state <= idle;
end if;
when others =>
null;
end case;
end if;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity io_bus_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_io_req;
resp : in t_io_resp );
end io_bus_bfm;
architecture bfm of io_bus_bfm is
shared variable this : p_io_bus_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, wait_for_response);
signal state : t_state := idle;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_io_bus_bfm(g_name, this);
bound <= true;
wait;
end process;
process(clock)
begin
if rising_edge(clock) then
req <= c_io_req_init;
case state is
when idle =>
if bound then
if this.command = e_io_read then
req.address <= this.address;
req.read <= '1';
state <= wait_for_response;
elsif this.command = e_io_write then
req.address <= this.address;
req.write <= '1';
req.data <= this.data;
state <= wait_for_response;
end if;
end if;
when wait_for_response =>
if resp.ack='1' then
this.data := resp.data;
this.command := e_io_none;
state <= idle;
end if;
when others =>
null;
end case;
end if;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity io_bus_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_io_req;
resp : in t_io_resp );
end io_bus_bfm;
architecture bfm of io_bus_bfm is
shared variable this : p_io_bus_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, wait_for_response);
signal state : t_state := idle;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_io_bus_bfm(g_name, this);
bound <= true;
wait;
end process;
process(clock)
begin
if rising_edge(clock) then
req <= c_io_req_init;
case state is
when idle =>
if bound then
if this.command = e_io_read then
req.address <= this.address;
req.read <= '1';
state <= wait_for_response;
elsif this.command = e_io_write then
req.address <= this.address;
req.write <= '1';
req.data <= this.data;
state <= wait_for_response;
end if;
end if;
when wait_for_response =>
if resp.ack='1' then
this.data := resp.data;
this.command := e_io_none;
state <= idle;
end if;
when others =>
null;
end case;
end if;
end process;
end bfm;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.zpu_top_pkg.all;
use work.wishbone_pkg.all;
use work.zpupkg.all;
use work.zpu_config.all;
entity zpu_system is
generic(
simulate : boolean := false);
port ( areset : in std_logic;
cpu_clk : in std_logic;
-- ZPU Control signals
enable : in std_logic;
interrupt : in std_logic;
zpu_status : out std_logic_vector(63 downto 0);
-- wishbone interfaces
zpu_wb_i : in wishbone_bus_out;
zpu_wb_o : out wishbone_bus_in);
end zpu_system;
architecture behave of zpu_system is
signal mem_req : std_logic;
signal mem_we : std_logic;
signal mem_ack : std_logic;
signal mem_read : std_logic_vector(wordSize-1 downto 0);
signal mem_write : std_logic_vector(wordSize-1 downto 0);
signal out_mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
begin
my_zpu_core:
zpu_core port map (
clk => cpu_clk,
areset => areset,
enable => enable,
mem_req => mem_req,
mem_we => mem_we,
mem_ack => mem_ack,
mem_read => mem_read,
mem_write => mem_write,
out_mem_addr => out_mem_addr,
mem_writeMask => mem_writeMask,
interrupt => interrupt,
zpu_status => zpu_status,
break => open);
my_zpu_wb_bridge:
zpu_wb_bridge port map (
clk => cpu_clk,
areset => areset,
mem_req => mem_req,
mem_we => mem_we,
mem_ack => mem_ack,
mem_read => mem_read,
mem_write => mem_write,
out_mem_addr => out_mem_addr,
mem_writeMask => mem_writeMask,
zpu_wb_i => zpu_wb_i,
zpu_wb_o => zpu_wb_o);
end behave;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spimctrl
-- File: spimctrl.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: SPI flash memory controller. Supports a wide range of SPI
-- memory devices with the data read instruction configurable via
-- generics. Also has limited support for initializing and reading
-- SD Cards in SPI mode.
--
-- The controller has two memory areas. The flash area where the flash memory
-- is directly mapped and the I/O area where core registers are mapped.
--
-- Revision 1 added support for burst reads when sdcard = 0
--
-- Post revision 1: Remove support for SD card by commenting out code
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.spi.all;
entity spimctrl is
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
faddr : integer := 16#000#; -- Flash map base address
fmask : integer := 16#fff#; -- Flash area mask
ioaddr : integer := 16#000#; -- I/O base address
iomask : integer := 16#fff#; -- I/O mask
spliten : integer := 0; -- AMBA SPLIT support
oepol : integer := 0; -- Output enable polarity
sdcard : integer range 0 to 0 := 0; -- Unused
readcmd : integer range 0 to 255 := 16#0B#; -- Mem. dev. READ command
dummybyte : integer range 0 to 1 := 1; -- Dummy byte after cmd
dualoutput : integer range 0 to 1 := 0; -- Enable dual output
scaler : integer range 1 to 512 := 1; -- SCK scaler
altscaler : integer range 1 to 512 := 1; -- Alternate SCK scaler
pwrupcnt : integer := 0; -- System clock cycles to init
maxahbaccsz : integer range 0 to 256 := AHBDW; -- Max AHB access size
offset : integer := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
spii : in spimctrl_in_type;
spio : out spimctrl_out_type
);
end spimctrl;
architecture rtl of spimctrl is
constant REVISION : amba_version_type := 1;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPIMCTRL, 0, REVISION, hirq),
4 => ahb_iobar(ioaddr, iomask),
5 => ahb_membar(faddr, '1', '1', fmask),
others => zero32);
-- BANKs
constant CTRL_BANK : integer := 0;
constant FLASH_BANK : integer := 1;
constant MAXDW : integer := maxahbaccsz;
-----------------------------------------------------------------------------
-- SD card constants
-----------------------------------------------------------------------------
-- constant SD_BLEN : integer := 4;
-- constant SD_CRC_BYTE : std_logic_vector(7 downto 0) := X"95";
-- constant SD_BLOCKLEN : std_logic_vector(31 downto 0) :=
-- conv_std_logic_vector(SD_BLEN, 32);
-- -- Commands
-- constant SD_CMD0 : std_logic_vector(5 downto 0) := "000000";
-- constant SD_CMD16 : std_logic_vector(5 downto 0) := "010000";
-- constant SD_CMD17 : std_logic_vector(5 downto 0) := "010001";
-- constant SD_CMD55 : std_logic_vector(5 downto 0) := "110111";
-- constant SD_ACMD41 : std_logic_vector(5 downto 0) := "101001";
-- -- Command timeout
-- constant SD_CMD_TIMEOUT : integer := 100;
-- -- Data token timeout
-- constant SD_DATATOK_TIMEOUT : integer := 312500;
-----------------------------------------------------------------------------
-- SPI device constants
-----------------------------------------------------------------------------
-- Length of read instruction argument-1
constant SPI_ARG_LEN : integer := 2 + dummybyte;
-----------------------------------------------------------------------------
-- Core constants
-----------------------------------------------------------------------------
-- OEN
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1); -- Enable outputs
constant INPUT : std_ulogic := not OUTPUT; -- Tri-state outputs
-- Register offsets
constant CONF_REG_OFF : std_logic_vector(7 downto 2) := "000000";
constant CTRL_REG_OFF : std_logic_vector(7 downto 2) := "000001";
constant STAT_REG_OFF : std_logic_vector(7 downto 2) := "000010";
constant RX_REG_OFF : std_logic_vector(7 downto 2) := "000011";
constant TX_REG_OFF : std_logic_vector(7 downto 2) := "000100";
-----------------------------------------------------------------------------
-- Subprograms
-----------------------------------------------------------------------------
-- Description: Determines required size of timer used for clock scaling
function timer_size
return integer is
begin -- timer_size
if altscaler > scaler then
return altscaler;
end if;
return scaler;
end timer_size;
-- Description: Returns the number of bits required for the haddr vector to
-- be able to save the Flash area address.
function req_addr_bits
return integer is
begin -- req_addr_bits
case fmask is
when 16#fff# => return 20;
when 16#ffe# => return 21;
when 16#ffc# => return 22;
when 16#ff8# => return 23;
when 16#ff0# => return 24;
when 16#fe0# => return 25;
when 16#fc0# => return 26;
when 16#f80# => return 27;
when 16#f00# => return 28;
when 16#e00# => return 29;
when 16#c00# => return 30;
when others => return 31;
end case;
end req_addr_bits;
-- Description: Returns true if SCK clock should transition
function sck_toggle (
curr : std_logic_vector((timer_size-1) downto 0);
last : std_logic_vector((timer_size-1) downto 0);
usealtscaler : boolean)
return boolean is
begin -- sck_toggle
if usealtscaler then
return (curr(altscaler-1) xor last(altscaler-1)) = '1';
end if;
return (curr(scaler-1) xor last(scaler-1)) = '1';
end sck_toggle;
-- Description: Short for conv_std_logic_vector, avoiding an alias
function cslv (
i : integer;
w : integer)
return std_logic_vector is
begin -- cslv
return conv_std_logic_vector(i,w);
end cslv;
-- Description: Calculates value for spi.cnt based on AMBA HSIZE
function calc_spi_cnt (
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable cnt : std_logic_vector(4 downto 0) := (others => '0');
begin -- calc_spi_cnt
for i in 0 to 4 loop
if i < conv_integer(hsize) then
cnt(i) := '1';
end if;
end loop; -- i
return cnt;
end calc_spi_cnt;
-----------------------------------------------------------------------------
-- States
-----------------------------------------------------------------------------
-- Main FSM states
type spimstate_type is (IDLE, AHB_RESPOND, USER_SPI, BUSY);
-- SPI device FSM states
type spistate_type is (SPI_PWRUP, SPI_READY, SPI_READ, SPI_ADDR, SPI_DATA);
-- SD FSM states
type sdstate_type is (SD_CHECK_PRES, SD_PWRUP0, SD_PWRUP1, SD_INIT_IDLE,
SD_ISS_ACMD41, SD_CHECK_CMD16, SD_READY,
SD_CHECK_CMD17, SD_CHECK_TOKEN, SD_HANDLE_DATA,
SD_SEND_CMD, SD_GET_RESP);
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type spim_ctrl_reg_type is record -- Control register
eas : std_ulogic; -- Enable alternate scaler
ien : std_ulogic; -- Interrupt enable
usrc : std_ulogic; -- User mode
end record;
type spim_stat_reg_type is record -- Status register
busy : std_ulogic; -- Core busy
done : std_ulogic; -- User operation done
end record;
type spim_regif_type is record -- Register bank
ctrl : spim_ctrl_reg_type; -- Control register
stat : spim_stat_reg_type; -- Status register
end record;
-- type sdcard_type is record -- Present when SD card
-- state : sdstate_type; -- SD state
-- tcnt : std_logic_vector(2 downto 0); -- Transmit count
-- rcnt : std_logic_vector(3 downto 0); -- Receive count
-- cmd : std_logic_vector(5 downto 0); -- SD command
-- rstate : sdstate_type; -- Return state
-- htb : std_ulogic; -- Handle trailing byte
-- vresp : std_ulogic; -- Valid response
-- cd : std_ulogic; -- Synchronized card detect
-- timeout : std_ulogic; -- Timeout status bit
-- dtocnt : std_logic_vector(18 downto 0); -- Data token timeout counter
-- ctocnt : std_logic_vector(6 downto 0); -- CMD resp. timeout counter
-- end record;
type spiflash_type is record -- Present when !SD card
state : spistate_type; -- Mem. device comm. state
cnt : std_logic_vector(4 downto 0); -- Generic counter
hsize : std_logic_vector(2 downto 0); -- Size of access
hburst : std_logic_vector(0 downto 0); -- Incremental burst
end record;
type spimctrl_in_array is array (1 downto 0) of spimctrl_in_type;
type spim_reg_type is record
-- Common
spimstate : spimstate_type; -- Main FSM
rst : std_ulogic; -- Reset
reg : spim_regif_type; -- Register bank
timer : std_logic_vector((timer_size-1) downto 0);
sample : std_logic_vector(1 downto 0); -- Sample data line
bd : std_ulogic;
sreg : std_logic_vector(7 downto 0); -- Shiftreg
bcnt : std_logic_vector(2 downto 0); -- Bit counter
go : std_ulogic; -- SPI comm. active
stop : std_ulogic; -- Stop SPI comm.
ar : std_logic_vector(MAXDW-1 downto 0); -- argument/response
hold : std_ulogic; -- Do not shift ar
insplit : std_ulogic; -- SPLIT response issued
unsplit : std_ulogic; -- SPLIT complete not issued
-- SPI flash device
spi : spiflash_type; -- Used when !SD card
-- SD
-- sd : sdcard_type; -- Used when SD card
-- AHB
irq : std_ulogic; -- Interrupt request
hsize : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 1);
haddr : std_logic_vector((req_addr_bits-1) downto 0);
hready : std_ulogic;
frdata : std_logic_vector(MAXDW-1 downto 0); -- Flash response data
rrdata : std_logic_vector(7 downto 0); -- Register response data
hresp : std_logic_vector(1 downto 0);
splmst : std_logic_vector(log2(NAHBMST)-1 downto 0); -- SPLIT:ed master
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- Other SPLIT:ed masters
ahbcancel : std_ulogic; -- Locked access cancels ongoing SPLIT
-- response
hburst : std_logic_vector(0 downto 0);
seq : std_ulogic; -- Sequential burst
-- Inputs and outputs
spii : spimctrl_in_array;
spio : spimctrl_out_type;
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : spim_reg_type;
begin -- rtl
comb: process (r, rstn, ahbsi, spii)
variable v : spim_reg_type;
variable change : std_ulogic;
variable regaddr : std_logic_vector(7 downto 2);
variable hsplit : std_logic_vector(NAHBMST-1 downto 0);
variable ahbirq : std_logic_vector((NAHBIRQ-1) downto 0);
variable lastbit : std_ulogic;
variable enable_altscaler : boolean;
variable disable_flash : boolean;
variable read_flash : boolean;
variable hrdata : std_logic_vector(MAXDW-1 downto 0);
variable hwdatax : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(7 downto 0);
begin -- process comb
v := r; v.spii := r.spii(0) & spii; v.sample := r.sample(0) & '0';
change := '0'; v.irq := '0'; v.hresp := HRESP_OKAY; v.hready := '1';
regaddr := r.haddr(7 downto 2); hsplit := (others => '0');
hwdatax := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
hwdata := hwdatax(7 downto 0);
ahbirq := (others => '0'); ahbirq(hirq) := r.irq;
-- if sdcard = 1 then v.sd.cd := r.spii(0).cd; else v.sd.cd := '0'; end if;
read_flash := false;
enable_altscaler := (not r.spio.initialized or r.reg.ctrl.eas) = '1';
-- disable_flash := (r.spio.errorn = '0' or r.reg.ctrl.usrc = '1' or
disable_flash := (r.reg.ctrl.usrc = '1' or
r.spio.initialized = '0' or r.spimstate = USER_SPI);
if dualoutput = 1 and sdcard = 0 then
lastbit := andv(r.bcnt(1 downto 0)) and
((r.spio.mosioen xnor INPUT) or r.bcnt(2));
else
lastbit := andv(r.bcnt);
end if;
v.bd := lastbit and r.sample(0);
---------------------------------------------------------------------------
-- AHB communication
---------------------------------------------------------------------------
if ahbsi.hready = '1' then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hmbsel := ahbsi.hmbsel(r.hmbsel'range);
if (spliten = 0 or r.spimstate /= AHB_RESPOND or
ahbsi.hmbsel(CTRL_BANK) = '1' or ahbsi.hmastlock = '1') then
-- Writes to register space have no wait state
v.hready := ahbsi.hmbsel(CTRL_BANK) and ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hwrite := ahbsi.hwrite;
v.haddr := ahbsi.haddr(r.haddr'range);
v.hsel := '1';
if ahbsi.hmbsel(FLASH_BANK) = '1' then
if sdcard = 0 then
v.hburst(r.hburst'range) := ahbsi.hburst(r.hburst'range);
v.seq := ahbsi.htrans(0);
end if;
if ahbsi.hwrite = '1' or disable_flash then
v.hresp := HRESP_ERROR;
v.hsel := '0';
else
if spliten /= 0 then
if ahbsi.hmastlock = '0' then
v.hresp := HRESP_SPLIT;
v.splmst := ahbsi.hmaster;
v.unsplit := '1';
else
v.ahbcancel := r.insplit;
end if;
v.insplit := not ahbsi.hmastlock;
end if;
end if;
end if;
else
-- Core is busy, transfer is not locked and access was to flash
-- area. Respond with SPLIT or insert wait states
v.hready := '0';
if spliten /= 0 then
v.hresp := HRESP_SPLIT;
v.hsplit(conv_integer(ahbsi.hmaster)) := '1';
end if;
end if;
else
v.hsel := '0';
end if;
end if;
if (r.hready = '0') then
if (r.hresp = HRESP_OKAY) then v.hready := '0';
else v.hresp := r.hresp; end if;
end if;
-- Read access to core registers
if (r.hsel and r.hmbsel(CTRL_BANK) and not r.hwrite) = '1' then
v.rrdata := (others => '0');
v.hready := '1';
v.hsel := '0';
case regaddr is
when CONF_REG_OFF =>
-- if sdcard = 1 then
-- v.rrdata := (others => '0');
-- else
v.rrdata := cslv(readcmd, 8);
-- end if;
when CTRL_REG_OFF =>
v.rrdata(3) := r.spio.csn;
v.rrdata(2) := r.reg.ctrl.eas;
v.rrdata(1) := r.reg.ctrl.ien;
v.rrdata(0) := r.reg.ctrl.usrc;
when STAT_REG_OFF =>
-- v.rrdata(5) := r.sd.cd;
-- v.rrdata(4) := r.sd.timeout;
-- v.rrdata(3) := not r.spio.errorn;
v.rrdata(2) := r.spio.initialized;
v.rrdata(1) := r.reg.stat.busy;
v.rrdata(0) := r.reg.stat.done;
when RX_REG_OFF => v.rrdata := r.ar(7 downto 0);
when others => null;
end case;
end if;
-- Write access to core registers
if (r.hsel and r.hmbsel(CTRL_BANK) and r.hwrite) = '1' then
case regaddr is
when CTRL_REG_OFF =>
v.rst := hwdata(4);
if (r.reg.ctrl.usrc and not hwdata(0)) = '1' then
v.spio.csn := '1';
elsif hwdata(0) = '1' then
v.spio.csn := hwdata(3);
end if;
v.reg.ctrl.eas := hwdata(2);
v.reg.ctrl.ien := hwdata(1);
v.reg.ctrl.usrc := hwdata(0);
when STAT_REG_OFF =>
-- v.spio.errorn := r.spio.errorn or hwdata(3);
v.reg.stat.done := r.reg.stat.done and not hwdata(0);
when RX_REG_OFF => null;
when TX_REG_OFF =>
if r.reg.ctrl.usrc = '1' then
v.sreg := hwdata(7 downto 0);
end if;
when others => null;
end case;
end if;
---------------------------------------------------------------------------
-- SPIMCTRL control FSM
---------------------------------------------------------------------------
v.reg.stat.busy := '1';
case r.spimstate is
when BUSY =>
-- Wait for core to finish user mode access
if (r.go or r.spio.sck) = '0' then
v.spimstate := IDLE;
v.reg.stat.done:= '1';
v.irq := r.reg.ctrl.ien;
end if;
when AHB_RESPOND =>
if r.spio.ready = '1' then
if spliten /= 0 and r.unsplit = '1' then
hsplit(conv_integer(r.splmst)) := '1';
v.unsplit := '0';
end if;
if ((spliten = 0 or v.ahbcancel = '0') and
(spliten = 0 or ahbsi.hmaster = r.splmst or r.insplit = '0') and
(((ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1') or
((spliten = 0 or r.insplit = '0') and r.hready = '0' and r.hresp = HRESP_OKAY))) then
v.spimstate := IDLE;
v.hresp := HRESP_OKAY;
if spliten /= 0 then
v.insplit := '0';
v.hsplit := r.hsplit;
end if;
v.hready := '1';
v.hsel := '0';
-- if r.spio.errorn = '0' then
-- v.hready := '0';
-- v.hresp := HRESP_ERROR;
-- end if;
elsif spliten /= 0 and v.ahbcancel = '1' then
v.spimstate := IDLE;
v.ahbcancel := '0';
end if;
end if;
when USER_SPI =>
if r.bd = '1' then
v.spimstate := BUSY;
v.hold := '1';
end if;
when others => -- IDLE
if spliten /= 0 and r.hresp /= HRESP_SPLIT then
hsplit := r.hsplit;
v.hsplit := (others => '0');
end if;
v.reg.stat.busy := '0';
if r.hsel = '1' then
if r.hmbsel(FLASH_BANK) = '1' then
-- Access to memory mapped flash area
v.spimstate := AHB_RESPOND;
read_flash := true;
elsif regaddr = TX_REG_OFF and (r.hwrite and r.reg.ctrl.usrc) = '1' then
-- Access to core transmit register
v.spimstate := USER_SPI;
v.go := '1';
v.stop := '1';
change := '1';
v.hold := '0';
if sdcard = 0 and dualoutput = 1 then
v.spio.mosioen := OUTPUT;
end if;
end if;
end if;
end case;
---------------------------------------------------------------------------
-- SD Card specific code
---------------------------------------------------------------------------
-- SD card initialization sequence:
-- * Check if card is present
-- * Perform power-up initialization sequence
-- * Issue CMD0 GO_IDLE_STATE
-- * Issue CMD55 APP_CMD
-- * Issue ACMD41 SEND_OP_COND
-- * Issue CMD16 SET_BLOCKLEN
-- if sdcard = 1 then
-- case r.sd.state is
-- when SD_PWRUP0 =>
-- v.go := '1';
-- v.sd.vresp := '1';
-- v.sd.state := SD_GET_RESP;
-- v.sd.rstate := SD_PWRUP1;
-- v.sd.rcnt := cslv(2, r.sd.rcnt'length);
-- when SD_PWRUP1 =>
-- v.sd.state := SD_SEND_CMD;
-- v.sd.rstate := SD_INIT_IDLE;
-- v.sd.cmd := SD_CMD0;
-- v.sd.rcnt := (others => '0');
-- v.ar := (others => '0');
-- when SD_INIT_IDLE =>
-- v.sd.state := SD_SEND_CMD;
-- v.sd.rcnt := (others => '0');
-- if r.ar(0) = '0' and r.sd.cmd /= SD_CMD0 then
-- v.sd.cmd := SD_CMD16;
-- v.ar := SD_BLOCKLEN;
-- v.sd.rstate := SD_CHECK_CMD16;
-- else
-- v.sd.cmd := SD_CMD55;
-- v.ar := (others => '0');
-- v.sd.rstate := SD_ISS_ACMD41;
-- end if;
-- when SD_ISS_ACMD41 =>
-- v.sd.state := SD_SEND_CMD;
-- v.sd.cmd := SD_ACMD41;
-- v.sd.rcnt := (others => '0');
-- v.ar := (others => '0');
-- v.sd.rstate := SD_INIT_IDLE;
-- when SD_CHECK_CMD16 =>
-- if r.ar(7 downto 0) /= zero32(7 downto 0) then
-- v.spio.errorn := '0';
-- else
-- v.spio.errorn := '1';
-- v.spio.initialized := '1';
-- v.sd.timeout := '0';
-- end if;
-- v.sd.state := SD_READY;
-- when SD_READY =>
-- v.spio.ready := '1';
-- v.sd.cmd := SD_CMD17;
-- v.sd.rstate := SD_CHECK_CMD17;
-- if read_flash then
-- v.sd.state := SD_SEND_CMD;
-- v.spio.ready := '0';
-- v.ar := (others => '0');
-- v.ar(r.haddr'left downto 2) := r.haddr(r.haddr'left downto 2);
-- end if;
-- when SD_CHECK_CMD17 =>
-- if r.ar(7 downto 0) /= X"00" then
-- v.sd.state := SD_READY;
-- v.spio.errorn := '0';
-- else
-- v.sd.rstate := SD_CHECK_TOKEN;
-- v.spio.csn := '0';
-- v.go := '1';
-- change := '1';
-- end if;
-- v.sd.dtocnt := cslv(SD_DATATOK_TIMEOUT, r.sd.dtocnt'length);
-- v.sd.state := SD_GET_RESP;
-- v.sd.vresp := '1';
-- v.hold := '0';
-- when SD_CHECK_TOKEN =>
-- if (r.ar(7 downto 5) = "111" and
-- r.sd.dtocnt /= zero32(r.sd.dtocnt'range)) then
-- v.sd.dtocnt := r.sd.dtocnt - 1;
-- v.sd.state := SD_GET_RESP;
-- if r.ar(0) = '0' then
-- v.sd.rstate := SD_HANDLE_DATA;
-- v.sd.rcnt := cslv(SD_BLEN-1, r.sd.rcnt'length);
-- end if;
-- v.spio.csn := '0';
-- v.go := '1';
-- change := '1';
-- else
-- v.spio.errorn := '0';
-- v.sd.state := SD_READY;
-- end if;
-- v.sd.timeout := not orv(r.sd.dtocnt);
-- v.sd.ctocnt := cslv(SD_CMD_TIMEOUT, r.sd.ctocnt'length);
-- v.hold := '0';
-- when SD_HANDLE_DATA =>
-- v.frdata := r.ar;
-- -- Receive and discard CRC
-- v.sd.state := SD_GET_RESP;
-- v.sd.rstate := SD_READY;
-- v.sd.htb := '1';
-- v.spio.csn := '0';
-- v.go := '1';
-- change := '1';
-- v.sd.vresp := '1';
-- v.spio.errorn := '1';
-- when SD_SEND_CMD =>
-- v.sd.htb := '1';
-- v.sd.vresp := '0';
-- v.spio.csn := '0';
-- v.sd.ctocnt := cslv(SD_CMD_TIMEOUT, r.sd.ctocnt'length);
-- if (v.bd or not r.go) = '1'then
-- v.hold := '0';
-- case r.sd.tcnt is
-- when "000" => v.sreg := "01" & r.sd.cmd;
-- v.hold := '1'; change := '1';
-- when "001" => v.sreg := r.ar(31 downto 24);
-- when "010" => v.sreg := r.ar(30 downto 23);
-- when "011" => v.sreg := r.ar(30 downto 23);
-- when "100" => v.sreg := r.ar(30 downto 23);
-- when "101" => v.sreg := SD_CRC_BYTE;
-- when others => v.sd.state := SD_GET_RESP;
-- end case;
-- v.go := '1';
-- v.sd.tcnt := r.sd.tcnt + 1;
-- end if;
-- when SD_GET_RESP =>
-- if v.bd = '1' then
-- if r.sd.vresp = '1' or r.sd.ctocnt = zero32(r.sd.ctocnt'range) then
-- if r.sd.rcnt = zero32(r.sd.rcnt'range) then
-- if r.sd.htb = '0' then
-- v.spio.csn := '1';
-- end if;
-- v.sd.htb := '0';
-- v.hold := '1';
-- else
-- v.sd.rcnt := r.sd.rcnt - 1;
-- end if;
-- else
-- v.sd.ctocnt := r.sd.ctocnt - 1;
-- end if;
-- end if;
-- if lastbit = '1' then
-- v.sd.vresp := r.sd.vresp or not r.ar(6);
-- if r.sd.rcnt = zero32(r.sd.rcnt'range) then
-- v.stop := r.sd.vresp and r.go and not r.sd.htb;
-- end if;
-- end if;
-- if r.sd.ctocnt = zero32(r.sd.ctocnt'range) then
-- v.stop := r.go;
-- end if;
-- if (r.go or r.spio.sck) = '0' then
-- v.sd.state := r.sd.rstate;
-- if r.sd.ctocnt = zero32(r.sd.ctocnt'range) then
-- if r.spio.initialized = '1' then
-- v.sd.state := SD_READY;
-- else
-- -- Try to initialize again
-- v.sd.state := SD_CHECK_PRES;
-- end if;
-- v.spio.errorn := '0';
-- v.sd.timeout := '1';
-- end if;
-- v.spio.csn := '1';
-- end if;
-- v.sd.tcnt := (others => '0');
-- when others => -- SD_CHECK_PRES
-- if r.sd.cd = '1' then
-- v.go := '1';
-- v.spio.csn := '0';
-- v.sd.state := SD_GET_RESP;
-- v.spio.cdcsnoen := OUTPUT;
-- end if;
-- v.sd.htb := '0';
-- v.sd.vresp := '1';
-- v.sd.rstate := SD_PWRUP0;
-- v.sd.rcnt := cslv(10, r.sd.rcnt'length);
-- v.sd.ctocnt := cslv(SD_CMD_TIMEOUT, r.sd.ctocnt'length);
-- end case;
-- end if;
---------------------------------------------------------------------------
-- SPI Flash (non SD) specific code
---------------------------------------------------------------------------
if sdcard = 0 then
case r.spi.state is
when SPI_READ =>
if r.go = '0' then
v.go := '1';
change := '1';
end if;
v.spi.cnt := cslv(SPI_ARG_LEN, r.spi.cnt'length);
if v.bd = '1' then
v.sreg := r.ar(23 downto 16);
end if;
if r.bd = '1' then
v.hold := '0';
v.spi.state := SPI_ADDR;
end if;
when SPI_ADDR =>
if v.bd = '1' then
v.sreg := r.ar(22 downto 15);
if dualoutput = 1 then
if r.spi.cnt = zero32(r.spi.cnt'range) then
v.spio.mosioen := INPUT;
end if;
end if;
end if;
if r.bd = '1' then
if r.spi.cnt = zero32(r.spi.cnt'range) then
v.spi.state := SPI_DATA;
v.spi.cnt := calc_spi_cnt(r.spi.hsize);
else
v.spi.cnt := r.spi.cnt - 1;
end if;
end if;
when SPI_DATA =>
if v.bd = '1' then
v.spi.cnt := r.spi.cnt - 1;
end if;
if lastbit = '1' and r.spi.cnt = zero32(r.spi.cnt'range) then
v.stop := r.go;
end if;
if (r.go or r.spio.sck) = '0' then
if r.spi.hburst(0) = '0' then -- not an incrementing burst
v.spi.state := SPI_PWRUP; -- CSN wait
v.spio.csn := '1';
v.go := '1';
v.stop := '1';
v.seq := '1'; -- Make right choice in SPI_PWRUP
v.bcnt := "110";
else
v.spi.state := SPI_READY;
end if;
v.hold := '1';
end if;
when SPI_READY =>
v.spio.ready := '1';
if read_flash then
v.go := '1';
if dualoutput = 1 then
v.bcnt(2) := '0';
end if;
if r.spio.csn = '1' then
-- New access, command and address
v.go := '0';
v.spio.csn := '0';
v.spi.state := SPI_READ;
elsif r.seq = '1' then
-- Continuation of burst
v.spi.state := SPI_DATA;
v.hold := '0';
else
-- Burst ended and new access
v.stop := '1';
v.spio.csn := '1';
v.spi.state := SPI_PWRUP;
v.bcnt := "011";
end if;
v.ar := (others => '0');
if offset /= 0 then
v.ar(r.haddr'range) := r.haddr + cslv(offset, req_addr_bits);
else
v.ar(r.haddr'range) := r.haddr;
end if;
v.spio.ready := '0';
v.sreg := cslv(readcmd, 8);
end if;
if r.spio.ready = '0' then
case r.spi.hsize is
when HSIZE_BYTE =>
for i in 0 to (MAXDW/8-1) loop
v.frdata(7+8*i downto 8*i):= r.ar(7 downto 0);
end loop; -- i
when HSIZE_HWORD =>
for i in 0 to (MAXDW/16-1) loop
v.frdata(15+16*i downto 16*i) := r.ar(15 downto 0);
end loop; -- i
when HSIZE_WORD =>
for i in 0 to (MAXDW/32-1) loop
v.frdata(31+32*i downto 32*i) := r.ar(31 downto 0);
end loop; -- i
when HSIZE_DWORD =>
if MAXDW > 32 and AHBDW > 32 then
for i in 0 to (MAXDW/64-1) loop
if MAXDW = 64 then
v.frdata(MAXDW-1+MAXDW*i downto MAXDW*i) :=
r.ar(MAXDW-1 downto 0);
elsif MAXDW = 128 then
v.frdata(MAXDW/2-1+MAXDW/2*i downto MAXDW/2*i) :=
r.ar(MAXDW/2-1 downto 0);
else
v.frdata(MAXDW/4-1+MAXDW/4*i downto MAXDW/4*i) :=
r.ar(MAXDW/4-1 downto 0);
end if;
end loop; -- i
else
null;
end if;
when HSIZE_4WORD =>
if MAXDW > 64 and AHBDW > 64 then
for i in 0 to (MAXDW/128-1) loop
if MAXDW = 128 then
v.frdata(MAXDW-1+MAXDW*i downto MAXDW*i) :=
r.ar(MAXDW-1 downto 0);
else
v.frdata(MAXDW/2-1+MAXDW/2*i downto MAXDW/2*i) :=
r.ar(MAXDW/2-1 downto 0);
end if;
end loop; -- i
else
null;
end if;
when others =>
if MAXDW > 128 and AHBDW > 128 then
v.frdata := r.ar;
else
null;
end if;
end case;
end if;
v.spi.hsize := r.hsize;
v.spi.hburst(0) := r.hburst(0);
v.spi.cnt := calc_spi_cnt(r.spi.hsize);
when others => -- SPI_PWRUP
v.hold := '1';
if r.spio.initialized = '1' then
-- Chip select wait
if (r.go or r.spio.sck) = '0' then
if r.seq = '1' then
v.spi.state := SPI_READY;
else
v.spi.state := SPI_READ;
v.spio.csn := '0';
end if;
if dualoutput = 1 then
v.spio.mosioen := OUTPUT;
v.bcnt(2) := '0';
end if;
end if;
else
-- Power up wait
if pwrupcnt /= 0 then
v.frdata := r.frdata - 1;
if r.frdata = zahbdw(r.frdata'range) then
v.spio.initialized := '1';
v.spi.state := SPI_READY;
end if;
else
v.spio.initialized := '1';
v.spi.state := SPI_READY;
end if;
end if;
end case;
end if;
---------------------------------------------------------------------------
-- SPI communication
---------------------------------------------------------------------------
-- Clock generation
if (r.go or r.spio.sck) = '1' then
v.timer := r.timer - 1;
if sck_toggle(v.timer, r.timer, enable_altscaler) then
v.spio.sck := not r.spio.sck;
v.sample(0) := not r.spio.sck;
change := r.spio.sck and r.go;
if (v.stop and lastbit and not r.spio.sck) = '1' then
v.go := '0';
v.stop := '0';
end if;
end if;
else
v.timer := (others => '1');
end if;
if r.sample(0) = '1' then
v.bcnt := r.bcnt + 1;
end if;
if r.sample(1-sdcard) = '1' then
if r.hold = '0' then
if sdcard = 0 and dualoutput = 1 and r.spio.mosioen = INPUT then
v.ar := r.ar(r.ar'left-2 downto 0) & r.spii(1-sdcard).miso & r.spii(1-sdcard).mosi;
else
v.ar := r.ar(r.ar'left-1 downto 0) & r.spii(1-sdcard).miso;
end if;
end if;
end if;
if change = '1' then
v.spio.mosi := v.sreg(7);
if sdcard = 1 or r.spi.state /= SPI_PWRUP then
v.sreg(7 downto 0) := v.sreg(6 downto 0) & '1';
end if;
end if;
---------------------------------------------------------------------------
-- System and core reset
---------------------------------------------------------------------------
if (not rstn or r.rst) = '1' then
-- if sdcard = 1 then
-- v.sd.state := SD_CHECK_PRES;
-- v.spio.cdcsnoen := INPUT;
-- v.sd.timeout := '0';
-- else
v.spi.state := SPI_PWRUP;
v.frdata := cslv(pwrupcnt, r.frdata'length);
v.spio.cdcsnoen := OUTPUT;
-- end if;
v.spimstate := IDLE;
v.rst := '0';
--
v.reg.ctrl := ('0', '0', '0');
v.reg.stat.done := '0';
--
v.sample := (others => '0');
v.sreg := (others => '1');
v.bcnt := (others => '0');
v.go := '0';
v.stop := '0';
v.hold := '0';
v.unsplit := '0';
--
v.hready := '1';
v.hwrite := '0';
v.hsel := '0';
v.hmbsel := (others => '0');
v.ahbcancel := '0';
--
v.spio.sck := '0';
v.spio.mosi := '1';
v.spio.mosioen := OUTPUT;
v.spio.csn := '1';
-- v.spio.errorn := '1';
v.spio.initialized := '0';
v.spio.ready := '0';
end if;
---------------------------------------------------------------------------
-- Drive unused signals
---------------------------------------------------------------------------
-- if sdcard = 1 then
-- v.spi.state := SPI_PWRUP;
-- v.spi.cnt := (others => '0');
-- v.spi.hsize := (others => '0');
-- v.spi.hburst := (others => '0');
-- v.hburst := (others => '0');
-- v.seq := '0';
-- else
-- v.sd.state := SD_CHECK_PRES;
-- v.sd.tcnt := (others => '0');
-- v.sd.rcnt := (others => '0');
-- v.sd.cmd := (others => '0');
-- v.sd.rstate := SD_CHECK_PRES;
-- v.sd.htb := '0';
-- v.sd.vresp := '0';
-- v.sd.timeout := '0';
-- v.sd.dtocnt := (others => '0');
-- v.sd.ctocnt := (others => '0');
-- end if;
if spliten = 0 then
v.insplit := '0';
v.unsplit := '0';
v.splmst := (others => '0');
v.hsplit := (others => '0');
v.ahbcancel := '0';
end if;
---------------------------------------------------------------------------
-- Signal assignments
---------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB slave output
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
if r.hmbsel(CTRL_BANK) = '1' then
for i in 0 to (MAXDW/32-1) loop
hrdata(31 + 32*i downto 32*i) := zero32(31 downto 8) & r.rrdata;
end loop;
else
hrdata := r.frdata;
end if;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hconfig <= HCONFIG;
ahbso.hirq <= ahbirq;
ahbso.hindex <= hindex;
ahbso.hsplit <= hsplit;
-- SPI signals
spio <= r.spio;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"spimctrl" & tost(hindex) & ": SPI memory controller rev " &
tost(REVISION) & ", irq " & tost(hirq));
-- pragma translate_on
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.rtl_pack.all;
use work.tb_pack.all;
entity gearbox_tb is
end;
architecture tb of gearbox_tb is
constant a_width_g : positive := 4;
constant b_width_g : positive := 3;
constant fifo_depth_order_g : positive := 4;
signal run : boolean := true;
signal reset : std_ulogic := '1';
signal a_reset_i : std_ulogic;
signal a_clock_i : std_ulogic;
signal a_data_i, a_data_o : std_ulogic_vector(a_width_g-1 downto 0);
signal b_reset_i : std_ulogic;
signal b_clock_i : std_ulogic;
signal b_data : std_ulogic_vector(b_width_g-1 downto 0);
signal pll_lock : std_ulogic;
begin
clk_gen(a_clock_i, run);
pll : entity work.pll
generic map (
multiplier_g => a_width_g,
divider_g => b_width_g)
port map (
run_i => run,
clock_i => a_clock_i,
clock_o => b_clock_i,
lock_o => pll_lock);
reset_a_sync : entity work.sync
generic map (
reset_value_g => '1')
port map (
reset_i => reset,
clock_i => a_clock_i,
data_i(0) => reset,
data_o(0) => a_reset_i);
reset_b_sync : entity work.sync
generic map (
reset_value_g => '1')
port map (
reset_i => reset,
clock_i => b_clock_i,
data_i(0) => reset,
data_o(0) => b_reset_i);
gearbox_a_b : entity work.gearbox
generic map (
a_width_g => a_width_g,
b_width_g => b_width_g,
fifo_depth_order_g => fifo_depth_order_g)
port map (
a_reset_i => a_reset_i,
a_clock_i => a_clock_i,
a_data_i => a_data_i,
b_reset_i => b_reset_i,
b_clock_i => b_clock_i,
b_data_o => b_data);
gearbox_b_a : entity work.gearbox
generic map (
a_width_g => b_width_g,
b_width_g => a_width_g,
fifo_depth_order_g => fifo_depth_order_g)
port map (
a_reset_i => b_reset_i,
a_clock_i => b_clock_i,
a_data_i => b_data,
b_reset_i => a_reset_i,
b_clock_i => a_clock_i,
b_data_o => a_data_o);
stim : process
begin
rst_gen(reset);
wait until (a_reset_i or b_reset_i) = '0';
for i in 0 to 2**a_width_g-1 loop
a_data_i <= std_ulogic_vector(to_unsigned(i, a_width_g));
wait_clk(a_clock_i);
end loop;
wait_clk(a_clock_i, 2**(fifo_depth_order_g+1));
run <= false;
wait;
end process;
end; |
entity test_output is
port (
output : inout integer := 10
);
end test_output;
architecture only of test_output is
begin -- test_output
test: process
begin -- process test
assert output = 10 report "test failed" severity error;
assert output /= 10 report "test passed" severity note;
wait;
end process test;
end only;
|
entity test_output is
port (
output : inout integer := 10
);
end test_output;
architecture only of test_output is
begin -- test_output
test: process
begin -- process test
assert output = 10 report "test failed" severity error;
assert output /= 10 report "test passed" severity note;
wait;
end process test;
end only;
|
entity test_output is
port (
output : inout integer := 10
);
end test_output;
architecture only of test_output is
begin -- test_output
test: process
begin -- process test
assert output = 10 report "test failed" severity error;
assert output /= 10 report "test passed" severity note;
wait;
end process test;
end only;
|
library verilog;
use verilog.vl_types.all;
entity dcfifo_low_latency is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_width_r : vl_notype;
lpm_widthu_r : vl_notype;
lpm_numwords : integer := 2;
delay_rdusedw : integer := 2;
delay_wrusedw : integer := 2;
rdsync_delaypipe: integer := 0;
wrsync_delaypipe: integer := 0;
intended_device_family: string := "Stratix";
lpm_showahead : string := "OFF";
underflow_checking: string := "ON";
overflow_checking: string := "ON";
add_usedw_msb_bit: string := "OFF";
read_aclr_synch : string := "OFF";
write_aclr_synch: string := "OFF";
use_eab : string := "ON";
clocks_are_synchronized: string := "FALSE";
add_ram_output_register: string := "OFF";
lpm_hint : string := "USE_EAB=ON";
WIDTH_RATIO : vl_notype;
FIFO_DEPTH : vl_notype
);
port(
data : in vl_logic_vector;
rdclk : in vl_logic;
wrclk : in vl_logic;
aclr : in vl_logic;
rdreq : in vl_logic;
wrreq : in vl_logic;
rdfull : out vl_logic;
wrfull : out vl_logic;
rdempty : out vl_logic;
wrempty : out vl_logic;
rdusedw : out vl_logic_vector;
wrusedw : out vl_logic_vector;
q : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_width : constant is 1;
attribute mti_svvh_generic_type of lpm_widthu : constant is 1;
attribute mti_svvh_generic_type of lpm_width_r : constant is 3;
attribute mti_svvh_generic_type of lpm_widthu_r : constant is 3;
attribute mti_svvh_generic_type of lpm_numwords : constant is 1;
attribute mti_svvh_generic_type of delay_rdusedw : constant is 1;
attribute mti_svvh_generic_type of delay_wrusedw : constant is 1;
attribute mti_svvh_generic_type of rdsync_delaypipe : constant is 1;
attribute mti_svvh_generic_type of wrsync_delaypipe : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_showahead : constant is 1;
attribute mti_svvh_generic_type of underflow_checking : constant is 1;
attribute mti_svvh_generic_type of overflow_checking : constant is 1;
attribute mti_svvh_generic_type of add_usedw_msb_bit : constant is 1;
attribute mti_svvh_generic_type of read_aclr_synch : constant is 1;
attribute mti_svvh_generic_type of write_aclr_synch : constant is 1;
attribute mti_svvh_generic_type of use_eab : constant is 1;
attribute mti_svvh_generic_type of clocks_are_synchronized : constant is 1;
attribute mti_svvh_generic_type of add_ram_output_register : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of WIDTH_RATIO : constant is 3;
attribute mti_svvh_generic_type of FIFO_DEPTH : constant is 3;
end dcfifo_low_latency;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_7;
USE axi_bram_ctrl_v4_0_7.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_0_0;
ARCHITECTURE design_1_axi_bram_ctrl_0_0_arch OF design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_0_0_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_7;
USE axi_bram_ctrl_v4_0_7.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_0_0;
ARCHITECTURE design_1_axi_bram_ctrl_0_0_arch OF design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_0_0_arch;
|
architecture ARCH of ENTITY is
signal sig1, sig2, sig3,
sig4, sig5, sig6 : std_logic;
signal siga, sigb,
sigc,
sigd,
sige,
sigf
: std_logic; -- This is a comment
-- Test variations of a single signal declaration
signal sig1 : std_logic;
signal sig1 : std_logic
;
signal sig1 :
std_logic
;
signal sig1
:
std_logic
;
signal
sig1
:
std_logic
;
-- Test variations of a two signal declarations
signal sig1, sig2 : std_logic;
signal sig1, sig2 : std_logic
;
signal sig1, sig2 :
std_logic
;
signal sig1, sig2
:
std_logic
;
signal sig1,
sig2
:
std_logic
;
signal sig1
,
sig2
:
std_logic
;
signal
sig1
,
sig2
:
std_logic
;
signal sig1, sig2 : std_logic; -- Comma, should not induce a failure
-- This should pass
signal foo : std_logic_vector(maximum(G_A, G_B) + maximum(C_A, C_B)-1 downto 0);
signal foo, bar, mine : std_logic_vector(maximum(G_A, G_B) + maximum(C_A, C_B)-1 downto 0);
signal ar,ai,ar3,ai3: STD_LOGIC_VECTOR (width-1 downto 0);
signal br1,bi1,br,bi,br2,bi2: STD_LOGIC_VECTOR (width-1 downto 0);
begin
end architecture ARCH;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
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`protect end_protected
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gen_mul_61x61
-- File: mul_inferred.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Generic 61x61 multplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
entity gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of gen_mul_61x61 is
signal r1, r1in, r2, r2in : std_logic_vector(121 downto 0);
begin
comb : process(A, B, r1)
begin
-- pragma translate_off
if not (is_x(A) or is_x(B)) then
-- pragma translate_on
r1in <= std_logic_vector(unsigned(A) * unsigned(B));
-- pragma translate_off
end if;
-- pragma translate_on
r2in <= r1;
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if EN = '1' then
r1 <= r1in;
r2 <= r2in;
end if;
end if;
end process;
PRODUCT <= r2;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity gen_mult_pipe is
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1); -- '0': non-stallable; '1': stallable
port (
clk : in std_logic; -- register clock
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end ;
architecture simple of gen_mult_pipe is
subtype resw is std_logic_vector(A_width+B_width-1 downto 0);
type pipet is array (num_stages-1 downto 1) of resw;
signal p_i : pipet;
signal prod : resw;
begin
comb : process(A, B, TC)
begin
-- pragma translate_off
if notx(A) and notx(B) and notx(tc) then
-- pragma translate_on
if TC = '1' then
prod <= signed(A) * signed(B);
else
prod <= unsigned(A) * unsigned(B);
end if;
-- pragma translate_off
else
prod <= (others => 'X');
end if;
-- pragma translate_on
end process;
w2 : if num_stages = 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i(1) <= prod;
end if;
end if;
end process;
end generate;
w3 : if num_stages > 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i <= p_i(num_stages-2 downto 1) & prod;
end if;
end if;
end process;
end generate;
product <= p_i(num_stages-1);
end;
|
-- NEED RESULT: ARCH00558: Variable declarations - composite static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00558
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.3 (10)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00558)
-- ENT00558_Test_Bench(ARCH00558_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00558 of E00000 is
begin
process
variable correct : boolean := true ;
variable va_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
variable va_st_string_1 : st_string
:= c_st_string_1 ;
variable va_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
variable va_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
variable va_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
variable va_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
variable va_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
variable va_st_arr3_1 : st_arr3
:= c_st_arr3_1 ;
begin
correct := correct and va_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and va_st_string_1 = c_st_string_1 ;
correct := correct and va_st_rec1_1 = c_st_rec1_1 ;
correct := correct and va_st_rec2_1 = c_st_rec2_1 ;
correct := correct and va_st_rec3_1 = c_st_rec3_1 ;
correct := correct and va_st_arr1_1 = c_st_arr1_1 ;
correct := correct and va_st_arr2_1 = c_st_arr2_1 ;
correct := correct and va_st_arr3_1 = c_st_arr3_1 ;
va_st_bit_vector_1 := c_st_bit_vector_2 ;
va_st_string_1 := c_st_string_2 ;
va_st_rec1_1 := c_st_rec1_2 ;
va_st_rec2_1 := c_st_rec2_2 ;
va_st_rec3_1 := c_st_rec3_2 ;
va_st_arr1_1 := c_st_arr1_2 ;
va_st_arr2_1 := c_st_arr2_2 ;
va_st_arr3_1 := c_st_arr3_2 ;
correct := correct and va_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and va_st_string_1 = c_st_string_2 ;
correct := correct and va_st_rec1_1 = c_st_rec1_2 ;
correct := correct and va_st_rec2_1 = c_st_rec2_2 ;
correct := correct and va_st_rec3_1 = c_st_rec3_2 ;
correct := correct and va_st_arr1_1 = c_st_arr1_2 ;
correct := correct and va_st_arr2_1 = c_st_arr2_2 ;
correct := correct and va_st_arr3_1 = c_st_arr3_2 ;
test_report ( "ARCH00558" ,
"Variable declarations - composite static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00558 ;
--
entity ENT00558_Test_Bench is
end ENT00558_Test_Bench ;
--
architecture ARCH00558_Test_Bench of ENT00558_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00558 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00558_Test_Bench ;
|
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-05C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- I,J,U,V,T,G,L & D registers and A,B bus assembly
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY RegsABAssm IS
port
(
-- Inputs
-- A_BUS_IN : INOUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
SALS : IN SALS_BUS;
MACH_RST_SET_LCH : IN STD_LOGIC; -- 03B
SEL_SHARE_CYCLE : IN STD_LOGIC; -- ?
USE_MAN_DECODER : IN STD_LOGIC; -- 03D
MAN_STOR_PWR : IN STD_LOGIC; -- 03D
USE_MAN_DECODER_PWR : IN STD_LOGIC; -- 03D
FG_SWS : IN STD_LOGIC_VECTOR(0 to 7); -- 04C
FG_SW_P : IN STD_LOGIC;
HJ_SWS : IN STD_LOGIC_VECTOR(0 to 7); -- 8 is P
HJ_SW_P : IN STD_LOGIC;
USE_BASIC_CA_DECODER : IN STD_LOGIC; -- 02A
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
MPX_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 08C 8 is P
FT0,FT3,FT5,FT6 : IN STD_LOGIC; -- 08D
FT1 : IN STD_LOGIC; -- 07C
FT2,FT7 : IN STD_LOGIC; -- 08C
FT4 : IN STD_LOGIC; -- 03C
E_SW_SEL_BUS : IN E_SW_BUS_TYPE; -- 04C
CD_CTRL_REG : IN STD_LOGIC_VECTOR(0 to 3);
CD_REG_2 : IN STD_LOGIC; -- 04C Unused
MACH_RST_2A_B : IN STD_LOGIC; -- 06B
Z_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 06B 8 is P
R_REG : IN STD_LOGIC_VECTOR(0 to 8); -- 06C 8 is P
-- Outputs
USE_CPU_DECODER : OUT STD_LOGIC; -- 05B,04D
GATED_CA_BITS : OUT STD_LOGIC_VECTOR(0 to 3); -- 07C,10C
GT_J_TO_A,GT_D_TO_A : OUT STD_LOGIC; -- 03C
I,J,U,V,T,G,L : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
A_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 06B 8 is P
B_BUS_OUT : OUT STD_LOGIC_VECTOR(0 to 8); -- 06B 8 is P
-- Clocks
T4 : IN STD_LOGIC
);
END RegsABAssm;
ARCHITECTURE FMD OF RegsABAssm IS
alias CA : STD_LOGIC_VECTOR(0 to 3) is SALS.SALS_CA;
alias CK : STD_LOGIC_VECTOR(0 to 3) is SALS.SALS_CK;
alias CB : STD_LOGIC_VECTOR(0 to 1) is SALS.SALS_CB;
alias AK_SAL_BIT : STD_LOGIC is SALS.SALS_AK;
signal GT_HJ_SWS_TO_B_BUS : STD_LOGIC;
signal GT_R_TO_B,GT_L_TO_B,GT_D_TO_B,GT_CK_TO_B : STD_LOGIC;
signal GT_FG_TO_A, GT_MPX_TAGS_TO_A, GT_MPX_BUS_TO_A,GT_I_TO_A,GT_U_TO_A, GT_V_TO_A,GT_T_TO_A,GT_G_TO_A,GT_L_TO_A,GT_R_TO_A : STD_LOGIC;
signal LCH_I,LCH_J,LCH_U,LCH_V,LCH_T,LCH_G,LCH_L,LCH_D : STD_LOGIC;
signal sUSE_CPU_DECODER : STD_LOGIC;
signal sGATED_CA_BITS : STD_LOGIC_VECTOR(0 to 3);
signal sGT_J_TO_A, sGT_D_TO_A : STD_LOGIC;
signal sI,sJ,sU,sV,sT,sG,sL,sD : STD_LOGIC_VECTOR(0 to 8);
BEGIN
-- Fig 5-05C
sUSE_CPU_DECODER <= not MACH_RST_SET_LCH and not SEL_SHARE_CYCLE and not USE_MAN_DECODER; -- AB3C5
USE_CPU_DECODER <= sUSE_CPU_DECODER;
sGATED_CA_BITS <= CA and (0 to 3 => sUSE_CPU_DECODER); -- AA2J6,AA2J2
GATED_CA_BITS <= sGATED_CA_BITS;
GT_HJ_SWS_TO_B_BUS <= (not CK(0) and CK(1) and not CK(2) and not CK(3) and AK_SAL_BIT) or (MAN_STOR_PWR and USE_MAN_DECODER_PWR); -- AB3H7
GT_R_TO_B <= not CB(0) and not CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
GT_L_TO_B <= not CB(0) and CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
GT_D_TO_B <= CB(0) and not CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
GT_CK_TO_B <= CB(0) and CB(1) and not GT_HJ_SWS_TO_B_BUS and sUSE_CPU_DECODER;
B_BUS_OUT <= ((0 to 8 => GT_R_TO_B) and R_REG) or -- AB1K5
((0 to 8 => GT_L_TO_B) and sL) or -- AB1K5
((0 to 8 => GT_D_TO_B) and sD) or -- AB1K5
((0 to 8 => GT_CK_TO_B) and CK & CK & '1') or -- AB1L5
((0 to 8 => GT_HJ_SWS_TO_B_BUS) and HJ_SWS & HJ_SW_P); -- AB1L5
GT_FG_TO_A <= '1' when sGATED_CA_BITS="0001" and USE_ALT_CA_DECODER='1' else '0'; -- AB1F5
GT_MPX_TAGS_TO_A <= '1' when (sGATED_CA_BITS="0000" and USE_BASIC_CA_DECODER='1' and sUSE_CPU_DECODER='1') or (E_SW_SEL_BUS.FT_SEL='1' and USE_MAN_DECODER_PWR='1') else '0'; -- AA2C6 ?? and sUSE_CPU_DECODER required to prevent FT (CA=0000) from being put on A bus when not wanted
GT_MPX_BUS_TO_A <= '1' when (sGATED_CA_BITS="0110" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.FI_SEL='1') else '0'; -- AB3C3
GT_I_TO_A <= '1' when (sGATED_CA_BITS="1111" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.I_SEL='1') else '0'; -- AB1F4
sGT_J_TO_A <= '1' when (sGATED_CA_BITS="1110" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.J_SEL='1') else '0'; -- AB1F4
GT_J_TO_A <= sGT_J_TO_A;
GT_U_TO_A <= '1' when (sGATED_CA_BITS="1101" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.U_SEL='1') else '0'; -- AB1F4
GT_V_TO_A <= '1' when (sGATED_CA_BITS="1100" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.V_SEL='1') else '0'; -- AB1F4
GT_T_TO_A <= '1' when (sGATED_CA_BITS="1011" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.T_SEL='1') else '0'; -- AB1F4
GT_G_TO_A <= '1' when (sGATED_CA_BITS="1010" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.G_SEL='1') else '0'; -- AB1F4
GT_L_TO_A <= '1' when (sGATED_CA_BITS="1001" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.L_SEL='1') else '0'; -- AB3C3
sGT_D_TO_A <= '1' when (sGATED_CA_BITS="1000" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.D_SEL='1') else '0'; -- AB3C3
GT_D_TO_A <= sGT_D_TO_A;
GT_R_TO_A <= '1' when (sGATED_CA_BITS="0111" and USE_BASIC_CA_DECODER='1') or (USE_MAN_DECODER_PWR='1' and E_SW_SEL_BUS.R_SEL='1') else '0'; -- AB3C3
A_BUS <= not(FG_SWS & FG_SW_P) when GT_FG_TO_A='1' else
not(FT0 & FT1 & FT2 & FT3 & FT4 & FT5 & FT6 & FT7 & '0') when GT_MPX_TAGS_TO_A='1' else
not MPX_BUS when GT_MPX_BUS_TO_A='1' else
not sI when GT_I_TO_A='1' else
not sJ when sGT_J_TO_A='1' else
not sU when GT_U_TO_A='1' else
not sV when GT_V_TO_A='1' else
not sT when GT_T_TO_A='1' else
not sG when GT_G_TO_A='1' else
not sL when GT_L_TO_A='1' else
not sD when sGT_D_TO_A='1' else
not R_REG when GT_R_TO_A='1' else
"111111111";
-- A_BUS_OUT <= A_BUS_IN or
-- ((0 to 8 => GT_FG_TO_A) and FG_SWS & FG_SW_P) or -- AB1D6
-- ((0 to 8 => GT_MPX_TAGS_TO_A) and FT0 & FT1 & FT2 & FT3 & FT4 & FT5 & FT6 & FT7 & '0') or -- AB1D6
-- ((0 to 8 => GT_MPX_BUS_TO_A) and MPX_BUS) or -- AB1D6
-- ((0 to 8 => GT_I_TO_A) and sI) or -- AB1F4
-- ((0 to 8 => sGT_J_TO_A) and sJ) or -- AB1F4
-- ((0 to 8 => GT_U_TO_A) and sU) or -- AB1F4
-- ((0 to 8 => GT_V_TO_A) and sV) or -- AB1C7
-- ((0 to 8 => GT_T_TO_A) and sT) or -- AB1C7
-- ((0 to 8 => GT_G_TO_A) and sG) or -- AB1C7
-- ((0 to 8 => GT_L_TO_A) and sL) or -- AB3C3
-- ((0 to 8 => sGT_D_TO_A) and sD) or -- AB3C3
-- ((0 to 8 => GT_R_TO_A) and R_REG); -- AB3C3
LCH_I <= '1' when (CD_CTRL_REG="1111" and T4='1') or (E_SW_SEL_BUS.I_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1G5
LCH_J <= '1' when (CD_CTRL_REG="1110" and T4='1') or (E_SW_SEL_BUS.J_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1G5
LCH_U <= '1' when (CD_CTRL_REG="1101" and T4='1') or (E_SW_SEL_BUS.U_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1G5
LCH_V <= '1' when (CD_CTRL_REG="1100" and T4='1') or (E_SW_SEL_BUS.V_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1H5
LCH_T <= '1' when (CD_CTRL_REG="1011" and T4='1') or (E_SW_SEL_BUS.T_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1H5
LCH_G <= '1' when (CD_CTRL_REG="1010" and T4='1') or (E_SW_SEL_BUS.G_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1H5
LCH_L <= '1' when (CD_CTRL_REG="1001" and T4='1') or (E_SW_SEL_BUS.L_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1J2
LCH_D <= '1' when (CD_CTRL_REG="1000" and T4='1') or (E_SW_SEL_BUS.D_SEL='1' and MAN_STOR_PWR='1') or MACH_RST_2A_B='1' else '0'; -- AB1J2
I_REG: PHV9 port map(Z_BUS,LCH_I,sI); -- AB1G3
I <= sI;
J_REG: PHV9 port map(Z_BUS,LCH_J,sJ); -- AB1G4
J <= sJ;
U_REG: PHV9 port map(Z_BUS,LCH_U,sU); -- AB1H3
U <= sU;
V_REG: PHV9 port map(Z_BUS,LCH_V,sV); -- AB1H4
V <= sV;
T_REG: PHV9 port map(Z_BUS,LCH_T,sT); -- AB1J4
T <= sT;
G_REG: PHV9 port map(Z_BUS,LCH_G,sG); -- AB1K4
G <= sG;
L_REG: PHV9 port map(Z_BUS,LCH_L,sL); -- AB1J2
L <= sL;
D_REG: PHV9 port map(Z_BUS,LCH_D,sD); -- AB1K3
END FMD;
|
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.mac_types.all;
entity mac_expectedoutput is
port(arg : in signed(8 downto 0);
-- clock
system1000 : in std_logic;
-- asynchronous reset: active low
system1000_rstn : in std_logic;
result : out boolean);
end;
architecture structural of mac_expectedoutput is
begin
mac_outputverifier_soutputverifier_result : entity mac_outputverifier_soutputverifier
port map
(result => result
,system1000 => system1000
,system1000_rstn => system1000_rstn
,i => arg);
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2456.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02456ent IS
END c07s03b02x02p03n02i02456ent;
ARCHITECTURE c07s03b02x02p03n02i02456arch OF c07s03b02x02p03n02i02456ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of CHARACTER;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
function F return CONSTRAINED_ARRAY is
begin
return ( 'a','b', others => 'c' );
-- "others" choice is legal.
end F;
BEGIN
TESTING: PROCESS
variable k : CONSTRAINED_ARRAY;
BEGIN
k := F;
assert NOT(k(1)='a' and k(2)='b' and k(3)='c')
report "***PASSED TEST: c07s03b02x02p03n02i02456"
severity NOTE;
assert (k(1)='a' and k(2)='b' and k(3)='c')
report "***FAILED TEST: c07s03b02x02p03n02i02456 - The others choice should be allowed as the aggregate is the result expression of a function."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02456arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2456.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02456ent IS
END c07s03b02x02p03n02i02456ent;
ARCHITECTURE c07s03b02x02p03n02i02456arch OF c07s03b02x02p03n02i02456ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of CHARACTER;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
function F return CONSTRAINED_ARRAY is
begin
return ( 'a','b', others => 'c' );
-- "others" choice is legal.
end F;
BEGIN
TESTING: PROCESS
variable k : CONSTRAINED_ARRAY;
BEGIN
k := F;
assert NOT(k(1)='a' and k(2)='b' and k(3)='c')
report "***PASSED TEST: c07s03b02x02p03n02i02456"
severity NOTE;
assert (k(1)='a' and k(2)='b' and k(3)='c')
report "***FAILED TEST: c07s03b02x02p03n02i02456 - The others choice should be allowed as the aggregate is the result expression of a function."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02456arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2456.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02456ent IS
END c07s03b02x02p03n02i02456ent;
ARCHITECTURE c07s03b02x02p03n02i02456arch OF c07s03b02x02p03n02i02456ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of CHARACTER;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
function F return CONSTRAINED_ARRAY is
begin
return ( 'a','b', others => 'c' );
-- "others" choice is legal.
end F;
BEGIN
TESTING: PROCESS
variable k : CONSTRAINED_ARRAY;
BEGIN
k := F;
assert NOT(k(1)='a' and k(2)='b' and k(3)='c')
report "***PASSED TEST: c07s03b02x02p03n02i02456"
severity NOTE;
assert (k(1)='a' and k(2)='b' and k(3)='c')
report "***FAILED TEST: c07s03b02x02p03n02i02456 - The others choice should be allowed as the aggregate is the result expression of a function."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02456arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1585.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p02n01i01585ent IS
END c08s11b00x00p02n01i01585ent;
ARCHITECTURE c08s11b00x00p02n01i01585arch OF c08s11b00x00p02n01i01585ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
while k < 10 loop
exit when k = 5;
k := k + 1;
end loop;
assert NOT( k=5 )
report "***PASSED TEST: c08s11b00x00p02n01i01585"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s11b00x00p02n01i01585 - The loop label in the exit statement is optional"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p02n01i01585arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1585.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p02n01i01585ent IS
END c08s11b00x00p02n01i01585ent;
ARCHITECTURE c08s11b00x00p02n01i01585arch OF c08s11b00x00p02n01i01585ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
while k < 10 loop
exit when k = 5;
k := k + 1;
end loop;
assert NOT( k=5 )
report "***PASSED TEST: c08s11b00x00p02n01i01585"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s11b00x00p02n01i01585 - The loop label in the exit statement is optional"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p02n01i01585arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1585.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p02n01i01585ent IS
END c08s11b00x00p02n01i01585ent;
ARCHITECTURE c08s11b00x00p02n01i01585arch OF c08s11b00x00p02n01i01585ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
while k < 10 loop
exit when k = 5;
k := k + 1;
end loop;
assert NOT( k=5 )
report "***PASSED TEST: c08s11b00x00p02n01i01585"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s11b00x00p02n01i01585 - The loop label in the exit statement is optional"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p02n01i01585arch;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for vgca_tb
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca_tb-struct-conf-c.vhd,v 1.2 2005/04/14 06:53:00 wig Exp $
-- $Date: 2005/04/14 06:53:00 $
-- $Log: vgca_tb-struct-conf-c.vhd,v $
-- Revision 1.2 2005/04/14 06:53:00 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration vgca_tb_struct_conf / vgca_tb
--
configuration vgca_tb_struct_conf of vgca_tb is
for struct
-- Generated Configuration
for dut : vgca
use configuration work.vgca_struct_conf;
end for;
end for;
end vgca_tb_struct_conf;
--
-- End of Generated Configuration vgca_tb_struct_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- test_ng.vhd
entity TEST_NG is
generic (
INFO_BITS : integer := 1;
INFO_1_VAL : integer := 0
);
port (
I_INFO_0 : in bit_vector(INFO_BITS-1 downto 0);
I_INFO_1 : in bit_vector(INFO_BITS-1 downto 0);
O_INFO_0 : out bit_vector(INFO_BITS-1 downto 0);
O_INFO_1 : out bit_vector(INFO_BITS-1 downto 0)
);
end TEST_NG;
architecture MODEL of TEST_NG is
type INFO_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
end record;
type VEC_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
INFO_0 : INFO_RANGE_TYPE;
INFO_1 : INFO_RANGE_TYPE;
end record;
function SET_VEC_RANGE return VEC_RANGE_TYPE is
variable d_pos : integer;
variable v : VEC_RANGE_TYPE;
procedure SET_INFO_RANGE(INFO_RANGE: inout INFO_RANGE_TYPE; BITS: in integer) is
begin
INFO_RANGE.DATA_LO := d_pos;
INFO_RANGE.DATA_HI := d_pos + BITS-1;
d_pos := d_pos + BITS;
end procedure;
begin
d_pos := 0;
v.DATA_LO := d_pos;
SET_INFO_RANGE(v.INFO_0, INFO_BITS);
if (INFO_1_VAL /= 0) then
SET_INFO_RANGE(v.INFO_1, INFO_BITS);
end if;
v.DATA_HI := d_pos - 1;
if (INFO_1_VAL = 0) then
SET_INFO_RANGE(v.INFO_1, INFO_BITS);
end if;
return v;
end function;
constant VEC_RANGE : VEC_RANGE_TYPE := SET_VEC_RANGE;
signal i_data : bit_vector(VEC_RANGE.DATA_HI downto VEC_RANGE.DATA_LO);
begin
i_data(VEC_RANGE.INFO_0.DATA_HI downto VEC_RANGE.INFO_0.DATA_LO) <= I_INFO_0;
O_INFO_0 <= i_data(VEC_RANGE.INFO_0.DATA_HI downto VEC_RANGE.INFO_0.DATA_LO);
INFO_1: if (INFO_1_VAL /= 0) generate
i_data(VEC_RANGE.INFO_1.DATA_HI downto VEC_RANGE.INFO_1.DATA_LO) <= I_INFO_1;
O_INFO_1 <= i_data(VEC_RANGE.INFO_1.DATA_HI downto VEC_RANGE.INFO_1.DATA_LO);
end generate;
end MODEL;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net4
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net4
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net5,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net4
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net4
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net5,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_ROM_2Pos is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
READ_EN : in STD_LOGIC;
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture cRAM of Q16_8_ROM_2Pos is
type rom_type is array (0 to 288-1) of UNSIGNED(2 downto 0);
constant rom_2Pos : rom_type := (
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3), TO_UNSIGNED(6, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3),
TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3), TO_UNSIGNED(7, 3)
);
SIGNAL READ_C : UNSIGNED(11 downto 0);
--SIGNAL WRITE_C : UNSIGNED(11 downto 0);
--SIGNAL ROM_ADR : UNSIGNED(11 downto 0);
--signal IN_BIS : STD_LOGIC_VECTOR (15 downto 0);
--signal WE_BIS : STD_LOGIC;
--signal HD_BIS : STD_LOGIC;
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
--PROCESS
--BEGIN
--WAIT FOR 1 ns;
--printmsg("(IMS) Q16_8_IndexLUT : ALLOCATION OK !");
--WAIT;
--END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(11 downto 0);
VARIABLE ADR : INTEGER RANGE 0 to 288;
begin
if reset = '0' then
READ_C <= TO_UNSIGNED(0, 12);
OUTPUT_1(2 downto 0) <= "000";
elsif clock'event and clock = '1' then
TEMP := READ_C;
if read_en = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 12);
IF TEMP = 288 THEN
TEMP := TO_UNSIGNED(0, 12);
END IF;
end if;
READ_C <= TEMP;
ADR := to_integer( TEMP );
OUTPUT_1(2 downto 0) <= STD_LOGIC_VECTOR( rom_2Pos( ADR ) );
end if;
end process;
OUTPUT_1(31 downto 3) <= "00000000000000000000000000000";
END cRAM; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_CalcBuckParams is
end tb_CalcBuckParams;
architecture tb_CalcBuckParams of tb_CalcBuckParams is
-- Component declarations
-- Signal declarations
quantity Cmin : capacitance;
quantity freq_in : real;
quantity Lmin : inductance;
begin
-- Signal assignments
-- Component instances
src1 : entity work.src_pulse(ideal)
generic map(
initial => 25.0e3,
pulse => 200.0e3,
ti2p => 1ms,
tp2i => 1ms,
delay => 1ms,
width => 100ms,
period => 1000ms
)
port map(
output => freq_in
);
CalcBuckParams1 : entity work.CalcBuckParams_wa(ideal)
generic map(
Vripple => 100.0e-3,
Vin => 42.0,
Vout => 4.8,
Vd => 0.7,
Imin => 15.0e-3,
Resr => 50.0e-3
)
port map(
Fsw => freq_in,
Lmin => Lmin,
Cmin => Cmin
);
end tb_CalcBuckParams;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_CalcBuckParams is
end tb_CalcBuckParams;
architecture tb_CalcBuckParams of tb_CalcBuckParams is
-- Component declarations
-- Signal declarations
quantity Cmin : capacitance;
quantity freq_in : real;
quantity Lmin : inductance;
begin
-- Signal assignments
-- Component instances
src1 : entity work.src_pulse(ideal)
generic map(
initial => 25.0e3,
pulse => 200.0e3,
ti2p => 1ms,
tp2i => 1ms,
delay => 1ms,
width => 100ms,
period => 1000ms
)
port map(
output => freq_in
);
CalcBuckParams1 : entity work.CalcBuckParams_wa(ideal)
generic map(
Vripple => 100.0e-3,
Vin => 42.0,
Vout => 4.8,
Vd => 0.7,
Imin => 15.0e-3,
Resr => 50.0e-3
)
port map(
Fsw => freq_in,
Lmin => Lmin,
Cmin => Cmin
);
end tb_CalcBuckParams;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_CalcBuckParams is
end tb_CalcBuckParams;
architecture tb_CalcBuckParams of tb_CalcBuckParams is
-- Component declarations
-- Signal declarations
quantity Cmin : capacitance;
quantity freq_in : real;
quantity Lmin : inductance;
begin
-- Signal assignments
-- Component instances
src1 : entity work.src_pulse(ideal)
generic map(
initial => 25.0e3,
pulse => 200.0e3,
ti2p => 1ms,
tp2i => 1ms,
delay => 1ms,
width => 100ms,
period => 1000ms
)
port map(
output => freq_in
);
CalcBuckParams1 : entity work.CalcBuckParams_wa(ideal)
generic map(
Vripple => 100.0e-3,
Vin => 42.0,
Vout => 4.8,
Vd => 0.7,
Imin => 15.0e-3,
Resr => 50.0e-3
)
port map(
Fsw => freq_in,
Lmin => Lmin,
Cmin => Cmin
);
end tb_CalcBuckParams;
|
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-03C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Clock Start & Stop control
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Change PROC_STOP_LOOP condition to make STOP/START buttons happier
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY ClockStartStop IS
port
(
-- Switches
SW_START,SW_LOAD,SW_SET_IC,SW_STOP : IN std_logic;
SW_INH_CF_STOP,SW_PROC,SW_SCAN : IN std_logic;
SW_SINGLE_CYCLE,SW_INSTRUCTION_STEP,SW_RATE_SW_PROCESS : IN std_logic;
SW_PWR_OFF : IN std_logic;
-- Other inputs
ALLOW_MAN_OPER : IN std_logic;
FT3_MPX_SHARE_REQ : IN std_logic;
M_CONV_OSC : IN std_logic;
SEL_ROS_REQ : IN std_logic;
MACH_RST_3 : IN std_logic;
CLOCK_ON : IN std_logic;
SAR_DLYD_STOP_SW : IN std_logic;
MATCH : IN std_logic;
SALS : IN SALS_Bus;
FORCE_IJ_REQ : IN std_logic;
MACH_START_RST : IN std_logic;
MACH_RST_SW : IN std_logic;
USE_BASIC_CA_DECO : IN std_logic;
S_REG_1_DLYD : IN std_logic;
INTERRUPT : IN std_logic;
END_OF_E_CY_LCH : IN std_logic;
ANY_PRIORITY_PULSE : IN std_logic;
FORCE_IJ_REQ_LCH : IN std_logic;
P_CONV_OSC : IN std_logic;
MAN_OPERATION : IN std_logic;
ALLOW_WRITE : IN std_logic;
MACH_CHK_PULSE : IN std_logic;
MACH_CHK_RST : IN std_logic;
HZ_DEST_RST : IN std_logic;
FIRST_MACH_CHK : IN std_logic;
CHK_OR_DIAG_STOP_SW : IN std_logic;
ANY_MACH_CHK : IN std_logic;
MATCH_LCH : IN std_logic;
EARLY_ROAR_STOP_SW : IN std_logic;
ALU_CHK : IN std_logic;
DIAGNOSTIC_SW : IN std_logic;
CS_DECODE_X001 : IN std_logic;
BASIC_CS0 : IN std_logic;
SUPPR_MACH_CHK_TRAP : IN std_logic;
Z_BUS_0 : IN std_logic;
SAR_STOP_SW : IN std_logic;
ROAR_STOP_SW : IN std_logic;
ANY_PRIORITY_PULSE_PWR : IN std_logic;
GT_CK_DECODE : IN std_logic;
SX1_SHARE_CYCLE,SX2_SHARE_CYCLE : IN std_logic;
SEL_T4 : IN std_logic;
SEL_SHARE_HOLD : IN std_logic;
SEL_CONV_OSC : IN std_logic;
SEL_BASIC_CLOCK_OFF : IN std_logic;
GT_J_REG_TO_A_BUS : IN std_logic;
M_CONV_OSC_2 : IN std_logic;
MPX_SHARE_REQ : IN std_logic;
SYSTEM_RESET_SW : IN std_logic;
-- Outputs
START_SW_RST : OUT std_logic;
E_CY_STOP_SAMPLE : OUT std_logic;
LOAD_KEY_SW : OUT std_logic;
LOAD_KEY_INLK : OUT std_logic;
SET_IC_ALLOWED : OUT std_logic;
INH_ROSAR_SET : OUT std_logic;
STOP_REQ : OUT std_logic;
ROS_SCAN : OUT std_logic;
ROS_CTRL_PROC_SW : OUT std_logic;
FT_4_LD_IND : OUT std_logic;
LOAD_REQ_LCH : OUT std_logic;
LOAD_IND : OUT std_logic;
RST_SEL_CHNL_DIAG_LCHS : OUT std_logic;
RST_LOAD : OUT std_logic;
CLOCK_START_LCH : OUT std_logic;
PWR_OFF_SW : OUT std_logic;
N2ND_ERROR_STOP : OUT std_logic;
SEL_CHNL_CPU_CLOCK_STOP : OUT std_logic;
CLOCK_START : OUT std_logic;
EARLY_ROAR_STOP : OUT std_logic;
HARD_STOP_LCH : OUT std_logic;
-- CLOCK_RST : OUT std_logic;
-- CLOCK_STOP : OUT std_logic;
DEBUG : OUT std_logic;
-- Clocks
T2,T3,T4 : IN std_logic;
P1 : IN std_logic;
clk : IN std_logic
);
END ClockStartStop;
ARCHITECTURE slt OF ClockStartStop IS
signal STT_RST_INLK : std_logic := '1';
signal CLK_STT_CTRL : std_logic := '0';
signal SET_IC_START : std_logic;
signal SET_IC_INLK : std_logic := '1';
signal PROCESS_STOP : std_logic := '0';
signal PROC_STOP_LOOP_ACTIVE : std_logic;
signal LOAD_KEY : std_logic := '0';
signal CF100T4 : std_logic;
signal CF_STOP : std_logic := '0';
signal INSTRUCTION_STEP_SW : std_logic;
signal SINGLE_CYCLE_SW : std_logic;
signal HS_MACH_CHK, HS_ALU_CHK, HS_DIAG, HS_MATCH, HS_INSTR : std_logic;
signal LOAD_REQ : std_logic;
signal PWR_OFF : std_logic := '0';
signal sSTART_SW_RST : std_logic := '0';
signal sE_CY_STOP_SAMPLE : std_logic := '0';
signal sLOAD_KEY_SW : std_logic;
signal sLOAD_KEY_INLK : std_logic := '1';
signal sSET_IC_ALLOWED : std_logic := '0';
signal sROS_SCAN : std_logic;
signal sLOAD_IND : std_logic := '0';
signal sRST_SEL_CHNL_DIAG_LCHS : std_logic;
signal sRST_LOAD : std_logic;
signal sCLOCK_START_LCH : std_logic := '0';
signal sPWR_OFF_SW : std_logic;
signal sN2ND_ERROR_STOP : std_logic := '0';
signal sSEL_CHNL_CPU_CLOCK_STOP : std_logic;
signal sCLOCK_START : std_logic;
signal sEARLY_ROAR_STOP : std_logic;
signal sHARD_STOP_LCH : std_logic := '0';
signal sCLOCK_RST : std_logic;
signal sCLOCK_STOP : std_logic;
signal HS_DIAG_DEGLITCHED : std_logic;
-- The following signals are required to allow the FL components to instantiate
signal CSC_LCH_Set,SSR_LCH_Set,SSR_LCH_Reset,ECS_LCH_Set,ECS_LCH_Reset,LKI_LCH_Set,
LK_LCH_Set,LK_LCH_Reset,SI_LCH_Set,SI_LCH_Reset,SIA_LCH_Set,SIA_LCH_Reset,
PS_LCH_Set,PS_LCH_Reset,CFS_LCH_Reset,CS_LCH_Set,CS_LCH_Reset,N2E_LCH_Set,N2E_LCH_Reset,
PO_LCH_Set,HS_LCH_Set : std_logic;
BEGIN
-- Fig 5-03C
-- STT RST INLK
SRI_LCH: entity work.FLL port map(R=>sSTART_SW_RST,S=>SW_START,Q=>STT_RST_INLK); -- AC1G7 - Note inputs reversed to make inverted output
-- STT RST
SSR_LCH_Set <= ALLOW_MAN_OPER and STT_RST_INLK and not SW_START;
SSR_LCH_Reset <= T2 or MACH_RST_SW;
SSR_LCH: entity work.FLL port map(S=>SSR_LCH_Set,R=>SSR_LCH_Reset,Q=>sSTART_SW_RST); -- AC1G7
START_SW_RST <= sSTART_SW_RST;
-- CLK STT CTRL
CSC_LCH_Set <= sCLOCK_RST or sE_CY_STOP_SAMPLE;
CSC_LCH: entity work.FLL port map(S=>CSC_LCH_Set,R=>sSTART_SW_RST,Q=>CLK_STT_CTRL); -- AC1F5
-- E CY STOP SAMPLE
ECS_LCH_Set <= SET_IC_START or (FT3_MPX_SHARE_REQ and M_CONV_OSC and PROC_STOP_LOOP_ACTIVE) or
(M_CONV_OSC and PROC_STOP_LOOP_ACTIVE and SEL_ROS_REQ) or
(not SW_START and M_CONV_OSC and not CLK_STT_CTRL); -- "not CLK_STT_CTRL" ?? is CLK_STT_CTRL meant to be inverted?
ECS_LCH_Reset <= MACH_RST_SW or T4;
ECS_LCH: entity work.FLL port map(S=>ECS_LCH_Set, R=>ECS_LCH_Reset, Q=>sE_CY_STOP_SAMPLE); -- AC1F7
E_CY_STOP_SAMPLE <= sE_CY_STOP_SAMPLE;
-- LOAD KEY INLK
LKI_LCH_Set <= (not SW_LOAD and MACH_RST_3) or LOAD_KEY;
LKI_LCH: entity work.FLL port map(R=>LKI_LCH_Set, S=>SW_LOAD, Q=>sLOAD_KEY_INLK); -- AC1F7 - Note inputs reversed to make inverted output
LOAD_KEY_INLK <= sLOAD_KEY_INLK;
-- LOAD KEY
LK_LCH_Set <= not sLOAD_KEY_SW and sLOAD_KEY_INLK;
LK_LCH_Reset <= T4 or sCLOCK_RST;
LK_LCH: entity work.FLL port map(S=>LK_LCH_Set, R=>LK_LCH_Reset, Q=>LOAD_KEY); -- AC1F7
sLOAD_KEY_SW <= SW_LOAD;
LOAD_KEY_SW <= sLOAD_KEY_SW;
-- SET IC INLK
SI_LCH_Set <= (CLOCK_ON and SW_SET_IC) or MACH_RST_3 or sSET_IC_ALLOWED; -- MACH_RST_3 inverted??
SI_LCH_Reset <= not SW_SET_IC; -- FMD is missing invert on switch output??
SI_LCH: entity work.FLL port map(S=>SI_LCH_Set, R=>SI_LCH_Reset, Q=>SET_IC_INLK); -- AC1G7
-- SET IC
SIA_LCH_Set <= ALLOW_MAN_OPER and not SET_IC_INLK and SW_SET_IC;
SIA_LCH_Reset <= T2 or MACH_RST_SW;
SIA_LCH: entity work.FLL port map(S=>SIA_LCH_Set, R=>SIA_LCH_Reset, Q=>sSET_IC_ALLOWED); -- AC1G7
SET_IC_ALLOWED <= sSET_IC_ALLOWED;
SET_IC_START <= not FORCE_IJ_REQ_LCH and M_CONV_OSC and sSET_IC_ALLOWED; -- AC1D6
-- PROCESS STOP
PS_LCH_Set <= sSET_IC_ALLOWED or SW_STOP or (SAR_DLYD_STOP_SW and MATCH) or (INSTRUCTION_STEP_SW and T4);
PS_LCH_Reset <= sSTART_SW_RST or '0'; -- ?? What is second reset input?
PS_LCH: entity work.FLL port map(S=>PS_LCH_Set, R=>PS_LCH_Reset, Q=>PROCESS_STOP); -- AC1E5
DEBUG <= PROCESS_STOP; -- ?? DEBUG ??
-- PROC_STOP_LOOP_ACTIVE <= (not (USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed??
PROC_STOP_LOOP_ACTIVE <= ((USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed?? and inverter on AA2G5 removed??
INH_ROSAR_SET <= PROC_STOP_LOOP_ACTIVE and not ANY_PRIORITY_PULSE; -- AC1D5
STOP_REQ <= PROCESS_STOP and not S_REG_1_DLYD and not INTERRUPT and END_OF_E_CY_LCH; -- AC1H7
-- CF STOP
CF100T4 <= SALS.SALS_CF(0) and not SALS.SALS_CF(1) and not SALS.SALS_CF(2) and T4; -- AA2G5
CFS_LCH_Reset <= (not CF100T4 and T4) or (not FORCE_IJ_REQ and not sROS_SCAN and not SW_PROC) or MACH_START_RST; -- AC1G5 AC1K6 AC1M5 AC1F2 ?? SW_INH_CF_STOP instead of SW_PROC ??
CFS_LCH: entity work.FLL port map(S=>CF100T4, R=>CFS_LCH_Reset, Q=>CF_STOP); -- AC1D5
sROS_SCAN <= SW_SCAN;
ROS_SCAN <= sROS_SCAN;
ROS_CTRL_PROC_SW <= SW_PROC;
SINGLE_CYCLE_SW <= SW_SINGLE_CYCLE;
INSTRUCTION_STEP_SW <= SW_INSTRUCTION_STEP;
-- LOAD REQ
sRST_LOAD <= GT_CK_DECODE and SALS.SALS_CK(0) and SALS.SALS_CK(1) and not SALS.SALS_CK(2) and SALS.SALS_CK(3); -- AB3F7
RST_LOAD <= sRST_LOAD;
sRST_SEL_CHNL_DIAG_LCHS <= MACH_RST_3 or sRST_LOAD; -- AC1F5,AC1H6
LOAD_REQ_FL: entity work.FLL port map(LOAD_KEY, sRST_SEL_CHNL_DIAG_LCHS, sLOAD_IND); -- AC1E5
RST_SEL_CHNL_DIAG_LCHS <= sRST_SEL_CHNL_DIAG_LCHS;
LOAD_IND <= sLOAD_IND;
LOAD_REQ <= sLOAD_IND;
LOAD_REQ_LCH <= sLOAD_IND; -- AC1F2
FT_4_LD_IND <= sLOAD_IND;
-- CLOCK START
CS_LCH_Set <= (LOAD_KEY and P_CONV_OSC) or (P_CONV_OSC and sE_CY_STOP_SAMPLE and not MAN_OPERATION);
CS_LCH_Reset <= sCLOCK_RST or sCLOCK_STOP;
CS_LCH: entity work.FLL port map(S=>CS_LCH_Set, R=>CS_LCH_Reset, Q=>sCLOCK_START_LCH); -- AC1K6
CLOCK_START_LCH <= sCLOCK_START_LCH;
sSEL_CHNL_CPU_CLOCK_STOP <= not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and T4) and
not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and SEL_T4) and
not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and not SEL_SHARE_HOLD) and
not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and SEL_CONV_OSC and SEL_BASIC_CLOCK_OFF); -- AD1D2,AD1C4
SEL_CHNL_CPU_CLOCK_STOP <= sSEL_CHNL_CPU_CLOCK_STOP;
sCLOCK_START <= (not sSEL_CHNL_CPU_CLOCK_STOP and sCLOCK_START_LCH and not PWR_OFF) and ((GT_J_REG_TO_A_BUS or not CF_STOP) and sCLOCK_START_LCH); -- AC1E4,AC1G6 ?? CLOCK_START_LCH twice?
CLOCK_START <= sCLOCK_START;
-- 2ND ERR STP
N2E_LCH_Set <= MACH_CHK_PULSE and P1;
N2E_LCH_Reset <= MACH_CHK_RST or HZ_DEST_RST;
N2E_LCH: entity work.FLL port map(S=>N2E_LCH_Set, R=>N2E_LCH_Reset, Q=>sN2ND_ERROR_STOP); -- AB3F4
N2ND_ERROR_STOP <= sN2ND_ERROR_STOP;
--PWR OFF
sPWR_OFF_SW <= SW_PWR_OFF;
PWR_OFF_SW <= sPWR_OFF_SW;
PO_LCH_Set <= sPWR_OFF_SW and T3 and not ALLOW_WRITE;
PO_LCH: entity work.FLL port map(S=>PO_LCH_Set, R=>MACH_START_RST, Q=>PWR_OFF); -- AC1F4
-- HARD STOP
HS_MACH_CHK <= (sN2ND_ERROR_STOP and T4 and FIRST_MACH_CHK) or (CHK_OR_DIAG_STOP_SW and ANY_MACH_CHK); -- AB3F4
sEARLY_ROAR_STOP <= MATCH_LCH and EARLY_ROAR_STOP_SW; -- AC1K5
EARLY_ROAR_STOP <= sEARLY_ROAR_STOP;
HS_ALU_CHK <= CHK_OR_DIAG_STOP_SW and ALU_CHK and T4; -- AB3H3
-- Z0_DELAY: entity AR port map(Z_BUS_0,clk,Z_BUS_0_DLYD); -- Delay to ensure Z0 signal is there at the end of T4
-- T4_DELAY: entity AR port map(T4,clk,T4_DLYD); -- Delay to ensure Z0 signal is there at the end of T4
HS_DIAG <= T4 and DIAGNOSTIC_SW and CS_DECODE_X001 and BASIC_CS0 and SUPPR_MACH_CHK_TRAP and not Z_BUS_0; -- AC1J6
-- DEGLITCH: entity DEGLITCH2 port map(HS_DIAG,clk,HS_DIAG_DEGLITCHED);
HS_MATCH <= (SAR_STOP_SW and MATCH_LCH and T4) or (ROAR_STOP_SW and T4 and MATCH_LCH) or (T4 and SINGLE_CYCLE_SW);
HS_INSTR <= T4 and INSTRUCTION_STEP_SW and ANY_PRIORITY_PULSE_PWR and sROS_SCAN; -- AB3H2
HS_LCH_Set <= HS_MACH_CHK or sEARLY_ROAR_STOP or HS_ALU_CHK or HS_DIAG or HS_MATCH or HS_INSTR;
HS_LCH: entity work.FLL port map(S=>HS_LCH_Set, R=>MACH_START_RST, Q=>sHARD_STOP_LCH); -- AB3H6
HARD_STOP_LCH <= sHARD_STOP_LCH;
sCLOCK_RST <= MACH_RST_3 or (sHARD_STOP_LCH and M_CONV_OSC_2) or (M_CONV_OSC_2 and not GT_J_REG_TO_A_BUS and CF_STOP); -- AC1F6,AC1G5
-- CLOCK_RST <= sCLOCK_RST;
sCLOCK_STOP <= (PROC_STOP_LOOP_ACTIVE and not SEL_ROS_REQ and not MPX_SHARE_REQ and T2) or (not LOAD_REQ and sLOAD_KEY_SW) or SYSTEM_RESET_SW; -- AC1H7,AC1J6,AC1J7
-- CLOCK_STOP <= sCLOCK_STOP;
END slt;
|
--input 48.828125 kHz 8 bit audio
--interpolated to 2048 * 8 * 48.828125 = 800 MHz sampling rate 19-bits
--upconverted to lo
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmitter is
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
frequency_stb : in std_logic;
frequency_ack : out std_logic;
control : in std_logic_vector(31 downto 0);
control_stb : in std_logic;
control_ack : out std_logic;
amplitude : in std_logic_vector(31 downto 0);
amplitude_stb : in std_logic;
amplitude_ack : out std_logic;
rf : out std_logic;
tx_rx : out std_logic;
tx_pa : out std_logic
);
end entity transmitter;
architecture rtl of transmitter is
component interpolate is
generic(
interpolation_factor : integer;
output_width : integer;
width : integer
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width - 1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output_0 : out std_logic_vector(output_width - 1 downto 0);
output_1 : out std_logic_vector(output_width - 1 downto 0);
output_2 : out std_logic_vector(output_width - 1 downto 0);
output_3 : out std_logic_vector(output_width - 1 downto 0);
output_4 : out std_logic_vector(output_width - 1 downto 0);
output_5 : out std_logic_vector(output_width - 1 downto 0);
output_6 : out std_logic_vector(output_width - 1 downto 0);
output_7 : out std_logic_vector(output_width - 1 downto 0)
);
end component interpolate;
component nco is
generic(
width : integer
);
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
lo_i_0 : out std_logic_vector(width - 1 downto 0);
lo_i_1 : out std_logic_vector(width - 1 downto 0);
lo_i_2 : out std_logic_vector(width - 1 downto 0);
lo_i_3 : out std_logic_vector(width - 1 downto 0);
lo_i_4 : out std_logic_vector(width - 1 downto 0);
lo_i_5 : out std_logic_vector(width - 1 downto 0);
lo_i_6 : out std_logic_vector(width - 1 downto 0);
lo_i_7 : out std_logic_vector(width - 1 downto 0);
lo_q_0 : out std_logic_vector(width - 1 downto 0);
lo_q_1 : out std_logic_vector(width - 1 downto 0);
lo_q_2 : out std_logic_vector(width - 1 downto 0);
lo_q_3 : out std_logic_vector(width - 1 downto 0);
lo_q_4 : out std_logic_vector(width - 1 downto 0);
lo_q_5 : out std_logic_vector(width - 1 downto 0);
lo_q_6 : out std_logic_vector(width - 1 downto 0);
lo_q_7 : out std_logic_vector(width - 1 downto 0)
);
end component nco;
component dac_interface is
generic(
width : integer
);
port(
clk : in std_logic;
rst : in std_logic;
dithering : in std_logic;
input_0 : in std_logic_vector(width - 1 downto 0);
input_1 : in std_logic_vector(width - 1 downto 0);
input_2 : in std_logic_vector(width - 1 downto 0);
input_3 : in std_logic_vector(width - 1 downto 0);
input_4 : in std_logic_vector(width - 1 downto 0);
input_5 : in std_logic_vector(width - 1 downto 0);
input_6 : in std_logic_vector(width - 1 downto 0);
input_7 : in std_logic_vector(width - 1 downto 0);
output : out std_logic
);
end component dac_interface;
signal i_full_rate_0 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_1 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_2 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_3 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_4 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_5 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_6 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_7 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_0 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_1 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_2 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_3 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_4 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_5 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_6 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_7 : std_logic_vector(23 downto 0) := (others => '0');
signal lo_i_0 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_1 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_2 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_3 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_4 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_5 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_6 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_7 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_0 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_1 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_2 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_3 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_4 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_5 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_6 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_7 : std_logic_vector(9 downto 0) := (others => '0');
signal i_out_0 : signed(33 downto 0) := (others => '0');
signal i_out_1 : signed(33 downto 0) := (others => '0');
signal i_out_2 : signed(33 downto 0) := (others => '0');
signal i_out_3 : signed(33 downto 0) := (others => '0');
signal i_out_4 : signed(33 downto 0) := (others => '0');
signal i_out_5 : signed(33 downto 0) := (others => '0');
signal i_out_6 : signed(33 downto 0) := (others => '0');
signal i_out_7 : signed(33 downto 0) := (others => '0');
signal q_out_0 : signed(33 downto 0) := (others => '0');
signal q_out_1 : signed(33 downto 0) := (others => '0');
signal q_out_2 : signed(33 downto 0) := (others => '0');
signal q_out_3 : signed(33 downto 0) := (others => '0');
signal q_out_4 : signed(33 downto 0) := (others => '0');
signal q_out_5 : signed(33 downto 0) := (others => '0');
signal q_out_6 : signed(33 downto 0) := (others => '0');
signal q_out_7 : signed(33 downto 0) := (others => '0');
signal out_0 : std_logic_vector(31 downto 0) := (others => '0');
signal out_1 : std_logic_vector(31 downto 0) := (others => '0');
signal out_2 : std_logic_vector(31 downto 0) := (others => '0');
signal out_3 : std_logic_vector(31 downto 0) := (others => '0');
signal out_4 : std_logic_vector(31 downto 0) := (others => '0');
signal out_5 : std_logic_vector(31 downto 0) := (others => '0');
signal out_6 : std_logic_vector(31 downto 0) := (others => '0');
signal out_7 : std_logic_vector(31 downto 0) := (others => '0');
signal dithering : std_logic := '0';
signal frequency_reg : std_logic_vector(31 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
if control_stb = '1' then
dithering <= control(0);
tx_rx <= control(1);
tx_pa <= control(2);
end if;
if frequency_stb = '1' then
frequency_reg <= frequency;
end if;
end process;
control_ack <= '1';
frequency_ack <= '1';
nco_inst_1 : nco generic map(
width => 10
) port map (
clk => clk,
rst => rst,
frequency => frequency_reg,
lo_i_0 => lo_i_0,
lo_i_1 => lo_i_1,
lo_i_2 => lo_i_2,
lo_i_3 => lo_i_3,
lo_i_4 => lo_i_4,
lo_i_5 => lo_i_5,
lo_i_6 => lo_i_6,
lo_i_7 => lo_i_7,
lo_q_0 => lo_q_0,
lo_q_1 => lo_q_1,
lo_q_2 => lo_q_2,
lo_q_3 => lo_q_3,
lo_q_4 => lo_q_4,
lo_q_5 => lo_q_5,
lo_q_6 => lo_q_6,
lo_q_7 => lo_q_7
);
interpolate_inst_1 : interpolate generic map(
interpolation_factor => 8192,
output_width => 13 + 3 + 8,
width => 8
) port map (
clk => clk,
rst => rst,
input => amplitude(23 downto 16),
input_stb => amplitude_stb,
input_ack => amplitude_ack,
output_0 => i_full_rate_0,
output_1 => i_full_rate_1,
output_2 => i_full_rate_2,
output_3 => i_full_rate_3,
output_4 => i_full_rate_4,
output_5 => i_full_rate_5,
output_6 => i_full_rate_6,
output_7 => i_full_rate_7
);
interpolate_inst_2 : interpolate generic map(
interpolation_factor => 8192,
output_width => 13 + 3 + 8,
width => 8
) port map (
clk => clk,
rst => rst,
input => amplitude(7 downto 0),
input_stb => amplitude_stb,
input_ack => open,
output_0 => q_full_rate_0,
output_1 => q_full_rate_1,
output_2 => q_full_rate_2,
output_3 => q_full_rate_3,
output_4 => q_full_rate_4,
output_5 => q_full_rate_5,
output_6 => q_full_rate_6,
output_7 => q_full_rate_7
);
process
variable temp_0 : signed(34 downto 0);
variable temp_1 : signed(34 downto 0);
variable temp_2 : signed(34 downto 0);
variable temp_3 : signed(34 downto 0);
variable temp_4 : signed(34 downto 0);
variable temp_5 : signed(34 downto 0);
variable temp_6 : signed(34 downto 0);
variable temp_7 : signed(34 downto 0);
begin
wait until rising_edge(clk);
i_out_0 <= signed(i_full_rate_0) * signed(lo_i_0);
i_out_1 <= signed(i_full_rate_1) * signed(lo_i_1);
i_out_2 <= signed(i_full_rate_2) * signed(lo_i_2);
i_out_3 <= signed(i_full_rate_3) * signed(lo_i_3);
i_out_4 <= signed(i_full_rate_4) * signed(lo_i_4);
i_out_5 <= signed(i_full_rate_5) * signed(lo_i_5);
i_out_6 <= signed(i_full_rate_6) * signed(lo_i_6);
i_out_7 <= signed(i_full_rate_7) * signed(lo_i_7);
q_out_0 <= signed(q_full_rate_0) * signed(lo_q_0);
q_out_1 <= signed(q_full_rate_1) * signed(lo_q_1);
q_out_2 <= signed(q_full_rate_2) * signed(lo_q_2);
q_out_3 <= signed(q_full_rate_3) * signed(lo_q_3);
q_out_4 <= signed(q_full_rate_4) * signed(lo_q_4);
q_out_5 <= signed(q_full_rate_5) * signed(lo_q_5);
q_out_6 <= signed(q_full_rate_6) * signed(lo_q_6);
q_out_7 <= signed(q_full_rate_7) * signed(lo_q_7);
temp_0 := resize(i_out_0, 35) + q_out_0;
temp_1 := resize(i_out_1, 35) + q_out_1;
temp_2 := resize(i_out_2, 35) + q_out_2;
temp_3 := resize(i_out_3, 35) + q_out_3;
temp_4 := resize(i_out_4, 35) + q_out_4;
temp_5 := resize(i_out_5, 35) + q_out_5;
temp_6 := resize(i_out_6, 35) + q_out_6;
temp_7 := resize(i_out_7, 35) + q_out_7;
out_0 <= std_logic_vector(temp_0(32 downto 1));
out_1 <= std_logic_vector(temp_1(32 downto 1));
out_2 <= std_logic_vector(temp_2(32 downto 1));
out_3 <= std_logic_vector(temp_3(32 downto 1));
out_4 <= std_logic_vector(temp_4(32 downto 1));
out_5 <= std_logic_vector(temp_5(32 downto 1));
out_6 <= std_logic_vector(temp_6(32 downto 1));
out_7 <= std_logic_vector(temp_7(32 downto 1));
end process;
dac_interface_inst_1 : dac_interface generic map(
width => 32
) port map (
clk => clk,
rst => rst,
dithering => dithering,
input_0 => out_0,
input_1 => out_1,
input_2 => out_2,
input_3 => out_3,
input_4 => out_4,
input_5 => out_5,
input_6 => out_6,
input_7 => out_7,
output => rf
);
end rtl;
|
--input 48.828125 kHz 8 bit audio
--interpolated to 2048 * 8 * 48.828125 = 800 MHz sampling rate 19-bits
--upconverted to lo
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmitter is
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
frequency_stb : in std_logic;
frequency_ack : out std_logic;
control : in std_logic_vector(31 downto 0);
control_stb : in std_logic;
control_ack : out std_logic;
amplitude : in std_logic_vector(31 downto 0);
amplitude_stb : in std_logic;
amplitude_ack : out std_logic;
rf : out std_logic;
tx_rx : out std_logic;
tx_pa : out std_logic
);
end entity transmitter;
architecture rtl of transmitter is
component interpolate is
generic(
interpolation_factor : integer;
output_width : integer;
width : integer
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width - 1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output_0 : out std_logic_vector(output_width - 1 downto 0);
output_1 : out std_logic_vector(output_width - 1 downto 0);
output_2 : out std_logic_vector(output_width - 1 downto 0);
output_3 : out std_logic_vector(output_width - 1 downto 0);
output_4 : out std_logic_vector(output_width - 1 downto 0);
output_5 : out std_logic_vector(output_width - 1 downto 0);
output_6 : out std_logic_vector(output_width - 1 downto 0);
output_7 : out std_logic_vector(output_width - 1 downto 0)
);
end component interpolate;
component nco is
generic(
width : integer
);
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
lo_i_0 : out std_logic_vector(width - 1 downto 0);
lo_i_1 : out std_logic_vector(width - 1 downto 0);
lo_i_2 : out std_logic_vector(width - 1 downto 0);
lo_i_3 : out std_logic_vector(width - 1 downto 0);
lo_i_4 : out std_logic_vector(width - 1 downto 0);
lo_i_5 : out std_logic_vector(width - 1 downto 0);
lo_i_6 : out std_logic_vector(width - 1 downto 0);
lo_i_7 : out std_logic_vector(width - 1 downto 0);
lo_q_0 : out std_logic_vector(width - 1 downto 0);
lo_q_1 : out std_logic_vector(width - 1 downto 0);
lo_q_2 : out std_logic_vector(width - 1 downto 0);
lo_q_3 : out std_logic_vector(width - 1 downto 0);
lo_q_4 : out std_logic_vector(width - 1 downto 0);
lo_q_5 : out std_logic_vector(width - 1 downto 0);
lo_q_6 : out std_logic_vector(width - 1 downto 0);
lo_q_7 : out std_logic_vector(width - 1 downto 0)
);
end component nco;
component dac_interface is
generic(
width : integer
);
port(
clk : in std_logic;
rst : in std_logic;
dithering : in std_logic;
input_0 : in std_logic_vector(width - 1 downto 0);
input_1 : in std_logic_vector(width - 1 downto 0);
input_2 : in std_logic_vector(width - 1 downto 0);
input_3 : in std_logic_vector(width - 1 downto 0);
input_4 : in std_logic_vector(width - 1 downto 0);
input_5 : in std_logic_vector(width - 1 downto 0);
input_6 : in std_logic_vector(width - 1 downto 0);
input_7 : in std_logic_vector(width - 1 downto 0);
output : out std_logic
);
end component dac_interface;
signal i_full_rate_0 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_1 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_2 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_3 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_4 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_5 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_6 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_7 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_0 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_1 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_2 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_3 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_4 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_5 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_6 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_7 : std_logic_vector(23 downto 0) := (others => '0');
signal lo_i_0 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_1 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_2 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_3 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_4 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_5 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_6 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_7 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_0 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_1 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_2 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_3 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_4 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_5 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_6 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_7 : std_logic_vector(9 downto 0) := (others => '0');
signal i_out_0 : signed(33 downto 0) := (others => '0');
signal i_out_1 : signed(33 downto 0) := (others => '0');
signal i_out_2 : signed(33 downto 0) := (others => '0');
signal i_out_3 : signed(33 downto 0) := (others => '0');
signal i_out_4 : signed(33 downto 0) := (others => '0');
signal i_out_5 : signed(33 downto 0) := (others => '0');
signal i_out_6 : signed(33 downto 0) := (others => '0');
signal i_out_7 : signed(33 downto 0) := (others => '0');
signal q_out_0 : signed(33 downto 0) := (others => '0');
signal q_out_1 : signed(33 downto 0) := (others => '0');
signal q_out_2 : signed(33 downto 0) := (others => '0');
signal q_out_3 : signed(33 downto 0) := (others => '0');
signal q_out_4 : signed(33 downto 0) := (others => '0');
signal q_out_5 : signed(33 downto 0) := (others => '0');
signal q_out_6 : signed(33 downto 0) := (others => '0');
signal q_out_7 : signed(33 downto 0) := (others => '0');
signal out_0 : std_logic_vector(31 downto 0) := (others => '0');
signal out_1 : std_logic_vector(31 downto 0) := (others => '0');
signal out_2 : std_logic_vector(31 downto 0) := (others => '0');
signal out_3 : std_logic_vector(31 downto 0) := (others => '0');
signal out_4 : std_logic_vector(31 downto 0) := (others => '0');
signal out_5 : std_logic_vector(31 downto 0) := (others => '0');
signal out_6 : std_logic_vector(31 downto 0) := (others => '0');
signal out_7 : std_logic_vector(31 downto 0) := (others => '0');
signal dithering : std_logic := '0';
signal frequency_reg : std_logic_vector(31 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
if control_stb = '1' then
dithering <= control(0);
tx_rx <= control(1);
tx_pa <= control(2);
end if;
if frequency_stb = '1' then
frequency_reg <= frequency;
end if;
end process;
control_ack <= '1';
frequency_ack <= '1';
nco_inst_1 : nco generic map(
width => 10
) port map (
clk => clk,
rst => rst,
frequency => frequency_reg,
lo_i_0 => lo_i_0,
lo_i_1 => lo_i_1,
lo_i_2 => lo_i_2,
lo_i_3 => lo_i_3,
lo_i_4 => lo_i_4,
lo_i_5 => lo_i_5,
lo_i_6 => lo_i_6,
lo_i_7 => lo_i_7,
lo_q_0 => lo_q_0,
lo_q_1 => lo_q_1,
lo_q_2 => lo_q_2,
lo_q_3 => lo_q_3,
lo_q_4 => lo_q_4,
lo_q_5 => lo_q_5,
lo_q_6 => lo_q_6,
lo_q_7 => lo_q_7
);
interpolate_inst_1 : interpolate generic map(
interpolation_factor => 8192,
output_width => 13 + 3 + 8,
width => 8
) port map (
clk => clk,
rst => rst,
input => amplitude(23 downto 16),
input_stb => amplitude_stb,
input_ack => amplitude_ack,
output_0 => i_full_rate_0,
output_1 => i_full_rate_1,
output_2 => i_full_rate_2,
output_3 => i_full_rate_3,
output_4 => i_full_rate_4,
output_5 => i_full_rate_5,
output_6 => i_full_rate_6,
output_7 => i_full_rate_7
);
interpolate_inst_2 : interpolate generic map(
interpolation_factor => 8192,
output_width => 13 + 3 + 8,
width => 8
) port map (
clk => clk,
rst => rst,
input => amplitude(7 downto 0),
input_stb => amplitude_stb,
input_ack => open,
output_0 => q_full_rate_0,
output_1 => q_full_rate_1,
output_2 => q_full_rate_2,
output_3 => q_full_rate_3,
output_4 => q_full_rate_4,
output_5 => q_full_rate_5,
output_6 => q_full_rate_6,
output_7 => q_full_rate_7
);
process
variable temp_0 : signed(34 downto 0);
variable temp_1 : signed(34 downto 0);
variable temp_2 : signed(34 downto 0);
variable temp_3 : signed(34 downto 0);
variable temp_4 : signed(34 downto 0);
variable temp_5 : signed(34 downto 0);
variable temp_6 : signed(34 downto 0);
variable temp_7 : signed(34 downto 0);
begin
wait until rising_edge(clk);
i_out_0 <= signed(i_full_rate_0) * signed(lo_i_0);
i_out_1 <= signed(i_full_rate_1) * signed(lo_i_1);
i_out_2 <= signed(i_full_rate_2) * signed(lo_i_2);
i_out_3 <= signed(i_full_rate_3) * signed(lo_i_3);
i_out_4 <= signed(i_full_rate_4) * signed(lo_i_4);
i_out_5 <= signed(i_full_rate_5) * signed(lo_i_5);
i_out_6 <= signed(i_full_rate_6) * signed(lo_i_6);
i_out_7 <= signed(i_full_rate_7) * signed(lo_i_7);
q_out_0 <= signed(q_full_rate_0) * signed(lo_q_0);
q_out_1 <= signed(q_full_rate_1) * signed(lo_q_1);
q_out_2 <= signed(q_full_rate_2) * signed(lo_q_2);
q_out_3 <= signed(q_full_rate_3) * signed(lo_q_3);
q_out_4 <= signed(q_full_rate_4) * signed(lo_q_4);
q_out_5 <= signed(q_full_rate_5) * signed(lo_q_5);
q_out_6 <= signed(q_full_rate_6) * signed(lo_q_6);
q_out_7 <= signed(q_full_rate_7) * signed(lo_q_7);
temp_0 := resize(i_out_0, 35) + q_out_0;
temp_1 := resize(i_out_1, 35) + q_out_1;
temp_2 := resize(i_out_2, 35) + q_out_2;
temp_3 := resize(i_out_3, 35) + q_out_3;
temp_4 := resize(i_out_4, 35) + q_out_4;
temp_5 := resize(i_out_5, 35) + q_out_5;
temp_6 := resize(i_out_6, 35) + q_out_6;
temp_7 := resize(i_out_7, 35) + q_out_7;
out_0 <= std_logic_vector(temp_0(32 downto 1));
out_1 <= std_logic_vector(temp_1(32 downto 1));
out_2 <= std_logic_vector(temp_2(32 downto 1));
out_3 <= std_logic_vector(temp_3(32 downto 1));
out_4 <= std_logic_vector(temp_4(32 downto 1));
out_5 <= std_logic_vector(temp_5(32 downto 1));
out_6 <= std_logic_vector(temp_6(32 downto 1));
out_7 <= std_logic_vector(temp_7(32 downto 1));
end process;
dac_interface_inst_1 : dac_interface generic map(
width => 32
) port map (
clk => clk,
rst => rst,
dithering => dithering,
input_0 => out_0,
input_1 => out_1,
input_2 => out_2,
input_3 => out_3,
input_4 => out_4,
input_5 => out_5,
input_6 => out_6,
input_7 => out_7,
output => rf
);
end rtl;
|
--input 48.828125 kHz 8 bit audio
--interpolated to 2048 * 8 * 48.828125 = 800 MHz sampling rate 19-bits
--upconverted to lo
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmitter is
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
frequency_stb : in std_logic;
frequency_ack : out std_logic;
control : in std_logic_vector(31 downto 0);
control_stb : in std_logic;
control_ack : out std_logic;
amplitude : in std_logic_vector(31 downto 0);
amplitude_stb : in std_logic;
amplitude_ack : out std_logic;
rf : out std_logic;
tx_rx : out std_logic;
tx_pa : out std_logic
);
end entity transmitter;
architecture rtl of transmitter is
component interpolate is
generic(
interpolation_factor : integer;
output_width : integer;
width : integer
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width - 1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output_0 : out std_logic_vector(output_width - 1 downto 0);
output_1 : out std_logic_vector(output_width - 1 downto 0);
output_2 : out std_logic_vector(output_width - 1 downto 0);
output_3 : out std_logic_vector(output_width - 1 downto 0);
output_4 : out std_logic_vector(output_width - 1 downto 0);
output_5 : out std_logic_vector(output_width - 1 downto 0);
output_6 : out std_logic_vector(output_width - 1 downto 0);
output_7 : out std_logic_vector(output_width - 1 downto 0)
);
end component interpolate;
component nco is
generic(
width : integer
);
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
lo_i_0 : out std_logic_vector(width - 1 downto 0);
lo_i_1 : out std_logic_vector(width - 1 downto 0);
lo_i_2 : out std_logic_vector(width - 1 downto 0);
lo_i_3 : out std_logic_vector(width - 1 downto 0);
lo_i_4 : out std_logic_vector(width - 1 downto 0);
lo_i_5 : out std_logic_vector(width - 1 downto 0);
lo_i_6 : out std_logic_vector(width - 1 downto 0);
lo_i_7 : out std_logic_vector(width - 1 downto 0);
lo_q_0 : out std_logic_vector(width - 1 downto 0);
lo_q_1 : out std_logic_vector(width - 1 downto 0);
lo_q_2 : out std_logic_vector(width - 1 downto 0);
lo_q_3 : out std_logic_vector(width - 1 downto 0);
lo_q_4 : out std_logic_vector(width - 1 downto 0);
lo_q_5 : out std_logic_vector(width - 1 downto 0);
lo_q_6 : out std_logic_vector(width - 1 downto 0);
lo_q_7 : out std_logic_vector(width - 1 downto 0)
);
end component nco;
component dac_interface is
generic(
width : integer
);
port(
clk : in std_logic;
rst : in std_logic;
dithering : in std_logic;
input_0 : in std_logic_vector(width - 1 downto 0);
input_1 : in std_logic_vector(width - 1 downto 0);
input_2 : in std_logic_vector(width - 1 downto 0);
input_3 : in std_logic_vector(width - 1 downto 0);
input_4 : in std_logic_vector(width - 1 downto 0);
input_5 : in std_logic_vector(width - 1 downto 0);
input_6 : in std_logic_vector(width - 1 downto 0);
input_7 : in std_logic_vector(width - 1 downto 0);
output : out std_logic
);
end component dac_interface;
signal i_full_rate_0 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_1 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_2 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_3 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_4 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_5 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_6 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_7 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_0 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_1 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_2 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_3 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_4 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_5 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_6 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_7 : std_logic_vector(23 downto 0) := (others => '0');
signal lo_i_0 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_1 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_2 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_3 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_4 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_5 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_6 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_7 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_0 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_1 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_2 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_3 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_4 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_5 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_6 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_7 : std_logic_vector(9 downto 0) := (others => '0');
signal i_out_0 : signed(33 downto 0) := (others => '0');
signal i_out_1 : signed(33 downto 0) := (others => '0');
signal i_out_2 : signed(33 downto 0) := (others => '0');
signal i_out_3 : signed(33 downto 0) := (others => '0');
signal i_out_4 : signed(33 downto 0) := (others => '0');
signal i_out_5 : signed(33 downto 0) := (others => '0');
signal i_out_6 : signed(33 downto 0) := (others => '0');
signal i_out_7 : signed(33 downto 0) := (others => '0');
signal q_out_0 : signed(33 downto 0) := (others => '0');
signal q_out_1 : signed(33 downto 0) := (others => '0');
signal q_out_2 : signed(33 downto 0) := (others => '0');
signal q_out_3 : signed(33 downto 0) := (others => '0');
signal q_out_4 : signed(33 downto 0) := (others => '0');
signal q_out_5 : signed(33 downto 0) := (others => '0');
signal q_out_6 : signed(33 downto 0) := (others => '0');
signal q_out_7 : signed(33 downto 0) := (others => '0');
signal out_0 : std_logic_vector(31 downto 0) := (others => '0');
signal out_1 : std_logic_vector(31 downto 0) := (others => '0');
signal out_2 : std_logic_vector(31 downto 0) := (others => '0');
signal out_3 : std_logic_vector(31 downto 0) := (others => '0');
signal out_4 : std_logic_vector(31 downto 0) := (others => '0');
signal out_5 : std_logic_vector(31 downto 0) := (others => '0');
signal out_6 : std_logic_vector(31 downto 0) := (others => '0');
signal out_7 : std_logic_vector(31 downto 0) := (others => '0');
signal dithering : std_logic := '0';
signal frequency_reg : std_logic_vector(31 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
if control_stb = '1' then
dithering <= control(0);
tx_rx <= control(1);
tx_pa <= control(2);
end if;
if frequency_stb = '1' then
frequency_reg <= frequency;
end if;
end process;
control_ack <= '1';
frequency_ack <= '1';
nco_inst_1 : nco generic map(
width => 10
) port map (
clk => clk,
rst => rst,
frequency => frequency_reg,
lo_i_0 => lo_i_0,
lo_i_1 => lo_i_1,
lo_i_2 => lo_i_2,
lo_i_3 => lo_i_3,
lo_i_4 => lo_i_4,
lo_i_5 => lo_i_5,
lo_i_6 => lo_i_6,
lo_i_7 => lo_i_7,
lo_q_0 => lo_q_0,
lo_q_1 => lo_q_1,
lo_q_2 => lo_q_2,
lo_q_3 => lo_q_3,
lo_q_4 => lo_q_4,
lo_q_5 => lo_q_5,
lo_q_6 => lo_q_6,
lo_q_7 => lo_q_7
);
interpolate_inst_1 : interpolate generic map(
interpolation_factor => 8192,
output_width => 13 + 3 + 8,
width => 8
) port map (
clk => clk,
rst => rst,
input => amplitude(23 downto 16),
input_stb => amplitude_stb,
input_ack => amplitude_ack,
output_0 => i_full_rate_0,
output_1 => i_full_rate_1,
output_2 => i_full_rate_2,
output_3 => i_full_rate_3,
output_4 => i_full_rate_4,
output_5 => i_full_rate_5,
output_6 => i_full_rate_6,
output_7 => i_full_rate_7
);
interpolate_inst_2 : interpolate generic map(
interpolation_factor => 8192,
output_width => 13 + 3 + 8,
width => 8
) port map (
clk => clk,
rst => rst,
input => amplitude(7 downto 0),
input_stb => amplitude_stb,
input_ack => open,
output_0 => q_full_rate_0,
output_1 => q_full_rate_1,
output_2 => q_full_rate_2,
output_3 => q_full_rate_3,
output_4 => q_full_rate_4,
output_5 => q_full_rate_5,
output_6 => q_full_rate_6,
output_7 => q_full_rate_7
);
process
variable temp_0 : signed(34 downto 0);
variable temp_1 : signed(34 downto 0);
variable temp_2 : signed(34 downto 0);
variable temp_3 : signed(34 downto 0);
variable temp_4 : signed(34 downto 0);
variable temp_5 : signed(34 downto 0);
variable temp_6 : signed(34 downto 0);
variable temp_7 : signed(34 downto 0);
begin
wait until rising_edge(clk);
i_out_0 <= signed(i_full_rate_0) * signed(lo_i_0);
i_out_1 <= signed(i_full_rate_1) * signed(lo_i_1);
i_out_2 <= signed(i_full_rate_2) * signed(lo_i_2);
i_out_3 <= signed(i_full_rate_3) * signed(lo_i_3);
i_out_4 <= signed(i_full_rate_4) * signed(lo_i_4);
i_out_5 <= signed(i_full_rate_5) * signed(lo_i_5);
i_out_6 <= signed(i_full_rate_6) * signed(lo_i_6);
i_out_7 <= signed(i_full_rate_7) * signed(lo_i_7);
q_out_0 <= signed(q_full_rate_0) * signed(lo_q_0);
q_out_1 <= signed(q_full_rate_1) * signed(lo_q_1);
q_out_2 <= signed(q_full_rate_2) * signed(lo_q_2);
q_out_3 <= signed(q_full_rate_3) * signed(lo_q_3);
q_out_4 <= signed(q_full_rate_4) * signed(lo_q_4);
q_out_5 <= signed(q_full_rate_5) * signed(lo_q_5);
q_out_6 <= signed(q_full_rate_6) * signed(lo_q_6);
q_out_7 <= signed(q_full_rate_7) * signed(lo_q_7);
temp_0 := resize(i_out_0, 35) + q_out_0;
temp_1 := resize(i_out_1, 35) + q_out_1;
temp_2 := resize(i_out_2, 35) + q_out_2;
temp_3 := resize(i_out_3, 35) + q_out_3;
temp_4 := resize(i_out_4, 35) + q_out_4;
temp_5 := resize(i_out_5, 35) + q_out_5;
temp_6 := resize(i_out_6, 35) + q_out_6;
temp_7 := resize(i_out_7, 35) + q_out_7;
out_0 <= std_logic_vector(temp_0(32 downto 1));
out_1 <= std_logic_vector(temp_1(32 downto 1));
out_2 <= std_logic_vector(temp_2(32 downto 1));
out_3 <= std_logic_vector(temp_3(32 downto 1));
out_4 <= std_logic_vector(temp_4(32 downto 1));
out_5 <= std_logic_vector(temp_5(32 downto 1));
out_6 <= std_logic_vector(temp_6(32 downto 1));
out_7 <= std_logic_vector(temp_7(32 downto 1));
end process;
dac_interface_inst_1 : dac_interface generic map(
width => 32
) port map (
clk => clk,
rst => rst,
dithering => dithering,
input_0 => out_0,
input_1 => out_1,
input_2 => out_2,
input_3 => out_3,
input_4 => out_4,
input_5 => out_5,
input_6 => out_6,
input_7 => out_7,
output => rf
);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity var05 is
port (sel : std_logic;
a, b : std_logic_vector (1 downto 0);
res : out std_logic_vector (1 downto 0));
end var05;
architecture behav of var05 is
begin
process (all)
variable idx : integer;
begin
res <= a;
if sel = '1' then
idx := 1;
res <= b;
end if;
end process;
end behav;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 8;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : partial_test_tb
--
-- Description : Parts of the testbench used for testing the Bitvis Utility Library
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use std.textio.all;
library work;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
use work.methods_pkg.all;
use work.bfm_common_pkg.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all; -- Used for to_string(real)
use ieee_proposed.std_logic_1164_additions.all; -- Used for to_string(std_logic)
entity partial_test_tb is
end entity;
architecture func of partial_test_tb is
signal sl : std_logic := '0';
signal clk100M : std_logic;
signal clk100M_ena : boolean := true;
signal clk200M : std_logic;
signal clk200M_ena : boolean := true;
signal clk50M : std_logic;
constant C_CLK100M_PERIOD : time := 10 ns;
begin
------------------------------------------------
-- Process: clock generator
------------------------------------------------
-- Overloaded version with enable signal as argument
clock_generator(clk100M, clk100M_ena, C_CLK100M_PERIOD, "Clk100M");
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
constant C_SCOPE : string := "TB seq";
-- Log overloads for simplification
procedure log(
msg : string) is
begin
log(ID_SEQUENCER, msg, C_SCOPE);
end;
begin
set_alert_file_name("alertlog.txt");
set_log_file_name("testlog.txt");
set_alert_stop_limit(WARNING, 0);
set_alert_stop_limit(ERROR, 0); -- 0 = Never stop
wait for 1 ns;
-- ####################### BLOCK 1 - Causes "internal error: delayed" ##########################
-- FROM_NOW, FROM_NOW
await_stable(sl, 50 ns, FROM_NOW, 100 ns, FROM_NOW, ERROR, "sl: Stable FROM_NOW, FROM_NOW, OK after 50 ns", C_SCOPE);
sl <= transport not sl after 30 ns;
await_stable(sl, 50 ns, FROM_NOW, 100 ns, FROM_NOW, ERROR, "sl: Stable FROM_NOW, FROM_NOW, OK after 80 ns", C_SCOPE);
sl <= transport not sl after 30 ns;
await_stable(sl, 50 ns, FROM_NOW, 60 ns, FROM_NOW, ERROR, "sl: Not stable FROM_NOW, FROM_NOW, Fail after 30 ns", C_SCOPE);
increment_expected_alerts(ERROR, 1);
await_stable(sl, 50 ns, FROM_NOW, 1 ns, FROM_NOW, ERROR, "sl: Timeout before stable_req, FROM_NOW, FROM_NOW, Fail immediately", C_SCOPE);
increment_expected_alerts(ERROR, 1);
await_stable(sl, 0 ns, FROM_NOW, 0 ns, FROM_NOW, ERROR, "sl: stable for 0 ns, FROM_NOW, FROM_NOW, OK after 0 ns", C_SCOPE);
-- FROM_LAST_EVENT, FROM_NOW
sl <= not sl;
log("NOTE: ERROR HAPPENS AFTER HERE");
wait for 10 ns;
log("NOTE: ERROR HAPPENS BEFORE HERE");
-- ####################### END OF BLOCK 1 ##########################
-- ####################### BLOCK 2 - Code works if this is removed ##########################
-- Pulse a certain number of clock periods
clk100M_ena <= true; -- Clock must be running
sl <= '0';
wait for 0 ns; -- Wait for signal to update
gen_pulse(sl, clk100M, 10, "Test pulse 10 clk periods");
check_value(sl'delayed(0 ns)'last_event, 10*C_CLK100M_PERIOD, ERROR, "Check start of pulse");
wait for 0 ns; -- Wait for signal to be updated
check_value(sl, '0', ERROR, "pulse for 10 clk periods, pulse done", C_SCOPE);
check_value(sl'last_event, 0 ns, ERROR, "pulse for 10 clk periods. Check that it actually pulsed for a delta cycle", C_SCOPE);
check_value(sl'last_value, '1', ERROR, "pulse for 10 clk periods, check that it actually pulsed for a delta cycle", C_SCOPE);
wait for 100 ns;
-- ####################### END OF BLOCK 2 ##########################
--==================================================================================================
-- Ending the simulation
--------------------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(INTERMEDIATE);
report_alert_counters(FINAL);
log(ID_LOG_HDR,"SIMULATION COMPLETED", C_SCOPE);
assert false
report "End of simulation. (***Ignore this failure. Was provoked to stop the simulation.)"
severity failure;
wait; -- to stop completely
end process p_main;
end func;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : partial_test_tb
--
-- Description : Parts of the testbench used for testing the Bitvis Utility Library
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use std.textio.all;
library work;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
use work.methods_pkg.all;
use work.bfm_common_pkg.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all; -- Used for to_string(real)
use ieee_proposed.std_logic_1164_additions.all; -- Used for to_string(std_logic)
entity partial_test_tb is
end entity;
architecture func of partial_test_tb is
signal sl : std_logic := '0';
signal clk100M : std_logic;
signal clk100M_ena : boolean := true;
signal clk200M : std_logic;
signal clk200M_ena : boolean := true;
signal clk50M : std_logic;
constant C_CLK100M_PERIOD : time := 10 ns;
begin
------------------------------------------------
-- Process: clock generator
------------------------------------------------
-- Overloaded version with enable signal as argument
clock_generator(clk100M, clk100M_ena, C_CLK100M_PERIOD, "Clk100M");
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
constant C_SCOPE : string := "TB seq";
-- Log overloads for simplification
procedure log(
msg : string) is
begin
log(ID_SEQUENCER, msg, C_SCOPE);
end;
begin
set_alert_file_name("alertlog.txt");
set_log_file_name("testlog.txt");
set_alert_stop_limit(WARNING, 0);
set_alert_stop_limit(ERROR, 0); -- 0 = Never stop
wait for 1 ns;
-- ####################### BLOCK 1 - Causes "internal error: delayed" ##########################
-- FROM_NOW, FROM_NOW
await_stable(sl, 50 ns, FROM_NOW, 100 ns, FROM_NOW, ERROR, "sl: Stable FROM_NOW, FROM_NOW, OK after 50 ns", C_SCOPE);
sl <= transport not sl after 30 ns;
await_stable(sl, 50 ns, FROM_NOW, 100 ns, FROM_NOW, ERROR, "sl: Stable FROM_NOW, FROM_NOW, OK after 80 ns", C_SCOPE);
sl <= transport not sl after 30 ns;
await_stable(sl, 50 ns, FROM_NOW, 60 ns, FROM_NOW, ERROR, "sl: Not stable FROM_NOW, FROM_NOW, Fail after 30 ns", C_SCOPE);
increment_expected_alerts(ERROR, 1);
await_stable(sl, 50 ns, FROM_NOW, 1 ns, FROM_NOW, ERROR, "sl: Timeout before stable_req, FROM_NOW, FROM_NOW, Fail immediately", C_SCOPE);
increment_expected_alerts(ERROR, 1);
await_stable(sl, 0 ns, FROM_NOW, 0 ns, FROM_NOW, ERROR, "sl: stable for 0 ns, FROM_NOW, FROM_NOW, OK after 0 ns", C_SCOPE);
-- FROM_LAST_EVENT, FROM_NOW
sl <= not sl;
log("NOTE: ERROR HAPPENS AFTER HERE");
wait for 10 ns;
log("NOTE: ERROR HAPPENS BEFORE HERE");
-- ####################### END OF BLOCK 1 ##########################
-- ####################### BLOCK 2 - Code works if this is removed ##########################
-- Pulse a certain number of clock periods
clk100M_ena <= true; -- Clock must be running
sl <= '0';
wait for 0 ns; -- Wait for signal to update
gen_pulse(sl, clk100M, 10, "Test pulse 10 clk periods");
check_value(sl'delayed(0 ns)'last_event, 10*C_CLK100M_PERIOD, ERROR, "Check start of pulse");
wait for 0 ns; -- Wait for signal to be updated
check_value(sl, '0', ERROR, "pulse for 10 clk periods, pulse done", C_SCOPE);
check_value(sl'last_event, 0 ns, ERROR, "pulse for 10 clk periods. Check that it actually pulsed for a delta cycle", C_SCOPE);
check_value(sl'last_value, '1', ERROR, "pulse for 10 clk periods, check that it actually pulsed for a delta cycle", C_SCOPE);
wait for 100 ns;
-- ####################### END OF BLOCK 2 ##########################
--==================================================================================================
-- Ending the simulation
--------------------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(INTERMEDIATE);
report_alert_counters(FINAL);
log(ID_LOG_HDR,"SIMULATION COMPLETED", C_SCOPE);
assert false
report "End of simulation. (***Ignore this failure. Was provoked to stop the simulation.)"
severity failure;
wait; -- to stop completely
end process p_main;
end func;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : partial_test_tb
--
-- Description : Parts of the testbench used for testing the Bitvis Utility Library
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use std.textio.all;
library work;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
use work.methods_pkg.all;
use work.bfm_common_pkg.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all; -- Used for to_string(real)
use ieee_proposed.std_logic_1164_additions.all; -- Used for to_string(std_logic)
entity partial_test_tb is
end entity;
architecture func of partial_test_tb is
signal sl : std_logic := '0';
signal clk100M : std_logic;
signal clk100M_ena : boolean := true;
signal clk200M : std_logic;
signal clk200M_ena : boolean := true;
signal clk50M : std_logic;
constant C_CLK100M_PERIOD : time := 10 ns;
begin
------------------------------------------------
-- Process: clock generator
------------------------------------------------
-- Overloaded version with enable signal as argument
clock_generator(clk100M, clk100M_ena, C_CLK100M_PERIOD, "Clk100M");
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
constant C_SCOPE : string := "TB seq";
-- Log overloads for simplification
procedure log(
msg : string) is
begin
log(ID_SEQUENCER, msg, C_SCOPE);
end;
begin
set_alert_file_name("alertlog.txt");
set_log_file_name("testlog.txt");
set_alert_stop_limit(WARNING, 0);
set_alert_stop_limit(ERROR, 0); -- 0 = Never stop
wait for 1 ns;
-- ####################### BLOCK 1 - Causes "internal error: delayed" ##########################
-- FROM_NOW, FROM_NOW
await_stable(sl, 50 ns, FROM_NOW, 100 ns, FROM_NOW, ERROR, "sl: Stable FROM_NOW, FROM_NOW, OK after 50 ns", C_SCOPE);
sl <= transport not sl after 30 ns;
await_stable(sl, 50 ns, FROM_NOW, 100 ns, FROM_NOW, ERROR, "sl: Stable FROM_NOW, FROM_NOW, OK after 80 ns", C_SCOPE);
sl <= transport not sl after 30 ns;
await_stable(sl, 50 ns, FROM_NOW, 60 ns, FROM_NOW, ERROR, "sl: Not stable FROM_NOW, FROM_NOW, Fail after 30 ns", C_SCOPE);
increment_expected_alerts(ERROR, 1);
await_stable(sl, 50 ns, FROM_NOW, 1 ns, FROM_NOW, ERROR, "sl: Timeout before stable_req, FROM_NOW, FROM_NOW, Fail immediately", C_SCOPE);
increment_expected_alerts(ERROR, 1);
await_stable(sl, 0 ns, FROM_NOW, 0 ns, FROM_NOW, ERROR, "sl: stable for 0 ns, FROM_NOW, FROM_NOW, OK after 0 ns", C_SCOPE);
-- FROM_LAST_EVENT, FROM_NOW
sl <= not sl;
log("NOTE: ERROR HAPPENS AFTER HERE");
wait for 10 ns;
log("NOTE: ERROR HAPPENS BEFORE HERE");
-- ####################### END OF BLOCK 1 ##########################
-- ####################### BLOCK 2 - Code works if this is removed ##########################
-- Pulse a certain number of clock periods
clk100M_ena <= true; -- Clock must be running
sl <= '0';
wait for 0 ns; -- Wait for signal to update
gen_pulse(sl, clk100M, 10, "Test pulse 10 clk periods");
check_value(sl'delayed(0 ns)'last_event, 10*C_CLK100M_PERIOD, ERROR, "Check start of pulse");
wait for 0 ns; -- Wait for signal to be updated
check_value(sl, '0', ERROR, "pulse for 10 clk periods, pulse done", C_SCOPE);
check_value(sl'last_event, 0 ns, ERROR, "pulse for 10 clk periods. Check that it actually pulsed for a delta cycle", C_SCOPE);
check_value(sl'last_value, '1', ERROR, "pulse for 10 clk periods, check that it actually pulsed for a delta cycle", C_SCOPE);
wait for 100 ns;
-- ####################### END OF BLOCK 2 ##########################
--==================================================================================================
-- Ending the simulation
--------------------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(INTERMEDIATE);
report_alert_counters(FINAL);
log(ID_LOG_HDR,"SIMULATION COMPLETED", C_SCOPE);
assert false
report "End of simulation. (***Ignore this failure. Was provoked to stop the simulation.)"
severity failure;
wait; -- to stop completely
end process p_main;
end func;
|
library verilog;
use verilog.vl_types.all;
entity CMMaster0Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_TESTREMAPENABLE: in vl_logic;
F2_TESTESRAM1REMAP: in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_ESRAMFWREMAP: in vl_logic;
COM_ENVMREMAPSIZE: in vl_logic_vector(4 downto 0);
COM_ENVMREMAPBASE: in vl_logic_vector(19 downto 0);
COM_CLEARSTATUS : in vl_logic;
COM_ERRORSTATUS : out vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HMASTLOCK : in vl_logic;
HSIZE : in vl_logic_vector(2 downto 0);
HTRANS1 : in vl_logic;
HWRITE : in vl_logic;
HRESP : out vl_logic;
HRDATA : out vl_logic_vector(31 downto 0);
HREADY_M : out vl_logic;
sAddrReady : in vl_logic_vector(7 downto 0);
sDataReady : in vl_logic_vector(7 downto 0);
sHResp : in vl_logic_vector(7 downto 0);
gatedHADDR : out vl_logic_vector(31 downto 0);
gatedHMASTLOCK : out vl_logic;
gatedHSIZE : out vl_logic_vector(2 downto 0);
gatedHTRANS1 : out vl_logic;
gatedHWRITE : out vl_logic;
sAddrSel : out vl_logic_vector(7 downto 0);
sDataSel : out vl_logic_vector(7 downto 0);
prevDataSlaveReady: out vl_logic;
HRDATA_S0 : in vl_logic_vector(31 downto 0);
HREADYOUT_S0 : in vl_logic;
HRDATA_S1 : in vl_logic_vector(31 downto 0);
HREADYOUT_S1 : in vl_logic;
HRDATA_S2 : in vl_logic_vector(31 downto 0);
HREADYOUT_S2 : in vl_logic
);
end CMMaster0Stage;
|
library verilog;
use verilog.vl_types.all;
entity CMMaster0Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_TESTREMAPENABLE: in vl_logic;
F2_TESTESRAM1REMAP: in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_ESRAMFWREMAP: in vl_logic;
COM_ENVMREMAPSIZE: in vl_logic_vector(4 downto 0);
COM_ENVMREMAPBASE: in vl_logic_vector(19 downto 0);
COM_CLEARSTATUS : in vl_logic;
COM_ERRORSTATUS : out vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HMASTLOCK : in vl_logic;
HSIZE : in vl_logic_vector(2 downto 0);
HTRANS1 : in vl_logic;
HWRITE : in vl_logic;
HRESP : out vl_logic;
HRDATA : out vl_logic_vector(31 downto 0);
HREADY_M : out vl_logic;
sAddrReady : in vl_logic_vector(7 downto 0);
sDataReady : in vl_logic_vector(7 downto 0);
sHResp : in vl_logic_vector(7 downto 0);
gatedHADDR : out vl_logic_vector(31 downto 0);
gatedHMASTLOCK : out vl_logic;
gatedHSIZE : out vl_logic_vector(2 downto 0);
gatedHTRANS1 : out vl_logic;
gatedHWRITE : out vl_logic;
sAddrSel : out vl_logic_vector(7 downto 0);
sDataSel : out vl_logic_vector(7 downto 0);
prevDataSlaveReady: out vl_logic;
HRDATA_S0 : in vl_logic_vector(31 downto 0);
HREADYOUT_S0 : in vl_logic;
HRDATA_S1 : in vl_logic_vector(31 downto 0);
HREADYOUT_S1 : in vl_logic;
HRDATA_S2 : in vl_logic_vector(31 downto 0);
HREADYOUT_S2 : in vl_logic
);
end CMMaster0Stage;
|
library verilog;
use verilog.vl_types.all;
entity CMMaster0Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_TESTREMAPENABLE: in vl_logic;
F2_TESTESRAM1REMAP: in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_ESRAMFWREMAP: in vl_logic;
COM_ENVMREMAPSIZE: in vl_logic_vector(4 downto 0);
COM_ENVMREMAPBASE: in vl_logic_vector(19 downto 0);
COM_CLEARSTATUS : in vl_logic;
COM_ERRORSTATUS : out vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HMASTLOCK : in vl_logic;
HSIZE : in vl_logic_vector(2 downto 0);
HTRANS1 : in vl_logic;
HWRITE : in vl_logic;
HRESP : out vl_logic;
HRDATA : out vl_logic_vector(31 downto 0);
HREADY_M : out vl_logic;
sAddrReady : in vl_logic_vector(7 downto 0);
sDataReady : in vl_logic_vector(7 downto 0);
sHResp : in vl_logic_vector(7 downto 0);
gatedHADDR : out vl_logic_vector(31 downto 0);
gatedHMASTLOCK : out vl_logic;
gatedHSIZE : out vl_logic_vector(2 downto 0);
gatedHTRANS1 : out vl_logic;
gatedHWRITE : out vl_logic;
sAddrSel : out vl_logic_vector(7 downto 0);
sDataSel : out vl_logic_vector(7 downto 0);
prevDataSlaveReady: out vl_logic;
HRDATA_S0 : in vl_logic_vector(31 downto 0);
HREADYOUT_S0 : in vl_logic;
HRDATA_S1 : in vl_logic_vector(31 downto 0);
HREADYOUT_S1 : in vl_logic;
HRDATA_S2 : in vl_logic_vector(31 downto 0);
HREADYOUT_S2 : in vl_logic
);
end CMMaster0Stage;
|
component ni2 is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_external_connection_export : out std_logic_vector(7 downto 0) -- export
);
end component ni2;
u0 : component ni2
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
pio_external_connection_export => CONNECTED_TO_pio_external_connection_export -- pio_external_connection.export
);
|
component ni2 is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_external_connection_export : out std_logic_vector(7 downto 0) -- export
);
end component ni2;
u0 : component ni2
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
pio_external_connection_export => CONNECTED_TO_pio_external_connection_export -- pio_external_connection.export
);
|
component ni2 is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_external_connection_export : out std_logic_vector(7 downto 0) -- export
);
end component ni2;
u0 : component ni2
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
pio_external_connection_export => CONNECTED_TO_pio_external_connection_export -- pio_external_connection.export
);
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY t_display IS
END t_display;
ARCHITECTURE behavior OF t_display IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT display
PORT(
a : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
display1 : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal display1 : std_logic_vector(6 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: display PORT MAP (
a => a,
clk => clk,
display1 => display1
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
entity substractor is
port(
X, Y: in std_logic_vector(3 downto 0);
Bin: in std_logic;
D: out std_logic_vector(3 downto 0);
Bout: out std_logic
);
end entity;
architecture substractor of substractor is
component full_sub is
port(
X, Y: in std_logic;
Bin: in std_logic;
Bout: out std_logic;
D: out std_logic
);
end component;
signal B_1_2, B_2_3, B_3_4: std_logic;
begin
SUB1: full_sub port map(X => X(3), Y => Y(3), Bin => Bin, D => D(3), Bout => B_1_2);
SUB2: full_sub port map(X => X(2), Y => Y(2), Bin => B_1_2, D => D(2), Bout => B_2_3);
SUB3: full_sub port map(X => X(1), Y => Y(1), Bin => B_2_3, D => D(1), Bout => B_3_4);
SUB4: full_sub port map(X => X(0), Y => Y(0), Bin => B_3_4, D => D(0), Bout => Bout );
end architecture;
|
--
-- ADC interface
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpuino_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity zpuino_adc is
generic (
fifo_width_bits: integer := 16;
upper_offset: integer := 15;
lower_offset: integer := 4
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
sample: in std_logic; -- External trigger
-- GPIO SPI pins
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
seln: out std_logic;
enabled: out std_logic
);
end entity zpuino_adc;
architecture behave of zpuino_adc is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
constant fifo_lower_bit: integer := fifo_width_bits/8;
signal request_samples_q: unsigned(11-fifo_lower_bit downto 0); -- Maximum 4K samples
signal current_sample_q: unsigned(11-fifo_lower_bit downto 0); -- Current sample
signal read_fifo_ptr_q: unsigned(10 downto 2);
-- signal dly_interval_q: unsigned(31 downto 0); -- Additional clock delay between samples
signal fifo_read: std_logic_vector(31 downto 0);
signal fifo_read_address: std_logic_vector(10 downto 2);
signal fifo_write_address: std_logic_vector(11-fifo_lower_bit downto 0);
signal fifo_write: std_logic_vector(fifo_width_bits-1 downto 0);
signal fifo_wr: std_logic;
signal spi_dout: std_logic_vector(31 downto 0);
signal spi_enable: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
-- Configuration registers
signal adc_enabled_q: std_logic;
signal adc_source_external_q: std_logic;
signal run_spi: std_logic;
signal do_sample: std_logic;
begin
enabled <= adc_enabled_q;
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
process(spi_enable,spi_ready)
begin
seln<='1';
if spi_enable='1' or spi_ready='0' then
seln<='0';
end if;
end process;
adcspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => (others => '0'), -- Change to channel number
dout => spi_dout,
en => spi_enable,
ready => spi_ready,
transfersize => "01", -- Fixed 16-bit transfers
miso => miso,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => '1'
);
acdclkgen: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
cpol => '1',
pres => "010", -- Fixed
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck
);
process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
read_fifo_ptr_q <= (others => '0');
else
if wb_we_i='1' and wb_adr_i(4 downto 2)="100" then
read_fifo_ptr_q <= unsigned(wb_dat_i(10 downto 2));
else
if wb_cyc_i='1' and wb_we_i='0' and wb_stb_i='1' and wb_adr_i(4 downto 2)="101" then
-- FIFO wb_dat_o, increment wb_adr_i
read_fifo_ptr_q <= read_fifo_ptr_q+1;
end if;
end if;
end if;
end if;
end process;
-- READ muxer
process(wb_adr_i,fifo_read,request_samples_q,current_sample_q)
begin
wb_dat_o <= (others => DontCareValue);
case wb_adr_i(4 downto 2) is
when "000" =>
if (request_samples_q /= current_sample_q) then
wb_dat_o(0) <= '0';
else
wb_dat_o(0) <= '1';
end if;
when "101" =>
wb_dat_o <= fifo_read;
when others =>
end case;
end process;
fifo_write_address <= std_logic_vector(current_sample_q);
fifo_read_address <= std_logic_vector(read_fifo_ptr_q);
process(spi_dout)
begin
fifo_write <= (others => '0');
fifo_write(upper_offset-lower_offset downto 0) <= spi_dout(upper_offset downto lower_offset); -- Data from SPI
end process;
ram8: if fifo_width_bits=8 generate
ram: RAMB16_S9_S36
port map (
DOA => open,
DOB => fifo_read,
DOPA => open,
DOPB => open,
ADDRA => fifo_write_address,
ADDRB => fifo_read_address,
CLKA => wb_clk_i,
CLKB => wb_clk_i,
DIA => fifo_write,
DIB => (others => '0'),
DIPA => (others => '0'),
DIPB => (others => '0'),
ENA => '1',
ENB => '1',
SSRA => '0',
SSRB => '0',
WEA => fifo_wr,
WEB => '0'
);
end generate;
ram16: if fifo_width_bits=16 generate
ram: RAMB16_S18_S36
port map (
DOA => open,
DOB => fifo_read,
DOPA => open,
DOPB => open,
ADDRA => fifo_write_address,
ADDRB => fifo_read_address,
CLKA => wb_clk_i,
CLKB => wb_clk_i,
DIA => fifo_write,
DIB => (others => '0'),
DIPA => (others => '0'),
DIPB => (others => '0'),
ENA => '1',
ENB => '1',
SSRA => '0',
SSRB => '0',
WEA => fifo_wr,
WEB => '0'
);
end generate;
spi_enable <= '1' when run_spi='1' and spi_ready='1' and do_sample='1' else '0';
do_sample <= sample when adc_source_external_q='1' else '1';
-- Main process
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
request_samples_q <= (others => '0');
current_sample_q <= (others => '0');
run_spi <= '0';
fifo_wr <= '0';
adc_source_external_q <= '0';
adc_enabled_q<='0';
else
fifo_wr <= '0';
if wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
-- Write configuration
adc_enabled_q <= wb_dat_i(0);
adc_source_external_q <= wb_dat_i(1);
when "001" =>
-- Write request samples
request_samples_q <= unsigned(wb_dat_i(11-fifo_lower_bit downto 0));
current_sample_q <= (others => '1'); -- WARNING - this will overwrite last value on RAM
run_spi <= '1';
when others =>
end case;
else
-- Normal run.
if (request_samples_q /= current_sample_q) then
-- Sampling right now.
if spi_ready='1' then
-- Add delay here.
if do_sample='1' then
fifo_wr <= '1';
run_spi <= '1';
end if;
end if;
else
run_spi <= '0';
end if;
if fifo_wr='1' then
current_sample_q <= current_sample_q + 1;
end if;
end if;
end if;
end if;
end process;
end behave;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grlfpw
-- File: grlfpw.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU LITE / GRLFPC wrapper
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.gencomp.all;
entity grlfpw_net is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 1 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of grlfpw_net is
component grlfpw_0_axcelerator is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3 is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_unisim
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_altera
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_stratixii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_stratixiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_cycloneiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_actfus is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3e is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3l is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
begin
alt : if (tech = altera) generate -- Cyclone, Stratix V, Cyclone V
grlfpw0 : grlfpw_0_altera
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtx : if (tech = stratix1) or (tech = stratix2) generate
grlfpw0 : grlfpw_0_stratixii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtxiii : if (tech = stratix3) or (tech = stratix4) generate
grlfpw40 : grlfpw_0_stratixiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
cyc3 : if (tech = cyclone3) generate
grlfpw40 : grlfpw_0_cycloneiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
ax : if (tech = axcel) or (tech = axdsp) generate
grlfpw0 : grlfpw_0_axcelerator
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
fus : if (tech = actfus) generate
grlfpw0 : grlfpw_0_actfus
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3 : if (tech = apa3) generate
grlfpw0 : grlfpw_0_proasic3
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3l : if (tech = apa3l) generate
grlfpw0 : grlfpw_0_proasic3l
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3e : if (tech = apa3e) generate
grlfpw0 : grlfpw_0_proasic3e
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
uni : if (is_unisim(tech) = 1) generate
grlfpw0 : grlfpw_0_unisim
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
end;
|
library ieee ;
context ieee.ieee_std_context;
use work.components.all;
entity top is
port (
pin1: out std_logic
);
attribute LOC: string;
attribute LOC of pin1: signal is "13";
end;
architecture arch of top is
signal clk: std_logic;
signal led_timer: unsigned(23 downto 0) := (others=>'0');
begin
internal_oscillator_inst: OSCH
generic map (
NOM_FREQ => "16.63"
)
port map (
STDBY => '0',
OSC => clk
);
process(clk)
begin
if rising_edge(clk) then
led_timer <= led_timer + 1;
end if;
end process;
pin1 <= led_timer(led_timer'left);
end;
|
library ieee ;
context ieee.ieee_std_context;
use work.components.all;
entity top is
port (
pin1: out std_logic
);
attribute LOC: string;
attribute LOC of pin1: signal is "13";
end;
architecture arch of top is
signal clk: std_logic;
signal led_timer: unsigned(23 downto 0) := (others=>'0');
begin
internal_oscillator_inst: OSCH
generic map (
NOM_FREQ => "16.63"
)
port map (
STDBY => '0',
OSC => clk
);
process(clk)
begin
if rising_edge(clk) then
led_timer <= led_timer + 1;
end if;
end process;
pin1 <= led_timer(led_timer'left);
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:34:50 02/23/2010
-- Design Name:
-- Module Name: VGA_Display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VGA_Display is
generic (MX_HS : NATURAL := 800;
MX_VS : NATURAL := 521);
PORT(
En : IN std_logic;
Xin : IN NATURAL range 0 to MX_HS;
Yin : IN NATURAL range 0 to MX_VS;
R : OUT std_logic_vector(2 downto 0);
G : OUT std_logic_vector(2 downto 0);
B : OUT std_logic_vector(1 downto 0));
end VGA_Display;
architecture Behavioral of VGA_Display is
signal Color : std_logic_vector(7 downto 0);
begin
process(En, Xin, Yin, Color)
begin
if En = '1' then
if Xin < 80 then Color <= "11100000";
elsif Xin < 160 then Color <= "00011100";
elsif Xin < 240 then Color <= "00000011";
elsif Xin < 320 then Color <= "10110110";
elsif Xin < 400 then Color <= "01001001";
elsif Xin < 480 then Color <= "11111100";
elsif Xin < 560 then Color <= "11100011";
else Color <= "00011111";
end if;
else Color <= "00000000";
end if;
R <= Color(7 downto 5);
G <= Color(4 downto 2);
B <= Color(1 downto 0);
end process;
end Behavioral;
|
entity delay3 is
end entity;
architecture test of delay3 is
signal x : bit;
begin
p1: process is
variable v : time := 5 ns;
begin
x <= reject v inertial '1' after 2 ns;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Data/address/control bus for simple von-Neumann MCU.
-- The bus master (CPU) can read/write in every cycle. The bus slaves are
-- assumed to have registerd read data output with an address-in to data-out
-- latency of 1 cc. The read data muxing from bus slaves to the bus master is
-- done combinationally. Thus, at the bus master interface, there results a
-- read data latency of 1 cc.
-------------------------------------------------------------------------------
-- Note on code portability:
-------------------------------------------------------------------------------
-- The address decoding logic as implemented in process P_dec below, shows how
-- to write portable code by means of a user-defined enumaration type which is
-- used as the index range for a constant array, see mcu_pkg. This allows to
-- leave the local code (in process P_dec) unchanged when the number and/or
-- base addresses of the bus slaves in the system change. Such changes then
-- need only to be made in the global definition package.
-- To generate such portable code for the rest of the functionality (e.g. for
-- the read data mux) would require to organize all data input vectors in a
-- signal array first. This would destroy the portability of the code, since it
-- requires manual code adaption when design parameter change.
-------------------------------------------------------------------------------
-- Total # of FFs: 3
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity buss is
port(rst : in std_logic;
clk : in std_logic;
-- CPU bus signals
cpu_in : in t_cpu2bus;
cpu_out : out t_bus2cpu;
-- ROM bus signals
rom_in : in t_ros2bus;
rom_out : out t_bus2ros;
-- RAM bus signals
ram_in : in t_rws2bus;
ram_out : out t_bus2rws;
-- GPIO bus signals
gpio_in : in t_rws2bus;
gpio_out : out t_bus2rws;
-- FMC bus signals
fmc_in : in t_rws2bus;
fmc_out : out t_bus2rws
);
end buss;
architecture rtl of buss is
-- currently addressed bus slave
signal bus_slave, bus_slave_reg : t_bus_slave;
begin
-----------------------------------------------------------------------------
-- address decoding
-----------------------------------------------------------------------------
-- convey lower address bist from CPU to all bus slaves
rom_out.addr <= cpu_in.addr(AWL-1 downto 0);
ram_out.addr <= cpu_in.addr(AWL-1 downto 0);
gpio_out.addr <= cpu_in.addr(AWL-1 downto 0);
fmc_out.addr <= cpu_in.addr(AWL-1 downto 0);
-- combinational process:
-- determine addressed slave by decoding higher address bits
-----------------------------------------------------------------------------
P_dec: process(cpu_in)
begin
bus_slave <= ROM; -- default assignment
for k in t_bus_slave loop
if cpu_in.addr(AW-1 downto AW-AWH) = HBA(k) then
bus_slave <= k;
end if;
end loop;
end process;
-----------------------------------------------------------------------------
-- write transfer logic
-----------------------------------------------------------------------------
-- convey write data from CPU to all bus slaves
-- rom is read-only slave
ram_out.data <= cpu_in.data;
gpio_out.data <= cpu_in.data;
fmc_out.data <= cpu_in.data;
-- convey write enable from CPU to addressed slave only
ram_out.wr_enb <= cpu_in.wr_enb when bus_slave = RAM else '0';
gpio_out.wr_enb <= cpu_in.wr_enb when bus_slave = GPIO else '0';
fmc_out.wr_enb <= cpu_in.wr_enb when bus_slave = FMC else '0';
-----------------------------------------------------------------------------
-- read transfer logic
-----------------------------------------------------------------------------
-- read data mux
with bus_slave_reg select cpu_out.data <= rom_in.data when ROM,
ram_in.data when RAM,
gpio_in.data when GPIO,
fmc_in.data when FMC,
(others => '-') when others;
-- convey read enable from CPU to addressed slave only
ram_out.rd_enb <= cpu_in.rd_enb when bus_slave = RAM else '0';
gpio_out.rd_enb <= cpu_in.rd_enb when bus_slave = GPIO else '0';
fmc_out.rd_enb <= cpu_in.rd_enb when bus_slave = FMC else '0';
-- sequential process:
-- register decode information to compensate read-latency of slaves
-----------------------------------------------------------------------------
P_reg: process(rst, clk)
begin
if rst = '1' then
bus_slave_reg <= ROM;
elsif rising_edge(clk) then
bus_slave_reg <= bus_slave;
end if;
end process;
end rtl;
|
------------------------------------------------------------------------
-- title : package for the 10 gig ethernet mac fifo reference design
-- project : 10 gig ethernet mac fifo reference design
------------------------------------------------------------------------
-- file : xgmac_fifo_pack.vhd
-- author : xilinx inc.
------------------------------------------------------------------------
-- description : this module is the package used by the 10-gigabit
-- ethernet mac fifo interface.
--
------------------------------------------------------------------------
-- (c) Copyright 2001-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package xgmac_fifo_pack is
---------------------------------------------------------------------
-- purpose: define function to convert fifo word size into an address
-- width
-- type : function
---------------------------------------------------------------------
function log2 (
value : integer)
return integer;
---------------------------------------------------------------------
-- purpose : converts gray code to binary code
-- type : function
---------------------------------------------------------------------
function gray_to_bin (
gray : std_logic_vector)
return std_logic_vector;
---------------------------------------------------------------------
-- purpose : converts binary to gray code (by calling gray_to_bin)
---------------------------------------------------------------------
function bin_to_gray (
bin : std_logic_vector)
return std_logic_vector;
end xgmac_fifo_pack;
package body xgmac_fifo_pack is
---------------------------------------------------------------------
-- purpose: define function to convert fifo word size into an address
-- width
-- type : function
---------------------------------------------------------------------
function log2 (value : integer) return integer is
variable ret_val : integer;
begin
ret_val := 0;
if value <= 2**ret_val then
ret_val := 0;
else
while 2**ret_val < value loop
ret_val := ret_val + 1;
end loop;
end if;
return ret_val;
end log2;
function gray_to_bin (
gray : std_logic_vector)
return std_logic_vector is
variable binary : std_logic_vector(gray'range);
begin
for i in gray'high downto gray'low loop
if i = gray'high then
binary(i) := gray(i);
else
binary(i) := binary(i+1) xor gray(i);
end if;
end loop; -- i
return binary;
end gray_to_bin;
function bin_to_gray (
bin : std_logic_vector)
return std_logic_vector is
variable gray : std_logic_vector(bin'range);
begin
for i in bin'range loop
if i = bin'left then
gray(i) := bin(i);
else
gray(i) := bin(i+1) xor bin(i);
end if;
end loop; -- i
return gray;
end bin_to_gray;
end xgmac_fifo_pack;
|
------------------------------------------------------------------------
-- title : package for the 10 gig ethernet mac fifo reference design
-- project : 10 gig ethernet mac fifo reference design
------------------------------------------------------------------------
-- file : xgmac_fifo_pack.vhd
-- author : xilinx inc.
------------------------------------------------------------------------
-- description : this module is the package used by the 10-gigabit
-- ethernet mac fifo interface.
--
------------------------------------------------------------------------
-- (c) Copyright 2001-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package xgmac_fifo_pack is
---------------------------------------------------------------------
-- purpose: define function to convert fifo word size into an address
-- width
-- type : function
---------------------------------------------------------------------
function log2 (
value : integer)
return integer;
---------------------------------------------------------------------
-- purpose : converts gray code to binary code
-- type : function
---------------------------------------------------------------------
function gray_to_bin (
gray : std_logic_vector)
return std_logic_vector;
---------------------------------------------------------------------
-- purpose : converts binary to gray code (by calling gray_to_bin)
---------------------------------------------------------------------
function bin_to_gray (
bin : std_logic_vector)
return std_logic_vector;
end xgmac_fifo_pack;
package body xgmac_fifo_pack is
---------------------------------------------------------------------
-- purpose: define function to convert fifo word size into an address
-- width
-- type : function
---------------------------------------------------------------------
function log2 (value : integer) return integer is
variable ret_val : integer;
begin
ret_val := 0;
if value <= 2**ret_val then
ret_val := 0;
else
while 2**ret_val < value loop
ret_val := ret_val + 1;
end loop;
end if;
return ret_val;
end log2;
function gray_to_bin (
gray : std_logic_vector)
return std_logic_vector is
variable binary : std_logic_vector(gray'range);
begin
for i in gray'high downto gray'low loop
if i = gray'high then
binary(i) := gray(i);
else
binary(i) := binary(i+1) xor gray(i);
end if;
end loop; -- i
return binary;
end gray_to_bin;
function bin_to_gray (
bin : std_logic_vector)
return std_logic_vector is
variable gray : std_logic_vector(bin'range);
begin
for i in bin'range loop
if i = bin'left then
gray(i) := bin(i);
else
gray(i) := bin(i+1) xor bin(i);
end if;
end loop; -- i
return gray;
end bin_to_gray;
end xgmac_fifo_pack;
|
------------------------------------------------------------------------
-- title : package for the 10 gig ethernet mac fifo reference design
-- project : 10 gig ethernet mac fifo reference design
------------------------------------------------------------------------
-- file : xgmac_fifo_pack.vhd
-- author : xilinx inc.
------------------------------------------------------------------------
-- description : this module is the package used by the 10-gigabit
-- ethernet mac fifo interface.
--
------------------------------------------------------------------------
-- (c) Copyright 2001-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package xgmac_fifo_pack is
---------------------------------------------------------------------
-- purpose: define function to convert fifo word size into an address
-- width
-- type : function
---------------------------------------------------------------------
function log2 (
value : integer)
return integer;
---------------------------------------------------------------------
-- purpose : converts gray code to binary code
-- type : function
---------------------------------------------------------------------
function gray_to_bin (
gray : std_logic_vector)
return std_logic_vector;
---------------------------------------------------------------------
-- purpose : converts binary to gray code (by calling gray_to_bin)
---------------------------------------------------------------------
function bin_to_gray (
bin : std_logic_vector)
return std_logic_vector;
end xgmac_fifo_pack;
package body xgmac_fifo_pack is
---------------------------------------------------------------------
-- purpose: define function to convert fifo word size into an address
-- width
-- type : function
---------------------------------------------------------------------
function log2 (value : integer) return integer is
variable ret_val : integer;
begin
ret_val := 0;
if value <= 2**ret_val then
ret_val := 0;
else
while 2**ret_val < value loop
ret_val := ret_val + 1;
end loop;
end if;
return ret_val;
end log2;
function gray_to_bin (
gray : std_logic_vector)
return std_logic_vector is
variable binary : std_logic_vector(gray'range);
begin
for i in gray'high downto gray'low loop
if i = gray'high then
binary(i) := gray(i);
else
binary(i) := binary(i+1) xor gray(i);
end if;
end loop; -- i
return binary;
end gray_to_bin;
function bin_to_gray (
bin : std_logic_vector)
return std_logic_vector is
variable gray : std_logic_vector(bin'range);
begin
for i in bin'range loop
if i = bin'left then
gray(i) := bin(i);
else
gray(i) := bin(i+1) xor bin(i);
end if;
end loop; -- i
return gray;
end bin_to_gray;
end xgmac_fifo_pack;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- modified by Thomas Ameseder, Gleichmann Electronics 2004, 2005 to
-- support the use of an external AHB slave and different HPE board versions
------------------------------------------------------------------------------
-- further adapted from Hpe_compact to Hpe_mini (Feb. 2005)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd1, rxd1 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 1000 ns;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
resetn => rst,
resoutn => resoutn,
clk_100mhz => clk,
errorn => error,
address => address(22 downto 1),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
sertx => dsutx,
serrx => dsurx,
rtsn => rtsn,
ctsn => ctsn,
dsuen => dsuen,
dsubre => dsubre,
dsuact => dsuactn,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
-- u1 : mt46v16m16
-- generic map (index => -1, fname => sdramfile)
-- port map(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 1)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
-- phy0 : if CFG_GRETH > 0 generate
-- p0 : phy
-- port map(rst, led_cfg, open, etx_clk, erx_clk, erxd, erx_dv,
-- erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc);
-- end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
use work.IDROMConst.all;
library UNISIM;
use UNISIM.VComponents.all;
entity HostMot2 is
generic
(
ThePinDesc: PinDescType;
TheModuleID: ModuleIDType;
StepGens: integer;
QCounters: integer;
MuxedQCounters: integer;
MuxedQCountersMIM: integer;
PWMGens: integer;
SPIs: integer;
BSPIs: integer;
DBSPIs: integer;
SSSIs: integer;
UARTs: integer;
PWMRefWidth: integer;
StepGenTableWidth: integer;
BSPICSWidth : integer;
DBSPICSWidth : integer;
IDROMType: integer;
SepClocks: boolean;
OneWS: boolean;
UseStepGenPrescaler : boolean;
UseIRQLogic: boolean;
UseWatchDog: boolean;
OffsetToModules: integer;
OffsetToPinDesc: integer;
ClockHigh: integer;
ClockLow: integer;
BoardNameLow : std_Logic_Vector(31 downto 0);
BoardNameHigh : std_Logic_Vector(31 downto 0);
FPGASize: integer;
FPGAPins: integer;
IOPorts: integer;
IOWidth: integer;
PortWidth: integer;
BusWidth: integer;
AddrWidth: integer;
InstStride0: integer;
InstStride1: integer;
RegStride0: integer;
RegStride1: integer;
LEDCount: integer
);
port
(
-- Generic 32 bit bus interface signals --
ibus: in std_logic_vector(buswidth -1 downto 0);
obus: out std_logic_vector(buswidth -1 downto 0);
addr: in std_logic_vector(addrwidth -1 downto 2);
read: in std_logic;
write: in std_logic;
clklow: in std_logic;
clkhigh: in std_logic;
int: out std_logic;
iobits: inout std_logic_vector (iowidth -1 downto 0);
leds: out std_logic_vector(ledcount-1 downto 0)
);
end HostMot2;
architecture dataflow of HostMot2 is
-- decodes --
-- IDROM related signals
signal A : std_logic_vector(addrwidth -1 downto 2);
signal LoadIDROM: std_logic;
signal ReadIDROM: std_logic;
signal LoadIDROMWEn: std_logic;
signal ReadIDROMWEn: std_logic;
signal IDROMWEn: std_logic_vector(0 downto 0);
signal ROMAdd: std_logic_vector(7 downto 0);
-- I/O port related signals
signal AltData : std_logic_vector(IOWidth-1 downto 0);
signal PortSel: std_logic;
signal LoadPortCmd: std_logic_vector(IOPorts -1 downto 0);
signal ReadPortCmd: std_logic_vector(IOPorts -1 downto 0);
signal DDRSel: std_logic;
signal LoadDDRCmd: std_logic_vector(IOPorts -1 downto 0);
signal ReadDDRCmd: std_logic_vector(IOPorts -1 downto 0);
signal AltDataSrcSel: std_logic;
signal LoadAltDataSrcCmd: std_logic_vector(IOPorts -1 downto 0);
signal OpenDrainModeSel: std_logic;
signal LoadOpenDrainModeCmd: std_logic_vector(IOPorts -1 downto 0);
signal OutputInvSel: std_logic;
signal LoadOutputInvCmd: std_logic_vector(IOPorts -1 downto 0);
-- Step generator related signals
signal StepGenRateSel: std_logic;
signal LoadStepGenRate: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenRate: std_logic_vector(StepGens -1 downto 0);
signal StepGenAccumSel: std_logic;
signal LoadStepGenAccum: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenAccum: std_logic_vector(StepGens -1 downto 0);
signal StepGenModeSel: std_logic;
signal LoadStepGenMode: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenMode: std_logic_vector(StepGens -1 downto 0);
signal StepGenDSUTimeSel: std_logic;
signal LoadStepGenDSUTime: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenDSUTime: std_logic_vector(StepGens -1 downto 0);
signal StepGenDHLDTimeSel: std_logic;
signal LoadStepGenDHLDTime: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenDHLDTime: std_logic_vector(StepGens -1 downto 0);
signal StepGenPulseATimeSel: std_logic;
signal LoadStepGenPulseATime: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenPulseATime: std_logic_vector(StepGens -1 downto 0);
signal StepGenPulseITimeSel: std_logic;
signal LoadStepGenPulseITime: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenPulseITime: std_logic_vector(StepGens -1 downto 0);
signal StepGenTableMaxSel: std_logic;
signal LoadStepGenTableMax: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenTableMax: std_logic_vector(StepGens -1 downto 0);
signal StepGenTableSel: std_logic;
signal LoadStepGenTable: std_logic_vector(StepGens -1 downto 0);
signal ReadStepGenTable: std_logic_vector(StepGens -1 downto 0);
type StepGenOutType is array(StepGens-1 downto 0) of std_logic_vector(StepGenTableWidth-1 downto 0);
signal StepGenOut : StepGenOutType;
-- Step generators master rate related signals
signal LoadStepGenBasicRate: std_logic;
signal ReadStepGenBasicRate: std_logic;
signal StepGenBasicRate: std_logic;
-- Quadrature counter related signals
signal QCounterSel : std_logic;
signal LoadQCounter: std_logic_vector(QCounters-1 downto 0);
signal ReadQCounter: std_logic_vector(QCounters-1 downto 0);
signal QCounterCCRSel : std_logic;
signal LoadQCounterCCR: std_logic_vector(QCounters-1 downto 0);
signal ReadQCounterCCR: std_logic_vector(QCounters-1 downto 0);
-- Quadrature counter timestamp reference counter
signal LoadTSDiv : std_logic;
signal ReadTSDiv : std_logic;
signal ReadTS : std_logic;
signal TimeStampBus: std_logic_vector(15 downto 0);
-- Quadrature counter filter rate signals
signal LoadQCountRate : std_logic;
signal QCountFilterRate : std_logic;
-- Quadrature counter input signals
signal QuadA: std_logic_vector(QCounters-1 downto 0);
signal QuadB: std_logic_vector(QCounters-1 downto 0);
signal Index: std_logic_vector(QCounters -1 downto 0);
signal IndexMask: std_logic_vector(QCounters -1 downto 0);
--- Multiplexed Encoder related signals
signal MuxedQCounterSel : std_logic;
signal LoadMuxedQCounter: std_logic_vector(MuxedQCounters-1 downto 0);
signal ReadMuxedQCounter: std_logic_vector(MuxedQCounters-1 downto 0);
signal MuxedQCounterCCRSel : std_logic;
signal LoadMuxedQCounterCCR: std_logic_vector(MuxedQCounters-1 downto 0);
signal ReadMuxedQCounterCCR: std_logic_vector(MuxedQCounters-1 downto 0);
-- Muxed Quadrature counter timestamp reference counter
signal LoadMuxedTSDiv : std_logic;
signal ReadMuxedTSDiv : std_logic;
signal ReadMuxedTS : std_logic;
signal MuxedTimeStampBus: std_logic_vector(15 downto 0);
-- Muxed Quadrature counter filter rate signals
signal LoadMuxedQCountRate : std_logic;
signal MuxedQCountFilterRate : std_logic;
signal PreMuxedQctrSel : std_logic_vector(1 downto 0);
signal MuxedQCtrSel : std_logic_vector(1 downto 0);
signal MuxedQuadA: std_logic_vector(MuxedQCounters/2 -1 downto 0); -- 2 should be muxdepth constant?
signal MuxedQuadB: std_logic_vector(MuxedQCounters/2 -1 downto 0);
signal MuxedIndex: std_logic_vector(MuxedQCounters/2 -1 downto 0);
signal MuxedIndexMask: std_logic_vector(MuxedQCounters -1 downto 0);
signal MuxedIndexMaskMIM: std_logic_vector(MuxedQCountersMIM/2 -1 downto 0);
signal DemuxedIndexMask: std_logic_vector(MuxedQCountersMIM -1 downto 0);
signal DeMuxedQuadA: std_logic_vector(MuxedQCounters -1 downto 0);
signal DeMuxedQuadB: std_logic_vector(MuxedQCounters -1 downto 0);
signal DeMuxedIndex: std_logic_vector(MuxedQCounters -1 downto 0);
-- PWM generator related signals
signal NumberOfPWMS : integer;
signal PWMGenOutA: std_logic_vector(PWMGens -1 downto 0);
signal PWMGenOutB: std_logic_vector(PWMGens -1 downto 0);
signal PWMGenOutC: std_logic_vector(PWMGens -1 downto 0);
signal LoadPWMRate : std_logic;
signal LoadPDMRate : std_logic;
signal RefCountBus : std_logic_vector(PWMRefWidth-1 downto 0);
signal PDMRate : std_logic;
signal PWMValSel : std_logic;
signal PWMCRSel : std_logic;
signal LoadPWMVal: std_logic_vector(PWMGens -1 downto 0);
signal LoadPWMCR: std_logic_vector(PWMGens -1 downto 0);
signal LoadPWMEnas: std_logic;
signal ReadPWMEnas: std_logic;
--- SPI interface related signals
signal SPIBitCountSel : std_logic;
signal SPIBitrateSel : std_logic;
signal SPIDataSel : std_logic;
signal LoadSPIBitCount: std_logic_vector(SPIs -1 downto 0);
signal LoadSPIBitRate: std_logic_vector(SPIs -1 downto 0);
signal LoadSPIData: std_logic_vector(SPIs -1 downto 0);
signal ReadSPIData: std_logic_vector(SPIs -1 downto 0);
signal ReadSPIBitCOunt: std_logic_vector(SPIs -1 downto 0);
signal ReadSPIBitRate: std_logic_vector(SPIs -1 downto 0);
signal SPIClk: std_logic_vector(SPIs -1 downto 0);
signal SPIIn: std_logic_vector(SPIs -1 downto 0);
signal SPIOut: std_logic_vector(SPIs -1 downto 0);
signal SPIFrame: std_logic_vector(SPIs -1 downto 0);
signal SPIDAV: std_logic_vector(SPIs -1 downto 0);
--- BSPI interface related signals
signal BSPIDataSel : std_logic;
signal BSPIFIFOCountSel : std_logic;
signal BSPIDescriptorSel : std_logic;
signal LoadBSPIData: std_logic_vector(BSPIs -1 downto 0);
signal ReadBSPIData: std_logic_vector(BSPIs -1 downto 0);
signal LoadBSPIDescriptor: std_logic_vector(BSPIs -1 downto 0);
signal ReadBSPIFIFOCOunt: std_logic_vector(BSPIs -1 downto 0);
signal ClearBSPIFIFO: std_logic_vector(BSPIs -1 downto 0);
signal BSPIClk: std_logic_vector(BSPIs -1 downto 0);
signal BSPIIn: std_logic_vector(BSPIs -1 downto 0);
signal BSPIOut: std_logic_vector(BSPIs -1 downto 0);
signal BSPIFrame: std_logic_vector(BSPIs -1 downto 0);
type BSPICSType is array(BSPIs-1 downto 0) of std_logic_vector(BSPICSWidth-1 downto 0);
signal BSPICS : BSPICSType;
--- DBSPI interface related signals
signal DBSPIDataSel : std_logic;
signal DBSPIFIFOCountSel : std_logic;
signal DBSPIDescriptorSel : std_logic;
signal LoadDBSPIData: std_logic_vector(DBSPIs -1 downto 0);
signal ReadDBSPIData: std_logic_vector(DBSPIs -1 downto 0);
signal LoadDBSPIDescriptor: std_logic_vector(DBSPIs -1 downto 0);
signal ReadDBSPIFIFOCOunt: std_logic_vector(DBSPIs -1 downto 0);
signal ClearDBSPIFIFO: std_logic_vector(DBSPIs -1 downto 0);
signal DBSPIClk: std_logic_vector(DBSPIs -1 downto 0);
signal DBSPIIn: std_logic_vector(DBSPIs -1 downto 0);
signal DBSPIOut: std_logic_vector(DBSPIs -1 downto 0);
type DBSPICSType is array(DBSPIs-1 downto 0) of std_logic_vector(DBSPICSWidth-1 downto 0);
signal DBSPICS : DBSPICSType;
--- SSSI interface related signals
signal SSSIDataSel : std_logic;
signal SSSIBitCountSel : std_logic;
signal SSSIBitRateSel : std_logic;
signal LoadSSSIData: std_logic_vector(SSSIs -1 downto 0);
signal ReadSSSIData: std_logic_vector(SSSIs -1 downto 0);
signal LoadSSSIBitCount: std_logic_vector(SSSIs -1 downto 0);
signal ReadSSSIBitCOunt: std_logic_vector(SSSIs -1 downto 0);
signal LoadSSSIBitRate: std_logic_vector(SSSIs -1 downto 0);
signal ReadSSSIBitRate: std_logic_vector(SSSIs -1 downto 0);
signal GlobalPStartSSSI : std_logic;
signal GlobalTStartSSSI : std_logic;
signal SSSIClk: std_logic_vector(SSSIs -1 downto 0);
signal SSSIIn: std_logic_vector(SSSIs -1 downto 0);
--- UARTX interface related signals
signal UARTTDataSel : std_logic;
signal UARTTBitrateSel : std_logic;
signal UARTTFIFOCountSel : std_logic;
signal UARTTModeRegSel : std_logic;
signal LoadUARTTData: std_logic_vector(UARTs -1 downto 0);
signal LoadUARTTBitRate: std_logic_vector(UARTs -1 downto 0);
signal LoadUARTTModeReg: std_logic_vector(UARTs -1 downto 0);
signal CLearUARTTFIFO: std_logic_vector(UARTs -1 downto 0);
signal ReadUARTTFIFOCount: std_logic_vector(UARTs -1 downto 0);
signal ReadUARTTBitrate: std_logic_vector(UARTs -1 downto 0);
signal ReadUARTTModeReg: std_logic_vector(UARTs -1 downto 0);
signal UARTTFIFOEmpty: std_logic_vector(UARTs -1 downto 0);
signal UTDrvEn: std_logic_vector(UARTs -1 downto 0);
signal UTData: std_logic_vector(UARTs -1 downto 0);
--- UARTR interface related signals
signal UARTRDataSel : std_logic;
signal UARTRBitrateSel : std_logic;
signal UARTRFIFOCountSel : std_logic;
signal UARTRModeRegSel : std_logic;
signal LoadUARTRData: std_logic_vector(UARTs -1 downto 0);
signal LoadUARTRBitRate: std_logic_vector(UARTs -1 downto 0);
signal ReadUARTRBitrate: std_logic_vector(UARTs -1 downto 0);
signal ClearUARTRFIFO: std_logic_vector(UARTs -1 downto 0);
signal ReadUARTRFIFOCount: std_logic_vector(UARTs -1 downto 0);
signal ReadUARTRModeReg: std_logic_vector(UARTs -1 downto 0);
signal LoadUARTRModeReg: std_logic_vector(UARTs -1 downto 0);
signal UARTRFIFOHasData: std_logic_vector(UARTs -1 downto 0);
signal URData: std_logic_vector(UARTs -1 downto 0);
--- Watchdog related signals
signal LoadWDTime : std_logic;
signal ReadWDTime : std_logic;
signal LoadWDStatus : std_logic;
signal ReadWDStatus : std_logic;
signal WDCookie: std_logic;
signal WDBite : std_logic;
signal WDLatchedBite : std_logic;
--- IRQ related signals
signal LoadIRQDiv : std_logic;
signal ReadIRQDiv : std_logic;
signal LoadIRQStatus : std_logic;
signal ReadIrqStatus : std_logic;
signal ClearIRQ : std_logic;
--- ID related signals
signal ReadID : std_logic;
--- LED related signals
signal LoadLEDS : std_logic;
function OneOfNdecode(width : integer;ena1 : std_logic;ena2 : std_logic; dec : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(width-1 downto 0);
begin
if ena1 = '1' and ena2 = '1' then
for i in 0 to width -1 loop
if CONV_INTEGER(dec) = i then
result(i) := '1';
else
result(i) := '0';
end if;
end loop;
else
result := (others => '0');
end if;
return result;
end OneOfNDecode;
function bitreverse(v: in std_logic_vector) -- Thanks: J. Bromley
return std_logic_vector is
variable result: std_logic_vector(v'RANGE);
alias tv: std_logic_vector(v'REVERSE_RANGE) is v;
begin
for i in tv'RANGE loop
result(i) := tv(i);
end loop;
return result;
end;
begin
ahosmotid : entity hostmotid
generic map (
buswidth => BusWidth,
cookie => Cookie,
namelow => HostMotNameLow ,
namehigh => HostMotNameHigh,
idromoffset => IDROMOffset
)
port map (
readid => ReadID,
addr => A(3 downto 2),
obus => obus
);
makeoports: for i in 0 to IOPorts -1 generate
oportx: entity WordPR
generic map (
size => PortWidth,
buswidth => BusWidth
)
port map (
clear => WDBite,
clk => clklow,
ibus => ibus,
obus => obus,
loadport => LoadPortCmd(i),
loadddr => LoadDDRCmd(i),
loadaltdatasrc => LoadAltDataSrcCmd(i),
loadopendrainmode => LoadOpenDrainModeCmd(i),
loadinvert => LoadOutputInvCmd(i),
readddr => ReadDDRCmd(i),
portdata => IOBits((((i+1)*PortWidth) -1) downto (i*PortWidth)),
altdata => Altdata((((i+1)*PortWidth) -1) downto (i*PortWidth))
);
end generate;
makeiports: for i in 0 to IOPorts -1 generate
iportx: entity WordRB
generic map (size => PortWidth,
buswidth => BusWidth)
port map (
obus => obus,
readport => ReadPortCmd(i),
portdata => IOBits((((i+1)*PortWidth) -1) downto (i*PortWidth))
);
end generate;
makewatchdog: if UseWatchDog generate
wdogabittus: entity watchdog
generic map ( buswidth => BusWidth)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
loadtime => LoadWDTime,
readtime => ReadWDTime,
loadstatus=> LoadWDStatus,
readstatus=> ReadWDStatus,
cookie => WDCookie,
wdbite => WDBite,
wdlatchedbite => WDLatchedBite
);
end generate;
makeirqlogic: if UseIRQlogic generate
somoldirqlogic: entity irqlogic
generic map(
buswidth => BusWidth,
dividerwidth => 16
)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
loaddiv => LoadIRQDiv,
readdiv => ReadIRQDiv,
loadstatus => LoadIRQStatus,
readstatus => ReadIrqStatus,
clear => ClearIRQ,
ratesource => RefCountBus(PWMRefWidth-1 downto PWMRefWidth-8), -- from toggle bit all the way to 8X PWM rate
int => INT);
end generate;
makestepgens: if StepGens >0 generate
makeStepGenPreScaler: if UseStepGenPreScaler generate
StepRategen : entity RateGen port map(
ibus => ibus,
obus => obus,
loadbasicrate => LoadStepGenBasicRate,
readbasicrate => ReadStepGenBasicRate,
hold => '0',
basicrate => StepGenBasicRate,
clk => clklow);
end generate;
generatestepgens: for i in 0 to StepGens-1 generate
usg: if UseStepGenPreScaler generate
stepgenx: entity stepgen
generic map (
buswidth => BusWidth,
timersize => 14, -- = ~480 usec at 33 MHz, ~320 at 50 Mhz
tablewidth => StepGenTableWidth,
asize => 48,
rsize => 32
)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
loadsteprate => LoadStepGenRate(i),
loadaccum => LoadStepGenAccum(i),
loadstepmode => LoadStepGenMode(i),
loaddirsetuptime => LoadStepGenDSUTime(i),
loaddirholdtime => LoadStepGenDHLDTime(i),
loadpulseactivetime => LoadStepGenPulseATime(i),
loadpulseidletime => LoadStepGenPulseITime(i),
loadtable => LoadStepGenTable(i),
loadtablemax => LoadStepGenTableMax(i),
readsteprate => ReadStepGenRate(i),
readaccum => ReadStepGenAccum(i),
readstepmode => ReadStepGenMode(i),
readdirsetuptime => ReadStepGenDSUTime(i),
readdirholdtime => ReadStepGenDHLDTime(i),
readpulseactivetime => ReadStepGenPulseATime(i),
readpulseidletime => ReadStepGenPulseITime(i),
readtable => ReadStepGenTable(i),
readtablemax => ReadStepGenTableMax(i),
basicrate => StepGenBasicRate,
hold => '0',
stout => StepGenOut(i)
);
end generate usg;
nusg: if not UseStepGenPreScaler generate
stepgenx: entity stepgen
generic map (
buswidth => BusWidth,
timersize => 14, -- = ~480 usec at 33 MHz, ~320 at 50 Mhz
tablewidth => StepGenTableWidth,
asize => 48,
rsize => 32
)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
loadsteprate => LoadStepGenRate(i),
loadaccum => LoadStepGenAccum(i),
loadstepmode => LoadStepGenMode(i),
loaddirsetuptime => LoadStepGenDSUTime(i),
loaddirholdtime => LoadStepGenDHLDTime(i),
loadpulseactivetime => LoadStepGenPulseATime(i),
loadpulseidletime => LoadStepGenPulseITime(i),
loadtable => LoadStepGenTable(i),
loadtablemax => LoadStepGenTableMax(i),
readsteprate => ReadStepGenRate(i),
readaccum => ReadStepGenAccum(i),
readstepmode => ReadStepGenMode(i),
readdirsetuptime => ReadStepGenDSUTime(i),
readdirholdtime => ReadStepGenDHLDTime(i),
readpulseactivetime => ReadStepGenPulseATime(i),
readpulseidletime => ReadStepGenPulseITime(i),
readtable => ReadStepGenTable(i),
readtablemax => ReadStepGenTableMax(i),
basicrate => '1',
hold => '0',
stout => StepGenOut(i) -- densely packed starting with I/O bit 0
);
end generate nusg;
end generate generatestepgens;
end generate makestepgens;
makequadcounters: for i in 0 to QCounters-1 generate
qcounterx: entity qcounter
generic map (
buswidth => BusWidth
)
port map (
obus => obus,
ibus => ibus,
quada => QuadA(i),
quadb => QuadB(i),
index => Index(i),
loadccr => LoadQcounterCCR(i),
readccr => ReadQcounterCCR(i),
readcount => ReadQcounter(i),
countclear => LoadQcounter(i),
timestamp => TimeStampBus,
indexmask => IndexMask(i),
filterrate => QCountFilterRate,
clk => clklow
);
end generate makequadcounters;
makemuxedquadcounters: for i in 0 to MuxedQCounters-1 generate
qcounterx: entity qcounter
generic map (
buswidth => BusWidth
)
port map (
obus => obus,
ibus => ibus,
quada => DemuxedQuadA(i),
quadb => DemuxedQuadB(i),
index => DemuxedIndex(i),
loadccr => LoadMuxedQcounterCCR(i),
readccr => ReadMuxedQcounterCCR(i),
readcount => ReadMuxedQcounter(i),
countclear => LoadMuxedQcounter(i),
timestamp => MuxedTimeStampBus,
indexmask => MuxedIndexMask(i),
filterrate => MuxedQCountFilterRate,
clk => clklow
);
end generate makemuxedquadcounters;
makemuxedquadcountersmim: for i in 0 to MuxedQCountersMIM-1 generate
qcounterx: entity qcounter
generic map (
buswidth => BusWidth
)
port map (
obus => obus,
ibus => ibus,
quada => DemuxedQuadA(i),
quadb => DemuxedQuadB(i),
index => DemuxedIndex(i),
loadccr => LoadMuxedQcounterCCR(i),
readccr => ReadMuxedQcounterCCR(i),
readcount => ReadMuxedQcounter(i),
countclear => LoadMuxedQcounter(i),
timestamp => MuxedTimeStampBus,
indexmask => DeMuxedIndexMask(i),
filterrate => MuxedQCountFilterRate,
clk => clklow
);
end generate makemuxedquadcountersmim;
makeqcounterglobals: if (QCounters >0) generate
timestampx: entity timestamp
port map(
ibus => ibus(15 downto 0),
obus => obus(15 downto 0),
loadtsdiv => LoadTSDiv ,
readts => ReadTS,
readtsdiv =>ReadTSDiv,
tscount => TimeStampBus,
clk => clklow
);
qcountratex: entity qcounterate
generic map (defaultrate => x"800") -- default is clklow divided by 1 for normal counters
port map(
ibus => ibus(11 downto 0),
loadRate => LoadQCountRate,
rateout => QcountFilterRate,
clk => clklow
);
end generate;
makemuxedqcounterglobals: if (MuxedQCounters >0) generate
timestampx: entity timestamp
port map(
ibus => ibus(15 downto 0),
obus => obus(15 downto 0),
loadtsdiv => LoadTSDiv ,
readts => ReadMuxedTS,
readtsdiv =>ReadMuxedTSDiv,
tscount => MuxedTimeStampBus,
clk => clklow
);
qcountratex: entity qcounterate
generic map (defaultrate => x"002") -- default is clklow divided by 4 (N+2) for muxed counters
port map(
ibus => ibus(11 downto 0),
loadRate => LoadMuxedQCountRate,
rateout => MuxedQcountFilterRate,
clk => clklow
);
end generate;
makepwmref: if ((PWMGens > 0) or UseIRQLogic) generate
pwmref : entity pwmrefh
generic map (
buswidth => 16,
refwidth => PWMRefWidth -- Normally 13 for 12,11,10, and 9 bit PWM resolutions = 25KHz,50KHz,100KHz,200KHz max. Freq
)
port map (
clk => clklow,
hclk => clkhigh,
refcount => RefCountBus,
ibus => ibus(15 downto 0),
pdmrate => PDMRate,
pwmrateload => LoadPWMRate,
pdmrateload => LoadPDMRate
);
end generate;
makepwmgens : for i in 0 to PWMGens-1 generate
pwmgenx: entity pwmpdmgenh
generic map (
buswidth => BusWidth,
refwidth => PWMRefWidth -- Normally 13 for 12,11,10, and 9 bit PWM resolutions = 25KHz,50KHz,100KHz,200KHz max. Freq
)
port map (
clk => clklow,
hclk => clkhigh,
refcount => RefCountBus,
ibus => ibus,
loadpwmval => LoadPWMVal(i),
pcrloadcmd => LoadPWMCR(i),
pdmrate => PDMRate,
pwmouta => PWMGenOutA(i),
pwmoutb => PWMGenOutB(i)
);
end generate;
makePWMEna: if (PWMGens >0) generate
PWMEnaReg : entity boutreg
generic map (
size => PWMGens,
buswidth => BusWidth,
invert => true -- Must be true! got changed to false somehow
)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
load => LoadPWMEnas,
read => ReadPWMEnas,
clear => '0',
dout => PWMGenOutC
);
end generate;
makeSPIs: for i in 0 to SPIs -1 generate
aspi: entity SimpleSPI
generic map (
buswidth => BusWidth)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
loadbitcount => LoadSPIBitCount(i),
loadbitrate => LoadSPIBitRate(i),
loaddata => LoadSPIData(i),
readdata => ReadSPIData(i),
readbitcount => ReadSPIBitCOunt(i),
readbitrate => ReadSPIBitRate(i),
spiclk => SPIClk(i),
spiin => SPIIn(i),
spiout => SPIOut(i),
spiframe => SPIFrame(i),
davout => SPIDAV(i)
);
end generate;
makeBSPIs: for i in 0 to BSPIs -1 generate
bspi: entity BufferedSPI
generic map (
cswidth => BSPICSWidth,
gatedcs => false)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
addr => A(5 downto 2),
hostpush => LoadBSPIData(i),
hostpop => ReadBSPIData(i),
loaddesc => LoadBSPIDescriptor(i),
loadasend => '0',
clear => ClearBSPIFIFO(i),
readcount => ReadBSPIFIFOCount(i),
spiclk => BSPIClk(i),
spiin => BSPIIn(i),
spiout => BSPIOut(i),
spiframe => BSPIFrame(i),
spicsout => BSPICS(i)
);
end generate;
makeDBSPIs: for i in 0 to DBSPIs -1 generate
bspi: entity BufferedSPI
generic map (
cswidth => DBSPICSWidth,
gatedcs => true
)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
addr => A(5 downto 2),
hostpush => LoadDBSPIData(i),
hostpop => ReadDBSPIData(i),
loaddesc => LoadDBSPIDescriptor(i),
loadasend => '0',
clear => ClearDBSPIFIFO(i),
readcount => ReadDBSPIFIFOCount(i),
spiclk => DBSPIClk(i),
spiin => DBSPIIn(i),
spiout => DBSPIOut(i),
spicsout => DBSPICS(i)
);
end generate;
MakeSSSIs: for i in 0 to SSSIs -1 generate
sssi: entity SimpleSSI
Port map (
clk => clklow,
ibus => ibus,
obus => obus,
loadbitcount => LoadSSSIBitCount(i),
loadbitrate => LoadSSSIBitRate(i),
lstart => LoadSSSIData(i),
tstart => GlobalTStartSSSI,
pstart => GlobalPstartSSSI,
readdata => ReadSSSIData(i),
readbitcount => ReadSSSIBitCount(i),
readbitrate => ReadSSSIBitRate(i),
ssiclk => SSSIClk(i),
ssiin => SSSIIn(i)
);
end generate;
makeUARTRs: for i in 0 to UARTs -1 generate
auarrx: entity uartr
port map (
clk => clklow,
ibus => ibus,
obus => obus,
addr => A(3 downto 2),
popfifo => LoadUARTRData(i),
loadbitrate => LoadUARTRBitRate(i),
readbitrate => ReadUARTRBitrate(i),
clrfifo => ClearUARTRFIFO(i),
readfifocount => ReadUARTRFIFOCount(i),
loadmode => LoadUARTRModeReg(i),
readmode => ReadUARTRModeReg(i),
fifohasdata => UARTRFIFOHasData(i),
rxmask => UTDrvEn(i), -- for half duplex rx mask
rxdata => URData(i)
);
end generate;
makeUARTTXs: for i in 0 to UARTs -1 generate
auartx: entity uartx
port map (
clk => clklow,
ibus => ibus,
obus => obus,
addr => A(3 downto 2),
pushfifo => LoadUARTTData(i),
loadbitrate => LoadUARTTBitRate(i),
readbitrate => ReadUARTTBitrate(i),
clrfifo => ClearUARTTFIFO(i),
readfifocount => ReadUARTTFIFOCount(i),
loadmode => LoadUARTTModeReg(i),
readmode => ReadUARTTModeReg(i),
fifoempty => UARTTFIFOEmpty(i),
txen => '1',
drven => UTDrvEn(i),
txdata => UTData(i)
);
end generate;
LEDReg : entity boutreg
generic map (
size => LEDCount,
buswidth => LEDCount,
invert => true)
port map (
clk => clklow,
ibus => ibus(BusWidth-1 downto BusWidth-LEDCount),
obus => obus(BusWidth-1 downto BusWidth-LEDCount),
load => LoadLEDs,
read => '0',
clear => '0',
dout => LEDS
);
IDROMWP : entity boutreg
generic map (
size => 1,
buswidth => BusWidth,
invert => false
)
port map (
clk => clklow,
ibus => ibus,
obus => obus,
load => LoadIDROMWEn,
read => ReadIDROMWEn,
clear => '0',
dout => IDROMWen
);
IDROM : entity IDROM
generic map (
idromtype => IDROMType,
offsettomodules => OffsetToModules,
offsettopindesc => OffsetToPinDesc,
boardnamelow => BoardNameLow,
boardnameHigh => BoardNameHigh,
fpgasize => FPGASize,
fpgapins => FPGAPins,
ioports => IOPorts,
iowidth => IOWidth,
portwidth => PortWidth,
clocklow => ClockLow,
clockhigh => ClockHigh,
inststride0 => InstStride0,
inststride1 => InstStride1,
regstride0 => RegStride0,
regstride1 => RegStride1,
pindesc => ThePinDesc,
moduleid => TheModuleID)
port map (
clk => clklow,
we => LoadIDROM,
re => ReadIDROM,
radd => addr(9 downto 2),
wadd => A(9 downto 2),
din => ibus,
dout => obus
);
DoPinout: process(PWMGenOutA,PWMGenOutB,PWMGenOutC,StepGenOut,SPIFrame,SPIOut,SPIClk,
UTData,UTDrvEn,BSPIFrame,BSPIOut,BSPIClk,BSPICS,DBSPIOut,DBSPIClk,
DBSPICS,IOBits)
begin
Altdata <= (others => '0');
for i in 0 to IOWidth -1 loop
case ThePinDesc(i)(15 downto 8) is -- GTag
-- all these nasty subranges will go away when pindescs are changed to records
when QCountTag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function
when QCountQAPin =>
QuadA(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when QCountQBPin =>
QuadB(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when QCountIdxPin =>
Index(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when QCountIdxMaskPin =>
IndexMask(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when others => null;
end case;
when MuxedQCountTag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function
when MuxedQCountQAPin =>
MuxedQuadA(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when MuxedQCountQBPin =>
MuxedQuadB(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when MuxedQCountIdxPin =>
MuxedIndex(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when MuxedQCountIdxMaskPin =>
MuxedIndexMask(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when others => null;
end case;
when MuxedQCountSelTag =>
case(ThePinDesc(i)(7 downto 0)) is --secondary pin function
when MuxedQCountSel0Pin =>
AltData(i) <= MuxedQCtrSel(0);
when MuxedQCountSel1Pin =>
AltData(i) <= MuxedQCtrSel(1);
when others => null;
end case;
when PWMTag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function
when PWMAOutPin =>
AltData(i) <= PWMGENOutA(conv_integer(ThePinDesc(i)(23 downto 16)));
when PWMBDirPin =>
AltData(i) <= PWMGENOutB(conv_integer(ThePinDesc(i)(23 downto 16)));
when PWMCEnaPin =>
AltData(i) <= PWMGENOutC(conv_integer(ThePinDesc(i)(23 downto 16)));
when others => null;
end case;
when StepGenTag =>
AltData(i) <= StepGenOut(conv_integer(ThePinDesc(i)(23 downto 16)))(conv_integer(ThePinDesc(i)(6 downto 0))-1);
when UARTTTag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function
when UTDataPin =>
AltData(i) <= UTData(conv_integer(ThePinDesc(i)(23 downto 16)));
when UTDrvEnPin =>
AltData(i) <= UTDrvEn(conv_integer(ThePinDesc(i)(23 downto 16)));
when others => null;
end case;
when UARTRTag =>
if (ThePinDesc(i)(7 downto 0)) = URDataPin then
URData(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
end if;
when SPITag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function, drop MSB
when SPIFramePin =>
AltData(i) <= SPIFrame(conv_integer(ThePinDesc(i)(23 downto 16)));
when SPIOutPin =>
AltData(i) <= SPIOut(conv_integer(ThePinDesc(i)(23 downto 16)));
when SPIClkPin =>
AltData(i) <= SPIClk(conv_integer(ThePinDesc(i)(23 downto 16)));
when SPIInPin =>
SPIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when others => null;
end case;
when BSPITag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function, drop MSB
when BSPIFramePin =>
AltData(i) <= BSPIFrame(conv_integer(ThePinDesc(i)(23 downto 16)));
when BSPIOutPin =>
AltData(i) <= BSPIOut(conv_integer(ThePinDesc(i)(23 downto 16)));
when BSPIClkPin =>
AltData(i) <= BSPIClk(conv_integer(ThePinDesc(i)(23 downto 16)));
when BSPIInPin =>
BSPIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when others => AltData(i) <= BSPICS(conv_integer(ThePinDesc(i)(23 downto 16)))(conv_integer(ThePinDesc(i)(6 downto 0))-5);
-- magic foo, magic foo, what on earth does it do?
-- (this needs to written more clearly!)
end case;
when DBSPITag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function, drop MSB
when DBSPIOutPin =>
AltData(i) <= DBSPIOut(conv_integer(ThePinDesc(i)(23 downto 16)));
when DBSPIClkPin =>
AltData(i) <= DBSPIClk(conv_integer(ThePinDesc(i)(23 downto 16)));
when DBSPIInPin =>
DBSPIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when others => AltData(i) <= DBSPICS(conv_integer(ThePinDesc(i)(23 downto 16)))(conv_integer(ThePinDesc(i)(6 downto 0))-5);
-- magic foo, magic foo, what on earth does it do?
-- (this needs to written more clearly!)
end case;
when SSSITag =>
case (ThePinDesc(i)(7 downto 0)) is --secondary pin function, drop MSB
when SSSIClkPin =>
AltData(i) <= SSSIClk(conv_integer(ThePinDesc(i)(23 downto 16)));
when SSSIInPin =>
SSSIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBits(i);
when others => null;
end case;
when others => null;
end case;
end loop;
end process;
LooseEnds: process(A,clklow)
begin
if rising_edge(clklow) then
A <= addr;
end if;
end process;
MuxedEnc: if MuxedQCounters > 0 generate
EncoderDeMux: process(clklow)
begin
if rising_edge(clklow) then
if MuxedQCountFilterRate = '1' then
PreMuxedQCtrSel <= PreMuxedQCtrSel + 1;
end if;
MuxedQCtrSel <= PreMuxedQCtrSel;
for i in 0 to ((MuxedQCounters/2) -1) loop -- just 2 deep for now
if PreMuxedQCtrSel(0) = '1' and MuxedQCtrSel(0) = '0' then -- latch the even inputs
DeMuxedQuadA(2*i) <= MuxedQuadA(i);
DeMuxedQuadB(2*i) <= MuxedQuadB(i);
DeMuxedIndex(2*i) <= MuxedIndex(i);
end if;
if PreMuxedQCtrSel(0) = '0' and MuxedQCtrSel(0) = '1' then -- latch the odd inputs
DeMuxedQuadA(2*i+1) <= MuxedQuadA(i);
DeMuxedQuadB(2*i+1) <= MuxedQuadB(i);
DeMuxedIndex(2*i+1) <= MuxedIndex(i);
end if;
end loop;
end if; -- clk
end process;
end generate;
MuxedEncMIM: if MuxedQCountersMIM > 0 generate
EncoderDeMuxMIM: process(clklow)
begin
if rising_edge(clklow) then
if MuxedQCountFilterRate = '1' then
PreMuxedQCtrSel <= PreMuxedQCtrSel + 1;
end if;
MuxedQCtrSel <= PreMuxedQCtrSel;
for i in 0 to ((MuxedQCounters/2) -1) loop -- just 2 deep for now
if PreMuxedQCtrSel(0) = '1' and MuxedQCtrSel(0) = '0' then -- latch the even inputs
DeMuxedQuadA(2*i) <= MuxedQuadA(i);
DeMuxedQuadB(2*i) <= MuxedQuadB(i);
DeMuxedIndex(2*i) <= MuxedIndex(i);
DeMuxedIndexMask(2*i) <= MuxedIndexMask(i);
end if;
if PreMuxedQCtrSel(0) = '0' and MuxedQCtrSel(0) = '1' then -- latch the odd inputs
DeMuxedQuadA(2*i+1) <= MuxedQuadA(i);
DeMuxedQuadB(2*i+1) <= MuxedQuadB(i);
DeMuxedIndex(2*i+1) <= MuxedIndex(i);
DeMuxedIndexMask(2*i+1) <= MuxedIndexMask(i);
end if;
end loop;
end if; -- clk
end process;
end generate;
Decode: process(A,write, IDROMWEn, read)
begin
-- basic multi decodes are at 256 byte increments (64 longs)
-- first decode is 256 x 32 ID ROM
if (A(15 downto 10) = IDROMAddr(7 downto 2)) and Write = '1' and IDROMWEn = "1" then -- 400 Hex
LoadIDROM <= '1';
else
LoadIDROM <= '0';
end if;
if (A(15 downto 10) = IDROMAddr(7 downto 2)) and Read = '1' then --
ReadIDROM <= '1';
else
ReadIDROM <= '0';
end if;
if A(15 downto 8) = PortAddr then -- basic I/O port select
PortSel <= '1';
else
PortSel <= '0';
end if;
if A(15 downto 8) = DDRAddr then -- DDR register select
DDRSel <= '1';
else
DDRSel <= '0';
end if;
if A(15 downto 8) = AltDataSrcAddr then -- Alt data source register select
AltDataSrcSel <= '1';
else
AltDataSrcSel <= '0';
end if;
if A(15 downto 8) = OpenDrainModeAddr then -- OpenDrain register select
OpendrainModeSel <= '1';
else
OpenDrainModeSel <= '0';
end if;
if A(15 downto 8) = OutputInvAddr then -- IO invert register select
OutputInvSel <= '1';
else
OutputInvSel <= '0';
end if;
if A(15 downto 8) = StepGenRateAddr then -- stepgen rate register select
StepGenRateSel <= '1';
else
StepGenRateSel <= '0';
end if;
if A(15 downto 8) = StepGenAccumAddr then -- stepgen Accumumlator low select
StepGenAccumSel <= '1';
else
StepGenAccumSel <= '0';
end if;
if A(15 downto 8) = StepGenModeAddr then -- stepgen mode register select
StepGenModeSel <= '1';
else
StepGenModeSel <= '0';
end if;
if A(15 downto 8) = StepGenDSUTimeAddr then -- stepgen Dir setup time register select
StepGenDSUTimeSel <= '1';
else
StepGenDSUTimeSel <= '0';
end if;
if A(15 downto 8) =StepGenDHLDTimeAddr then -- stepgen Dir hold time register select
StepGenDHLDTimeSel <= '1';
else
StepGenDHLDTimeSel <= '0';
end if;
if A(15 downto 8) = StepGenPulseATimeAddr then -- stepgen pulse width register select
StepGenPulseATimeSel <= '1';
else
StepGenPulseATimeSel <= '0';
end if;
if A(15 downto 8) = StepGenPulseITimeAddr then -- stepgen pulse width register select
StepGenPulseITimeSel <= '1';
else
StepGenPulseITimeSel <= '0';
end if;
if A(15 downto 8) = StepGenTableAddr then -- stepgen pulse width register select
StepGenTableSel <= '1';
else
StepGenTableSel <= '0';
end if;
if A(15 downto 8) = StepGenTableMaxAddr then -- stepgen pulse width register select
StepGenTableMaxSel <= '1';
else
StepGenTableMaxSel <= '0';
end if;
if A(15 downto 8) = QCounterAddr then -- QCounter select
QCounterSel <= '1';
else
QCounterSel <= '0';
end if;
if A(15 downto 8) = QCounterCCRAddr then -- QCounter CCR register select
QCounterCCRSel <= '1';
else
QCounterCCRSel <= '0';
end if;
if A(15 downto 8) = MuxedQCounterAddr then -- QCounter select
MuxedQCounterSel <= '1';
else
MuxedQCounterSel <= '0';
end if;
if A(15 downto 8) = MuxedQCounterCCRAddr then -- QCounter CCR register select
MuxedQCounterCCRSel <= '1';
else
MuxedQCounterCCRSel <= '0';
end if;
if A(15 downto 8) = PWMValAddr then -- PWMVal select
PWMValSel <= '1';
else
PWMValSel <= '0';
end if;
if A(15 downto 8) = PWMCRAddr then -- PWM mode register select
PWMCRSel <= '1';
else
PWMCRSel <= '0';
end if;
if A(15 downto 8) = SPIDataAddr then -- SPI data register select
SPIDataSel <= '1';
else
SPIDataSel <= '0';
end if;
if A(15 downto 8) = SPIBitCountAddr then -- SPI bit count register select
SPIBitCountSel <= '1';
else
SPIBitCountSel <= '0';
end if;
if A(15 downto 8) = SPIBitrateAddr then -- SPI bit rate register select
SPIBitrateSel <= '1';
else
SPIBitrateSel <= '0';
end if;
if A(15 downto 8) = SSSIDataAddr then -- SSSI data register select
SSSIDataSel <= '1';
else
SSSIDataSel <= '0';
end if;
if A(15 downto 8) = SSSIBitCountAddr then -- SSSI bit count register select
SSSIBitCountSel <= '1';
else
SSSIBitCountSel <= '0';
end if;
if A(15 downto 8) = SSSIBitrateAddr then -- SSSI bit rate register select
SSSIBitrateSel <= '1';
else
SSSIBitrateSel <= '0';
end if;
if A(15 downto 8) = BSPIDataAddr then -- BSPI data register select
BSPIDataSel <= '1';
else
BSPIDataSel <= '0';
end if;
if A(15 downto 8) = BSPIFIFOCountAddr then -- BSPI FIFO count register select
BSPIFIFOCountSel <= '1';
else
BSPIFIFOCountSel <= '0';
end if;
if A(15 downto 8) = BSPIDescriptorAddr then -- BSPI channel descriptor register select
BSPIDescriptorSel <= '1';
else
BSPIDescriptorSel <= '0';
end if;
if A(15 downto 8) = DBSPIDataAddr then -- DBSPI data register select
DBSPIDataSel <= '1';
else
DBSPIDataSel <= '0';
end if;
if A(15 downto 8) = DBSPIFIFOCountAddr then -- DBSPI FIFO count register select
DBSPIFIFOCountSel <= '1';
else
DBSPIFIFOCountSel <= '0';
end if;
if A(15 downto 8) = DBSPIDescriptorAddr then -- DBSPI channel descriptor register select
DBSPIDescriptorSel <= '1';
else
DBSPIDescriptorSel <= '0';
end if;
if A(15 downto 8) = UARTTDataAddr then -- UART TX data register select
UARTTDataSel <= '1';
else
UARTTDataSel <= '0';
end if;
if A(15 downto 8) = UARTTFIFOCountAddr then -- UART TX FIFO count register select
UARTTFIFOCountSel <= '1';
else
UARTTFIFOCountSel <= '0';
end if;
if A(15 downto 8) = UARTTBitrateAddr then -- UART TX bit rate register select
UARTTBitrateSel <= '1';
else
UARTTBitrateSel <= '0';
end if;
if A(15 downto 8) = UARTTModeRegAddr then -- UART TX bit mode register select
UARTTModeRegSel <= '1';
else
UARTTModeRegSel <= '0';
end if;
if A(15 downto 8) = UARTRDataAddr then -- UART RX data register select
UARTRDataSel <= '1';
else
UARTRDataSel <= '0';
end if;
if A(15 downto 8) = UARTRFIFOCountAddr then -- UART RX FIFO count register select
UARTRFIFOCountSel <= '1';
else
UARTRFIFOCountSel <= '0';
end if;
if A(15 downto 8) = UARTRBitrateAddr then -- UART RX bit rate register select
UARTRBitrateSel <= '1';
else
UARTRBitrateSel <= '0';
end if;
if A(15 downto 8) = UARTRModeRegAddr then -- UART RX status register select
UARTRModeRegSel <= '1';
else
UARTRModeRegSel <= '0';
end if;
if A(15 downto 8) = ReadIDAddr and Read = '1' then --
ReadID <= '1';
else
ReadID <= '0';
end if;
if A(15 downto 8) = WatchdogTimeAddr and Read = '1' then --
ReadWDTime <= '1';
else
ReadWDTime <= '0';
end if;
if A(15 downto 8) = WatchdogTimeAddr and Write = '1' then --
LoadWDTime <= '1';
else
LoadWDTime <= '0';
end if;
if A(15 downto 8) = WatchdogStatusAddr and Read = '1' then --
ReadWDStatus <= '1';
else
ReadWDStatus <= '0';
end if;
if A(15 downto 8) = WatchdogStatusAddr and Write = '1' then --
LoadWDStatus <= '1';
else
LoadWDStatus <= '0';
end if;
if A(15 downto 8) = WatchdogCookieAddr and Write = '1' then --
WDCookie <= '1';
else
WDCookie <= '0';
end if;
if A(15 downto 8) = IRQDivAddr and Write = '1' then --
LoadIRQDiv <= '1';
else
LoadIRQDiv <= '0';
end if;
if A(15 downto 8) = IRQDivAddr and Read = '1' then --
ReadIRQDiv <= '1';
else
ReadIRQDiv <= '0';
end if;
if A(15 downto 8) = IRQStatusAddr and Write = '1' then --
LoadIRQStatus <= '1';
else
LoadIRQStatus <= '0';
end if;
if A(15 downto 8) = IRQStatusAddr and Read = '1' then --
ReadIrqStatus <= '1';
else
ReadIrqStatus <= '0';
end if;
if A(15 downto 8) = ClearIRQAddr and Write = '1' then --
ClearIRQ <= '1';
else
ClearIRQ <= '0';
end if;
if A(15 downto 8) = StepGenBasicRateAddr and Write = '1' then --
LoadStepGenBasicRate <= '1';
else
LoadStepGenBasicRate <= '0';
end if;
if A(15 downto 8) = StepGenBasicRateAddr and Read = '1' then --
ReadStepGenBasicRate <= '1';
else
ReadStepGenBasicRate <= '0';
end if;
if A(15 downto 8) = TSDivAddr and Write = '1' then --
LoadTSDiv <= '1';
else
LoadTSDiv <= '0';
end if;
if A(15 downto 8) = TSDivAddr and Read = '1' then --
ReadTSDiv <= '1';
else
ReadTSDiv <= '0';
end if;
if A(15 downto 8) = TSAddr and Read = '1' then --
ReadTS <= '1';
else
ReadTS <= '0';
end if;
if A(15 downto 8) = QCRateAddr and Write = '1' then --
LoadQCountRate <= '1';
else
LoadQCountRate <= '0';
end if;
if A(15 downto 8) = MuxedTSDivAddr and Write = '1' then --
LoadMuxedTSDiv <= '1';
else
LoadMuxedTSDiv <= '0';
end if;
if A(15 downto 8) = MuxedTSDivAddr and Read = '1' then --
ReadMuxedTSDiv <= '1';
else
ReadMuxedTSDiv <= '0';
end if;
if A(15 downto 8) = MuxedTSAddr and Read = '1' then --
ReadMuxedTS <= '1';
else
ReadMuxedTS <= '0';
end if;
if A(15 downto 8) = MuxedQCRateAddr and Write = '1' then --
LoadMuxedQCountRate <= '1';
else
LoadMuxedQCountRate <= '0';
end if;
if A(15 downto 8) = PWMRateAddr and Write = '1' then --
LoadPWMRate <= '1';
else
LoadPWMRate <= '0';
end if;
if A(15 downto 8) = PDMRateAddr and Write = '1' then --
LoadPDMRate <= '1';
else
LoadPDMRate <= '0';
end if;
if A(15 downto 8) = PWMEnasAddr and Write = '1' then --
LoadPWMEnas <= '1';
else
LoadPWMEnas <= '0';
end if;
if A(15 downto 8) = PWMEnasAddr and Read = '1' then --
ReadPWMEnas <= '1';
else
ReadPWMEnas <= '0';
end if;
if A(15 downto 8) = SSSIGlobalPStartAddr and Write = '1' then --
GlobalPStartSSSI <= '1';
else
GlobalPStartSSSI <= '0';
end if;
if A(15 downto 8) = IDROMWEnAddr and Write = '1' then --
LoadIDROMWEn <= '1';
else
LoadIDROMWEn <= '0';
end if;
if A(15 downto 8) = IDROMWEnAddr and Read = '1' then --
ReadIDROMWEn <= '1';
else
ReadIDROMWEn <= '0';
end if;
if A(15 downto 8) = LEDAddr and Write = '1' then --
LoadLEDs <= '1';
else
LoadLEDs <= '0';
end if;
end process;
PortDecode: process (A,Read,Write,PortSel, DDRSel, AltDataSrcSel, OpenDrainModeSel, OutputInvSel)
begin
LoadPortCMD <= OneOfNDecode(IOPorts,PortSel,Write,A(3 downto 2)); -- 4 max
ReadPortCMD <= OneOfNDecode(IOPorts,PortSel,Read,A(3 downto 2));
LoadDDRCMD <= OneOfNDecode(IOPorts,DDRSel,Write,A(3 downto 2));
ReadDDRCMD <= OneOfNDecode(IOPorts,DDRSel,Read,A(3 downto 2));
LoadAltDataSrcCMD <= OneOfNDecode(IOPorts,AltDataSrcSel,Write,A(3 downto 2));
LoadOpenDrainModeCMD <= OneOfNDecode(IOPorts,OpenDrainModeSel,Write,A(3 downto 2));
LoadOutputInvCMD <= OneOfNDecode(IOPorts,OutputInvSel,Write,A(3 downto 2));
end process PortDecode;
StepGenDecode: if (STEPGENs > 0) generate
StepGenDecodeProcess : process (A,Read,write,StepGenRateSel, StepGenAccumSel, StepGenModeSel,
StepGenDSUTimeSel, StepGenDHLDTimeSel, StepGenPulseATimeSel,
StepGenPulseITimeSel, StepGenTableSel, StepGenTableMaxSel)
begin
LoadStepGenRate <= OneOfNDecode(STEPGENs,StepGenRateSel,Write,A(6 downto 2)); -- 32 max
ReadStepGenRate <= OneOfNDecode(STEPGENs,StepGenRateSel,Read,A(6 downto 2));
LoadStepGenAccum <= OneOfNDecode(STEPGENs,StepGenAccumSel,Write,A(6 downto 2));
ReadStepGenAccum <= OneOfNDecode(STEPGENs,StepGenAccumSel,Read,A(6 downto 2));
LoadStepGenMode <= OneOfNDecode(STEPGENs,StepGenModeSel,Write,A(6 downto 2));
ReadStepGenMode <= OneOfNDecode(STEPGENs,StepGenModeSel,Read,A(6 downto 2));
LoadStepGenDSUTime <= OneOfNDecode(STEPGENs,StepGenDSUTimeSel,Write,A(6 downto 2));
ReadStepGenDSUTime <= OneOfNDecode(STEPGENs,StepGenDSUTimeSel,Read,A(6 downto 2));
LoadStepGenDHLDTime <= OneOfNDecode(STEPGENs,StepGenDHLDTimeSel,Write,A(6 downto 2));
ReadStepGenDHLDTime <= OneOfNDecode(STEPGENs,StepGenDHLDTimeSel,Read,A(6 downto 2));
LoadStepGenPulseATime <= OneOfNDecode(STEPGENs,StepGenPulseATimeSel,Write,A(6 downto 2));
ReadStepGenPulseATime <= OneOfNDecode(STEPGENs,StepGenPulseATimeSel,Read,A(6 downto 2));
LoadStepGenPulseITime <= OneOfNDecode(STEPGENs,StepGenPulseITimeSel,Write,A(6 downto 2));
ReadStepGenPulseITime <= OneOfNDecode(STEPGENs,StepGenPulseITimeSel,Read,A(6 downto 2));
LoadStepGenTable <= OneOfNDecode(STEPGENs,StepGenTableSel,Write,A(6 downto 2));
ReadStepGenTable <= OneOfNDecode(STEPGENs,StepGenTableSel,Read,A(6 downto 2));
LoadStepGenTableMax <= OneOfNDecode(STEPGENs,StepGenTableMaxSel,Write,A(6 downto 2));
ReadStepGenTableMax <= OneOfNDecode(STEPGENs,StepGenTableMaxSel,Read,A(6 downto 2));
end process StepGenDecodeProcess;
end generate;
QCounterDecode: if (QCounters > 0) generate
QCounterDecodeProcess : process (A,Read,write,QCounterSel, QCounterCCRSel)
begin
LoadQCounter <= OneOfNDecode(QCounters,QCounterSel,Write,A(6 downto 2)); -- 32 max
ReadQCounter <= OneOfNDecode(QCounters,QCounterSel,Read,A(6 downto 2));
LoadQCounterCCR <= OneOfNDecode(QCounters,QCounterCCRSel,Write,A(6 downto 2));
ReadQCounterCCR <= OneOfNDecode(QCounters,QCounterCCRSel,Read,A(6 downto 2));
end process QCounterDecodeProcess;
end generate;
MuxedQCounterDecode: if (MuxedQcounters > 0) generate
MuxedQCounterDecodeProcess : process (A,Read,write,MuxedQCounterSel, MuxedQCounterCCRSel)
begin
LoadMuxedQCounter <= OneOfNDecode(MuxedQCounters,MuxedQCounterSel,Write,A(6 downto 2)); -- 32 max
ReadMuxedQCounter <= OneOfNDecode(MuxedQCounters,MuxedQCounterSel,Read,A(6 downto 2));
LoadMuxedQCounterCCR <= OneOfNDecode(MuxedQCounters,MuxedQCounterCCRSel,Write,A(6 downto 2));
ReadMuxedQCounterCCR <= OneOfNDecode(MuxedQCounters,MuxedQCounterCCRSel,Read,A(6 downto 2));
end process MuxedQCounterDecodeProcess;
end generate;
PWMDecode: if (PWMGENs > 0) generate
PWMDecodeProcess : process (A,Read,write,PWMValSel, PWMCRSel)
begin
LoadPWMVal <= OneOfNDecode(PWMGENs,PWMValSel,Write,A(6 downto 2)); -- 32 max
LoadPWMCR <= OneOfNDecode(PWMGENs, PWMCRSel,Write,A(6 downto 2));
end process PWMDecodeProcess;
end generate;
SPIDecode: if (SPIs > 0) generate
SPIDecodeProcess : process (A,Read,write,SPIDataSel,SPIBitCountSel,SPIBitRateSel)
begin
LoadSPIData <= OneOfNDecode(SPIs,SPIDataSel,Write,A(5 downto 2)); -- 16 max
ReadSPIData <= OneOfNDecode(SPIs,SPIDataSel,Read,A(5 downto 2));
LoadSPIBitCount <= OneOfNDecode(SPIs,SPIBitCountSel,Write,A(5 downto 2));
ReadSPIBitCount <= OneOfNDecode(SPIs,SPIBitCountSel,Read,A(5 downto 2));
LoadSPIBitRate <= OneOfNDecode(SPIs,SPIBitRateSel,Write,A(5 downto 2));
ReadSPIBitRate <= OneOfNDecode(SPIs,SPIBitRateSel,Read,A(5 downto 2));
end process SPIDecodeProcess;
end generate;
BSPIDecode: if (BSPIs > 0) generate
BSPIDecodeProcess : process (A,Read,write,BSPIDataSel,BSPIFIFOCountSel,BSPIDescriptorSel)
begin
LoadBSPIData <= OneOfNDecode(BSPIs,BSPIDataSel,Write,A(7 downto 6)); -- 4 max
ReadBSPIData <= OneOfNDecode(BSPIs,BSPIDataSel,Read,A(7 downto 6));
LoadBSPIDescriptor<= OneOfNDecode(BSPIs,BSPIDescriptorSel,Write,A(5 downto 2));
ReadBSPIFIFOCOunt <= OneOfNDecode(BSPIs,BSPIFIFOCountSel,Read,A(5 downto 2));
ClearBSPIFIFO <= OneOfNDecode(BSPIs,BSPIFIFOCountSel,Write,A(5 downto 2));
end process BSPIDecodeProcess;
end generate;
DBSPIDecode: if (DBSPIs > 0) generate
DBSPIDecodeProcess : process (A,Read,write,DBSPIDataSel,DBSPIFIFOCountSel,DBSPIDescriptorSel)
begin
LoadDBSPIData <= OneOfNDecode(DBSPIs,DBSPIDataSel,Write,A(7 downto 6)); -- 4 max
ReadDBSPIData <= OneOfNDecode(DBSPIs,DBSPIDataSel,Read,A(7 downto 6));
LoadDBSPIDescriptor<= OneOfNDecode(DBSPIs,DBSPIDescriptorSel,Write,A(5 downto 2));
ReadDBSPIFIFOCOunt <= OneOfNDecode(DBSPIs,DBSPIFIFOCountSel,Read,A(5 downto 2));
ClearDBSPIFIFO <= OneOfNDecode(DBSPIs,DBSPIFIFOCountSel,Write,A(5 downto 2));
end process DBSPIDecodeProcess;
end generate;
SSSIDecode: if (SSSIs > 0) generate
SSSIDecodeProcess : process (A,Read,write,SSSIDataSel,SSSIBitCountSel,SSSIBitRateSel)
begin
LoadSSSIData <= OneOfNDecode(SSSIs,SSSIDataSel,Write,A(5 downto 2));
ReadSSSIData <= OneOfNDecode(SSSIs,SSSIDataSel,Read,A(5 downto 2));
LoadSSSIBitCount <= OneOfNDecode(SSSIs,SSSIBitCountSel,Write,A(5 downto 2));
ReadSSSIBitCount <= OneOfNDecode(SSSIs,SSSIBitCountSel,Read,A(5 downto 2));
LoadSSSIBitRate <= OneOfNDecode(SSSIs,SSSIBitRateSel,Write,A(5 downto 2));
ReadSSSIBitRate <= OneOfNDecode(SSSIs,SSSIBitRateSel,Read,A(5 downto 2));
end process SSSIDecodeProcess;
end generate;
UARTDecode: if (UARTs > 0) generate
UARTDecodeProcess : process (A,Read,write,UARTTDataSel,UARTTBitRateSel,UARTTModeRegSel,UARTTFIFOCountSel,
UARTRDataSel,UARTRBitRateSel,UARTRFIFOCountSel,UARTRModeRegSel)
begin
LoadUARTTData <= OneOfNDecode(UARTs,UARTTDataSel,Write,A(6 downto 4));
LoadUARTTBitRate <= OneOfNDecode(UARTs,UARTTBitRateSel,Write,A(4 downto 2));
ReadUARTTBitrate <= OneOfNDecode(UARTs,UARTTBitRateSel,Read,A(4 downto 2));
LoadUARTTModeReg <= OneOfNDecode(UARTs,UARTTModeRegSel,Write,A(4 downto 2));
ReadUARTTModeReg <= OneOfNDecode(UARTs,UARTTModeRegSel,Read,A(4 downto 2));
ClearUARTTFIFO <= OneOfNDecode(UARTs,UARTTFIFOCountSel,Write,A(4 downto 2));
ReadUARTTFIFOCount <= OneOfNDecode(UARTs,UARTTFIFOCountSel,Read,A(4 downto 2));
LoadUARTRData <= OneOfNDecode(UARTs,UARTRDataSel,Read,A(6 downto 4));
LoadUARTRBitRate <= OneOfNDecode(UARTs,UARTRBitRateSel,Write,A(4 downto 2));
ReadUARTRBitrate <= OneOfNDecode(UARTs,UARTRBitRateSel,Read,A(4 downto 2));
ClearUARTRFIFO <= OneOfNDecode(UARTs,UARTRFIFOCountSel,Write,A(4 downto 2));
ReadUARTRFIFOCount <= OneOfNDecode(UARTs,UARTRFIFOCountSel,Read,A(4 downto 2));
LoadUARTRModeReg <= OneOfNDecode(UARTs,UARTRModeRegSel,Write,A(4 downto 2));
ReadUARTRModeReg <= OneOfNDecode(UARTs,UARTRModeRegSel,Read,A(4 downto 2));
end process UARTDecodeProcess;
end generate;
dotieupint: if not UseIRQLogic generate
tieupint : process(clklow)
begin
INT <= '1';
end process;
end generate;
end dataflow;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity vga_demo is
port(
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0);
VGA_HS : out std_logic;
VGA_VS : out std_logic;
VGA_BLANK : out std_logic;
VGA_SYNC : out std_logic;
VGA_CLK : out std_logic
);
end vga_demo;
architecture rtl of vga_demo is
component vga_adapter ---- Component from the Verilog file: vga_adapter.v
generic(
RESOLUTION : string
);
port (
resetn : in std_logic;
clock : in std_logic;
colour : in std_logic_vector(2 downto 0);
x : in std_logic_vector(7 downto 0);
y : in std_logic_vector(6 downto 0);
plot : in std_logic;
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0);
VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic
);
end component;
signal resetn : std_logic;
signal x : std_logic_vector(7 downto 0);
signal y : std_logic_vector(6 downto 0);
signal colour : std_logic_vector(2 downto 0);
signal plot : std_logic;
begin
resetn <= KEY(3);
x <= SW(7 downto 0);
y <= SW(14 downto 8);
colour <= SW(17 downto 15);
plot <= not KEY(0);
vga_u0 : vga_adapter
generic map(
RESOLUTION => "160x120"
) ---- Sets the resolution of display (as per vga_adapter.v description)
port map(
resetn => resetn,
clock => CLOCK_50,
colour => colour,
x => x,
y => y,
plot => plot,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HS => VGA_HS,
VGA_VS => VGA_VS,
VGA_BLANK => VGA_BLANK,
VGA_SYNC => VGA_SYNC,
VGA_CLK => VGA_CLK
);
end rtl;
|
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc316.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b00x00p03n02i00316ent IS
END c03s02b00x00p03n02i00316ent;
ARCHITECTURE c03s02b00x00p03n02i00316arch OF c03s02b00x00p03n02i00316ent IS
type FT is file of integer;
type rec_type is
record
x : bit;
y : integer;
z : FT; -- Failure_here
end record;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b00x00p03n02i00316 - Elements of file types are not allowed in a composite type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b00x00p03n02i00316arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc316.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b00x00p03n02i00316ent IS
END c03s02b00x00p03n02i00316ent;
ARCHITECTURE c03s02b00x00p03n02i00316arch OF c03s02b00x00p03n02i00316ent IS
type FT is file of integer;
type rec_type is
record
x : bit;
y : integer;
z : FT; -- Failure_here
end record;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b00x00p03n02i00316 - Elements of file types are not allowed in a composite type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b00x00p03n02i00316arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc316.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b00x00p03n02i00316ent IS
END c03s02b00x00p03n02i00316ent;
ARCHITECTURE c03s02b00x00p03n02i00316arch OF c03s02b00x00p03n02i00316ent IS
type FT is file of integer;
type rec_type is
record
x : bit;
y : integer;
z : FT; -- Failure_here
end record;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b00x00p03n02i00316 - Elements of file types are not allowed in a composite type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b00x00p03n02i00316arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutlb
-- File: mmutlb.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU TLB logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmutlb is
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 1;
mmupgsz : integer range 0 to 5 := 0;
scantest : integer := 0;
ramcbits: integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end mmutlb;
architecture rtl of mmutlb is
constant M_TLB_FASTWRITE : integer range 0 to 3 :=
conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant entries_log : integer := log2(entries);
constant entries_max : std_logic_vector(entries_log-1 downto 0) :=
conv_std_logic_vector(entries-1, entries_log);
type states is (idle, match, walk, pack, flush, sync, diag, dofault);
type tlb_rtype is record
s2_tlbstate : states;
s2_entry : std_logic_vector(entries_log-1 downto 0);
s2_hm : std_logic;
s2_needsync : std_logic;
s2_data : std_logic_vector(31 downto 0);
s2_isid : mmu_idcache;
s2_su : std_logic;
s2_read : std_logic;
s2_flush : std_logic;
s2_ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
walk_use : std_logic;
walk_transdata : mmuidc_data_out_type;
walk_fault : mmutlbfault_out_type;
nrep : std_logic_vector(entries_log-1 downto 0);
tpos : std_logic_vector(entries_log-1 downto 0);
touch : std_logic;
sync_isw : std_logic;
tlbmiss : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RRES : tlb_rtype := (
s2_tlbstate => idle,
s2_entry => (others => '0'),
s2_hm => '0',
s2_needsync => '0',
s2_data => (others => '0'),
s2_isid => id_icache,
s2_su => '0',
s2_read => '0',
s2_flush => '0',
s2_ctx => (others => '0'),
walk_use => '0',
walk_transdata => mmuidco_zero,
walk_fault => mmutlbfault_out_zero,
nrep => (others => '0'),
tpos => (others => '0'),
touch => '0',
sync_isw => '0',
tlbmiss => '0');
signal c,r : tlb_rtype;
-- tlb cams
component mmutlbcam
generic (
tlb_type : integer range 0 to 3 := 1;
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
tlbcami : in mmutlbcam_in_type;
tlbcamo : out mmutlbcam_out_type
);
end component;
signal tlbcami : mmutlbcami_a (entries-1 downto 0);
signal tlbcamo : mmutlbcamo_a (entries-1 downto 0);
-- least recently used
component mmulru
generic (
entries : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
lrui : in mmulru_in_type;
lruo : out mmulru_out_type
);
end component;
signal lrui : mmulru_in_type;
signal lruo : mmulru_out_type;
-- data-ram syncram signals
signal dr1_addr : std_logic_vector(entries_log-1 downto 0);
signal dr1_datain : std_logic_vector(29 downto 0);
signal dr1_dataout : std_logic_vector(29 downto 0);
signal dr1_enable : std_logic;
signal dr1_write : std_logic;
begin
p0: process (rst, r, tlbi, two, tlbcamo, dr1_dataout, lruo)
variable v : tlb_rtype;
variable finish, selstate : std_logic;
variable cam_hitaddr : std_logic_vector(entries_log-1 downto 0);
variable cam_hit_all : std_logic;
variable mtag,ftag : tlbcam_tfp;
-- tlb cam input
variable tlbcam_trans_op : std_logic;
variable tlbcam_write_op : std_logic_vector(entries-1 downto 0);
variable tlbcam_flush_op : std_logic;
-- tw inputs
variable twi_walk_op_ur : std_logic;
variable twi_data : std_logic_vector(31 downto 0);
variable twi_areq_ur : std_logic;
variable twi_aaddr : std_logic_vector(31 downto 0);
variable twi_adata : std_logic_vector(31 downto 0);
variable two_error : std_logic;
-- lru inputs
variable lrui_touch : std_logic;
variable lrui_touchmin : std_logic;
variable lrui_pos : std_logic_vector(entries_log-1 downto 0);
-- syncram inputs
variable dr1write : std_logic;
-- hit tlbcam's output
variable ACC : std_logic_vector(2 downto 0);
variable PTE : std_logic_vector(31 downto 0);
variable LVL : std_logic_vector(1 downto 0);
variable CAC : std_logic;
variable NEEDSYNC : std_logic;
-- wb hit tlbcam's output
variable wb_i_entry : integer range 0 to entries-1;
variable wb_ACC : std_logic_vector(2 downto 0);
variable wb_PTE : std_logic_vector(31 downto 0);
variable wb_LVL : std_logic_vector(1 downto 0);
variable wb_CAC : std_logic;
variable wb_fault_pro, wb_fault_pri : std_logic;
variable wb_WBNEEDSYNC : std_logic;
variable twACC : std_logic_vector(2 downto 0);
variable tWLVL : std_logic_vector(1 downto 0);
variable twPTE : std_logic_vector(31 downto 0);
variable twNEEDSYNC : std_logic;
variable tlbcam_tagin : tlbcam_tfp;
variable tlbcam_tagwrite : tlbcam_reg;
variable store : std_logic;
variable reppos : std_logic_vector(entries_log-1 downto 0);
variable i_entry : integer range 0 to entries-1;
variable i_reppos : integer range 0 to entries-1;
variable fault_pro, fault_pri : std_logic;
variable fault_mexc, fault_trans, fault_inv, fault_access : std_logic;
variable transdata : mmuidc_data_out_type;
variable fault : mmutlbfault_out_type;
variable savewalk : std_logic;
variable tlbo_s1finished : std_logic;
variable wb_transdata : mmuidc_data_out_type;
variable cam_addr : std_logic_vector(31 downto 0);
begin
v := r; v.tlbmiss := '0';
cam_addr := tlbi.transdata.data;
wb_i_entry := 0;
wb_ACC := (others => '0');
wb_PTE := (others => '0');
wb_LVL := (others => '0');
wb_CAC := '0';
wb_fault_pro := '0';
wb_fault_pri := '0';
wb_WBNEEDSYNC := '0';
if (M_TLB_FASTWRITE /= 0) and (tlbi.trans_op = '0') then
cam_addr := tlbi.transdata.wb_data;
end if;
wb_transdata.finish := '0';
wb_transdata.data := (others => '0');
wb_transdata.cache := '0';
wb_transdata.accexc := '0';
finish := '0';
selstate := '0';
cam_hitaddr := (others => '0');
cam_hit_all := '0';
mtag.TYP := (others => '0');
mtag.I1 := (others => '0');
mtag.I2 := (others => '0');
mtag.I3 := (others => '0');
mtag.CTX := (others => '0');
mtag.M := '0';
ftag.TYP := (others => '0');
ftag.I1 := (others => '0');
ftag.I2 := (others => '0');
ftag.I3 := (others => '0');
ftag.CTX := (others => '0');
ftag.M := '0';
tlbcam_trans_op := '0';
tlbcam_write_op := (others => '0');
tlbcam_flush_op := '0';
twi_walk_op_ur := '0';
twi_data := (others => '0');
twi_areq_ur := '0';
twi_aaddr := (others => '0');
twi_adata := (others => '0');
two_error := '0';
lrui_touch:= '0';
lrui_touchmin:= '0';
lrui_pos := (others => '0');
dr1write := '0';
ACC := (others => '0');
PTE := (others => '0');
LVL := (others => '0');
CAC := '0';
NEEDSYNC := '0';
twACC := (others => '0');
tWLVL := (others => '0');
twPTE := (others => '0');
twNEEDSYNC := '0';
tlbcam_tagin.TYP := (others => '0');
tlbcam_tagin.I1 := (others => '0');
tlbcam_tagin.I2 := (others => '0');
tlbcam_tagin.I3 := (others => '0');
tlbcam_tagin.CTX := (others => '0');
tlbcam_tagin.M := '0';
tlbcam_tagwrite.ET := (others => '0');
tlbcam_tagwrite.ACC := (others => '0');
tlbcam_tagwrite.M := '0';
tlbcam_tagwrite.R := '0';
tlbcam_tagwrite.SU := '0';
tlbcam_tagwrite.VALID := '0';
tlbcam_tagwrite.LVL := (others => '0');
tlbcam_tagwrite.I1 := (others => '0');
tlbcam_tagwrite.I2 := (others => '0');
tlbcam_tagwrite.I3 := (others => '0');
tlbcam_tagwrite.CTX := (others => '0');
tlbcam_tagwrite.PPN := (others => '0');
tlbcam_tagwrite.C := '0';
store := '0';
reppos := (others => '0');
fault_pro := '0';
fault_pri := '0';
fault_mexc := '0';
fault_trans := '0';
fault_inv := '0';
fault_access := '0';
transdata.finish := '0';
transdata.data := (others => '0');
transdata.cache := '0';
transdata.accexc := '0';
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
savewalk := '0';
tlbo_s1finished := '0';
tlbcam_trans_op := '0'; tlbcam_write_op := (others => '0'); tlbcam_flush_op := '0';
lrui_touch := '0'; lrui_touchmin := '0'; lrui_pos := (others => '0');
dr1write := '0';
fault_pro := '0'; fault_pri := '0'; fault_mexc := '0'; fault_trans := '0'; fault_inv := '0'; fault_access := '0';
twi_walk_op_ur := '0'; twi_areq_ur := '0'; twi_aaddr := dr1_dataout&"00";
finish := '0';
store := '0'; savewalk := '0'; tlbo_s1finished := '0';
selstate := '0';
cam_hitaddr := (others => '0');
cam_hit_all := '0';
NEEDSYNC := '0';
for i in entries-1 downto 0 loop
NEEDSYNC := NEEDSYNC or tlbcamo(i).NEEDSYNC;
if (tlbcamo(i).hit) = '1' then
cam_hitaddr(entries_log-1 downto 0) := cam_hitaddr(entries_log-1 downto 0) or conv_std_logic_vector(i, entries_log);
cam_hit_all := '1';
end if;
end loop;
-- tlbcam write operation
tlbcam_tagwrite := TLB_CreateCamWrite( two.data, r.s2_read, two.lvl, r.s2_ctx, r.s2_data);
-- replacement position
reppos := (others => '0');
if tlb_rep = 0 then
reppos := lruo.pos(entries_log-1 downto 0);
v.touch := '0';
elsif tlb_rep = 1 then
reppos := r.nrep;
end if;
i_reppos := conv_integer(reppos);
-- tw
two_error := two.fault_mexc or two.fault_trans or two.fault_inv;
twACC := two.data(PTE_ACC_U downto PTE_ACC_D);
twLVL := two.lvl;
twPTE := two.data;
twNEEDSYNC := (not two.data(PTE_R)) or ((not r.s2_read) and (not two.data(PTE_M))); -- tw : writeback on next flush
case r.s2_tlbstate is
when idle =>
if (tlbi.s2valid) = '1' then
if r.s2_flush = '1' then
v.s2_tlbstate := pack;
else
v.walk_fault.fault_pri := '0';
v.walk_fault.fault_pro := '0';
v.walk_fault.fault_access := '0';
v.walk_fault.fault_trans := '0';
v.walk_fault.fault_inv := '0';
v.walk_fault.fault_mexc := '0';
if (r.s2_hm and not tlbi.mmctrl1.tlbdis ) = '1' then
if r.s2_needsync = '1' then
v.s2_tlbstate := sync;
else
finish := '1';
end if;
if tlb_rep = 0 then
v.tpos := r.s2_entry; v.touch := '1'; -- touch lru
end if;
else
v.s2_entry := reppos;
v.s2_tlbstate := walk; v.tlbmiss := '1';
if tlb_rep = 0 then
lrui_touchmin := '1'; -- lru element consumed
end if;
end if;
end if;
end if;
when walk =>
if (two.finish = '1') then
if ( two_error ) = '0' then
tlbcam_write_op := decode(r.s2_entry);
dr1write := '1';
TLB_CheckFault( twACC, r.s2_isid, r.s2_su, r.s2_read, v.walk_fault.fault_pro, v.walk_fault.fault_pri );
end if;
TLB_MergeData( mmupgsz, tlbi.mmctrl1, two.lvl , two.data, r.s2_data, v.walk_transdata.data );
v.walk_transdata.cache := two.data(PTE_C);
v.walk_fault.fault_lvl := two.fault_lvl;
v.walk_fault.fault_access := '0';
v.walk_fault.fault_mexc := two.fault_mexc;
v.walk_fault.fault_trans := two.fault_trans;
v.walk_fault.fault_inv := two.fault_inv;
v.walk_use := '1';
if ( twNEEDSYNC = '0' or two_error = '1') then
v.s2_tlbstate := pack;
else
v.s2_tlbstate := sync;
v.sync_isw := '1';
end if;
if tlb_rep = 1 then
if (r.nrep = entries_max) then v.nrep := (others => '0');
else v.nrep := r.nrep + 1;
end if;
end if;
else
twi_walk_op_ur := '1';
end if;
when pack =>
v.s2_flush := '0';
v.walk_use := '0';
finish := '1';
v.s2_tlbstate := idle;
when sync =>
tlbcam_trans_op := '1';
if ( v.sync_isw = '1') then
-- pte address is currently written to syncram, wait one cycle before issuing twi_areq_ur
v.sync_isw := '0';
else
if (two.finish = '1') then
v.s2_tlbstate := pack;
v.walk_fault.fault_mexc := two.fault_mexc;
if (two.fault_mexc) = '1' then
v.walk_use := '1';
end if;
else
twi_areq_ur := '1';
end if;
end if;
when others =>
v .s2_tlbstate := idle;
end case;
if selstate = '1' then
if tlbi.trans_op = '1' then
elsif tlbi.flush_op = '1' then
end if;
end if;
i_entry := conv_integer(r.s2_entry);
ACC := tlbcamo(i_entry).pteout(PTE_ACC_U downto PTE_ACC_D);
PTE := tlbcamo(i_entry).pteout;
LVL := tlbcamo(i_entry).LVL;
CAC := tlbcamo(i_entry).pteout(PTE_C);
transdata.cache := CAC;
TLB_CheckFault( ACC, r.s2_isid, r.s2_su, r.s2_read, fault_pro, fault_pri );
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
if finish = '1' and (r.s2_flush = '0') then --protect flush path
fault.fault_pro := fault_pro;
fault.fault_pri := fault_pri;
fault.fault_access := fault_access;
fault.fault_mexc := fault_mexc;
fault.fault_trans := fault_trans;
fault.fault_inv := fault_inv;
end if;
if (M_TLB_FASTWRITE /= 0) then
wb_i_entry := conv_integer(cam_hitaddr(entries_log-1 downto 0));
wb_ACC := tlbcamo(wb_i_entry).pteout(PTE_ACC_U downto PTE_ACC_D);
wb_PTE := tlbcamo(wb_i_entry).pteout;
wb_LVL := tlbcamo(wb_i_entry).LVL;
wb_CAC := tlbcamo(wb_i_entry).pteout(PTE_C);
wb_WBNEEDSYNC := tlbcamo(wb_i_entry).WBNEEDSYNC;
wb_transdata.cache := wb_CAC;
TLB_MergeData( mmupgsz, tlbi.mmctrl1, wb_LVL, wb_PTE, tlbi.transdata.data, wb_transdata.data );
TLB_CheckFault( wb_ACC, tlbi.transdata.isid, tlbi.transdata.su, tlbi.transdata.read, wb_fault_pro, wb_fault_pri );
wb_transdata.accexc := wb_fault_pro or wb_fault_pri or wb_WBNEEDSYNC or (not cam_hit_all);
end if;
--# merge data
TLB_MergeData( mmupgsz, tlbi.mmctrl1, LVL, PTE, r.s2_data, transdata.data );
--# reset
if (not ASYNC_RESET) and (not RESET_ALL) and (rst = '0') then
v.s2_flush := '0';
v.s2_tlbstate := idle;
if tlb_rep = 1 then
v.nrep := (others => '0');
end if;
if tlb_rep = 0 then
v.touch := '0';
end if;
v.sync_isw := '0';
end if;
if (finish = '1') or (tlbi.s2valid = '0') then
tlbo_s1finished := '1';
v.s2_hm := cam_hit_all;
v.s2_entry := cam_hitaddr(entries_log-1 downto 0);
v.s2_needsync := NEEDSYNC;
v.s2_data := tlbi.transdata.data;
v.s2_read := tlbi.transdata.read;
v.s2_su := tlbi.transdata.su;
v.s2_isid := tlbi.transdata.isid;
v.s2_flush := tlbi.flush_op;
v.s2_ctx := tlbi.mmctrl1.ctx;
end if;
-- translation operation tag
mtag := TLB_CreateCamTrans( cam_addr, tlbi.transdata.read, tlbi.mmctrl1.ctx );
tlbcam_tagin := mtag;
-- flush/(probe) operation tag
ftag := TLB_CreateCamFlush( r.s2_data, tlbi.mmctrl1.ctx );
if (r.s2_flush = '1') then
tlbcam_tagin := ftag;
end if;
if r.walk_use = '1' then
transdata := r.walk_transdata;
fault := r.walk_fault;
end if;
fault.fault_read := r.s2_read;
fault.fault_su := r.s2_su;
fault.fault_isid := r.s2_isid;
fault.fault_addr := r.s2_data;
transdata.finish := finish;
transdata.accexc := '0';
twi_adata := PTE;
--# drive signals
tlbo.wbtransdata <= wb_transdata;
tlbo.transdata <= transdata;
tlbo.fault <= fault;
tlbo.nexttrans <= store;
tlbo.s1finished <= tlbo_s1finished;
twi.walk_op_ur <= twi_walk_op_ur;
twi.data <= r.s2_data;
twi.areq_ur <= twi_areq_ur;
twi.adata <= twi_adata;
twi.aaddr <= twi_aaddr;
twi.tlbmiss <= r.tlbmiss;
if tlb_rep = 0 then
lrui.flush <= r.s2_flush;
lrui.touch <= r.touch;
lrui.touchmin <= lrui_touchmin;
lrui.pos <= (others => '0');
lrui.pos(entries_log-1 downto 0) <= r.tpos;
lrui.mmctrl1 <= tlbi.mmctrl1;
end if;
dr1_addr <= r.s2_entry;
dr1_datain <= two.addr(31 downto 2);
dr1_enable <= '1';
dr1_write <= dr1write;
for i in entries-1 downto 0 loop
tlbcami(i).mmctrl <= tlbi.mmctrl1;
tlbcami(i).tagin <= tlbcam_tagin;
tlbcami(i).trans_op <= tlbi.trans_op; --tlbcam_trans_op;
tlbcami(i).wb_op <= tlbi.wb_op; --tlbcam_trans_op;
tlbcami(i).flush_op <= r.s2_flush;
tlbcami(i).mmuen <= tlbi.mmctrl1.e;
tlbcami(i).tagwrite <= tlbcam_tagwrite;
tlbcami(i).write_op <= tlbcam_write_op(i);
tlbcami(i).mset <= '0';
end loop; -- i
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r <= RRES;
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
-- tag-cam tlb entries
tlbcam0: for i in entries-1 downto 0 generate
tag0 : mmutlbcam
generic map ( tlb_type, mmupgsz )
port map (rst, clk, tlbcami(i), tlbcamo(i));
end generate tlbcam0;
-- data-ram syncram
dataram : syncram
generic map ( tech => tech, dbits => 30, abits => entries_log, testen => scantest, custombits => ramcbits)
port map ( clk, dr1_addr, dr1_datain, dr1_dataout, dr1_enable, dr1_write,
testin
);
-- lru
lru0: if tlb_rep = 0 generate
lru : mmulru
generic map ( entries => entries)
port map ( clk, rst, lrui, lruo );
end generate lru0;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity rotate_mix_nibbles is
port(data_in: in std_logic_vector(63 downto 0);
data_out: out std_logic_vector(63 downto 0)
);
end entity;
architecture structual of rotate_mix_nibbles is
signal rotated: std_logic_vector(63 downto 0);
signal mix_mul_in,
mix_mul_out: std_logic_vector(63 downto 0);
component mul_poly
port(data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0)
);
end component;
begin
rotated <= data_in(47 downto 0) & data_in(63 downto 48);
-- MixNibbles algorithm inspired from
-- https://link.springer.com/chapter/10.1007/978-3-642-25578-6_11
mix_mul_in(63 downto 56) <= rotated(63 downto 56) xor rotated(55 downto 48);
mix_mul_in(55 downto 48) <= rotated(55 downto 48) xor rotated(47 downto 40);
mix_mul_in(47 downto 40) <= rotated(47 downto 40) xor rotated(39 downto 32);
mix_mul_in(39 downto 32) <= rotated(39 downto 32) xor rotated(63 downto 56);
mix_mul_in(31 downto 24) <= rotated(31 downto 24) xor rotated(23 downto 16);
mix_mul_in(23 downto 16) <= rotated(23 downto 16) xor rotated(15 downto 8);
mix_mul_in(15 downto 8) <= rotated(15 downto 8) xor rotated(7 downto 0);
mix_mul_in(7 downto 0) <= rotated(7 downto 0) xor rotated(31 downto 24);
MUL: for i in 0 to 7 generate
MX: mul_poly port map(
data_in => mix_mul_in(63-(8*i) downto 63-(8*i)-7),
data_out => mix_mul_out(63-(8*i) downto 63-(8*i)-7)
);
end generate;
data_out(63 downto 56) <= mix_mul_out(63 downto 56) xor
mix_mul_in(55 downto 48) xor
rotated(39 downto 32);
data_out(55 downto 48) <= mix_mul_out(55 downto 48) xor
mix_mul_in(47 downto 40) xor
rotated(63 downto 56);
data_out(47 downto 40) <= mix_mul_out(47 downto 40) xor
mix_mul_in(63 downto 56) xor
rotated(39 downto 32);
data_out(39 downto 32) <= mix_mul_out(39 downto 32) xor
mix_mul_in(63 downto 56) xor
rotated(47 downto 40);
data_out(31 downto 24) <= mix_mul_out(31 downto 24) xor
mix_mul_in(23 downto 16) xor
rotated(7 downto 0);
data_out(23 downto 16) <= mix_mul_out(23 downto 16) xor
mix_mul_in(15 downto 8) xor
rotated(31 downto 24);
data_out(15 downto 8) <= mix_mul_out(15 downto 8) xor
mix_mul_in(31 downto 24) xor
rotated(7 downto 0);
data_out(7 downto 0) <= mix_mul_out(7 downto 0) xor
mix_mul_in(31 downto 24) xor
rotated(15 downto 8);
end architecture;
|
--------------------------------------------------------------------------------
--
-- FileName: pwm.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 8/1/2013 Scott Larson
-- Initial Public Release
-- Version 2.0 1/9/2015 Scott Larson
-- Transistion between duty cycles always starts at center of pulse to avoid
-- anomalies in pulse shapes
--
--------------------------------------------------------------------------------
-- PWM code taken from IEEE wiki - https://eewiki.net/pages/viewpage.action?pageId=20939345#PWMGenerator(VHDL)-CodeDownload
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY pwm IS
GENERIC(
sys_clk : INTEGER := 100_000_000; --system clock frequency in Hz
pwm_freq : INTEGER := 500_000; --PWM switching frequency in Hz
bits_resolution : INTEGER := 64; --bits of resolution setting the duty cycle
phases : INTEGER := 1); --number of output pwms and phases
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
ena : IN STD_LOGIC; --latches in new duty cycle
duty : IN STD_LOGIC_VECTOR(bits_resolution-1 DOWNTO 0); --duty cycle
pwm_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0); --pwm outputs
pwm_n_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0)); --pwm inverse outputs
END pwm;
ARCHITECTURE logic OF pwm IS
CONSTANT period : INTEGER := sys_clk/pwm_freq; --number of clocks in one pwm period
TYPE counters IS ARRAY (0 TO phases-1) OF INTEGER RANGE 0 TO period - 1; --data type for array of period counters
SIGNAL count : counters := (OTHERS => 0); --array of period counters
SIGNAL half_duty_new : INTEGER RANGE 0 TO period/2 := 0; --number of clocks in 1/2 duty cycle
TYPE half_duties IS ARRAY (0 TO phases-1) OF INTEGER RANGE 0 TO period/2; --data type for array of half duty values
SIGNAL half_duty : half_duties := (OTHERS => 0); --array of half duty values (for each phase)
BEGIN
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --asynchronous reset
count <= (OTHERS => 0); --clear counter
pwm_out <= (OTHERS => '0'); --clear pwm outputs
pwm_n_out <= (OTHERS => '0'); --clear pwm inverse outputs
ELSIF((clk'EVENT AND clk = '1')) THEN --rising system clock edge
IF(ena = '1') THEN --latch in new duty cycle
half_duty_new <= conv_integer(duty)*period/(2**bits_resolution)/2; --determine clocks in 1/2 duty cycle
END IF;
FOR i IN 0 to phases-1 LOOP --create a counter for each phase
IF(count(0) = period - 1 - i*period/phases) THEN --end of period reached
count(i) <= 0; --reset counter
half_duty(i) <= half_duty_new; --set most recent duty cycle value
ELSE --end of period not reached
count(i) <= count(i) + 1; --increment counter
END IF;
END LOOP;
FOR i IN 0 to phases-1 LOOP --control outputs for each phase
IF(count(i) = half_duty(i)) THEN --phase's falling edge reached
pwm_out(i) <= '0'; --deassert the pwm output
pwm_n_out(i) <= '1'; --assert the pwm inverse output
ELSIF(count(i) = period - half_duty(i)) THEN --phase's rising edge reached
pwm_out(i) <= '1'; --assert the pwm output
pwm_n_out(i) <= '0'; --deassert the pwm inverse output
END IF;
END LOOP;
END IF;
END PROCESS;
END logic;
--library ieee;
--use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
--entity pwm_prog is
--generic(
-- N : integer := 8); -- number of bit of PWM counter
--port (
-- i_clk : in std_logic;
-- i_rstb : in std_logic;
-- i_sync_reset : in std_logic;
-- i_pwm_module : in std_logic_vector(N-1 downto 0); -- PWM Freq = clock freq/ (i_pwm_module+1); max value = 2^N-1
-- i_pwm_width : in std_logic_vector(N-1 downto 0); -- PWM width = (others=>0)=> OFF; i_pwm_module => MAX ON
-- o_pwm : out std_logic);
--end pwm_prog;
--architecture rtl of pwm_prog is
--signal r_max_count : unsigned(N-1 downto 0);
--signal r_pwm_counter : unsigned(N-1 downto 0);
--signal r_pwm_width : unsigned(N-1 downto 0);
--signal w_tc_pwm_counter : std_logic;
--begin
--w_tc_pwm_counter <= '0' when(r_pwm_counter<r_max_count) else '1'; -- use to strobe new word
----------------------------------------------------------------------
--p_state_out : process(i_clk,i_rstb)
--begin
-- if(i_rstb='0') then
-- r_max_count <= (others=>'0');
-- r_pwm_width <= (others=>'0');
-- r_pwm_counter <= (others=>'0');
-- o_pwm <= '0';
-- elsif(rising_edge(i_clk)) then
-- r_max_count <= unsigned(i_pwm_module);
-- if(i_sync_reset='1') then
-- r_pwm_width <= unsigned(i_pwm_width);
-- r_pwm_counter <= to_unsigned(0,N);
-- o_pwm <= '0';
-- else
-- if(r_pwm_counter=0) and (r_pwm_width/=r_max_count) then
-- o_pwm <= '0';
-- elsif(r_pwm_counter<=r_pwm_width) then
-- o_pwm <= '1';
-- else
-- o_pwm <= '0';
-- end if;
-- if(w_tc_pwm_counter='1') then
-- r_pwm_width <= unsigned(i_pwm_width);
-- end if;
-- if(r_pwm_counter=r_max_count) then
-- r_pwm_counter <= to_unsigned(0,N);
-- else
-- r_pwm_counter <= r_pwm_counter + 1;
-- end if;
-- end if;
-- end if;
--end process p_state_out;
--end rtl; |
------------------------------------------------------------------------------
-- Title : BPM RF channels swapping and de-swapping mode selector
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Select among distinct swapping and de-swapping modes affecting
-- how the swap master clock is propagated to the swap and de-swap
-- output signals.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bpm_cores_pkg.all;
entity swmode_sel is
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic := '1';
-- Swap master clock
clk_swap_i : in std_logic;
-- Swap and de-swap signals
swap_o : out std_logic;
deswap_o : out std_logic;
-- Swap mode setting
swap_mode_i : in t_swap_mode
);
end swmode_sel;
architecture rtl of swmode_sel is
signal swap : std_logic;
signal deswap : std_logic;
begin
p_swap_mode : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
swap <= '0';
deswap <= '0';
else
if en_i = '1' then
case swap_mode_i is
when c_swmode_swap_deswap =>
if clk_swap_i = '1' then
swap <= '1';
deswap <= '1';
else
swap <= '0';
deswap <= '0';
end if;
when c_swmode_static_direct =>
swap <= '0';
deswap <= '0';
when c_swmode_static_inverted =>
swap <= '1';
deswap <= '0';
when c_swmode_rffe_swap =>
if clk_swap_i = '1' then
swap <= '1';
else
swap <= '0';
end if;
deswap <= '0';
when others =>
swap <= '0';
deswap <= '0';
end case;
end if;
end if;
end if;
end process p_swap_mode;
swap_o <= swap;
deswap_o <= deswap;
end rtl;
|
-------------------------------------------------------------------------------
-- File Name : BUF_FIFO.vhd
--
-- Project : JPEG_ENC
--
-- Module : BUF_FIFO
--
-- Content : Input FIFO Buffer
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090311: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity BUF_FIFO is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HOST PROG
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
sof : in std_logic;
-- HOST DATA
iram_wren : in std_logic;
iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);
fifo_almost_full : out std_logic;
-- FDCT
fdct_fifo_rd : in std_logic;
fdct_fifo_q : out std_logic_vector(23 downto 0);
fdct_fifo_hf_full : out std_logic
);
end entity BUF_FIFO;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of BUF_FIFO is
constant C_NUM_LINES : integer := 8 + C_EXTRA_LINES;
signal pixel_cnt : unsigned(15 downto 0);
signal line_cnt : unsigned(15 downto 0);
signal ramq : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal ramwaddr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
signal ramenw : STD_LOGIC;
signal ramraddr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
signal pix_inblk_cnt : unsigned(3 downto 0);
signal pix_inblk_cnt_d1 : unsigned(3 downto 0);
signal line_inblk_cnt : unsigned(2 downto 0);
signal read_block_cnt : unsigned(12 downto 0);
signal read_block_cnt_d1 : unsigned(12 downto 0);
signal write_block_cnt : unsigned(12 downto 0);
signal ramraddr_int : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
signal raddr_base_line : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
signal raddr_tmp : unsigned(15 downto 0);
signal ramwaddr_d1 : unsigned(ramwaddr'range);
signal line_lock : unsigned(log2(C_NUM_LINES)-1 downto 0);
signal memwr_line_cnt : unsigned(log2(C_NUM_LINES)-1 downto 0);
signal memrd_offs_cnt : unsigned(log2(C_NUM_LINES)-1+1 downto 0);
signal memrd_line : unsigned(log2(C_NUM_LINES)-1 downto 0);
signal wr_line_idx : unsigned(15 downto 0);
signal rd_line_idx : unsigned(15 downto 0);
signal image_write_end : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- RAM for SUB_FIFOs
-------------------------------------------------------------------
U_SUB_RAMZ : entity work.SUB_RAMZ
generic map
(
RAMADDR_W => log2( C_MAX_LINE_WIDTH*C_NUM_LINES ),
RAMDATA_W => C_PIXEL_BITS
)
port map
(
d => ramd,
waddr => std_logic_vector(ramwaddr_d1),
raddr => std_logic_vector(ramraddr),
we => ramenw,
clk => clk,
q => ramq
);
-------------------------------------------------------------------
-- register RAM data input
-------------------------------------------------------------------
p_mux1 : process(CLK, RST)
begin
if RST = '1' then
ramenw <= '0';
ramd <= (others => '0');
elsif CLK'event and CLK = '1' then
ramd <= iram_wdata;
ramenw <= iram_wren;
end if;
end process;
-------------------------------------------------------------------
-- resolve RAM write address
-------------------------------------------------------------------
p_pixel_cnt : process(CLK, RST)
begin
if RST = '1' then
pixel_cnt <= (others => '0');
memwr_line_cnt <= (others => '0');
wr_line_idx <= (others => '0');
ramwaddr <= (others => '0');
ramwaddr_d1 <= (others => '0');
image_write_end <= '0';
elsif CLK'event and CLK = '1' then
ramwaddr_d1 <= ramwaddr;
if iram_wren = '1' then
-- end of line
if pixel_cnt = unsigned(img_size_x)-1 then
pixel_cnt <= (others => '0');
-- absolute write line index
wr_line_idx <= wr_line_idx + 1;
if wr_line_idx = unsigned(img_size_y)-1 then
image_write_end <= '1';
end if;
-- memory line index
if memwr_line_cnt = C_NUM_LINES-1 then
memwr_line_cnt <= (others => '0');
ramwaddr <= (others => '0');
else
memwr_line_cnt <= memwr_line_cnt + 1;
ramwaddr <= ramwaddr + 1;
end if;
else
pixel_cnt <= pixel_cnt + 1;
ramwaddr <= ramwaddr + 1;
end if;
end if;
if sof = '1' then
pixel_cnt <= (others => '0');
ramwaddr <= (others => '0');
memwr_line_cnt <= (others => '0');
wr_line_idx <= (others => '0');
image_write_end <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------
-- FIFO half full / almost full flag generation
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
fdct_fifo_hf_full <= '0';
fifo_almost_full <= '0';
elsif CLK'event and CLK = '1' then
if rd_line_idx + 8 <= wr_line_idx then
fdct_fifo_hf_full <= '1';
else
fdct_fifo_hf_full <= '0';
end if;
fifo_almost_full <= '0';
if wr_line_idx = rd_line_idx + C_NUM_LINES-1 then
if pixel_cnt >= unsigned(img_size_x)-1-1 then
fifo_almost_full <= '1';
end if;
elsif wr_line_idx > rd_line_idx + C_NUM_LINES-1 then
fifo_almost_full <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------
-- read side
-------------------------------------------------------------------
p_mux5 : process(CLK, RST)
begin
if RST = '1' then
memrd_offs_cnt <= (others => '0');
read_block_cnt <= (others => '0');
pix_inblk_cnt <= (others => '0');
line_inblk_cnt <= (others => '0');
rd_line_idx <= (others => '0');
pix_inblk_cnt_d1 <= (others => '0');
read_block_cnt_d1 <= (others => '0');
elsif CLK'event and CLK = '1' then
pix_inblk_cnt_d1 <= pix_inblk_cnt;
read_block_cnt_d1 <= read_block_cnt;
-- BUF FIFO read
if fdct_fifo_rd = '1' then
-- last pixel in block
if pix_inblk_cnt = 8-1 then
pix_inblk_cnt <= (others => '0');
-- last line in 8
if line_inblk_cnt = 8-1 then
line_inblk_cnt <= (others => '0');
-- last block in last line
if read_block_cnt = unsigned(img_size_x(15 downto 3))-1 then
read_block_cnt <= (others => '0');
rd_line_idx <= rd_line_idx + 8;
if memrd_offs_cnt + 8 > C_NUM_LINES-1 then
memrd_offs_cnt <= memrd_offs_cnt + 8 - C_NUM_LINES;
else
memrd_offs_cnt <= memrd_offs_cnt + 8;
end if;
else
read_block_cnt <= read_block_cnt + 1;
end if;
else
line_inblk_cnt <= line_inblk_cnt + 1;
end if;
else
pix_inblk_cnt <= pix_inblk_cnt + 1;
end if;
end if;
if memrd_offs_cnt + (line_inblk_cnt) > C_NUM_LINES-1 then
memrd_line <= memrd_offs_cnt(memrd_line'range) + (line_inblk_cnt) - (C_NUM_LINES);
else
memrd_line <= memrd_offs_cnt(memrd_line'range) + (line_inblk_cnt);
end if;
if sof = '1' then
memrd_line <= (others => '0');
memrd_offs_cnt <= (others => '0');
read_block_cnt <= (others => '0');
pix_inblk_cnt <= (others => '0');
line_inblk_cnt <= (others => '0');
rd_line_idx <= (others => '0');
end if;
end if;
end process;
-- generate RAM data output based on 16 or 24 bit mode selection
fdct_fifo_q <= (ramq(15 downto 11) & "000" &
ramq(10 downto 5) & "00" &
ramq(4 downto 0) & "000") when C_PIXEL_BITS = 16 else
std_logic_vector(resize(unsigned(ramq), 24));
ramraddr <= ramraddr_int(ramraddr'range);
-------------------------------------------------------------------
-- resolve RAM read address
-------------------------------------------------------------------
p_mux4 : process(CLK, RST)
begin
if RST = '1' then
ramraddr_int <= (others => '0');
elsif CLK'event and CLK = '1' then
raddr_base_line <= (memrd_line) * unsigned(img_size_x);
raddr_tmp <= (read_block_cnt_d1 & "000") + pix_inblk_cnt_d1;
ramraddr_int <= raddr_tmp + raddr_base_line;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY demux IS
GENERIC(
select_width, line_width : positive;
default_out : std_logic
);
PORT(
INPUT : IN std_logic_vector(line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
FLOOD : IN std_logic; -- FLOOD=1 causes all bits of OUTPUT to be set to 1
OUTPUT : OUT std_logic_vector(2**select_width*line_width-1 DOWNTO 0)
);
END demux;
ARCHITECTURE recursive OF demux IS
SIGNAL subdemux_0_IN, subdemux_1_IN : std_logic_vector(line_width-1 DOWNTO 0);
COMPONENT demux
GENERIC(
select_width, line_width : positive;
default_out : std_logic
);
PORT(
INPUT : IN std_logic_vector(line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
FLOOD : IN std_logic; -- FLOOD=1 causes all bits of OUTPUT to be set to 1
OUTPUT : OUT std_logic_vector(2**select_width*line_width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : demux USE ENTITY WORK.demux(recursive);
BEGIN
demux1to2: IF select_width=1 GENERATE
OUTPUT(line_width-1 DOWNTO 0) <= (OTHERS => '1') WHEN FLOOD='1'
ELSE INPUT WHEN SEL="0" ELSE (OTHERS => default_out);
OUTPUT(2*line_width-1 DOWNTO line_width) <= (OTHERS => '1') WHEN FLOOD='1'
ELSE INPUT WHEN SEL="1" ELSE (OTHERS => default_out);
END GENERATE;
demux1toN: IF select_width>1 GENERATE
subdemux_0: demux
GENERIC MAP(select_width => select_width-1, line_width => line_width,
default_out => default_out)
PORT MAP(INPUT => subdemux_0_IN,
SEL => SEL(select_width-2 DOWNTO 0),
FLOOD => FLOOD,
OUTPUT => OUTPUT(2**(select_width-1)*line_width-1 DOWNTO 0));
subdemux_1: demux
GENERIC MAP(select_width => select_width-1, line_width => line_width,
default_out => default_out)
PORT MAP(INPUT => subdemux_1_IN,
SEL => SEL(select_width-2 DOWNTO 0),
FLOOD => FLOOD,
OUTPUT => OUTPUT(2**select_width*line_width-1
DOWNTO 2**(select_width-1)*line_width));
subdemux_0_IN <= INPUT WHEN SEL(select_width-1)='0'
ELSE (OTHERS => default_out);
subdemux_1_IN <= INPUT WHEN SEL(select_width-1)='1'
ELSE (OTHERS => default_out);
END GENERATE;
END recursive;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY demux IS
GENERIC(
select_width, line_width : positive;
default_out : std_logic
);
PORT(
INPUT : IN std_logic_vector(line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
FLOOD : IN std_logic; -- FLOOD=1 causes all bits of OUTPUT to be set to 1
OUTPUT : OUT std_logic_vector(2**select_width*line_width-1 DOWNTO 0)
);
END demux;
ARCHITECTURE recursive OF demux IS
SIGNAL subdemux_0_IN, subdemux_1_IN : std_logic_vector(line_width-1 DOWNTO 0);
COMPONENT demux
GENERIC(
select_width, line_width : positive;
default_out : std_logic
);
PORT(
INPUT : IN std_logic_vector(line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
FLOOD : IN std_logic; -- FLOOD=1 causes all bits of OUTPUT to be set to 1
OUTPUT : OUT std_logic_vector(2**select_width*line_width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : demux USE ENTITY WORK.demux(recursive);
BEGIN
demux1to2: IF select_width=1 GENERATE
OUTPUT(line_width-1 DOWNTO 0) <= (OTHERS => '1') WHEN FLOOD='1'
ELSE INPUT WHEN SEL="0" ELSE (OTHERS => default_out);
OUTPUT(2*line_width-1 DOWNTO line_width) <= (OTHERS => '1') WHEN FLOOD='1'
ELSE INPUT WHEN SEL="1" ELSE (OTHERS => default_out);
END GENERATE;
demux1toN: IF select_width>1 GENERATE
subdemux_0: demux
GENERIC MAP(select_width => select_width-1, line_width => line_width,
default_out => default_out)
PORT MAP(INPUT => subdemux_0_IN,
SEL => SEL(select_width-2 DOWNTO 0),
FLOOD => FLOOD,
OUTPUT => OUTPUT(2**(select_width-1)*line_width-1 DOWNTO 0));
subdemux_1: demux
GENERIC MAP(select_width => select_width-1, line_width => line_width,
default_out => default_out)
PORT MAP(INPUT => subdemux_1_IN,
SEL => SEL(select_width-2 DOWNTO 0),
FLOOD => FLOOD,
OUTPUT => OUTPUT(2**select_width*line_width-1
DOWNTO 2**(select_width-1)*line_width));
subdemux_0_IN <= INPUT WHEN SEL(select_width-1)='0'
ELSE (OTHERS => default_out);
subdemux_1_IN <= INPUT WHEN SEL(select_width-1)='1'
ELSE (OTHERS => default_out);
END GENERATE;
END recursive;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:32:19 01/31/2015
-- Design Name:
-- Module Name: /home/james/devroot/learnfpga/midi/tb/shift_out_tb.vhdl
-- Project Name: midi
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: shift_out
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY shift_out_tb IS
END shift_out_tb;
ARCHITECTURE behavior OF shift_out_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT shift_out
GENERIC(
width : positive
);
PORT(
par_in : IN std_logic_vector(width - 1 downto 0);
load : IN std_logic;
ser_out : OUT std_logic;
clk : IN std_logic;
ce : IN std_logic
);
END COMPONENT;
--Inputs
signal par_in : std_logic_vector(9 downto 0) := (others => '0');
signal load : std_logic := '0';
signal clk : std_logic := '0';
signal ce : std_logic := '0';
--Outputs
signal ser_out : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: shift_out GENERIC MAP (
width => 10
) PORT MAP (
par_in => par_in,
load => load,
ser_out => ser_out,
clk => clk,
ce => ce
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
load <= '0';
ce <= '0';
-- hold reset state for 100 ns.
wait for 100 ns;
par_in <= "1001110001";
load <= '1';
wait for clk_period*10;
load <= '0';
ce <= '1';
wait for clk_period * 12;
load <= '1';
wait for clk_period;
load <= '0';
wait for clk_period * 12;
load <= '1';
wait for clk_period * 5;
load <= '0';
-- insert stimulus here
wait;
end process;
END;
|
-- NEED RESULT: ARCH00018: Wait in P1_1 did resume passed
-- NEED RESULT: ARCH00018: Wait in P1_2 did resume passed
-- NEED RESULT: ARCH00018: Wait in P2_1 did resume passed
-- NEED RESULT: ARCH00018: Wait in P2_2 did resume passed
-- NEED RESULT: ARCH00018: Wait in P3_1 did resume passed
-- NEED RESULT: ARCH00018: Wait in P3_2 did resume passed
-- NEED RESULT: ARCH00018: Wait in R1_1 did resume passed
-- NEED RESULT: ARCH00018: Wait in R1_2 did resume passed
-- NEED RESULT: ARCH00018: Wait in PROC1_1 did resume passed
-- NEED RESULT: ARCH00018: Wait in PROC1_2 did resume passed
-- NEED RESULT: ARCH00018: Wait in PROC2_1 did resume passed
-- NEED RESULT: ARCH00018: Wait in PROC2_2 did resume passed
-- NEED RESULT: ARCH00018: Wait in PROC3_1 did resume passed
-- NEED RESULT: ARCH00018: Wait in PROC3_2 did resume passed
-- NEED RESULT: ARCH00018: Wait in PROC4_1 did resume passed
-- NEED RESULT: ARCH00018: Wait in PROC4_2 did resume passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00018
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (8)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00018(ARCH00018)
-- ENT00018_Test_Bench(ARCH00018_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00018 is
generic ( G1 : Time := 10 ns ) ;
port ( P1 : in Time := 10 ns ) ;
end ENT00018 ;
architecture ARCH00018 of ENT00018 is
signal Num_Cycles : Integer := 0 ;
signal Dummy_Cond : Boolean := false ;
signal P1_1_Did_Resume, P1_2_Did_Resume : Boolean := false ;
signal P2_1_Did_Resume, P2_2_Did_Resume : Boolean := false ;
signal P3_1_Did_Resume, P3_2_Did_Resume : Boolean := false ;
signal R1_1_Did_Resume, R1_2_Did_Resume : Boolean := false ;
signal PROC1_1_Did_Resume, PROC1_2_Did_Resume : Boolean := false ;
signal PROC2_1_Did_Resume, PROC2_2_Did_Resume : Boolean := false ;
signal PROC3_1_Did_Resume, PROC3_2_Did_Resume : Boolean := false ;
signal PROC4_1_Did_Resume, PROC4_2_Did_Resume : Boolean := false ;
constant Time_To_Wait : Time := 10 ns ;
procedure PROC1_1 ( Signal Resume_Chk : inout boolean ) is
begin
wait on Num_Cycles until Dummy_Cond for Time_To_Wait ; -- Locally Static
Resume_Chk <= transport True ;
end PROC1_1 ;
procedure PROC1_2 ( Signal Resume_Chk : inout boolean ) is
begin
wait until (Num_Cycles = 1000) for Time_To_Wait ; -- Locally Static
Resume_Chk <= transport True ;
end PROC1_2 ;
procedure PROC2_1 ( Signal Resume_Chk : inout boolean ) is
begin
wait on Num_Cycles until Dummy_Cond for G1 ; -- Globally Static
Resume_Chk <= transport True ;
end PROC2_1 ;
procedure PROC2_2 ( Signal Resume_Chk : inout boolean ) is
begin
wait until (Num_Cycles = 1000) for G1 ; -- Globally Static
Resume_Chk <= transport True ;
end PROC2_2 ;
procedure PROC3_1 ( Signal Resume_Chk : inout boolean ) is
begin
wait on Num_Cycles until Dummy_Cond for P1 ; -- Dynamic
Resume_Chk <= transport True ;
end PROC3_1 ;
procedure PROC3_2 ( Signal Resume_Chk : inout boolean ) is
begin
wait until (Num_Cycles = 1000) for P1 ; -- Dynamic
Resume_Chk <= transport True ;
end PROC3_2 ;
procedure PROC4_1 (Time_To_Wait : Time;
Signal Resume_Chk : inout boolean) is
begin
wait on Num_Cycles until Dummy_Cond for Time_To_Wait ;
Resume_Chk <= transport True ;
end PROC4_1 ;
procedure PROC4_2 (Time_To_Wait : Time;
Signal Resume_Chk : inout boolean) is
begin
wait until (Num_Cycles = 1000) for Time_To_Wait ;
Resume_Chk <= transport True ;
end PROC4_2 ;
begin
Test_Control :
process ( Num_Cycles )
begin
if Num_Cycles < 9 then
Num_Cycles <= transport Num_Cycles + 1 after 1 ns ;
elsif Num_Cycles = 9 then
-- Verify that in fact, none of the wait statements resumed
test_report ( "ARCH00018" ,
"Wait in P1_1 did resume" ,
Not P1_1_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in P1_2 did resume" ,
Not P1_2_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in P2_1 did resume" ,
Not P2_1_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in P2_2 did resume" ,
Not P2_2_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in P3_1 did resume" ,
Not P3_1_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in P3_2 did resume" ,
Not P3_2_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in R1_1 did resume" ,
Not R1_1_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in R1_2 did resume" ,
Not R1_2_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in PROC1_1 did resume" ,
Not PROC1_1_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in PROC1_2 did resume" ,
Not PROC1_2_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in PROC2_1 did resume" ,
Not PROC2_1_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in PROC2_2 did resume" ,
Not PROC2_2_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in PROC3_1 did resume" ,
Not PROC3_1_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in PROC3_2 did resume" ,
Not PROC3_2_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in PROC4_1 did resume" ,
Not PROC4_1_Did_Resume ) ;
test_report ( "ARCH00018" ,
"Wait in PROC4_2 did resume" ,
Not PROC4_2_Did_Resume ) ;
end if ;
end process Test_Control ;
P1_1 :
process
begin
wait on Num_Cycles until Dummy_Cond for Time_To_Wait ; -- Locally Static
P1_1_Did_Resume <= transport True ;
wait;
end process P1_1 ;
P1_2 :
process
begin
wait until (Num_Cycles = 1000) for Time_To_Wait ; -- Locally Static
P1_2_Did_Resume <= transport True ;
wait;
end process P1_2 ;
P2_1 :
process
begin
wait on Num_Cycles until Dummy_Cond for G1 ; -- Globally Static
P2_1_Did_Resume <= transport True ;
wait;
end process P2_1 ;
P2_2 :
process
begin
wait until (Num_Cycles = 1000) for G1 ; -- Globally Static
P2_2_Did_Resume <= transport True ;
wait;
end process P2_2 ;
P3_1 :
process
begin
wait on Num_Cycles until Dummy_Cond for P1 ; -- Dynamic
P3_1_Did_Resume <= transport True ;
wait;
end process P3_1 ;
P3_2 :
process
begin
wait until (Num_Cycles = 1000) for P1 ; -- Dynamic
P3_2_Did_Resume <= transport True ;
wait;
end process P3_2 ;
Q1_1 :
process
begin
PROC1_1 (PROC1_1_Did_Resume) ;
wait;
end process Q1_1 ;
Q1_2 :
process
begin
PROC1_2 (PROC1_2_Did_Resume) ;
wait;
end process Q1_2 ;
Q2_1 :
process
begin
PROC2_1 (PROC2_1_Did_Resume) ;
wait;
end process Q2_1 ;
Q2_2 :
process
begin
PROC2_2 (PROC2_2_Did_Resume) ;
wait;
end process Q2_2 ;
Q3_1 :
process
begin
PROC3_1 (PROC3_1_Did_Resume) ;
wait;
end process Q3_1 ;
Q3_2 :
process
begin
PROC3_2 (PROC3_2_Did_Resume) ;
wait;
end process Q3_2 ;
Q4_1 :
process
begin
PROC4_1 (Time_To_Wait, PROC4_1_Did_Resume) ;
wait;
end process Q4_1 ;
Q4_2 :
process
begin
PROC4_2 (P1, PROC4_2_Did_Resume) ;
wait;
end process Q4_2 ;
R1_1 :
process
begin
wait on Num_Cycles until Dummy_Cond ; -- No Time
R1_1_Did_Resume <= transport True ;
wait;
end process R1_1 ;
R1_2 :
process
begin
wait until (Num_Cycles = 1000) ; -- No Time
R1_2_Did_Resume <= transport True ;
wait;
end process R1_2 ;
end ARCH00018 ;
entity ENT00018_Test_Bench is
end ENT00018_Test_Bench ;
architecture ARCH00018_Test_Bench of ENT00018_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00018 ( ARCH00018 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00018_Test_Bench ;
|
-- NEED RESULT: ARCH00289: Logical operators are correctly predefined for boolean array types passed
-- NEED RESULT: ARCH00289: Logical operators are correctly predefined for bit array types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00289
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.1 (2)
-- 7.2.1 (9)
-- 7.2.1 (10)
-- 7.2.1 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00289(ARCH00289)
-- ENT00289_Test_Bench(ARCH00289_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00289 is
generic ( bit1, bit2 : st_bit_vector ;
bool1, bool2 : boolean ) ;
port ( locally_static_correct_1, locally_static_correct_2 : out boolean ;
dynamic_correct_1, dynamic_correct_2 : out boolean ) ;
end ENT00289 ;
architecture ARCH00289 of ENT00289 is
signal sbit1, sbit2 : st_bit_vector := B"10100" ;
signal sboolean1, sboolean2 : st_boolean_vector ;
constant answer : boolean := true ;
begin
sbit2 <= B"01011" ;
sboolean1 <= (true, false, true, false, false);
sboolean2 <= (false, true, false, true, true);
-- bit vector
g1: if (((bit1 and bit1) = B"10100") and
((bit1 and bit2) = B"00000") and
((bit2 and bit1) = B"00000") and
((bit2 and bit2) = B"01011") and
((bit1 or bit1) = B"10100") and
((bit1 or bit2) = B"11111") and
((bit2 or bit1) = B"11111") and
((bit2 or bit2) = B"01011") and
((bit1 nand bit1) = B"01011") and
((bit1 nand bit2) = B"11111") and
((bit2 nand bit1) = B"11111") and
((bit2 nand bit2) = B"10100") and
((bit1 nor bit1) = B"01011") and
((bit1 nor bit2) = B"00000") and
((bit2 nor bit1) = B"00000") and
((bit2 nor bit2) = B"10100") and
((bit1 xor bit1) = B"00000") and
((bit1 xor bit2) = B"11111") and
((bit2 xor bit1) = B"11111") and
((bit2 xor bit2) = B"00000") and
((not bit1) = bit2) and
((not bit2) = bit1) ) generate
process ( sbit2 )
variable bool : boolean ;
begin
if sbit2 = B"01011" then
locally_static_correct_1 <= true ;
dynamic_correct_1 <=
((sbit1 and sbit1) = B"10100") and
((sbit1 and sbit2) = B"00000") and
((sbit2 and sbit1) = B"00000") and
((sbit2 and sbit2) = B"01011") and
((sbit1 or sbit1) = B"10100") and
((sbit1 or sbit2) = B"11111") and
((sbit2 or sbit1) = B"11111") and
((sbit2 or sbit2) = B"01011") and
((sbit1 nand sbit1) = B"01011") and
((sbit1 nand sbit2) = B"11111") and
((sbit2 nand sbit1) = B"11111") and
((sbit2 nand sbit2) = B"10100") and
((sbit1 nor sbit1) = B"01011") and
((sbit1 nor sbit2) = B"00000") and
((sbit2 nor sbit1) = B"00000") and
((sbit2 nor sbit2) = B"10100") and
((sbit1 xor sbit1) = B"00000") and
((sbit1 xor sbit2) = B"11111") and
((sbit2 xor sbit1) = B"11111") and
((sbit2 xor sbit2) = B"00000") and
((not sbit1) = sbit2) and
((not sbit2) = sbit1) ;
end if ;
end process ;
end generate ;
-- boolean vector
process ( sboolean2 )
variable bool : boolean ;
variable true_vector, false_vector : st_boolean_vector ;
begin
true_vector := (true, true, true, true, true);
false_vector :=(false, false, false, false, false);
if sboolean2 = (false, true, false, true, true) then
locally_static_correct_2 <= true ;
bool := (sboolean1 and sboolean1) = sboolean1 and
(sboolean1 and sboolean2) = false_vector and
(sboolean2 and sboolean1) = false_vector and
(sboolean2 and sboolean2) = sboolean2 and
(sboolean1 or sboolean1) = sboolean1 and
(sboolean1 or sboolean2) = true_vector ;
bool := bool and
(sboolean2 or sboolean1) = true_vector and
(sboolean2 or sboolean2) = sboolean2 and
(sboolean1 nand sboolean1) = sboolean2 and
(sboolean1 nand sboolean2) = true_vector and
(sboolean2 nand sboolean1) = true_vector and
(sboolean2 nand sboolean2) = sboolean1 ;
bool := bool and
(sboolean1 nor sboolean1) = sboolean2 and
(sboolean1 nor sboolean2) = false_vector and
(sboolean2 nor sboolean1) = false_vector and
(sboolean2 nor sboolean2) = sboolean1 and
(sboolean1 xor sboolean1) = false_vector ;
bool := bool and
(sboolean1 xor sboolean2) = true_vector and
(sboolean2 xor sboolean1) = true_vector and
(sboolean2 xor sboolean2) = false_vector and
((not sboolean1) = sboolean2) and
((not sboolean2) = sboolean1) ;
dynamic_correct_2 <= bool ;
end if ;
end process ;
end ARCH00289 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00289_Test_Bench is
end ENT00289_Test_Bench ;
architecture ARCH00289_Test_Bench of ENT00289_Test_Bench is
begin
L1:
block
signal locally_static_correct_1, dynamic_correct_1 : boolean := false ;
signal locally_static_correct_2, dynamic_correct_2 : boolean := false ;
constant local_c_st_bit_vector_1 : st_bit_vector := B"10100";
constant local_c_st_bit_vector_2 : st_bit_vector := B"01011";
component UUT
generic ( bit1, bit2 : st_bit_vector ;
bool1, bool2 : boolean ) ;
port ( locally_static_correct_1, locally_static_correct_2 :
out boolean := false ;
dynamic_correct_1, dynamic_correct_2 : out boolean := false ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00289 ( ARCH00289 ) ;
begin
CIS1 : UUT
generic map ( local_c_st_bit_vector_1, local_c_st_bit_vector_2,
c_boolean_1, c_boolean_2 )
port map ( locally_static_correct_1,
locally_static_correct_2 ,
dynamic_correct_1 ,
dynamic_correct_2 ) ;
process ( locally_static_correct_1, locally_static_correct_2,
dynamic_correct_1, dynamic_correct_2 )
begin
if locally_static_correct_1 and dynamic_correct_1 then
test_report ( "ARCH00289" ,
"Logical operators are correctly predefined"
& " for boolean array types" ,
true ) ;
end if ;
if locally_static_correct_2 and dynamic_correct_2 then
test_report ( "ARCH00289" ,
"Logical operators are correctly predefined"
& " for bit array types" ,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00289_Test_Bench ;
|
-- **************************************************
-- * Circuito de pruebas para la sincronización VGA *
-- **************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_top is
port(
clk , rst : in std_logic;
sw : in std_logic_vector(2 downto 0);
rgb : out std_logic_vector(2 downto 0);
hsinc, vsinc : out std_logic
);
end vga_top;
architecture arq of vga_top is
signal rgb_reg : std_logic_vector(2 downto 0);
signal video_on: std_logic;
begin
-- Instanciar un circuito de sincronización VGA
unidad_vga_sinc: entity work.vga_sinc(arq)
port map(
clk => clk,
rst => rst,
px_tick => open,
video_on => video_on,
pixel_x => open,
pixel_y => open,
hsinc => hsinc,
vsinc => vsinc
);
-- Búfer RGB
process(clk, rst) begin
if rst = '0' then
rgb_reg <= (others => '0');
elsif(rising_edge(clk)) then
rgb_reg <= sw;
end if;
end process;
rgb <= rgb_reg when video_on = '1' else "000";
end arq;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_a_e-e.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_a_e
--
entity inst_a_e is
-- Generics:
-- No Generated Generics for Entity inst_a_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_a_e
widesig_o : out std_ulogic_vector(31 downto 0);
widesig_r_0 : out std_ulogic;
widesig_r_1 : out std_ulogic;
widesig_r_2 : out std_ulogic;
widesig_r_3 : out std_ulogic;
widesig_r_4 : out std_ulogic;
widesig_r_5 : out std_ulogic;
widesig_r_6 : out std_ulogic;
widesig_r_7 : out std_ulogic;
widesig_r_8 : out std_ulogic;
widesig_r_9 : out std_ulogic;
widesig_r_10 : out std_ulogic;
widesig_r_11 : out std_ulogic;
widesig_r_12 : out std_ulogic;
widesig_r_13 : out std_ulogic;
widesig_r_14 : out std_ulogic;
widesig_r_15 : out std_ulogic;
widesig_r_16 : out std_ulogic;
widesig_r_17 : out std_ulogic;
widesig_r_18 : out std_ulogic;
widesig_r_19 : out std_ulogic;
widesig_r_20 : out std_ulogic;
widesig_r_21 : out std_ulogic;
widesig_r_22 : out std_ulogic;
widesig_r_23 : out std_ulogic;
widesig_r_24 : out std_ulogic;
widesig_r_25 : out std_ulogic;
widesig_r_26 : out std_ulogic;
widesig_r_27 : out std_ulogic;
widesig_r_28 : out std_ulogic;
widesig_r_29 : out std_ulogic;
widesig_r_30 : out std_ulogic;
unsplice_a1_no3 : out std_ulogic_vector(127 downto 0); -- leaves 3 unconnected
unsplice_a2_all128 : out std_ulogic_vector(127 downto 0); -- full 128 bit port
unsplice_a3_up100 : out std_ulogic_vector(127 downto 0); -- connect 100 bits from 0
unsplice_a4_mid100 : out std_ulogic_vector(127 downto 0); -- connect mid 100 bits
unsplice_a5_midp100 : out std_ulogic_vector(127 downto 0); -- connect mid 100 bits
unsplice_bad_a : out std_ulogic_vector(127 downto 0);
unsplice_bad_b : out std_ulogic_vector(127 downto 0);
widemerge_a1 : out std_ulogic_vector(31 downto 0);
p_mix_test1_go : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end inst_a_e;
--
-- End of Generated Entity inst_a_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity flashyLights is
Port ( CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0));
end flashyLights;
architecture Behavioral of flashyLights is
COMPONENT counter30 PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(29 DOWNTO 0));
END COMPONENT;
COMPONENT memmory PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
signal count : STD_LOGIC_VECTOR(29 downto 0);
begin
addr_counter : counter30 PORT MAP (
clk => CLK,
q => count
);
rom_memory : memmory
PORT MAP (
clka => CLK,
addra => count(29 downto 20),
douta => LED
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/27/2017 08:36:56 AM
-- Module Name: regfile - Behavioral
-- Description:
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity regfile is
Port(
clk: in std_logic;
rst: in std_logic;
read_addr_1: in std_logic_vector(4 downto 0); -- Register source read_data_1
read_addr_2: in std_logic_vector(4 downto 0); -- Register source read_data_2
write_addr: in std_logic_vector(4 downto 0); -- Write dest write_data
write_data: in doubleword; -- Data to be written
halt: in std_logic; -- Control, do nothing on high
write_en: in std_logic; -- write_data is valid
read_data_1: out doubleword; -- Data from read_addr_1
read_data_2: out doubleword; -- Data from read_addr_2
write_error: out std_logic; -- Writing to constant, HW exception
debug_out: out regfile_arr -- Copy of regfile contents for debugger
);
end regfile;
architecture Behavioral of regfile is
-- Contents of regfile, all zeros
signal reggie: regfile_arr := (others => (others => '0'));
begin
-- Synchronous write
process(clk, rst)
begin
if('1' = halt) then
-- Do nothing
else
write_error <= '0';
if('1' = rst) then
reggie <= (others => (others => '0'));
elsif(rising_edge(clk)) then
if('1' = write_en) then
if("00000" = write_addr) then
write_error <= '1';
else
reggie(to_integer(unsigned(write_addr))) <= write_data;
end if; -- write_error
end if; -- write_en
end if; -- rst
end if; -- halt
end process;
-- Asynchronous read
read_data_1 <= reggie(to_integer(unsigned(read_addr_1)));
read_data_2 <= reggie(to_integer(unsigned(read_addr_2)));
-- Asynchronous debug out
debug_out <= reggie;
end Behavioral; |
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