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entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2) := ( 6, 7 );
assert v(2 to 3) = ( 7, 4 );
wait for 1 ns;
x <= ( 1, 2, 3, 4 );
x(1 to 2) <= ( 6, 7 );
assert x(2 to 3) = ( 7, 4 );
wait for 1 ns;
u := ( 1, 2, 3, 4);
u(4 downto 3) := ( 6, 7 );
assert u(3 downto 2) = ( 7, 4 );
wait;
end process;
end architecture;
|
entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2) := ( 6, 7 );
assert v(2 to 3) = ( 7, 4 );
wait for 1 ns;
x <= ( 1, 2, 3, 4 );
x(1 to 2) <= ( 6, 7 );
assert x(2 to 3) = ( 7, 4 );
wait for 1 ns;
u := ( 1, 2, 3, 4);
u(4 downto 3) := ( 6, 7 );
assert u(3 downto 2) = ( 7, 4 );
wait;
end process;
end architecture;
|
entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2) := ( 6, 7 );
assert v(2 to 3) = ( 7, 4 );
wait for 1 ns;
x <= ( 1, 2, 3, 4 );
x(1 to 2) <= ( 6, 7 );
assert x(2 to 3) = ( 7, 4 );
wait for 1 ns;
u := ( 1, 2, 3, 4);
u(4 downto 3) := ( 6, 7 );
assert u(3 downto 2) = ( 7, 4 );
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 sink interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure, deserialization, phase alignment, channel deskew and
-- decode logic. It outputs 24-bit RGB video data along with pixel clock and
-- synchronization signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvi2rgb is
Generic (
kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
-- 7-series specific
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
-- Auxiliary signals
RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc.
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video out
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic; --pixel-clock recovered from the DVI interface
SerialClk : out std_logic; -- advanced use only; 5x PixelClk
aPixelClkLckd : out std_logic; -- advanced use only; PixelClk and SerialClk stable
-- Optional DDC port
DDC_SDA_I : in std_logic;
DDC_SDA_O : out std_logic;
DDC_SDA_T : out std_logic;
DDC_SCL_I : in std_logic;
DDC_SCL_O : out std_logic;
DDC_SCL_T : out std_logic;
pRst : in std_logic; -- synchronous reset; will restart locking procedure
pRst_n : in std_logic -- synchronous reset; will restart locking procedure
);
end dvi2rgb;
architecture Behavioral of dvi2rgb is
type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0);
signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic;
signal pRdy, pVld, pDE, pAlignErr, pC0, pC1 : std_logic_vector(2 downto 0);
signal pDataIn : dataIn_t;
signal pEyeSize : eyeSize_t;
signal aRst_int, pRst_int : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
pRst_int <= not pRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
pRst_int <= pRst;
end generate ResetActiveHigh;
-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock
TMDS_ClockingX: entity work.TMDS_Clocking
generic map (
kClkRange => kClkRange)
port map (
aRst => aRst_int,
RefClk => RefClk,
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
aLocked => aLocked,
PixelClk => PixelClk_int, -- slow parallel clock
SerialClk => SerialClk_int -- fast serial clock
);
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aLocked,
OutClk => PixelClk_int,
oRst => pLockLostRst);
-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec)
kRefClkFrqMHz => 200, --what is the RefClk frequency
kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap
kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter
port map (
aRst => pLockLostRst,
PixelClk => PixelClk_int,
SerialClk => SerialClk_int,
RefClk => RefClk,
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pAlignErr => pAlignErr(iCh),
pC0 => pC0(iCh),
pC1 => pC1(iCh),
pMeRdy => pRdy(iCh),
pMeVld => pVld(iCh),
pVde => pDE(iCh),
pDataIn(7 downto 0) => pDataIn(iCh),
pEyeSize => pEyeSize(iCh)
);
end generate DataDecoders;
-- RGB Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason video_data uses RBG packing
vid_pData(23 downto 16) <= pDataIn(2); -- red is channel 2
vid_pData(7 downto 0) <= pDataIn(1); -- green is channel 1
vid_pData(15 downto 8) <= pDataIn(0); -- blue is channel 0
vid_pHSync <= pC0(0); -- channel 0 carries control signals too
vid_pVSync <= pC1(0); -- channel 0 carries control signals too
vid_pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once
-- Clock outputs
PixelClk <= PixelClk_int; -- pixel clock sourced from DVI link
SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only
aPixelClkLckd <= aLocked;
----------------------------------------------------------------------------------
-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B)
-- The EDID will be loaded from the file specified below in kInitFileName.
----------------------------------------------------------------------------------
GenerateDDC: if kEmulateDDC generate
DDC_EEPROM: entity work.EEPROM_8b
generic map (
kSampleClkFreqInMHz => 200,
kSlaveAddress => "1010000",
kAddrBits => 7, -- 128 byte EDID 1.x data
kWritable => false,
kInitFileName => "dgl_dvi_edid.txt") -- name of file containing init values
port map(
SampleClk => RefClk,
sRst => '0',
aSDA_I => DDC_SDA_I,
aSDA_O => DDC_SDA_O,
aSDA_T => DDC_SDA_T,
aSCL_I => DDC_SCL_I,
aSCL_O => DDC_SCL_O,
aSCL_T => DDC_SCL_T);
end generate GenerateDDC;
end Behavioral;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declaration of Micron SDRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package components is
component mt48lc16m16a2
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
component mt46v16m16
GENERIC ( -- Timing for -75Z CL2
tCK : TIME := 7.500 ns;
tCH : TIME := 3.375 ns; -- 0.45*tCK
tCL : TIME := 3.375 ns; -- 0.45*tCK
tDH : TIME := 0.500 ns;
tDS : TIME := 0.500 ns;
tIH : TIME := 0.900 ns;
tIS : TIME := 0.900 ns;
tMRD : TIME := 15.000 ns;
tRAS : TIME := 40.000 ns;
tRAP : TIME := 20.000 ns;
tRC : TIME := 65.000 ns;
tRFC : TIME := 75.000 ns;
tRCD : TIME := 20.000 ns;
tRP : TIME := 20.000 ns;
tRRD : TIME := 15.000 ns;
tWR : TIME := 15.000 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
cols_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec"; -- File to read from
bbits : INTEGER := 16;
fdelay : INTEGER := 0;
chktiming : boolean := true
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END component;
component ftmt48lc16m16a2
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec"; -- File to read from
err : INTEGER := 0
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
component ddr2 is
generic(
DM_BITS : integer := 2;
ADDR_BITS : integer := 13;
ROW_BITS : integer := 13;
COL_BITS : integer := 9;
DQ_BITS : integer := 16;
DQS_BITS : integer := 2;
TRRD : integer := 10000;
TFAW : integer := 50000;
DEBUG : integer := 0
);
port (
ck : in std_ulogic;
ck_n : in std_ulogic;
cke : in std_ulogic;
cs_n : in std_ulogic;
ras_n : in std_ulogic;
cas_n : in std_ulogic;
we_n : in std_ulogic;
dm_rdqs : inout std_logic_vector(DQS_BITS-1 downto 0);
ba : in std_logic_vector(1 downto 0);
addr : in std_logic_vector(ADDR_BITS-1 downto 0);
dq : inout std_logic_vector(DQ_BITS-1 downto 0);
dqs : inout std_logic_vector(DQS_BITS-1 downto 0);
dqs_n : inout std_logic_vector(DQS_BITS-1 downto 0);
rdqs_n : out std_logic_vector(DQS_BITS-1 downto 0);
odt : in std_ulogic
);
end component;
component mobile_ddr
--GENERIC ( -- Timing for -75Z CL2
-- tCK : TIME := 7.500 ns;
-- tCH : TIME := 3.375 ns; -- 0.45*tCK
-- tCL : TIME := 3.375 ns; -- 0.45*tCK
-- tDH : TIME := 0.500 ns;
-- tDS : TIME := 0.500 ns;
-- tIH : TIME := 0.900 ns;
-- tIS : TIME := 0.900 ns;
-- tMRD : TIME := 15.000 ns;
-- tRAS : TIME := 40.000 ns;
-- tRAP : TIME := 20.000 ns;
-- tRC : TIME := 65.000 ns;
-- tRFC : TIME := 75.000 ns;
-- tRCD : TIME := 20.000 ns;
-- tRP : TIME := 20.000 ns;
-- tRRD : TIME := 15.000 ns;
-- tWR : TIME := 15.000 ns;
-- addr_bits : INTEGER := 13;
-- data_bits : INTEGER := 16;
-- cols_bits : INTEGER := 9;
-- index : INTEGER := 0;
-- fname : string := "ram.srec"; -- File to read from
-- bbits : INTEGER := 32
--);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
----Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'Z');
----Dqs : INOUT STD_LOGIC_VECTOR (data_bits/8 - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
----Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
----Dm : IN STD_LOGIC_VECTOR (data_bits/8 - 1 DOWNTO 0)
);
END component;
component mobile_ddr_fe
generic (addr_swap : integer := 0);
port (
Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
BEaddr: out std_logic_vector (24 downto 0);
BEwr : out std_logic_vector(1 downto 0);
BEdin : out std_logic_vector(15 downto 0);
BEdout: in std_logic_vector(15 downto 0);
BEclear: out std_logic;
BEclrpart: out std_logic;
BEsynco: out std_logic;
BEsynci: in std_logic
);
end component;
component mobile_ddr_febe
generic (
dbits: integer := 32;
rampad: integer := 0;
fname: string := "dummy";
autoload: integer := 1;
rstmode: integer := 0;
rstdatah: integer := 16#DEAD#;
rstdatal: integer := 16#BEEF#;
addr_swap : integer := 0;
offset_addr : std_logic_vector(31 downto 0) := x"00000000";
swap_halfw : integer := 0
);
port (
Dq : INOUT STD_LOGIC_VECTOR (dbits-1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (dbits/8-1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (dbits/8-1 DOWNTO 0)
);
end component;
component mobile_ddr2_fe
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ca : in std_logic_vector( 9 downto 0);
dm : in std_logic_vector( 1 downto 0);
dq : inout std_logic_vector(15 downto 0) := (OTHERS => 'Z');
dqs : inout std_logic_vector( 1 downto 0) := (OTHERS => 'Z');
dqs_n : inout std_logic_vector( 1 downto 0) := (OTHERS => 'Z');
BEaddr : out std_logic_vector(27 downto 0);
BEwr_h : out std_logic_vector( 1 downto 0);
BEwr_l : out std_logic_vector( 1 downto 0);
BEdin_h : out std_logic_vector(15 downto 0);
BEdin_l : out std_logic_vector(15 downto 0);
BEdout_h: in std_logic_vector(15 downto 0);
BEdout_l: in std_logic_vector(15 downto 0);
BEclear : out std_logic;
BEreload: out std_logic;
BEsynco : out std_logic;
BEsynci : in std_logic
);
end component;
component mobile_ddr2_febe
generic (
dbits: integer := 32;
rampad: integer := 0;
fname: string := "dummy";
autoload: integer := 1;
rstmode: integer := 0;
rstdatah: integer := 16#DEAD#;
rstdatal: integer := 16#BEEF#
);
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ca : in std_logic_vector( 9 downto 0);
dm : in std_logic_vector(dbits/8-1 downto 0);
dq : inout std_logic_vector( dbits-1 downto 0) := (OTHERS => 'Z');
dqs : inout std_logic_vector(dbits/8-1 downto 0) := (OTHERS => 'Z');
dqs_n : inout std_logic_vector(dbits/8-1 downto 0) := (OTHERS => 'Z')
);
end component;
component mobile_sdr
--GENERIC (
-- DEBUG : INTEGER := 1;
-- addr_bits : INTEGER := 13;
-- data_bits : INTEGER := 16
--);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
end;
-- pragma translate_on
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy_datapath
-- File: ddrphy_datapath.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR/DDR2 PHY data path (digital part of phy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ddrphy_datapath is
generic (
regtech: integer := 0;
dbits: integer;
abits: integer;
bankbits: integer range 2 to 3 := 2;
ncs: integer;
nclk: integer;
-- Enable extra resync stage clocked by clkresync
resync: integer range 0 to 2 := 0
);
port (
clk0: in std_ulogic;
clk90: in std_ulogic;
clk180: in std_ulogic;
clk270: in std_ulogic;
clkresync: in std_ulogic;
ddr_clk: out std_logic_vector(nclk-1 downto 0);
ddr_clkb: out std_logic_vector(nclk-1 downto 0);
ddr_dq_in: in std_logic_vector(dbits-1 downto 0);
ddr_dq_out: out std_logic_vector(dbits-1 downto 0);
ddr_dq_oen: out std_logic_vector(dbits-1 downto 0);
ddr_dqs_in90: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_in90n: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_out: out std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_oen: out std_logic_vector(dbits/8-1 downto 0);
ddr_cke: out std_logic_vector(ncs-1 downto 0);
ddr_csb: out std_logic_vector(ncs-1 downto 0);
ddr_web: out std_ulogic;
ddr_rasb: out std_ulogic;
ddr_casb: out std_ulogic;
ddr_ad: out std_logic_vector(abits-1 downto 0);
ddr_ba: out std_logic_vector(bankbits-1 downto 0);
ddr_dm: out std_logic_vector(dbits/8-1 downto 0);
ddr_odt: out std_logic_vector(ncs-1 downto 0);
-- Control signals synchronous to clk0
dqin: out std_logic_vector(dbits*2-1 downto 0);
dqout: in std_logic_vector(dbits*2-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (bankbits-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0); -- Clk enable control signal to memory
odt : in std_logic_vector(ncs-1 downto 0);
dqs_en : in std_ulogic; -- Run dqs strobe (active low)
dqs_oen : in std_ulogic; -- DQS output enable (active low)
ddrclk_en : in std_logic_vector(nclk-1 downto 0) -- Enable/stop ddr_clk
);
end;
architecture rtl of ddrphy_datapath is
signal vcc,gnd: std_ulogic;
signal dqs_en_inv,dqs_en_inv180: std_ulogic;
signal dqcaptr,dqcaptf: std_logic_vector(dbits-1 downto 0);
signal dqsyncr,dqsyncf: std_logic_vector(dbits-1 downto 0);
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- DDR interface clock signal
-----------------------------------------------------------------------------
-- 90 degree shifted relative to master clock, gated by ddrclk_en
genclk: for x in 0 to nclk-1 generate
clkreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => ddrclk_en(x), d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clk(x));
clkbreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => gnd, d2 => ddrclk_en(x), ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clkb(x));
end generate;
-----------------------------------------------------------------------------
-- Control signals RAS,CAS,WE,BA,ADDR,CS,ODT,CKE
-----------------------------------------------------------------------------
rasreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => rasn, q => ddr_rasb);
casreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => casn, q => ddr_casb);
wereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => wen, q => ddr_web);
genba: for x in 0 to bankbits-1 generate
bareg: grdff generic map (tech => regtech)
port map (clk => clk0, d => ba(x), q => ddr_ba(x));
end generate;
gencs: for x in 0 to ncs-1 generate
csreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => csn(x), q => ddr_csb(x));
ckereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => cke(x), q => ddr_cke(x));
odtreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => odt(x), q => ddr_odt(x));
end generate;
genaddr: for x in 0 to abits-1 generate
addrreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => addr(x), q => ddr_ad(x));
end generate;
-----------------------------------------------------------------------------
-- Outgoing data, output enable, DQS, DQSOEN, DM
-----------------------------------------------------------------------------
gendqout: for x in 0 to dbits-1 generate
dqoutreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqout(x+dbits), d2 => dqout(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dq_out(x));
dqoenreg: grdff
generic map (tech => regtech)
port map (clk => clk0, d => oen, q => ddr_dq_oen(x));
end generate;
-- dqs_en -> invert -> delay -> +90-deg DDR-regs -> dqs_out
-- In total oen is delayed 5/4 cycles. We use 1/2 cycle delay
-- instead of 1 cycle delay to get better timing margin to DDR regs.
-- DQSOEN is delayed one cycle just like ctrl sigs
dqs_en_inv <= not dqs_en;
dqseninv180reg: grdff
generic map (tech => regtech)
port map (clk => clk180, d => dqs_en_inv, q => dqs_en_inv180);
gendqsout: for x in 0 to dbits/8-1 generate
dqsreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqs_en_inv180, d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_dqs_out(x));
dqsoenreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqs_oen, q => ddr_dqs_oen(x));
end generate;
gendm: for x in 0 to dbits/8-1 generate
dmreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dm(x+dbits/8), d2 => dm(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dm(x));
end generate;
-----------------------------------------------------------------------------
-- Incoming data
-----------------------------------------------------------------------------
gendqin: for x in 0 to dbits-1 generate
-- capture using dqs+90
-- Note: The ddr_ireg delivers both edges on c1 rising edge, therefore c1
-- is connected to inverted clock (c1 rising edge == dqs falling edge)
dqcaptreg: ddr_ireg generic map (tech => regtech)
port map (d => ddr_dq_in(x),
c1 => ddr_dqs_in90n(x/8), c2 => ddr_dqs_in90(x/8), ce => vcc, r => gnd, s => gnd,
q1 => dqcaptf(x), q2 => dqcaptr(x));
-- optional extra resync stage
ifresync: if resync=1 generate
genresync: for x in 0 to dbits-1 generate
dqsyncrreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptr(x), q => dqsyncr(x));
dqsyncfreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptf(x), q => dqsyncf(x));
end generate;
end generate;
noresync: if resync/=1 generate
dqsyncr <= dqcaptr;
dqsyncf <= dqcaptf;
end generate;
-- sample in clk0 domain
gensamp: if resync/=2 generate
dqinregr: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncr(x), q => dqin(x+dbits));
dqinregf: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncf(x), q => dqin(x));
end generate;
nosamp: if resync=2 generate
dqin(x+dbits) <= dqsyncr(x);
dqin(x) <= dqsyncf(x);
end generate;
end generate;
end;
|
-- File: pck_myhdl_08.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Mar 8 21:33:13 2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_08 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
end pck_myhdl_08;
package body pck_myhdl_08 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
end pck_myhdl_08;
|
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessordf_types.all;
entity packetprocessordf_testbench is
port(done : out boolean);
end;
architecture structural of packetprocessordf_testbench is
signal finished : boolean;
signal system1000 : std_logic;
signal system1000_rstn : std_logic;
signal i : packetprocessordf_types.tup2;
signal result : packetprocessordf_types.counterstate;
begin
done <= finished;
-- pragma translate_off
process is
begin
system1000 <= '0';
wait for 3 ns;
while (not finished) loop
system1000 <= not system1000;
wait for 500 ns;
system1000 <= not system1000;
wait for 500 ns;
end loop;
wait;
end process;
-- pragma translate_on
-- pragma translate_off
system1000_rstn <= '0',
'1' after 2 ns;
-- pragma translate_on
totest : entity packetprocessordf_topentity_0
port map
(system1000 => system1000
,system1000_rstn => system1000_rstn
,i => i
,result => result);
i <= packetprocessordf_types.tup2'(std_logic_vector'(0 to 28 => 'X'),true);
finished <=
-- pragma translate_off
false,
-- pragma translate_on
true
-- pragma translate_off
after 100 ns
-- pragma translate_on
;
end;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_ch_16_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_16_06 is
end entity ch_16_06;
----------------------------------------------------------------
architecture test of ch_16_06 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
signal source_bus_1, source_bus_2 : resolved_word bus;
signal address_bus : resolved_word bus;
-- code from book:
disconnect address_bus : resolved_word after 3 ns;
disconnect others : resolved_word after 2 ns;
-- end of code from book
signal s : word;
signal g : boolean;
begin
b : block (g) is
begin
source_bus_1 <= guarded s after 4 ns;
source_bus_2 <= guarded s after 4 ns;
address_bus <= guarded s after 4 ns;
end block b;
stimulus : process is
begin
s <= X"DDDDDDDD";
wait for 10 ns;
g <= true;
wait for 10 ns;
s <= X"AAAAAAAA";
wait for 10 ns;
g <= false;
wait for 10 ns;
s <= X"11111111";
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_ch_16_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_16_06 is
end entity ch_16_06;
----------------------------------------------------------------
architecture test of ch_16_06 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
signal source_bus_1, source_bus_2 : resolved_word bus;
signal address_bus : resolved_word bus;
-- code from book:
disconnect address_bus : resolved_word after 3 ns;
disconnect others : resolved_word after 2 ns;
-- end of code from book
signal s : word;
signal g : boolean;
begin
b : block (g) is
begin
source_bus_1 <= guarded s after 4 ns;
source_bus_2 <= guarded s after 4 ns;
address_bus <= guarded s after 4 ns;
end block b;
stimulus : process is
begin
s <= X"DDDDDDDD";
wait for 10 ns;
g <= true;
wait for 10 ns;
s <= X"AAAAAAAA";
wait for 10 ns;
g <= false;
wait for 10 ns;
s <= X"11111111";
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_ch_16_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_16_06 is
end entity ch_16_06;
----------------------------------------------------------------
architecture test of ch_16_06 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
signal source_bus_1, source_bus_2 : resolved_word bus;
signal address_bus : resolved_word bus;
-- code from book:
disconnect address_bus : resolved_word after 3 ns;
disconnect others : resolved_word after 2 ns;
-- end of code from book
signal s : word;
signal g : boolean;
begin
b : block (g) is
begin
source_bus_1 <= guarded s after 4 ns;
source_bus_2 <= guarded s after 4 ns;
address_bus <= guarded s after 4 ns;
end block b;
stimulus : process is
begin
s <= X"DDDDDDDD";
wait for 10 ns;
g <= true;
wait for 10 ns;
s <= X"AAAAAAAA";
wait for 10 ns;
g <= false;
wait for 10 ns;
s <= X"11111111";
wait;
end process stimulus;
end architecture test;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:35:20 11/27/2016
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.PIC_pkg.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
port ( Reset : in std_logic; -- asynnchronous, active low
Clk : in std_logic; -- System clock, 20 MHz, rising_edge
u_instruction : in alu_op; -- u-instructions from CPU
FlagZ : out std_logic; -- Zero flag
-- FlagC : out std_logic; -- Carry flag
-- FlagN : out std_logic; -- Nibble carry bit
-- FlagE : out std_logic; -- Error flag
Index_Reg : out std_logic_vector(7 downto 0); -- Index register
Databus : inout std_logic_vector(7 downto 0)); -- System Data bus
end ALU;
architecture Behavioral of ALU is
signal operandoA : std_logic_vector(7 downto 0);
signal operandoB : std_logic_vector(7 downto 0);
signal acumulador : std_logic_vector(7 downto 0);
signal index : std_logic_vector(7 downto 0);
signal Flag_Z: std_logic;
begin
process(Clk, Databus, Reset)
begin
if Reset = '0' then
operandoA <= (others => '0');
operandoB <= (others => '0');
acumulador <= (others => '0');
index <= (others => '0');
Flag_Z <= '0';
Databus <= (others => 'Z');
elsif Clk'event and Clk = '1' then
Flag_Z <= '0';
case u_instruction is
when nop =>
Databus <= (others => 'Z');
when op_lda =>
operandoA <= Databus;
when op_ldb =>
operandoB <= Databus;
when op_ldacc =>
acumulador <= Databus;
when op_ldid =>
index <= Databus;
when op_mvacc2id =>
index <= acumulador;
Databus <= (others => 'Z');
when op_mvacc2a =>
operandoA <= acumulador;
Databus <= (others => 'Z');
when op_mvacc2b =>
operandoB <= acumulador;
Databus <= (others => 'Z');
when op_add =>
acumulador <= operandoA + operandoB;
if (operandoA + operandoB) = X"00" then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_sub =>
acumulador <= operandoA - operandoB;
if (operandoA - operandoB) = X"00" then
Flag_Z <= '0';
end if;
Databus <= (others => 'Z');
when op_shiftl =>
acumulador <= acumulador(7 downto 1) & '0';
Databus <= (others => 'Z');
when op_shiftr =>
acumulador <= '0' & acumulador(6 downto 0);
Databus <= (others => 'Z');
when op_and =>
acumulador <= operandoA and operandoB;
if (operandoA and operandoB) = X"00" then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_or =>
acumulador <= operandoA or operandoB;
if (operandoA or operandoB) = X"00" then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_xor =>
acumulador <= operandoA xor operandoB;
if (operandoA xor operandoB) = X"00" then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_cmpe =>
if (operandoA = OperandoB) then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_cmpl =>
if (operandoA < OperandoB) then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_cmpg =>
if (operandoA > OperandoB) then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_ascii2bin =>
Databus <= (others => 'Z');
if operandoA = X"30" then
acumulador <= X"00";
elsif operandoA = X"31" then
acumulador <= X"01";
elsif operandoA = X"32" then
acumulador <= X"02";
elsif operandoA = X"33" then
acumulador <= X"03";
elsif operandoA = X"34" then
acumulador <= X"04";
elsif operandoA = X"35" then
acumulador <= X"05";
elsif operandoA = X"36" then
acumulador <= X"06";
elsif operandoA = X"37" then
acumulador <= X"07";
elsif operandoA = X"38" then
acumulador <= X"08";
elsif operandoA = X"39" then
acumulador <= X"09";
else
acumulador <= X"FF";
end if;
when op_bin2ascii =>
Databus <= (others => 'Z');
if operandoA = 0 then
acumulador <= X"30";
elsif operandoA = 1 then
acumulador <= X"31";
elsif operandoA = 2 then
acumulador <= X"32";
elsif operandoA = 3 then
acumulador <= X"33";
elsif operandoA = 4 then
acumulador <= X"34";
elsif operandoA = 5 then
acumulador <= X"35";
elsif operandoA = 6 then
acumulador <= X"36";
elsif operandoA = 7 then
acumulador <= X"37";
elsif operandoA = 8 then
acumulador <= X"38";
elsif operandoA = 9 then
acumulador <= X"39";
elsif operandoA = 10 then
acumulador <= X"41"; -- A
elsif operandoA = 11 then
acumulador <= X"42"; -- B
elsif operandoA = 12 then
acumulador <= X"43"; -- C
elsif operandoA = 13 then
acumulador <= X"44"; -- D
elsif operandoA = 14 then
acumulador <= X"45"; -- E
elsif operandoA = 15 then
acumulador <= X"46"; -- F
else
acumulador <= X"FF";
end if;
when op_oeacc =>
Databus <= acumulador;
when others =>
Databus <= (others => 'Z');
end case;
FlagZ <= Flag_Z;
Index_Reg <= index;
end if;
end process;
end Behavioral;
|
entity ram1 is
end entity;
architecture test of ram1 is
type byte_array_t is array (natural range <>) of bit_vector(7 downto 0);
signal ram : byte_array_t(15 downto 0);
signal addr : integer;
signal dout : bit_vector(7 downto 0);
signal din : bit_vector(7 downto 0);
signal we : bit;
begin
dout_p: dout <= ram(addr);
wr_p: process (we, din, addr) is
begin
if we = '1' then
ram(addr) <= din;
end if;
end process;
end architecture;
|
process(CLK)
begin
if(CLK = '1' and CLK'event) then
Q <= D;
end if;
end process;
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
-- Testbench for FIR Moving Average filter which averages L points
entity Testbench is
end Testbench;
architecture test of Testbench is
-- Constants to initialize generics of DUT
constant L : natural := 256;
constant L_BW : natural := natural(ceil(log2(real(L))));
constant W : natural := 16;
-- Simulation control
constant CLK_CYCLE_TIME : time := 10 ns;
signal sim_end : boolean := false;
signal sample_cnt : natural := 1024;--natural(2**(W-1));
-- Signals to connect ports of DUT
signal clk : std_logic := '0'; -- clock
signal reset_n : std_logic := '0'; -- active low asynchronous reset
signal fir_en : std_logic := '0'; -- handshake signal
signal fir_in : std_logic_vector( W-1 downto 0 ) := ( others => '0' ); -- sample inout x[n]
signal fir_out : std_logic_vector( W-1 downto 0 ) := ( others => '0' ); -- sample output y[n]
signal fir_rdy : std_logic := '0'; -- handshake signal
begin
-- create instance of FIR Filter (DUT)
DUT: entity work.fir(rtl)
generic map ( L => L, -- L = Filter length or number of points to be averaged
L_BW => L_BW, -- L_BW = Ceil(Log2(L))
W => W -- W = Bit width of input and output sample data (signed)
)
port map ( clk => clk, -- clock
reset_n => reset_n, -- active low asynchronous reset
fir_en => fir_en, -- handshake signal
fir_in => fir_in, -- sample inout x[n]
fir_out => fir_out, -- sample output y[n]
fir_rdy => fir_rdy -- handshake signal
);
-- Clock generation
clk_gen: process
begin
if( not sim_end ) then
clk <= '0';
wait for CLK_CYCLE_TIME/2;
clk <= '1';
wait for CLK_CYCLE_TIME/2;
else
wait;
end if;
end process clk_gen;
-- Reset generation
reset_n <= '0',
'1' after 1.3*CLK_CYCLE_TIME;
-- test vectors
stimulus : process
variable seed1, seed2 : positive := 1;
variable x: real := 0.0;
variable en: std_logic := '0';
procedure apply_stimulus( constant en : in std_logic;
constant x : in integer;
constant DELAY: in time ) is
begin
fir_en <= en;
fir_in <= std_logic_vector( to_signed( x, fir_in'LENGTH ) );
wait for DELAY;
end procedure apply_stimulus;
procedure apply_stimulus( constant en : in std_logic;
constant x : in integer ) is
begin
fir_en <= en;
fir_in <= std_logic_vector( to_signed( x, fir_in'LENGTH ) );
end procedure apply_stimulus;
begin
-- Reset
en := '0';
x := 0.0;
apply_stimulus( en, integer(x) );
wait until reset_n = '1';
for i in 1 to 4 loop
wait until falling_edge( clk );
end loop;
-- Enable filter and wait for M clock cycles (falling edges)
en := '1';
apply_stimulus( en, integer(x) );
-- Apply simple increasing stimulus
for i in 0 to (sample_cnt-1) loop
wait until falling_edge( clk );
apply_stimulus( en, i+1 );
end loop;
-- Apply random stimulus
for i in 0 to (sample_cnt-1) loop
wait until falling_edge( clk );
-- x = random number between 0.0 and 1.0 (exclusive)
uniform( seed1, seed2, x );
apply_stimulus( en, integer(floor(x * real(2**W))) );
end loop;
-- Apply upward trend stimulus
for i in 0 to (sample_cnt-1) loop
wait until falling_edge( clk );
if ( i rem 4 = 0 ) then
-- x = random number between 0.0 and 1.0 (exclusive)
uniform( seed1, seed2, x );
apply_stimulus( en, integer(floor(x * real(2**W))) );
else
apply_stimulus( en, i );
end if;
end loop;
-- Apply downward trend stimulus
for i in (sample_cnt-1) downto 0 loop
wait until falling_edge( clk );
if ( i rem 4 = 0 ) then
-- x = random number between 0.0 and 1.0 (exclusive)
uniform( seed1, seed2, x );
apply_stimulus( en, integer(floor(x * real(2**W))) );
else
apply_stimulus( en, i );
end if;
end loop;
-- Disable the filter
wait until falling_edge( clk );
en := '0';
apply_stimulus( en, 0 );
wait until falling_edge( clk );
wait until falling_edge( clk );
-- End simulation
sim_end <= true;
wait;
end process stimulus;
end architecture test; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux2x1_10:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux2x1_10_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC;
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END RAT_Mux2x1_10_0_0;
ARCHITECTURE RAT_Mux2x1_10_0_0_arch OF RAT_Mux2x1_10_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux2x1_10_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Mux2x1_10 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC;
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT Mux2x1_10;
BEGIN
U0 : Mux2x1_10
PORT MAP (
A => A,
B => B,
SEL => SEL,
X => X
);
END RAT_Mux2x1_10_0_0_arch;
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
|
-- Baudrate Generator
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity baudrategenerator is
generic
(
NUM_BAUD_CLOCK_TICKS : unsigned := to_unsigned(417-1,9); -- 8.000.000 / 19200 = 417
TX_TRIGGER_VALUE : unsigned := to_unsigned(1-1,9) -- ???
);
port
(
clk : in std_logic;
enable : in std_logic;
rst_n : in std_logic;
trigger_flag : out std_logic
);
end entity;
architecture rtl of baudrategenerator is
component counter
port
(
clk : in std_logic;
enable : in std_logic;
rst_n : in std_logic;
clear : in std_logic;
cnt_out : out std_logic_vector(9 downto 0)
);
end component;
signal cnt_out : std_logic_vector(9 downto 0);
signal cnt_clear : std_logic;
signal cnt_flag : std_logic := '0';
begin
cnt : counter port map
(
clk => clk,
enable => enable,
rst_n => rst_n,
clear => cnt_clear,
cnt_out => cnt_out
);
cnt_clear <= (not enable) or cnt_flag;
cnt_flag <= '1' when ((unsigned(cnt_out) = NUM_BAUD_CLOCK_TICKS)) else '0';
trigger_flag <= enable when ((unsigned(cnt_out) = TX_TRIGGER_VALUE)) else '0';
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
-- framebuffer access
data_i : in std_logic_vector(7 downto 0);
write_row_i : in std_logic;
write_column_i : in std_logic;
write_color_i : in std_logic;
-- VGA output
hsync_o : out std_logic;
vsync_o : out std_logic;
red_o : out std_logic_vector(2 downto 0);
green_o : out std_logic_vector(2 downto 0);
blue_o : out std_logic_vector(1 downto 0)
);
end vga;
architecture behavioral of vga is
-- output
signal color : std_logic_vector(7 downto 0);
-- delay
signal hsync_delay1 : std_logic;
signal vsync_delay1 : std_logic;
signal column_enable_delay1 : std_logic;
signal row_enable_delay1 : std_logic;
signal hsync_delay2 : std_logic;
signal vsync_delay2 : std_logic;
signal color_delay2 : std_logic_vector(7 downto 0);
-- registers
signal reg_row : std_logic_vector(4 downto 0);
signal reg_column : std_logic_vector(5 downto 0);
-- hsync
signal hcount : std_logic_vector(10 downto 0);
signal row_clock : std_logic;
signal hsync : std_logic;
signal column_enable : std_logic;
-- vsync
signal vcount : std_logic_vector(9 downto 0);
signal vsync : std_logic;
signal row_enable : std_logic;
-- framebuffer
type frame_type is array(0 to 2047) of std_logic_vector(7 downto 0);
signal frame : frame_type := (others => (others => '0'));
signal frame_addr_out : std_logic_vector(10 downto 0);
signal frame_data_out : std_logic_vector(7 downto 0);
signal frame_addr_in : std_logic_vector(10 downto 0);
begin
hsync_o <= hsync_delay2;
vsync_o <= vsync_delay2;
red_o <= color_delay2(7 downto 5);
green_o <= color_delay2(4 downto 2);
blue_o <= color_delay2(1 downto 0);
-- delay
process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
hsync_delay1 <= '0';
vsync_delay1 <= '0';
column_enable_delay1 <= '0';
row_enable_delay1 <= '0';
vsync_delay1 <= '0';
hsync_delay2 <= '0';
vsync_delay2 <= '0';
color_delay2 <= (others => '0');
else
hsync_delay1 <= hsync;
vsync_delay1 <= vsync;
column_enable_delay1 <= column_enable;
row_enable_delay1 <= row_enable;
hsync_delay2 <= hsync_delay1;
vsync_delay2 <= vsync_delay1;
color_delay2 <= color;
end if;
end if;
end process;
-- registers
process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_row <= (others => '0');
else
if (write_row_i ='1') then
reg_row <= data_i(4 downto 0);
else
reg_row <= reg_row;
end if;
end if;
end if;
end process;
process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_column <= (others => '0');
else
if (write_column_i = '1') then
reg_column <= data_i(5 downto 0);
else
reg_column <= reg_column;
end if;
end if;
end if;
end process;
-- hsync
process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
hcount <= (others => '0');
else
if (hcount = 1600 - 1) then
hcount <= (others => '0');
else
hcount <= hcount + 1;
end if;
end if;
end if;
end process;
process(hcount)
begin
if (hcount = 1600 - 1) then
row_clock <= '1';
else
row_clock <= '0';
end if;
if (hcount < 1280) then
column_enable <= '1';
else
column_enable <= '0';
end if;
if (hcount >= (1280 + 96) and hcount < (1280 + 96 + 192)) then
hsync <= '0';
else
hsync <= '1';
end if;
end process;
-- vsync
process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
vcount <= (others => '0');
elsif (row_clock = '1') then
if (vcount = 521 - 1) then
vcount <= (others => '0');
else
vcount <= vcount + 1;
end if;
else
vcount <= vcount;
end if;
end if;
end process;
process(vcount)
begin
if (vcount < 480) then
row_enable <= '1';
else
row_enable <= '0';
end if;
if (vcount >= (480 + 29) and vcount < (480 + 29 + 2)) then
vsync <= '0';
else
vsync <= '1';
end if;
end process;
-- framebuffer
frame_addr_out <= vcount(8 downto 4) & hcount(10 downto 5);
frame_addr_in <= reg_row & reg_column;
process(clock_i)
begin
if (rising_edge(clock_i)) then
frame_data_out <= frame(conv_integer(frame_addr_out));
end if;
end process;
process (clock_i)
begin
if (rising_edge(clock_i)) then
if (write_color_i = '1') then
frame(conv_integer(frame_addr_in)) <= data_i;
end if;
end if;
end process;
-- output
process(column_enable_delay1, row_enable_delay1, frame_data_out)
begin
if (column_enable_delay1 = '1' and
row_enable_delay1 ='1') then
color <= frame_data_out;
else
color <= (others => '0');
end if;
end process;
end behavioral;
|
-- synthesis library lib
--------------------------------------------------------------------
-- Project : SPI receivers master
-- Author : AlexRayne
-- Date : 2009.03.16.03
-- File :
-- Design :
--------------------------------------------------------------------
-- Description : (win1251) SPI мастер-приемник с минимальными затратами ресурсов.
-- и возможностью выдачи shut-down посылки. Преназначено для загрузки АЦП AD747x.
-- Может загружать настраиваемую часть SPI последовательности (кусок).
-- формирует последовательность вхождения и выхода из посылки сигналов nSS и SCK:
-- посылка обозначается активным nSS('0'), на старте посылки SCK='1' полтакта
-- загружаются биты по переднему фронту SCK, последний бит посылки неимеет заднего
-- фронта, SCK = '1' все пассивное время.
-- Description : SPI master-receiver minimalistic costs
-- intended for loading ADC AD747x, capable produce shut-down frames.
-- can load tunable part of frame. generate entry/exit sequences on nSS, SCK:
-- activate nSS='0' on frame transfer, SCK='1' for half clock cycle at frame start,
-- data loads on rising front SCK, last frame bit have no falling edge SCK,
-- SCK='1' durung inactive period.
-- SDLen, SDMax:
-- sets len of short spi sequence for poweroff purposes short (SDLen) and maximum (SDMax) length
-- QuietLen:
-- requred TimeOut before start
-- Start:
--Start lock on rising CLK, and changes ignores during transmition. if one still high after transmition
-- ends, then new frame starts after QuietLen timeout if ContinueStart not active
-- ContinueStart:
-- if false then spi produce controling sequense of xfer entry and inter-frame pause
-- else spi start new frame xfer immeidate after completing current frame
-- ShutDown
-- locks by high level, after Shuting down complete new SutDown sequence can be forced by Start
-- if one activate during transmition, then it forces current frame to close if it can (beetween SDLen..SDMax bits)
-- or generate short shutdown frame after completing current frae else
-- Ready:
-- rising edge of ready can be used for loading DQ data to dest.
-- Shift:
-- shift clock for internal data register intended to expand load logic to parallel loading registers,
-- to make a multi chanel reciever
-- Sleeping
-- State of ADC power mode - is it shutdowned.
--------------------------------------------------------------------
-- $Log$
--------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY AdcRecv IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
GENERIC(
SPILen : positive := 16;
DataLen : positive := 16;
DataOffset : natural := 0;
SDLen : natural := 1;
SDMax : natural := 10;
QuietLen : natural := 1
);
PORT
(
CLK : IN STD_LOGIC;
Start : IN STD_LOGIC;
ContinueStart : in STD_LOGIC := '0';
ShutDown: IN STD_LOGIC;
reset : IN STD_LOGIC;
SDI : IN STD_LOGIC;
SCK : OUT STD_LOGIC;
nSS : OUT STD_LOGIC;
DQ : OUT std_logic_vector(DataLen-1 downto 0);--STD_LOGIC_2D(Chanels-1 downto 0, DataLen-1 downto 0);
Ready : OUT STD_LOGIC;
Shift : OUT STD_LOGIC;
Sleeping : OUT STD_LOGIC
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END AdcRecv;
-- Architecture Body
ARCHITECTURE BEH OF AdcRecv IS
signal SS : std_logic;
signal Data : std_logic_vector(DataLen-1 downto 0);
signal iSCK : std_logic;
signal iReady : std_logic;
subtype BitIndex is natural range 0 to SPILen-1;
signal BitNo : BitIndex;
subtype QuietIndex is natural range 0 to QuietLen;
signal QuietCnt : QuietIndex;
signal QuietOk : std_logic;
signal isLastBit : std_logic;
signal isLastDataBit: std_logic;
signal isFirstBit : std_logic;
signal Transfer : std_logic := '0';
signal PrepTransfer : std_logic := '0';
signal ReceiveWindow : std_logic := '0';
type States is ( stSerLoading, stQuietCheck); --stReady,
signal FSMState : States := stQuietCheck;
signal NextState : States;
signal SDEnough : std_logic;
signal SDDone : std_logic;
signal NeedSD : std_logic;
signal Enable : std_logic;
begin
BitCounter : process(CLK, reset, Enable, Transfer, isLastBit, FSMState) is begin
if (reset = '1') or (FSMState = stQuietCheck) then -- (Enable = '0') then
BitNo <= 0;
else
if falling_edge(CLK) then
if isLastBit = '1' then
BitNo <= 0;
else
if Transfer = '1' then
BitNo <= BitNo+1;
end if;
end if;
end if;
end if;
end process;
isFirstBit <= '1' when (BitNo = 0) else '0';
isLastBit <= '1' when (BitNo = SPILen-1) else '0';
isLastDataBit <= '1'when (BitNo = DataOffset + DataLen-1) else '0';
ReceiveWindow <= '1' when (BitNo >= DataOffset) and (BitNo <= DataOffset + DataLen-1)
else '0';
SDEnough <= '1' when (BitNo >= SDLen) and (BitNo < SDMax) else '0';
SDmonitor : process(SS, enable, iSCK, NeedSD, SDEnough, Reset) is begin
if (reset = '1') or (iSCK = '0') then
SDDone <= '0';
elsif falling_edge(enable) then
SDDone <= SDEnough;
end if;
end process;
Sleeping <= SDDone;
Qsafer: if QuietLen > 1 generate
QuietOk <= '1' when (QuietCnt >= QuietLen) else '0';
QuietCounter: process(FSMState, reset, CLK, QuietOk) is begin
if (reset = '1')
or (FSMState = stSerLoading)
then
QuietCnt <= 0;
else
if rising_edge(CLK) then
if QuietOk = '0' then
QuietCnt <= QuietCnt+1;
end if;
end if;
end if;
end process;
end generate;
EmptyQsafer: if QuietLen <= 1 generate
QuietOk <= '1';
end generate;
EnableReg: process(Start, NeedSD, iReady, NextState, FSMState, CLK, Reset) is begin
if (reset = '1') then
Enable <= '0';
elsif rising_edge(CLK) then
if (iReady and (Start or NeedSD)) = '1' then
Enable <= '1';
else
if (FSMState = stSerLoading) and (NextState /= stSerLoading) then
Enable <= '0';
end if;
end if;
end if;
end process;
SDRequest: process(ShutDown, SDDone, Reset) is begin
if (Reset = '1') or (SDDone = '1') then
NeedSD <= '0';
elsif (ShutDown = '1') and (SDDone = '0') then
NeedSD <= '1';
end if;
end process;
-- NeedSD <= ShutDown and not SDDone;
-- NeedSD <= '1' when ShutDown and not SDDone else
-- '0' when ;
FSMStepper : process(NextState, CLK, Reset) is begin
if reset = '1' then
FSMState <= stQuietCheck;
elsif falling_edge(CLK) then
FSMState <= NextState;
end if;
end process;
FSM : process(FSMState, CLK, QuietOk, isLastBit, ContinueStart
, ShutDown, SDEnough, Start, NeedSD, Reset, Enable)
is begin
case FSMState is
when stSerLoading =>
if (ShutDown = '1') and (SDEnough = '1') then
NextState <= stQuietCheck;
elsif (isLastBit = '1') then
if ContinueStart = '0' then
NextState <= stQuietCheck;
else
NextState <= stSerLoading;--stReady;
end if;
else
NextState <= stSerLoading;
end if;
when stQuietCheck =>
if (QuietOk = '1') then
if ((Enable = '1') or (NeedSD = '1')) then
NextState <= stSerLoading;
else
NextState <= stQuietCheck;--stReady;
end if;
else
NextState <= stQuietCheck;
end if;
when others =>
NextState <= stQuietCheck;
end case;
end process;
Transfer <= '1' when (FSMState = stSerLoading) else '0';
-- SS must contain gap with '1' about 1/2cycle on SCK at start and end of frames
SS <= Transfer or Enable;
iSCK <= CLK or not Enable; --when (FSMState = stSerLoading) else '1';
nSS <= not SS;
SCK <= iSCK;
DataCell : process (Data, CLK, reset, ReceiveWindow, SS) is begin
if reset = '1' then
Data <= (others => '0');
elsif rising_edge(CLK) then
if (ReceiveWindow = '1') and (SS = '1') then
Data(Data'high downto 1) <= Data(Data'high-1 downto 0);
Data(0) <= SDI;
end if;
end if;
end process;
DQ <= Data;
Shift <= CLK and ReceiveWindow;
readyMoitor: process(CLK, FSMState, isFirstbit, isLastDataBit, Reset) is begin
if (reset = '1') or (FSMState = stQuietCheck) then
iready <= '1';
elsif (FSMState = stSerLoading) and (isFirstbit = '1') and (CLK = '1') then
iready <= '0';
elsif falling_edge(CLK) then
if isLastDataBit = '1' then
iready <= '1';
end if;
end if;
end process;
Ready <= iReady;
end architecture BEH;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
entity testbench_passage_a_niveau is
end entity;
architecture behaviorial of testbench_passage_a_niveau is
component passage_a_niveau is
port(
clock: in std_logic;
reset: in std_logic;
capteur_droite: in std_logic;
capteur_gauche: in std_logic;
ampoule: out std_logic;
alert: out std_logic
);
end component;
signal clock, reset, capteur_droite, capteur_gauche, ampoule, alert: std_logic;
begin
-- Instantiate the Unit Under Test (UUT)
uut: passage_a_niveau port map(
clock => clock,
reset => reset,
capteur_droite => capteur_droite,
capteur_gauche => capteur_gauche,
ampoule => ampoule,
alert => alert
);
-- a clock process
clock_process: process
begin
clock <= '1';
wait for 0.5 ns;
clock <= '0';
wait for 0.5 ns;
end process;
-- A test process
test_process: process
begin
reset <= '1';
wait for 2.3 ns;
reset <= '0';
capteur_gauche <= '0';
capteur_droite <= '0';
wait for 12.3 ns;
-- un train court vient de droite
capteur_droite <= '1';
wait for 10 ns;
capteur_droite <= '0';
wait for 5 ns;
capteur_gauche <= '1';
wait for 10 ns;
capteur_gauche <= '0';
wait for 20 ns;
-- un train long vient de droite
capteur_droite <= '1';
wait for 20 ns;
capteur_gauche <= '1';
wait for 10 ns;
capteur_droite <= '0';
wait for 20 ns;
capteur_gauche <= '0';
wait for 20 ns;
-- deux trains rentrent en collision
capteur_droite <= '1';
capteur_gauche <= '1';
wait for 10 ns;
capteur_droite <= '0';
capteur_gauche <= '0';
wait for 20 ns;
end process;
end behaviorial;
|
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- VGA Video sync and timing generator
--
-- -----------------------------------------------------------------------
--
-- clk - video clock
-- clkDiv - Clock divider. 0=clk, 1=clk/2, 2=clk/3 ... 15=clk/16
-- hSync - Horizontal sync (sync polarity is set with hSyncPol)
-- vSync - Vertical sync (sync polarity is set with vSyncPol)
-- genlock_hold - Delay start of vertical sync while genlock hold is one.
-- This is used to sync the vga timing to another video source.
-- endOfPixel - Pixel clock is high each (clkDiv+1) clocks.
-- When clkDiv=0 is stays high continuously
-- endOfLine - High when the last pixel on the current line is displayed.
-- endOfFrame - High when the last pixel on the last line is displayed.
-- currentX - X coordinate of current pixel.
-- currentY - Y coordinate of current pixel.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity video_vga_master is
generic (
clkDivBits : integer := 4
);
port (
-- System
clk : in std_logic;
clkDiv : in unsigned((clkDivBits-1) downto 0);
-- Sync outputs
hSync : out std_logic;
vSync : out std_logic;
-- Sync inputs
genlock_hold : in std_logic := '0';
-- Control outputs
endOfPixel : out std_logic;
endOfLine : out std_logic;
endOfFrame : out std_logic;
currentX : out unsigned(11 downto 0);
currentY : out unsigned(11 downto 0);
-- Configuration
hSyncPol : in std_logic := '1';
vSyncPol : in std_logic := '1';
xSize : in unsigned(11 downto 0);
ySize : in unsigned(11 downto 0);
xSyncFr : in unsigned(11 downto 0);
xSyncTo : in unsigned(11 downto 0);
ySyncFr : in unsigned(11 downto 0);
ySyncTo : in unsigned(11 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of video_vga_master is
signal clkDivCnt : unsigned(clkDiv'high downto 0) := (others => '0');
signal xCounter : unsigned(11 downto 0) := (others => '0');
signal yCounter : unsigned(11 downto 0) := (others => '0');
signal xCounterInc : unsigned(11 downto 0) := (others => '0');
signal yCounterInc : unsigned(11 downto 0) := (others => '0');
signal newPixel : std_logic := '0';
signal hSync_reg : std_logic;
signal vSync_reg : std_logic;
signal pixel_reg : std_logic := '0';
signal line_reg : std_logic := '0';
signal frame_reg : std_logic := '0';
begin
-- -----------------------------------------------------------------------
-- Copy of local signals as outputs (for vga-slaves)
hSync <= hSync_reg;
vSync <= vSync_reg;
currentX <= xCounter;
currentY <= yCounter;
endOfPixel <= pixel_reg;
endOfLine <= line_reg;
endOfFrame <= frame_reg;
-- -----------------------------------------------------------------------
-- X & Y counters
process(clk)
begin
if rising_edge(clk) then
yCounterInc <= yCounter + 1;
pixel_reg <= '0';
line_reg <= '0';
frame_reg <= '0';
if newPixel = '1' then
pixel_reg <= '1';
xCounter <= xCounterInc;
if xCounterInc = xSize then
line_reg <= '1';
xCounter <= (others => '0');
if (genlock_hold = '0') or (yCounterInc < ySyncFr) then
yCounter <= yCounterInc;
end if;
if yCounterInc = ySize then
frame_reg <= '1';
yCounter <= (others => '0');
end if;
end if;
end if;
end if;
end process;
xCounterInc <= xCounter + 1;
-- -----------------------------------------------------------------------
-- Clock divider
process(clk)
begin
if rising_edge(clk) then
newPixel <= '0';
clkDivCnt <= clkDivCnt + 1;
if clkDivCnt = clkDiv then
clkDivCnt <= (others => '0');
newPixel <= '1';
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- hSync
process(clk)
begin
if rising_edge(clk) then
hSync_reg <= not hSyncPol;
if xCounter >= xSyncFr
and xCounter < xSyncTo then
hSync_reg <= hSyncPol;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- vSync
process(clk)
begin
if rising_edge(clk) then
if xCounter = xSyncFr then
vSync_reg <= not vSyncPol;
if yCounter >= ySyncFr
and yCounter < ySyncTo then
vSync_reg <= vSyncPol;
end if;
end if;
end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:25:10 01/18/2015
-- Design Name:
-- Module Name: C:/Users/Angel LM/Desktop/Frecuencimetroo 6.0/Frecuencimentro/PreEscala_TB.vhd
-- Project Name: Frecuencimentro
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: EscaladoPrePresentacion
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY PreEscala_TB IS
END PreEscala_TB;
ARCHITECTURE behavior OF PreEscala_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT EscaladoPrePresentacion
PORT(
entrada_frec : IN std_logic_vector(0 to 31);
salida_frec : OUT std_logic_vector(15 downto 0);
salida_uds : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_frec : std_logic_vector(0 to 31) := (others => '0');
--Outputs
signal salida_frec : std_logic_vector(15 downto 0);
signal salida_uds : std_logic_vector(1 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: EscaladoPrePresentacion PORT MAP (
entrada_frec => entrada_frec,
salida_frec => salida_frec,
salida_uds => salida_uds
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
entrada_frec<="00000000000000000000000000000010"; -- 2
wait for 100 ns;
entrada_frec<="00000000000000000100110110111100"; -- 19900
wait for 100 ns;
entrada_frec<="00101101110101000101000000111000"; -- 768888888
wait for 100 ns;
entrada_frec<="00000000111101000010010000000000"; -- 16000000
-- wait for <clock>_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:25:10 01/18/2015
-- Design Name:
-- Module Name: C:/Users/Angel LM/Desktop/Frecuencimetroo 6.0/Frecuencimentro/PreEscala_TB.vhd
-- Project Name: Frecuencimentro
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: EscaladoPrePresentacion
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY PreEscala_TB IS
END PreEscala_TB;
ARCHITECTURE behavior OF PreEscala_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT EscaladoPrePresentacion
PORT(
entrada_frec : IN std_logic_vector(0 to 31);
salida_frec : OUT std_logic_vector(15 downto 0);
salida_uds : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_frec : std_logic_vector(0 to 31) := (others => '0');
--Outputs
signal salida_frec : std_logic_vector(15 downto 0);
signal salida_uds : std_logic_vector(1 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: EscaladoPrePresentacion PORT MAP (
entrada_frec => entrada_frec,
salida_frec => salida_frec,
salida_uds => salida_uds
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
entrada_frec<="00000000000000000000000000000010"; -- 2
wait for 100 ns;
entrada_frec<="00000000000000000100110110111100"; -- 19900
wait for 100 ns;
entrada_frec<="00101101110101000101000000111000"; -- 768888888
wait for 100 ns;
entrada_frec<="00000000111101000010010000000000"; -- 16000000
-- wait for <clock>_period*10;
-- insert stimulus here
wait;
end process;
END;
|
architecture RTL of FIFO is
type state_machine is (idle, write, read, done);
-- Violations below
type state_machine is (idle, write, read, done);
type state_machine is (idle, write, read, done);
begin
end architecture RTL;
|
-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.10.0.111.2
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
use IEEE.numeric_std.all;
entity tb is
end entity tb;
architecture test of tb is
component fmexg_fifo_w_flags
port (Data : in std_logic_vector(11 downto 0);
WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
Q : out std_logic_vector(11 downto 0); Empty: out std_logic;
Full: out std_logic; AlmostEmpty: out std_logic;
AlmostFull: out std_logic
);
end component;
signal Data : std_logic_vector(11 downto 0) := (others => '0');
signal WrClock: std_logic := '0';
signal RdClock: std_logic := '0';
signal WrEn: std_logic := '0';
signal RdEn: std_logic := '0';
signal Reset: std_logic := '0';
signal RPReset: std_logic := '0';
signal Q : std_logic_vector(11 downto 0);
signal Empty: std_logic;
signal Full: std_logic;
signal AlmostEmpty: std_logic;
signal AlmostFull: std_logic;
begin
u1 : fmexg_fifo_w_flags
port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
Q => Q, Empty => Empty, Full => Full, AlmostEmpty => AlmostEmpty,
AlmostFull => AlmostFull
);
process
begin
Data <= (others => '0') ;
wait for 100 ns;
wait until Reset = '0';
for i in 0 to 8195 loop
wait until WrClock'event and WrClock = '1';
Data <= Data + '1' after 1 ns;
end loop;
wait;
end process;
WrClock <= not WrClock after 5.00 ns;
RdClock <= not RdClock after 5.00 ns;
process
begin
WrEn <= '0' ;
wait for 100 ns;
wait until Reset = '0';
for i in 0 to 8195 loop
wait until WrClock'event and WrClock = '1';
WrEn <= '1' after 1 ns;
end loop;
WrEn <= '0' ;
wait;
end process;
process
begin
RdEn <= '0' ;
wait until Reset = '0';
wait until WrEn = '1';
wait until WrEn = '0';
for i in 0 to 8195 loop
wait until RdClock'event and RdClock = '1';
RdEn <= '1' after 1 ns;
end loop;
RdEn <= '0' ;
wait;
end process;
process
begin
Reset <= '1' ;
wait for 100 ns;
Reset <= '0' ;
wait;
end process;
process
begin
RPReset <= '1' ;
wait for 100 ns;
RPReset <= '0' ;
wait;
end process;
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dff04 is
port (r : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic);
end dff04;
architecture behav of dff04 is
signal q : std_logic_vector(7 downto 0);
begin
process (clk, q) is
begin
if rising_edge (clk) then
q <= d;
end if;
r <= std_logic_vector(unsigned(q) + 1);
end process;
end behav;
|
--------------------------------------------------------------------------------
--! @file pulse2pulse_tb.vhd
--! @brief Testbench for pulse clock-domain crossing module pulse2pulse
--! @author Yuan Mei
--!
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY pulse2pulse_tb IS
END pulse2pulse_tb;
ARCHITECTURE Behavioral OF pulse2pulse_tb IS
COMPONENT pulse2pulse IS
PORT (
IN_CLK : IN std_logic;
OUT_CLK : IN std_logic;
RST : IN std_logic;
PULSEIN : IN std_logic;
INBUSY : OUT std_logic;
PULSEOUT : OUT std_logic
);
END COMPONENT;
SIGNAL CLK : std_logic := '0';
SIGNAL RESET : std_logic := '0';
--
SIGNAL OUT_CLK : std_logic;
SIGNAL PULSEIN : std_logic;
SIGNAL INBUSY : std_logic;
SIGNAL PULSEOUT : std_logic;
-- Clock period definitions
CONSTANT CLK_period : time := 10 ns;
CONSTANT CLKOUT_period : time := 5 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : pulse2pulse
PORT MAP (
IN_CLK => CLK,
OUT_CLK => OUT_CLK,
RST => RESET,
PULSEIN => PULSEIN,
INBUSY => INBUSY,
PULSEOUT => PULSEOUT
);
-- Clock process definitions
CLK_process : PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_period/2;
CLK <= '1';
WAIT FOR CLK_period/2;
END PROCESS;
CLKOUT_process : PROCESS
BEGIN
OUT_CLK <= '0';
WAIT FOR CLKOUT_period/2;
OUT_CLK <= '1';
WAIT FOR CLKOUT_period/2;
END PROCESS;
-- Stimulus process
stim_proc : PROCESS
BEGIN
PULSEIN <= '0';
-- hold reset state
RESET <= '0';
WAIT FOR 15 ns;
RESET <= '1';
WAIT FOR CLK_period*3;
RESET <= '0';
WAIT FOR CLK_period*5.3;
--
PULSEIN <= '1';
WAIT FOR CLK_period*3;
PULSEIN <= '0';
--
WAIT;
END PROCESS;
END Behavioral;
|
--------------------------------------------------------------------------------
--! @file pulse2pulse_tb.vhd
--! @brief Testbench for pulse clock-domain crossing module pulse2pulse
--! @author Yuan Mei
--!
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY pulse2pulse_tb IS
END pulse2pulse_tb;
ARCHITECTURE Behavioral OF pulse2pulse_tb IS
COMPONENT pulse2pulse IS
PORT (
IN_CLK : IN std_logic;
OUT_CLK : IN std_logic;
RST : IN std_logic;
PULSEIN : IN std_logic;
INBUSY : OUT std_logic;
PULSEOUT : OUT std_logic
);
END COMPONENT;
SIGNAL CLK : std_logic := '0';
SIGNAL RESET : std_logic := '0';
--
SIGNAL OUT_CLK : std_logic;
SIGNAL PULSEIN : std_logic;
SIGNAL INBUSY : std_logic;
SIGNAL PULSEOUT : std_logic;
-- Clock period definitions
CONSTANT CLK_period : time := 10 ns;
CONSTANT CLKOUT_period : time := 5 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : pulse2pulse
PORT MAP (
IN_CLK => CLK,
OUT_CLK => OUT_CLK,
RST => RESET,
PULSEIN => PULSEIN,
INBUSY => INBUSY,
PULSEOUT => PULSEOUT
);
-- Clock process definitions
CLK_process : PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_period/2;
CLK <= '1';
WAIT FOR CLK_period/2;
END PROCESS;
CLKOUT_process : PROCESS
BEGIN
OUT_CLK <= '0';
WAIT FOR CLKOUT_period/2;
OUT_CLK <= '1';
WAIT FOR CLKOUT_period/2;
END PROCESS;
-- Stimulus process
stim_proc : PROCESS
BEGIN
PULSEIN <= '0';
-- hold reset state
RESET <= '0';
WAIT FOR 15 ns;
RESET <= '1';
WAIT FOR CLK_period*3;
RESET <= '0';
WAIT FOR CLK_period*5.3;
--
PULSEIN <= '1';
WAIT FOR CLK_period*3;
PULSEIN <= '0';
--
WAIT;
END PROCESS;
END Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DataMemoryMulticycle is
port(
WriteData: in std_logic_vector(31 downto 0);
Address: in std_logic_vector(31 downto 0);
MemRead, MemWrite: in std_logic;
ReadData: out std_logic_vector(31 downto 0)
);
end DataMemoryMulticycle;
Architecture Structural of DataMemoryMulticycle is
type mem_array is array(0 to 55) of std_logic_vector(31 downto 0);
signal data_mem: mem_array := (
-- Instruction Memory
0 => X"8d100028", -- lw $s0, 40($t0)
1 => X"8d11002c", -- lw $s1, 44($t0)
2 => X"12110002", -- beq $s0, $s1, L
3 => X"02959820", -- add $s3, $s4, $s5
4 => X"08000006", -- j exit
5 => X"02959822", -- L: sub $s3, $s4, $s5
6 => X"ad130030", -- exit: sw $s3, 48($t0)
-- Data Memory
10 => X"00000004",
11 => X"00000004", -- Branch Taken
-- 11 => X"FFFFFFFB", -- Branch Untaken
others => x"00000000"
);
signal temp_data: std_logic_vector(31 downto 0) := X"00000000";
begin
ReadData <= temp_data;
process(WriteData, Address, MemRead, MemWrite)
begin
if MemWrite = '1' then
data_mem(to_integer(unsigned(Address)) / 4) <= WriteData;
end if;
if MemRead = '1' then
temp_data <= data_mem(to_integer(unsigned(Address)) / 4);
end if;
end process;
end Structural;
|
library verilog;
use verilog.vl_types.all;
entity memory is
port(
addr_a : in vl_logic_vector(10 downto 0);
addr_b : in vl_logic_vector(10 downto 0);
clk : in vl_logic;
q_a : out vl_logic_vector(7 downto 0);
q_b : out vl_logic_vector(7 downto 0)
);
end memory;
|
library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
-- Entidad
entity eXnor is
port(
entrada1_xnor: in std_logic;
entrada2_xnor: in std_logic;
salida_xnor: out std_logic);
end;
-- Arquitectura
architecture aXnor of eXnor is
begin
salida_xnor <= entrada1_xnor XNOR entrada2_xnor;
end aXnor;
|
------------------------------------------------------------------------------
-- This file is part of a signal tracing utility for the LEON3 processor
-- Copyright (C) 2017, ARCADE Lab @ Columbia University
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-----------------------------------------------------------------------------
-- Entity: detect_mem_access
-- File: detect_mem_access.vhd
-- Author: Van Bui - ARCADE @ Columbia University
-- Description: Detects a memory access over the bus
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library sld;
use sld.tracing.all;
entity detect_mem_access is
port (
ahbsi : in ahb_slv_in_type;
mem_selected : out std_logic_vector(AHB_BITS-1 downto 0));
end detect_mem_access;
architecture beh of detect_mem_access is
begin --beh
check_mem_access: process (ahbsi)
variable haddr : std_logic_vector(1 downto 0);
begin -- process detect_mem_access
haddr := ahbsi.haddr(31 downto 30);
if (haddr = "01" and (ahbsi.htrans = HTRANS_NONSEQ)) then
mem_selected <= "01";
elsif (haddr = "01" and (ahbsi.htrans = HTRANS_SEQ)) then
mem_selected <= "10";
elsif (haddr = "01" and (ahbsi.htrans = HTRANS_BUSY)) then
mem_selected <= "11";
else
mem_selected <= "00";
end if;
end process check_mem_access;
end beh;
|
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5728)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
library ieee;
use ieee.std_logic_1164.all;
entity imp_{{ current_var.name }} is
port (
clk: in std_logic;
reset: in std_logic;
clear: in std_logic;
change: out std_logic;
contra: out std_logic;
{% for var in variables %}
{{ var.name }}: inout std_logic_vector(0 to 1);
{% endfor %}
value: in std_logic_vector(0 to 1)
);
end imp_{{ current_var.name }};
architecture behavioral of imp_{{ current_var.name }} is
signal imp: std_logic_vector(0 to 1);
signal nxt: std_logic_vector(0 to 1);
signal cur: std_logic_vector(0 to 1);
begin
process (clk, reset, clear)
begin
if (reset='1') then
cur <= "00";
elsif (clear='1') then
cur <= "00";
elsif (rising_edge(clk)) then
cur <= nxt;
end if;
end process;
{{ current_var.name }} <= cur;
imp(0) <= {{ current_var.pos_implications }};
imp(1) <= {{ current_var.neg_implications }};
nxt(0) <= value(0) or imp(0);
nxt(1) <= value(1) or imp(1);
change <= (nxt(0) xor cur(0)) or (nxt(1) xor cur(1));
contra <= cur(0) and cur(1);
end behavioral; |
-- revision history:
-- 06.07.2015 Alex Schoenberger created
-- 04.08.2015 Patrick Appenheimer added entity and architecture behave
-- 05.08.2015 Patrick Appenheimer bugfixes
-- 05.08.2015 Patrick Appenheimer subu, and, or added
-- 10.08.2015 Patrick Appenheimer shift, slt added
library IEEE;
use IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
library WORK;
use WORK.all;
-- -- ALU FUNCTION CODES: -- --
-- ADD ==> 10_0000
-- SUB ==> 10_0010
-- AND ==> 10_0100
-- OR ==> 10_0101
-- result <= reg_a ==> 00_0001
-- result <= reg_b ==> 00_0010
-- shift ==> 00_0100
-- slt ==> 00_1000
entity alu is
port(
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
function_code : in std_logic_vector(5 downto 0);
result : out std_logic_vector(31 downto 0);
zero : out std_logic_vector(0 downto 0)
);
end entity alu;
architecture behave of alu is
begin
process(in_a, in_b, function_code)
-- declaration of variables
variable a_uns : std_logic_vector(31 downto 0);
variable b_uns : std_logic_vector(31 downto 0);
variable r_uns : std_logic_vector(31 downto 0);
variable z_uns : std_logic_vector(0 downto 0);
begin
-- initialize values
a_uns := in_a;
b_uns := in_b;
r_uns := (others => '0');
z_uns := b"0";
-- select operation
case function_code is
-- add
when b"10_0000" =>
r_uns := std_logic_vector(unsigned(a_uns) + unsigned(b_uns));
-- sub
when b"10_0010" =>
r_uns := std_logic_vector(unsigned(a_uns) - unsigned(b_uns));
-- and
when b"10_0100" =>
r_uns := in_a and in_b;--std_logic_vector(unsigned(a_uns) AND unsigned(b_uns));
-- or
when b"10_0101" =>
r_uns := std_logic_vector(unsigned(a_uns) OR unsigned(b_uns));
-- out <= a
when b"00_0001" =>
r_uns := a_uns;
-- out <= b
when b"00_0010" =>
r_uns := b_uns;
-- shift
when b"00_0100" =>
r_uns := std_logic_vector(SHIFT_LEFT(unsigned(b_uns),to_integer(unsigned(a_uns))));
-- slt
when b"00_1000" =>
if (to_integer(signed(a_uns)) < to_integer(signed(b_uns))) then
r_uns := x"0000_0001";
end if;
-- others
when others => r_uns := (others => 'X');
end case;
if r_uns = x"0000_0000" then
z_uns := b"1";
else
z_uns := b"0";
end if;
-- assign variables to output signals
result <= r_uns;
zero <= std_logic_vector(unsigned(z_uns));
end process;
end architecture behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memif is
Port (
CLK : in STD_LOGIC;
-- Interface
RAM_CS : in STD_LOGIC; -- RAM chip enable
ROM_CS : in STD_LOGIC; -- ROM chip enable
RW : in STD_LOGIC; -- 0: read, 1: write
A : in STD_LOGIC_VECTOR (23 downto 0);
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC := '1';
-- External Memory Bus:
ADDR : out STD_LOGIC_VECTOR (23 downto 0);
DATA : inout STD_LOGIC_VECTOR (15 downto 0);
OE : out STD_LOGIC := '1'; -- active low
WE : out STD_LOGIC := '1'; -- active low
MT_ADV : out STD_LOGIC := '0'; -- active low
MT_CLK : out STD_LOGIC := '0';
MT_UB : out STD_LOGIC := '1'; -- active low
MT_LB : out STD_LOGIC := '1'; -- active low
MT_CE : out STD_LOGIC := '1'; -- active low
MT_CRE : out STD_LOGIC := '0'; -- active high
MT_WAIT : in STD_LOGIC;
ST_STS : in STD_LOGIC;
RP : out STD_LOGIC := '1'; -- active low
ST_CE : out STD_LOGIC := '1' -- active low
);
end memif;
architecture Dataflow of memif is
signal LAST_CS : BOOLEAN;
signal READ : STD_LOGIC;
signal WRITE : STD_LOGIC;
signal A16a : STD_LOGIC_VECTOR (23 downto 0);
signal Din16a : STD_LOGIC_VECTOR (15 downto 0);
signal Dout16a : STD_LOGIC_VECTOR (15 downto 0);
signal LB16a : STD_LOGIC;
signal UB16a : STD_LOGIC;
signal EN16a : STD_LOGIC;
signal A16b : STD_LOGIC_VECTOR (23 downto 0);
signal Din16b : STD_LOGIC_VECTOR (15 downto 0);
signal Dout16b : STD_LOGIC_VECTOR (15 downto 0);
signal LB16b : STD_LOGIC;
signal UB16b : STD_LOGIC;
signal EN16b : STD_LOGIC;
signal A16 : STD_LOGIC_VECTOR (23 downto 0) := x"000000";
signal Din16 : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
signal Dout16 : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
signal LB16 : STD_LOGIC := '0';
signal UB16 : STD_LOGIC := '0';
signal EN16 : STD_LOGIC := '0';
signal counter : integer range 0 to 100 := 0;
begin
-- Read and Write signals:
READ <= (RAM_CS OR ROM_CS) AND EN16 AND (NOT RW);
WRITE <= (RAM_CS ) AND EN16 AND RW;
-- Address bus:
ADDR <= A16; -- NOTE: ADDRESS(0) is unconnected.
-- Data bus:
Dout16 <= DATA (15 downto 0) when READ='1' else "0000000000000000";
DATA <= Din16(15 downto 0) when WRITE='1' else "ZZZZZZZZZZZZZZZZ";
-- Bus direction:
OE <= NOT READ;
WE <= NOT WRITE;
-- Chip Enable:
MT_CE <= NOT (EN16 AND RAM_CS);
ST_CE <= NOT (EN16 AND ROM_CS);
-- Which byte
MT_LB <= NOT LB16;
MT_UB <= NOT Ub16;
-- Dout signal
Dout <= Dout16b & Dout16a when ((RAM_CS OR ROM_CS) AND (NOT RW))='1'
else x"00000000";
-- 32-BIT bus interfacing
process (CLK)
begin
if ( CLK = '1' and CLK'event ) then
if ((NOT LAST_CS) and (RAM_CS = '1' OR ROM_CS = '1')) then
-- startup of a new memory cycle
counter <= 0;
RDY <= '0';
if (DTYPE(0) = '1') then
-- BYTE
A16a <= A(23 downto 1) & "0";
Din16a <= Din(7 downto 0) & Din(7 downto 0);
LB16a <= NOT A(0);
UB16a <= A(0);
EN16a <= '1';
A16b <= x"000000";
Din16b <= x"0000";
LB16b <= '0';
UB16b <= '0';
EN16b <= '0';
elsif (DTYPE(1) = '1') then
-- HALF
A16a <= A(23 downto 1) & "0";
Din16a <= Din(15 downto 0);
LB16a <= '1';
UB16a <= '1';
EN16a <= '1';
A16b <= x"000000";
Din16b <= x"0000";
LB16b <= '0';
UB16b <= '0';
EN16b <= '0';
elsif (DTYPE(2) = '1') then
-- WORD
A16a <= A(23 downto 2) & "00";
Din16a <= Din(15 downto 0);
LB16a <= '1';
UB16a <= '1';
EN16a <= '1';
A16b <= A(23 downto 2) & "10";
Din16b <= Din(31 downto 16);
LB16b <= '1';
UB16b <= '1';
EN16b <= '1';
end if;
else
-- increase counter
if (counter < 7) then
-- in phase 1
A16 <= A16a;
Din16 <= Din16a;
LB16 <= LB16a;
UB16 <= UB16a;
EN16 <= EN16a;
if (DTYPE(0) = '1') then
if (LB16a = '1') then
Dout16a <= x"00" & Dout16(7 downto 0);
else
Dout16a <= x"00" & Dout16(15 downto 8);
end if;
else
Dout16a <= Dout16;
end if;
counter <= counter + 1;
elsif (counter = 7) then
-- before phase 2
A16 <= x"000000";
Din16 <= x"0000";
LB16 <= '0';
UB16 <= '0';
EN16 <= '0';
if (EN16b = '0') then
counter <= 14;
else
counter <= counter + 1;
end if;
elsif (counter < 14) then
-- in phase 2
A16 <= A16b;
Din16 <= Din16b;
LB16 <= LB16b;
UB16 <= UB16b;
EN16 <= EN16b;
Dout16b <= Dout16;
counter <= counter + 1;
else
-- done
A16 <= x"000000";
Din16 <= x"0000";
LB16 <= '0';
UB16 <= '0';
EN16 <= '0';
RDY <= '1';
end if;
end if;
LAST_CS <= (RAM_CS = '1' OR ROM_CS = '1');
end if;
end process;
end Dataflow;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM_TB is
end entity;
architecture RTL of PWM_TB is
component PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end component PWM;
signal CLK : std_logic;
signal DATA : std_logic_vector(31 downto 0);
signal DATA_STB : std_logic;
signal DATA_ACK : std_logic;
signal OUT_BIT : std_logic;
begin
process
begin
while True loop
CLK <= '0';
wait for 10.0 ns;
CLK <= '1';
wait for 10.0 ns;
end loop;
wait;
end process;
PWM_INST_1 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 10
) port map(
CLK => CLK,
DATA => DATA,
DATA_STB => DATA_STB,
DATA_ACK => DATA_ACK,
OUT_BIT => OUT_BIT
);
process
begin
wait for 200 ns;
wait until rising_edge(CLK);
DATA <= X"000000FF";
DATA_STB <= '1';
wait until rising_edge(CLK);
DATA_STB <= '0';
wait for 200 us;
wait until rising_edge(CLK);
DATA <= X"0000007F";
DATA_STB <= '1';
wait until rising_edge(CLK);
DATA_STB <= '0';
wait for 200 us;
wait until rising_edge(CLK);
DATA <= X"0000003F";
DATA_STB <= '1';
wait until rising_edge(CLK);
DATA_STB <= '0';
wait for 200 us;
wait until rising_edge(CLK);
DATA <= X"00000000";
DATA_STB <= '1';
wait until rising_edge(CLK);
DATA_STB <= '0';
wait;
end process;
end architecture RTL;
|
-- PS/2 interface
constant CFG_PS2_ENABLE : integer := CONFIG_PS2_ENABLE;
|
-- PS/2 interface
constant CFG_PS2_ENABLE : integer := CONFIG_PS2_ENABLE;
|
-- PS/2 interface
constant CFG_PS2_ENABLE : integer := CONFIG_PS2_ENABLE;
|
-- PS/2 interface
constant CFG_PS2_ENABLE : integer := CONFIG_PS2_ENABLE;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 02.01.2014 13:22:29
-- Design Name:
-- Module Name: input_queue_overflow - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.4
--
-- Description:
-- combinatioral path to check for overflow of the iq_memory and iq_fifos
--
-- more detailed information can found in file switch_port_rxpath_input_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity input_queue_overflow is
Generic(
IQ_FIFO_DATA_WIDTH : integer;
IQ_MEM_ADDR_WIDTH : integer;
IQ_FIFO_MEM_PTR_START : integer;
NR_IQ_FIFOS : integer
);
Port (
fifo_full : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
fifo_empty : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
mem_wr_addr : in std_logic_vector(IQ_MEM_ADDR_WIDTH-1 downto 0);
mem_rd_addr : in std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
overflow : out std_logic_vector(NR_IQ_FIFOS-1 downto 0)
);
end input_queue_overflow;
architecture rtl of input_queue_overflow is
begin
-- overflow if the memory currently written to is one address below current fifo word
-- or if fifo is full
overflow_detection_p : process(mem_rd_addr, mem_wr_addr, fifo_empty, fifo_full)
begin
for i in 0 to NR_IQ_FIFOS-1 loop
if fifo_empty(i) = '0' and mem_rd_addr(i*IQ_FIFO_DATA_WIDTH+IQ_FIFO_MEM_PTR_START+IQ_MEM_ADDR_WIDTH-1
downto i*IQ_FIFO_DATA_WIDTH+IQ_FIFO_MEM_PTR_START) - mem_wr_addr = 1 then
overflow(i) <= '1';
elsif fifo_full(i) = '1' then
overflow(i) <= '1';
else
overflow(i) <= '0';
end if;
end loop;
end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 02.01.2014 13:22:29
-- Design Name:
-- Module Name: input_queue_overflow - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.4
--
-- Description:
-- combinatioral path to check for overflow of the iq_memory and iq_fifos
--
-- more detailed information can found in file switch_port_rxpath_input_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity input_queue_overflow is
Generic(
IQ_FIFO_DATA_WIDTH : integer;
IQ_MEM_ADDR_WIDTH : integer;
IQ_FIFO_MEM_PTR_START : integer;
NR_IQ_FIFOS : integer
);
Port (
fifo_full : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
fifo_empty : in std_logic_vector(NR_IQ_FIFOS-1 downto 0);
mem_wr_addr : in std_logic_vector(IQ_MEM_ADDR_WIDTH-1 downto 0);
mem_rd_addr : in std_logic_vector(NR_IQ_FIFOS*IQ_FIFO_DATA_WIDTH-1 downto 0);
overflow : out std_logic_vector(NR_IQ_FIFOS-1 downto 0)
);
end input_queue_overflow;
architecture rtl of input_queue_overflow is
begin
-- overflow if the memory currently written to is one address below current fifo word
-- or if fifo is full
overflow_detection_p : process(mem_rd_addr, mem_wr_addr, fifo_empty, fifo_full)
begin
for i in 0 to NR_IQ_FIFOS-1 loop
if fifo_empty(i) = '0' and mem_rd_addr(i*IQ_FIFO_DATA_WIDTH+IQ_FIFO_MEM_PTR_START+IQ_MEM_ADDR_WIDTH-1
downto i*IQ_FIFO_DATA_WIDTH+IQ_FIFO_MEM_PTR_START) - mem_wr_addr = 1 then
overflow(i) <= '1';
elsif fifo_full(i) = '1' then
overflow(i) <= '1';
else
overflow(i) <= '0';
end if;
end loop;
end process;
end rtl;
|
-------------------------------------------------------------------------------
-- cpu_xadc_wiz_0_0_family.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cpu_xadc_wiz_0_0_family.vhd
--
-- Description:
-- This HDL file provides various functions for determining features (such
-- as BRAM types) in the various device families in Xilinx products.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- cpu_xadc_wiz_0_0_family.vhd
--
-------------------------------------------------------------------------------
-- Revision history
--
-- ??? ?????????? Initial version
-- jam 03/31/2003 added spartan3 to constants and derived function. Added
-- comments to try and explain how the function is used
-- jam 04/01/2003 removed VIRTEX from the derived list for BYZANTIUM,
-- VIRTEX2P, and SPARTAN3. This changes VIRTEX2 to be a
-- base family type, similar to X4K and VIRTEX
-- jam 04/02/2003 add VIRTEX back into the hierarchy of VIRTEX2P, BYZANTIUM
-- and SPARTAN3; add additional comments showing use in
-- VHDL
-- lss 03/24/2004 Added QVIRTEX2, QRVIRTEX2, VIRTEX4
-- flo 03/22/2005 Added SPARTAN3E
-- als 02/23/2006 Added VIRTEX5
-- flo 09/13/2006 Added SPARTAN3A and SPARTAN3A. This may allow
-- legacy designs to support spartan3a and spartan3an in
-- terms of BRAMs. For new work (and maintenence where
-- possible) this package, family, should be dropped in favor
-- of the package, family_support.
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_H_SP1
-- Added spartan3e
-- @END_CHANGELOG
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
package cpu_xadc_wiz_0_0_family is
-- constant declarations
constant ANY : string := "any";
constant X4K : string := "x4k";
constant X4KE : string := "x4ke";
constant X4KL : string := "x4kl";
constant X4KEX : string := "x4kex";
constant X4KXL : string := "x4kxl";
constant X4KXV : string := "x4kxv";
constant X4KXLA : string := "x4kxla";
constant SPARTAN : string := "spartan";
constant SPARTANXL : string := "spartanxl";
constant SPARTAN2 : string := "spartan2";
constant SPARTAN2E : string := "spartan2e";
constant VIRTEX : string := "virtex";
constant VIRTEXE : string := "virtexe";
constant VIRTEX2 : string := "virtex2";
constant VIRTEX2P : string := "virtex2p";
constant BYZANTIUM : string := "byzantium";
constant SPARTAN3 : string := "spartan3";
constant QRVIRTEX2 : string := "qrvirtex2";
constant QVIRTEX2 : string := "qvirtex2";
constant VIRTEX4 : string := "virtex4";
constant VIRTEX5 : string := "virtex5";
constant SPARTAN3E : string := "spartan3e";
constant SPARTAN3A : string := "spartan3a";
constant SPARTAN3AN: string := "spartan3an";
-- function declarations
-- derived - provides a means to determine if a family specified in child is
-- the same as, or is a super set of, the family specified in
-- ancestor.
--
-- Typically, child is set to the generic specifying the family type
-- the user wishes to implement the design into (C_FAMILY), and the
-- designer hard codes ancestor to the family type supported by the
-- design. If the design supports multiple family types, then each
-- of those family types would need to be tested against C_FAMILY
-- using this function. An example for the VIRTEX2P hierarchy
-- is shown below:
--
-- VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2P)
-- generate
-- -- logic specific to Virtex2P family
-- end generate VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if not derived(C_FAMILY,VIRTEX2P)
-- generate
--
-- VIRTEX2_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2)
-- generate
-- -- logic specific to Virtex2 family
-- end generate VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2_SPECIFIC_LOGIC_GEN
-- if not derived(C_FAMILY,VIRTEX2)
-- generate
--
-- VIRTEX_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX)
-- generate
-- -- logic specific to Virtex family
-- end generate VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX_SPECIFIC_LOGIC_GEN;
-- if not derived(C_FAMILY,VIRTEX)
-- generate
--
-- ANY_FAMILY_TYPE_LOGIC_GEN:
-- if derived(C_FAMILY,ANY)
-- generate
-- -- logic not specific to any family
-- end generate ANY_FAMILY_TYPE_LOGIC_GEN;
--
-- end generate NON_VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- This function will return TRUE if the family type specified in
-- child is equal to, or a super set of, the family type specified in
-- ancestor, otherwise it returns FALSE.
--
-- The current super sets are defined by the following list, where
-- all family types listed to the right of an item are contained in
-- the super set of that item, for all lines containing that item.
--
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
--
-- For exampel, all other family types are contained in the super set
-- for ANY. Stated another way, if the designer specifies ANY
-- for the family type the design supports, then the function will
-- return TRUE for any family type the user wishes to implement the
-- design into.
--
-- if derived(C_FAMILY,ANY) generate ... end generate;
--
-- If the designer specifies VIRTEX2 as the family type supported by
-- the design, then the function will only return TRUE if the user
-- intends to implement the design in VIRTEX2, VIRTEX2P, BYZANTIUM,
-- or SPARTAN3.
--
-- if derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses VIRTEX2 BRAMs
-- end generate;
--
-- if not derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses non VIRTEX2 BRAMs
-- end generate;
--
-- Note:
-- The last three lines of the list above were modified from the
-- original to remove VIRTEX from those lines because, from our point
-- of view, VIRTEX2 is different enough from VIRTEX to conclude that
-- it should be its own base family type.
--
-- **************************************************************************
-- WARNING
-- **************************************************************************
-- DO NOT RELY ON THE DERIVED FUNCTION TO PROVIDE DIFFERENTIATION BETWEEN
-- FAMILY TYPES FOR ANYTHING OTHER THAN BRAMS
--
-- Use of the derived function assumes that the designer is not using
-- RLOCs (RLOC'd FIFO's from Coregen, etc.) and that the BRAMs in the
-- derived families are similar. If the designer is using specific
-- elements of a family type, they are responsible for ensuring that
-- those same elements are available in all family types supported by
-- their design, and that the elements function exactly the same in all
-- "similar" families.
--
-- **************************************************************************
--
function derived ( child, ancestor : string ) return boolean;
-- equalIgnoreCase - Returns TRUE if case insensitive string comparison
-- determines that str1 and str2 are equal, otherwise FALSE
function equalIgnoreCase( str1, str2 : string ) return boolean;
-- toLowerCaseChar - Returns the lower case form of char if char is an upper
-- case letter. Otherwise char is returned.
function toLowerCaseChar( char : character ) return character;
end cpu_xadc_wiz_0_0_family;
package body cpu_xadc_wiz_0_0_family is
-- True if architecture "child" is derived from, or equal to,
-- the architecture "ancestor".
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
function derived ( child, ancestor : string ) return boolean is
variable is_derived : boolean := FALSE;
begin
if equalIgnoreCase( child, VIRTEX ) then -- base family type
if ( equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2 ) then
if ( equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QRVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QRVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX5 ) then
if ( equalIgnoreCase(ancestor,VIRTEX5) OR
equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX4 ) then
if ( equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2P ) then
if ( equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, BYZANTIUM ) then
if ( equalIgnoreCase(ancestor,BYZANTIUM) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEXE ) then
if ( equalIgnoreCase(ancestor,VIRTEXE) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2 ) then
if ( equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2E ) then
if ( equalIgnoreCase(ancestor,SPARTAN2E) OR
equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3 ) then
if ( equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3E ) then
if ( equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3A ) then
if ( equalIgnoreCase(ancestor,SPARTAN3A) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3AN ) then
if ( equalIgnoreCase(ancestor,SPARTAN3AN) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4K ) then -- base family type
if ( equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KEX ) then
if ( equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXL ) then
if ( equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXV ) then
if ( equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXLA ) then
if ( equalIgnoreCase(ancestor,X4KXLA) OR
equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KE ) then
if ( equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KL ) then
if ( equalIgnoreCase(ancestor,X4KL) OR
equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN ) then
if ( equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTANXL ) then
if ( equalIgnoreCase(ancestor,SPARTANXL) OR
equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, ANY ) then
if equalIgnoreCase( ancestor, any ) then is_derived := TRUE;
end if;
end if;
return is_derived;
end derived;
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalIgnoreCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoreCase;
end cpu_xadc_wiz_0_0_family;
|
-- USB Host Controller
constant CFG_USBHC : integer := CONFIG_GRUSBHC_ENABLE;
constant CFG_USBHC_NPORTS : integer := CONFIG_GRUSBHC_NPORTS;
constant CFG_USBHC_EHC : integer := CONFIG_GRUSBHC_EHC;
constant CFG_USBHC_UHC : integer := CONFIG_GRUSBHC_UHC;
constant CFG_USBHC_NCC : integer := CONFIG_GRUSBHC_NCC;
constant CFG_USBHC_NPCC : integer := CONFIG_GRUSBHC_NPCC;
constant CFG_USBHC_PRR : integer := CONFIG_GRUSBHC_PRR;
constant CFG_USBHC_PR1 : integer := CONFIG_GRUSBHC_PORTROUTE1;
constant CFG_USBHC_PR2 : integer := CONFIG_GRUSBHC_PORTROUTE2;
constant CFG_USBHC_ENDIAN : integer := CONFIG_GRUSBHC_ENDIAN;
constant CFG_USBHC_BEREGS : integer := CONFIG_GRUSBHC_BEREGS;
constant CFG_USBHC_BEDESC : integer := CONFIG_GRUSBHC_BEDESC;
constant CFG_USBHC_BLO : integer := CONFIG_GRUSBHC_BLO;
constant CFG_USBHC_BWRD : integer := CONFIG_GRUSBHC_BWRD;
constant CFG_USBHC_UTM : integer := CONFIG_GRUSBHC_UTMTYPE;
constant CFG_USBHC_VBUSCONF : integer := CONFIG_GRUSBHC_VBUSCONF;
|
-- USB Host Controller
constant CFG_USBHC : integer := CONFIG_GRUSBHC_ENABLE;
constant CFG_USBHC_NPORTS : integer := CONFIG_GRUSBHC_NPORTS;
constant CFG_USBHC_EHC : integer := CONFIG_GRUSBHC_EHC;
constant CFG_USBHC_UHC : integer := CONFIG_GRUSBHC_UHC;
constant CFG_USBHC_NCC : integer := CONFIG_GRUSBHC_NCC;
constant CFG_USBHC_NPCC : integer := CONFIG_GRUSBHC_NPCC;
constant CFG_USBHC_PRR : integer := CONFIG_GRUSBHC_PRR;
constant CFG_USBHC_PR1 : integer := CONFIG_GRUSBHC_PORTROUTE1;
constant CFG_USBHC_PR2 : integer := CONFIG_GRUSBHC_PORTROUTE2;
constant CFG_USBHC_ENDIAN : integer := CONFIG_GRUSBHC_ENDIAN;
constant CFG_USBHC_BEREGS : integer := CONFIG_GRUSBHC_BEREGS;
constant CFG_USBHC_BEDESC : integer := CONFIG_GRUSBHC_BEDESC;
constant CFG_USBHC_BLO : integer := CONFIG_GRUSBHC_BLO;
constant CFG_USBHC_BWRD : integer := CONFIG_GRUSBHC_BWRD;
constant CFG_USBHC_UTM : integer := CONFIG_GRUSBHC_UTMTYPE;
constant CFG_USBHC_VBUSCONF : integer := CONFIG_GRUSBHC_VBUSCONF;
|
-------------------------------------------------------------------------------
-- Title : VIA 6522
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the 6522 VIA chip.
-- A LOT OF REVERSE ENGINEERING has been done to make this module
-- as accurate as it is now. Thanks to gyurco for ironing out some
-- differences that were left unnoticed.
-------------------------------------------------------------------------------
-- License: GPL 3.0 - Free to use, distribute and change to your own needs.
-- Leaving a reference to the author will be highly appreciated.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity via6522 is
port (
clock : in std_logic;
rising : in std_logic;
falling : in std_logic;
reset : in std_logic;
addr : in std_logic_vector(3 downto 0);
wen : in std_logic;
ren : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
phi2_ref : out std_logic;
-- pio --
port_a_o : out std_logic_vector(7 downto 0);
port_a_t : out std_logic_vector(7 downto 0);
port_a_i : in std_logic_vector(7 downto 0);
port_b_o : out std_logic_vector(7 downto 0);
port_b_t : out std_logic_vector(7 downto 0);
port_b_i : in std_logic_vector(7 downto 0);
-- handshake pins
ca1_i : in std_logic;
ca2_o : out std_logic;
ca2_i : in std_logic;
ca2_t : out std_logic;
cb1_o : out std_logic;
cb1_i : in std_logic;
cb1_t : out std_logic;
cb2_o : out std_logic;
cb2_i : in std_logic;
cb2_t : out std_logic;
irq : out std_logic );
end via6522;
architecture Gideon of via6522 is
type pio_t is
record
pra : std_logic_vector(7 downto 0);
ddra : std_logic_vector(7 downto 0);
prb : std_logic_vector(7 downto 0);
ddrb : std_logic_vector(7 downto 0);
end record;
constant pio_default : pio_t := (others => (others => '0'));
constant latch_reset_pattern : std_logic_vector(15 downto 0) := X"5550";
signal last_data : std_logic_vector(7 downto 0) := X"55";
signal pio_i : pio_t;
signal port_a_c : std_logic_vector(7 downto 0) := (others => '0');
signal port_b_c : std_logic_vector(7 downto 0) := (others => '0');
signal irq_mask : std_logic_vector(6 downto 0) := (others => '0');
signal irq_flags : std_logic_vector(6 downto 0) := (others => '0');
signal irq_events : std_logic_vector(6 downto 0) := (others => '0');
signal irq_out : std_logic;
signal timer_a_latch : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_b_latch : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_a_count : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_b_count : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_a_out : std_logic;
signal timer_b_tick : std_logic;
signal acr, pcr : std_logic_vector(7 downto 0) := X"00";
signal shift_reg : std_logic_vector(7 downto 0) := X"00";
signal serport_en : std_logic;
signal ser_cb2_o : std_logic;
signal hs_cb2_o : std_logic;
signal cb1_t_int : std_logic;
signal cb1_o_int : std_logic;
signal cb2_t_int : std_logic;
signal cb2_o_int : std_logic;
alias ca2_event : std_logic is irq_events(0);
alias ca1_event : std_logic is irq_events(1);
alias serial_event : std_logic is irq_events(2);
alias cb2_event : std_logic is irq_events(3);
alias cb1_event : std_logic is irq_events(4);
alias timer_b_event : std_logic is irq_events(5);
alias timer_a_event : std_logic is irq_events(6);
alias ca2_flag : std_logic is irq_flags(0);
alias ca1_flag : std_logic is irq_flags(1);
alias serial_flag : std_logic is irq_flags(2);
alias cb2_flag : std_logic is irq_flags(3);
alias cb1_flag : std_logic is irq_flags(4);
alias timer_b_flag : std_logic is irq_flags(5);
alias timer_a_flag : std_logic is irq_flags(6);
alias tmr_a_output_en : std_logic is acr(7);
alias tmr_a_freerun : std_logic is acr(6);
alias tmr_b_count_mode : std_logic is acr(5);
alias shift_dir : std_logic is acr(4);
alias shift_clk_sel : std_logic_vector(1 downto 0) is acr(3 downto 2);
alias shift_mode_control : std_logic_vector(2 downto 0) is acr(4 downto 2);
alias pb_latch_en : std_logic is acr(1);
alias pa_latch_en : std_logic is acr(0);
alias cb2_is_output : std_logic is pcr(7);
alias cb2_edge_select : std_logic is pcr(6); -- for when CB2 is input
alias cb2_no_irq_clr : std_logic is pcr(5); -- for when CB2 is input
alias cb2_out_mode : std_logic_vector(1 downto 0) is pcr(6 downto 5);
alias cb1_edge_select : std_logic is pcr(4);
alias ca2_is_output : std_logic is pcr(3);
alias ca2_edge_select : std_logic is pcr(2); -- for when CA2 is input
alias ca2_no_irq_clr : std_logic is pcr(1); -- for when CA2 is input
alias ca2_out_mode : std_logic_vector(1 downto 0) is pcr(2 downto 1);
alias ca1_edge_select : std_logic is pcr(0);
signal ira, irb : std_logic_vector(7 downto 0) := (others => '0');
signal write_t1c_l : std_logic;
signal write_t1c_h : std_logic;
signal write_t2c_h : std_logic;
signal ca1_c, ca2_c : std_logic;
signal cb1_c, cb2_c : std_logic;
signal ca1_d1, ca2_d1 : std_logic;
signal cb1_d1, cb2_d1 : std_logic;
signal ca1_d2, ca2_d2 : std_logic;
signal cb1_d2, cb2_d2 : std_logic;
signal ca2_handshake_o : std_logic;
signal ca2_pulse_o : std_logic;
signal cb2_handshake_o : std_logic;
signal cb2_pulse_o : std_logic;
signal shift_active : std_logic;
begin
irq <= irq_out;
write_t1c_l <= '1' when (addr = X"4" or addr = x"6") and wen='1' and falling = '1' else '0';
write_t1c_h <= '1' when addr = X"5" and wen='1' and falling = '1' else '0';
write_t2c_h <= '1' when addr = X"9" and wen='1' and falling = '1' else '0';
ca1_event <= (ca1_d1 xor ca1_d2) and (ca1_d2 xor ca1_edge_select);
ca2_event <= (ca2_d1 xor ca2_d2) and (ca2_d2 xor ca2_edge_select);
cb1_event <= (cb1_d1 xor cb1_d2) and (cb1_d2 xor cb1_edge_select);
cb2_event <= (cb2_d1 xor cb2_d2) and (cb2_d2 xor cb2_edge_select);
ca2_t <= ca2_is_output;
cb2_t_int <= cb2_is_output when serport_en='0' else shift_dir;
cb2_o_int <= hs_cb2_o when serport_en='0' else ser_cb2_o;
cb1_t <= cb1_t_int;
cb1_o <= cb1_o_int;
cb2_t <= cb2_t_int;
cb2_o <= cb2_o_int;
with ca2_out_mode select ca2_o <=
ca2_handshake_o when "00",
ca2_pulse_o when "01",
'0' when "10",
'1' when others;
with cb2_out_mode select hs_cb2_o <=
cb2_handshake_o when "00",
cb2_pulse_o when "01",
'0' when "10",
'1' when others;
process(irq_flags, irq_mask)
begin
if (irq_flags and irq_mask) = "0000000" then
irq_out <= '0';
else
irq_out <= '1';
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if rising = '1' then
phi2_ref <= '1';
elsif falling = '1' then
phi2_ref <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
-- CA1/CA2/CB1/CB2 edge detect flipflops
ca1_c <= To_X01(ca1_i);
ca2_c <= To_X01(ca2_i);
cb1_c <= To_X01(cb1_i);
cb2_c <= To_X01(cb2_i);
ca1_d1 <= ca1_c;
ca2_d1 <= ca2_c;
cb1_d1 <= cb1_c;
cb2_d1 <= cb2_c;
ca1_d2 <= ca1_d1;
ca2_d2 <= ca2_d1;
cb1_d2 <= cb1_d1;
cb2_d2 <= cb2_d1;
-- input registers
port_a_c <= port_a_i;
port_b_c <= port_b_i;
-- input latch emulation
if pa_latch_en = '0' or (ca1_event = '1' and ca2_handshake_o = '1') then
ira <= port_a_c;
end if;
if pb_latch_en = '0' or (cb1_event = '1' and cb2_handshake_o = '1') then
irb <= port_b_c;
end if;
-- CA2 logic
if ca1_event = '1' then
ca2_handshake_o <= '0';
elsif (ren = '1' or wen = '1') and addr = X"1" and falling = '1' then
ca2_handshake_o <= '1';
end if;
if falling = '1' then
if (ren = '1' or wen = '1') and addr = X"1" then
ca2_pulse_o <= '0';
else
ca2_pulse_o <= '1';
end if;
end if;
-- CB2 logic
if cb1_event = '1' then
cb2_handshake_o <= '0';
elsif (ren = '1' or wen = '1') and addr = X"0" and falling = '1' then
cb2_handshake_o <= '1';
end if;
if falling = '1' then
if (ren = '1' or wen = '1') and addr = X"0" then
cb2_pulse_o <= '0';
else
cb2_pulse_o <= '1';
end if;
end if;
-- Interrupt logic
irq_flags <= irq_flags or irq_events;
-- Writes --
if wen='1' and falling = '1' then
last_data <= data_in;
case addr is
when X"0" => -- ORB
pio_i.prb <= data_in;
if cb2_no_irq_clr='0' then
cb2_flag <= '0';
end if;
cb1_flag <= '0';
when X"1" => -- ORA
pio_i.pra <= data_in;
if ca2_no_irq_clr='0' then
ca2_flag <= '0';
end if;
ca1_flag <= '0';
when X"2" => -- DDRB
pio_i.ddrb <= data_in;
when X"3" => -- DDRA
pio_i.ddra <= data_in;
when X"4" => -- TA LO counter (write=latch)
timer_a_latch(7 downto 0) <= data_in;
when X"5" => -- TA HI counter
timer_a_latch(15 downto 8) <= data_in;
timer_a_flag <= '0';
when X"6" => -- TA LO latch
timer_a_latch(7 downto 0) <= data_in;
when X"7" => -- TA HI latch
timer_a_latch(15 downto 8) <= data_in;
timer_a_flag <= '0';
when X"8" => -- TB LO latch
timer_b_latch(7 downto 0) <= data_in;
when X"9" => -- TB HI counter
timer_b_flag <= '0';
when X"A" => -- Serial port
serial_flag <= '0';
when X"B" => -- ACR (Auxiliary Control Register)
acr <= data_in;
when X"C" => -- PCR (Peripheral Control Register)
pcr <= data_in;
when X"D" => -- IFR
irq_flags <= irq_flags and not data_in(6 downto 0);
when X"E" => -- IER
if data_in(7)='1' then -- set
irq_mask <= irq_mask or data_in(6 downto 0);
else -- clear
irq_mask <= irq_mask and not data_in(6 downto 0);
end if;
when X"F" => -- ORA no handshake
pio_i.pra <= data_in;
when others =>
null;
end case;
end if;
-- Reads - Output only --
data_out <= X"00";
case addr is
when X"0" => -- ORB
--Port B reads its own output register for pins set to output.
data_out <= (pio_i.prb and pio_i.ddrb) or (irb and not pio_i.ddrb);
if tmr_a_output_en='1' then
data_out(7) <= timer_a_out;
end if;
when X"1" => -- ORA
data_out <= ira;
when X"2" => -- DDRB
data_out <= pio_i.ddrb;
when X"3" => -- DDRA
data_out <= pio_i.ddra;
when X"4" => -- TA LO counter
data_out <= timer_a_count(7 downto 0);
when X"5" => -- TA HI counter
data_out <= timer_a_count(15 downto 8);
when X"6" => -- TA LO latch
data_out <= timer_a_latch(7 downto 0);
when X"7" => -- TA HI latch
data_out <= timer_a_latch(15 downto 8);
when X"8" => -- TA LO counter
data_out <= timer_b_count(7 downto 0);
when X"9" => -- TA HI counter
data_out <= timer_b_count(15 downto 8);
when X"A" => -- SR
data_out <= shift_reg;
when X"B" => -- ACR
data_out <= acr;
when X"C" => -- PCR
data_out <= pcr;
when X"D" => -- IFR
data_out <= irq_out & irq_flags;
when X"E" => -- IER
data_out <= '0' & irq_mask;
when X"F" => -- ORA
data_out <= ira;
when others =>
null;
end case;
-- Read actions --
if ren = '1' and falling = '1' then
case addr is
when X"0" => -- ORB
if cb2_no_irq_clr='0' then
cb2_flag <= '0';
end if;
cb1_flag <= '0';
when X"1" => -- ORA
if ca2_no_irq_clr='0' then
ca2_flag <= '0';
end if;
ca1_flag <= '0';
when X"4" => -- TA LO counter
timer_a_flag <= '0';
when X"8" => -- TB LO counter
timer_b_flag <= '0';
when X"A" => -- SR
serial_flag <= '0';
when others =>
null;
end case;
end if;
if reset='1' then
-- Reset avoids packing into shift register
ca1_c <= '1';
ca2_c <= '1';
cb1_c <= '1';
cb2_c <= '1';
ca1_d1 <= '1';
ca2_d1 <= '1';
cb1_d1 <= '1';
cb2_d1 <= '1';
ca1_d2 <= '1';
ca2_d2 <= '1';
cb1_d2 <= '1';
cb2_d2 <= '1';
pio_i <= pio_default;
irq_mask <= (others => '0');
irq_flags <= (others => '0');
acr <= (others => '0');
pcr <= (others => '0');
ca2_handshake_o <= '1';
ca2_pulse_o <= '1';
cb2_handshake_o <= '1';
cb2_pulse_o <= '1';
timer_a_latch <= latch_reset_pattern;
timer_b_latch <= latch_reset_pattern;
end if;
end if;
end process;
-- PIO Out select --
port_a_o <= pio_i.pra;
port_b_o(6 downto 0) <= pio_i.prb(6 downto 0);
port_b_o(7) <= pio_i.prb(7) when tmr_a_output_en='0' else timer_a_out;
port_a_t <= pio_i.ddra;
port_b_t(6 downto 0) <= pio_i.ddrb(6 downto 0);
port_b_t(7) <= pio_i.ddrb(7) or tmr_a_output_en;
-- Timer A
tmr_a: block
signal timer_a_reload : std_logic;
signal timer_a_toggle : std_logic;
signal timer_a_may_interrupt : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if falling = '1' then
-- always count, or load
if timer_a_reload = '1' then
timer_a_count <= timer_a_latch;
if write_t1c_l = '1' then
timer_a_count(7 downto 0) <= data_in;
end if;
timer_a_reload <= '0';
timer_a_may_interrupt <= timer_a_may_interrupt and tmr_a_freerun;
else
if timer_a_count = X"0000" then
-- generate an event if we were triggered
timer_a_reload <= '1';
end if;
--Timer coutinues to count in both free run and one shot.
timer_a_count <= timer_a_count - X"0001";
end if;
end if;
if rising = '1' then
if timer_a_event = '1' and tmr_a_output_en = '1' then
timer_a_toggle <= not timer_a_toggle;
end if;
end if;
if write_t1c_h = '1' then
timer_a_may_interrupt <= '1';
timer_a_toggle <= not tmr_a_output_en;
timer_a_count <= data_in & timer_a_latch(7 downto 0);
timer_a_reload <= '0';
end if;
if reset='1' then
timer_a_may_interrupt <= '0';
timer_a_toggle <= '1';
timer_a_count <= latch_reset_pattern;
timer_a_reload <= '0';
end if;
end if;
end process;
timer_a_out <= timer_a_toggle;
timer_a_event <= rising and timer_a_reload and timer_a_may_interrupt;
end block tmr_a;
-- Timer B
tmr_b: block
signal timer_b_reload_lo : std_logic;
signal timer_b_oneshot_trig : std_logic;
signal timer_b_timeout : std_logic;
signal pb6_c, pb6_d : std_logic;
begin
process(clock)
variable timer_b_decrement : std_logic;
begin
if rising_edge(clock) then
timer_b_decrement := '0';
if rising = '1' then
pb6_c <= To_X01(port_b_i(6));
pb6_d <= pb6_c;
end if;
if falling = '1' then
timer_b_timeout <= '0';
timer_b_tick <= '0';
if tmr_b_count_mode = '1' then
if (pb6_d='1' and pb6_c='0') then
timer_b_decrement := '1';
end if;
else -- one shot or used for shift register
timer_b_decrement := '1';
end if;
if timer_b_decrement = '1' then
if timer_b_count = X"0000" then
if timer_b_oneshot_trig = '1' then
timer_b_oneshot_trig <= '0';
timer_b_timeout <= '1';
end if;
end if;
if timer_b_count(7 downto 0) = X"00" then
case shift_mode_control is
when "001" | "101" | "100" =>
timer_b_reload_lo <= '1';
timer_b_tick <= '1';
when others =>
null;
end case;
end if;
timer_b_count <= timer_b_count - X"0001";
end if;
if timer_b_reload_lo = '1' then
timer_b_count(7 downto 0) <= timer_b_latch(7 downto 0);
timer_b_reload_lo <= '0';
end if;
end if;
if write_t2c_h = '1' then
timer_b_count <= data_in & timer_b_latch(7 downto 0);
timer_b_oneshot_trig <= '1';
end if;
if reset='1' then
timer_b_count <= latch_reset_pattern;
timer_b_reload_lo <= '0';
timer_b_oneshot_trig <= '0';
end if;
end if;
end process;
timer_b_event <= rising and timer_b_timeout;
end block tmr_b;
ser: block
signal trigger_serial: std_logic;
signal shift_clock_d : std_logic;
signal shift_clock : std_logic;
signal shift_tick_r : std_logic;
signal shift_tick_f : std_logic;
signal shift_timer_tick : std_logic;
signal bit_cnt : integer range 0 to 7;
signal shift_pulse : std_logic;
begin
process(shift_active, timer_b_tick, shift_clk_sel, shift_clock, shift_clock_d, shift_timer_tick)
begin
case shift_clk_sel is
when "10" =>
shift_pulse <= '1';
when "00"|"01" =>
shift_pulse <= shift_timer_tick;
when others =>
shift_pulse <= shift_clock and not shift_clock_d;
end case;
if shift_active = '0' then
-- Mode 0 still loads the shift register to external pulse (MMBEEB SD-Card interface uses this)
if shift_mode_control = "000" then
shift_pulse <= shift_clock and not shift_clock_d;
else
shift_pulse <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if rising = '1' then
if shift_active='0' then
if shift_mode_control = "000" then
shift_clock <= cb1_d1;
else
shift_clock <= '1';
end if;
elsif shift_clk_sel = "11" then
shift_clock <= cb1_d1;
elsif shift_pulse = '1' then
shift_clock <= not shift_clock;
end if;
shift_clock_d <= shift_clock;
end if;
if falling = '1' then
shift_timer_tick <= timer_b_tick;
end if;
if reset = '1' then
shift_clock <= '1';
shift_clock_d <= '1';
end if;
end if;
end process;
cb1_t_int <= '0' when shift_clk_sel="11" else serport_en;
cb1_o_int <= shift_clock_d;
ser_cb2_o <= shift_reg(7);
serport_en <= shift_dir or shift_clk_sel(1) or shift_clk_sel(0);
trigger_serial <= '1' when (ren='1' or wen='1') and addr=x"A" else '0';
shift_tick_r <= not shift_clock_d and shift_clock;
shift_tick_f <= shift_clock_d and not shift_clock;
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
shift_reg <= X"FF";
elsif falling = '1' then
if wen = '1' and addr = X"A" then
shift_reg <= data_in;
elsif shift_dir='1' and shift_tick_f = '1' then -- output
shift_reg <= shift_reg(6 downto 0) & shift_reg(7);
elsif shift_dir='0' and shift_tick_r = '1' then -- input
shift_reg <= shift_reg(6 downto 0) & cb2_d1;
end if;
end if;
end if;
end process;
-- tell people that we're ready!
serial_event <= shift_tick_r and not shift_active and rising and serport_en;
process(clock)
begin
if rising_edge(clock) then
if falling = '1' then
if shift_active = '0' and shift_mode_control /= "000" then
if trigger_serial = '1' then
bit_cnt <= 7;
shift_active <= '1';
end if;
else -- we're active
if shift_clk_sel = "00" then
shift_active <= shift_dir; -- when '1' we're active, but for mode 000 we go inactive.
elsif shift_pulse = '1' and shift_clock = '1' then
if bit_cnt = 0 then
shift_active <= '0';
else
bit_cnt <= bit_cnt - 1;
end if;
end if;
end if;
end if;
if reset='1' then
shift_active <= '0';
bit_cnt <= 0;
end if;
end if;
end process;
end block ser;
end Gideon;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: mmuconfig
-- File: mmuconfig.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU types and constants
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
package mmuconfig is
constant M_CTX_SZ : integer := 8;
constant M_ENT_MAX : integer := 64;
constant XM_ENT_MAX_LOG : integer := log2(M_ENT_MAX);
constant M_ENT_MAX_LOG : integer := XM_ENT_MAX_LOG;
type mmu_idcache is (id_icache, id_dcache);
-- ##############################################################
-- 1.0 virtual address [sparc V8: p.243,Appx.H,Figure H-4]
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 24 23 18 17 12 11 0
constant VA_I1_SZ : integer := 8;
constant VA_I2_SZ : integer := 6;
constant VA_I3_SZ : integer := 6;
constant VA_I_SZ : integer := VA_I1_SZ+VA_I2_SZ+VA_I3_SZ;
constant VA_I_MAX : integer := 8;
constant VA_I1_U : integer := 31;
constant VA_I1_D : integer := 32-VA_I1_SZ;
constant VA_I2_U : integer := 31-VA_I1_SZ;
constant VA_I2_D : integer := 32-VA_I1_SZ-VA_I2_SZ;
constant VA_I3_U : integer := 31-VA_I1_SZ-VA_I2_SZ;
constant VA_I3_D : integer := 32-VA_I_SZ;
constant VA_I_U : integer := 31;
constant VA_I_D : integer := 32-VA_I_SZ;
constant VA_OFF_U : integer := 31-VA_I_SZ;
constant VA_OFF_D : integer := 0;
constant VA_OFFCTX_U : integer := 31;
constant VA_OFFCTX_D : integer := 0;
constant VA_OFFREG_U : integer := 31-VA_I1_SZ;
constant VA_OFFREG_D : integer := 0;
constant VA_OFFSEG_U : integer := 31-VA_I1_SZ-VA_I2_SZ;
constant VA_OFFSEG_D : integer := 0;
constant VA_OFFPAG_U : integer := 31-VA_I_SZ;
constant VA_OFFPAG_D : integer := 0;
-- 8k pages
-- 7 6 6 13
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 25 24 19 18 13 12 0
constant P8K_VA_I1_SZ : integer := 7;
constant P8K_VA_I2_SZ : integer := 6;
constant P8K_VA_I3_SZ : integer := 6;
constant P8K_VA_I_SZ : integer := P8K_VA_I1_SZ+P8K_VA_I2_SZ+P8K_VA_I3_SZ;
constant P8K_VA_I_MAX : integer := 7;
constant P8K_VA_I1_U : integer := 31;
constant P8K_VA_I1_D : integer := 32-P8K_VA_I1_SZ;
constant P8K_VA_I2_U : integer := 31-P8K_VA_I1_SZ;
constant P8K_VA_I2_D : integer := 32-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_VA_I3_U : integer := 31-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_VA_I3_D : integer := 32-P8K_VA_I_SZ;
constant P8K_VA_I_U : integer := 31;
constant P8K_VA_I_D : integer := 32-P8K_VA_I_SZ;
constant P8K_VA_OFF_U : integer := 31-P8K_VA_I_SZ;
constant P8K_VA_OFF_D : integer := 0;
constant P8K_VA_OFFCTX_U : integer := 31;
constant P8K_VA_OFFCTX_D : integer := 0;
constant P8K_VA_OFFREG_U : integer := 31-P8K_VA_I1_SZ;
constant P8K_VA_OFFREG_D : integer := 0;
constant P8K_VA_OFFSEG_U : integer := 31-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_VA_OFFSEG_D : integer := 0;
constant P8K_VA_OFFPAG_U : integer := 31-P8K_VA_I_SZ;
constant P8K_VA_OFFPAG_D : integer := 0;
-- 16k pages
-- 6 6 6 14
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 26 25 20 19 14 13 0
constant P16K_VA_I1_SZ : integer := 6;
constant P16K_VA_I2_SZ : integer := 6;
constant P16K_VA_I3_SZ : integer := 6;
constant P16K_VA_I_SZ : integer := P16K_VA_I1_SZ+P16K_VA_I2_SZ+P16K_VA_I3_SZ;
constant P16K_VA_I_MAX : integer := 6;
constant P16K_VA_I1_U : integer := 31;
constant P16K_VA_I1_D : integer := 32-P16K_VA_I1_SZ;
constant P16K_VA_I2_U : integer := 31-P16K_VA_I1_SZ;
constant P16K_VA_I2_D : integer := 32-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_VA_I3_U : integer := 31-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_VA_I3_D : integer := 32-P16K_VA_I_SZ;
constant P16K_VA_I_U : integer := 31;
constant P16K_VA_I_D : integer := 32-P16K_VA_I_SZ;
constant P16K_VA_OFF_U : integer := 31-P16K_VA_I_SZ;
constant P16K_VA_OFF_D : integer := 0;
constant P16K_VA_OFFCTX_U : integer := 31;
constant P16K_VA_OFFCTX_D : integer := 0;
constant P16K_VA_OFFREG_U : integer := 31-P16K_VA_I1_SZ;
constant P16K_VA_OFFREG_D : integer := 0;
constant P16K_VA_OFFSEG_U : integer := 31-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_VA_OFFSEG_D : integer := 0;
constant P16K_VA_OFFPAG_U : integer := 31-P16K_VA_I_SZ;
constant P16K_VA_OFFPAG_D : integer := 0;
-- 32k pages
-- 4 7 6 15
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 28 27 21 20 15 14 0
constant P32K_VA_I1_SZ : integer := 4;
constant P32K_VA_I2_SZ : integer := 7;
constant P32K_VA_I3_SZ : integer := 6;
constant P32K_VA_I_SZ : integer := P32K_VA_I1_SZ+P32K_VA_I2_SZ+P32K_VA_I3_SZ;
constant P32K_VA_I_MAX : integer := 7;
constant P32K_VA_I1_U : integer := 31;
constant P32K_VA_I1_D : integer := 32-P32K_VA_I1_SZ;
constant P32K_VA_I2_U : integer := 31-P32K_VA_I1_SZ;
constant P32K_VA_I2_D : integer := 32-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_VA_I3_U : integer := 31-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_VA_I3_D : integer := 32-P32K_VA_I_SZ;
constant P32K_VA_I_U : integer := 31;
constant P32K_VA_I_D : integer := 32-P32K_VA_I_SZ;
constant P32K_VA_OFF_U : integer := 31-P32K_VA_I_SZ;
constant P32K_VA_OFF_D : integer := 0;
constant P32K_VA_OFFCTX_U : integer := 31;
constant P32K_VA_OFFCTX_D : integer := 0;
constant P32K_VA_OFFREG_U : integer := 31-P32K_VA_I1_SZ;
constant P32K_VA_OFFREG_D : integer := 0;
constant P32K_VA_OFFSEG_U : integer := 31-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_VA_OFFSEG_D : integer := 0;
constant P32K_VA_OFFPAG_U : integer := 31-P32K_VA_I_SZ;
constant P32K_VA_OFFPAG_D : integer := 0;
-- ##############################################################
-- 2.0 PAGE TABE DESCRIPTOR (PTD) [sparc V8: p.247,Appx.H,Figure H-7]
--
-- +-------------------------------------------------+---+---+
-- | Page Table Pointer (PTP) | 0 | 0 |
-- +-------------------------------------------------+---+---+
-- 31 2 1 0
--
-- 2.1 PAGE TABE ENTRY (PTE) [sparc V8: p.247,Appx.H,Figure H-8]
--
-- +-----------------------------+---+---+---+-----------+---+
-- |Physical Page Number (PPN) | C | M | R | ACC | ET|
-- +-----------------------------+---+---+---+-----------+---+
-- 31 8 7 6 5 4 2 1 0
--
constant PTD_PTP_U : integer := 31; -- PTD: page table pointer
constant PTD_PTP_D : integer := 2;
constant PTD_PTP32_U : integer := 27; -- PTD: page table pointer 32 bit
constant PTD_PTP32_D : integer := 2;
constant PTE_PPN_U : integer := 31; -- PTE: physical page number
constant PTE_PPN_D : integer := 8;
constant PTE_PPN_S : integer := (PTE_PPN_U+1)-PTE_PPN_D; -- PTE: pysical page number size
constant PTE_PPN32_U : integer := 27; -- PTE: physical page number 32 bit addr
constant PTE_PPN32_D : integer := 8;
constant PTE_PPN32_S : integer := (PTE_PPN32_U+1)-PTE_PPN32_D; -- PTE: pysical page number 32 bit size
constant PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant PTE_PPN32REG_D : integer := PTE_PPN32_U+1-VA_I1_SZ;
constant PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-VA_I1_SZ-VA_I2_SZ;
constant PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-VA_I_SZ;
-- 8k pages
constant P8K_PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant P8K_PTE_PPN32REG_D : integer := PTE_PPN32_U+1-P8K_VA_I1_SZ;
constant P8K_PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant P8K_PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant P8K_PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-P8K_VA_I_SZ;
-- 16k pages
constant P16K_PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant P16K_PTE_PPN32REG_D : integer := PTE_PPN32_U+1-P16K_VA_I1_SZ;
constant P16K_PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant P16K_PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant P16K_PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-P16K_VA_I_SZ;
-- 32k pages
constant P32K_PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant P32K_PTE_PPN32REG_D : integer := PTE_PPN32_U+1-P32K_VA_I1_SZ;
constant P32K_PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant P32K_PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant P32K_PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-P32K_VA_I_SZ;
constant PTE_C : integer := 7; -- PTE: Cacheable bit
constant PTE_M : integer := 6; -- PTE: Modified bit
constant PTE_R : integer := 5; -- PTE: Reference Bit - a "1" indicates an PTE
constant PTE_ACC_U : integer := 4; -- PTE: Access field
constant PTE_ACC_D : integer := 2;
constant ACC_W : integer := 2; -- PTE::ACC : write permission
constant ACC_E : integer := 3; -- PTE::ACC : exec permission
constant ACC_SU : integer := 4; -- PTE::ACC : privileged
constant PT_ET_U : integer := 1; -- PTD/PTE: PTE Type
constant PT_ET_D : integer := 0;
constant ET_INV : std_logic_vector(1 downto 0) := "00";
constant ET_PTD : std_logic_vector(1 downto 0) := "01";
constant ET_PTE : std_logic_vector(1 downto 0) := "10";
constant ET_RVD : std_logic_vector(1 downto 0) := "11";
constant PADDR_PTD_U : integer := 31;
constant PADDR_PTD_D : integer := 6;
-- ##############################################################
-- 3.0 TLBCAM TAG hardware representation (TTG)
--
type tlbcam_reg is record
ET : std_logic_vector(1 downto 0); -- et field
ACC : std_logic_vector(2 downto 0); -- on flush/probe this will become FPTY
M : std_logic; -- modified
R : std_logic; -- referenced
SU : std_logic; -- equal ACC >= 6
VALID : std_logic;
LVL : std_logic_vector(1 downto 0); -- level in pth
I1 : std_logic_vector(7 downto 0); -- vaddr
I2 : std_logic_vector(5 downto 0);
I3 : std_logic_vector(5 downto 0);
CTX : std_logic_vector(M_CTX_SZ-1 downto 0); -- ctx number
PPN : std_logic_vector(PTE_PPN_S-1 downto 0); -- physical page number
C : std_logic; -- cachable
end record;
constant tlbcam_reg_none : tlbcam_reg := ("00", "000", '0', '0', '0', '0',
"00", "00000000", "000000", "000000", "00000000", (others => '0'), '0');
-- tlbcam_reg::LVL
constant LVL_PAGE : std_logic_vector(1 downto 0) := "00"; -- equal tlbcam_tfp::TYP FPTY_PAGE
constant LVL_SEGMENT : std_logic_vector(1 downto 0) := "01"; -- equal tlbcam_tfp::TYP FPTY_SEGMENT
constant LVL_REGION : std_logic_vector(1 downto 0) := "10"; -- equal tlbcam_tfp::TYP FPTY_REGION
constant LVL_CTX : std_logic_vector(1 downto 0) := "11"; -- equal tlbcam_tfp::TYP FPTY_CTX
-- ##############################################################
-- 4.0 TLBCAM tag i/o for translation/flush/(probe)
--
type tlbcam_tfp is record
TYP : std_logic_vector(2 downto 0); -- f/(p) type
I1 : std_logic_vector(7 downto 0); -- vaddr
I2 : std_logic_vector(5 downto 0);
I3 : std_logic_vector(5 downto 0);
CTX : std_logic_vector(M_CTX_SZ-1 downto 0); -- ctx number
M : std_logic;
end record;
constant tlbcam_tfp_none : tlbcam_tfp := ("000", "00000000", "000000", "000000", "00000000", '0');
--tlbcam_tfp::TYP
constant FPTY_PAGE : std_logic_vector(2 downto 0) := "000"; -- level 3 PTE match I1+I2+I3
constant FPTY_SEGMENT : std_logic_vector(2 downto 0) := "001"; -- level 2/3 PTE/PTD match I1+I2
constant FPTY_REGION : std_logic_vector(2 downto 0) := "010"; -- level 1/2/3 PTE/PTD match I1
constant FPTY_CTX : std_logic_vector(2 downto 0) := "011"; -- level 0/1/2/3 PTE/PTD ctx
constant FPTY_N : std_logic_vector(2 downto 0) := "100"; -- entire tlb
-- ##############################################################
-- 5.0 MMU Control Register [sparc V8: p.253,Appx.H,Figure H-10]
--
-- +-------+-----+------------------+-----+-------+--+--+
-- | IMPL | VER | SC | PSO | resvd |NF|E |
-- +-------+-----+------------------+-----+-------+--+--+
-- 31 28 27 24 23 8 7 6 2 1 0
--
-- MMU Context Pointer [sparc V8: p.254,Appx.H,Figure H-11]
-- +-------------------------------------------+--------+
-- | Context Table Pointer | resvd |
-- +-------------------------------------------+--------+
-- 31 2 1 0
--
-- MMU Context Number [sparc V8: p.255,Appx.H,Figure H-12]
-- +----------------------------------------------------+
-- | Context Table Pointer |
-- +----------------------------------------------------+
-- 31 0
--
-- fault status/address register [sparc V8: p.256,Appx.H,Table H-13/14]
-- +------------+-----+---+----+----+-----+----+
-- | reserved | EBE | L | AT | FT | FAV | OW |
-- +------------+-----+---+----+----+-----+----+
-- 31 18 17 10 9 8 7 5 4 2 1 0
--
-- +----------------------------------------------------+
-- | fault address register |
-- +----------------------------------------------------+
-- 31 0
constant MMCTRL_CTXP_SZ : integer := 30;
constant MMCTRL_PTP32_U : integer := 25;
constant MMCTRL_PTP32_D : integer := 0;
constant MMCTRL_E : integer := 0;
constant MMCTRL_NF : integer := 1;
constant MMCTRL_PSO : integer := 7;
constant MMCTRL_SC_U : integer := 23;
constant MMCTRL_SC_D : integer := 8;
constant MMCTRL_PGSZ_U : integer := 17;
constant MMCTRL_PGSZ_D : integer := 16;
constant MMCTRL_VER_U : integer := 27;
constant MMCTRL_VER_D : integer := 24;
constant MMCTRL_IMPL_U : integer := 31;
constant MMCTRL_IMPL_D : integer := 28;
constant MMCTRL_TLBDIS : integer := 15;
constant MMCTRL_TLBSEP : integer := 14;
constant MMCTXP_U : integer := 31;
constant MMCTXP_D : integer := 2;
constant MMCTXNR_U : integer := M_CTX_SZ-1;
constant MMCTXNR_D : integer := 0;
constant FS_SZ : integer := 18; -- fault status size
constant FS_EBE_U : integer := 17;
constant FS_EBE_D : integer := 10;
constant FS_L_U : integer := 9;
constant FS_L_D : integer := 8;
constant FS_L_CTX : std_logic_vector(1 downto 0) := "00";
constant FS_L_L1 : std_logic_vector(1 downto 0) := "01";
constant FS_L_L2 : std_logic_vector(1 downto 0) := "10";
constant FS_L_L3 : std_logic_vector(1 downto 0) := "11";
constant FS_AT_U : integer := 7;
constant FS_AT_D : integer := 5;
constant FS_AT_LS : natural := 7; --L=0 S=1
constant FS_AT_ID : natural := 6; --D=0 I=1
constant FS_AT_SU : natural := 5; --U=0 SU=1
constant FS_AT_LUDS : std_logic_vector(2 downto 0) := "000";
constant FS_AT_LSDS : std_logic_vector(2 downto 0) := "001";
constant FS_AT_LUIS : std_logic_vector(2 downto 0) := "010";
constant FS_AT_LSIS : std_logic_vector(2 downto 0) := "011";
constant FS_AT_SUDS : std_logic_vector(2 downto 0) := "100";
constant FS_AT_SSDS : std_logic_vector(2 downto 0) := "101";
constant FS_AT_SUIS : std_logic_vector(2 downto 0) := "110";
constant FS_AT_SSIS : std_logic_vector(2 downto 0) := "111";
constant FS_FT_U : integer := 4;
constant FS_FT_D : integer := 2;
constant FS_FT_NONE : std_logic_vector(2 downto 0) := "000";
constant FS_FT_INV : std_logic_vector(2 downto 0) := "001";
constant FS_FT_PRO : std_logic_vector(2 downto 0) := "010";
constant FS_FT_PRI : std_logic_vector(2 downto 0) := "011";
constant FS_FT_TRANS : std_logic_vector(2 downto 0):= "100";
constant FS_FT_BUS : std_logic_vector(2 downto 0) := "101";
constant FS_FT_INT : std_logic_vector(2 downto 0) := "110";
constant FS_FT_RVD : std_logic_vector(2 downto 0) := "111";
constant FS_FAV : natural := 1;
constant FS_OW : natural := 0;
--# mmu ctrl reg
type mmctrl_type1 is record
e : std_logic; -- enable
nf : std_logic; -- no fault
pso : std_logic; -- partial store order
-- pre : std_logic; -- pretranslation source
-- pri : std_logic; -- i/d priority
pagesize : std_logic_vector(1 downto 0);-- page size
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);-- context nr
ctxp : std_logic_vector(MMCTRL_CTXP_SZ-1 downto 0); -- context table pointer
tlbdis : std_logic; -- tlb disabled
bar : std_logic_vector(1 downto 0); -- preplace barrier
end record;
constant mmctrl_type1_none : mmctrl_type1 := ('0', '0', '0', (others => '0'), (others => '0'), (others => '0'), '0', (others => '0'));
--# fault status reg
type mmctrl_fs_type is record
ow : std_logic;
fav : std_logic;
ft : std_logic_vector(2 downto 0); -- fault type
at_ls : std_logic; -- access type, load/store
at_id : std_logic; -- access type, i/dcache
at_su : std_logic; -- access type, su/user
l : std_logic_vector(1 downto 0); -- level
ebe : std_logic_vector(7 downto 0);
end record;
constant mmctrl_fs_zero : mmctrl_fs_type :=
('0', '0', "000", '0', '0', '0', "00", "00000000");
type mmctrl_type2 is record
fs : mmctrl_fs_type;
valid : std_logic;
fa : std_logic_vector(VA_I_SZ-1 downto 0); -- fault address register
end record;
constant mmctrl2_zero : mmctrl_type2 :=
(mmctrl_fs_zero, '0', zero32(VA_I_SZ-1 downto 0));
-- ##############################################################
-- 6. Virtual Flush/Probe address [sparc V8: p.249,Appx.H,Figure H-9]
-- +---------------------------------------+--------+-------+
-- | VIRTUAL FLUSH&Probe Address (VFPA) | type | rvd |
-- +---------------------------------------+--------+-------+
-- 31 12 11 8 7 0
--
--
subtype FPA is natural range 31 downto 12;
constant FPA_I1_U : integer := 31;
constant FPA_I1_D : integer := 24;
constant FPA_I2_U : integer := 23;
constant FPA_I2_D : integer := 18;
constant FPA_I3_U : integer := 17;
constant FPA_I3_D : integer := 12;
constant FPTY_U : integer := 10; -- only 3 bits
constant FPTY_D : integer := 8;
-- ##############################################################
-- 7. control register virtual address [sparc V8: p.253,Appx.H,Table H-5]
-- +---------------------------------+-----+--------+
-- | | CNR | rsvd |
-- +---------------------------------+-----+--------+
-- 31 10 8 7 0
constant CNR_U : integer := 10;
constant CNR_D : integer := 8;
constant CNR_CTRL : std_logic_vector(2 downto 0) := "000";
constant CNR_CTXP : std_logic_vector(2 downto 0) := "001";
constant CNR_CTX : std_logic_vector(2 downto 0) := "010";
constant CNR_F : std_logic_vector(2 downto 0) := "011";
constant CNR_FADDR : std_logic_vector(2 downto 0) := "100";
-- ##############################################################
-- 8. Precise flush (ASI 0x10-14) [sparc V8: p.266,Appx.I]
-- supported: ASI_FLUSH_PAGE
-- ASI_FLUSH_CTX
constant PFLUSH_PAGE : std_logic := '0';
constant PFLUSH_CTX : std_logic := '1';
-- ##############################################################
-- 9. Diagnostic access
--
constant DIAGF_LVL_U : integer := 1;
constant DIAGF_LVL_D : integer := 0;
constant DIAGF_WR : integer := 3;
constant DIAGF_HIT : integer := 4;
constant DIAGF_CTX_U : integer := 12;
constant DIAGF_CTX_D : integer := 5;
constant DIAGF_VALID : integer := 13;
end mmuconfig;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:07:01 11/16/2013
-- Design Name:
-- Module Name: myMux2X1_948282 - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity myMux2X1_948282 is
Port ( A : in STD_LOGIC_VECTOR (4 downto 0);
B : in STD_LOGIC_VECTOR (4 downto 0);
Op : in STD_LOGIC;
result : out STD_LOGIC_VECTOR (4 downto 0));
end myMux2X1_948282;
architecture Behavorial of myMux2X1_948282 is
component myNanddown_948282 is
Port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
o1 : out STD_LOGIC);
end component;
component myNOT_948282 is
Port ( i1 : in STD_LOGIC;
o1 : out STD_LOGIC);
end component;
signal sig2, sig3, sig4, sig5, sig6, sig7: std_logic;
signal sig1i,sig2i, sig3i, sig4i, sig5i, sig6i, sig7i: std_logic;
signal sig2j,sig1j, sig3j, sig4j, sig5j, sig6j, sig7j: std_logic;
signal sig2k, sig3k,sig1k, sig4k, sig5k, sig6k, sig7k: std_logic;
signal sig1l, sig2l, sig3l, sig4l, sig5l, sig6l, sig7l: std_logic;
signal sig1: std_logic;
begin
u0: myNOT_948282 port map (i1=>Op, o1=>sig1);
u1: myNanddown_948282 port map (i0=>sig1, i1=>B(0), o1=>sig2);
u2: myNot_948282 port map (i1=>sig2, o1=>sig3);
u3: myNanddown_948282 port map (i0=>sig3, i1=>sig3, o1=>sig4);
u4: myNanddown_948282 port map (i0=>Op, i1=>A(0), o1=>sig5);
u5: MyNot_948282 port map (i1=>sig5, o1=>sig6);
u6: MyNanddown_948282 port map (i0=>sig6, i1=>sig6, o1=>sig7);
u7: MyNanddown_948282 port map (i0=>sig4, i1=>sig7, o1=>result(0));
u8: myNOT_948282 port map (i1=>Op, o1=>sig1i);
u9: myNanddown_948282 port map (i0=>sig1i, i1=>B(1), o1=>sig2i);
u10: myNot_948282 port map (i1=>sig2i, o1=>sig3i);
u11: myNanddown_948282 port map (i0=>sig3i, i1=>sig3i, o1=>sig4i);
u12: myNanddown_948282 port map (i0=>Op, i1=>A(1), o1=>sig5i);
u13: MyNot_948282 port map (i1=>sig5i, o1=>sig6i);
u14: MyNanddown_948282 port map (i0=>sig6i, i1=>sig6i, o1=>sig7i);
u15: MyNanddown_948282 port map (i0=>sig4i, i1=>sig7i, o1=>result(1));
u16: myNOT_948282 port map (i1=>Op, o1=>sig1j);
u17: myNanddown_948282 port map (i0=>sig1j, i1=>B(2), o1=>sig2j);
u18: myNot_948282 port map (i1=>sig2j, o1=>sig3j);
u19: myNanddown_948282 port map (i0=>sig3j, i1=>sig3j, o1=>sig4j);
u20: myNanddown_948282 port map (i0=>Op, i1=>A(2), o1=>sig5j);
u21: MyNot_948282 port map (i1=>sig5j, o1=>sig6j);
u22: MyNanddown_948282 port map (i0=>sig6j, i1=>sig6j, o1=>sig7j);
u23: MyNanddown_948282 port map (i0=>sig4j, i1=>sig7j, o1=>result(2));
u24: myNOT_948282 port map (i1=>Op, o1=>sig1k);
u25: myNanddown_948282 port map (i0=>sig1k, i1=>B(3), o1=>sig2k);
u26: myNot_948282 port map (i1=>sig2k, o1=>sig3k);
u27: myNanddown_948282 port map (i0=>sig3k, i1=>sig3k, o1=>sig4k);
u28: myNanddown_948282 port map (i0=>Op, i1=>A(3), o1=>sig5k);
u29: MyNot_948282 port map (i1=>sig5k, o1=>sig6k);
u30: MyNanddown_948282 port map (i0=>sig6k, i1=>sig6k, o1=>sig7k);
u31: MyNanddown_948282 port map (i0=>sig4k, i1=>sig7k, o1=>result(3));
u32: myNOT_948282 port map (i1=>Op, o1=>sig1l);
u33: myNanddown_948282 port map (i0=>sig1l, i1=>B(4), o1=>sig2l);
u34: myNot_948282 port map (i1=>sig2l, o1=>sig3l);
u35: myNanddown_948282 port map (i0=>sig3l, i1=>sig3l, o1=>sig4l);
u36: myNanddown_948282 port map (i0=>Op, i1=>A(4), o1=>sig5l);
u37: MyNot_948282 port map (i1=>sig5l, o1=>sig6l);
u38: MyNanddown_948282 port map (i0=>sig6l, i1=>sig6l, o1=>sig7l);
u39: MyNanddown_948282 port map (i0=>sig4l, i1=>sig7l, o1=>result(4));
end Behavorial;
|
--!-----------------------------------------------------------------------------
--! --
--! Weizmann Institute of Science --
--! Electronics & Data Acquisition Group --
--! --
--!-----------------------------------------------------------------------------
--!
--! unit name: centralRouter package
--!
--! author: [email protected]
--!
--! date: $10/12/2014 $: created
--!
--! version: $Rev 0 $:
--!
--! description: package file for the centralRouter interface
--!
--!-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package centralRouter_package is
-------------------------------------------------------------------
-- general use type definitions
-------------------------------------------------------------------
type array7_std_logic_vector_15 is array (0 to 6) of std_logic_vector(14 downto 0);
type array8_std_logic_vector_15 is array (0 to 7) of std_logic_vector(14 downto 0);
type array8_std_logic_vector_16 is array (0 to 7) of std_logic_vector(15 downto 0);
type array7_std_logic_vector_8 is array (0 to 6) of std_logic_vector(7 downto 0);
type array8_std_logic_vector_8 is array (0 to 7) of std_logic_vector(7 downto 0);
type array15_std_logic_vector_7 is array (0 to 14) of std_logic_vector(6 downto 0);
type array15_std_logic_vector_8 is array (0 to 14) of std_logic_vector(7 downto 0);
type array15_std_logic_vector_6 is array (0 to 14) of std_logic_vector(5 downto 0);
type array15_std_logic_vector_3 is array (0 to 14) of std_logic_vector(2 downto 0);
-------------------------------------------------------------------
-- EPROC internal type definitions
-------------------------------------------------------------------
type isk_2array_type is array (0 to 1) of std_logic_vector(1 downto 0); -- 2 words of 2bit
type word8b_2array_type is array (0 to 1) of std_logic_vector(7 downto 0); -- 2 words of 8bit
type word10b_2array_type is array (0 to 1) of std_logic_vector(9 downto 0); -- 2 words of 10bit
type word10b_2array_4array_type is array (0 to 3) of word10b_2array_type; -- 4 groups of {2 words of 10bit}, one group per alignment
--
type isk_4array_type is array (0 to 3) of std_logic_vector(1 downto 0); -- 4 words of 2bit
type word8b_4array_type is array (0 to 3) of std_logic_vector(7 downto 0); -- 4 words of 8bit
type word10b_4array_type is array (0 to 3) of std_logic_vector(9 downto 0); -- 4 words of 10bit
type word10b_4array_8array_type is array (0 to 7) of word10b_4array_type; -- 8 groups of {4 words of 10bit}, one group per alignment
--
type isk_8array_type is array (0 to 7) of std_logic_vector(1 downto 0); -- 8 words of 2bit
type word8b_8array_type is array (0 to 7) of std_logic_vector(7 downto 0); -- 8 words of 8bit
type word10b_8array_type is array (0 to 7) of std_logic_vector(9 downto 0); -- 8 words of 10bit
type word10b_8array_16array_type is array (0 to 15) of word10b_8array_type; -- 16 groups of {8 words of 10bit}, one group per alignment
-------------------------------------------------------------------
-- 7 and 5 entry arrays of 16 input lines, 16bit line per EGROUP
-------------------------------------------------------------------
type from1GBTdata_array_type is array (0 to 6) of std_logic_vector(15 downto 0);
type to1GBTdata_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
type to1GBTdataNcode_array_type is array (0 to 4) of std_logic_vector(17 downto 0);
-------------------------------------------------------------------
-- N entry array of 16 output lines, 16bit output line per EGROUP
-------------------------------------------------------------------
type GBTdata_array_type is array ( NATURAL RANGE <>) of std_logic_vector(15 downto 0);
-------------------------------------------------------------------
-- GBT_NUM entry arrays
-------------------------------------------------------------------
type ic_data_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type cr_DIN_array_type is array ( NATURAL RANGE <>) of from1GBTdata_array_type;
type cr_DOUT_array_type is array ( NATURAL RANGE <>) of to1GBTdata_array_type;
type cr_8MSbs_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type cr_4bit_array_type is array ( NATURAL RANGE <>) of std_logic_vector(3 downto 0);
type TTCin_array_type is array ( NATURAL RANGE <>) of std_logic_vector(9 downto 0);
type DownFifoFull_mon_array_type is array ( NATURAL RANGE <>) of std_logic_vector(58 downto 0);
type fmch_monitor_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type busyOut_array_type is array ( NATURAL RANGE <>) of std_logic_vector(56 downto 0);
-------------------------------------------------------------------
-- Central Router configuration register arrays
-------------------------------------------------------------------
type crDownstreamConfig_type is array (0 to 7) of std_logic_vector(63 downto 0);
type crUpstreamConfig_type is array (0 to 5) of std_logic_vector(63 downto 0);
-------------------------------------------------------------------
-- 256-bit fifo out, one per GBT
-------------------------------------------------------------------
type d256b_array_type is array (natural range <>) of std_logic_vector(255 downto 0);
type txrx33b_type is array (natural range <>) of std_logic_vector(32 downto 0);
type GBTdm_data_array_type is array ( NATURAL RANGE <>) of std_logic_vector(255 downto 0);
type GBTdm_dsdata_array_type is array ( NATURAL RANGE <>) of std_logic_vector(31 downto 0);
type d32bit_array_type is array (0 to 255) of std_logic_vector(31 downto 0);
type d32bit_array32_type is array (0 to 31) of std_logic_vector(31 downto 0);
-------------------------------------------------------------------
-- 8 entry array of 8bit input
-------------------------------------------------------------------
type EPROC_FIFO_DIN_array_type is array (0 to 7) of std_logic_vector(7 downto 0);
type EPROC_FIFO_DIN_CODE_array_type is array (0 to 7) of std_logic_vector(1 downto 0);
-------------------------------------------------------------------
-- BLOCK size definition [in 16bit words]
-- chunck can span on part of a BLOCK or on several BLOCKs
-------------------------------------------------------------------
constant BLOCK_WORDn : std_logic_vector(9 downto 0) := "1000000000"; -- = 512 (number of 16-bit words in a block)
constant BLOCK_WORD32n : std_logic_vector(8 downto 0) := "100000000"; -- = 256 (number of 32-bit words in a block)
-------------------------------------------------------------------
-- 8b10b encoding / decoding parameters
-------------------------------------------------------------------
-- 1. 10-bit values
--- comma / idle character
constant COMMAp : std_logic_vector (9 downto 0) := "0011111010"; -- -K.28.5
constant COMMAn : std_logic_vector (9 downto 0) := "1100000101"; -- +K.28.5
--- start-of-chunk and end-of-chunk characters
constant EOCp : std_logic_vector (9 downto 0) := "0011110110"; -- -K.28.6
constant EOCn : std_logic_vector (9 downto 0) := "1100001001"; -- +K.28.6
constant SOCp : std_logic_vector (9 downto 0) := "0011111001"; -- -K.28.1
constant SOCn : std_logic_vector (9 downto 0) := "1100000110"; -- +K.28.1
--- start-of-busy and end-of-busy characters
constant SOBp : std_logic_vector (9 downto 0) := "0011110101"; -- -K.28.2
constant SOBn : std_logic_vector (9 downto 0) := "1100001010"; -- +K.28.2
constant EOBp : std_logic_vector (9 downto 0) := "0011110011"; -- -K.28.3
constant EOBn : std_logic_vector (9 downto 0) := "1100001100"; -- +K.28.3
-- 2. 8-bit values
constant Kchar_comma : std_logic_vector (7 downto 0) := "10111100"; -- K28.5
constant Kchar_eop : std_logic_vector (7 downto 0) := "11011100"; -- K28.6
constant Kchar_sop : std_logic_vector (7 downto 0) := "00111100"; -- K28.1
constant Kchar_sob : std_logic_vector (7 downto 0) := "01011100"; -- K28.2
constant Kchar_eob : std_logic_vector (7 downto 0) := "01111100"; -- K28.3
-------------------------------------------------------------------
-- HDLC encoding / decoding parameters
-------------------------------------------------------------------
constant HDLC_flag : std_logic_vector(7 downto 0) := "01111110";
-------------------------------------------------------------------
-- TTC ToHost Data type
-------------------------------------------------------------------
type TTC_ToHost_data_type is record
FMT : std_logic_vector(7 downto 0); --byte0
LEN : std_logic_vector(7 downto 0); --byte1
reserved0 : std_logic_vector(3 downto 0); --byte2
BCID : std_logic_vector(11 downto 0); --byte2,3
XL1ID : std_logic_vector(7 downto 0); --byte4
L1ID : std_logic_vector(23 downto 0); --byte 5,6,7
orbit : std_logic_vector(31 downto 0); --byte 8,9,10,11
trigger_type : std_logic_vector(15 downto 0); --byte 12,13
reserved1 : std_logic_vector(15 downto 0); --byte 14,15
L0ID : std_logic_vector(31 downto 0); --byte 16,17,18,19
data_rdy : std_logic;
end record;
----------------------------------------------------------------------------------
-- 7 EGROUPs configuration parameters:
----------------------------------------------------------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- MATLAB generated parameters, consistent with GBT LINK DATA EMULATOR .coe files
--<< begin
--
-- 1. EPROC_ENA_bits 15 bit vector per EGROUP (15 EPROCs in one EGROUP)
-- [EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN4 EPROC_IN4 EPROC_IN4 EPROC_IN4 EPROC_IN8 EPROC_IN8 EPROC_IN16]
--
type EPROC_ENA_bits_array_type is array (0 to 7) of std_logic_vector(14 downto 0);
constant EPROC_ENA_bits_array : EPROC_ENA_bits_array_type :=(
"000000000000110",
"000000001111000",
"000000000000001",
"111111110000000",
"110011000101000",
"001100111010000",
"110011000101000",
"100000000000000");
--
-- 2. PATH_ENCODING, 16 bit vector per EGROUP (2 bits per PATH, 8 PATHs in one EGROUP)
-- for each of 8 output paths: "00"=non, "01"=8b10b, "10"=HDLC
--
type EPROC_ENCODING_array_type is array (0 to 7) of std_logic_vector(15 downto 0);
constant PATH_ENCODING_array : EPROC_ENCODING_array_type :=(
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"1000000000000000");
--
-- 3. Maximal valid CHUNK length for data truncation
-- per GBT channel, 3MSBs per Eproc type
--
constant MAX_CHUNK_LEN_array : std_logic_vector(11 downto 0) := "000000000000";
--<< end
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
constant zeros17bits : std_logic_vector(16 downto 0) := (others=>'0');
constant zeros21bits : std_logic_vector(20 downto 0) := (others =>'0');
-------------------------------------------------------------------
-- initial conf. constants for the case of {TTC_test_mode = false}
--
-- NOT a TTC test, initial configuration is generated using Matlab,
-- according to the selected options in a gui.
-------------------------------------------------------------------
constant CR_TH_EGROUP0_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(0) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(0)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP1_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(1) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(1)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP2_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(2) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(2)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP3_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(3) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(3)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP4_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(4) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(4)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP5_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(5) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(5)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP6_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(6) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(6)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP7_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(7) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(7)); -- 15 bit: (14 downto 0)
-------------------------------------------------------------------
-- Initial configuration of the from-host path:
-- matched the initial configuration of the to-host path
-- (and the initial contents of the GBT data emulators)
-- this allows for the loop-back test without reconfiguration
-------------------------------------------------------------------
constant CR_FH_EGROUP0_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(0)(15 downto 14) &
"00" & PATH_ENCODING_array(0)(13 downto 12) &
"00" & PATH_ENCODING_array(0)(11 downto 10) &
"00" & PATH_ENCODING_array(0)(9 downto 8) &
"00" & PATH_ENCODING_array(0)(7 downto 6) &
"00" & PATH_ENCODING_array(0)(5 downto 4) &
"00" & PATH_ENCODING_array(0)(3 downto 2) &
"00" & PATH_ENCODING_array(0)(1 downto 0) &
EPROC_ENA_bits_array(0));
constant CR_FH_EGROUP1_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(1)(15 downto 14) &
"00" & PATH_ENCODING_array(1)(13 downto 12) &
"00" & PATH_ENCODING_array(1)(11 downto 10) &
"00" & PATH_ENCODING_array(1)(9 downto 8) &
"00" & PATH_ENCODING_array(1)(7 downto 6) &
"00" & PATH_ENCODING_array(1)(5 downto 4) &
"00" & PATH_ENCODING_array(1)(3 downto 2) &
"00" & PATH_ENCODING_array(1)(1 downto 0) &
EPROC_ENA_bits_array(1));
constant CR_FH_EGROUP2_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(2)(15 downto 14) &
"00" & PATH_ENCODING_array(2)(13 downto 12) &
"00" & PATH_ENCODING_array(2)(11 downto 10) &
"00" & PATH_ENCODING_array(2)(9 downto 8) &
"00" & PATH_ENCODING_array(2)(7 downto 6) &
"00" & PATH_ENCODING_array(2)(5 downto 4) &
"00" & PATH_ENCODING_array(2)(3 downto 2) &
"00" & PATH_ENCODING_array(2)(1 downto 0) &
EPROC_ENA_bits_array(2));
constant CR_FH_EGROUP3_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(3)(15 downto 14) &
"00" & PATH_ENCODING_array(3)(13 downto 12) &
"00" & PATH_ENCODING_array(3)(11 downto 10) &
"00" & PATH_ENCODING_array(3)(9 downto 8) &
"00" & PATH_ENCODING_array(3)(7 downto 6) &
"00" & PATH_ENCODING_array(3)(5 downto 4) &
"00" & PATH_ENCODING_array(3)(3 downto 2) &
"00" & PATH_ENCODING_array(3)(1 downto 0) &
EPROC_ENA_bits_array(3));
constant CR_FH_EGROUP4_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(4)(15 downto 14) &
"00" & PATH_ENCODING_array(4)(13 downto 12) &
"00" & PATH_ENCODING_array(4)(11 downto 10) &
"00" & PATH_ENCODING_array(4)(9 downto 8) &
"00" & PATH_ENCODING_array(4)(7 downto 6) &
"00" & PATH_ENCODING_array(4)(5 downto 4) &
"00" & PATH_ENCODING_array(4)(3 downto 2) &
"00" & PATH_ENCODING_array(4)(1 downto 0) &
EPROC_ENA_bits_array(4));
constant CR_FH_EGROUP5_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(7)(15 downto 14) &
"00" & PATH_ENCODING_array(7)(13 downto 12) &
"00" & PATH_ENCODING_array(7)(11 downto 10) &
"00" & PATH_ENCODING_array(7)(9 downto 8) &
"00" & PATH_ENCODING_array(7)(7 downto 6) &
"00" & PATH_ENCODING_array(7)(5 downto 4) &
"00" & PATH_ENCODING_array(7)(3 downto 2) &
"00" & PATH_ENCODING_array(7)(1 downto 0) &
EPROC_ENA_bits_array(7));
-------------------------------------------------------------------
-- initial configuration of the from- and to-host paths
-- for the case of {TTC_test_mode = true}
-- TTC test mode, normal GBT mode only!
-- Central Router generic 'wideMode' has to be set false.
-- Congifuration of TTC-from-host matches
-- the direct-to-host congifuration.
-- Trom-Host is TTC, to-Host is direct data.
-------------------------------------------------------------------
--
-- egroup0: 8 x EPROCx2s. direct data: TTC-0 (2bit) [B-chan L1A]
constant CR_FH_EGROUP0_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"33333333" & "111111110000000"; -- TTC-0
constant CR_TH_EGROUP0_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "111111110000000";
-- egroup1: 4 x EPROCx4s. direct data: TTC-1 (4bit) [B-chan ECR BCR L1A]
constant CR_FH_EGROUP1_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"03030303" & "000000001111000"; -- TTC-1
constant CR_TH_EGROUP1_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000001111000";
-- egroup2: 4 x EPROCx4s. direct data: TTC-2 (4bit) [Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP2_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"04040404" & "000000001111000"; -- TTC-2
constant CR_TH_EGROUP2_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000001111000";
-- egroup3: 2 x EPROCx8s. direct data: TTC-3 (8bit) [B-chan Brcst[5] Brcst[4] Brcst[3] Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP3_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"00300030" & "000000000000110"; -- TTC-3
constant CR_TH_EGROUP3_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000000000110";
-- egroup4: 2 x EPROCx8s. direct data: TTC-4 (8bit) [Brcst[6] Brcst[5] Brcst[4] Brcst[3] Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP4_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"00400040" & "000000000000110"; -- TTC-4
constant CR_TH_EGROUP4_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000000000110";
-- egroup7: 8 x EPROCx2s. direct data: TTC-0 (2bit) [B-chan L1A]
constant CR_FH_EGROUP5_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"33333333" & "111111110000000"; -- TTC-0
constant CR_TH_EGROUP7_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000000000110";
--
--
constant CR_TH_EGROUP5_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := (others=>'0');
constant CR_TH_EGROUP6_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := (others=>'0');
--
--
end package centralRouter_package ;
|
--!-----------------------------------------------------------------------------
--! --
--! Weizmann Institute of Science --
--! Electronics & Data Acquisition Group --
--! --
--!-----------------------------------------------------------------------------
--!
--! unit name: centralRouter package
--!
--! author: [email protected]
--!
--! date: $10/12/2014 $: created
--!
--! version: $Rev 0 $:
--!
--! description: package file for the centralRouter interface
--!
--!-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package centralRouter_package is
-------------------------------------------------------------------
-- general use type definitions
-------------------------------------------------------------------
type array7_std_logic_vector_15 is array (0 to 6) of std_logic_vector(14 downto 0);
type array8_std_logic_vector_15 is array (0 to 7) of std_logic_vector(14 downto 0);
type array8_std_logic_vector_16 is array (0 to 7) of std_logic_vector(15 downto 0);
type array7_std_logic_vector_8 is array (0 to 6) of std_logic_vector(7 downto 0);
type array8_std_logic_vector_8 is array (0 to 7) of std_logic_vector(7 downto 0);
type array15_std_logic_vector_7 is array (0 to 14) of std_logic_vector(6 downto 0);
type array15_std_logic_vector_8 is array (0 to 14) of std_logic_vector(7 downto 0);
type array15_std_logic_vector_6 is array (0 to 14) of std_logic_vector(5 downto 0);
type array15_std_logic_vector_3 is array (0 to 14) of std_logic_vector(2 downto 0);
-------------------------------------------------------------------
-- EPROC internal type definitions
-------------------------------------------------------------------
type isk_2array_type is array (0 to 1) of std_logic_vector(1 downto 0); -- 2 words of 2bit
type word8b_2array_type is array (0 to 1) of std_logic_vector(7 downto 0); -- 2 words of 8bit
type word10b_2array_type is array (0 to 1) of std_logic_vector(9 downto 0); -- 2 words of 10bit
type word10b_2array_4array_type is array (0 to 3) of word10b_2array_type; -- 4 groups of {2 words of 10bit}, one group per alignment
--
type isk_4array_type is array (0 to 3) of std_logic_vector(1 downto 0); -- 4 words of 2bit
type word8b_4array_type is array (0 to 3) of std_logic_vector(7 downto 0); -- 4 words of 8bit
type word10b_4array_type is array (0 to 3) of std_logic_vector(9 downto 0); -- 4 words of 10bit
type word10b_4array_8array_type is array (0 to 7) of word10b_4array_type; -- 8 groups of {4 words of 10bit}, one group per alignment
--
type isk_8array_type is array (0 to 7) of std_logic_vector(1 downto 0); -- 8 words of 2bit
type word8b_8array_type is array (0 to 7) of std_logic_vector(7 downto 0); -- 8 words of 8bit
type word10b_8array_type is array (0 to 7) of std_logic_vector(9 downto 0); -- 8 words of 10bit
type word10b_8array_16array_type is array (0 to 15) of word10b_8array_type; -- 16 groups of {8 words of 10bit}, one group per alignment
-------------------------------------------------------------------
-- 7 and 5 entry arrays of 16 input lines, 16bit line per EGROUP
-------------------------------------------------------------------
type from1GBTdata_array_type is array (0 to 6) of std_logic_vector(15 downto 0);
type to1GBTdata_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
type to1GBTdataNcode_array_type is array (0 to 4) of std_logic_vector(17 downto 0);
-------------------------------------------------------------------
-- N entry array of 16 output lines, 16bit output line per EGROUP
-------------------------------------------------------------------
type GBTdata_array_type is array ( NATURAL RANGE <>) of std_logic_vector(15 downto 0);
-------------------------------------------------------------------
-- GBT_NUM entry arrays
-------------------------------------------------------------------
type ic_data_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type cr_DIN_array_type is array ( NATURAL RANGE <>) of from1GBTdata_array_type;
type cr_DOUT_array_type is array ( NATURAL RANGE <>) of to1GBTdata_array_type;
type cr_8MSbs_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type cr_4bit_array_type is array ( NATURAL RANGE <>) of std_logic_vector(3 downto 0);
type TTCin_array_type is array ( NATURAL RANGE <>) of std_logic_vector(9 downto 0);
type DownFifoFull_mon_array_type is array ( NATURAL RANGE <>) of std_logic_vector(58 downto 0);
type fmch_monitor_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type busyOut_array_type is array ( NATURAL RANGE <>) of std_logic_vector(56 downto 0);
-------------------------------------------------------------------
-- Central Router configuration register arrays
-------------------------------------------------------------------
type crDownstreamConfig_type is array (0 to 7) of std_logic_vector(63 downto 0);
type crUpstreamConfig_type is array (0 to 5) of std_logic_vector(63 downto 0);
-------------------------------------------------------------------
-- 256-bit fifo out, one per GBT
-------------------------------------------------------------------
type d256b_array_type is array (natural range <>) of std_logic_vector(255 downto 0);
type txrx33b_type is array (natural range <>) of std_logic_vector(32 downto 0);
type GBTdm_data_array_type is array ( NATURAL RANGE <>) of std_logic_vector(255 downto 0);
type GBTdm_dsdata_array_type is array ( NATURAL RANGE <>) of std_logic_vector(31 downto 0);
type d32bit_array_type is array (0 to 255) of std_logic_vector(31 downto 0);
type d32bit_array32_type is array (0 to 31) of std_logic_vector(31 downto 0);
-------------------------------------------------------------------
-- 8 entry array of 8bit input
-------------------------------------------------------------------
type EPROC_FIFO_DIN_array_type is array (0 to 7) of std_logic_vector(7 downto 0);
type EPROC_FIFO_DIN_CODE_array_type is array (0 to 7) of std_logic_vector(1 downto 0);
-------------------------------------------------------------------
-- BLOCK size definition [in 16bit words]
-- chunck can span on part of a BLOCK or on several BLOCKs
-------------------------------------------------------------------
constant BLOCK_WORDn : std_logic_vector(9 downto 0) := "1000000000"; -- = 512 (number of 16-bit words in a block)
constant BLOCK_WORD32n : std_logic_vector(8 downto 0) := "100000000"; -- = 256 (number of 32-bit words in a block)
-------------------------------------------------------------------
-- 8b10b encoding / decoding parameters
-------------------------------------------------------------------
-- 1. 10-bit values
--- comma / idle character
constant COMMAp : std_logic_vector (9 downto 0) := "0011111010"; -- -K.28.5
constant COMMAn : std_logic_vector (9 downto 0) := "1100000101"; -- +K.28.5
--- start-of-chunk and end-of-chunk characters
constant EOCp : std_logic_vector (9 downto 0) := "0011110110"; -- -K.28.6
constant EOCn : std_logic_vector (9 downto 0) := "1100001001"; -- +K.28.6
constant SOCp : std_logic_vector (9 downto 0) := "0011111001"; -- -K.28.1
constant SOCn : std_logic_vector (9 downto 0) := "1100000110"; -- +K.28.1
--- start-of-busy and end-of-busy characters
constant SOBp : std_logic_vector (9 downto 0) := "0011110101"; -- -K.28.2
constant SOBn : std_logic_vector (9 downto 0) := "1100001010"; -- +K.28.2
constant EOBp : std_logic_vector (9 downto 0) := "0011110011"; -- -K.28.3
constant EOBn : std_logic_vector (9 downto 0) := "1100001100"; -- +K.28.3
-- 2. 8-bit values
constant Kchar_comma : std_logic_vector (7 downto 0) := "10111100"; -- K28.5
constant Kchar_eop : std_logic_vector (7 downto 0) := "11011100"; -- K28.6
constant Kchar_sop : std_logic_vector (7 downto 0) := "00111100"; -- K28.1
constant Kchar_sob : std_logic_vector (7 downto 0) := "01011100"; -- K28.2
constant Kchar_eob : std_logic_vector (7 downto 0) := "01111100"; -- K28.3
-------------------------------------------------------------------
-- HDLC encoding / decoding parameters
-------------------------------------------------------------------
constant HDLC_flag : std_logic_vector(7 downto 0) := "01111110";
-------------------------------------------------------------------
-- TTC ToHost Data type
-------------------------------------------------------------------
type TTC_ToHost_data_type is record
FMT : std_logic_vector(7 downto 0); --byte0
LEN : std_logic_vector(7 downto 0); --byte1
reserved0 : std_logic_vector(3 downto 0); --byte2
BCID : std_logic_vector(11 downto 0); --byte2,3
XL1ID : std_logic_vector(7 downto 0); --byte4
L1ID : std_logic_vector(23 downto 0); --byte 5,6,7
orbit : std_logic_vector(31 downto 0); --byte 8,9,10,11
trigger_type : std_logic_vector(15 downto 0); --byte 12,13
reserved1 : std_logic_vector(15 downto 0); --byte 14,15
L0ID : std_logic_vector(31 downto 0); --byte 16,17,18,19
data_rdy : std_logic;
end record;
----------------------------------------------------------------------------------
-- 7 EGROUPs configuration parameters:
----------------------------------------------------------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- MATLAB generated parameters, consistent with GBT LINK DATA EMULATOR .coe files
--<< begin
--
-- 1. EPROC_ENA_bits 15 bit vector per EGROUP (15 EPROCs in one EGROUP)
-- [EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN4 EPROC_IN4 EPROC_IN4 EPROC_IN4 EPROC_IN8 EPROC_IN8 EPROC_IN16]
--
type EPROC_ENA_bits_array_type is array (0 to 7) of std_logic_vector(14 downto 0);
constant EPROC_ENA_bits_array : EPROC_ENA_bits_array_type :=(
"000000000000110",
"000000001111000",
"000000000000001",
"111111110000000",
"110011000101000",
"001100111010000",
"110011000101000",
"100000000000000");
--
-- 2. PATH_ENCODING, 16 bit vector per EGROUP (2 bits per PATH, 8 PATHs in one EGROUP)
-- for each of 8 output paths: "00"=non, "01"=8b10b, "10"=HDLC
--
type EPROC_ENCODING_array_type is array (0 to 7) of std_logic_vector(15 downto 0);
constant PATH_ENCODING_array : EPROC_ENCODING_array_type :=(
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"1000000000000000");
--
-- 3. Maximal valid CHUNK length for data truncation
-- per GBT channel, 3MSBs per Eproc type
--
constant MAX_CHUNK_LEN_array : std_logic_vector(11 downto 0) := "000000000000";
--<< end
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
constant zeros17bits : std_logic_vector(16 downto 0) := (others=>'0');
constant zeros21bits : std_logic_vector(20 downto 0) := (others =>'0');
-------------------------------------------------------------------
-- initial conf. constants for the case of {TTC_test_mode = false}
--
-- NOT a TTC test, initial configuration is generated using Matlab,
-- according to the selected options in a gui.
-------------------------------------------------------------------
constant CR_TH_EGROUP0_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(0) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(0)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP1_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(1) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(1)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP2_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(2) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(2)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP3_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(3) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(3)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP4_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(4) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(4)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP5_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(5) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(5)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP6_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(6) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(6)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP7_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(7) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(7)); -- 15 bit: (14 downto 0)
-------------------------------------------------------------------
-- Initial configuration of the from-host path:
-- matched the initial configuration of the to-host path
-- (and the initial contents of the GBT data emulators)
-- this allows for the loop-back test without reconfiguration
-------------------------------------------------------------------
constant CR_FH_EGROUP0_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(0)(15 downto 14) &
"00" & PATH_ENCODING_array(0)(13 downto 12) &
"00" & PATH_ENCODING_array(0)(11 downto 10) &
"00" & PATH_ENCODING_array(0)(9 downto 8) &
"00" & PATH_ENCODING_array(0)(7 downto 6) &
"00" & PATH_ENCODING_array(0)(5 downto 4) &
"00" & PATH_ENCODING_array(0)(3 downto 2) &
"00" & PATH_ENCODING_array(0)(1 downto 0) &
EPROC_ENA_bits_array(0));
constant CR_FH_EGROUP1_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(1)(15 downto 14) &
"00" & PATH_ENCODING_array(1)(13 downto 12) &
"00" & PATH_ENCODING_array(1)(11 downto 10) &
"00" & PATH_ENCODING_array(1)(9 downto 8) &
"00" & PATH_ENCODING_array(1)(7 downto 6) &
"00" & PATH_ENCODING_array(1)(5 downto 4) &
"00" & PATH_ENCODING_array(1)(3 downto 2) &
"00" & PATH_ENCODING_array(1)(1 downto 0) &
EPROC_ENA_bits_array(1));
constant CR_FH_EGROUP2_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(2)(15 downto 14) &
"00" & PATH_ENCODING_array(2)(13 downto 12) &
"00" & PATH_ENCODING_array(2)(11 downto 10) &
"00" & PATH_ENCODING_array(2)(9 downto 8) &
"00" & PATH_ENCODING_array(2)(7 downto 6) &
"00" & PATH_ENCODING_array(2)(5 downto 4) &
"00" & PATH_ENCODING_array(2)(3 downto 2) &
"00" & PATH_ENCODING_array(2)(1 downto 0) &
EPROC_ENA_bits_array(2));
constant CR_FH_EGROUP3_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(3)(15 downto 14) &
"00" & PATH_ENCODING_array(3)(13 downto 12) &
"00" & PATH_ENCODING_array(3)(11 downto 10) &
"00" & PATH_ENCODING_array(3)(9 downto 8) &
"00" & PATH_ENCODING_array(3)(7 downto 6) &
"00" & PATH_ENCODING_array(3)(5 downto 4) &
"00" & PATH_ENCODING_array(3)(3 downto 2) &
"00" & PATH_ENCODING_array(3)(1 downto 0) &
EPROC_ENA_bits_array(3));
constant CR_FH_EGROUP4_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(4)(15 downto 14) &
"00" & PATH_ENCODING_array(4)(13 downto 12) &
"00" & PATH_ENCODING_array(4)(11 downto 10) &
"00" & PATH_ENCODING_array(4)(9 downto 8) &
"00" & PATH_ENCODING_array(4)(7 downto 6) &
"00" & PATH_ENCODING_array(4)(5 downto 4) &
"00" & PATH_ENCODING_array(4)(3 downto 2) &
"00" & PATH_ENCODING_array(4)(1 downto 0) &
EPROC_ENA_bits_array(4));
constant CR_FH_EGROUP5_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(7)(15 downto 14) &
"00" & PATH_ENCODING_array(7)(13 downto 12) &
"00" & PATH_ENCODING_array(7)(11 downto 10) &
"00" & PATH_ENCODING_array(7)(9 downto 8) &
"00" & PATH_ENCODING_array(7)(7 downto 6) &
"00" & PATH_ENCODING_array(7)(5 downto 4) &
"00" & PATH_ENCODING_array(7)(3 downto 2) &
"00" & PATH_ENCODING_array(7)(1 downto 0) &
EPROC_ENA_bits_array(7));
-------------------------------------------------------------------
-- initial configuration of the from- and to-host paths
-- for the case of {TTC_test_mode = true}
-- TTC test mode, normal GBT mode only!
-- Central Router generic 'wideMode' has to be set false.
-- Congifuration of TTC-from-host matches
-- the direct-to-host congifuration.
-- Trom-Host is TTC, to-Host is direct data.
-------------------------------------------------------------------
--
-- egroup0: 8 x EPROCx2s. direct data: TTC-0 (2bit) [B-chan L1A]
constant CR_FH_EGROUP0_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"33333333" & "111111110000000"; -- TTC-0
constant CR_TH_EGROUP0_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "111111110000000";
-- egroup1: 4 x EPROCx4s. direct data: TTC-1 (4bit) [B-chan ECR BCR L1A]
constant CR_FH_EGROUP1_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"03030303" & "000000001111000"; -- TTC-1
constant CR_TH_EGROUP1_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000001111000";
-- egroup2: 4 x EPROCx4s. direct data: TTC-2 (4bit) [Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP2_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"04040404" & "000000001111000"; -- TTC-2
constant CR_TH_EGROUP2_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000001111000";
-- egroup3: 2 x EPROCx8s. direct data: TTC-3 (8bit) [B-chan Brcst[5] Brcst[4] Brcst[3] Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP3_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"00300030" & "000000000000110"; -- TTC-3
constant CR_TH_EGROUP3_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000000000110";
-- egroup4: 2 x EPROCx8s. direct data: TTC-4 (8bit) [Brcst[6] Brcst[5] Brcst[4] Brcst[3] Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP4_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"00400040" & "000000000000110"; -- TTC-4
constant CR_TH_EGROUP4_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000000000110";
-- egroup7: 8 x EPROCx2s. direct data: TTC-0 (2bit) [B-chan L1A]
constant CR_FH_EGROUP5_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"33333333" & "111111110000000"; -- TTC-0
constant CR_TH_EGROUP7_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000000000110";
--
--
constant CR_TH_EGROUP5_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := (others=>'0');
constant CR_TH_EGROUP6_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := (others=>'0');
--
--
end package centralRouter_package ;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_mmu_inst_pkg.all;
entity cpu_mmu_inst is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_mmu_inst_ctrl_in : in cpu_mmu_inst_ctrl_in_type;
cpu_mmu_inst_dp_in : in cpu_mmu_inst_dp_in_type;
cpu_mmu_inst_ctrl_out : out cpu_mmu_inst_ctrl_out_type;
cpu_mmu_inst_dp_out : out cpu_mmu_inst_dp_out_type
);
end;
|
-- niosii.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii is
port (
clk_clk : in std_logic := '0'; -- clk.clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- pio_0_external_connection.export
reset_reset_n : in std_logic := '0'; -- reset.reset_n
uart_0_rxd : in std_logic := '0'; -- uart_0.rxd
uart_0_txd : out std_logic -- .txd
);
end entity niosii;
architecture rtl of niosii is
component niosii_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c1 : out std_logic; -- clk
c2 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component niosii_altpll_0;
component niosii_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component niosii_jtag_uart_0;
component niosii_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(17 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(17 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component niosii_nios2_gen2_0;
component niosii_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component niosii_onchip_memory2_0;
component niosii_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component niosii_pio_0;
component niosii_timer_ms is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component niosii_timer_ms;
component niosii_timer_us is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component niosii_timer_us;
component niosii_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
begintransfer : in std_logic := 'X'; -- begintransfer
chipselect : in std_logic := 'X'; -- chipselect
read_n : in std_logic := 'X'; -- read_n
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
dataavailable : out std_logic; -- dataavailable
readyfordata : out std_logic; -- readyfordata
rxd : in std_logic := 'X'; -- export
txd : out std_logic; -- export
irq : out std_logic -- irq
);
end component niosii_uart_0;
component niosii_mm_interconnect_0 is
port (
altpll_0_c0_clk : in std_logic := 'X'; -- clk
altpll_0_c1_clk : in std_logic := 'X'; -- clk
altpll_0_c2_clk : in std_logic := 'X'; -- clk
clk_0_clk_clk : in std_logic := 'X'; -- clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
pio_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
timer_us_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_data_master_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address
altpll_0_pll_slave_write : out std_logic; -- write
altpll_0_pll_slave_read : out std_logic; -- read
altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_uart_0_avalon_jtag_slave_address : out std_logic_vector(0 downto 0); -- address
jtag_uart_0_avalon_jtag_slave_write : out std_logic; -- write
jtag_uart_0_avalon_jtag_slave_read : out std_logic; -- read
jtag_uart_0_avalon_jtag_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_uart_0_avalon_jtag_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_uart_0_avalon_jtag_slave_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(13 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic; -- chipselect
timer_ms_s1_address : out std_logic_vector(2 downto 0); -- address
timer_ms_s1_write : out std_logic; -- write
timer_ms_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
timer_ms_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
timer_ms_s1_chipselect : out std_logic; -- chipselect
timer_us_s1_address : out std_logic_vector(2 downto 0); -- address
timer_us_s1_write : out std_logic; -- write
timer_us_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
timer_us_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
timer_us_s1_chipselect : out std_logic; -- chipselect
uart_0_s1_address : out std_logic_vector(2 downto 0); -- address
uart_0_s1_write : out std_logic; -- write
uart_0_s1_read : out std_logic; -- read
uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
uart_0_s1_begintransfer : out std_logic; -- begintransfer
uart_0_s1_chipselect : out std_logic -- chipselect
);
end component niosii_mm_interconnect_0;
component niosii_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
receiver2_irq : in std_logic := 'X'; -- irq
receiver3_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component niosii_irq_mapper;
component altera_irq_clock_crosser is
generic (
IRQ_WIDTH : integer := 1
);
port (
receiver_clk : in std_logic := 'X'; -- clk
sender_clk : in std_logic := 'X'; -- clk
receiver_reset : in std_logic := 'X'; -- reset
sender_reset : in std_logic := 'X'; -- reset
receiver_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
sender_irq : out std_logic_vector(0 downto 0) -- irq
);
end component altera_irq_clock_crosser;
component niosii_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller;
component niosii_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller_001;
signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [irq_mapper:clk, irq_synchronizer:sender_clk, irq_synchronizer_001:sender_clk, irq_synchronizer_002:sender_clk, jtag_uart_0:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_memory2_0:clk, rst_controller_001:clk]
signal altpll_0_c1_clk : std_logic; -- altpll_0:c1 -> [irq_synchronizer:receiver_clk, mm_interconnect_0:altpll_0_c1_clk, pio_0:clk, rst_controller_002:clk, uart_0:clk]
signal altpll_0_c2_clk : std_logic; -- altpll_0:c2 -> [irq_synchronizer_001:receiver_clk, irq_synchronizer_002:receiver_clk, mm_interconnect_0:altpll_0_c2_clk, rst_controller_003:clk, timer_ms:clk, timer_us:clk]
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(17 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(17 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata
signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address
signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read
signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write
signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(13 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address
signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in
signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in
signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
signal mm_interconnect_0_timer_us_s1_chipselect : std_logic; -- mm_interconnect_0:timer_us_s1_chipselect -> timer_us:chipselect
signal mm_interconnect_0_timer_us_s1_readdata : std_logic_vector(15 downto 0); -- timer_us:readdata -> mm_interconnect_0:timer_us_s1_readdata
signal mm_interconnect_0_timer_us_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:timer_us_s1_address -> timer_us:address
signal mm_interconnect_0_timer_us_s1_write : std_logic; -- mm_interconnect_0:timer_us_s1_write -> mm_interconnect_0_timer_us_s1_write:in
signal mm_interconnect_0_timer_us_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:timer_us_s1_writedata -> timer_us:writedata
signal mm_interconnect_0_timer_ms_s1_chipselect : std_logic; -- mm_interconnect_0:timer_ms_s1_chipselect -> timer_ms:chipselect
signal mm_interconnect_0_timer_ms_s1_readdata : std_logic_vector(15 downto 0); -- timer_ms:readdata -> mm_interconnect_0:timer_ms_s1_readdata
signal mm_interconnect_0_timer_ms_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:timer_ms_s1_address -> timer_ms:address
signal mm_interconnect_0_timer_ms_s1_write : std_logic; -- mm_interconnect_0:timer_ms_s1_write -> mm_interconnect_0_timer_ms_s1_write:in
signal mm_interconnect_0_timer_ms_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:timer_ms_s1_writedata -> timer_ms:writedata
signal irq_mapper_receiver0_irq : std_logic; -- jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal irq_mapper_receiver1_irq : std_logic; -- irq_synchronizer:sender_irq -> irq_mapper:receiver1_irq
signal irq_synchronizer_receiver_irq : std_logic_vector(0 downto 0); -- uart_0:irq -> irq_synchronizer:receiver_irq
signal irq_mapper_receiver2_irq : std_logic; -- irq_synchronizer_001:sender_irq -> irq_mapper:receiver2_irq
signal irq_synchronizer_001_receiver_irq : std_logic_vector(0 downto 0); -- timer_us:irq -> irq_synchronizer_001:receiver_irq
signal irq_mapper_receiver3_irq : std_logic; -- irq_synchronizer_002:sender_irq -> irq_mapper:receiver3_irq
signal irq_synchronizer_002_receiver_irq : std_logic_vector(0 downto 0); -- timer_ms:irq -> irq_synchronizer_002:receiver_irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [irq_mapper:reset, irq_synchronizer:sender_reset, irq_synchronizer_001:sender_reset, irq_synchronizer_002:sender_reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_001_reset_out_reset:in, rst_translator:in_reset]
signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal rst_controller_002_reset_out_reset : std_logic; -- rst_controller_002:reset_out -> [irq_synchronizer:receiver_reset, mm_interconnect_0:pio_0_reset_reset_bridge_in_reset_reset, rst_controller_002_reset_out_reset:in]
signal rst_controller_003_reset_out_reset : std_logic; -- rst_controller_003:reset_out -> [irq_synchronizer_001:receiver_reset, irq_synchronizer_002:receiver_reset, mm_interconnect_0:timer_us_reset_reset_bridge_in_reset_reset, rst_controller_003_reset_out_reset:in]
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0, rst_controller_003:reset_in0]
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:inv -> jtag_uart_0:av_read_n
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:inv -> jtag_uart_0:av_write_n
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n
signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n
signal mm_interconnect_0_timer_us_s1_write_ports_inv : std_logic; -- mm_interconnect_0_timer_us_s1_write:inv -> timer_us:write_n
signal mm_interconnect_0_timer_ms_s1_write_ports_inv : std_logic; -- mm_interconnect_0_timer_ms_s1_write:inv -> timer_ms:write_n
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [jtag_uart_0:rst_n, nios2_gen2_0:reset_n]
signal rst_controller_002_reset_out_reset_ports_inv : std_logic; -- rst_controller_002_reset_out_reset:inv -> [pio_0:reset_n, uart_0:reset_n]
signal rst_controller_003_reset_out_reset_ports_inv : std_logic; -- rst_controller_003_reset_out_reset:inv -> [timer_ms:reset_n, timer_us:reset_n]
begin
altpll_0 : component niosii_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset
read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read
write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address
readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
c1 => altpll_0_c1_clk, -- c1.clk
c2 => altpll_0_c2_clk, -- c2.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
jtag_uart_0 : component niosii_jtag_uart_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
rst_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- avalon_jtag_slave.chipselect
av_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address(0), -- .address
av_read_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv, -- .read_n
av_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
av_write_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv, -- .write_n
av_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
av_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
av_irq => irq_mapper_receiver0_irq -- irq.irq
);
nios2_gen2_0 : component niosii_nios2_gen2_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => open, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component niosii_onchip_memory2_0
port map (
clk => altpll_0_c0_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_001_reset_out_reset, -- reset1.reset
reset_req => rst_controller_001_reset_out_reset_req -- .reset_req
);
pio_0 : component niosii_pio_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
out_port => pio_0_external_connection_export -- external_connection.export
);
timer_ms : component niosii_timer_ms
port map (
clk => altpll_0_c2_clk, -- clk.clk
reset_n => rst_controller_003_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_timer_ms_s1_address, -- s1.address
writedata => mm_interconnect_0_timer_ms_s1_writedata, -- .writedata
readdata => mm_interconnect_0_timer_ms_s1_readdata, -- .readdata
chipselect => mm_interconnect_0_timer_ms_s1_chipselect, -- .chipselect
write_n => mm_interconnect_0_timer_ms_s1_write_ports_inv, -- .write_n
irq => irq_synchronizer_002_receiver_irq(0) -- irq.irq
);
timer_us : component niosii_timer_us
port map (
clk => altpll_0_c2_clk, -- clk.clk
reset_n => rst_controller_003_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_timer_us_s1_address, -- s1.address
writedata => mm_interconnect_0_timer_us_s1_writedata, -- .writedata
readdata => mm_interconnect_0_timer_us_s1_readdata, -- .readdata
chipselect => mm_interconnect_0_timer_us_s1_chipselect, -- .chipselect
write_n => mm_interconnect_0_timer_us_s1_write_ports_inv, -- .write_n
irq => irq_synchronizer_001_receiver_irq(0) -- irq.irq
);
uart_0 : component niosii_uart_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_uart_0_s1_address, -- s1.address
begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect
read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n
write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
dataavailable => open, -- .dataavailable
readyfordata => open, -- .readyfordata
rxd => uart_0_rxd, -- external_connection.export
txd => uart_0_txd, -- .export
irq => irq_synchronizer_receiver_irq(0) -- irq.irq
);
mm_interconnect_0 : component niosii_mm_interconnect_0
port map (
altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk
altpll_0_c1_clk => altpll_0_c1_clk, -- altpll_0_c1.clk
altpll_0_c2_clk => altpll_0_c2_clk, -- altpll_0_c2.clk
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
pio_0_reset_reset_bridge_in_reset_reset => rst_controller_002_reset_out_reset, -- pio_0_reset_reset_bridge_in_reset.reset
timer_us_reset_reset_bridge_in_reset_reset => rst_controller_003_reset_out_reset, -- timer_us_reset_reset_bridge_in_reset.reset
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address
altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read
altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
jtag_uart_0_avalon_jtag_slave_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address, -- jtag_uart_0_avalon_jtag_slave.address
jtag_uart_0_avalon_jtag_slave_write => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write, -- .write
jtag_uart_0_avalon_jtag_slave_read => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read, -- .read
jtag_uart_0_avalon_jtag_slave_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
jtag_uart_0_avalon_jtag_slave_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
jtag_uart_0_avalon_jtag_slave_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
timer_ms_s1_address => mm_interconnect_0_timer_ms_s1_address, -- timer_ms_s1.address
timer_ms_s1_write => mm_interconnect_0_timer_ms_s1_write, -- .write
timer_ms_s1_readdata => mm_interconnect_0_timer_ms_s1_readdata, -- .readdata
timer_ms_s1_writedata => mm_interconnect_0_timer_ms_s1_writedata, -- .writedata
timer_ms_s1_chipselect => mm_interconnect_0_timer_ms_s1_chipselect, -- .chipselect
timer_us_s1_address => mm_interconnect_0_timer_us_s1_address, -- timer_us_s1.address
timer_us_s1_write => mm_interconnect_0_timer_us_s1_write, -- .write
timer_us_s1_readdata => mm_interconnect_0_timer_us_s1_readdata, -- .readdata
timer_us_s1_writedata => mm_interconnect_0_timer_us_s1_writedata, -- .writedata
timer_us_s1_chipselect => mm_interconnect_0_timer_us_s1_chipselect, -- .chipselect
uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address
uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write
uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read
uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect
);
irq_mapper : component niosii_irq_mapper
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq
receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
irq_synchronizer : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c1_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_002_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_001_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver1_irq -- sender.irq
);
irq_synchronizer_001 : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c2_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_003_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_001_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_001_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver2_irq -- sender.irq
);
irq_synchronizer_002 : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c2_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_003_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_001_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_002_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver3_irq -- sender.irq
);
rst_controller : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component niosii_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_002 : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c1_clk, -- clk.clk
reset_out => rst_controller_002_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_003 : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c2_clk, -- clk.clk
reset_out => rst_controller_003_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read;
mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write;
mm_interconnect_0_timer_us_s1_write_ports_inv <= not mm_interconnect_0_timer_us_s1_write;
mm_interconnect_0_timer_ms_s1_write_ports_inv <= not mm_interconnect_0_timer_ms_s1_write;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
rst_controller_002_reset_out_reset_ports_inv <= not rst_controller_002_reset_out_reset;
rst_controller_003_reset_out_reset_ports_inv <= not rst_controller_003_reset_out_reset;
end architecture rtl; -- of niosii
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/pikachu_pixel_1/pikachu_pixel_stub.vhdl
-- Design : pikachu_pixel
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pikachu_pixel is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end pikachu_pixel;
architecture stub of pikachu_pixel is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[12:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/pikachu_pixel_1/pikachu_pixel_stub.vhdl
-- Design : pikachu_pixel
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pikachu_pixel is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end pikachu_pixel;
architecture stub of pikachu_pixel is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[12:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 24 22:16:07 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/andrewandre/Documents/GitHub/axiplasma/hdl/projects/Nexys4/rtl_project/rtl_project.srcs/sources_1/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_0_0/mig_wrap_proc_sys_reset_0_0_stub.vhdl
-- Design : mig_wrap_proc_sys_reset_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mig_wrap_proc_sys_reset_0_0 is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end mig_wrap_proc_sys_reset_0_0;
architecture stub of mig_wrap_proc_sys_reset_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2016.4";
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1141.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p05n02i01141ent IS
END c06s05b00x00p05n02i01141ent;
ARCHITECTURE c06s05b00x00p05n02i01141arch OF c06s05b00x00p05n02i01141ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (M1, M2, M3, M4, M5, M6);
type A is array ( ENUM1 range <> ) of BOOLEAN;
subtype A1 is A(M1 to M6) ;
subtype A2 is A(M6 downto M1) ;
variable V1: A1 ;
variable V2: A2 ;
BEGIN
V1(M2 to M4) := V1(M4 downto M2);
--ERROR: discrete range descending when the prefix
--type was declared with a ascending range results in a null
--slice, which is incompatible with non-null slice
assert FALSE
report "***FAILED TEST: c06s05b00x00p05n02i01141 - Null slice is not compatible with non-null slice."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p05n02i01141arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1141.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p05n02i01141ent IS
END c06s05b00x00p05n02i01141ent;
ARCHITECTURE c06s05b00x00p05n02i01141arch OF c06s05b00x00p05n02i01141ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (M1, M2, M3, M4, M5, M6);
type A is array ( ENUM1 range <> ) of BOOLEAN;
subtype A1 is A(M1 to M6) ;
subtype A2 is A(M6 downto M1) ;
variable V1: A1 ;
variable V2: A2 ;
BEGIN
V1(M2 to M4) := V1(M4 downto M2);
--ERROR: discrete range descending when the prefix
--type was declared with a ascending range results in a null
--slice, which is incompatible with non-null slice
assert FALSE
report "***FAILED TEST: c06s05b00x00p05n02i01141 - Null slice is not compatible with non-null slice."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p05n02i01141arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1141.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p05n02i01141ent IS
END c06s05b00x00p05n02i01141ent;
ARCHITECTURE c06s05b00x00p05n02i01141arch OF c06s05b00x00p05n02i01141ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (M1, M2, M3, M4, M5, M6);
type A is array ( ENUM1 range <> ) of BOOLEAN;
subtype A1 is A(M1 to M6) ;
subtype A2 is A(M6 downto M1) ;
variable V1: A1 ;
variable V2: A2 ;
BEGIN
V1(M2 to M4) := V1(M4 downto M2);
--ERROR: discrete range descending when the prefix
--type was declared with a ascending range results in a null
--slice, which is incompatible with non-null slice
assert FALSE
report "***FAILED TEST: c06s05b00x00p05n02i01141 - Null slice is not compatible with non-null slice."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p05n02i01141arch;
|
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Copyright 2011-2013(c) Analog Devices, Inc.
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- [email protected] (c) Analog Devices Inc.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tx_package.all;
use work.axi_ctrlif;
use work.axi_streaming_dma_tx_fifo;
use work.pl330_dma_fifo;
entity axi_spdif_tx is
generic (
S_AXI_DATA_WIDTH : integer := 32;
S_AXI_ADDRESS_WIDTH : integer := 32;
DEVICE_FAMILY : string := "virtex6";
DMA_TYPE : integer := 0
);
port (
--SPDIF ports
spdif_data_clk : in std_logic;
spdif_tx_o : out std_logic;
--AXI Lite interface
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
--AXI streaming interface
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
--PL330 DMA interface
DMA_REQ_ACLK : in std_logic;
DMA_REQ_RSTN : in std_logic;
DMA_REQ_DAVALID : in std_logic;
DMA_REQ_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_DAREADY : out std_logic;
DMA_REQ_DRVALID : out std_logic;
DMA_REQ_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_DRLAST : out std_logic;
DMA_REQ_DRREADY : in std_logic
);
end entity axi_spdif_tx;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_spdif_tx is
------------------------------------------
-- SPDIF signals
------------------------------------------
signal config_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
signal chstatus_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
signal chstat_freq : std_logic_vector(1 downto 0);
signal chstat_gstat, chstat_preem, chstat_copy, chstat_audio : std_logic;
signal sample_data_ack : std_logic;
signal sample_data: std_logic_vector(15 downto 0);
signal conf_mode : std_logic_vector(3 downto 0);
signal conf_ratio : std_logic_vector(7 downto 0);
signal conf_tinten, conf_txdata, conf_txen : std_logic;
signal channel : std_logic;
signal enable : boolean;
signal fifo_data_out : std_logic_vector(31 downto 0);
signal fifo_data_ack : std_logic;
signal fifo_reset : std_logic;
signal tx_fifo_stb : std_logic;
-- Register access
signal wr_data : std_logic_vector(31 downto 0);
signal rd_data : std_logic_vector(31 downto 0);
signal wr_addr : integer range 0 to 3;
signal rd_addr : integer range 0 to 3;
signal wr_stb : std_logic;
signal rd_ack : std_logic;
begin
fifo_reset <= not conf_txdata;
enable <= conf_txdata = '1';
fifo_data_ack <= channel and sample_data_ack;
streaming_dma_gen: if DMA_TYPE = 0 generate
fifo: entity axi_streaming_dma_tx_fifo
generic map (
RAM_ADDR_WIDTH => 3,
FIFO_DWIDTH => 32
)
port map (
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => fifo_reset,
enable => enable,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TVALID => S_AXIS_TLAST,
S_AXIS_TLAST => S_AXIS_TVALID,
out_ack => fifo_data_ack,
out_data => fifo_data_out
);
end generate;
no_streaming_dma_gen: if DMA_TYPE /= 0 generate
S_AXIS_TREADY <= '0';
end generate;
pl330_dma_gen: if DMA_TYPE = 1 generate
tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0';
fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => 3,
FIFO_DWIDTH => 32,
FIFO_DIRECTION => 0
)
port map (
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => fifo_reset,
enable => enable,
in_data => wr_data,
in_stb => tx_fifo_stb,
out_ack => fifo_data_ack,
out_data => fifo_data_out,
dclk => DMA_REQ_ACLK,
dresetn => DMA_REQ_RSTN,
davalid => DMA_REQ_DAVALID,
daready => DMA_REQ_DAREADY,
datype => DMA_REQ_DATYPE,
drvalid => DMA_REQ_DRVALID,
drready => DMA_REQ_DRREADY,
drtype => DMA_REQ_DRTYPE,
drlast => DMA_REQ_DRLAST
);
end generate;
no_pl330_dma_gen: if DMA_TYPE /= 1 generate
DMA_REQ_DAREADY <= '0';
DMA_REQ_DRVALID <= '0';
DMA_REQ_DRTYPE <= (others => '0');
DMA_REQ_DRLAST <= '0';
end generate;
sample_data_mux: process (fifo_data_out, channel) is
begin
if channel = '0' then
sample_data <= fifo_data_out(15 downto 0);
else
sample_data <= fifo_data_out(31 downto 16);
end if;
end process;
-- Configuration signals update
conf_mode(3 downto 0) <= config_reg(23 downto 20);
conf_ratio(7 downto 0) <= config_reg(15 downto 8);
conf_tinten <= config_reg(2);
conf_txdata <= config_reg(1);
conf_txen <= config_reg(0);
-- Channel status signals update
chstat_freq(1 downto 0) <= chstatus_reg(7 downto 6);
chstat_gstat <= chstatus_reg(3);
chstat_preem <= chstatus_reg(2);
chstat_copy <= chstatus_reg(1);
chstat_audio <= chstatus_reg(0);
-- Transmit encoder
TENC: tx_encoder
generic map (
DATA_WIDTH => 16
)
port map (
up_clk => S_AXI_ACLK,
data_clk => spdif_data_clk, -- data clock
resetn => S_AXI_ARESETN, -- resetn
conf_mode => conf_mode, -- sample format
conf_ratio => conf_ratio, -- clock divider
conf_txdata => conf_txdata, -- sample data enable
conf_txen => conf_txen, -- spdif signal enable
chstat_freq => chstat_freq, -- sample freq.
chstat_gstat => chstat_gstat, -- generation status
chstat_preem => chstat_preem, -- preemphasis status
chstat_copy => chstat_copy, -- copyright bit
chstat_audio => chstat_audio, -- data format
sample_data => sample_data, -- audio data
sample_data_ack => sample_data_ack, -- sample buffer read
channel => channel, -- which channel should be read
spdif_tx_o => spdif_tx_o -- SPDIF output signal
);
ctrlif: entity axi_ctrlif
generic map (
C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH,
C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH,
C_NUM_REG => 4
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
rd_addr => rd_addr,
rd_data => rd_data,
rd_ack => rd_ack,
rd_stb => '1',
wr_addr => wr_addr,
wr_data => wr_data,
wr_ack => '1',
wr_stb => wr_stb
);
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
config_reg <= (others => '0');
chstatus_reg <= (others => '0');
else
if wr_stb = '1' then
case wr_addr is
when 0 => config_reg <= wr_data;
when 1 => chstatus_reg <= wr_data;
when others => null;
end case;
end if;
end if;
end if;
end process;
process (rd_addr, config_reg, chstatus_reg)
begin
case rd_addr is
when 0 => rd_data <= config_reg;
when 1 => rd_data <= chstatus_reg;
when others => rd_data <= (others => '0');
end case;
end process;
end IMP;
|
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_address_swap.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This address swap block will accept the first 12 byte of a packet before
-- starting to loop it out. At this point both the source and destination fields have
-- been completely captured and can therefore be swapped.
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tri_mode_ethernet_mac_0_address_swap is
port (
axi_tclk : in std_logic;
axi_tresetn : in std_logic;
-- address swap enable control
enable_address_swap : in std_logic;
-- data from the RX FIFO
rx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : in std_logic;
rx_axis_fifo_tlast : in std_logic;
rx_axis_fifo_tready : out std_logic;
-- data TO the tx fifo
tx_axis_fifo_tdata : out std_logic_vector(7 downto 0) := (others => '0');
tx_axis_fifo_tvalid : out std_logic;
tx_axis_fifo_tlast : out std_logic;
tx_axis_fifo_tready : in std_logic
);
end tri_mode_ethernet_mac_0_address_swap;
architecture rtl of tri_mode_ethernet_mac_0_address_swap is
-- State machine
type rd_state_typ is (IDLE,
WAIT_S,
READ_DEST,
READ_SRC,
READ_DEST2,
READ_SRC2,
READ);
type wr_state_typ is (IDLE_W,
WRITE_SLOT1,
WRITE_SLOT2,
WRITE);
signal next_rd_state : rd_state_typ;
signal rd_state : rd_state_typ;
signal next_wr_state : wr_state_typ;
signal wr_state : wr_state_typ;
signal rx_axis_fifo_tvalid_reg : std_logic;
signal rx_axis_fifo_tlast_reg : std_logic;
signal wr_count : unsigned(3 downto 0) := (others => '0');
signal fifo_full : std_logic;
signal wr_slot : unsigned(2 downto 0) := (others => '0');
signal wr_addr : unsigned(2 downto 0) := (others => '0');
signal dia : std_logic_vector(8 downto 0);
signal doa : std_logic_vector(8 downto 0);
signal wea : std_logic;
signal rd_count : unsigned(3 downto 0) := (others => '0');
signal fifo_empty : std_logic;
signal rd_slot : unsigned(2 downto 0) := (others => '0');
signal rd_addr : unsigned(2 downto 0) := (others => '0');
signal dob : std_logic_vector(8 downto 0);
signal tx_axis_fifo_tvalid_int : std_logic;
signal tx_axis_fifo_tlast_int : std_logic;
signal rx_axis_fifo_tready_int : std_logic;
signal axi_treset : std_logic;
signal new_packet_start : std_logic;
signal rd_count_6 : std_logic;
signal rd_count_12 : std_logic;
signal slot_diff : unsigned(2 downto 0) := (others => '0');
signal packet_waiting : std_logic;
begin
rx_axis_fifo_tready <= rx_axis_fifo_tready_int;
axi_treset <= not axi_tresetn;
-- capture a new packet starting as we only want to start taking it once the read side is idle
new_pkt_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
new_packet_start <= '0';
elsif wr_state = IDLE_W and packet_waiting = '0' and rx_axis_fifo_tvalid = '1' and
(rx_axis_fifo_tvalid_reg = '0' or rx_axis_fifo_tlast_reg = '1') then
new_packet_start <= '1';
elsif wr_state /= IDLE_W then
new_packet_start <= '0';
end if;
end if;
end process new_pkt_p;
-- need to monitor the RX FIFO AXI interface and when a new transaction starts capture the first
-- 6 bytes of the frame. Use a LUT6 to capture the data - allows some backoff to take place
-- need to maintain a read an write interface..
-- Write interface
reg_axi_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
rx_axis_fifo_tvalid_reg <= rx_axis_fifo_tvalid;
rx_axis_fifo_tlast_reg <= rx_axis_fifo_tlast;
end if;
end process reg_axi_p;
-- simple write state machine
next_wr_s : process(wr_state, rx_axis_fifo_tvalid, wr_count, rx_axis_fifo_tlast,
new_packet_start, rd_state)
begin
next_wr_state <= wr_state;
case wr_state is
-- detect a rising edge on TVALID OR TLAST on previous cycle AND TVALID
when IDLE_W =>
if rd_state = IDLE and new_packet_start = '1' then
next_wr_state <= WRITE_SLOT1;
end if;
-- finish writing when tlast is high
when WRITE_SLOT1 =>
if wr_count = X"6" and rx_axis_fifo_tvalid = '1' then
next_wr_state <= WRITE_SLOT2;
elsif rx_axis_fifo_tlast = '1' and rx_axis_fifo_tvalid = '1' then
next_wr_state <= IDLE_W;
end if;
when WRITE_SLOT2 =>
if wr_count = X"c" and rx_axis_fifo_tvalid = '1' then
next_wr_state <= WRITE;
elsif rx_axis_fifo_tlast = '1' and rx_axis_fifo_tvalid = '1' then
next_wr_state <= IDLE_W;
end if;
when WRITE =>
if rx_axis_fifo_tlast = '1' and rx_axis_fifo_tvalid = '1' then
next_wr_state <= IDLE_W;
end if;
end case;
end process;
wr_state_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
wr_state <= IDLE_W;
elsif fifo_full = '0' then
wr_state <= next_wr_state;
end if;
end if;
end process wr_state_p;
packet_wait_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
packet_waiting <= '0';
elsif wr_state = IDLE_W and next_wr_state = WRITE_SLOT1 then
packet_waiting <= '1';
elsif rd_state /= IDLE then
packet_waiting <= '0';
end if;
end if;
end process packet_wait_p;
-- generate a write count to control where the data is written
wr_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
wr_count <= (others => '0');
else
if wr_state = IDLE_W and next_wr_state = WRITE_SLOT1 then
wr_count <= X"1";
elsif wr_state /= IDLE_W and rx_axis_fifo_tvalid = '1' and fifo_full = '0' and wr_count /= x"f" then
wr_count <= wr_count + X"1";
end if;
end if;
end if;
end process wr_count_p;
-- we have a 64 deep lut - to simplify storing/fetching of data this is split into 8 address slots. When
-- a new packet starts the first byte of the address is stored in the next available address slot, with the next address being
-- stored in the next slot (i.e after a gap of two locations). Once the addresses have been stored the data starts
-- at the next slot and then continues until completion.
wr_slot_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
wr_slot <= (others => '0');
wr_addr <= (others => '0');
elsif wr_state = IDLE_W and next_wr_state = WRITE_SLOT1 then
wr_slot <= "000";
wr_addr <= (others => '0');
elsif wr_state = WRITE_SLOT1 and next_wr_state = WRITE_SLOT2 then
wr_slot <= "001";
wr_addr <= (others => '0');
elsif wr_state = WRITE_SLOT2 and next_wr_state = WRITE then
wr_slot <= "010";
wr_addr <= (others => '0');
elsif rx_axis_fifo_tready_int = '1' and rx_axis_fifo_tvalid = '1' and fifo_full = '0' then
wr_addr <= wr_addr + "001";
if wr_addr = "111" then
wr_slot <= wr_slot + "001";
end if;
end if;
end if;
end process wr_slot_p;
slot_diff <= rd_slot - wr_slot;
-- need to generate full logic to generate the ready - simplified by there only being
-- one clock domain..
-- to allow for reaction time generate as full when we are only one slot away
fifo_full_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if (slot_diff = "010" or slot_diff = "001") and wr_state = WRITE then
fifo_full <= '1';
else
fifo_full <= '0';
end if;
end if;
end process fifo_full_p;
rx_axis_fifo_tready_int <= '1' when fifo_full = '0' and wr_state /= IDLE_W else '0';
dia <= rx_axis_fifo_tlast & rx_axis_fifo_tdata;
wea <= '1' when rx_axis_fifo_tready_int = '1' else '0';
LUT6_gen : for I in 0 to 8 generate
begin
RAM64X1D_inst : RAM64X1D
port map (
DPO => dob(I),
SPO => doa(I),
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_slot(0),
A4 => wr_slot(1),
A5 => wr_slot(2),
D => dia(I),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_slot(0),
DPRA4 => rd_slot(1),
DPRA5 => rd_slot(2),
WCLK => axi_tclk,
WE => wea
);
end generate;
-- read logic - this is kicked into action when the wr_state moves from IDLE but will not start to read until
-- the wr_state moves to WRITE as the two addresses are then in situ
-- can then choose if we wish to addess swap or not - if a small packet is rxd which is less than the required 12 bytes
-- the read logic will revert to non address swap and just output what is there..
next_rd_s : process(rd_state, enable_address_swap, rd_count_6, rd_count_12, tx_axis_fifo_tready, dob,
wr_state, tx_axis_fifo_tvalid_int)
begin
next_rd_state <= rd_state;
case rd_state is
when IDLE =>
if wr_state /= IDLE_W then
next_rd_state <= WAIT_S;
end if;
when WAIT_S =>
if wr_state = IDLE_W then
next_rd_state <= READ_DEST2;
elsif wr_state = WRITE then
if enable_address_swap = '1' then
next_rd_state <= READ_SRC;
else
next_rd_state <= READ_DEST2;
end if;
end if;
when READ_SRC =>
if rd_count_6 = '1' and tx_axis_fifo_tready = '1' and tx_axis_fifo_tvalid_int = '1' then
next_rd_state <= READ_DEST;
end if;
when READ_DEST =>
if rd_count_12 = '1' and tx_axis_fifo_tready = '1' and tx_axis_fifo_tvalid_int = '1' then
next_rd_state <= READ;
end if;
when READ_DEST2 =>
if rd_count_6 = '1' and tx_axis_fifo_tready = '1' and tx_axis_fifo_tvalid_int = '1' then
next_rd_state <= READ_SRC2;
end if;
when READ_SRC2 =>
if rd_count_12 = '1' and tx_axis_fifo_tready = '1' and tx_axis_fifo_tvalid_int = '1' then
next_rd_state <= READ;
end if;
when READ =>
if dob(8) = '1' and tx_axis_fifo_tready = '1' and tx_axis_fifo_tvalid_int = '1' then
next_rd_state <= IDLE;
end if;
when others =>
next_rd_state <= IDLE;
end case;
end process;
rd_state_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
rd_state <= IDLE;
else
rd_state <= next_rd_state;
end if;
end if;
end process rd_state_p;
-- generate a read count to control where the data is read
rd_count_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
rd_count <= (others => '0');
rd_count_6 <= '0';
rd_count_12 <= '0';
else
if rd_state = WAIT_S then
rd_count <= X"1";
elsif rd_state /= IDLE and tx_axis_fifo_tvalid_int = '1' and
tx_axis_fifo_tready = '1' and rd_count /= X"f" then
rd_count <= rd_count + X"1";
if rd_count = X"5" then
rd_count_6 <= '1';
else
rd_count_6 <= '0';
end if;
if rd_count = X"b" then
rd_count_12 <= '1';
else
rd_count_12 <= '0';
end if;
end if;
end if;
end if;
end process rd_count_p;
-- we have a 64 deep lut - to simplify storing/fetching of data this is split into 8 address slots. When
-- a new packet starts the first byte of the address is stored in the next available address slot, with the next address being
-- stored in the next slot (i.e after a gap of two locations). Once the addresses have been stored the data starts
-- at the next slot and then continues until completion.
rd_slot_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if axi_treset = '1' then
rd_slot <= (others => '0');
rd_addr <= (others => '0');
elsif rd_state = WAIT_S and next_rd_state = READ_DEST2 then
rd_slot <= "000";
rd_addr <= (others => '0');
elsif rd_state = WAIT_S and next_rd_state = READ_SRC then
rd_slot <= "001";
rd_addr <= (others => '0');
elsif rd_state = READ_DEST2 and next_rd_state = READ_SRC2 then
rd_slot <= "001";
rd_addr <= (others => '0');
elsif rd_state = READ_SRC and next_rd_state = READ_DEST then
rd_slot <= "000";
rd_addr <= (others => '0');
elsif rd_state = READ_DEST and next_rd_state = READ then
rd_slot <= "010";
rd_addr <= (others => '0');
elsif rd_state = READ_SRC2 and next_rd_state = READ then
rd_slot <= "010";
rd_addr <= (others => '0');
elsif tx_axis_fifo_tvalid_int = '1' and tx_axis_fifo_tready = '1' then
rd_addr <= rd_addr + "001";
if rd_addr = "111" then
rd_slot <= rd_slot + "001";
end if;
end if;
end if;
end process rd_slot_p;
-- need to generate empty to generate the tvalid for the tx_fifo interface - the empty is purely a compare of the
-- rd/wr access point - if the same and TLAST (dob[8]) is low then must still be in packet so drop tvalid - and stall read
empty_p : process (wr_slot, wr_addr, rd_slot, rd_addr)
begin
if wr_slot = rd_slot and wr_addr = rd_addr then
fifo_empty <= '1';
else
fifo_empty <= '0';
end if;
end process;
-- generate the tvalid
valid_p : process (rd_state, fifo_empty, tx_axis_fifo_tready, dob)
begin
if rd_state = IDLE then
tx_axis_fifo_tvalid_int <= '0';
elsif rd_state /= WAIT_S then
if fifo_empty = '1' and tx_axis_fifo_tready = '1' and dob(8) = '0' then
tx_axis_fifo_tvalid_int <= '0';
else
tx_axis_fifo_tvalid_int <= '1';
end if;
else
tx_axis_fifo_tvalid_int <= '0';
end if;
end process;
-- and the output data/tlast
rd_data_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if tx_axis_fifo_tready = '1' then
if fifo_empty = '0' then
tx_axis_fifo_tdata <= dob(7 downto 0);
end if;
tx_axis_fifo_tvalid <= tx_axis_fifo_tvalid_int;
tx_axis_fifo_tlast_int <= dob(8);
end if;
end if;
end process rd_data_p;
tx_axis_fifo_tlast <= tx_axis_fifo_tlast_int;
end rtl;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_02a is
end entity inline_02a;
----------------------------------------------------------------
architecture test of inline_02a is
begin
process is
-- code from book:
type stimulus_record is record
stimulus_time : time;
stimulus_value : real_vector(0 to 3);
end record stimulus_record;
type stimulus_ptr is access stimulus_record;
variable bus_stimulus : stimulus_ptr;
-- end of code from book
begin
-- code from book:
bus_stimulus := new stimulus_record'( 20 ns, real_vector'(0.0, 5.0, 0.0, 42.0) );
-- end of code from book
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_02a is
end entity inline_02a;
----------------------------------------------------------------
architecture test of inline_02a is
begin
process is
-- code from book:
type stimulus_record is record
stimulus_time : time;
stimulus_value : real_vector(0 to 3);
end record stimulus_record;
type stimulus_ptr is access stimulus_record;
variable bus_stimulus : stimulus_ptr;
-- end of code from book
begin
-- code from book:
bus_stimulus := new stimulus_record'( 20 ns, real_vector'(0.0, 5.0, 0.0, 42.0) );
-- end of code from book
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_02a is
end entity inline_02a;
----------------------------------------------------------------
architecture test of inline_02a is
begin
process is
-- code from book:
type stimulus_record is record
stimulus_time : time;
stimulus_value : real_vector(0 to 3);
end record stimulus_record;
type stimulus_ptr is access stimulus_record;
variable bus_stimulus : stimulus_ptr;
-- end of code from book
begin
-- code from book:
bus_stimulus := new stimulus_record'( 20 ns, real_vector'(0.0, 5.0, 0.0, 42.0) );
-- end of code from book
wait;
end process;
end architecture test;
|
library verilog;
use verilog.vl_types.all;
entity ID_EX_Seg is
port(
Clk : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
PC_Add : in vl_logic_vector(31 downto 0);
OverflowEn : in vl_logic;
condition : in vl_logic_vector(2 downto 0);
Branch : in vl_logic;
PC_write : in vl_logic_vector(2 downto 0);
Mem_Byte_Write : in vl_logic_vector(3 downto 0);
Rd_Write_Byte_en: in vl_logic_vector(3 downto 0);
MemWBSrc : in vl_logic;
Jump : in vl_logic;
ALUShiftSrc : in vl_logic;
MemDataSrc : in vl_logic_vector(2 downto 0);
ALUSrcA : in vl_logic;
ALUSrcB : in vl_logic;
ALUOp : in vl_logic_vector(3 downto 0);
RegDst : in vl_logic_vector(1 downto 0);
ShiftAmountSrc : in vl_logic;
ShiftOp : in vl_logic_vector(1 downto 0);
OperandA : in vl_logic_vector(31 downto 0);
OperandB : in vl_logic_vector(31 downto 0);
Rs : in vl_logic_vector(4 downto 0);
Rt : in vl_logic_vector(4 downto 0);
Rd : in vl_logic_vector(4 downto 0);
Immediate32 : in vl_logic_vector(31 downto 0);
Shamt : in vl_logic_vector(4 downto 0);
BranchSel : in vl_logic;
RtRead : in vl_logic_vector(1 downto 0);
PC_Add_out : out vl_logic_vector(31 downto 0);
OverflowEn_out : out vl_logic;
condition_out : out vl_logic_vector(2 downto 0);
Branch_out : out vl_logic;
PC_write_out : out vl_logic_vector(2 downto 0);
Mem_Byte_Write_out: out vl_logic_vector(3 downto 0);
Rd_Write_Byte_en_out: out vl_logic_vector(3 downto 0);
MemWBSrc_out : out vl_logic;
Jump_out : out vl_logic;
ALUShiftSrc_out : out vl_logic;
MemDataSrc_out : out vl_logic_vector(2 downto 0);
ALUSrcA_out : out vl_logic;
ALUSrcB_out : out vl_logic;
ALUOp_out : out vl_logic_vector(3 downto 0);
RegDst_out : out vl_logic_vector(1 downto 0);
ShiftAmountSrc_out: out vl_logic;
ShiftOp_out : out vl_logic_vector(1 downto 0);
OperandA_out : out vl_logic_vector(31 downto 0);
OperandB_out : out vl_logic_vector(31 downto 0);
Rs_out : out vl_logic_vector(4 downto 0);
Rt_out : out vl_logic_vector(4 downto 0);
Rd_out : out vl_logic_vector(4 downto 0);
Immediate32_out : out vl_logic_vector(31 downto 0);
Shamt_out : out vl_logic_vector(4 downto 0);
BranchSel_out : out vl_logic;
RtRead_out : out vl_logic_vector(1 downto 0)
);
end ID_EX_Seg;
|
package A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean);
procedure PROC_B(I:in integer; O:out integer; Z:out boolean);
procedure PROC_C(I:in integer; O:out integer; Z:out boolean);
end package;
package body A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean) is
begin
-- Used to abort calling forward-declared procedure
PROC_B(I,O,Z);
end procedure;
procedure PROC_B(I:in integer; O:out integer; Z:out boolean) is
begin
PROC_C(I,O,Z);
end procedure;
procedure PROC_C(I:in integer; O:out integer; Z:out boolean) is
begin
O := I;
Z := (I = 0);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue121 is
end entity;
use work.A.all;
architecture test of issue121 is
begin
process is
variable o : integer;
variable z : boolean;
begin
proc_a(1, o, z);
assert o = 1;
assert not z;
proc_a(0, o, z);
assert o = 0;
assert z;
wait;
end process;
end architecture;
|
package A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean);
procedure PROC_B(I:in integer; O:out integer; Z:out boolean);
procedure PROC_C(I:in integer; O:out integer; Z:out boolean);
end package;
package body A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean) is
begin
-- Used to abort calling forward-declared procedure
PROC_B(I,O,Z);
end procedure;
procedure PROC_B(I:in integer; O:out integer; Z:out boolean) is
begin
PROC_C(I,O,Z);
end procedure;
procedure PROC_C(I:in integer; O:out integer; Z:out boolean) is
begin
O := I;
Z := (I = 0);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue121 is
end entity;
use work.A.all;
architecture test of issue121 is
begin
process is
variable o : integer;
variable z : boolean;
begin
proc_a(1, o, z);
assert o = 1;
assert not z;
proc_a(0, o, z);
assert o = 0;
assert z;
wait;
end process;
end architecture;
|
package A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean);
procedure PROC_B(I:in integer; O:out integer; Z:out boolean);
procedure PROC_C(I:in integer; O:out integer; Z:out boolean);
end package;
package body A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean) is
begin
-- Used to abort calling forward-declared procedure
PROC_B(I,O,Z);
end procedure;
procedure PROC_B(I:in integer; O:out integer; Z:out boolean) is
begin
PROC_C(I,O,Z);
end procedure;
procedure PROC_C(I:in integer; O:out integer; Z:out boolean) is
begin
O := I;
Z := (I = 0);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue121 is
end entity;
use work.A.all;
architecture test of issue121 is
begin
process is
variable o : integer;
variable z : boolean;
begin
proc_a(1, o, z);
assert o = 1;
assert not z;
proc_a(0, o, z);
assert o = 0;
assert z;
wait;
end process;
end architecture;
|
package A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean);
procedure PROC_B(I:in integer; O:out integer; Z:out boolean);
procedure PROC_C(I:in integer; O:out integer; Z:out boolean);
end package;
package body A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean) is
begin
-- Used to abort calling forward-declared procedure
PROC_B(I,O,Z);
end procedure;
procedure PROC_B(I:in integer; O:out integer; Z:out boolean) is
begin
PROC_C(I,O,Z);
end procedure;
procedure PROC_C(I:in integer; O:out integer; Z:out boolean) is
begin
O := I;
Z := (I = 0);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue121 is
end entity;
use work.A.all;
architecture test of issue121 is
begin
process is
variable o : integer;
variable z : boolean;
begin
proc_a(1, o, z);
assert o = 1;
assert not z;
proc_a(0, o, z);
assert o = 0;
assert z;
wait;
end process;
end architecture;
|
package A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean);
procedure PROC_B(I:in integer; O:out integer; Z:out boolean);
procedure PROC_C(I:in integer; O:out integer; Z:out boolean);
end package;
package body A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean) is
begin
-- Used to abort calling forward-declared procedure
PROC_B(I,O,Z);
end procedure;
procedure PROC_B(I:in integer; O:out integer; Z:out boolean) is
begin
PROC_C(I,O,Z);
end procedure;
procedure PROC_C(I:in integer; O:out integer; Z:out boolean) is
begin
O := I;
Z := (I = 0);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue121 is
end entity;
use work.A.all;
architecture test of issue121 is
begin
process is
variable o : integer;
variable z : boolean;
begin
proc_a(1, o, z);
assert o = 1;
assert not z;
proc_a(0, o, z);
assert o = 0;
assert z;
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package spwcomp is
component grspwc2 is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 64 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_ulogic;
tickinraw : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_ulogic;
tickout : out std_ulogic;
tickoutraw : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(5 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(5 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(5 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(5 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(9 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(9 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
--parallel rx data out
rxdav : out std_ulogic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_ulogic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
-- SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grspwc is
generic(
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
tech : integer;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
rmapact : out std_ulogic
);
end component;
component grspwc_axcelerator is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc_unisim is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspw_gen is
generic(
tech : integer := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspw_codec_core is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
inputtest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx fifo signals
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(9 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(9 downto 0);
rxaccess : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx fifo signals
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(8 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(8 downto 0);
txaccess : out std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickin_busy : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
credcnt : out std_logic_vector(5 downto 0);
ocredcnt : out std_logic_vector(5 downto 0);
--misc
powerdown : out std_ulogic;
powerdownrx : out std_ulogic;
-- input timing testing
testdi : in std_logic_vector(1 downto 0) := "00";
testsi : in std_logic_vector(1 downto 0) := "00";
testinput : in std_ulogic := '0'
);
end component;
component grspw2_gen is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 64 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
techfifo : integer range 0 to 1 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_ulogic;
tickinraw : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_ulogic;
tickout : out std_ulogic;
tickoutraw : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--parallel rx data out
rxdav : out std_ulogic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_ulogic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
-- SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grspw_codec_gen is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--misc
merror : out std_ulogic
);
end component;
end package;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: vram_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY vram_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END vram_exdes;
ARCHITECTURE xilinx OF vram_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT vram IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : vram
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
-------------------------------------------------------------------------------
--
-- Title : half_adder_gates
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\half_adder_gates.vhd
-- Generated : Thu Nov 17 09:55:39 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {half_adder_gates} architecture {half_adder_gates}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity inv is
port(
i1: in std_logic;
o1: out std_logic
);
end inv;
--}} End of automatically maintained section
architecture dataflow of inv is
begin
o1 <= not i1;
-- enter your statements here --
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity or_2 is
port(
i1, i2: in std_logic;
o1: out std_logic);
end or_2;
architecture dataflow of or_2 is
begin
o1 <= i1 or i2;
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity and_2 is
port(
i1, i2: in std_logic;
o1: out std_logic);
end and_2;
architecture dataflow of and_2 is
begin
o1 <= i1 and i2;
end dataflow;
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: soamem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2018 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY soamem IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END soamem;
ARCHITECTURE SYN OF soamem IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "NORMAL",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 32,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 5,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
clocken0 => clken,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "1"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL soamem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL soamem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL soamem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL soamem.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL soamem_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
constant I2CFSMLength : integer := 1295;
constant I2CFSMCfg : std_logic_vector(I2CFSMLength-1 downto 0) := "00011000000010000000010000010001010011000000000010001100110001100000000000000111001000110000000001000100000101001000001100000000000000100001000000010000100000000000000001000100011101100001000000000001000000011000001001000000000001000010000000101010000110000000000010001000000010100000000100010000000000101000000011000101001000000100000001010000000101010110010110001000000100100000100100011001100001000000001001000001000101001000100010000000010100000000011000100010000010000000001000000011001000010001000000000000000100000001100010100100010000000000001011000000001111000110010100000100000110000000000111100001001000001000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000";
|
constant I2CFSMLength : integer := 1295;
constant I2CFSMCfg : std_logic_vector(I2CFSMLength-1 downto 0) := "00011000000010000000010000010001010011000000000010001100110001100000000000000111001000110000000001000100000101001000001100000000000000100001000000010000100000000000000001000100011101100001000000000001000000011000001001000000000001000010000000101010000110000000000010001000000010100000000100010000000000101000000011000101001000000100000001010000000101010110010110001000000100100000100100011001100001000000001001000001000101001000100010000000010100000000011000100010000010000000001000000011001000010001000000000000000100000001100010100100010000000000001011000000001111000110010100000100000110000000000111100001001000001000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000";
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity roi_process is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
status_reg_bypass_bit : in std_logic;
in_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
out_size_reg_out_w_reg : in std_logic_vector(11 downto 0);
out_size_reg_out_h_reg : in std_logic_vector(11 downto 0);
out_offset_reg_out_x_reg : in std_logic_vector(11 downto 0);
out_offset_reg_out_y_reg : in std_logic_vector(11 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end roi_process;
architecture rtl of roi_process is
constant X_COUNTER_SIZE : integer := 12;
constant Y_COUNTER_SIZE : integer := 12;
signal x_pos : unsigned(X_COUNTER_SIZE-1 downto 0);
signal y_pos : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal bypass_s : std_logic;
begin
data_process : process (clk_proc, reset_n)
begin
if(reset_n='0') then
out_data <= (others => '0');
out_dv <= '0';
out_fv <= '0';
x_pos <= to_unsigned(0, X_COUNTER_SIZE);
y_pos <= to_unsigned(0, Y_COUNTER_SIZE);
bypass_s <= '0';
elsif(rising_edge(clk_proc)) then
if(in_fv = '1'
and status_reg_enable_bit = '1'
and (unsigned(out_offset_reg_out_x_reg) < unsigned(in_size_reg_in_w_reg))
and (unsigned(out_offset_reg_out_y_reg) < unsigned(in_size_reg_in_h_reg))) then
out_fv <= '1';
else
out_fv <= '0';
end if;
out_dv <= '0';
if(in_fv = '0') then
x_pos <= to_unsigned(0, X_COUNTER_SIZE);
y_pos <= to_unsigned(0, Y_COUNTER_SIZE);
bypass_s <= status_reg_bypass_bit;
else
if(in_dv = '1' and status_reg_enable_bit = '1') then
x_pos <= x_pos + 1;
if(x_pos=unsigned(in_size_reg_in_w_reg)-1) then
y_pos <= y_pos + 1;
x_pos <= to_unsigned(0, X_COUNTER_SIZE);
end if;
if(bypass_s = '0') then
if(y_pos >= unsigned(out_offset_reg_out_y_reg)
and y_pos < (unsigned(out_offset_reg_out_y_reg) + unsigned(out_size_reg_out_h_reg))
and x_pos >= unsigned(out_offset_reg_out_x_reg)
and x_pos < (unsigned(out_offset_reg_out_x_reg) + unsigned(out_size_reg_out_w_reg))) then
out_dv <= '1';
out_data <= in_data;
end if;
else
out_dv <= '1';
out_data <= in_data;
end if;
end if;
end if;
end if;
end process;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY cpu_core_portb_int IS
END cpu_core_portb_int;
ARCHITECTURE behavior OF cpu_core_portb_int IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cpu_core
GENERIC( instruction_file : string);
PORT(
clk : IN std_logic;
reset : IN std_logic;
porta : INOUT std_logic_vector(4 downto 0);
portb : INOUT std_logic_vector(7 downto 0);
pc_out : OUT std_logic_vector(12 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal porta : std_logic_vector(4 downto 0);
signal portb : std_logic_vector(7 downto 0);
signal pc_out : std_logic_vector(12 downto 0);
-- Clock period definitions
constant clk_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cpu_core
Generic map(instruction_file => "scripts/instructions_portb_int.mif")
PORT MAP (
clk => clk,
reset => reset,
porta => porta,
portb => portb,
pc_out => pc_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
portb <= "00000000";
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
wait for clk_period*20;
portb <= "10000000";
wait for clk_period;
portb <= "00000000";
wait for clk_period*2;
-- Check that RBI interrupt has been caught, e.g. PC is 0x04 (interrupt vector)
assert pc_out = std_logic_vector(to_unsigned(4,13)) report "RB interrupt not caught" severity failure;
wait for clk_period*3;
portb <= "00000001";
wait for clk_period*3;
-- Check that RB0/INT interrupt has been caught, e.g. PC is 0x04 (interrupt vector)
assert pc_out = std_logic_vector(to_unsigned(4,13)) report "RB0/INT interrupt not caught" severity failure;
wait;
end process;
END;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
entity rc5_key is
port( clr : in std_logic;
clk : in std_logic;
key : in std_logic_vector(127 downto 0);
key_vld : in std_logic;
skey : out rc5_rom_26;
key_rdy : out std_logic);
end rc5_key;
architecture key_exp of rc5_key is
signal i_cnt : std_logic_vector(04 downto 00); -- s_array counter
signal j_cnt : std_logic_vector(04 downto 00); -- l_array counter
signal r_cnt : std_logic_vector(06 downto 00); -- overall counterer; counts to 78
signal a : std_logic_vector(31 downto 00);
signal a_circ : std_logic_vector(31 downto 00);
signal a_reg : std_logic_vector(31 downto 00); -- register A
signal b : std_logic_vector(31 downto 00);
signal b_circ : std_logic_vector(31 downto 00);
signal b_reg : std_logic_vector(31 downto 00); -- register B
signal temp : std_logic_vector(31 downto 00);
--Key Expansion state machine has five states: idle, key in, expansion and ready
signal state : rc5_key_StateType;
signal l : rc5_rom_4;
signal s : rc5_rom_26;
begin
-- it is not a data-dependent rotation!
--A = S[i] = (S[i] + A + B) <<< 3;
a <= s(conv_integer(i_cnt)) + a_reg + b_reg; --S + A + B
a_circ <= a(28 downto 0) & a(31 downto 29); --rot by 3
-- this is a data-dependent rotation!
--B = L[j] = (L[j] + A + B) <<< (A + B);
b <= l(conv_integer(j_cnt)) + a_circ + b_reg; --L + A + B
-- rot by A + B
temp <= a_circ + b_reg;
with temp(4 downto 0) select
b_circ <= b(30 downto 0) & b(31) when "00001", --01
b(29 downto 0) & b(31 downto 30) when "00010", --02
b(28 downto 0) & b(31 downto 29) when "00011", --03
b(27 downto 0) & b(31 downto 28) when "00100", --04
b(26 downto 0) & b(31 downto 27) when "00101", --05
b(25 downto 0) & b(31 downto 26) when "00110", --06
b(24 downto 0) & b(31 downto 25) when "00111", --07
b(23 downto 0) & b(31 downto 24) when "01000", --08
b(22 downto 0) & b(31 downto 23) when "01001", --09
b(21 downto 0) & b(31 downto 22) when "01010", --10
b(20 downto 0) & b(31 downto 21) when "01011", --11
b(19 downto 0) & b(31 downto 20) when "01100", --12
b(18 downto 0) & b(31 downto 19) when "01101", --13
b(17 downto 0) & b(31 downto 18) when "01110", --14
b(16 downto 0) & b(31 downto 17) when "01111", --15
b(15 downto 0) & b(31 downto 16) when "10000", --16
b(14 downto 0) & b(31 downto 15) when "10001", --17
b(13 downto 0) & b(31 downto 14) when "10010", --18
b(12 downto 0) & b(31 downto 13) when "10011", --19
b(11 downto 0) & b(31 downto 12) when "10100", --20
b(10 downto 0) & b(31 downto 11) when "10101", --21
b(09 downto 0) & b(31 downto 10) when "10110", --22
b(08 downto 0) & b(31 downto 09) when "10111", --23
b(07 downto 0) & b(31 downto 08) when "11000", --24
b(06 downto 0) & b(31 downto 07) when "11001", --25
b(05 downto 0) & b(31 downto 06) when "11010", --26
b(04 downto 0) & b(31 downto 05) when "11011", --27
b(03 downto 0) & b(31 downto 04) when "11100", --28
b(02 downto 0) & b(31 downto 03) when "11101", --29
b(01 downto 0) & b(31 downto 02) when "11110", --30
b(0) & b(31 downto 01) when "11111", --31
b when others;
state_block:
process(clr, clk)
begin
if (clr = '0') then
state <= st_idle;
elsif (rising_edge(clk)) then
case state is
when st_idle =>
if(key_vld = '1') then
state <= st_key_in;
end if;
when st_key_in =>
state <= st_key_exp;
when st_key_exp =>
if (r_cnt = "1001101") then
state <= st_ready;
end if;
when st_ready =>
state <= st_idle;
end case;
end if;
end process;
a_reg_block:
process(clr, clk)
begin
if(clr = '0') then
a_reg <= (others => '0');
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
a_reg <= a_circ;
end if;
end if;
end process;
b_reg_block:
process(clr, clk)
begin
if(clr = '0') then
b_reg <= (others => '0');
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
b_reg <= b_circ;
end if;
end if;
end process;
s_array_counter_block:
process(clr, clk)
begin
if(clr='0') then i_cnt<=(others=>'0');
elsif(rising_edge(clk)) then
if(state=ST_KEY_EXP) then
if(i_cnt="11001") then i_cnt <= (others=>'0');
else i_cnt <= i_cnt + 1;
end if;
end if;
end if;
end process;
l_array_counter_block:
process(clr, clk)
begin
if(clr='0') then j_cnt<=(others=>'0');
elsif(rising_edge(clk)) then
if(j_cnt="00011") then j_cnt<=(others=>'0');
else j_cnt <= j_cnt + 1;
end if;
end if;
end process;
overall_counter_block:
process(clr, clk)
begin
if (clr = '0') then
r_cnt <= "0000000";
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
r_cnt <= r_cnt + 1;
end if;
end if;
end process;
--S[0] = 0xB7E15163 (Pw)
--for i=1 to 25 do S[i] = S[i-1]+ 0x9E3779B9 (Qw)
--array s
process(clr, clk)
begin
if (clr = '0') then
s(0) <= X"b7e15163"; s(1) <= X"5618cb1c";s(2) <= X"f45044d5";
s(3) <= X"9287be8e";s(4) <= X"30bf3847";s(5) <= X"cef6b200";
s(6) <= X"6d2e2bb9";s(7) <= X"0b65a572";s(8) <= X"a99d1f2b";
s(9) <= X"47d498e4";s(10) <= X"e60c129d";s(11) <= X"84438c56";
s(12) <= X"227b060f";s(13) <= X"c0b27fc8";s(14) <= X"5ee9f981";
s(15) <= X"fd21733a";s(16) <= X"9b58ecf3";s(17) <= X"399066ac";
s(18) <= X"d7c7e065";s(19) <= X"75ff5a1e";s(20) <= X"1436d3d7";
s(21) <= X"b26e4d90";s(22) <= X"50a5c749";s(23) <= X"eedd4102";
s(24) <= X"8d14babb";s(25) <= X"2b4c3474";
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
s(conv_integer(i_cnt)) <= a_circ;--i = (i + 1) mod 26;
end if;
end if;
end process;
--l array
process(clr, clk)
begin
if(clr = '0') then
l(0) <= (others=>'0');
l(1) <= (others=>'0');
l(2) <= (others=>'0');
l(3) <= (others=>'0');
elsif (rising_edge(clk)) then
if(state = st_key_in) then
l(0) <= key(31 downto 0);
l(1) <= key(63 downto 32);
l(2) <= key(95 downto 64);
l(3) <= key(127 downto 96);
elsif(state = st_key_exp) then
l(conv_integer(j_cnt)) <= b_circ; --j = (j + 1) mod 4;
end if;
end if;
end process;
skey <= s;
with state select
key_rdy <= '1' when st_ready,
'0' when others;
end key_exp; |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.1
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END bram;
ARCHITECTURE bram_arch OF bram IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_RST_TYPE : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_CTRL_ECC_ALGO : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_arch: ARCHITECTURE IS "blk_mem_gen_v8_1,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_arch : ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_arch: ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.1,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=bram.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_RST_TYPE=SYNC,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_ENABLE_32BIT_ADDRESS=0,C_DISABLE_WARN_BHV_COLL=0,C_DISABLE_WARN_BHV_RANGE=0,C_USE_BRAM_BLOCK=0,C_CTRL_ECC_ALGO=NONE}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_1
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "bram.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_RST_TYPE => "SYNC",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_ENABLE_32BIT_ADDRESS => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_USE_BRAM_BLOCK => 0,
C_CTRL_ECC_ALGO => "NONE"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_arch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.1
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END bram;
ARCHITECTURE bram_arch OF bram IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_RST_TYPE : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_CTRL_ECC_ALGO : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_arch: ARCHITECTURE IS "blk_mem_gen_v8_1,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_arch : ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_arch: ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.1,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=bram.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_RST_TYPE=SYNC,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_ENABLE_32BIT_ADDRESS=0,C_DISABLE_WARN_BHV_COLL=0,C_DISABLE_WARN_BHV_RANGE=0,C_USE_BRAM_BLOCK=0,C_CTRL_ECC_ALGO=NONE}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_1
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "bram.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_RST_TYPE => "SYNC",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_ENABLE_32BIT_ADDRESS => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_USE_BRAM_BLOCK => 0,
C_CTRL_ECC_ALGO => "NONE"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_arch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.1
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END bram;
ARCHITECTURE bram_arch OF bram IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_RST_TYPE : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_CTRL_ECC_ALGO : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_arch: ARCHITECTURE IS "blk_mem_gen_v8_1,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_arch : ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_arch: ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.1,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=bram.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_RST_TYPE=SYNC,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_ENABLE_32BIT_ADDRESS=0,C_DISABLE_WARN_BHV_COLL=0,C_DISABLE_WARN_BHV_RANGE=0,C_USE_BRAM_BLOCK=0,C_CTRL_ECC_ALGO=NONE}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_1
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "bram.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_RST_TYPE => "SYNC",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_ENABLE_32BIT_ADDRESS => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_USE_BRAM_BLOCK => 0,
C_CTRL_ECC_ALGO => "NONE"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_arch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.1
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END bram;
ARCHITECTURE bram_arch OF bram IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_RST_TYPE : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_CTRL_ECC_ALGO : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_arch: ARCHITECTURE IS "blk_mem_gen_v8_1,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_arch : ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_arch: ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.1,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=bram.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_RST_TYPE=SYNC,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_ENABLE_32BIT_ADDRESS=0,C_DISABLE_WARN_BHV_COLL=0,C_DISABLE_WARN_BHV_RANGE=0,C_USE_BRAM_BLOCK=0,C_CTRL_ECC_ALGO=NONE}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_1
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "bram.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_RST_TYPE => "SYNC",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_ENABLE_32BIT_ADDRESS => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_USE_BRAM_BLOCK => 0,
C_CTRL_ECC_ALGO => "NONE"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_arch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.1
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END bram;
ARCHITECTURE bram_arch OF bram IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_RST_TYPE : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_CTRL_ECC_ALGO : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_arch: ARCHITECTURE IS "blk_mem_gen_v8_1,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_arch : ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_arch: ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.1,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=bram.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_RST_TYPE=SYNC,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_ENABLE_32BIT_ADDRESS=0,C_DISABLE_WARN_BHV_COLL=0,C_DISABLE_WARN_BHV_RANGE=0,C_USE_BRAM_BLOCK=0,C_CTRL_ECC_ALGO=NONE}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_1
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "bram.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_RST_TYPE => "SYNC",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_ENABLE_32BIT_ADDRESS => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_USE_BRAM_BLOCK => 0,
C_CTRL_ECC_ALGO => "NONE"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_arch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.1
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END bram;
ARCHITECTURE bram_arch OF bram IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_RST_TYPE : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_CTRL_ECC_ALGO : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_arch: ARCHITECTURE IS "blk_mem_gen_v8_1,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_arch : ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_arch: ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.1,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=bram.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_RST_TYPE=SYNC,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_ENABLE_32BIT_ADDRESS=0,C_DISABLE_WARN_BHV_COLL=0,C_DISABLE_WARN_BHV_RANGE=0,C_USE_BRAM_BLOCK=0,C_CTRL_ECC_ALGO=NONE}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_1
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "bram.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_RST_TYPE => "SYNC",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_ENABLE_32BIT_ADDRESS => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_USE_BRAM_BLOCK => 0,
C_CTRL_ECC_ALGO => "NONE"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_arch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.1
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END bram;
ARCHITECTURE bram_arch OF bram IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_RST_TYPE : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_CTRL_ECC_ALGO : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_arch: ARCHITECTURE IS "blk_mem_gen_v8_1,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_arch : ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_arch: ARCHITECTURE IS "bram,blk_mem_gen_v8_1,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.1,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=bram.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_RST_TYPE=SYNC,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_ENABLE_32BIT_ADDRESS=0,C_DISABLE_WARN_BHV_COLL=0,C_DISABLE_WARN_BHV_RANGE=0,C_USE_BRAM_BLOCK=0,C_CTRL_ECC_ALGO=NONE}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_1
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "bram.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_RST_TYPE => "SYNC",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "READ_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_ENABLE_32BIT_ADDRESS => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_USE_BRAM_BLOCK => 0,
C_CTRL_ECC_ALGO => "NONE"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity FSM is
port (
Clk, Rst, Enter : in std_logic;
Operacao: in std_logic_vector(1 downto 0);
Sel: out std_logic_vector(1 downto 0);
Enable_1, Enable_2: out std_logic
);
end FSM;
architecture FSM_beh of FSM is
type states is (S0, S1, S2, S3, S4, S5, S6, S7);
signal EA: states;
signal last_sel, last_EN: std_logic_vector(1 downto 0);
begin
P1: process (Clk, Rst, Enter, Operacao)
begin
-- não esquecer do end if;
if Rst = '0' then
EA <= S0;
elsif Clk'event and Clk = '1' then
case EA is
when S0 =>
if Enter = '0' then
EA <= S1;
else
EA <= S0;
end if;
when S1 =>
if Enter = '0' then
EA <= S1;
else
EA <= S2;
end if;
when S2 =>
if Operacao = "00" then
EA <= S3; -- Fazer SOMA
elsif Operacao = "01" then
EA <= S4; -- Fazer SUB
elsif Operacao = "10" then
EA <= S5; -- Fazer /2
else
EA <= S6; -- Fazer *2
end if;
when S3 => --SOMA
if Enter = '1' then
EA <= S3;
else
EA <= S7;
end if;
when S4 => --SUB
if Enter = '1' then
EA <= S4;
else
EA <= S7;
end if;
when S5 => --/2
EA <= S0;
when S6 => --*2
EA <= S0;
when S7 =>
if Enter = '0' then
EA <= S7;
else
EA <= S0;
end if;
end case;
end if;
end process;
P2: process(EA)
begin
case EA is
when S0 =>
Enable_1 <= '0';
Enable_2 <= '0';
when S1 =>
Enable_1 <= '1';
Enable_2 <= '0';
when S2 =>
Enable_1 <= '0';
Enable_2 <= '0';
last_sel <= Operacao;
when S3 => --SOMA
--Enable_1 <= '0';
--Enable_2 <= '0';
Sel <= last_sel;
when S4 => --SUB
--Enable_1 <= '0';
--Enable_2 <= '0';
Sel <= last_sel;
when S5 => --/2
Enable_1 <= '0';
Enable_2 <= '1';
Sel <= last_sel;
when S6 => --*2
Enable_1 <= '0';
Enable_2 <= '1';
Sel <= last_sel;
when S7 =>
Enable_1 <= '0';
Enable_2 <= '1';
Sel <= last_sel;
end case;
end process;
end FSM_beh;
|
---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <[email protected]>
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
-- Color format :
-- "1111100000000000" : red (5 bits, 15 downto 11)
-- "0000011111100000" : green (6 bits, 10 downto 5)
-- "0000000000011111" : blue (5 bits, 4 downto 0)
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------------------------------
entity genpix is
generic(system_frequency: real := 50_000_000.0);
port(x : in std_logic_vector(7 downto 0); -- 0 .. 239 => 8 bits
y : in std_logic_vector(8 downto 0); -- 0 .. 319 => 9 bits
c : out std_logic_vector(15 downto 0); -- 16 bits colors
resetn: in std_logic;
clk : in std_logic);
end entity genpix;
---------------------------------------------------------------------------
architecture rtl of genpix is
constant t_cycles : natural := integer(system_frequency * 1.0e-1);
signal pos_x : unsigned(x'range);
signal pos_y : unsigned(y'range);
signal c0_reg, c1_reg, c2_reg, c3_reg: std_logic_vector(c'range);
signal split_x : unsigned(x'range);
signal split_y : unsigned(y'range);
begin
update_cpt: process(clk, resetn)
variable counter : natural range 0 to (t_cycles - 1);
begin
if resetn = '0' then
counter := 0;
c0_reg <= x"0000";
c1_reg <= x"F800";
c2_reg <= x"07E0";
c3_reg <= x"001F";
split_x <= (others => '0');
split_y <= (others => '0');
elsif rising_edge(clk) then
if (counter = t_cycles - 1) then
counter := 0;
-- Increments 16 bits color value by 1
c0_reg <= std_logic_vector(unsigned(c0_reg) + 1);
-- Increments only RED channel
c1_reg <= std_logic_vector(unsigned(c1_reg(15 downto 11)) + 1) &
"000000" &
"00000";
-- Increments only GREEN channel
c2_reg <= "00000" &
std_logic_vector(unsigned(c2_reg(10 downto 5)) + 1) &
"00000";
-- Increments only BLUE channel
c3_reg <= "00000" &
"000000" &
std_logic_vector(unsigned(c3_reg(4 downto 0)) + 1);
-- Moving line used to split screen into 2 areas
split_y <= (split_y + 1) mod 320;
split_x <= (split_x + 1) mod 240;
else
counter := counter + 1;
end if;
end if; -- resetn = '0'
end process update_cpt;
pos_x <= unsigned(x);
pos_y <= unsigned(y);
update_c:process(clk, resetn)
begin
if resetn = '0' then
c <= (others => '0');
elsif rising_edge(clk) then
-- Displays 3 colored pixels in a 1 pixel width black box
-- in the top left corner
if (pos_x < 5) and (pos_y = 0) then
c <= x"0000";
elsif (pos_x = 0) and (pos_y = 1) then
c <= x"0000";
elsif (pos_x = 1) and (pos_y = 1) then
c <= x"F800";
elsif (pos_x = 2) and (pos_y = 1) then
c <= x"07E0";
elsif (pos_x = 3) and (pos_y = 1) then
c <= x"001F";
elsif (pos_x = 4) and (pos_y = 1) then
c <= x"0000";
elsif (pos_x < 5) and (pos_y = 2) then
c <= x"0000";
-- Display 3 colored bands along the left side
elsif (pos_x < 10) then
c <= "11111" & "000000" & "00000"; -- R
elsif (pos_x < 20) then
c <= "00000" & "111111" & "00000"; -- V
elsif (pos_x < 30) then
c <= "00000" & "000000" & "11111"; -- B
-- Display 3 colored bands along the top side
elsif (pos_y < 10) then
c <= "11111" & "010000" & "01000";
elsif (pos_y < 20) then
c <= "01000" & "111111" & "01000";
elsif (pos_y < 30) then
c <= "01000" & "010000" & "11111";
-- Split the remaining screen area into 4 area-changing
-- sections, each filed with a single color
elsif pos_x < split_x then
if pos_y < split_y then
c <= c0_reg; -- x"07E0"; -- Green
else
c <= c1_reg; --x"001f"; -- Blue
end if; -- pos_x < 160
else
if pos_y < split_y then
c <= c2_reg; --x"F800"; -- Red
else
c <= c3_reg; --x"ffff";
end if; -- pos_x < 160
end if; -- pos_x < 120
end if; -- rising_edge(clk)
end process update_c;
end architecture rtl;
---------------------------------------------------------------------------
|
-- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____32.500______0.000______50.0______815.385____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
CLK50 : in std_logic;
-- Clock out ports
CLK : out std_logic
);
end clock;
architecture xilinx of clock is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock,clk_wiz_v3_3,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK50);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 20,
CLKFX_MULTIPLY => 13,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK,
I => clkfx);
end xilinx;
|
------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the implementation of a generic bidirectional
-- ps/2 interface.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- the ps/2 protocol works.
-- http://www.computer-engineering.org/ps2protocol/
-- This module implements a generic bidirectional ps/2 interface. It can
-- be used with any ps/2 compatible device. It offers its clients a
-- convenient way to exchange data with the device. The interface
-- transparently wraps the byte to be sent into a ps/2 frame, generates
-- parity for byte and sends the frame one bit at a time to the device.
-- Similarly, when receiving data from the ps2 device, the interface
-- receives the frame, checks for parity, and extract the usefull data
-- and forwards it to the client. If an error occurs during receiving
-- or sending a byte, the client is informed by settings the err output
-- line high. This way, the client can resend the data or can issue
-- a resend command to the device.
-- The physical ps/2 interface uses 4 lines
-- For the 6-pin connector pins are assigned as follows:
-- 1 - Data
-- 2 - Not Implemented
-- 3 - Ground
-- 4 - Vcc (+5V)
-- 5 - Clock
-- 6 - Not Implemented
-- The clock line carries the device generated clock which has a
-- frequency in range 10 - 16.7 kHz (30 to 50us). When line is idle
-- it is placed in high impedance. The clock is only generated when
-- device is sending or receiving data.
-- The Data and Clock lines are both open-collector with pullup
-- resistors to Vcc. An "open-collector" interface has two possible
-- states: low('0') or high impedance('Z').
-- When device wants to send a byte, it pulls the clock line low and the
-- host(i.e. this interfaces) recognizes that the device is sending data
-- When the host wants to send data, it maeks a request to send. This
-- is done by holding the clock line low for at least 100us, then with
-- the clock line low, the data line is brought low. Next the clock line
-- is released (placed in high impedance). The devices begins generating
-- clock signal on clock line.
-- When receiving data, bits are read from the data line (ps2_data) on
-- the falling edge of the clock (ps2_clk). When sending data, the
-- device reads the bits from the data line on the rising edge of the
-- clock.
-- A frame for sending a byte is comprised of 11 bits as shown bellow:
-- bits 10 9 8 7 6 5 4 3 2 1 0
-- -------------------------------------------------------------
-- | STOP| PAR | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | START |
-- -------------------------------------------------------------
-- STOP - stop bit, always '1'
-- PAR - parity bit, odd parity for the 8 data bits.
-- - select in such way that the number of bits of '1' in the data
-- - bits together with parity bit is odd.
-- D0-7 - data bits.
-- START - start bit, always '0'
--
-- Frame is sent bit by bit starting with the least significant bit
-- (starting bit) and is received the same way. This is done, when
-- receiving, by shifting the frame register to the left when a bit
-- is available and placing the bit on data line on the most significant
-- bit. This way the first bit sent will reach the least significant bit
-- of the frame when all the bits have been received. When sending data
-- the least significant bit of the frame is placed on the data line
-- and the frame is shifted to the right when another bit needs to be
-- sent. During the request to send, when releasing the clock line,
-- the device reads the data line and interprets the data on it as the
-- first bit of the frame. Data line is low at that time, at this is the
-- way the start bit('0') is sent. Because of this, when sending, only
-- 10 shifts of the frame will be made.
-- While the interface is sending or receiving data, the busy output
-- signal goes high. When interface is idle, busy is low.
-- After sending all the bits in the frame, the device must acknowledge
-- the data sent. This is done by the host releasing and data line
-- (clock line is already released) after the last bit is sent. The
-- devices brings the data line and the clock line low, in this order,
-- to acknowledge the data. If data line is high when clock line goes
-- low after last bit, the device did not acknowledge the data and
-- err output is set.
-- A FSM is used to manage the transitions the set all the command
-- signals. States that begin with "rx_" are used to receive data
-- from device and states begining with "tx_" are used to send data
-- to the device.
-- For the parity bit, a ROM holds the parity bit for all possible
-- data (256 possible values, since 8 bits of data). The ROM has
-- dimensions 256x1bit. For obtaining the parity bit of a value,
-- the bit at the data value address is read. Ex: to find the parity
-- bit of 174, the bit at address 174 is read.
-- For generating the necessary delay, counters are used. For example,
-- to generate the 100us delay a 14 bit counter is used that has the
-- upper limit for counting 10000. The interface is designed to run
-- at 100MHz. Thus, 10000x10ns = 100us.
-----------------------------------------------------------------------
-- If using the interface at different frequency than 100MHz, adjusting
-- the delay counters is necessary!!!
-----------------------------------------------------------------------
-- Clock line(ps2_clk) and data line(ps2_data) are passed through a
-- debouncer for the transitions of the clock and data to be clean.
-- Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized
-- value of the clock and data line to the system clock(clk).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- ps2_clk - inout pin, clock line of the ps/2 interface
-- ps2_data - inout pin, clock line of the ps/2 interface
-- clk - input pin, system clock signal
-- rst - input pin, system reset signal
-- tx_data - input pin, 8 bits, from client
-- - data to be sent to the device
-- write - input pin, from client
-- - should be active for one clock period when then
-- - client wants to send data to the device and
-- - data to be sent is valid on tx_data
-- rx_data - output pin, 8 bits, to client
-- - data received from device
-- read - output pin, to client
-- - active for one clock period when new data is
-- - available from device
-- busy - output pin, to client
-- - active while sending or receiving data.
-- err - output pin, to client
-- - active for one clock period when an error occurred
-- - during sending or receiving.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the ps2interface entity declaration
-- read above for behavioral description and port definitions.
entity ps2interface is
port(
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
clk : in std_logic;
rst : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
write : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
read : out std_logic;
busy : out std_logic;
err : out std_logic
);
-- forces the extraction of distributed ram for
-- the parityrom memory.
-- please remove if block ram is preffered.
attribute rom_extract : string;
attribute rom_extract of ps2interface: entity is "yes";
attribute rom_style : string;
attribute rom_style of ps2interface: entity is "distributed";
end ps2interface;
architecture Behavioral of ps2interface is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- Values are valid for a 100MHz clk. Please adjust for other
-- frequencies if necessary!
-- upper limit for 100us delay counter.
-- 10000 * 10ns = 100us
constant DELAY_100US : std_logic_vector(13 downto 0):= "10011100010000";
-- 10000 clock periods
-- upper limit for 20us delay counter.
-- 2000 * 10ns = 20us
constant DELAY_20US : std_logic_vector(10 downto 0) := "11111010000";
-- 2000 clock periods
-- upper limit for 63clk delay counter.
constant DELAY_63CLK : std_logic_vector(5 downto 0) := "111111";
-- 63 clock periods
-- delay from debouncing ps2_clk and ps2_data signals
constant DEBOUNCE_DELAY : std_logic_vector(3 downto 0) := "1111";
-- number of bits in a frame
constant NUMBITS: std_logic_vector(3 downto 0) := "1011"; -- 11
-- parity bit position in frame
constant PARITY_BIT: positive := 9;
-- (odd) parity bit ROM
-- Used instead of logic because this way speed is far greater
-- 256x1bit rom
-- If the odd parity bit for a 8 bits number, x, is needed
-- the bit at address x is the parity bit.
type ROM is array(0 to 255) of std_logic;
constant parityrom : ROM := (
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1'
);
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- 14 bits counter
-- max value DELAY_100US
-- used to wait 100us
signal delay_100us_count: std_logic_vector(13 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_20US
-- used to wait 20us
signal delay_20us_count: std_logic_vector(10 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_63CLK
-- used to wait 63 clock periods
signal delay_63clk_count: std_logic_vector(5 downto 0) :=
(others => '0');
-- done signal for the couters above
-- when a counter reaches max value,the corresponding done signal is set
signal delay_100us_done, delay_20us_done, delay_63clk_done: std_logic;
-- enable signal for 100us delay counter
signal delay_100us_counter_enable: std_logic := '0';
-- enable signal for 20us delay counter
signal delay_20us_counter_enable : std_logic := '0';
-- enable signal for 63clk delay counter
signal delay_63clk_counter_enable: std_logic := '0';
-- synchronzed input for ps2_clk and ps2_data
signal ps2_clk_s,ps2_data_s: std_logic := '1';
-- control the output of ps2_clk and ps2_data
-- if 1 then corresponding signal (ps2_clk or ps2_data) is
-- put in high impedance ('Z').
signal ps2_clk_h,ps2_data_h: std_logic := '1';
-- states of the FSM for controlling the communcation with the device
-- states that begin with "rx_" are used when receiving data
-- states that begin with "tx_" are used when transmiting data
type fsm_state is
(
idle,rx_clk_h,rx_clk_l,rx_down_edge,rx_error_parity,rx_data_ready,
tx_force_clk_l,tx_bring_data_down,tx_release_clk,
tx_first_wait_down_edge,tx_clk_l,tx_wait_up_edge,tx_clk_h,
tx_wait_up_edge_before_ack,tx_wait_ack,tx_received_ack,
tx_error_no_ack
);
-- the signal that holds the current state of the FSM
-- implicitly state is idle.
signal state: fsm_state := idle;
-- register that holds the frame received or the one to be sent.
-- Its contents are shifted in from the bus one bit at a time
-- from left to right when receiving data and are shifted on the
-- bus (ps2_data) one bit at a time to the right when sending data
signal frame: std_logic_vector(10 downto 0) := (others => '0');
-- how many bits have been sent or received.
signal bit_count: std_logic_vector(3 downto 0) := (others => '0');
-- when active the bit counter is reset.
signal reset_bit_count: std_logic := '0';
-- when active the contents of the frame is shifted to the right
-- and the most significant bit of frame is loaded with ps2_data.
signal shift_frame: std_logic := '0';
-- parity of the byte that was received from the device.
-- must match the parity bit received, else error occurred.
signal rx_parity: std_logic := '0';
-- parity bit that is sent with the frame, representing the
-- odd parity of the byte currently being sent
signal tx_parity: std_logic := '0';
-- when active, frame is loaded with the start bit, data on
-- tx_data, parity bit (tx_parity) and stop bit
-- this frame will be sent to the device.
signal load_tx_data: std_logic := '0';
-- when active bits 8 downto 1 from frame are loaded into
-- rx_data register. This is the byte received from the device.
signal load_rx_data: std_logic := '0';
-- intermediary signals used to debounce the inputs ps2_clk and ps2_data
signal ps2_clk_clean,ps2_data_clean: std_logic := '1';
-- debounce counter for the ps2_clk input and the ps2_data input.
signal clk_count,data_count: std_logic_vector(3 downto 0);
-- last value on ps2_clk and ps2_data.
signal clk_inter,data_inter: std_logic := '1';
begin
---------------------------------------------------------------------
-- FLAGS and PS2 CLOCK AND DATA LINES
---------------------------------------------------------------------
-- clean ps2_clk signal (debounce)
-- note that this introduces a delay in ps2_clk of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_clk is different
-- from the last value, then reset counter
-- and retain value
if(ps2_clk /= clk_inter) then
clk_inter <= ps2_clk;
clk_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(clk_count = DEBOUNCE_DELAY) then
ps2_clk_clean <= clk_inter;
-- ps2_clk did not change, but counter did not
-- reach limit. Increment counter
else
clk_count <= clk_count + 1;
end if;
end if;
end process;
-- clean ps2_data signal (debounce)
-- note that this introduces a delay in ps2_data of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_data is different
-- from the last value, then reset counter
-- and retain value
if(ps2_data /= data_inter) then
data_inter <= ps2_data;
data_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(data_count = DEBOUNCE_DELAY) then
ps2_data_clean <= data_inter;
-- ps2_data did not change, but counter did not
-- reach limit. Increment counter
else
data_count <= data_count + 1;
end if;
end if;
end process;
-- Synchronize ps2 entries
ps2_clk_s <= ps2_clk_clean when rising_edge(clk);
ps2_data_s <= ps2_data_clean when rising_edge(clk);
-- Assign parity from frame bits 8 downto 1, this is the parity
-- that should be received inside the frame on PARITY_BIT position
rx_parity <= parityrom(conv_integer(frame(8 downto 1)))
when rising_edge(clk);
-- The parity for the data to be sent
tx_parity <= parityrom(conv_integer(tx_data)) when rising_edge(clk);
-- Force ps2_clk to '0' if ps2_clk_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_clk <= 'Z' when ps2_clk_h = '1' else '0';
-- Force ps2_data to '0' if ps2_data_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_data <= 'Z' when ps2_data_h = '1' else '0';
-- Control busy flag. Interface is not busy while in idle state.
busy <= '0' when state = idle else '1';
-- reset the bit counter when in idle state.
reset_bit_count <= '1' when state = idle else '0';
-- Control shifting of the frame
-- When receiving from device, data is read
-- on the falling edge of ps2_clk
-- When sending to device, data is read by device
-- on the rising edge of ps2_clk
shift_frame <= '1' when state = rx_down_edge or
state = tx_clk_l else
'0';
---------------------------------------------------------------------
-- FINITE STATE MACHINE
---------------------------------------------------------------------
-- For the current state establish next state
-- and give necessary commands
manage_fsm: process(clk,rst,state,ps2_clk_s,ps2_data_s,write,tx_data,
bit_count,rx_parity,frame,delay_100us_done,
delay_20us_done,delay_63clk_done)
begin
-- if reset occurs, go to idle state.
if(rst = '1') then
state <= idle;
elsif(rising_edge(clk)) then
-- default values for these signals
-- ensures signals are reset to default value
-- when coditions for their activation are no
-- longer applied (transition to other state,
-- where signal should not be active)
-- Idle value for ps2_clk and ps2_data is 'Z'
ps2_clk_h <= '1';
ps2_data_h <= '1';
load_tx_data <= '0';
load_rx_data <= '0';
read <= '0';
err <= '0';
case state is
-- wait for the device to begin a transmission
-- by pulling the clock line low and go to state
-- rx_down_edge or, if write is high, the
-- client of this interface wants to send a byte
-- to the device and a transition is made to state
-- tx_force_clk_l
when idle =>
if(ps2_clk_s = '0') then
state <= rx_down_edge;
elsif(write = '1') then
state <= tx_force_clk_l;
else
state <= idle;
end if;
-- ps2_clk is high, check if all the bits have been read
-- if, last bit read, check parity, and if parity ok
-- load received data into rx_data.
-- else if more bits left, then wait for the ps2_clk to
-- go low
when rx_clk_h =>
if(bit_count = NUMBITS) then
if(not (rx_parity = frame(PARITY_BIT))) then
state <= rx_error_parity;
else
load_rx_data <= '1';
state <= rx_data_ready;
end if;
elsif(ps2_clk_s = '0') then
state <= rx_down_edge;
else
state <= rx_clk_h;
end if;
-- data must be read into frame in this state
-- the ps2_clk just transitioned from high to low
when rx_down_edge =>
state <= rx_clk_l;
-- ps2_clk line is low, wait for it to go high
when rx_clk_l =>
if(ps2_clk_s = '1') then
state <= rx_clk_h;
else
state <= rx_clk_l;
end if;
-- parity bit received is invalid
-- signal error and go back to idle.
when rx_error_parity =>
err <= '1';
state <= idle;
-- parity bit received was good
-- set read signal for the client to know
-- a new byte was received and is available on rx_data
when rx_data_ready =>
read <= '1';
state <= idle;
-- the client wishes to transmit a byte to the device
-- this is done by holding ps2_clk down for at least 100us
-- bringing down ps2_data, wait 20us and then releasing
-- the ps2_clk.
-- This constitutes a request to send command.
-- In this state, the ps2_clk line is held down and
-- the counter for waiting 100us is eanbled.
-- when the counter reached upper limit, transition
-- to tx_bring_data_down
when tx_force_clk_l =>
load_tx_data <= '1';
ps2_clk_h <= '0';
if(delay_100us_done = '1') then
state <= tx_bring_data_down;
else
state <= tx_force_clk_l;
end if;
-- with the ps2_clk line low bring ps2_data low
-- wait for 20us and then go to tx_release_clk
when tx_bring_data_down =>
-- keep clock line low
ps2_clk_h <= '0';
-- set data line low
-- when clock is released in the next state
-- the device will read bit 0 on data line
-- and this bit represents the start bit.
ps2_data_h <= '0'; -- start bit = '0'
if(delay_20us_done = '1') then
state <= tx_release_clk;
else
state <= tx_bring_data_down;
end if;
-- release the ps2_clk line
-- keep holding data line low
when tx_release_clk =>
ps2_clk_h <= '1';
-- must maintain data low,
-- otherwise will be released by default value
ps2_data_h <= '0';
state <= tx_first_wait_down_edge;
-- state is necessary because the clock signal
-- is not released instantaneously and, because of debounce,
-- delay is even greater.
-- Wait 63 clock periods for the clock line to release
-- then if clock is low then go to tx_clk_l
-- else wait until ps2_clk goes low.
when tx_first_wait_down_edge =>
ps2_data_h <= '0';
if(delay_63clk_done = '1') then
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_first_wait_down_edge;
end if;
else
state <= tx_first_wait_down_edge;
end if;
-- place the least significant bit from frame
-- on the data line
-- During this state the frame is shifted one
-- bit to the right
when tx_clk_l =>
ps2_data_h <= frame(0);
state <= tx_wait_up_edge;
-- wait for the clock to go high
-- this is the edge on which the device reads the data
-- on ps2_data.
-- keep holding ps2_data on frame(0) because else
-- will be released by default value.
-- Check if sent the last bit and if so, release data line
-- and go to state that wait for acknowledge
when tx_wait_up_edge =>
ps2_data_h <= frame(0);
-- NUMBITS - 1 because first (start bit = 0) bit was read
-- when the clock line was released in the request to
-- send command (see tx_bring_data_down state).
if(bit_count = NUMBITS-1) then
ps2_data_h <= '1';
state <= tx_wait_up_edge_before_ack;
-- if more bits to send, wait for the up edge
-- of ps2_clk
elsif(ps2_clk_s = '1') then
state <= tx_clk_h;
else
state <= tx_wait_up_edge;
end if;
-- ps2_clk is released, wait for down edge
-- and go to tx_clk_l when arrived
when tx_clk_h =>
ps2_data_h <= frame(0);
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_clk_h;
end if;
-- release ps2_data and wait for rising edge of ps2_clk
-- once this occurs, transition to tx_wait_ack
when tx_wait_up_edge_before_ack =>
ps2_data_h <= '1';
if(ps2_clk_s = '1') then
state <= tx_wait_ack;
else
state <= tx_wait_up_edge_before_ack;
end if;
-- wait for the falling edge of the clock line
-- if data line is low when this occurs, the
-- ack is received
-- else if data line is high, the device did not
-- acknowledge the transimission
when tx_wait_ack =>
if(ps2_clk_s = '0') then
if(ps2_data_s = '0') then
-- acknowledge received
state <= tx_received_ack;
else
-- acknowledge not received
state <= tx_error_no_ack;
end if;
else
state <= tx_wait_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
when tx_received_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
state <= idle;
else
state <= tx_received_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
-- signal error for not receiving ack
when tx_error_no_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
err <= '1';
state <= idle;
else
state <= tx_error_no_ack;
end if;
-- if invalid transition occurred, signal error and
-- go back to idle state
when others =>
err <= '1';
state <= idle;
end case;
end if;
end process manage_fsm;
---------------------------------------------------------------------
-- DELAY COUNTERS
---------------------------------------------------------------------
-- Enable the 100us counter only when state is tx_force_clk_l
delay_100us_counter_enable <= '1' when state = tx_force_clk_l else '0';
-- Counter for a 100us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_100us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_100us_counter_enable = '1') then
if(delay_100us_count = (DELAY_100US)) then
delay_100us_count <= delay_100us_count;
delay_100us_done <= '1';
else
delay_100us_count <= delay_100us_count + 1;
delay_100us_done <= '0';
end if;
else
delay_100us_count <= (others => '0');
delay_100us_done <= '0';
end if;
end if;
end process delay_100us_counter;
-- Enable the 20us counter only when state is tx_bring_data_down
delay_20us_counter_enable <= '1' when state = tx_bring_data_down else '0';
-- Counter for a 20us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_20us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_20us_counter_enable = '1') then
if(delay_20us_count = (DELAY_20US)) then
delay_20us_count <= delay_20us_count;
delay_20us_done <= '1';
else
delay_20us_count <= delay_20us_count + 1;
delay_20us_done <= '0';
end if;
else
delay_20us_count <= (others => '0');
delay_20us_done <= '0';
end if;
end if;
end process delay_20us_counter;
-- Enable the 63clk counter only when state is tx_first_wait_down_edge
delay_63clk_counter_enable <= '1' when state = tx_first_wait_down_edge else '0';
-- Counter for a 63 clock periods delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_63clk_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_63clk_counter_enable = '1') then
if(delay_63clk_count = (DELAY_63CLK)) then
delay_63clk_count <= delay_63clk_count;
delay_63clk_done <= '1';
else
delay_63clk_count <= delay_63clk_count + 1;
delay_63clk_done <= '0';
end if;
else
delay_63clk_count <= (others => '0');
delay_63clk_done <= '0';
end if;
end if;
end process delay_63clk_counter;
---------------------------------------------------------------------
-- BIT COUNTER AND FRAME SHIFTING LOGIC
---------------------------------------------------------------------
-- counts the number of bits shifted into the frame
-- or out of the frame.
bit_counter: process(clk)
begin
if(rising_edge(clk)) then
if(reset_bit_count = '1') then
bit_count <= (others => '0');
elsif(shift_frame = '1') then
bit_count <= bit_count + 1;
end if;
end if;
end process bit_counter;
-- shifts frame with one bit to right when shift_frame is acitve
-- and loads data into frame from tx_data then load_tx_data is high
load_tx_data_into_frame: process(clk)
begin
if(rising_edge(clk)) then
if(load_tx_data = '1') then
frame(8 downto 1) <= tx_data; -- byte to send
frame(0) <= '0'; -- start bit
frame(10) <= '1'; -- stop bit
frame(9) <= tx_parity; -- parity bit
elsif(shift_frame = '1') then
-- shift right 1 bit
frame(9 downto 0) <= frame(10 downto 1);
-- shift in from the ps2_data line
frame(10) <= ps2_data_s;
end if;
end if;
end process load_tx_data_into_frame;
-- Loads data from frame into rx_data output when data is ready
do_load_rx_data: process(clk)
begin
if(rising_edge(clk)) then
if(load_rx_data = '1') then
rx_data <= frame(8 downto 1);
end if;
end if;
end process do_load_rx_data;
end Behavioral;
|
------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the implementation of a generic bidirectional
-- ps/2 interface.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- the ps/2 protocol works.
-- http://www.computer-engineering.org/ps2protocol/
-- This module implements a generic bidirectional ps/2 interface. It can
-- be used with any ps/2 compatible device. It offers its clients a
-- convenient way to exchange data with the device. The interface
-- transparently wraps the byte to be sent into a ps/2 frame, generates
-- parity for byte and sends the frame one bit at a time to the device.
-- Similarly, when receiving data from the ps2 device, the interface
-- receives the frame, checks for parity, and extract the usefull data
-- and forwards it to the client. If an error occurs during receiving
-- or sending a byte, the client is informed by settings the err output
-- line high. This way, the client can resend the data or can issue
-- a resend command to the device.
-- The physical ps/2 interface uses 4 lines
-- For the 6-pin connector pins are assigned as follows:
-- 1 - Data
-- 2 - Not Implemented
-- 3 - Ground
-- 4 - Vcc (+5V)
-- 5 - Clock
-- 6 - Not Implemented
-- The clock line carries the device generated clock which has a
-- frequency in range 10 - 16.7 kHz (30 to 50us). When line is idle
-- it is placed in high impedance. The clock is only generated when
-- device is sending or receiving data.
-- The Data and Clock lines are both open-collector with pullup
-- resistors to Vcc. An "open-collector" interface has two possible
-- states: low('0') or high impedance('Z').
-- When device wants to send a byte, it pulls the clock line low and the
-- host(i.e. this interfaces) recognizes that the device is sending data
-- When the host wants to send data, it maeks a request to send. This
-- is done by holding the clock line low for at least 100us, then with
-- the clock line low, the data line is brought low. Next the clock line
-- is released (placed in high impedance). The devices begins generating
-- clock signal on clock line.
-- When receiving data, bits are read from the data line (ps2_data) on
-- the falling edge of the clock (ps2_clk). When sending data, the
-- device reads the bits from the data line on the rising edge of the
-- clock.
-- A frame for sending a byte is comprised of 11 bits as shown bellow:
-- bits 10 9 8 7 6 5 4 3 2 1 0
-- -------------------------------------------------------------
-- | STOP| PAR | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | START |
-- -------------------------------------------------------------
-- STOP - stop bit, always '1'
-- PAR - parity bit, odd parity for the 8 data bits.
-- - select in such way that the number of bits of '1' in the data
-- - bits together with parity bit is odd.
-- D0-7 - data bits.
-- START - start bit, always '0'
--
-- Frame is sent bit by bit starting with the least significant bit
-- (starting bit) and is received the same way. This is done, when
-- receiving, by shifting the frame register to the left when a bit
-- is available and placing the bit on data line on the most significant
-- bit. This way the first bit sent will reach the least significant bit
-- of the frame when all the bits have been received. When sending data
-- the least significant bit of the frame is placed on the data line
-- and the frame is shifted to the right when another bit needs to be
-- sent. During the request to send, when releasing the clock line,
-- the device reads the data line and interprets the data on it as the
-- first bit of the frame. Data line is low at that time, at this is the
-- way the start bit('0') is sent. Because of this, when sending, only
-- 10 shifts of the frame will be made.
-- While the interface is sending or receiving data, the busy output
-- signal goes high. When interface is idle, busy is low.
-- After sending all the bits in the frame, the device must acknowledge
-- the data sent. This is done by the host releasing and data line
-- (clock line is already released) after the last bit is sent. The
-- devices brings the data line and the clock line low, in this order,
-- to acknowledge the data. If data line is high when clock line goes
-- low after last bit, the device did not acknowledge the data and
-- err output is set.
-- A FSM is used to manage the transitions the set all the command
-- signals. States that begin with "rx_" are used to receive data
-- from device and states begining with "tx_" are used to send data
-- to the device.
-- For the parity bit, a ROM holds the parity bit for all possible
-- data (256 possible values, since 8 bits of data). The ROM has
-- dimensions 256x1bit. For obtaining the parity bit of a value,
-- the bit at the data value address is read. Ex: to find the parity
-- bit of 174, the bit at address 174 is read.
-- For generating the necessary delay, counters are used. For example,
-- to generate the 100us delay a 14 bit counter is used that has the
-- upper limit for counting 10000. The interface is designed to run
-- at 100MHz. Thus, 10000x10ns = 100us.
-----------------------------------------------------------------------
-- If using the interface at different frequency than 100MHz, adjusting
-- the delay counters is necessary!!!
-----------------------------------------------------------------------
-- Clock line(ps2_clk) and data line(ps2_data) are passed through a
-- debouncer for the transitions of the clock and data to be clean.
-- Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized
-- value of the clock and data line to the system clock(clk).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- ps2_clk - inout pin, clock line of the ps/2 interface
-- ps2_data - inout pin, clock line of the ps/2 interface
-- clk - input pin, system clock signal
-- rst - input pin, system reset signal
-- tx_data - input pin, 8 bits, from client
-- - data to be sent to the device
-- write - input pin, from client
-- - should be active for one clock period when then
-- - client wants to send data to the device and
-- - data to be sent is valid on tx_data
-- rx_data - output pin, 8 bits, to client
-- - data received from device
-- read - output pin, to client
-- - active for one clock period when new data is
-- - available from device
-- busy - output pin, to client
-- - active while sending or receiving data.
-- err - output pin, to client
-- - active for one clock period when an error occurred
-- - during sending or receiving.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the ps2interface entity declaration
-- read above for behavioral description and port definitions.
entity ps2interface is
port(
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
clk : in std_logic;
rst : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
write : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
read : out std_logic;
busy : out std_logic;
err : out std_logic
);
-- forces the extraction of distributed ram for
-- the parityrom memory.
-- please remove if block ram is preffered.
attribute rom_extract : string;
attribute rom_extract of ps2interface: entity is "yes";
attribute rom_style : string;
attribute rom_style of ps2interface: entity is "distributed";
end ps2interface;
architecture Behavioral of ps2interface is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- Values are valid for a 100MHz clk. Please adjust for other
-- frequencies if necessary!
-- upper limit for 100us delay counter.
-- 10000 * 10ns = 100us
constant DELAY_100US : std_logic_vector(13 downto 0):= "10011100010000";
-- 10000 clock periods
-- upper limit for 20us delay counter.
-- 2000 * 10ns = 20us
constant DELAY_20US : std_logic_vector(10 downto 0) := "11111010000";
-- 2000 clock periods
-- upper limit for 63clk delay counter.
constant DELAY_63CLK : std_logic_vector(5 downto 0) := "111111";
-- 63 clock periods
-- delay from debouncing ps2_clk and ps2_data signals
constant DEBOUNCE_DELAY : std_logic_vector(3 downto 0) := "1111";
-- number of bits in a frame
constant NUMBITS: std_logic_vector(3 downto 0) := "1011"; -- 11
-- parity bit position in frame
constant PARITY_BIT: positive := 9;
-- (odd) parity bit ROM
-- Used instead of logic because this way speed is far greater
-- 256x1bit rom
-- If the odd parity bit for a 8 bits number, x, is needed
-- the bit at address x is the parity bit.
type ROM is array(0 to 255) of std_logic;
constant parityrom : ROM := (
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1'
);
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- 14 bits counter
-- max value DELAY_100US
-- used to wait 100us
signal delay_100us_count: std_logic_vector(13 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_20US
-- used to wait 20us
signal delay_20us_count: std_logic_vector(10 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_63CLK
-- used to wait 63 clock periods
signal delay_63clk_count: std_logic_vector(5 downto 0) :=
(others => '0');
-- done signal for the couters above
-- when a counter reaches max value,the corresponding done signal is set
signal delay_100us_done, delay_20us_done, delay_63clk_done: std_logic;
-- enable signal for 100us delay counter
signal delay_100us_counter_enable: std_logic := '0';
-- enable signal for 20us delay counter
signal delay_20us_counter_enable : std_logic := '0';
-- enable signal for 63clk delay counter
signal delay_63clk_counter_enable: std_logic := '0';
-- synchronzed input for ps2_clk and ps2_data
signal ps2_clk_s,ps2_data_s: std_logic := '1';
-- control the output of ps2_clk and ps2_data
-- if 1 then corresponding signal (ps2_clk or ps2_data) is
-- put in high impedance ('Z').
signal ps2_clk_h,ps2_data_h: std_logic := '1';
-- states of the FSM for controlling the communcation with the device
-- states that begin with "rx_" are used when receiving data
-- states that begin with "tx_" are used when transmiting data
type fsm_state is
(
idle,rx_clk_h,rx_clk_l,rx_down_edge,rx_error_parity,rx_data_ready,
tx_force_clk_l,tx_bring_data_down,tx_release_clk,
tx_first_wait_down_edge,tx_clk_l,tx_wait_up_edge,tx_clk_h,
tx_wait_up_edge_before_ack,tx_wait_ack,tx_received_ack,
tx_error_no_ack
);
-- the signal that holds the current state of the FSM
-- implicitly state is idle.
signal state: fsm_state := idle;
-- register that holds the frame received or the one to be sent.
-- Its contents are shifted in from the bus one bit at a time
-- from left to right when receiving data and are shifted on the
-- bus (ps2_data) one bit at a time to the right when sending data
signal frame: std_logic_vector(10 downto 0) := (others => '0');
-- how many bits have been sent or received.
signal bit_count: std_logic_vector(3 downto 0) := (others => '0');
-- when active the bit counter is reset.
signal reset_bit_count: std_logic := '0';
-- when active the contents of the frame is shifted to the right
-- and the most significant bit of frame is loaded with ps2_data.
signal shift_frame: std_logic := '0';
-- parity of the byte that was received from the device.
-- must match the parity bit received, else error occurred.
signal rx_parity: std_logic := '0';
-- parity bit that is sent with the frame, representing the
-- odd parity of the byte currently being sent
signal tx_parity: std_logic := '0';
-- when active, frame is loaded with the start bit, data on
-- tx_data, parity bit (tx_parity) and stop bit
-- this frame will be sent to the device.
signal load_tx_data: std_logic := '0';
-- when active bits 8 downto 1 from frame are loaded into
-- rx_data register. This is the byte received from the device.
signal load_rx_data: std_logic := '0';
-- intermediary signals used to debounce the inputs ps2_clk and ps2_data
signal ps2_clk_clean,ps2_data_clean: std_logic := '1';
-- debounce counter for the ps2_clk input and the ps2_data input.
signal clk_count,data_count: std_logic_vector(3 downto 0);
-- last value on ps2_clk and ps2_data.
signal clk_inter,data_inter: std_logic := '1';
begin
---------------------------------------------------------------------
-- FLAGS and PS2 CLOCK AND DATA LINES
---------------------------------------------------------------------
-- clean ps2_clk signal (debounce)
-- note that this introduces a delay in ps2_clk of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_clk is different
-- from the last value, then reset counter
-- and retain value
if(ps2_clk /= clk_inter) then
clk_inter <= ps2_clk;
clk_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(clk_count = DEBOUNCE_DELAY) then
ps2_clk_clean <= clk_inter;
-- ps2_clk did not change, but counter did not
-- reach limit. Increment counter
else
clk_count <= clk_count + 1;
end if;
end if;
end process;
-- clean ps2_data signal (debounce)
-- note that this introduces a delay in ps2_data of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_data is different
-- from the last value, then reset counter
-- and retain value
if(ps2_data /= data_inter) then
data_inter <= ps2_data;
data_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(data_count = DEBOUNCE_DELAY) then
ps2_data_clean <= data_inter;
-- ps2_data did not change, but counter did not
-- reach limit. Increment counter
else
data_count <= data_count + 1;
end if;
end if;
end process;
-- Synchronize ps2 entries
ps2_clk_s <= ps2_clk_clean when rising_edge(clk);
ps2_data_s <= ps2_data_clean when rising_edge(clk);
-- Assign parity from frame bits 8 downto 1, this is the parity
-- that should be received inside the frame on PARITY_BIT position
rx_parity <= parityrom(conv_integer(frame(8 downto 1)))
when rising_edge(clk);
-- The parity for the data to be sent
tx_parity <= parityrom(conv_integer(tx_data)) when rising_edge(clk);
-- Force ps2_clk to '0' if ps2_clk_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_clk <= 'Z' when ps2_clk_h = '1' else '0';
-- Force ps2_data to '0' if ps2_data_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_data <= 'Z' when ps2_data_h = '1' else '0';
-- Control busy flag. Interface is not busy while in idle state.
busy <= '0' when state = idle else '1';
-- reset the bit counter when in idle state.
reset_bit_count <= '1' when state = idle else '0';
-- Control shifting of the frame
-- When receiving from device, data is read
-- on the falling edge of ps2_clk
-- When sending to device, data is read by device
-- on the rising edge of ps2_clk
shift_frame <= '1' when state = rx_down_edge or
state = tx_clk_l else
'0';
---------------------------------------------------------------------
-- FINITE STATE MACHINE
---------------------------------------------------------------------
-- For the current state establish next state
-- and give necessary commands
manage_fsm: process(clk,rst,state,ps2_clk_s,ps2_data_s,write,tx_data,
bit_count,rx_parity,frame,delay_100us_done,
delay_20us_done,delay_63clk_done)
begin
-- if reset occurs, go to idle state.
if(rst = '1') then
state <= idle;
elsif(rising_edge(clk)) then
-- default values for these signals
-- ensures signals are reset to default value
-- when coditions for their activation are no
-- longer applied (transition to other state,
-- where signal should not be active)
-- Idle value for ps2_clk and ps2_data is 'Z'
ps2_clk_h <= '1';
ps2_data_h <= '1';
load_tx_data <= '0';
load_rx_data <= '0';
read <= '0';
err <= '0';
case state is
-- wait for the device to begin a transmission
-- by pulling the clock line low and go to state
-- rx_down_edge or, if write is high, the
-- client of this interface wants to send a byte
-- to the device and a transition is made to state
-- tx_force_clk_l
when idle =>
if(ps2_clk_s = '0') then
state <= rx_down_edge;
elsif(write = '1') then
state <= tx_force_clk_l;
else
state <= idle;
end if;
-- ps2_clk is high, check if all the bits have been read
-- if, last bit read, check parity, and if parity ok
-- load received data into rx_data.
-- else if more bits left, then wait for the ps2_clk to
-- go low
when rx_clk_h =>
if(bit_count = NUMBITS) then
if(not (rx_parity = frame(PARITY_BIT))) then
state <= rx_error_parity;
else
load_rx_data <= '1';
state <= rx_data_ready;
end if;
elsif(ps2_clk_s = '0') then
state <= rx_down_edge;
else
state <= rx_clk_h;
end if;
-- data must be read into frame in this state
-- the ps2_clk just transitioned from high to low
when rx_down_edge =>
state <= rx_clk_l;
-- ps2_clk line is low, wait for it to go high
when rx_clk_l =>
if(ps2_clk_s = '1') then
state <= rx_clk_h;
else
state <= rx_clk_l;
end if;
-- parity bit received is invalid
-- signal error and go back to idle.
when rx_error_parity =>
err <= '1';
state <= idle;
-- parity bit received was good
-- set read signal for the client to know
-- a new byte was received and is available on rx_data
when rx_data_ready =>
read <= '1';
state <= idle;
-- the client wishes to transmit a byte to the device
-- this is done by holding ps2_clk down for at least 100us
-- bringing down ps2_data, wait 20us and then releasing
-- the ps2_clk.
-- This constitutes a request to send command.
-- In this state, the ps2_clk line is held down and
-- the counter for waiting 100us is eanbled.
-- when the counter reached upper limit, transition
-- to tx_bring_data_down
when tx_force_clk_l =>
load_tx_data <= '1';
ps2_clk_h <= '0';
if(delay_100us_done = '1') then
state <= tx_bring_data_down;
else
state <= tx_force_clk_l;
end if;
-- with the ps2_clk line low bring ps2_data low
-- wait for 20us and then go to tx_release_clk
when tx_bring_data_down =>
-- keep clock line low
ps2_clk_h <= '0';
-- set data line low
-- when clock is released in the next state
-- the device will read bit 0 on data line
-- and this bit represents the start bit.
ps2_data_h <= '0'; -- start bit = '0'
if(delay_20us_done = '1') then
state <= tx_release_clk;
else
state <= tx_bring_data_down;
end if;
-- release the ps2_clk line
-- keep holding data line low
when tx_release_clk =>
ps2_clk_h <= '1';
-- must maintain data low,
-- otherwise will be released by default value
ps2_data_h <= '0';
state <= tx_first_wait_down_edge;
-- state is necessary because the clock signal
-- is not released instantaneously and, because of debounce,
-- delay is even greater.
-- Wait 63 clock periods for the clock line to release
-- then if clock is low then go to tx_clk_l
-- else wait until ps2_clk goes low.
when tx_first_wait_down_edge =>
ps2_data_h <= '0';
if(delay_63clk_done = '1') then
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_first_wait_down_edge;
end if;
else
state <= tx_first_wait_down_edge;
end if;
-- place the least significant bit from frame
-- on the data line
-- During this state the frame is shifted one
-- bit to the right
when tx_clk_l =>
ps2_data_h <= frame(0);
state <= tx_wait_up_edge;
-- wait for the clock to go high
-- this is the edge on which the device reads the data
-- on ps2_data.
-- keep holding ps2_data on frame(0) because else
-- will be released by default value.
-- Check if sent the last bit and if so, release data line
-- and go to state that wait for acknowledge
when tx_wait_up_edge =>
ps2_data_h <= frame(0);
-- NUMBITS - 1 because first (start bit = 0) bit was read
-- when the clock line was released in the request to
-- send command (see tx_bring_data_down state).
if(bit_count = NUMBITS-1) then
ps2_data_h <= '1';
state <= tx_wait_up_edge_before_ack;
-- if more bits to send, wait for the up edge
-- of ps2_clk
elsif(ps2_clk_s = '1') then
state <= tx_clk_h;
else
state <= tx_wait_up_edge;
end if;
-- ps2_clk is released, wait for down edge
-- and go to tx_clk_l when arrived
when tx_clk_h =>
ps2_data_h <= frame(0);
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_clk_h;
end if;
-- release ps2_data and wait for rising edge of ps2_clk
-- once this occurs, transition to tx_wait_ack
when tx_wait_up_edge_before_ack =>
ps2_data_h <= '1';
if(ps2_clk_s = '1') then
state <= tx_wait_ack;
else
state <= tx_wait_up_edge_before_ack;
end if;
-- wait for the falling edge of the clock line
-- if data line is low when this occurs, the
-- ack is received
-- else if data line is high, the device did not
-- acknowledge the transimission
when tx_wait_ack =>
if(ps2_clk_s = '0') then
if(ps2_data_s = '0') then
-- acknowledge received
state <= tx_received_ack;
else
-- acknowledge not received
state <= tx_error_no_ack;
end if;
else
state <= tx_wait_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
when tx_received_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
state <= idle;
else
state <= tx_received_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
-- signal error for not receiving ack
when tx_error_no_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
err <= '1';
state <= idle;
else
state <= tx_error_no_ack;
end if;
-- if invalid transition occurred, signal error and
-- go back to idle state
when others =>
err <= '1';
state <= idle;
end case;
end if;
end process manage_fsm;
---------------------------------------------------------------------
-- DELAY COUNTERS
---------------------------------------------------------------------
-- Enable the 100us counter only when state is tx_force_clk_l
delay_100us_counter_enable <= '1' when state = tx_force_clk_l else '0';
-- Counter for a 100us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_100us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_100us_counter_enable = '1') then
if(delay_100us_count = (DELAY_100US)) then
delay_100us_count <= delay_100us_count;
delay_100us_done <= '1';
else
delay_100us_count <= delay_100us_count + 1;
delay_100us_done <= '0';
end if;
else
delay_100us_count <= (others => '0');
delay_100us_done <= '0';
end if;
end if;
end process delay_100us_counter;
-- Enable the 20us counter only when state is tx_bring_data_down
delay_20us_counter_enable <= '1' when state = tx_bring_data_down else '0';
-- Counter for a 20us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_20us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_20us_counter_enable = '1') then
if(delay_20us_count = (DELAY_20US)) then
delay_20us_count <= delay_20us_count;
delay_20us_done <= '1';
else
delay_20us_count <= delay_20us_count + 1;
delay_20us_done <= '0';
end if;
else
delay_20us_count <= (others => '0');
delay_20us_done <= '0';
end if;
end if;
end process delay_20us_counter;
-- Enable the 63clk counter only when state is tx_first_wait_down_edge
delay_63clk_counter_enable <= '1' when state = tx_first_wait_down_edge else '0';
-- Counter for a 63 clock periods delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_63clk_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_63clk_counter_enable = '1') then
if(delay_63clk_count = (DELAY_63CLK)) then
delay_63clk_count <= delay_63clk_count;
delay_63clk_done <= '1';
else
delay_63clk_count <= delay_63clk_count + 1;
delay_63clk_done <= '0';
end if;
else
delay_63clk_count <= (others => '0');
delay_63clk_done <= '0';
end if;
end if;
end process delay_63clk_counter;
---------------------------------------------------------------------
-- BIT COUNTER AND FRAME SHIFTING LOGIC
---------------------------------------------------------------------
-- counts the number of bits shifted into the frame
-- or out of the frame.
bit_counter: process(clk)
begin
if(rising_edge(clk)) then
if(reset_bit_count = '1') then
bit_count <= (others => '0');
elsif(shift_frame = '1') then
bit_count <= bit_count + 1;
end if;
end if;
end process bit_counter;
-- shifts frame with one bit to right when shift_frame is acitve
-- and loads data into frame from tx_data then load_tx_data is high
load_tx_data_into_frame: process(clk)
begin
if(rising_edge(clk)) then
if(load_tx_data = '1') then
frame(8 downto 1) <= tx_data; -- byte to send
frame(0) <= '0'; -- start bit
frame(10) <= '1'; -- stop bit
frame(9) <= tx_parity; -- parity bit
elsif(shift_frame = '1') then
-- shift right 1 bit
frame(9 downto 0) <= frame(10 downto 1);
-- shift in from the ps2_data line
frame(10) <= ps2_data_s;
end if;
end if;
end process load_tx_data_into_frame;
-- Loads data from frame into rx_data output when data is ready
do_load_rx_data: process(clk)
begin
if(rising_edge(clk)) then
if(load_rx_data = '1') then
rx_data <= frame(8 downto 1);
end if;
end if;
end process do_load_rx_data;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:06:19 11/21/2013
-- Design Name:
-- Module Name: Mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Mux is
Port(
choice : in STD_LOGIC_VECTOR (1 downto 0);
Input1 : in Int16;
Input2 : in Int16;
Input3 : in Int16;
Output : out Int16
);
end Mux;
architecture Behavioral of Mux is
begin
with choice select
Output <=
Input1 when "00",
Input2 when "01",
Input3 when "10",
Int16_Zero when others;
end Behavioral;
|
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: infrastructure.v
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:11 $
-- \ \ / \ Date Created:Tue Jun 30 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Clock generation/distribution and reset synchronization
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: infrastructure.vhd,v 1.1 2011/06/02 07:18:11 mishra Exp $
--**$Date: 2011/06/02 07:18:11 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/ip_top/infrastructure.vhd,v $
--******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library std;
use std.textio.all;
entity infrastructure is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
CLK_PERIOD : integer := 3000; -- Internal (fabric) clk period
nCK_PER_CLK : integer := 2; -- External (memory) clock period =
-- CLK_PERIOD/nCK_PER_CLK
INPUT_CLK_TYPE : string := "DIFFERENTIAL"; -- input clock type
-- "DIFFERENTIAL","SINGLE_ENDED"
MMCM_ADV_BANDWIDTH : string := "OPTIMIZED"; -- MMCM programming algorithm
CLKFBOUT_MULT_F : integer := 2; -- write PLL VCO multiplier
DIVCLK_DIVIDE : integer := 1; -- write PLL VCO divisor
CLKOUT_DIVIDE : integer := 2; -- VCO output divisor for fast
-- (memory) clocks
RST_ACT_LOW : integer := 1
);
port (
-- Clock inputs
mmcm_clk : in std_logic; -- System clock diff input
-- System reset input
sys_rst : in std_logic; -- core reset from user application
-- MMCM/IDELAYCTRL Lock status
iodelay_ctrl_rdy : in std_logic; -- IDELAYCTRL lock status
-- Clock outputs
clk_mem : out std_logic; -- 2x logic clock
clk : out std_logic; -- 1x logic clock
clk_rd_base : out std_logic; -- 2x base read clock
-- Reset outputs
rstdiv0 : out std_logic; -- Reset CLK and CLKDIV logic (incl I/O)
-- Phase Shift Interface
PSDONE : out std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic
);
end entity infrastructure;
architecture arch_infrastructure of infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on DCM lock status)
-- COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
constant RST_SYNC_NUM : integer := 15;
-- constant RST_SYNC_NUM : integer := 25;;
-- Round up for clk reset delay to ensure that CLKDIV reset deassertion
-- occurs at same time or after CLK reset deassertion (still need to
-- consider route delay - add one or two extra cycles to be sure!)
constant RST_DIV_SYNC_NUM : integer := (RST_SYNC_NUM+1)/2;
constant CLKIN1_PERIOD : real
:= real((CLKFBOUT_MULT_F * CLK_PERIOD))/
real(DIVCLK_DIVIDE * CLKOUT_DIVIDE * nCK_PER_CLK * 1000); -- in ns
constant VCO_PERIOD : integer
:= (DIVCLK_DIVIDE * CLK_PERIOD)/(CLKFBOUT_MULT_F * nCK_PER_CLK);
constant CLKOUT0_DIVIDE_F : integer := CLKOUT_DIVIDE;
constant CLKOUT1_DIVIDE : integer := CLKOUT_DIVIDE * nCK_PER_CLK;
constant CLKOUT2_DIVIDE : integer := CLKOUT_DIVIDE;
constant CLKOUT0_PERIOD : integer := VCO_PERIOD * CLKOUT0_DIVIDE_F;
constant CLKOUT1_PERIOD : integer := VCO_PERIOD * CLKOUT1_DIVIDE ;
constant CLKOUT2_PERIOD : integer := VCO_PERIOD * CLKOUT2_DIVIDE ;
signal clk_bufg : std_logic;
signal clk_mem_bufg : std_logic;
signal clk_mem_pll : std_logic;
signal clk_pll : std_logic;
signal clkfbout_pll : std_logic;
signal pll_lock : std_logic;
-- synthesis syn_maxfan = 10
signal rstdiv0_sync_r : std_logic_vector(RST_DIV_SYNC_NUM-1 downto 0);
-- synthesis syn_maxfan = 10
signal rst_tmp : std_logic;
signal sys_rst_act_hi : std_logic;
attribute syn_maxfan : integer;
attribute syn_maxfan of rstdiv0_sync_r : signal is 10 ;
begin
sys_rst_act_hi <= (not sys_rst) when(RST_ACT_LOW = 1) else (sys_rst);
--synthesis translate_off
print : process is
variable my_line : line;
begin
write(my_line, string'("############# Write Clocks MMCM_ADV Parameters #############"));
writeline(output, my_line);
write(my_line, string'("nCK_PER_CLK = "));
write(my_line, nCK_PER_CLK);
writeline(output, my_line);
write(my_line, string'("CLK_PERIOD = "));
write(my_line, CLK_PERIOD);
writeline(output, my_line);
write(my_line, string'("CLKIN1_PERIOD = "));
write(my_line, CLKIN1_PERIOD);
writeline(output, my_line);
write(my_line, string'("DIVCLK_DIVIDE = "));
write(my_line, DIVCLK_DIVIDE);
writeline(output, my_line);
write(my_line, string'("CLKFBOUT_MULT_F = "));
write(my_line, CLKFBOUT_MULT_F);
writeline(output, my_line);
write(my_line, string'("VCO_PERIOD = "));
write(my_line, VCO_PERIOD);
writeline(output, my_line);
write(my_line, string'("CLKOUT0_DIVIDE_F = "));
write(my_line, CLKOUT0_DIVIDE_F);
writeline(output, my_line);
write(my_line, string'("CLKOUT1_DIVIDE = "));
write(my_line, CLKOUT1_DIVIDE);
writeline(output, my_line);
write(my_line, string'("CLKOUT2_DIVIDE = "));
write(my_line, CLKOUT2_DIVIDE);
writeline(output, my_line);
write(my_line, string'("CLKOUT0_PERIOD = "));
write(my_line, CLKOUT0_PERIOD);
writeline(output, my_line);
write(my_line, string'("CLKOUT1_PERIOD = "));
write(my_line, CLKOUT1_PERIOD);
writeline(output, my_line);
write(my_line, string'("CLKOUT2_PERIOD = "));
write(my_line, CLKOUT2_PERIOD);
writeline(output, my_line);
write(my_line, string'("############################################################"));
writeline(output, my_line);
wait;
end process print;
--synthesis translate_on
--***************************************************************************
-- Assign global clocks:
-- 1. clk_mem : Full rate (used only for IOB)
-- 2. clk : Half rate (used for majority of internal logic)
--***************************************************************************
clk_mem <= clk_mem_bufg;
clk <= clk_bufg;
--***************************************************************************
-- Global base clock generation and distribution
--***************************************************************************
--*****************************************************************
-- NOTES ON CALCULTING PROPER VCO FREQUENCY
-- 1. VCO frequency =
-- 1/((DIVCLK_DIVIDE * CLK_PERIOD)/(CLKFBOUT_MULT_F * nCK_PER_CLK))
-- 2. VCO frequency must be in the range [800MHz, 1.2MHz] for -1 part.
-- The lower limit of 800MHz is greater than the lower supported
-- frequency of 400MHz according to the datasheet because the MMCM
-- jitter performance improves significantly when the VCO is operatin
-- above 800MHz. For speed grades faster than -1, the max VCO frequency
-- will be highe, and the multiply and divide factors can be adjusted
-- according (in general to run the VCO as fast as possible).
--*****************************************************************
u_mmcm_adv : MMCM_ADV
generic map (
BANDWIDTH => MMCM_ADV_BANDWIDTH,
CLOCK_HOLD => FALSE,
COMPENSATION => "INTERNAL",
REF_JITTER1 => 0.005,
REF_JITTER2 => 0.005,
STARTUP_WAIT => FALSE,
CLKIN1_PERIOD => CLKIN1_PERIOD,
CLKIN2_PERIOD => 10.000,
CLKFBOUT_MULT_F => real(CLKFBOUT_MULT_F),
DIVCLK_DIVIDE => DIVCLK_DIVIDE,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(CLKOUT0_DIVIDE_F),
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_PHASE => 0.000,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_PHASE => 0.000,
CLKOUT1_USE_FINE_PS => FALSE,
CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT2_PHASE => 0.000,
CLKOUT2_USE_FINE_PS => TRUE,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT3_PHASE => 0.000,
CLKOUT3_USE_FINE_PS => FALSE,
CLKOUT4_CASCADE => FALSE,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT4_PHASE => 0.000,
CLKOUT4_USE_FINE_PS => FALSE,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500,
CLKOUT5_PHASE => 0.000,
CLKOUT5_USE_FINE_PS => FALSE,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500,
CLKOUT6_PHASE => 0.000,
CLKOUT6_USE_FINE_PS => FALSE
)
port map (
CLKFBOUT => clkfbout_pll,
CLKFBOUTB => open,
CLKFBSTOPPED => open,
CLKINSTOPPED => open,
CLKOUT0 => clk_mem_pll,
CLKOUT0B => open,
CLKOUT1 => clk_pll,
CLKOUT1B => open,
CLKOUT2 => clk_rd_base, -- Performance path for inner columns
CLKOUT2B => open,
CLKOUT3 => open, -- Performance path for outer columns
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
DO => open,
DRDY => open,
LOCKED => pll_lock,
PSDONE => PSDONE,
CLKFBIN => clkfbout_pll,
CLKIN1 => mmcm_clk,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => x"0000",
DWE => '0',
PSCLK => clk_bufg,
PSEN => PSEN,
PSINCDEC => PSINCDEC,
PWRDWN => '0',
RST => sys_rst_act_hi
);
u_bufg_clk0 : BUFG
port map (
O => clk_mem_bufg,
I => clk_mem_pll
);
u_bufg_clkdiv0 : BUFG
port map (
O => clk_bufg,
I => clk_pll
);
--***************************************************************************
-- RESET SYNCHRONIZATION DESCRIPTION:
-- Various resets are generated to ensure that:
-- 1. All resets are synchronously deasserted with respect to the clock
-- domain they are interfacing to. There are several different clock
-- domains - each one will receive a synchronized reset.
-- 2. The reset deassertion order starts with deassertion of SYS_RST,
-- followed by deassertion of resets for various parts of the design
-- (see "RESET ORDER" below) based on the lock status of MMCMs.
-- RESET ORDER:
-- 1. User deasserts SYS_RST
-- 2. Reset MMCM and IDELAYCTRL
-- 3. Wait for MMCM and IDELAYCTRL to lock
-- 4. Release reset for all I/O primitives and internal logic
-- OTHER NOTES:
-- 1. Asynchronously assert reset. This way we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers
-- to prevent initial bus contention). Reset deassertion is synchronous.
--***************************************************************************
--*****************************************************************
-- CLK and CLKDIV logic reset
--*****************************************************************
-- Wait for both PLL's and IDELAYCTRL to lock
rst_tmp <= sys_rst_act_hi or (not pll_lock) or (not iodelay_ctrl_rdy);
process(clk_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rstdiv0_sync_r <= (others => '1') after (TCQ)*1 ps;
elsif(clk_bufg'event and clk_bufg = '1') then
rstdiv0_sync_r <= (rstdiv0_sync_r(RST_DIV_SYNC_NUM-2 downto 0) & '0') after (TCQ)*1 ps;
end if;
end process;
rstdiv0 <= rstdiv0_sync_r(RST_DIV_SYNC_NUM-1);
end architecture arch_infrastructure;
|
---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
--library UNISIM; --May need to uncomment for ModelSim
--use UNISIM.vcomponents.all; --May need to uncomment for ModelSim
--use UNISIM.all; --May need to uncomment for ModelSim
entity reg_bank is
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
begin
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
intr_enable_reg, data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "00000";
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0);
end if;
end if;
intr_enable <= intr_enable_reg;
end process;
--------------------------------------------------------------
---- Pick only ONE of the dual-port RAM implementations below!
--------------------------------------------------------------
-- Option #1
-- One tri-port RAM, two read-ports, one write-port
-- 32 registers 32-bits wide
-- tri_port_mem:
-- if memory_type = "TRI_PORT_X" generate
ram_proc: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
variable tri_port_ram : ram_type := (others => ZERO);
begin
data_out1 <= tri_port_ram(conv_integer(addr_read1));
data_out2 <= tri_port_ram(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
tri_port_ram(conv_integer(addr_write)) := reg_dest_new;
end if;
end if;
end process;
-- end generate; --tri_port_mem
-- Option #2
-- Two dual-port RAMs, each with one read-port and one write-port
-- dual_port_mem:
-- if memory_type = "DUAL_PORT_" generate
-- ram_proc2: process(clk, addr_read1, addr_read2,
-- addr_write, reg_dest_new, write_enable)
-- variable dual_port_ram1 : ram_type := (others => ZERO);
-- variable dual_port_ram2 : ram_type := (others => ZERO);
-- begin
-- data_out1 <= dual_port_ram1(conv_integer(addr_read1));
-- data_out2 <= dual_port_ram2(conv_integer(addr_read2));
-- if rising_edge(clk) then
-- if write_enable = '1' then
-- dual_port_ram1(conv_integer(addr_write)) := reg_dest_new;
-- dual_port_ram2(conv_integer(addr_write)) := reg_dest_new;
-- end if;
-- end if;
-- end process;
-- end generate; --dual_port_mem
end; --architecture ram_block
|
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