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package arith1 is
function div(x, y : integer) return integer;
function div(x, y : real) return real;
function div(x : integer; y : real) return real;
function exp(x : real; y : integer) return real;
function exp(x, y : integer) return integer;
function neg(x : integer) return integer;
function neg(x : real) return real;
function cast(x : real) return integer;
function abz(x : integer) return integer;
function abz(x : real) return real;
function modd(x, y : integer) return integer;
function remm(x, y : integer) return integer;
end package;
package body arith1 is
function div(x, y : integer) return integer is
begin
return x / y;
end function;
function div(x, y : real) return real is
begin
return x / y;
end function;
function div(x : integer; y : real) return real is
begin
return real(x) / y;
end function;
function exp(x : real; y : integer) return real is
begin
return x ** y;
end function;
function exp(x, y : integer) return integer is
begin
return x ** y;
end function;
function neg(x : integer) return integer is
begin
return -x;
end function;
function neg(x : real) return real is
begin
return -x;
end function;
function cast(x : real) return integer is
begin
return integer(x);
end function;
function abz(x : integer) return integer is
begin
return abs x;
end function;
function abz(x : real) return real is
begin
return abs x;
end function;
function modd(x, y : integer) return integer is
begin
return x mod y;
end function;
function remm(x, y : integer) return integer is
begin
return x rem y;
end function;
end package body;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
-- pragma translate_off
use altera_mf.altpll;
-- pragma translate_on
entity clkgen_de2 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of clkgen_de2 is
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "ZERO_DELAY_BUFFER",
compensate_clock => "CLK2",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= clkout(2);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "NORMAL",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= '0';
end generate;
end;
|
entity bug is
port(data: out integer);
end entity bug;
architecture arc of bug is
begin
end architecture arc;
entity bug_sim is
end entity bug_sim;
architecture sim of bug_sim is
signal data: natural;
begin
u0: entity work.bug
port map(data => data);
end architecture sim;
|
entity bug is
port(data: out integer);
end entity bug;
architecture arc of bug is
begin
end architecture arc;
entity bug_sim is
end entity bug_sim;
architecture sim of bug_sim is
signal data: natural;
begin
u0: entity work.bug
port map(data => data);
end architecture sim;
|
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`protect end_protected
|
----------------------------------------------------------------------
-- brdRstClk (for EmCraft SoC FG896 Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end brdLexSwx;
----------------------------------------------------------------------
architecture rtl of brdLexSwx is
begin
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
o_lex <= '0';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
o_pbx <= '1';
end rtl; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:16 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_2048_0_sim_netlist.vhdl
-- Design : bram_2048_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
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INIT_00 => X"3F3D3B39373533312F2D2B29272523211F1D1B19171513110F0D0B0907050301",
INIT_01 => X"7F7D7B79777573716F6D6B69676563615F5D5B59575553514F4D4B4947454341",
INIT_02 => X"BFBDBBB9B7B5B3B1AFADABA9A7A5A3A19F9D9B99979593918F8D8B8987858381",
INIT_03 => X"FFFDFBF9F7F5F3F1EFEDEBE9E7E5E3E1DFDDDBD9D7D5D3D1CFCDCBC9C7C5C3C1",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(13 downto 3) => addra(10 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 8) => B"00000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1) => '0',
DIPADIP(0) => dina(8),
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1),
DOPADOP(0) => douta(8),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena,
ENBWREN => '0',
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 10 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 10 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => addra(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 13) => B"0000000000000000000",
DIADI(12 downto 8) => dina(10 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => dina(5 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 16),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\,
DOADO(12 downto 8) => douta(10 downto 6),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5 downto 0) => douta(5 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 2),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
douta(8 downto 0) => douta(8 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 10 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 10 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(10 downto 0) => dina(10 downto 0),
douta(10 downto 0) => douta(10 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
douta(8 downto 0) => douta(8 downto 0),
ena => ena,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(10 downto 0) => dina(19 downto 9),
douta(10 downto 0) => douta(19 downto 9),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 11;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 11;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 3.9373 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_2048_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_2048_0.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 2048;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 2048;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 2048;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "bram_2048_0,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 11;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 11;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.9373 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_2048_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_2048_0.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 2048;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 2048;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 2048;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => B"00000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
-- Top level entity, MARK_II SoC
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MARK_II is
port(
--rs232
uart1_rts: out std_logic:= '1';
uart1_txd: out std_logic:= '1';
uart1_dtr: out std_logic:= '1';
uart1_dcd: in std_logic;
uart1_dsr: in std_logic;
uart1_rxd: in std_logic;
uart1_cts: in std_logic;
uart1_ri: in std_logic;
--vga
vga_hs: out std_logic:= '0';
vga_vs: out std_logic:= '0';
vga_r: out std_logic_vector(2 downto 0):= "000";
vga_g: out std_logic_vector(2 downto 0):= "000";
vga_b: out std_logic_vector(1 downto 0):= "00";
--ps2 keyboard
kb_clk: in std_logic;
kb_dat: in std_logic;
--ps2 mouse
ms_clk: in std_logic;
ms_dat: in std_logic;
--debug uart
uart0_txd: out std_logic:= '1';
uart0_rxd: in std_logic;
uart0_cbus: in std_logic_vector(1 downto 0);
--ethernet
enc_int: in std_logic;
enc_cs: out std_logic:= '1';
enc_si: out std_logic:= '0';
enc_so: in std_logic;
enc_sck: out std_logic:= '0';
--audio
i2s_bck: out std_logic:= '0';
i2s_din: out std_logic:= '0';
i2s_lrck: out std_logic:= '0';
--i2c devices
scl: inout std_logic:= 'Z';
sda: inout std_logic:= 'Z';
--rtc
rtc_mfp: in std_logic;
--microSD
sd_dat: inout std_logic_vector(3 downto 0):= "ZZZZ";
sd_cmd: out std_logic:= '0';
sd_clk: out std_logic:= '0';
--flash
flash_cs: out std_logic:= '0';
flash_sck: out std_logic:= '0';
flash_so: in std_logic;
flash_si: out std_logic:= '0';
--sdram
sdram_a: out std_logic_vector(12 downto 0):= '0' & x"000";
sdram_dq: inout std_logic_vector(7 downto 0):= "ZZZZZZZZ";
sdram_ba: out std_logic_vector(1 downto 0):= "00";
sdram_ras: out std_logic:= '0';
sdram_cas: out std_logic:= '0';
sdram_we: out std_logic:= '0';
sdram_clk: out std_logic:= '0';
--expansion
ex_cmd: out std_logic_vector(3 downto 0):= x"0";
ex_dq: inout std_logic_vector(7 downto 0):= "ZZZZZZZZ";
--oscil
clk_25M: in std_logic;
clk_18M432: in std_logic;
clk_22M5792: in std_logic;
--pwrmng
pwrmng_rx: in std_logic;
pwrmng_tx: out std_logic:= '1';
pwrmng_res: in std_logic;
--misc
res: buffer std_logic:= '0'
);
end entity MARK_II;
architecture MARK_II_arch of MARK_II is
component cpu is
port(
--system interface
clk: in std_logic;
res: in std_logic;
--bus interface
address: out std_logic_vector(23 downto 0);
data_mosi: out std_logic_vector(31 downto 0);
data_miso: in std_logic_vector(31 downto 0);
we: out std_logic;
oe: out std_logic;
ack: in std_logic;
swirq: out std_logic;
--interrupts
int: in std_logic;
int_address: in std_logic_vector(23 downto 0);
int_accept: out std_logic;
int_completed: out std_logic
);
end component cpu;
component intController is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
int_req: in std_logic_vector(15 downto 0); --peripherals may request interrupt with this signal
int_accept: in std_logic; --from the CPU
int_completed: in std_logic; --from the CPU
int_cpu_address: out std_logic_vector(23 downto 0); --connect this to the CPU, this is address of ISR
int_cpu_rq: out std_logic
);
end component intController;
component rom is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address of the ROM
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic
);
end component rom;
component ram is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"; --base address of the RAM
ADDRESS_WIDE: natural := 8 --default address range
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic
);
end component ram;
component systim is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
intrq: out std_logic
);
end component systim;
component uart is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address of the GPIO
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
clk_uart: in std_logic;
rx: in std_logic;
tx: out std_logic;
intrq: out std_logic
);
end component uart;
component vga is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address of the RAM
);
port(
clk_bus: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
clk_vga: in std_logic;
h_sync: out std_logic;
v_sync: out std_logic;
red: out std_logic_vector(2 downto 0);
green: out std_logic_vector(2 downto 0);
blue: out std_logic_vector(1 downto 0)
);
end component vga;
component ps2 is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_miso: out std_logic_vector(31 downto 0);
RD: in std_logic;
ack: out std_logic;
--device
ps2clk: in std_logic;
ps2dat: in std_logic;
intrq: out std_logic
);
end component ps2;
component clkgen is
port(
res: in std_logic;
clk_ext: in std_logic;
res_out: out std_logic;
clk_sdram: out std_logic;
clk_sdram_shift: out std_logic
);
end component clkgen;
component sdram is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
--bus interface
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
-- device specific interface
clk_sdram: in std_logic;
-- sdram interface
sdram_a: out std_logic_vector(12 downto 0);
sdram_ba: out std_logic_vector(1 downto 0);
sdram_dq: inout std_logic_vector(7 downto 0);
sdram_ras: out std_logic;
sdram_cas: out std_logic;
sdram_we: out std_logic
);
end component sdram;
component timer is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
intrq: out std_logic
);
end component timer;
component lfsr is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic
);
end component lfsr;
--signal for internal bus
signal bus_address: std_logic_vector(23 downto 0);
signal bus_data_mosi, bus_data_miso: std_logic_vector(31 downto 0);
signal bus_ack, bus_WR, bus_RD: std_logic;
signal int_req: std_logic_vector(15 downto 0) := x"0000";
--signal for interconnect CPU and int controller
signal intCompleted, intAccepted: std_logic;
signal intCPUReq: std_logic;
signal intAddress: std_logic_vector(23 downto 0);
signal rom_ack, ram0_ack, ram1_ack, int_ack, systim_ack, vga_ack, uart0_ack, uart1_ack, uart2_ack, ps2_0_ack, ps2_1_ack, dram0_ack, tim0_ack, tim1_ack, tim2_ack, tim3_ack, lfsr_ack: std_logic;
signal clk_uart, clk_vga, clk_sys, clk_audio, clk_sdram: std_logic;
begin
--clk def
clk_uart <= clk_18M432;
clk_vga <= clk_25M;
clk_sys <= clk_25M;
clk_audio <= clk_22M5792;
clkgen0: clkgen
port map(pwrmng_res, clk_25M, res, clk_sdram, sdram_clk);
--CPU parts
cpu0: cpu
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
bus_ack, int_req(0), intCPUReq, intAddress, intAccepted, intCompleted
);
int0: intController
generic map(x"00010F")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
int_ack, int_req, intAccepted, intCompleted, intAddress, intCPUReq
);
systim0: systim
generic map(x"000104")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
systim_ack, int_req(1)
);
--peripherals
rom0: rom
generic map(x"000000")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
rom_ack
);
ram0: ram
generic map(x"000400", 10)
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
ram0_ack
);
uart0: uart
generic map(x"000130")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
uart0_ack, clk_uart, uart0_rxd, uart0_txd, int_req(8)
);
uart1: uart
generic map(x"000134")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
uart1_ack, clk_uart, uart1_rxd, uart1_txd, int_req(9)
);
uart2: uart
generic map(x"000138")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
uart2_ack, clk_uart, pwrmng_rx, pwrmng_tx, int_req(10)
);
vga0: vga
generic map(x"001000")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
vga_ack, clk_vga, vga_hs, vga_vs, vga_r, vga_g, vga_b
);
ps2_0: ps2
generic map(x"000106")
port map(
clk_sys, res, bus_address, bus_data_miso, bus_RD,
ps2_0_ack, kb_clk, kb_dat, int_req(11)
);
ps2_1: ps2
generic map(x"000107")
port map(
clk_sys, res, bus_address, bus_data_miso, bus_RD,
ps2_1_ack, ms_clk, ms_dat, int_req(12)
);
ram1: ram
generic map(x"100000", 13)
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
ram1_ack
);
dram0: sdram
generic map(x"800000")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
dram0_ack, clk_sdram,
sdram_a, sdram_ba, sdram_dq, sdram_ras, sdram_cas, sdram_we
);
timer0: timer
generic map(x"000140")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
tim0_ack, int_req(4)
);
timer1: timer
generic map(x"000144")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
tim1_ack, int_req(5)
);
timer2: timer
generic map(x"000148")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
tim2_ack, int_req(6)
);
timer3: timer
generic map(x"00014C")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
tim3_ack, int_req(7)
);
lfsr0: lfsr
generic map(x"00010E")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
lfsr_ack
);
bus_ack <=
rom_ack or ram0_ack or ram1_ack or int_ack or systim_ack or vga_ack or
uart0_ack or uart1_ack or uart2_ack or ps2_0_ack or ps2_1_ack or dram0_ack or
tim0_ack or tim1_ack or tim2_ack or tim3_ack or lfsr_ack;
end architecture MARK_II_arch;
|
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`protect end_protected
|
--------------------------------------------------
-- Module Name: Hex4Digs_2_SSeg - behavioral --
--------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity Hex4Digs_2_SSeg is
Port ( clock : in std_logic; -- Input clock
sw0 : in std_logic; -- Switch to control clock
incr : in std_logic_vector (3 downto 0); -- Increment digits
anodes : out std_logic_vector (3 downto 0); -- Anodes for display
cathodes : out std_logic_vector (7 downto 0)); -- Cathodes for segments
end Hex4Digs_2_SSeg;
architecture behavioral of Hex4Digs_2_SSeg is
signal dsel : std_logic_vector (1 downto 0) := "00"; -- Display select
signal hx0, hx1, hx2, hx3 : std_logic_vector (3 downto 0) := "0000"; -- Hex digits
signal sg0, sg1, sg2, sg3 : std_logic_vector (7 downto 0) := "11111111"; -- Segments
begin
-- Get 4 Hex digits and assign their segments
dig0: Hex2SSeg port map (hx0, sg0);
dig1: Hex2SSeg port map (hx1, sg1);
dig2: Hex2SSeg port map (hx2, sg2);
dig3: Hex2SSeg port map (hx3, sg3);
process (incr)
begin
if (incr(0) = '1') then
hx0 <= hx0 + 1;
end if;
if (incr(1) = '1') then
hx1 <= hx1 + 1;
end if;
if (incr(2) = '1') then
hx2 <= hx2 + 1;
end if;
if (incr(3) = '1') then
hx3 <= hx3 + 1;
end if;
end process;
process (clock) -- choose output display with dsel
begin
if (clock'event and clock = '1') then
case dsel is
when "00" =>
cathodes <= sg0;
anodes <= "0111";
when "01" =>
cathodes <= sg1;
anodes <= "1011";
when "10" =>
cathodes <= sg2;
anodes <= "1101";
when others =>
cathodes <= sg3;
anodes <= "1110";
end case;
dsel <= dsel - 1;
end if;
end process;
end behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2506.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p03n01i02506ent IS
END c07s03b04x00p03n01i02506ent;
ARCHITECTURE c07s03b04x00p03n01i02506arch OF c07s03b04x00p03n01i02506ent IS
type rec_type is
record
x : bit;
y : integer;
z : boolean;
end record;
BEGIN
TESTING: PROCESS
variable S1 :rec_type;
BEGIN
S1 := rec_type'(bit'('0'), 1, true) ;-- No_Failure_here
assert NOT(S1.x='0' and S1.y=1 and S1.z=true)
report "***PASSED TEST: c07s03b04x00p03n01i02506"
severity NOTE;
assert (S1.x='0' and S1.y=1 and S1.z=true)
report "***FAILED TEST: c07s03b04x00p03n01i02506 - Expression type does not match type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p03n01i02506arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2506.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p03n01i02506ent IS
END c07s03b04x00p03n01i02506ent;
ARCHITECTURE c07s03b04x00p03n01i02506arch OF c07s03b04x00p03n01i02506ent IS
type rec_type is
record
x : bit;
y : integer;
z : boolean;
end record;
BEGIN
TESTING: PROCESS
variable S1 :rec_type;
BEGIN
S1 := rec_type'(bit'('0'), 1, true) ;-- No_Failure_here
assert NOT(S1.x='0' and S1.y=1 and S1.z=true)
report "***PASSED TEST: c07s03b04x00p03n01i02506"
severity NOTE;
assert (S1.x='0' and S1.y=1 and S1.z=true)
report "***FAILED TEST: c07s03b04x00p03n01i02506 - Expression type does not match type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p03n01i02506arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2506.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p03n01i02506ent IS
END c07s03b04x00p03n01i02506ent;
ARCHITECTURE c07s03b04x00p03n01i02506arch OF c07s03b04x00p03n01i02506ent IS
type rec_type is
record
x : bit;
y : integer;
z : boolean;
end record;
BEGIN
TESTING: PROCESS
variable S1 :rec_type;
BEGIN
S1 := rec_type'(bit'('0'), 1, true) ;-- No_Failure_here
assert NOT(S1.x='0' and S1.y=1 and S1.z=true)
report "***PASSED TEST: c07s03b04x00p03n01i02506"
severity NOTE;
assert (S1.x='0' and S1.y=1 and S1.z=true)
report "***FAILED TEST: c07s03b04x00p03n01i02506 - Expression type does not match type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p03n01i02506arch;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_64_16.vhd
-- /___/ /\ Timestamp: Mon Jul 14 16:27:30 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_64_16.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_64_16.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_16.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_16.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_64_16
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_64_16 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_64_16;
architecture STRUCTURE of fifo_generator_64_16 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal N111 : STD_LOGIC;
signal N19 : STD_LOGIC;
signal N21 : STD_LOGIC;
signal Result_0_1 : STD_LOGIC;
signal Result_1_1 : STD_LOGIC;
signal Result_2_1 : STD_LOGIC;
signal Result_3_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_13 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000014_17 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000023_18 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000056_19 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_32 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000026_33 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000081_34 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_36 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_53 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_54 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_55 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_56 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_60 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_61 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_62 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_63 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_64 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_65 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal Result : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_13;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_37;
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_13
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
D => Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_0_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => Result_1_1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_2_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_3_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_61,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_36
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_61,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_61,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_62,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_53
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_61,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_62
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_55,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_56
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_64,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_65
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_60,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_61
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_54,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_55
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_64,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_63
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_63,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_64
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_55,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_54
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_60
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_65,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_63,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_56,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_54,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_1_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => Result_2_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => Result_3_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en1 : LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_36,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb1 : LUT6
generic map(
INIT => X"303A3030003A0030"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_53,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_36,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
I5 => N111,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i_SW0 : LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
O => N19
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i : LUT5
generic map(
INIT => X"00008241"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I4 => N19,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_53,
I1 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_32
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000026 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000026_33
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000081 : LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000081_34
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000119 : LUT6
generic map(
INIT => X"AE0AAA0AAEAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_32,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000026_33,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000081_34,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000031_SW0 : LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
O => N21
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000031 : LUT5
generic map(
INIT => X"FFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I4 => N21,
O => N111
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000014 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000014_17
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000023 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000023_18
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000056 : LUT5
generic map(
INIT => X"80082002"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000056_19
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000105 : LUT6
generic map(
INIT => X"BAAAAAAA32222222"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_15,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000014_17,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000023_18,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000056_19,
I5 => N111,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_0_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP :
RAMB36SDP_EXP
generic map(
DO_REG => 0,
EN_ECC_READ => FALSE,
EN_ECC_SCRUB => FALSE,
EN_ECC_WRITE => FALSE,
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT => X"000000000000000000",
SRVAL => X"000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_MODE => "SAFE",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
RDENU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
RDENL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
WRENU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WRENL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SSRU => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
SSRL => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
RDCLKU => clk,
RDCLKL => clk,
WRCLKU => clk,
WRCLKL => clk,
RDRCLKU => clk,
RDRCLKL => clk,
REGCEU => N0,
REGCEL => N0,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SBITERR_UNCONNECTED
,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DBITERR_UNCONNECTED
,
DI(63) => din(63),
DI(62) => din(62),
DI(61) => din(61),
DI(60) => din(60),
DI(59) => din(59),
DI(58) => din(58),
DI(57) => din(57),
DI(56) => din(56),
DI(55) => din(55),
DI(54) => din(54),
DI(53) => din(53),
DI(52) => din(52),
DI(51) => din(51),
DI(50) => din(50),
DI(49) => din(49),
DI(48) => din(48),
DI(47) => din(47),
DI(46) => din(46),
DI(45) => din(45),
DI(44) => din(44),
DI(43) => din(43),
DI(42) => din(42),
DI(41) => din(41),
DI(40) => din(40),
DI(39) => din(39),
DI(38) => din(38),
DI(37) => din(37),
DI(36) => din(36),
DI(35) => din(35),
DI(34) => din(34),
DI(33) => din(33),
DI(32) => din(32),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(7) => N0,
DIP(6) => N0,
DIP(5) => N0,
DIP(4) => N0,
DIP(3) => N0,
DIP(2) => N0,
DIP(1) => N0,
DIP(0) => N0,
RDADDRL(15) => N1,
RDADDRL(14) => N0,
RDADDRL(13) => N0,
RDADDRL(12) => N0,
RDADDRL(11) => N0,
RDADDRL(10) => N0,
RDADDRL(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDRL(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDRL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDRL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
RDADDRL(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_5_UNCONNECTED
,
RDADDRL(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_4_UNCONNECTED
,
RDADDRL(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_3_UNCONNECTED
,
RDADDRL(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_2_UNCONNECTED
,
RDADDRL(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_1_UNCONNECTED
,
RDADDRL(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL_0_UNCONNECTED
,
RDADDRU(14) => N0,
RDADDRU(13) => N0,
RDADDRU(12) => N0,
RDADDRU(11) => N0,
RDADDRU(10) => N0,
RDADDRU(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
RDADDRU(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
RDADDRU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
RDADDRU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
RDADDRU(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_5_UNCONNECTED
,
RDADDRU(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_4_UNCONNECTED
,
RDADDRU(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_3_UNCONNECTED
,
RDADDRU(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_2_UNCONNECTED
,
RDADDRU(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_1_UNCONNECTED
,
RDADDRU(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU_0_UNCONNECTED
,
WRADDRL(15) => N1,
WRADDRL(14) => N0,
WRADDRL(13) => N0,
WRADDRL(12) => N0,
WRADDRL(11) => N0,
WRADDRL(10) => N0,
WRADDRL(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDRL(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDRL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDRL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
WRADDRL(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_5_UNCONNECTED
,
WRADDRL(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_4_UNCONNECTED
,
WRADDRL(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_3_UNCONNECTED
,
WRADDRL(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_2_UNCONNECTED
,
WRADDRL(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_1_UNCONNECTED
,
WRADDRL(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL_0_UNCONNECTED
,
WRADDRU(14) => N0,
WRADDRU(13) => N0,
WRADDRU(12) => N0,
WRADDRU(11) => N0,
WRADDRU(10) => N0,
WRADDRU(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
WRADDRU(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
WRADDRU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
WRADDRU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
WRADDRU(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_5_UNCONNECTED
,
WRADDRU(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_4_UNCONNECTED
,
WRADDRU(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_3_UNCONNECTED
,
WRADDRU(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_2_UNCONNECTED
,
WRADDRU(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_1_UNCONNECTED
,
WRADDRU(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU_0_UNCONNECTED
,
WEU(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEU(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEL(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DO(63) => dout(63),
DO(62) => dout(62),
DO(61) => dout(61),
DO(60) => dout(60),
DO(59) => dout(59),
DO(58) => dout(58),
DO(57) => dout(57),
DO(56) => dout(56),
DO(55) => dout(55),
DO(54) => dout(54),
DO(53) => dout(53),
DO(52) => dout(52),
DO(51) => dout(51),
DO(50) => dout(50),
DO(49) => dout(49),
DO(48) => dout(48),
DO(47) => dout(47),
DO(46) => dout(46),
DO(45) => dout(45),
DO(44) => dout(44),
DO(43) => dout(43),
DO(42) => dout(42),
DO(41) => dout(41),
DO(40) => dout(40),
DO(39) => dout(39),
DO(38) => dout(38),
DO(37) => dout(37),
DO(36) => dout(36),
DO(35) => dout(35),
DO(34) => dout(34),
DO(33) => dout(33),
DO(32) => dout(32),
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_7_UNCONNECTED
,
DOP(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_6_UNCONNECTED
,
DOP(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_5_UNCONNECTED
,
DOP(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_4_UNCONNECTED
,
DOP(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_3_UNCONNECTED
,
DOP(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_2_UNCONNECTED
,
DOP(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_1_UNCONNECTED
,
DOP(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY_0_UNCONNECTED
);
end STRUCTURE;
-- synthesis translate_on
|
library verilog;
use verilog.vl_types.all;
entity R_SEQ is
port(
address : in vl_logic_vector(7 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(127 downto 0)
);
end R_SEQ;
|
library verilog;
use verilog.vl_types.all;
entity R_SEQ is
port(
address : in vl_logic_vector(7 downto 0);
clock : in vl_logic;
q : out vl_logic_vector(127 downto 0)
);
end R_SEQ;
|
package pack is
function add4(x : in integer) return integer;
end package;
package body pack is
function add4(x : in integer) return integer is
begin
return x + 4;
end function;
end package body;
-------------------------------------------------------------------------------
entity ffold is
end entity;
use work.pack.all;
architecture a of ffold is
function add1(x : in integer) return integer is
begin
return x + 1;
end function;
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
--while true loop
--end loop;
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
function case1(x : in integer) return integer is
begin
case x is
when 1 =>
return 2;
when 2 =>
return 3;
when others =>
return 5;
end case;
end function;
function adddef(x, y : in integer := 5) return integer is
begin
return x + y;
end function;
function chain1(x : string) return boolean is
variable r : boolean := false;
begin
if x = "hello" then
r := true;
end if;
return r;
end function;
function chain2(x, y : string) return boolean is
variable r : boolean := false;
begin
if chain1(x) or chain1(y) then
r := true;
end if;
return r;
end function;
signal s1 : integer := add1(5);
signal s2 : integer := add4(1);
signal s3 : integer := log2(11);
signal s4 : integer := log2(integer(real'(5.5)));
signal s5 : integer := case1(1);
signal s6 : integer := case1(7);
signal s7 : integer := adddef;
signal s8 : boolean := chain2("foo", "hello");
begin
end architecture;
|
package pack is
function add4(x : in integer) return integer;
end package;
package body pack is
function add4(x : in integer) return integer is
begin
return x + 4;
end function;
end package body;
-------------------------------------------------------------------------------
entity ffold is
end entity;
use work.pack.all;
architecture a of ffold is
function add1(x : in integer) return integer is
begin
return x + 1;
end function;
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
--while true loop
--end loop;
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
function case1(x : in integer) return integer is
begin
case x is
when 1 =>
return 2;
when 2 =>
return 3;
when others =>
return 5;
end case;
end function;
function adddef(x, y : in integer := 5) return integer is
begin
return x + y;
end function;
function chain1(x : string) return boolean is
variable r : boolean := false;
begin
if x = "hello" then
r := true;
end if;
return r;
end function;
function chain2(x, y : string) return boolean is
variable r : boolean := false;
begin
if chain1(x) or chain1(y) then
r := true;
end if;
return r;
end function;
signal s1 : integer := add1(5);
signal s2 : integer := add4(1);
signal s3 : integer := log2(11);
signal s4 : integer := log2(integer(real'(5.5)));
signal s5 : integer := case1(1);
signal s6 : integer := case1(7);
signal s7 : integer := adddef;
signal s8 : boolean := chain2("foo", "hello");
begin
end architecture;
|
package pack is
function add4(x : in integer) return integer;
end package;
package body pack is
function add4(x : in integer) return integer is
begin
return x + 4;
end function;
end package body;
-------------------------------------------------------------------------------
entity ffold is
end entity;
use work.pack.all;
architecture a of ffold is
function add1(x : in integer) return integer is
begin
return x + 1;
end function;
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
--while true loop
--end loop;
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
function case1(x : in integer) return integer is
begin
case x is
when 1 =>
return 2;
when 2 =>
return 3;
when others =>
return 5;
end case;
end function;
function adddef(x, y : in integer := 5) return integer is
begin
return x + y;
end function;
function chain1(x : string) return boolean is
variable r : boolean := false;
begin
if x = "hello" then
r := true;
end if;
return r;
end function;
function chain2(x, y : string) return boolean is
variable r : boolean := false;
begin
if chain1(x) or chain1(y) then
r := true;
end if;
return r;
end function;
signal s1 : integer := add1(5);
signal s2 : integer := add4(1);
signal s3 : integer := log2(11);
signal s4 : integer := log2(integer(real'(5.5)));
signal s5 : integer := case1(1);
signal s6 : integer := case1(7);
signal s7 : integer := adddef;
signal s8 : boolean := chain2("foo", "hello");
begin
end architecture;
|
----------------------------------------------------------------------------------
-- Company: Universidad Complutense de Madrid
-- Engineer: Hortensia Mecha
--
-- Design Name: divisor
-- Module Name: divisor - divisor_arch
-- Project Name:
-- Target Devices:
-- Description: Creación de un reloj de 1Hz a partir de
-- un clk de 100 MHz
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.ALL;
entity divisor is
port (
reset: in STD_LOGIC;
clk_entrada: in STD_LOGIC; -- reloj de entrada de la entity superior
clk_salida: out STD_LOGIC -- reloj que se utiliza en los process del programa principal
);
end divisor;
architecture divisor_arch of divisor is
SIGNAL cuenta: std_logic_vector(1 downto 0);
SIGNAL clk_aux, clk: std_logic;
begin
clk<=clk_entrada;
clk_salida<=clk_aux;
contador:
PROCESS(reset, clk)
BEGIN
IF (reset='1') THEN
cuenta<= (OTHERS=>'0');
clk_aux <= '0';
ELSIF(clk'EVENT AND clk='1') THEN
IF (cuenta="11") THEN
clk_aux <= not clk_aux;
cuenta<= (OTHERS=>'0');
ELSE
cuenta <= cuenta+'1';
END IF;
END IF;
END PROCESS contador;
end divisor_arch;
|
----------------------------------------------------------------------------------
-- Company: Universidad Complutense de Madrid
-- Engineer: Hortensia Mecha
--
-- Design Name: divisor
-- Module Name: divisor - divisor_arch
-- Project Name:
-- Target Devices:
-- Description: Creación de un reloj de 1Hz a partir de
-- un clk de 100 MHz
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.ALL;
entity divisor is
port (
reset: in STD_LOGIC;
clk_entrada: in STD_LOGIC; -- reloj de entrada de la entity superior
clk_salida: out STD_LOGIC -- reloj que se utiliza en los process del programa principal
);
end divisor;
architecture divisor_arch of divisor is
SIGNAL cuenta: std_logic_vector(1 downto 0);
SIGNAL clk_aux, clk: std_logic;
begin
clk<=clk_entrada;
clk_salida<=clk_aux;
contador:
PROCESS(reset, clk)
BEGIN
IF (reset='1') THEN
cuenta<= (OTHERS=>'0');
clk_aux <= '0';
ELSIF(clk'EVENT AND clk='1') THEN
IF (cuenta="11") THEN
clk_aux <= not clk_aux;
cuenta<= (OTHERS=>'0');
ELSE
cuenta <= cuenta+'1';
END IF;
END IF;
END PROCESS contador;
end divisor_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pixel_gen is port (
clk : in std_logic;
x0,y0 : in std_logic_vector(17 downto 0);
overflow_bits : out std_logic_vector(19 downto 0));
end pixel_gen;
architecture Behavioral of pixel_gen is
type pipe_state is (s1,s2,s3);
signal state : pipe_state := s1;
component mandelbrot_pipeline4 port(
clk : IN std_logic;
ov_in : in std_logic;
x,y,x0,y0 : IN std_logic_vector(17 downto 0);
x_out,y_out,x0_out,y0_out : OUT std_logic_vector(17 downto 0);
ov : out std_logic_vector (3 downto 0));
end component;
signal x_in,y_in,x0_in,y0_in : std_logic_vector(17 downto 0);
signal x_out,y_out,x0_out,y0_out : std_logic_vector(17 downto 0);
signal ov_in : std_logic;
signal ov_out : std_logic_vector (3 downto 0);
-- latches
signal x_out1, y_out1, x0_out1, y0_out1 : std_logic_vector(17 downto 0);
signal x_out2, y_out2, x0_out2, y0_out2 : std_logic_vector(17 downto 0);
signal x_out3, y_out3, x0_out3, y0_out3 : std_logic_vector(17 downto 0);
signal x_out4, y_out4, x0_out4, y0_out4 : std_logic_vector(17 downto 0);
signal ov1, ov2, ov3, ov4 : std_logic_vector (3 downto 0);
signal overflow : std_logic_vector (19 downto 0);
begin
overflow_bits <= overflow;
pipeline : mandelbrot_pipeline4 port map(
clk => clk,
ov_in => ov_in,
x => x_in, y => y_in, x0 => x0_in, y0 => y0_in, -- inputs
x_out => x_out, y_out => y_out, ov => ov_out, -- outputs
x0_out=> x0_out, y0_out => y0_out
);
piped : process (clk) begin
if rising_edge(clk) then
case state is
when s1 =>
x_in <= x0; y_in <= y0; x0_in <= x0; y0_in <= y0; ov_in <= '0';
x_out1 <= x_out; y_out1 <= y_out; x0_out1 <= x0_out; y0_out1 <= y0_out;
ov1 <= ov_out;
state <= s2;
when s2 =>
x_in <= x_out1; y_in <= y_out1; x0_in <= x0_out1; y0_in <= y0_out1; ov_in <= ov1(0);
x_out2<= x_out; y_out2 <= y_out; x0_out2 <= x0_out;y0_out2 <= y0_out;
ov2 <= ov_out;
state <= s3;
when s3 =>
x_in <= x_out2; y_in <= y_out2; x0_in <= x0_out2; y0_in <= y0_out2; ov_in <= ov2(0);
overflow <= ov1 & ov2 & ov_out & x"00";
state <= s1;
end case;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:21 08/16/2010
-- Design Name:
-- Module Name: C:/Users/georgecuris/Desktop/Folders/FPGA/Projects/Current Projects/Systems/testytest/top_level_TB.vhd
-- Project Name: testytest
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: top_level
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY top_level_TB IS
END top_level_TB;
ARCHITECTURE behavior OF top_level_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top_level
PORT(
mclk : IN std_logic;
rst : IN std_logic;
CQ_write_en : IN std_logic;
VQ_read_en : IN std_logic;
memory_address_bus : INOUT std_logic_vector(22 downto 0);
memory_data_bus : INOUT std_logic_vector(15 downto 0);
anodes : OUT std_logic_vector(3 downto 0);
decoder_out : OUT std_logic_vector(6 downto 0);
RAM_oe : OUT std_logic;
RAM_we : OUT std_logic;
RAM_adv : OUT std_logic;
RAM_clk : OUT std_logic;
RAM_ub : OUT std_logic;
RAM_lb : OUT std_logic;
RAM_ce : OUT std_logic;
RAM_cre : OUT std_logic;
RAM_wait : IN std_logic;
LEDs : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal mclk : std_logic := '0';
signal rst : std_logic := '0';
signal CQ_write_en : std_logic := '0';
signal VQ_read_en : std_logic := '0';
signal RAM_wait : std_logic := '0';
--BiDirs
signal memory_address_bus : std_logic_vector(22 downto 0);
signal memory_data_bus : std_logic_vector(15 downto 0);
--Outputs
signal anodes : std_logic_vector(3 downto 0);
signal decoder_out : std_logic_vector(6 downto 0);
signal RAM_oe : std_logic;
signal RAM_we : std_logic;
signal RAM_adv : std_logic;
signal RAM_clk : std_logic;
signal RAM_ub : std_logic;
signal RAM_lb : std_logic;
signal RAM_ce : std_logic;
signal RAM_cre : std_logic;
signal LEDs : std_logic_vector(7 downto 0);
-- Clock period definitions
constant mclk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top_level PORT MAP (
mclk => mclk,
rst => rst,
CQ_write_en => CQ_write_en,
VQ_read_en => VQ_read_en,
memory_address_bus => memory_address_bus,
memory_data_bus => memory_data_bus,
anodes => anodes,
decoder_out => decoder_out,
RAM_oe => RAM_oe,
RAM_we => RAM_we,
RAM_adv => RAM_adv,
RAM_clk => RAM_clk,
RAM_ub => RAM_ub,
RAM_lb => RAM_lb,
RAM_ce => RAM_ce,
RAM_cre => RAM_cre,
RAM_wait => RAM_wait,
LEDs => LEDs
);
-- Clock process definitions
mclk_process :process
begin
mclk <= '1';
wait for mclk_period/2;
mclk <= '0';
wait for mclk_period/2;
end process;
RAM_wait_proc :process
begin
RAM_wait <= '0';
wait for 980 ns;
RAM_wait <= '0';
wait for 35 ns;
RAM_wait <= '1';
wait for 40 ns;
RAM_wait <= '0';
wait;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 300 ns;
rst <= '0';
wait;
end process;
END;
|
entity FIFO is
port (
port1 : in std_logic;
port1 : out std_logic;
port1 : inout std_logic bus;
port1 : buffer std_logic bus := "asdf";
port1 : linkage std_logic := "asdf";
port1 : std_logic
);
end entity FIFO;
entity FIFO is
port (
signal port1 : in std_logic;
signal port1 : out std_logic;
signal port1 : inout std_logic;
signal port1 : buffer std_logic;
signal port1 : linkage std_logic;
signal port1 : std_logic
);
end entity FIFO;
|
-- VHDL Entity lab10_WriteBack_Stage_lib.lab10_WriteBack_Stage.symbol
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 01:13:04 04/23/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY lab10_WriteBack_Stage IS
PORT(
Control : IN std_logic;
Dest : IN std_logic_vector (3 DOWNTO 0);
Value : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic;
Control_toRegFile : OUT std_logic;
Dest_toRegFile : OUT std_logic_vector (3 DOWNTO 0);
Value_toRegFile : OUT std_logic_vector (15 DOWNTO 0)
);
-- Declarations
END lab10_WriteBack_Stage ;
--
-- VHDL Architecture lab10_WriteBack_Stage_lib.lab10_WriteBack_Stage.struct
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 01:13:04 04/23/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE struct OF lab10_WriteBack_Stage IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL load_enable : std_logic;
-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
SIGNAL mw_U_0reg_cval : std_logic_vector(15 DOWNTO 0) := "0000000000000000";
-- ModuleWare signal declarations(v1.12) for instance 'U_1' of 'adff'
SIGNAL mw_U_1reg_cval : std_logic_vector(3 DOWNTO 0) := "0000";
-- ModuleWare signal declarations(v1.12) for instance 'U_2' of 'adff'
SIGNAL mw_U_2reg_cval : std_logic := '0';
BEGIN
-- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
Value_toRegFile <= mw_U_0reg_cval;
u_0seq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load_enable = '1') THEN
mw_U_0reg_cval <= Value;
END IF;
END IF;
END PROCESS u_0seq_proc;
-- ModuleWare code(v1.12) for instance 'U_1' of 'adff'
Dest_toRegFile <= mw_U_1reg_cval;
u_1seq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load_enable = '1') THEN
mw_U_1reg_cval <= Dest;
END IF;
END IF;
END PROCESS u_1seq_proc;
-- ModuleWare code(v1.12) for instance 'U_2' of 'adff'
Control_toRegFile <= mw_U_2reg_cval;
u_2seq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load_enable = '1') THEN
mw_U_2reg_cval <= Control;
END IF;
END IF;
END PROCESS u_2seq_proc;
-- ModuleWare code(v1.12) for instance 'ONE' of 'constval'
load_enable <= '1';
-- Instance port mappings.
END struct;
|
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
architecture behavioral of dynshreg_i_f is
constant USE_INFERRED : boolean := true;
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
begin
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
|
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
architecture behavioral of dynshreg_i_f is
constant USE_INFERRED : boolean := true;
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
begin
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
|
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
architecture behavioral of dynshreg_i_f is
constant USE_INFERRED : boolean := true;
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
begin
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
|
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
architecture behavioral of dynshreg_i_f is
constant USE_INFERRED : boolean := true;
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
begin
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
|
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
architecture behavioral of dynshreg_i_f is
constant USE_INFERRED : boolean := true;
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
begin
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
|
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
architecture behavioral of dynshreg_i_f is
constant USE_INFERRED : boolean := true;
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
begin
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2712.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p01n01i02712ent IS
END c13s04b02x00p01n01i02712ent;
ARCHITECTURE c13s04b02x00p01n01i02712arch OF c13s04b02x00p01n01i02712ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( (2#11#=3)
and (7#66#=48)
and (12#BB#=143)
and (16#FF#=255))
report "***PASSED TEST: c13s04b02x00p01n01i02712"
severity NOTE;
assert ( (2#11#=3)
and (7#66#=48)
and (12#BB#=143)
and (16#FF#=255))
report "***FAILED TEST: c13s04b02x00p01n01i02712 - Correct based literal test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p01n01i02712arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2712.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p01n01i02712ent IS
END c13s04b02x00p01n01i02712ent;
ARCHITECTURE c13s04b02x00p01n01i02712arch OF c13s04b02x00p01n01i02712ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( (2#11#=3)
and (7#66#=48)
and (12#BB#=143)
and (16#FF#=255))
report "***PASSED TEST: c13s04b02x00p01n01i02712"
severity NOTE;
assert ( (2#11#=3)
and (7#66#=48)
and (12#BB#=143)
and (16#FF#=255))
report "***FAILED TEST: c13s04b02x00p01n01i02712 - Correct based literal test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p01n01i02712arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2712.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p01n01i02712ent IS
END c13s04b02x00p01n01i02712ent;
ARCHITECTURE c13s04b02x00p01n01i02712arch OF c13s04b02x00p01n01i02712ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( (2#11#=3)
and (7#66#=48)
and (12#BB#=143)
and (16#FF#=255))
report "***PASSED TEST: c13s04b02x00p01n01i02712"
severity NOTE;
assert ( (2#11#=3)
and (7#66#=48)
and (12#BB#=143)
and (16#FF#=255))
report "***FAILED TEST: c13s04b02x00p01n01i02712 - Correct based literal test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p01n01i02712arch;
|
entity FIFO is
end entity;
entity FIFO is
end entity;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for mdec_core
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:56:34 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\nreset2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: mdec_core-rtl-conf-c.vhd,v 1.1 2004/04/06 10:46:43 wig Exp $
-- $Date: 2004/04/06 10:46:43 $
-- $Log: mdec_core-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:46:43 wig
-- Adding result/nreset2
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration mdec_core_rtl_conf / mdec_core
--
configuration mdec_core_rtl_conf of mdec_core is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for aou_i1 : aou
-- __I_NO_CONFIG_VERILOG -- use configuration work.aou_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for cgu_i1 : cgu
-- __I_NO_CONFIG_VERILOG -- use configuration work.cgu_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for cpu_i1 : cpu
-- __I_NO_CONFIG_VERILOG -- use configuration work.cpu_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for ema_i1 : ema
-- __I_NO_CONFIG_VERILOG -- use configuration work.ema_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
for ga_i1 : ga
use configuration work.ga_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for i58_io_logic_i1 : i58_io_logic
-- __I_NO_CONFIG_VERILOG -- use configuration work.i58_io_logic_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for ifu_top_i1 : ifu_top
-- __I_NO_CONFIG_VERILOG -- use configuration work.ifu_top_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for pdu_i1 : pdu
-- __I_NO_CONFIG_VERILOG -- use configuration work.pdu_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
-- __I_NO_CONFIG_VERILOG --for tsd_top_i1 : tsd_top
-- __I_NO_CONFIG_VERILOG -- use configuration work.tsd_top_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
for vip_i1 : vip
use configuration work.vip_rtl_c0;
end for;
for vo_i1 : vo
use configuration work.vo_rtl_conf;
end for;
for vor_i1 : vor
use configuration work.vor_rtl_conf;
end for;
end for;
end mdec_core_rtl_conf;
--
-- End of Generated Configuration mdec_core_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:axi_nic:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_axi_nic_10_1 IS
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END sys_axi_nic_10_1;
ARCHITECTURE sys_axi_nic_10_1_arch OF sys_axi_nic_10_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_axi_nic_10_1_arch: ARCHITECTURE IS "yes";
COMPONENT nic_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER;
C_S00_AXI_ADDR_WIDTH : INTEGER;
USE_1K_NOT_4K_FIFO_DEPTH : BOOLEAN
);
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END COMPONENT nic_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF RX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF RX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF TX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF TX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF TX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RREADY";
BEGIN
U0 : nic_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 5,
USE_1K_NOT_4K_FIFO_DEPTH => false
)
PORT MAP (
RX_DATA => RX_DATA,
RX_VALID => RX_VALID,
RX_READY => RX_READY,
TX_DATA => TX_DATA,
TX_VALID => TX_VALID,
TX_READY => TX_READY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready
);
END sys_axi_nic_10_1_arch;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: elinkInterface_package
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
--!
package elinkInterface_package is
constant elinkRate : integer := 80; -- 80 / 160 / 320 / 640 Mbps (*640 Mbps receiver only, data source is an 8b10b encoded data from emulator)
-- if elinkRate is 160 MHz, only {00-direct data} or {01-8b10b encoding} is supported
constant elinkEncoding : std_logic_vector(1 downto 0) := "01"; -- 00-direct data / 01-8b10b encoding / 10-HDLC encoding
--
constant packet_size : std_logic_vector(7 downto 0) := x"0a";
end package elinkInterface_package ; |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: elinkInterface_package
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
--!
package elinkInterface_package is
constant elinkRate : integer := 80; -- 80 / 160 / 320 / 640 Mbps (*640 Mbps receiver only, data source is an 8b10b encoded data from emulator)
-- if elinkRate is 160 MHz, only {00-direct data} or {01-8b10b encoding} is supported
constant elinkEncoding : std_logic_vector(1 downto 0) := "01"; -- 00-direct data / 01-8b10b encoding / 10-HDLC encoding
--
constant packet_size : std_logic_vector(7 downto 0) := x"0a";
end package elinkInterface_package ; |
-- Nancy Minderman
-- [email protected]
-- This file makes extensive use of Altera template structures.
-- This file is the top-level file for lab 1 winter 2014 for version 12.1sp1 on Windows 7
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward declares
-- it.
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity tracking_camera is
port
(
-- Input ports and 50 MHz Clock
KEY : in std_logic_vector (0 downto 0);
SW : in std_logic_vector (1 downto 0);
CLOCK_50 : in std_logic;
GPIO_0 : out std_logic_vector (0 downto 0);
-- Green leds on board
LEDG : out DE2_LED_GREEN;
-- LCD on board
LCD_BLON : out std_logic;
LCD_ON : out std_logic;
LCD_DATA : inout DE2_LCD_DATA_BUS;
LCD_RS : out std_logic;
LCD_EN : out std_logic;
LCD_RW : out std_logic;
-- SDRAM on board
--DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- SRAM on board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic
);
end tracking_camera;
architecture structure of tracking_camera is
-- Declarations (optional)
component tracking_camera_system is
port (
servo_pwm_0_conduit_end_0_export : out std_logic;
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
altpll_0_c0_clk : out std_logic; -- clk
green_leds_external_connection_export : out DE2_LED_GREEN; -- export
switch_external_connection_export : in std_logic := 'X'; -- export
switch_0_external_connection_export : in std_logic := 'X';
sram_0_external_interface_DQ : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out DE2_SRAM_ADDR_BUS; -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic; -- WE_N
character_lcd_0_external_interface_DATA : inout DE2_LCD_DATA_BUS := (others => 'X'); -- DATA
character_lcd_0_external_interface_ON : out std_logic; -- ON
character_lcd_0_external_interface_BLON : out std_logic; -- BLON
character_lcd_0_external_interface_EN : out std_logic; -- EN
character_lcd_0_external_interface_RS : out std_logic; -- RS
character_lcd_0_external_interface_RW : out std_logic -- RW
);
end component tracking_camera_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component tracking_camera_system
port map (
servo_pwm_0_conduit_end_0_export => GPIO_0(0),
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
altpll_0_c0_clk => DRAM_CLK,
green_leds_external_connection_export => LEDG,
switch_external_connection_export => SW(0),
switch_0_external_connection_export => SW(1),
sram_0_external_interface_DQ => SRAM_DQ,
sram_0_external_interface_ADDR => SRAM_ADDR,
sram_0_external_interface_LB_N => SRAM_LB_N,
sram_0_external_interface_UB_N => SRAM_UB_N,
sram_0_external_interface_CE_N => SRAM_CE_N,
sram_0_external_interface_OE_N => SRAM_OE_N,
sram_0_external_interface_WE_N => SRAM_WE_N,
character_lcd_0_external_interface_DATA => LCD_DATA,
character_lcd_0_external_interface_ON => LCD_ON,
character_lcd_0_external_interface_BLON => LCD_BLON,
character_lcd_0_external_interface_EN => LCD_EN,
character_lcd_0_external_interface_RS => LCD_RS,
character_lcd_0_external_interface_RW => LCD_RW
);
end structure;
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
end DE2_CONSTANTS;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity arpServerWrapper is
generic ( keyLength : integer := 32;
valueLength : integer := 48);
Port ( aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
myMacAddress : in std_logic_vector(47 downto 0);
myIpAddress : in std_logic_vector(31 downto 0);
axi_arp_to_arp_slice_tvalid : out std_logic;
axi_arp_to_arp_slice_tready : in std_logic;
axi_arp_to_arp_slice_tdata : out std_logic_vector(63 downto 0);
axi_arp_to_arp_slice_tkeep : out std_logic_vector(7 downto 0);
axi_arp_to_arp_slice_tlast : out std_logic;
axis_arp_lookup_reply_TVALID : out std_logic;
axis_arp_lookup_reply_TREADY : in std_logic;
axis_arp_lookup_reply_TDATA : out std_logic_vector(55 downto 0);
axi_arp_slice_to_arp_tvalid : in std_logic;
axi_arp_slice_to_arp_tready : out std_logic;
axi_arp_slice_to_arp_tdata : in std_logic_vector(63 downto 0);
axi_arp_slice_to_arp_tkeep : in std_logic_vector(7 downto 0);
axi_arp_slice_to_arp_tlast : in std_logic;
axis_arp_lookup_request_TVALID : in std_logic;
axis_arp_lookup_request_TREADY : out std_logic;
axis_arp_lookup_request_TDATA : in std_logic_vector(keyLength - 1 downto 0));
end arpServerWrapper;
architecture Structural of arpServerWrapper is
COMPONENT arp_server_ip
PORT(regIpAddress_V : IN std_logic_vector(31 downto 0);
myMacAddress_V : in std_logic_vector(47 downto 0);
aresetn : IN std_logic;
aclk : IN std_logic;
macUpdate_resp_TDATA : IN std_logic_vector(55 downto 0);
macUpdate_resp_TREADY : OUT std_logic;
macUpdate_resp_TVALID : IN std_logic;
macUpdate_req_TDATA : OUT std_logic_vector(87 downto 0);
macUpdate_req_TREADY : IN std_logic;
macUpdate_req_TVALID : OUT std_logic;
macLookup_resp_TDATA : IN std_logic_vector(55 downto 0);
macLookup_resp_TREADY : OUT std_logic;
macLookup_resp_TVALID : IN std_logic;
macLookup_req_TDATA : OUT std_logic_vector(39 downto 0);
macLookup_req_TREADY : IN std_logic;
macLookup_req_TVALID : OUT std_logic;
macIpEncode_rsp_TDATA : OUT std_logic_vector(55 downto 0);
macIpEncode_rsp_TREADY : IN std_logic;
macIpEncode_rsp_TVALID : OUT std_logic;
arpDataOut_TLAST : OUT std_logic;
arpDataOut_TKEEP : OUT std_logic_vector(7 downto 0);
arpDataOut_TDATA : OUT std_logic_vector(63 downto 0);
arpDataOut_TREADY : IN std_logic;
arpDataOut_TVALID : OUT std_logic;
macIpEncode_req_TDATA : IN std_logic_vector(31 downto 0);
macIpEncode_req_TREADY : OUT std_logic;
macIpEncode_req_TVALID : IN std_logic;
arpDataIn_TLAST : IN std_logic;
arpDataIn_TKEEP : IN std_logic_vector(7 downto 0);
arpDataIn_TDATA : IN std_logic_vector(63 downto 0);
arpDataIn_TREADY : OUT std_logic;
arpDataIn_TVALID : IN std_logic);
END COMPONENT;
signal invertedReset : std_logic;
signal lup_req_TVALID : std_logic;
signal lup_req_TREADY : std_logic;
signal lup_req_TDATA : std_logic_vector(39 downto 0);
signal lup_req_TDATA_im: std_logic_vector(keyLength downto 0);
signal lup_rsp_TVALID : std_logic;
signal lup_rsp_TREADY : std_logic;
signal lup_rsp_TDATA : std_logic_vector(55 downto 0);
signal lup_rsp_TDATA_im: std_logic_vector(valueLength downto 0);
signal upd_req_TVALID : std_logic;
signal upd_req_TREADY : std_logic;
signal upd_req_TDATA : std_logic_vector(87 downto 0);
signal upd_req_TDATA_im: std_logic_vector((keyLength + valueLength) + 1 downto 0);
signal upd_rsp_TVALID : std_logic;
signal upd_rsp_TREADY : std_logic;
signal upd_rsp_TDATA : std_logic_vector(55 downto 0);
signal upd_rsp_TDATA_im: std_logic_vector(valueLength + 1 downto 0);
begin
lup_req_TDATA_im <= lup_req_TDATA(32 downto 0);
lup_rsp_TDATA <= "0000000" & lup_rsp_TDATA_im;
upd_req_TDATA_im <= upd_req_TDATA((keyLength + valueLength) + 1 downto 0);
upd_rsp_TDATA <= "000000" & upd_rsp_TDATA_im;
invertedReset <= NOT aresetn;
-- SmartCam Wrapper
SmartCamCtl_inst: entity work.SmartCamCtlArp--(behavior)
port map(clk => aclk,
rst => invertedReset,
led0 => open,
led1 => open,
cam_ready => open,
lup_req_valid => lup_req_TVALID,
lup_req_ready => lup_req_TREADY,
lup_req_din => lup_req_TDATA_im,
lup_rsp_valid => lup_rsp_TVALID,
lup_rsp_ready => lup_rsp_TREADY,
lup_rsp_dout => lup_rsp_TDATA_im,
upd_req_valid => upd_req_TVALID,
upd_req_ready => upd_req_TREADY,
upd_req_din => upd_req_TDATA_im,
upd_rsp_valid => upd_rsp_TVALID,
upd_rsp_ready => upd_rsp_TREADY,
upd_rsp_dout => upd_rsp_TDATA_im,
debug => open);
-- ARP Server
arp_server_inst: arp_server_ip
port map (regIpAddress_V => myIpAddress,
myMacAddress_V => myMacAddress,
arpDataIn_TVALID => axi_arp_slice_to_arp_tvalid,
arpDataIn_TREADY => axi_arp_slice_to_arp_tready,
arpDataIn_TDATA => axi_arp_slice_to_arp_tdata,
arpDataIn_TKEEP => axi_arp_slice_to_arp_tkeep,
arpDataIn_TLAST => axi_arp_slice_to_arp_tlast,
macIpEncode_req_TVALID => axis_arp_lookup_request_TVALID,
macIpEncode_req_TREADY => axis_arp_lookup_request_TREADY,
macIpEncode_req_TDATA => axis_arp_lookup_request_TDATA,
arpDataOut_TVALID => axi_arp_to_arp_slice_tvalid,
arpDataOut_TREADY => axi_arp_to_arp_slice_tready,
arpDataOut_TDATA => axi_arp_to_arp_slice_tdata,
arpDataOut_TKEEP => axi_arp_to_arp_slice_tkeep,
arpDataOut_TLAST => axi_arp_to_arp_slice_tlast,
macIpEncode_rsp_TVALID => axis_arp_lookup_reply_TVALID,
macIpEncode_rsp_TREADY => axis_arp_lookup_reply_TREADY,
macIpEncode_rsp_TDATA => axis_arp_lookup_reply_TDATA,
macLookup_req_TVALID => lup_req_TVALID,
macLookup_req_TREADY => lup_req_TREADY,
macLookup_req_TDATA => lup_req_TDATA,
macLookup_resp_TVALID => lup_rsp_TVALID,
macLookup_resp_TREADY => lup_rsp_TREADY,
macLookup_resp_TDATA => lup_rsp_TDATA,
macUpdate_req_TVALID => upd_req_TVALID,
macUpdate_req_TREADY => upd_req_TREADY,
macUpdate_req_TDATA => upd_req_TDATA,
macUpdate_resp_TVALID => upd_rsp_TVALID,
macUpdate_resp_TREADY => upd_rsp_TREADY,
macUpdate_resp_TDATA => upd_rsp_TDATA,
aclk => aclk,
aresetn => aresetn);
end Structural; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity arpServerWrapper is
generic ( keyLength : integer := 32;
valueLength : integer := 48);
Port ( aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
myMacAddress : in std_logic_vector(47 downto 0);
myIpAddress : in std_logic_vector(31 downto 0);
axi_arp_to_arp_slice_tvalid : out std_logic;
axi_arp_to_arp_slice_tready : in std_logic;
axi_arp_to_arp_slice_tdata : out std_logic_vector(63 downto 0);
axi_arp_to_arp_slice_tkeep : out std_logic_vector(7 downto 0);
axi_arp_to_arp_slice_tlast : out std_logic;
axis_arp_lookup_reply_TVALID : out std_logic;
axis_arp_lookup_reply_TREADY : in std_logic;
axis_arp_lookup_reply_TDATA : out std_logic_vector(55 downto 0);
axi_arp_slice_to_arp_tvalid : in std_logic;
axi_arp_slice_to_arp_tready : out std_logic;
axi_arp_slice_to_arp_tdata : in std_logic_vector(63 downto 0);
axi_arp_slice_to_arp_tkeep : in std_logic_vector(7 downto 0);
axi_arp_slice_to_arp_tlast : in std_logic;
axis_arp_lookup_request_TVALID : in std_logic;
axis_arp_lookup_request_TREADY : out std_logic;
axis_arp_lookup_request_TDATA : in std_logic_vector(keyLength - 1 downto 0));
end arpServerWrapper;
architecture Structural of arpServerWrapper is
COMPONENT arp_server_ip
PORT(regIpAddress_V : IN std_logic_vector(31 downto 0);
myMacAddress_V : in std_logic_vector(47 downto 0);
aresetn : IN std_logic;
aclk : IN std_logic;
macUpdate_resp_TDATA : IN std_logic_vector(55 downto 0);
macUpdate_resp_TREADY : OUT std_logic;
macUpdate_resp_TVALID : IN std_logic;
macUpdate_req_TDATA : OUT std_logic_vector(87 downto 0);
macUpdate_req_TREADY : IN std_logic;
macUpdate_req_TVALID : OUT std_logic;
macLookup_resp_TDATA : IN std_logic_vector(55 downto 0);
macLookup_resp_TREADY : OUT std_logic;
macLookup_resp_TVALID : IN std_logic;
macLookup_req_TDATA : OUT std_logic_vector(39 downto 0);
macLookup_req_TREADY : IN std_logic;
macLookup_req_TVALID : OUT std_logic;
macIpEncode_rsp_TDATA : OUT std_logic_vector(55 downto 0);
macIpEncode_rsp_TREADY : IN std_logic;
macIpEncode_rsp_TVALID : OUT std_logic;
arpDataOut_TLAST : OUT std_logic;
arpDataOut_TKEEP : OUT std_logic_vector(7 downto 0);
arpDataOut_TDATA : OUT std_logic_vector(63 downto 0);
arpDataOut_TREADY : IN std_logic;
arpDataOut_TVALID : OUT std_logic;
macIpEncode_req_TDATA : IN std_logic_vector(31 downto 0);
macIpEncode_req_TREADY : OUT std_logic;
macIpEncode_req_TVALID : IN std_logic;
arpDataIn_TLAST : IN std_logic;
arpDataIn_TKEEP : IN std_logic_vector(7 downto 0);
arpDataIn_TDATA : IN std_logic_vector(63 downto 0);
arpDataIn_TREADY : OUT std_logic;
arpDataIn_TVALID : IN std_logic);
END COMPONENT;
signal invertedReset : std_logic;
signal lup_req_TVALID : std_logic;
signal lup_req_TREADY : std_logic;
signal lup_req_TDATA : std_logic_vector(39 downto 0);
signal lup_req_TDATA_im: std_logic_vector(keyLength downto 0);
signal lup_rsp_TVALID : std_logic;
signal lup_rsp_TREADY : std_logic;
signal lup_rsp_TDATA : std_logic_vector(55 downto 0);
signal lup_rsp_TDATA_im: std_logic_vector(valueLength downto 0);
signal upd_req_TVALID : std_logic;
signal upd_req_TREADY : std_logic;
signal upd_req_TDATA : std_logic_vector(87 downto 0);
signal upd_req_TDATA_im: std_logic_vector((keyLength + valueLength) + 1 downto 0);
signal upd_rsp_TVALID : std_logic;
signal upd_rsp_TREADY : std_logic;
signal upd_rsp_TDATA : std_logic_vector(55 downto 0);
signal upd_rsp_TDATA_im: std_logic_vector(valueLength + 1 downto 0);
begin
lup_req_TDATA_im <= lup_req_TDATA(32 downto 0);
lup_rsp_TDATA <= "0000000" & lup_rsp_TDATA_im;
upd_req_TDATA_im <= upd_req_TDATA((keyLength + valueLength) + 1 downto 0);
upd_rsp_TDATA <= "000000" & upd_rsp_TDATA_im;
invertedReset <= NOT aresetn;
-- SmartCam Wrapper
SmartCamCtl_inst: entity work.SmartCamCtlArp--(behavior)
port map(clk => aclk,
rst => invertedReset,
led0 => open,
led1 => open,
cam_ready => open,
lup_req_valid => lup_req_TVALID,
lup_req_ready => lup_req_TREADY,
lup_req_din => lup_req_TDATA_im,
lup_rsp_valid => lup_rsp_TVALID,
lup_rsp_ready => lup_rsp_TREADY,
lup_rsp_dout => lup_rsp_TDATA_im,
upd_req_valid => upd_req_TVALID,
upd_req_ready => upd_req_TREADY,
upd_req_din => upd_req_TDATA_im,
upd_rsp_valid => upd_rsp_TVALID,
upd_rsp_ready => upd_rsp_TREADY,
upd_rsp_dout => upd_rsp_TDATA_im,
debug => open);
-- ARP Server
arp_server_inst: arp_server_ip
port map (regIpAddress_V => myIpAddress,
myMacAddress_V => myMacAddress,
arpDataIn_TVALID => axi_arp_slice_to_arp_tvalid,
arpDataIn_TREADY => axi_arp_slice_to_arp_tready,
arpDataIn_TDATA => axi_arp_slice_to_arp_tdata,
arpDataIn_TKEEP => axi_arp_slice_to_arp_tkeep,
arpDataIn_TLAST => axi_arp_slice_to_arp_tlast,
macIpEncode_req_TVALID => axis_arp_lookup_request_TVALID,
macIpEncode_req_TREADY => axis_arp_lookup_request_TREADY,
macIpEncode_req_TDATA => axis_arp_lookup_request_TDATA,
arpDataOut_TVALID => axi_arp_to_arp_slice_tvalid,
arpDataOut_TREADY => axi_arp_to_arp_slice_tready,
arpDataOut_TDATA => axi_arp_to_arp_slice_tdata,
arpDataOut_TKEEP => axi_arp_to_arp_slice_tkeep,
arpDataOut_TLAST => axi_arp_to_arp_slice_tlast,
macIpEncode_rsp_TVALID => axis_arp_lookup_reply_TVALID,
macIpEncode_rsp_TREADY => axis_arp_lookup_reply_TREADY,
macIpEncode_rsp_TDATA => axis_arp_lookup_reply_TDATA,
macLookup_req_TVALID => lup_req_TVALID,
macLookup_req_TREADY => lup_req_TREADY,
macLookup_req_TDATA => lup_req_TDATA,
macLookup_resp_TVALID => lup_rsp_TVALID,
macLookup_resp_TREADY => lup_rsp_TREADY,
macLookup_resp_TDATA => lup_rsp_TDATA,
macUpdate_req_TVALID => upd_req_TVALID,
macUpdate_req_TREADY => upd_req_TREADY,
macUpdate_req_TDATA => upd_req_TDATA,
macUpdate_resp_TVALID => upd_rsp_TVALID,
macUpdate_resp_TREADY => upd_rsp_TREADY,
macUpdate_resp_TDATA => upd_rsp_TDATA,
aclk => aclk,
aresetn => aresetn);
end Structural; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity mem_bus_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req : in t_mem_req;
resp : out t_mem_resp );
end mem_bus_slave_bfm;
architecture bfm of mem_bus_slave_bfm is
shared variable mem : h_mem_object;
signal bound : boolean := false;
signal pipe : t_mem_req_array(0 to g_latency-1) := (others => c_mem_req_init);
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_model(mem_bus_slave_bfm'path_name, g_name, mem);
bound <= true;
wait;
end process;
resp.rack <= '1' when bound and req.request='1' else '0';
resp.rack_tag <= req.tag when bound and req.request='1' else (others => '0');
process(clock)
begin
if rising_edge(clock) then
pipe(0 to g_latency-2) <= pipe(1 to g_latency-1);
pipe(g_latency-1) <= req;
resp.dack_tag <= (others => '0');
resp.data <= (others => '0');
if bound then
if pipe(0).request='1' then
if pipe(0).read_writen='1' then
resp.dack_tag <= pipe(0).tag;
resp.data <= read_memory_8(mem, "000000" & std_logic_vector(pipe(0).address));
else
write_memory_8(mem, "000000" & std_logic_vector(pipe(0).address), pipe(0).data);
end if;
end if;
end if;
end if;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity mem_bus_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req : in t_mem_req;
resp : out t_mem_resp );
end mem_bus_slave_bfm;
architecture bfm of mem_bus_slave_bfm is
shared variable mem : h_mem_object;
signal bound : boolean := false;
signal pipe : t_mem_req_array(0 to g_latency-1) := (others => c_mem_req_init);
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_model(mem_bus_slave_bfm'path_name, g_name, mem);
bound <= true;
wait;
end process;
resp.rack <= '1' when bound and req.request='1' else '0';
resp.rack_tag <= req.tag when bound and req.request='1' else (others => '0');
process(clock)
begin
if rising_edge(clock) then
pipe(0 to g_latency-2) <= pipe(1 to g_latency-1);
pipe(g_latency-1) <= req;
resp.dack_tag <= (others => '0');
resp.data <= (others => '0');
if bound then
if pipe(0).request='1' then
if pipe(0).read_writen='1' then
resp.dack_tag <= pipe(0).tag;
resp.data <= read_memory_8(mem, "000000" & std_logic_vector(pipe(0).address));
else
write_memory_8(mem, "000000" & std_logic_vector(pipe(0).address), pipe(0).data);
end if;
end if;
end if;
end if;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity mem_bus_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req : in t_mem_req;
resp : out t_mem_resp );
end mem_bus_slave_bfm;
architecture bfm of mem_bus_slave_bfm is
shared variable mem : h_mem_object;
signal bound : boolean := false;
signal pipe : t_mem_req_array(0 to g_latency-1) := (others => c_mem_req_init);
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_model(mem_bus_slave_bfm'path_name, g_name, mem);
bound <= true;
wait;
end process;
resp.rack <= '1' when bound and req.request='1' else '0';
resp.rack_tag <= req.tag when bound and req.request='1' else (others => '0');
process(clock)
begin
if rising_edge(clock) then
pipe(0 to g_latency-2) <= pipe(1 to g_latency-1);
pipe(g_latency-1) <= req;
resp.dack_tag <= (others => '0');
resp.data <= (others => '0');
if bound then
if pipe(0).request='1' then
if pipe(0).read_writen='1' then
resp.dack_tag <= pipe(0).tag;
resp.data <= read_memory_8(mem, "000000" & std_logic_vector(pipe(0).address));
else
write_memory_8(mem, "000000" & std_logic_vector(pipe(0).address), pipe(0).data);
end if;
end if;
end if;
end if;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity mem_bus_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req : in t_mem_req;
resp : out t_mem_resp );
end mem_bus_slave_bfm;
architecture bfm of mem_bus_slave_bfm is
shared variable mem : h_mem_object;
signal bound : boolean := false;
signal pipe : t_mem_req_array(0 to g_latency-1) := (others => c_mem_req_init);
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_model(mem_bus_slave_bfm'path_name, g_name, mem);
bound <= true;
wait;
end process;
resp.rack <= '1' when bound and req.request='1' else '0';
resp.rack_tag <= req.tag when bound and req.request='1' else (others => '0');
process(clock)
begin
if rising_edge(clock) then
pipe(0 to g_latency-2) <= pipe(1 to g_latency-1);
pipe(g_latency-1) <= req;
resp.dack_tag <= (others => '0');
resp.data <= (others => '0');
if bound then
if pipe(0).request='1' then
if pipe(0).read_writen='1' then
resp.dack_tag <= pipe(0).tag;
resp.data <= read_memory_8(mem, "000000" & std_logic_vector(pipe(0).address));
else
write_memory_8(mem, "000000" & std_logic_vector(pipe(0).address), pipe(0).data);
end if;
end if;
end if;
end if;
end process;
end bfm;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity mem_bus_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req : in t_mem_req;
resp : out t_mem_resp );
end mem_bus_slave_bfm;
architecture bfm of mem_bus_slave_bfm is
shared variable mem : h_mem_object;
signal bound : boolean := false;
signal pipe : t_mem_req_array(0 to g_latency-1) := (others => c_mem_req_init);
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_model(mem_bus_slave_bfm'path_name, g_name, mem);
bound <= true;
wait;
end process;
resp.rack <= '1' when bound and req.request='1' else '0';
resp.rack_tag <= req.tag when bound and req.request='1' else (others => '0');
process(clock)
begin
if rising_edge(clock) then
pipe(0 to g_latency-2) <= pipe(1 to g_latency-1);
pipe(g_latency-1) <= req;
resp.dack_tag <= (others => '0');
resp.data <= (others => '0');
if bound then
if pipe(0).request='1' then
if pipe(0).read_writen='1' then
resp.dack_tag <= pipe(0).tag;
resp.data <= read_memory_8(mem, "000000" & std_logic_vector(pipe(0).address));
else
write_memory_8(mem, "000000" & std_logic_vector(pipe(0).address), pipe(0).data);
end if;
end if;
end if;
end if;
end process;
end bfm;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_tx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle transmission of an ARP packet.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created - refactored this arp_tx module from the complete arp v0.02 module
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arp_tx is
port (
-- control signals
send_I_have : in std_logic; -- pulse will be latched
arp_entry : in arp_entry_t; -- arp target for I_have req (will be latched)
send_who_has : in std_logic; -- pulse will be latched
ip_entry : in std_logic_vector (31 downto 0); -- IP target for who_has req (will be latched)
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
tx_clk : in std_logic;
reset : in std_logic
);
end arp_tx;
architecture Behavioral of arp_tx is
type count_mode_t is (RST, INCR, HOLD);
type set_clr_t is (SET, CLR, HOLD);
type tx_state_t is (IDLE, WAIT_MAC, SEND);
type tx_mode_t is (REPLY, REQUEST);
-- state variables
signal tx_mac_chn_reqd : std_logic;
signal tx_state : tx_state_t;
signal tx_count : unsigned (7 downto 0);
signal send_I_have_reg : std_logic;
signal send_who_has_reg : std_logic;
signal I_have_target : arp_entry_t; -- latched target for "I have" request
signal who_has_target : std_logic_vector (31 downto 0); -- latched IP for "who has" request
signal tx_mode : tx_mode_t; -- what sort of tx to make
signal target : arp_entry_t; -- target to send to
-- busses
signal next_tx_state : tx_state_t;
signal tx_mode_val : tx_mode_t;
signal target_val : arp_entry_t;
-- tx control signals
signal set_tx_state : std_logic;
signal tx_count_mode : count_mode_t;
signal set_chn_reqd : set_clr_t;
signal kill_data_out_valid : std_logic;
signal set_send_I_have : set_clr_t;
signal set_send_who_has : set_clr_t;
signal set_tx_mode : std_logic;
signal set_target : std_logic;
begin
tx_combinatorial : process (
-- input signals
send_I_have, send_who_has, arp_entry, ip_entry, data_out_ready, mac_tx_granted,
our_mac_address, our_ip_address, reset,
-- state variables
tx_state, tx_count, tx_mac_chn_reqd, I_have_target, who_has_target,
send_I_have_reg, send_who_has_reg, tx_mode, target,
-- busses
next_tx_state, tx_mode_val, target_val,
-- control signals
tx_count_mode, kill_data_out_valid, set_send_I_have, set_send_who_has,
set_chn_reqd, set_tx_mode, set_target
)
begin
-- set output followers
mac_tx_req <= tx_mac_chn_reqd;
-- set combinatorial output defaults
data_out_first <= '0';
case tx_state is
when SEND =>
if data_out_ready = '1' and kill_data_out_valid = '0' then
data_out_valid <= '1';
else
data_out_valid <= '0';
end if;
when others => data_out_valid <= '0';
end case;
-- set bus defaults
next_tx_state <= IDLE;
tx_mode_val <= REPLY;
target_val.ip <= (others => '0');
target_val.mac <= (others => '1');
-- set signal defaults
set_tx_state <= '0';
tx_count_mode <= HOLD;
data_out <= x"00";
data_out_last <= '0';
set_chn_reqd <= HOLD;
kill_data_out_valid <= '0';
set_send_I_have <= HOLD;
set_send_who_has <= HOLD;
set_tx_mode <= '0';
set_target <= '0';
-- process requests in regardless of FSM state
if send_I_have = '1' then
set_send_I_have <= SET;
end if;
if send_who_has = '1' then
set_send_who_has <= SET;
end if;
-- TX FSM
case tx_state is
when IDLE =>
tx_count_mode <= RST;
if send_I_have_reg = '1' then
set_chn_reqd <= SET;
tx_mode_val <= REPLY;
set_tx_mode <= '1';
target_val <= I_have_target;
set_target <= '1';
set_send_I_have <= CLR;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
elsif send_who_has_reg = '1' then
set_chn_reqd <= SET;
tx_mode_val <= REQUEST;
set_tx_mode <= '1';
target_val.ip <= who_has_target;
target_val.mac <= (others => '1');
set_target <= '1';
set_send_who_has <= CLR;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
else
set_chn_reqd <= CLR;
end if;
when WAIT_MAC =>
tx_count_mode <= RST;
if mac_tx_granted = '1' then
next_tx_state <= SEND;
set_tx_state <= '1';
end if;
-- TODO - should handle timeout here
when SEND =>
if data_out_ready = '1' then
tx_count_mode <= INCR;
end if;
case tx_count is
when x"00" => data_out_first <= data_out_ready;
data_out <= target.mac (47 downto 40); -- target mac--data_out <= x"ff"; -- dst = broadcast
when x"01" => data_out <= target.mac (39 downto 32); --data_out <= x"ff";
when x"02" => data_out <= target.mac (31 downto 24); --data_out <= x"ff";
when x"03" => data_out <= target.mac (23 downto 16); --data_out <= x"ff";
when x"04" => data_out <= target.mac (15 downto 8); --data_out <= x"ff";
when x"05" => data_out <= target.mac (7 downto 0); --data_out <= x"ff";
when x"06" => data_out <= our_mac_address (47 downto 40); -- src = our mac
when x"07" => data_out <= our_mac_address (39 downto 32);
when x"08" => data_out <= our_mac_address (31 downto 24);
when x"09" => data_out <= our_mac_address (23 downto 16);
when x"0a" => data_out <= our_mac_address (15 downto 8);
when x"0b" => data_out <= our_mac_address (7 downto 0);
when x"0c" => data_out <= x"08"; -- pkt type = 0806 : ARP
when x"0d" => data_out <= x"06";
when x"0e" => data_out <= x"00"; -- HW type = 0001 : eth
when x"0f" => data_out <= x"01";
when x"10" => data_out <= x"08"; -- protocol = 0800 : ip
when x"11" => data_out <= x"00";
when x"12" => data_out <= x"06"; -- HW size = 06
when x"13" => data_out <= x"04"; -- prot size = 04
when x"14" => data_out <= x"00"; -- opcode =
when x"15" =>
if tx_mode = REPLY then
data_out <= x"02"; -- 02 : REPLY
else
data_out <= x"01"; -- 01 : REQ
end if;
when x"16" => data_out <= our_mac_address (47 downto 40); -- sender mac
when x"17" => data_out <= our_mac_address (39 downto 32);
when x"18" => data_out <= our_mac_address (31 downto 24);
when x"19" => data_out <= our_mac_address (23 downto 16);
when x"1a" => data_out <= our_mac_address (15 downto 8);
when x"1b" => data_out <= our_mac_address (7 downto 0);
when x"1c" => data_out <= our_ip_address (31 downto 24); -- sender ip
when x"1d" => data_out <= our_ip_address (23 downto 16);
when x"1e" => data_out <= our_ip_address (15 downto 8);
when x"1f" => data_out <= our_ip_address (7 downto 0);
when x"20" => data_out <= target.mac (47 downto 40); -- target mac
when x"21" => data_out <= target.mac (39 downto 32);
when x"22" => data_out <= target.mac (31 downto 24);
when x"23" => data_out <= target.mac (23 downto 16);
when x"24" => data_out <= target.mac (15 downto 8);
when x"25" => data_out <= target.mac (7 downto 0);
when x"26" => data_out <= target.ip (31 downto 24); -- target ip
when x"27" => data_out <= target.ip (23 downto 16);
when x"28" => data_out <= target.ip (15 downto 8);
when x"29" =>
data_out <= target.ip(7 downto 0);
data_out_last <= '1';
when x"2a" =>
kill_data_out_valid <= '1'; -- data is no longer valid
next_tx_state <= IDLE;
set_tx_state <= '1';
when others =>
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end case;
end process;
tx_sequential : process (tx_clk)
begin
if rising_edge(tx_clk) then
if reset = '1' then
-- reset state variables
tx_state <= IDLE;
tx_count <= (others => '0');
tx_mac_chn_reqd <= '0';
send_I_have_reg <= '0';
send_who_has_reg <= '0';
who_has_target <= (others => '0');
I_have_target.ip <= (others => '0');
I_have_target.mac <= (others => '0');
target.ip <= (others => '0');
target.mac <= (others => '1');
else
-- normal (non reset) processing
-- Next tx_state processing
if set_tx_state = '1' then
tx_state <= next_tx_state;
else
tx_state <= tx_state;
end if;
-- input request latching
case set_send_I_have is
when SET =>
send_I_have_reg <= '1';
I_have_target <= arp_entry;
when CLR =>
send_I_have_reg <= '0';
I_have_target <= I_have_target;
when HOLD =>
send_I_have_reg <= send_I_have_reg;
I_have_target <= I_have_target;
end case;
case set_send_who_has is
when SET =>
send_who_has_reg <= '1';
who_has_target <= ip_entry;
when CLR =>
send_who_has_reg <= '0';
who_has_target <= who_has_target;
when HOLD =>
send_who_has_reg <= send_who_has_reg;
who_has_target <= who_has_target;
end case;
-- tx mode
if set_tx_mode = '1' then
tx_mode <= tx_mode_val;
else
tx_mode <= tx_mode;
end if;
-- target latching
if set_target = '1' then
target <= target_val;
else
target <= target;
end if;
-- tx_count processing
case tx_count_mode is
when RST =>
tx_count <= x"00";
when INCR =>
tx_count <= tx_count + 1;
when HOLD =>
tx_count <= tx_count;
end case;
-- control access request to mac tx chn
case set_chn_reqd is
when SET => tx_mac_chn_reqd <= '1';
when CLR => tx_mac_chn_reqd <= '0';
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd;
end case;
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_tx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle transmission of an ARP packet.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created - refactored this arp_tx module from the complete arp v0.02 module
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arp_tx is
port (
-- control signals
send_I_have : in std_logic; -- pulse will be latched
arp_entry : in arp_entry_t; -- arp target for I_have req (will be latched)
send_who_has : in std_logic; -- pulse will be latched
ip_entry : in std_logic_vector (31 downto 0); -- IP target for who_has req (will be latched)
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
tx_clk : in std_logic;
reset : in std_logic
);
end arp_tx;
architecture Behavioral of arp_tx is
type count_mode_t is (RST, INCR, HOLD);
type set_clr_t is (SET, CLR, HOLD);
type tx_state_t is (IDLE, WAIT_MAC, SEND);
type tx_mode_t is (REPLY, REQUEST);
-- state variables
signal tx_mac_chn_reqd : std_logic;
signal tx_state : tx_state_t;
signal tx_count : unsigned (7 downto 0);
signal send_I_have_reg : std_logic;
signal send_who_has_reg : std_logic;
signal I_have_target : arp_entry_t; -- latched target for "I have" request
signal who_has_target : std_logic_vector (31 downto 0); -- latched IP for "who has" request
signal tx_mode : tx_mode_t; -- what sort of tx to make
signal target : arp_entry_t; -- target to send to
-- busses
signal next_tx_state : tx_state_t;
signal tx_mode_val : tx_mode_t;
signal target_val : arp_entry_t;
-- tx control signals
signal set_tx_state : std_logic;
signal tx_count_mode : count_mode_t;
signal set_chn_reqd : set_clr_t;
signal kill_data_out_valid : std_logic;
signal set_send_I_have : set_clr_t;
signal set_send_who_has : set_clr_t;
signal set_tx_mode : std_logic;
signal set_target : std_logic;
begin
tx_combinatorial : process (
-- input signals
send_I_have, send_who_has, arp_entry, ip_entry, data_out_ready, mac_tx_granted,
our_mac_address, our_ip_address, reset,
-- state variables
tx_state, tx_count, tx_mac_chn_reqd, I_have_target, who_has_target,
send_I_have_reg, send_who_has_reg, tx_mode, target,
-- busses
next_tx_state, tx_mode_val, target_val,
-- control signals
tx_count_mode, kill_data_out_valid, set_send_I_have, set_send_who_has,
set_chn_reqd, set_tx_mode, set_target
)
begin
-- set output followers
mac_tx_req <= tx_mac_chn_reqd;
-- set combinatorial output defaults
data_out_first <= '0';
case tx_state is
when SEND =>
if data_out_ready = '1' and kill_data_out_valid = '0' then
data_out_valid <= '1';
else
data_out_valid <= '0';
end if;
when others => data_out_valid <= '0';
end case;
-- set bus defaults
next_tx_state <= IDLE;
tx_mode_val <= REPLY;
target_val.ip <= (others => '0');
target_val.mac <= (others => '1');
-- set signal defaults
set_tx_state <= '0';
tx_count_mode <= HOLD;
data_out <= x"00";
data_out_last <= '0';
set_chn_reqd <= HOLD;
kill_data_out_valid <= '0';
set_send_I_have <= HOLD;
set_send_who_has <= HOLD;
set_tx_mode <= '0';
set_target <= '0';
-- process requests in regardless of FSM state
if send_I_have = '1' then
set_send_I_have <= SET;
end if;
if send_who_has = '1' then
set_send_who_has <= SET;
end if;
-- TX FSM
case tx_state is
when IDLE =>
tx_count_mode <= RST;
if send_I_have_reg = '1' then
set_chn_reqd <= SET;
tx_mode_val <= REPLY;
set_tx_mode <= '1';
target_val <= I_have_target;
set_target <= '1';
set_send_I_have <= CLR;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
elsif send_who_has_reg = '1' then
set_chn_reqd <= SET;
tx_mode_val <= REQUEST;
set_tx_mode <= '1';
target_val.ip <= who_has_target;
target_val.mac <= (others => '1');
set_target <= '1';
set_send_who_has <= CLR;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
else
set_chn_reqd <= CLR;
end if;
when WAIT_MAC =>
tx_count_mode <= RST;
if mac_tx_granted = '1' then
next_tx_state <= SEND;
set_tx_state <= '1';
end if;
-- TODO - should handle timeout here
when SEND =>
if data_out_ready = '1' then
tx_count_mode <= INCR;
end if;
case tx_count is
when x"00" => data_out_first <= data_out_ready;
data_out <= target.mac (47 downto 40); -- target mac--data_out <= x"ff"; -- dst = broadcast
when x"01" => data_out <= target.mac (39 downto 32); --data_out <= x"ff";
when x"02" => data_out <= target.mac (31 downto 24); --data_out <= x"ff";
when x"03" => data_out <= target.mac (23 downto 16); --data_out <= x"ff";
when x"04" => data_out <= target.mac (15 downto 8); --data_out <= x"ff";
when x"05" => data_out <= target.mac (7 downto 0); --data_out <= x"ff";
when x"06" => data_out <= our_mac_address (47 downto 40); -- src = our mac
when x"07" => data_out <= our_mac_address (39 downto 32);
when x"08" => data_out <= our_mac_address (31 downto 24);
when x"09" => data_out <= our_mac_address (23 downto 16);
when x"0a" => data_out <= our_mac_address (15 downto 8);
when x"0b" => data_out <= our_mac_address (7 downto 0);
when x"0c" => data_out <= x"08"; -- pkt type = 0806 : ARP
when x"0d" => data_out <= x"06";
when x"0e" => data_out <= x"00"; -- HW type = 0001 : eth
when x"0f" => data_out <= x"01";
when x"10" => data_out <= x"08"; -- protocol = 0800 : ip
when x"11" => data_out <= x"00";
when x"12" => data_out <= x"06"; -- HW size = 06
when x"13" => data_out <= x"04"; -- prot size = 04
when x"14" => data_out <= x"00"; -- opcode =
when x"15" =>
if tx_mode = REPLY then
data_out <= x"02"; -- 02 : REPLY
else
data_out <= x"01"; -- 01 : REQ
end if;
when x"16" => data_out <= our_mac_address (47 downto 40); -- sender mac
when x"17" => data_out <= our_mac_address (39 downto 32);
when x"18" => data_out <= our_mac_address (31 downto 24);
when x"19" => data_out <= our_mac_address (23 downto 16);
when x"1a" => data_out <= our_mac_address (15 downto 8);
when x"1b" => data_out <= our_mac_address (7 downto 0);
when x"1c" => data_out <= our_ip_address (31 downto 24); -- sender ip
when x"1d" => data_out <= our_ip_address (23 downto 16);
when x"1e" => data_out <= our_ip_address (15 downto 8);
when x"1f" => data_out <= our_ip_address (7 downto 0);
when x"20" => data_out <= target.mac (47 downto 40); -- target mac
when x"21" => data_out <= target.mac (39 downto 32);
when x"22" => data_out <= target.mac (31 downto 24);
when x"23" => data_out <= target.mac (23 downto 16);
when x"24" => data_out <= target.mac (15 downto 8);
when x"25" => data_out <= target.mac (7 downto 0);
when x"26" => data_out <= target.ip (31 downto 24); -- target ip
when x"27" => data_out <= target.ip (23 downto 16);
when x"28" => data_out <= target.ip (15 downto 8);
when x"29" =>
data_out <= target.ip(7 downto 0);
data_out_last <= '1';
when x"2a" =>
kill_data_out_valid <= '1'; -- data is no longer valid
next_tx_state <= IDLE;
set_tx_state <= '1';
when others =>
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end case;
end process;
tx_sequential : process (tx_clk)
begin
if rising_edge(tx_clk) then
if reset = '1' then
-- reset state variables
tx_state <= IDLE;
tx_count <= (others => '0');
tx_mac_chn_reqd <= '0';
send_I_have_reg <= '0';
send_who_has_reg <= '0';
who_has_target <= (others => '0');
I_have_target.ip <= (others => '0');
I_have_target.mac <= (others => '0');
target.ip <= (others => '0');
target.mac <= (others => '1');
else
-- normal (non reset) processing
-- Next tx_state processing
if set_tx_state = '1' then
tx_state <= next_tx_state;
else
tx_state <= tx_state;
end if;
-- input request latching
case set_send_I_have is
when SET =>
send_I_have_reg <= '1';
I_have_target <= arp_entry;
when CLR =>
send_I_have_reg <= '0';
I_have_target <= I_have_target;
when HOLD =>
send_I_have_reg <= send_I_have_reg;
I_have_target <= I_have_target;
end case;
case set_send_who_has is
when SET =>
send_who_has_reg <= '1';
who_has_target <= ip_entry;
when CLR =>
send_who_has_reg <= '0';
who_has_target <= who_has_target;
when HOLD =>
send_who_has_reg <= send_who_has_reg;
who_has_target <= who_has_target;
end case;
-- tx mode
if set_tx_mode = '1' then
tx_mode <= tx_mode_val;
else
tx_mode <= tx_mode;
end if;
-- target latching
if set_target = '1' then
target <= target_val;
else
target <= target;
end if;
-- tx_count processing
case tx_count_mode is
when RST =>
tx_count <= x"00";
when INCR =>
tx_count <= tx_count + 1;
when HOLD =>
tx_count <= tx_count;
end case;
-- control access request to mac tx chn
case set_chn_reqd is
when SET => tx_mac_chn_reqd <= '1';
when CLR => tx_mac_chn_reqd <= '0';
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd;
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Containing a bridge between a RapidIO network and a Wishbone bus. Packets
-- NWRITE and NREAD are currently supported.
--
-- To Do:
-- -
--
-- Author(s):
-- - Nader Kardouni, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.ALL;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- entity for RioWbBridge.
-------------------------------------------------------------------------------
Entity RioWbBridge is
generic(
DEVICE_IDENTITY : std_logic_vector(15 downto 0);
DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
DEVICE_REV : std_logic_vector(31 downto 0);
ASSY_IDENTITY : std_logic_vector(15 downto 0);
ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
ASSY_REV : std_logic_vector(15 downto 0);
DEFAULT_BASE_DEVICE_ID : std_logic_vector(15 downto 0) := x"ffff");
port(
clk : in std_logic; -- Main clock 25MHz
areset_n : in std_logic; -- Asynchronous reset, active low
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
readContent_o : out std_logic;
readContentEnd_i : in std_logic;
readContentData_i : in std_logic_vector(31 downto 0);
writeFrameFull_i : in std_logic;
writeFrame_o : out std_logic;
writeFrameAbort_o : out std_logic;
writeContent_o : out std_logic;
writeContentData_o : out std_logic_vector(31 downto 0);
-- interface to the peripherals module
wbStb_o : out std_logic; -- strob signal, active high
wbWe_o : out std_logic; -- write signal, active high
wbData_o : out std_logic_vector(7 downto 0); -- master data bus
wbAdr_o : out std_logic_vector(25 downto 0); -- master address bus
wbErr_i : in std_logic; -- error signal, high active
wbAck_i : in std_logic; -- slave acknowledge
wbData_i : in std_logic_vector(7 downto 0) -- slave data bus
);
end;
-------------------------------------------------------------------------------
-- Architecture for RioWbBridge.
-------------------------------------------------------------------------------
architecture rtl of RioWbBridge is
component Crc16CITT is
port(
d_i : in std_logic_vector(15 downto 0);
crc_i : in std_logic_vector(15 downto 0);
crc_o : out std_logic_vector(15 downto 0));
end component;
constant RST_LVL : std_logic := '0';
constant BERR_UNKNOWN_DATA : std_logic_vector(7 downto 0) := X"08"; -- not valid data
constant BERR_FRAME_SIZE : std_logic_vector(7 downto 0) := X"81"; -- Frame code size error
constant BERR_FRAME_CODE : std_logic_vector(7 downto 0) := X"80"; -- Frame code type error
constant BERR_NOT_RESPONSE : std_logic_vector(7 downto 0) := X"86"; -- Not response from the device
type state_type_RioBrige is (IDLE, WAIT_HEADER_0, HEADER_0, HEADER_1, CHECK_OPERATION,
READ_ADDRESS, READ_FROM_FIFO, CHECK_ERROR, WRITE_DATA,
WRITE_TO_WB, WAIT_IDLE, SEND_DONE_0, SEND_DONE_1,
SEND_DONE_2, READ_FROM_WB, APPEND_CRC,
SEND_TO_FIFO, SEND_ERROR, SEND_FRAME, APPEND_CRC_AND_SEND,
SEND_MAINTENANCE_READ_RESPONSE_0, SEND_MAINTENANCE_READ_RESPONSE_1,
SEND_MAINTENANCE_WRITE_RESPONSE_0, SEND_MAINTENANCE_WRITE_RESPONSE_1);
signal stateRB, nextStateRB : state_type_RioBrige;
type byteArray8 is array (0 to 7) of std_logic_vector(7 downto 0);
signal dataLane : byteArray8;
-- type byteArray4 is array (0 to 3) of std_logic_vector(7 downto 0);
-- signal dataLaneS : byteArray4;
signal pos, byteOffset : integer range 0 to 7;
signal numberOfByte, byteCnt, headLen : integer range 0 to 256;
signal endianMsb, reserved, ready : std_logic;
signal start : std_logic;
signal wdptr : std_logic;
signal wbStb : std_logic;
signal xamsbs : std_logic_vector(1 downto 0);
signal ftype : std_logic_vector(3 downto 0);
signal ttype : std_logic_vector(3 downto 0);
signal size : std_logic_vector(3 downto 0);
signal tid : std_logic_vector(7 downto 0);
signal tt : std_logic_vector(1 downto 0);
signal errorCode : std_logic_vector(7 downto 0);
signal sourceId : std_logic_vector(15 downto 0);
signal destinationId : std_logic_vector(15 downto 0);
signal writeContentData : std_logic_vector(31 downto 0);
signal crc16Current, crc16Temp, crc16Next: std_logic_vector(15 downto 0);
signal tempAddr : std_logic_vector(25 downto 0);
signal timeOutCnt : std_logic_vector(14 downto 0);
-- Configuration memory signal declaration.
signal configEnable : std_logic;
signal configWrite : std_logic;
signal configAddress : std_logic_vector(23 downto 0);
signal configDataWrite : std_logic_vector(31 downto 0);
signal configDataRead : std_logic_vector(31 downto 0);
signal componentTag : std_logic_vector(31 downto 0);
signal baseDeviceId : std_logic_vector(15 downto 0) := DEFAULT_BASE_DEVICE_ID;
signal hostBaseDeviceIdLocked : std_logic;
signal hostBaseDeviceId : std_logic_vector(15 downto 0) := (others => '1');
begin
wbStb_o <= wbStb;
writeContentData_o <= writeContentData;
Crc16High: Crc16CITT
port map(
d_i=>writeContentData(31 downto 16), crc_i=>crc16Current, crc_o=>crc16Temp);
Crc16Low: Crc16CITT
port map(
d_i=>writeContentData(15 downto 0), crc_i=>crc16Temp, crc_o=>crc16Next);
-----------------------------------------------------------------------------
-- wbInterfaceCtrl
-- This process handle the Wishbone interface to the RioWbBridge module.
-----------------------------------------------------------------------------
wbInterfaceCtrl: process(clk, areset_n)
variable Temp : std_logic_vector(2 downto 0);
begin
if areset_n = RST_LVL then
start <= '0';
wdptr <= '0';
wbStb <= '0';
wbWe_o <= '0';
byteCnt <= 0;
headLen <= 0;
byteOffset <= 0;
readFrame_o <= '0';
readContent_o <= '0';
writeFrame_o <= '0';
writeContent_o <= '0';
writeFrameAbort_o <= '0';
configWrite <= '0';
configEnable <= '0';
ready <= '0';
endianMsb <= '0';
stateRB <= IDLE;
nextStateRB <= IDLE;
tt <= (others => '0');
tid <= (others => '0');
size <= (others => '0');
ttype <= (others => '0');
ftype <= (others => '0');
xamsbs <= (others => '0');
sourceId <= (others => '0');
configDataWrite <= (others => '0');
destinationId <= (others => '0');
errorCode <= (others => '0');
tempAddr <= (others => '0');
wbAdr_o <= (others => '0');
wbData_o <= (others => '0');
writeContentData <= (others => '0');
dataLane <= (others =>(others => '0'));
-- dataLaneS <= (others =>(others => '0'));
crc16Current <= (others => '0');
timeOutCnt <= (others => '0');
Temp := (others => '0');
elsif clk'event and clk ='1' then
case stateRB is
when IDLE =>
if (readFrameEmpty_i = '0') and (writeFrameFull_i = '0') then
readContent_o <= '1';
byteCnt <= 0;
ready <= '0';
endianMsb <= '1';
timeOutCnt <= (others => '0');
crc16Current <= (others => '1');
stateRB <= WAIT_HEADER_0;
else
start <= '0';
readFrame_o <= '0';
readContent_o <= '0';
writeFrame_o <= '0';
writeContent_o <= '0';
writeFrameAbort_o <= '0';
errorCode <= (others => '0');
writeContentData <= (others => '0');
dataLane <= (others =>(others => '0'));
-- dataLaneS <= (others =>(others => '0'));
Temp := (others => '0');
end if;
when WAIT_HEADER_0 =>
stateRB <= HEADER_0;
when HEADER_0 =>
readContent_o <= '1'; -- read the header (frame 0)
tt <= readContentData_i(21 downto 20);
ftype <= readContentData_i(19 downto 16);
destinationId <= readContentData_i(15 downto 0);
stateRB <= HEADER_1;
when HEADER_1 => -- read the header (frame 1)
readContent_o <= '1';
ttype <= readContentData_i(15 downto 12);
size <= readContentData_i(11 downto 8);
tid <= readContentData_i(7 downto 0);
sourceId <= readContentData_i(31 downto 16);
stateRB <= READ_ADDRESS;
when READ_ADDRESS =>
readContent_o <= '0';
wdptr <= readContentData_i(2);
xamsbs <= readContentData_i(1 downto 0);
tempAddr <= readContentData_i(25 downto 3) & "000"; -- Wishbone address bus is 26 bits width
configAddress <= readContentData_i(23 downto 0); -- this line is in case of maintenance pakage (config-offset(21-bits)+wdptr(1-bit)+rsv(2-bits))
stateRB <= CHECK_ERROR;
when CHECK_ERROR =>
byteOffset <= pos; -- first byte position in the first payload
tempAddr <= tempAddr + pos; -- first address
if readContentEnd_i = '1' then -- check if data not valid i the switch buffer
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= BERR_UNKNOWN_DATA; -- not valid data
stateRB <= SEND_ERROR;
-- check if error in the frame size for write pakage
elsif (reserved = '1') and (ftype = FTYPE_WRITE_CLASS) then
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= BERR_FRAME_SIZE; -- Frame code size error
stateRB <= SEND_ERROR;
-- type 5 pakage formate, NWRITE transaction (write to peripherals) read payload from the buffer
elsif (ftype = FTYPE_WRITE_CLASS) and (ttype = "0100") and (tt = "01") then
readContent_o <= '1';
stateRB <= READ_FROM_FIFO; -- read the payload
nextStateRB <= SEND_ERROR; -- this is in case not valid data in switch buffer
headLen <= 12;
-- Type 2 pakage formate, NREAD transaction, (read from peripherals) write payload to the buffer
elsif (ftype = FTYPE_REQUEST_CLASS) and (ttype = "0100") and (tt = "01") then
writeContent_o <= '1'; -- write the header-0 of the Read Response pakage
writeContentData(15 downto 0) <= sourceId; -- write to the source address
writeContentData(19 downto 16) <= "1101"; -- Response pakage type 13, ftype Response
writeContentData(21 downto 20) <= "01"; -- tt
writeContentData(31 downto 22) <= "0000000000"; -- acckId, vc, cfr, prio
stateRB <= SEND_DONE_0; --
headLen <= 8;
-- Type 8 pakage formate, maintenance Read request
elsif (ftype = FTYPE_MAINTENANCE_CLASS) and (ttype = TTYPE_MAINTENANCE_READ_REQUEST) and (tt = "01") then
configWrite <= '0'; -- read config operation
configEnable <= '1'; -- enable signal to the memoryConfig process
writeContent_o <= '1';
-- write the header-0 of the Read Response pakage
writeContentData(15 downto 0) <= sourceId; -- write to the source address, this is a response pakage
writeContentData(19 downto 16) <= FTYPE_MAINTENANCE_CLASS; -- ftype, maintenance
writeContentData(21 downto 20) <= "01"; -- tt
writeContentData(31 downto 22) <= "0000000000"; -- acckId, vc, cfr, prio
stateRB <= SEND_MAINTENANCE_READ_RESPONSE_0;
-- Type 8 pakage formate, maintenance Write request
elsif (ftype = FTYPE_MAINTENANCE_CLASS) and (ttype = TTYPE_MAINTENANCE_WRITE_REQUEST) and (tt = "01") then
configWrite <= '1'; -- write config operation
writeContent_o <= '1'; -- write the header-0
writeContentData(15 downto 0) <= sourceId; -- write to the source address, this is a response pakage
writeContentData(19 downto 16) <= FTYPE_MAINTENANCE_CLASS; -- ftype, maintenance
writeContentData(21 downto 20) <= "01"; -- tt
writeContentData(31 downto 22) <= "0000000000"; -- acckId, vc, cfr, prio
stateRB <= SEND_MAINTENANCE_WRITE_RESPONSE_0;
-- Error: unexpected ftype or ttype
else
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= BERR_FRAME_CODE;
stateRB <= SEND_ERROR; -- next state after the dataLane is stored in the switch buffer
end if;
when SEND_MAINTENANCE_READ_RESPONSE_0 =>
byteCnt <= 0;
configEnable <= '0'; -- disable signal to the memoryConfig process
-- write the header-1 of the Read Response pakage
writeContentData(7 downto 0) <= tid;
writeContentData(11 downto 8) <= "0000"; -- size/status
writeContentData(15 downto 12) <= TTYPE_MAINTENANCE_READ_RESPONSE; -- transaction type, Maintenance Read Response
writeContentData(31 downto 16) <= baseDeviceId; -- destination address, because this is a response pakage
crc16Current <= crc16Next; -- first frame's CRC
stateRB <= SEND_MAINTENANCE_READ_RESPONSE_1;
when SEND_MAINTENANCE_READ_RESPONSE_1 =>
byteCnt <= byteCnt + 1; -- using byteCnt as a counter
if byteCnt = 0 then
writeContentData <= X"FF" & X"000000"; -- write the filed with HOP + reserved
crc16Current <= crc16Next; -- second frame's CRC
elsif byteCnt = 1 then
if configAddress(2) = '0' then -- check the wdptr bit in the config offset field
writeContentData <= configDataRead; -- write payload-0 with data if wdptr='0'
else
writeContentData <= (others => '0'); -- write zeros
end if;
crc16Current <= crc16Next; -- third frame's CRC
elsif byteCnt = 2 then
if configAddress(2) = '0' then -- check the wdptr bit in the config offset field
writeContentData <= (others => '0'); -- write zeros
else
writeContentData <= configDataRead; -- write payload-1 with data if wdptr='1'
end if;
crc16Current <= crc16Next; -- forth frame's CRC
elsif byteCnt = 3 then
writeContentData <= crc16Next & X"0000"; -- write the CRC field
else
writeContent_o <= '0';
stateRB <= SEND_FRAME;
end if;
when SEND_MAINTENANCE_WRITE_RESPONSE_0 =>
byteCnt <= 0;
readContent_o <= '1'; -- read the config offset
if configAddress(2) = '0' then -- check the wdptr bit in the config offset field
configDataWrite <= readContentData_i; -- copy payload-0 if wdptr='0'
else
configDataWrite <= configDataWrite; -- do nothing
end if;
writeContentData(7 downto 0) <= tid;
writeContentData(11 downto 8) <= "0000"; -- size/status
writeContentData(15 downto 12) <= TTYPE_MAINTENANCE_WRITE_RESPONSE; -- transaction type, Maintenance Write Response
writeContentData(31 downto 16) <= baseDeviceId; -- destination address, because this is a response pakage
crc16Current <= crc16Next; -- first frame's CRC
stateRB <= SEND_MAINTENANCE_WRITE_RESPONSE_1;
when SEND_MAINTENANCE_WRITE_RESPONSE_1 =>
byteCnt <= byteCnt + 1; -- using byteCnt as a counter
if byteCnt = 0 then
writeContentData <= X"FF" & X"000000"; -- write the filed with HOP + reserved
crc16Current <= crc16Next; -- second frame's CRC
elsif byteCnt = 1 then
configEnable <= '1'; -- enable signal to the memoryConfig process
writeContentData <= crc16Next & X"0000"; -- write the CRC field
if configAddress(2) = '0' then -- check the wdptr bit in the config offset field
configDataWrite <= configDataWrite; -- do nothing
else
configDataWrite <= readContentData_i; -- copy payload-1 if wdptr='1'
end if;
else
configEnable <= '0'; -- disable signal to the memoryConfig process
readContent_o <= '0'; -- at this point even the frame's CRC is read from the buffer
writeContent_o <= '0';
stateRB <= SEND_FRAME;
end if;
when SEND_DONE_0 =>
writeContent_o <= '1';
writeContentData(7 downto 0) <= tid;
writeContentData(11 downto 8) <= "0000"; -- size/status
writeContentData(15 downto 12) <= "1000"; -- ttype
writeContentData(31 downto 16) <= baseDeviceId;
crc16Current <= crc16Next; -- first frame's CRC
stateRB <= SEND_DONE_1;
when SEND_DONE_1 =>
byteCnt <= 0;
dataLane <= (others =>(others => '0'));
writeContent_o <= '0'; -- this line is to make sure that the CRC is complete read
crc16Current <= crc16Next; -- second frame's CRC
wbAdr_o <= tempAddr;
tempAddr <= tempAddr + 1;
wbStb <= '1';
wbWe_o <= '0';
byteOffset <= pos;
stateRB <= READ_FROM_WB;
when READ_FROM_WB =>
if wbAck_i = '1' then
timeOutCnt <= (others => '0'); -- reset the time out conter
if wbErr_i = '0' then -- check if no error occur
if (byteCnt < numberOfByte - 1) then -- check if reach the last data byte
byteCnt <= byteCnt + 1;
if (byteCnt + headLen = 80) then -- when current position in payload is a CRC position
dataLane(0) <= crc16Current(15 downto 8);
dataLane(1) <= crc16Current(7 downto 0);
dataLane(2) <= wbData_i;
byteOffset <= 3;
elsif byteOffset < 7 then
dataLane(byteOffset) <= wbData_i;
byteOffset <= byteOffset + 1;
else -- dataLane vector is ready to send to fifo
dataLane(7) <= wbData_i;
byteOffset <= 0; -- Here, sets byteOffset for other response
stateRB <= SEND_TO_FIFO;
nextStateRB <= READ_FROM_WB; --
end if;
else -- get last data from Wishbone
wbStb <= '0';
byteCnt <= 0; -- Here, using byteCnt and reset it for other response
dataLane(byteOffset) <= wbData_i;
stateRB <= APPEND_CRC_AND_SEND;
if byteOffset < 7 then -- checking for CRC appending position
byteOffset <= byteOffset + 1;
else
byteOffset <= 0;
end if;
end if;
-- when Wishbone error occur
else
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= wbData_i;
stateRB <= SEND_ERROR;
end if;
else -- when no acknowledge received
if timeOutCnt(13) = '1' then -- when waiting more than 1 ms for response from the device
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= BERR_NOT_RESPONSE;
stateRB <= SEND_ERROR;
else
timeOutCnt <= timeOutCnt + 1;
end if;
end if;
-- appending CRC and write to the fifo when frame is shorter then 80 bytes
when APPEND_CRC_AND_SEND =>
writeContent_o <= '0';
byteCnt <= byteCnt + 1;
-- check if frame is shorter than 80 bytes
if (numberOfByte < 65) then
-- Yes, frame is shorter then 80 bytes
if byteCnt = 0 then
-- first write the current double word to the fifo
-- then put the CRC in the next double word
byteOffset <= 0;
stateRB <= SEND_TO_FIFO;
nextStateRB <= APPEND_CRC_AND_SEND;
elsif byteCnt = 1 then
-- append the CRC
writeContent_o <= '1';
writeContentData <= crc16Current & X"0000";
else
stateRB <= SEND_FRAME; -- store in the switch buffer
end if;
else
--No, appending CRC and write to the fifo when frame is longer then 80 bytes
if byteCnt = 0 then
-- check if the last byte was placed in the second half of the double word,
-- in that case write the first word to the fifo.
writeContentData <= dataLane(0) & dataLane(1) & dataLane(2) & dataLane(3);
elsif byteCnt = 1 then
crc16Current <= crc16Temp; -- calcylate the crc for the 16 most significant bits
elsif byteCnt = 2 then
writeContent_o <= '1';
writeContentData <= dataLane(0) & dataLane(1) & crc16Current;
else
stateRB <= SEND_FRAME; -- store in the switch buffer
end if;
end if;
when SEND_TO_FIFO =>
if byteOffset = 0 then -- using byteOffset as a counter
byteOffset <= 1;
writeContent_o <= '1';
writeContentData <= dataLane(0) & dataLane(1) & dataLane(2) & dataLane(3);
elsif byteOffset = 1 then -- using byteOffset as a counter
byteOffset <= 2;
writeContent_o <= '0';
crc16Current <= crc16Next; -- calcylate the crc
elsif byteOffset = 2 then
byteOffset <= 3;
writeContent_o <= '1';
writeContentData <= dataLane(4) & dataLane(5) & dataLane(6) & dataLane(7);
elsif byteOffset = 3 then
crc16Current <= crc16Next; -- calcylate the crc
writeContent_o <= '0';
byteOffset <= 0;
stateRB <= nextStateRB;
dataLane <= (others =>(others => '0'));
end if;
when READ_FROM_FIFO =>
if (endianMsb = '1') then
if (readContentEnd_i = '0') then
endianMsb <= '0';
dataLane(0 to 3) <= (readContentData_i(31 downto 24), readContentData_i(23 downto 16),
readContentData_i(15 downto 8), readContentData_i(7 downto 0));
else
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
readContent_o <= '0';
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= BERR_FRAME_SIZE;
stateRB <= SEND_ERROR;
-- stateRB <= IDLE;
end if;
else
endianMsb <= '1';
readContent_o <= '0';
dataLane(4 to 7) <= (readContentData_i(31 downto 24), readContentData_i(23 downto 16),
readContentData_i(15 downto 8), readContentData_i(7 downto 0));
if ready = '1' then
stateRB <= nextStateRB;
else
stateRB <= WRITE_TO_WB;
end if;
end if;
when WRITE_TO_WB =>
if wbStb = '0' then
wbStb <= '1';
wbWe_o <= '1';
byteCnt <= 1;
byteOffset <= byteOffset + 1; -- increase number of counted byte
tempAddr <= tempAddr + 1; -- increase the memory sddress address
wbAdr_o <= tempAddr;
wbData_o <= dataLane(byteOffset);
else
if wbAck_i = '1' then
timeOutCnt <= (others => '0'); -- reset the time out conter
if wbErr_i = '0' then -- check the peripherals error signal
if byteCnt < numberOfByte then
tempAddr <= tempAddr + 1; -- increase the memory sddress address
wbAdr_o <= tempAddr;
wbData_o <= dataLane(byteOffset);
byteCnt <= byteCnt + 1; -- increase number of counted byte
if byteOffset < 7 then
if (byteCnt + headLen = 79) then -- check for the CRC-byte position 80 in the frame
byteOffset <= byteOffset + 3;
else
byteOffset <= byteOffset + 1;
end if;
else
if (byteCnt + headLen = 79) then -- check for the CRC-byte position 80 in the frame
byteOffset <= 2;
else
byteOffset <= 0;
end if;
if byteCnt < numberOfByte - 1 then
readContent_o <= '1';
stateRB <= READ_FROM_FIFO;
end if;
end if;
else -- no more data to send to the peripherals
wbStb <= '0';
wbWe_o <= '0';
ready <= '1';
stateRB <= SEND_FRAME;
end if;
else -- if the peripheral generates an error, send an error Response
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= wbData_i;
stateRB <= SEND_ERROR;
end if;
else
-- if readContentEnd_i = '1' then -- when unvalid data in the switch buffer
-- wbStb <= '0';
-- wbWe_o <= '0';
-- readFrame_o <= '1';
-- byteOffset <= 0;
-- writeFrameAbort_o <= '1'; -- over write the frame with an error frame
-- errorCode <= BERR_FRAME_SIZE; -- more data content is expected, Frame size error
-- stateRB <= SEND_ERROR;
-- else
if timeOutCnt(13) = '1' then -- when waiting more than 1 ms for response from the device
wbStb <= '0';
wbWe_o <= '0';
readFrame_o <= '1';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= BERR_NOT_RESPONSE;
stateRB <= SEND_ERROR;
else
timeOutCnt <= timeOutCnt + 1;
end if;
-- end if;
end if;
end if;
when SEND_ERROR => -- Generate a Response Class, an error pakage ftype=13, ttype=8, status="1111"
readFrame_o <= '0';
writeFrameAbort_o <= '0';
byteOffset <= byteOffset + 1;
if byteOffset = 0 then
writeContent_o <= '1'; -- start write to the buffer
crc16Current <= (others => '1');
writeContentData <= "00000000" & "00" & "01" & "1101" & sourceId;
elsif byteOffset = 1 then
writeContentData <= baseDeviceId & "1000" & "1111" & tid;
crc16Current <= crc16Next; -- first frame's CRC
elsif byteOffset = 2 then
writeContentData <= errorCode & x"000000";
crc16Current <= crc16Next; -- second frame's CRC
elsif byteOffset = 3 then
writeContentData <= x"00000000";
crc16Current <= crc16Next; -- third frame's CRC
elsif byteOffset = 4 then
writeContentData <= crc16Next & X"0000"; -- write the CRC field
else
writeContent_o <= '0';
writeFrame_o <= '1';
readFrame_o <= '1';
stateRB <= WAIT_IDLE;
end if;
when SEND_FRAME =>
if (ftype = FTYPE_WRITE_CLASS) and (ttype = TTYPE_NWRITE_TRANSACTION) and (tt = "01") then -- check what type of pakage we got
readFrame_o <= '1';
elsif (ftype = FTYPE_REQUEST_CLASS) and (ttype = TTYPE_NREAD_TRANSACTION) and (tt = "01") then -- write payload to the buffer is done
readFrame_o <= '1';
writeFrame_o <= '1';
else -- the operation was not valid
readFrame_o <= '1';
writeFrame_o <= '1';
end if;
stateRB <= WAIT_IDLE;
when WAIT_IDLE =>
readFrame_o <= '0';
writeFrame_o <= '0';
readContent_o <= '0'; -- this line is to make sure that the CRC is complete read
stateRB <= IDLE;
when others =>
stateRB <= IDLE;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- Configuration memory.
-----------------------------------------------------------------------------
memoryConfig : process(clk, areset_n)
begin
if (areset_n = '0') then
configDataRead <= (others => '0');
baseDeviceId <= DEFAULT_BASE_DEVICE_ID;
componentTag <= (others => '0');
hostBaseDeviceIdLocked <= '0';
hostBaseDeviceId <= (others => '1');
elsif (clk'event and clk = '1') then
if (configEnable = '1') then
case (configAddress) is
when x"000000" =>
-- Device Identity CAR. Read-only.
configDataRead(31 downto 16) <= DEVICE_IDENTITY;
configDataRead(15 downto 0) <= DEVICE_VENDOR_IDENTITY;
when x"000004" =>
-- Device Information CAR. Read-only.
configDataRead(31 downto 0) <= DEVICE_REV;
when x"000008" =>
-- Assembly Identity CAR. Read-only.
configDataRead(31 downto 16) <= ASSY_IDENTITY;
configDataRead(15 downto 0) <= ASSY_VENDOR_IDENTITY;
when x"00000c" =>
-- Assembly Informaiton CAR. Read-only.
-- Extended features pointer to "0000".
configDataRead(31 downto 16) <= ASSY_REV;
configDataRead(15 downto 0) <= x"0000";
when x"000010" =>
-- Processing Element Features CAR. Read-only.
-- Bridge(31), Memory(30), Processor(29), Switch(28).
configDataRead(31) <= '1';
configDataRead(30 downto 4) <= (others => '0');
configDataRead(3) <= '1'; -- support 16 bits common transport large system
configDataRead(2 downto 0) <= "001"; -- support 34 bits address
when x"000018" =>
-- Source Operations CAR. Read-only.
configDataRead(31 downto 0) <= (others => '0');
when x"00001C" =>
-- Destination Operations CAR. Read-only.
configDataRead(31 downto 16) <= (others => '0');
configDataRead(15) <= '1';
configDataRead(14) <= '1';
configDataRead(13 downto 0) <= (others => '0');
when x"00004C" =>
-- Processing Element Logical Layer Control CSR.
configDataRead(31 downto 3) <= (others => '0');
configDataRead(2 downto 0) <= "001"; -- support 34 bits address
when x"000060" =>
-- Base Device ID CSR.
-- Only valid for end point devices.
if (configWrite = '1') then
baseDeviceId <= configDataWrite(15 downto 0);
else
configDataRead(15 downto 0) <= baseDeviceId;
end if;
when x"000068" =>
-- Host Base Device ID Lock CSR.
if (configWrite = '1') then
-- Check if this field has been written before.
if (hostBaseDeviceIdLocked = '0') then
-- The field has not been written.
-- Lock the field and set the host base device id.
hostBaseDeviceIdLocked <= '1';
hostBaseDeviceId <= configDataWrite(15 downto 0);
else
-- The field has been written.
-- Check if the written data is the same as the stored.
if (hostBaseDeviceId = configDataWrite(15 downto 0)) then
-- Same as stored, reset the value to its initial value.
hostBaseDeviceIdLocked <= '0';
hostBaseDeviceId <= (others => '1');
else
-- Not writing the same as the stored value.
-- Ignore the write.
end if;
end if;
else
configDataRead(31 downto 16) <= (others => '0');
configDataRead(15 downto 0) <= hostBaseDeviceId;
end if;
when x"00006C" =>
-- Component TAG CSR.
if (configWrite = '1') then
componentTag <= configDataWrite;
else
configDataRead <= componentTag;
end if;
when others =>
configDataRead <= (others => '0');
end case;
else
-- Config memory not enabled.
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- findInPayload
-- find out number of the bytes and first byte's position in the payload.
-----------------------------------------------------------------------------
findInPayload: process(wdptr, size)
begin
case size is
when "0000" =>
reserved <= '0';
numberOfByte <= 1;
if wdptr = '1' then
pos <= 4;
else
pos <= 0;
end if;
when "0001" =>
reserved <= '0';
numberOfByte <= 1;
if wdptr = '1' then
pos <= 5;
else
pos <= 1;
end if;
when "0010" =>
reserved <= '0';
numberOfByte <= 1;
if wdptr = '1' then
pos <= 6;
else
pos <= 2;
end if;
when "0011" =>
reserved <= '0';
numberOfByte <= 1;
if wdptr = '1' then
pos <= 7;
else
pos <= 3;
end if;
when "0100" =>
reserved <= '0';
numberOfByte <= 2;
if wdptr = '1' then
pos <= 4;
else
pos <= 0;
end if;
when "0101" =>
reserved <= '0';
numberOfByte <= 3;
if wdptr = '1' then
pos <= 5;
else
pos <= 0;
end if;
when "0110" =>
reserved <= '0';
numberOfByte <= 2;
if wdptr = '1' then
pos <= 6;
else
pos <= 2;
end if;
when "0111" =>
reserved <= '0';
numberOfByte <= 5;
if wdptr = '1' then
pos <= 3;
else
pos <= 0;
end if;
when "1000" =>
reserved <= '0';
numberOfByte <= 4;
if wdptr = '1' then
pos <= 4;
else
pos <= 0;
end if;
when "1001" =>
reserved <= '0';
numberOfByte <= 6;
if wdptr = '1' then
pos <= 2;
else
pos <= 0;
end if;
when "1010" =>
reserved <= '0';
numberOfByte <= 7;
if wdptr = '1' then
pos <= 1;
else
pos <= 0;
end if;
when "1011" =>
reserved <= '0';
if wdptr = '1' then
numberOfByte <= 16;
else
numberOfByte <= 8;
end if;
pos <= 0;
when "1100" =>
reserved <= '0';
if wdptr = '1' then
numberOfByte <= 64;
else
numberOfByte <= 32;
end if;
pos <= 0;
when "1101" =>
if wdptr = '1' then
reserved <= '0';
numberOfByte <= 128;
else
reserved <= '1';
numberOfByte <= 96;
end if;
pos <= 0;
when "1110" =>
if wdptr = '1' then
numberOfByte <= 192;
else
numberOfByte <= 160;
end if;
reserved <= '1';
pos <= 0;
when "1111" =>
if wdptr = '1' then
reserved <= '0';
numberOfByte <= 256;
else
reserved <= '1';
numberOfByte <= 224;
end if;
pos <= 0;
when others =>
reserved <= '1';
numberOfByte <= 0;
pos <= 0;
end case;
end process;
end architecture;
|
-- This file has been automatically generated by go-iec61499-vhdl and should not be edited by hand
-- Converter written by Hammond Pearce and available at github.com/kiwih/go-iec61499-vhdl
-- This file represents the Basic Function Block for ConveyorController
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ConveyorController is
port(
--for clock and reset signal
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
sync : in std_logic;
--input events
InjectDone : in std_logic;
EmergencyStopChanged : in std_logic;
LasersChanged : in std_logic;
--output events
ConveyorChanged : out std_logic;
ConveyorStoppedForInject : out std_logic;
--input variables
EmergencyStop_I : in std_logic; --type was BOOL
InjectSiteLaser_I : in std_logic; --type was BOOL
--output variables
ConveyorSpeed_O : out unsigned(7 downto 0); --type was BYTE
--for done signal
done : out std_logic
);
end entity;
architecture rtl of ConveyorController is
-- Build an enumerated type for the state machine
type state_type is (STATE_E_Stop, STATE_Running, STATE_Pause);
-- Register to hold the current state
signal state : state_type := STATE_E_Stop;
-- signals to store variable sampled on enable
signal EmergencyStop : std_logic := '0'; --register for input
signal InjectSiteLaser : std_logic := '0'; --register for input
-- signals to rename outputs
signal ConveyorSpeed : unsigned(7 downto 0) := (others => '0');
-- signals for enabling algorithms
signal ConveyorStart_alg_en : std_logic := '0';
signal ConveyorStart_alg_done : std_logic := '1';
signal ConveyorStop_alg_en : std_logic := '0';
signal ConveyorStop_alg_done : std_logic := '1';
signal ConveyorRunning_alg_en : std_logic := '0';
signal ConveyorRunning_alg_done : std_logic := '1';
signal ConveyorEStop_alg_en : std_logic := '0';
signal ConveyorEStop_alg_done : std_logic := '1';
-- signal for algorithm completion
signal AlgorithmsStart : std_logic := '0';
signal AlgorithmsDone : std_logic;
--internal variables
signal Variable1 : std_logic; --type was BOOL
begin
-- Registers for data variables (only updated on relevant events)
process (clk)
begin
if rising_edge(clk) then
if sync = '1' then
if EmergencyStopChanged = '1' then
EmergencyStop <= EmergencyStop_I;
end if;
if LasersChanged = '1' then
InjectSiteLaser <= InjectSiteLaser_I;
end if;
end if;
end if;
end process;
--output var renaming, no output registers as inputs are stored where they are processed
ConveyorSpeed_O <= ConveyorSpeed;
-- Logic to advance to the next state
process (clk, reset)
begin
if reset = '1' then
state <= STATE_E_Stop;
AlgorithmsStart <= '1';
elsif (rising_edge(clk)) then
if AlgorithmsStart = '1' then --algorithms should be triggered only once via this pulse signal
AlgorithmsStart <= '0';
elsif enable = '1' then
--default values
state <= state;
AlgorithmsStart <= '0';
--next state logic
if AlgorithmsStart = '0' and AlgorithmsDone = '1' then
case state is
when STATE_E_Stop =>
if EmergencyStopChanged = '1' and (not EmergencyStop = '1') then
state <= STATE_Running;
AlgorithmsStart <= '1';
end if;
when STATE_Running =>
if LasersChanged = '1' and (InjectSiteLaser = '1') then
state <= STATE_Pause;
AlgorithmsStart <= '1';
end if;
when STATE_Pause =>
if InjectDone = '1' then
state <= STATE_Running;
AlgorithmsStart <= '1';
elsif EmergencyStopChanged = '1' and (EmergencyStop = '1') then
state <= STATE_E_Stop;
AlgorithmsStart <= '1';
end if;
end case;
end if;
end if;
end if;
end process;
-- Event outputs and internal algorithm triggers depend solely on the current state
process (state)
begin
--default values
--events
ConveyorChanged <= '0';
ConveyorStoppedForInject <= '0';
--algorithms
ConveyorStart_alg_en <= '0';
ConveyorStop_alg_en <= '0';
ConveyorRunning_alg_en <= '0';
ConveyorEStop_alg_en <= '0';
case state is
when STATE_E_Stop =>
when STATE_Running =>
ConveyorStart_alg_en <= '1';
ConveyorChanged <= '1';
when STATE_Pause =>
ConveyorStop_alg_en <= '1';
ConveyorChanged <= '1';
ConveyorStoppedForInject <= '1';
end case;
end process;
-- Algorithms process
process(clk)
begin
if rising_edge(clk) then
if AlgorithmsStart = '1' then
if ConveyorStart_alg_en = '1' then -- Algorithm ConveyorStart
ConveyorStart_alg_done <= '0';
end if;
if ConveyorStop_alg_en = '1' then -- Algorithm ConveyorStop
ConveyorStop_alg_done <= '0';
end if;
if ConveyorRunning_alg_en = '1' then -- Algorithm ConveyorRunning
ConveyorRunning_alg_done <= '0';
end if;
if ConveyorEStop_alg_en = '1' then -- Algorithm ConveyorEStop
ConveyorEStop_alg_done <= '0';
end if;
end if;
if ConveyorStart_alg_done = '0' then -- Algorithm ConveyorStart
--begin algorithm raw text
ConveyorSpeed <= x"01";
ConveyorStart_alg_done <= '1';
--end algorithm raw text
end if;
if ConveyorStop_alg_done = '0' then -- Algorithm ConveyorStop
--begin algorithm raw text
ConveyorSpeed <= x"00";
ConveyorStop_alg_done <= '1';
--end algorithm raw text
end if;
if ConveyorRunning_alg_done = '0' then -- Algorithm ConveyorRunning
--begin algorithm raw text
ConveyorRunning_alg_done <= '1';
--end algorithm raw text
end if;
if ConveyorEStop_alg_done = '0' then -- Algorithm ConveyorEStop
--begin algorithm raw text
ConveyorEStop_alg_done <= '1';
--end algorithm raw text
end if;
end if;
end process;
--Done signal
AlgorithmsDone <= (not AlgorithmsStart) and ConveyorStart_alg_done and ConveyorStop_alg_done and ConveyorRunning_alg_done and ConveyorEStop_alg_done;
Done <= AlgorithmsDone;
end rtl;
|
-- This file has been automatically generated by go-iec61499-vhdl and should not be edited by hand
-- Converter written by Hammond Pearce and available at github.com/kiwih/go-iec61499-vhdl
-- This file represents the Basic Function Block for ConveyorController
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ConveyorController is
port(
--for clock and reset signal
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
sync : in std_logic;
--input events
InjectDone : in std_logic;
EmergencyStopChanged : in std_logic;
LasersChanged : in std_logic;
--output events
ConveyorChanged : out std_logic;
ConveyorStoppedForInject : out std_logic;
--input variables
EmergencyStop_I : in std_logic; --type was BOOL
InjectSiteLaser_I : in std_logic; --type was BOOL
--output variables
ConveyorSpeed_O : out unsigned(7 downto 0); --type was BYTE
--for done signal
done : out std_logic
);
end entity;
architecture rtl of ConveyorController is
-- Build an enumerated type for the state machine
type state_type is (STATE_E_Stop, STATE_Running, STATE_Pause);
-- Register to hold the current state
signal state : state_type := STATE_E_Stop;
-- signals to store variable sampled on enable
signal EmergencyStop : std_logic := '0'; --register for input
signal InjectSiteLaser : std_logic := '0'; --register for input
-- signals to rename outputs
signal ConveyorSpeed : unsigned(7 downto 0) := (others => '0');
-- signals for enabling algorithms
signal ConveyorStart_alg_en : std_logic := '0';
signal ConveyorStart_alg_done : std_logic := '1';
signal ConveyorStop_alg_en : std_logic := '0';
signal ConveyorStop_alg_done : std_logic := '1';
signal ConveyorRunning_alg_en : std_logic := '0';
signal ConveyorRunning_alg_done : std_logic := '1';
signal ConveyorEStop_alg_en : std_logic := '0';
signal ConveyorEStop_alg_done : std_logic := '1';
-- signal for algorithm completion
signal AlgorithmsStart : std_logic := '0';
signal AlgorithmsDone : std_logic;
--internal variables
signal Variable1 : std_logic; --type was BOOL
begin
-- Registers for data variables (only updated on relevant events)
process (clk)
begin
if rising_edge(clk) then
if sync = '1' then
if EmergencyStopChanged = '1' then
EmergencyStop <= EmergencyStop_I;
end if;
if LasersChanged = '1' then
InjectSiteLaser <= InjectSiteLaser_I;
end if;
end if;
end if;
end process;
--output var renaming, no output registers as inputs are stored where they are processed
ConveyorSpeed_O <= ConveyorSpeed;
-- Logic to advance to the next state
process (clk, reset)
begin
if reset = '1' then
state <= STATE_E_Stop;
AlgorithmsStart <= '1';
elsif (rising_edge(clk)) then
if AlgorithmsStart = '1' then --algorithms should be triggered only once via this pulse signal
AlgorithmsStart <= '0';
elsif enable = '1' then
--default values
state <= state;
AlgorithmsStart <= '0';
--next state logic
if AlgorithmsStart = '0' and AlgorithmsDone = '1' then
case state is
when STATE_E_Stop =>
if EmergencyStopChanged = '1' and (not EmergencyStop = '1') then
state <= STATE_Running;
AlgorithmsStart <= '1';
end if;
when STATE_Running =>
if LasersChanged = '1' and (InjectSiteLaser = '1') then
state <= STATE_Pause;
AlgorithmsStart <= '1';
end if;
when STATE_Pause =>
if InjectDone = '1' then
state <= STATE_Running;
AlgorithmsStart <= '1';
elsif EmergencyStopChanged = '1' and (EmergencyStop = '1') then
state <= STATE_E_Stop;
AlgorithmsStart <= '1';
end if;
end case;
end if;
end if;
end if;
end process;
-- Event outputs and internal algorithm triggers depend solely on the current state
process (state)
begin
--default values
--events
ConveyorChanged <= '0';
ConveyorStoppedForInject <= '0';
--algorithms
ConveyorStart_alg_en <= '0';
ConveyorStop_alg_en <= '0';
ConveyorRunning_alg_en <= '0';
ConveyorEStop_alg_en <= '0';
case state is
when STATE_E_Stop =>
when STATE_Running =>
ConveyorStart_alg_en <= '1';
ConveyorChanged <= '1';
when STATE_Pause =>
ConveyorStop_alg_en <= '1';
ConveyorChanged <= '1';
ConveyorStoppedForInject <= '1';
end case;
end process;
-- Algorithms process
process(clk)
begin
if rising_edge(clk) then
if AlgorithmsStart = '1' then
if ConveyorStart_alg_en = '1' then -- Algorithm ConveyorStart
ConveyorStart_alg_done <= '0';
end if;
if ConveyorStop_alg_en = '1' then -- Algorithm ConveyorStop
ConveyorStop_alg_done <= '0';
end if;
if ConveyorRunning_alg_en = '1' then -- Algorithm ConveyorRunning
ConveyorRunning_alg_done <= '0';
end if;
if ConveyorEStop_alg_en = '1' then -- Algorithm ConveyorEStop
ConveyorEStop_alg_done <= '0';
end if;
end if;
if ConveyorStart_alg_done = '0' then -- Algorithm ConveyorStart
--begin algorithm raw text
ConveyorSpeed <= x"01";
ConveyorStart_alg_done <= '1';
--end algorithm raw text
end if;
if ConveyorStop_alg_done = '0' then -- Algorithm ConveyorStop
--begin algorithm raw text
ConveyorSpeed <= x"00";
ConveyorStop_alg_done <= '1';
--end algorithm raw text
end if;
if ConveyorRunning_alg_done = '0' then -- Algorithm ConveyorRunning
--begin algorithm raw text
ConveyorRunning_alg_done <= '1';
--end algorithm raw text
end if;
if ConveyorEStop_alg_done = '0' then -- Algorithm ConveyorEStop
--begin algorithm raw text
ConveyorEStop_alg_done <= '1';
--end algorithm raw text
end if;
end if;
end process;
--Done signal
AlgorithmsDone <= (not AlgorithmsStart) and ConveyorStart_alg_done and ConveyorStop_alg_done and ConveyorRunning_alg_done and ConveyorEStop_alg_done;
Done <= AlgorithmsDone;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.all;
entity register_generic is
generic(N: integer);
port( CK: in std_logic;
RESET: in std_logic;
ENABLE: in std_logic;
D: in std_logic_vector(N-1 downto 0);
Q: out std_logic_vector(N-1 downto 0));
end register_generic;
architecture BEHAVIORAL of register_generic is
begin
REGISTER_PROCESS: process(CK, RESET)
begin
if CK'event and CK='1' then -- positive edge triggered:
if RESET='1' then -- active high reset
Q <= (others => '0');
else
if ENABLE = '1' then
Q <= D;
end if;
end if;
end if;
end process;
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Title : DMA for VME Interface
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : dma.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 24/06/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- The vme core has a DMA controller for high performance data transfers between
-- the SRAM, PCI space and VMEbus. It is operated through a series of registers
-- that control the source/destination for the data, length of the transfer and
-- the transfer protocol (A24 or A32) to be used. These registers are not
-- directly accessible, but they will be loaded with the content of the Buffer
-- Descriptor(s) located in the local SRAM.
-- One buffer descriptor may be linked to the next buffer descriptor, such that
-- when the DMA has completed the operations described by one buffer descriptor,
-- it automatically moves on to the next buffer descriptor in the local SRAM
-- list. The last buffer descriptor is reached, when the DMA_NULL bit is set in
-- the corresponding buffer descriptor. The maximum number of linked buffer
-- descriptors is 112.
-- The DMA supports interrupt assertion when all specified buffer descriptors
-- are processed (signaled via dma_irq to PCIe, see DMA_IEN).
-- The DMA controller is able to transfer data from the SRAM, PCI space and
-- VMEbus to each other. For this reason source and/or destination address can
-- be incremented or not depending on the settings. The source and destination
-- address must be 8-byte aligned to each other.
-- The scatter-gather list is located in the local SRAM area, so a DMA can also
-- be initiated by an external VME master by accessing the SRAM via A24/A32
-- slave and the DMA Status Register via A16 slave.
-- If transfers to PCI space has to be done, the used memory space must be
-- allocated for this function in order to prevent data mismatch!
-- If DMA functionality is used, the entire local SRAM cannot be used by other
-- functions, because the buffer descriptors are located at the end of this!
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_dma
-- vme_dma_mstr
-- vme_dma_slv
-- vme_dma_arbiter
-- vme_dma_du
-- vme_dma_au
-- vme_dma_fifo
-- fifo_256x32bit
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_dma.vhd,v $
-- Revision 1.2 2013/09/12 08:45:30 mmiehling
-- added bit 8 of tga for address modifier extension (supervisory, non-privileged data/program)
--
-- Revision 1.1 2012/03/29 10:14:48 MMiehling
-- Initial Revision
--
-- Revision 1.4 2006/05/18 14:02:16 MMiehling
-- changed comment
--
-- Revision 1.1 2005/10/28 17:52:20 mmiehling
-- Initial Revision
--
-- Revision 1.3 2004/08/13 15:41:08 mmiehling
-- removed dma-slave and improved timing
--
-- Revision 1.2 2004/07/27 17:23:15 mmiehling
-- removed slave port
--
-- Revision 1.1 2004/07/15 09:28:46 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vme_dma IS
PORT (
rst : IN std_logic;
clk : IN std_logic;
irq_o : OUT std_logic;
-- vme_du
dma_sta : IN std_logic_vector(9 DOWNTO 0);
clr_dma_en : OUT std_logic;
set_dma_err : OUT std_logic;
dma_act_bd : OUT std_logic_vector(7 DOWNTO 4);
-- wb-slave
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic;
cyc_i : IN std_logic;
sel_i : IN std_logic_vector(3 DOWNTO 0);
adr_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_o : OUT std_logic_vector(31 DOWNTO 0);
-- wb-master
stb_o : OUT std_logic;
ack_i : IN std_logic;
we_o : OUT std_logic;
cti : OUT std_logic_vector(2 DOWNTO 0);
tga_o : OUT std_logic_vector(8 DOWNTO 0); -- type of dma
err_i : IN std_logic;
cyc_o_sram : OUT std_logic;
cyc_o_vme : OUT std_logic;
cyc_o_pci : OUT std_logic;
sel_o : OUT std_logic_vector(3 DOWNTO 0);
adr_o : OUT std_logic_vector(31 DOWNTO 0);
mstr_dat_o : OUT std_logic_vector(31 DOWNTO 0);
mstr_dat_i : IN std_logic_vector(31 DOWNTO 0)
);
END vme_dma;
ARCHITECTURE vme_dma_arch OF vme_dma IS
COMPONENT vme_dma_arbiter
PORT (
rst : IN std_logic;
clk : IN std_logic;
-- vme_dma_slv
slv_req : IN std_logic;
slv_ack : OUT std_logic;
-- vme_dma_mstr
mstr_req : IN std_logic;
mstr_ack : OUT std_logic;
-- result
arbit_slv : OUT std_logic -- if set, vme_dma_slv has access and vica verse
);
END COMPONENT;
COMPONENT vme_dma_slv
PORT (
rst : IN std_logic;
clk : IN std_logic;
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic;
cyc_i : IN std_logic;
slv_req : OUT std_logic;
slv_ack : IN std_logic
);
END COMPONENT;
COMPONENT vme_dma_au
PORT (
rst : IN std_logic;
clk : IN std_logic;
-- wb_signals
adr_o : OUT std_logic_vector(31 DOWNTO 0); -- adress for wb-bus
sel_o : OUT std_logic_vector(3 DOWNTO 0); -- byte enables for wb_bus
we_o : OUT std_logic; -- write/read
tga_o : OUT std_logic_vector(8 DOWNTO 0); -- type of dma
cyc_o_sram : OUT std_logic; -- chip select for sram
cyc_o_pci : OUT std_logic; -- chip select for pci
cyc_o_vme : OUT std_logic; -- chip select for vme
stb_o : IN std_logic; -- request signal for cyc switching
-- fifo
fifo_empty : in std_logic;
fifo_full : in std_logic;
-- vme_dma_mstr
sour_dest : IN std_logic; -- if set, source adress will be used, otherwise destination ad. for adr_o
inc_adr : IN std_logic; -- flag indicates when adr should be incremented (depend on sour_dest and get_bd)
get_bd : IN std_logic; -- if set, adress for next bd reading is switched to adr_o
reached_size : OUT std_logic; -- if all data from one bd was read and stored in the fifo
load_cnt : IN std_logic; -- after new bd was stored in register, counters must be loaded with new values
boundary : OUT std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_boundary : out std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_reached_size : out std_logic; -- if all data from one bd was read and stored in the fifo
clr_dma_act_bd : IN std_logic; -- clears dma_act_bd if dma_mstr has done without error or
-- when dma_err will be cleared
-- vme_dma_du
start_dma : IN std_logic; -- flag starts dma-fsm and clears counters
dma_act_bd : OUT std_logic_vector(7 DOWNTO 2); -- [7:3] = active bd number
dma_dest_adr : IN std_logic_vector(31 DOWNTO 2); -- active bd destination adress
dma_sour_adr : IN std_logic_vector(31 DOWNTO 2); -- active bd source adress
dma_sour_device : IN std_logic_vector(2 DOWNTO 0); -- selects the source device
dma_dest_device : IN std_logic_vector(2 DOWNTO 0); -- selects the destination device
dma_vme_am : IN std_logic_vector(4 DOWNTO 0); -- type of dma transmission
blk_sgl : IN std_logic; -- indicates if DMA transfer should be done as block or single accesses
inc_sour : IN std_logic; -- indicates if source adress should be incremented
inc_dest : IN std_logic; -- indicates if destination adress should be incremented
dma_size : IN std_logic_vector(15 DOWNTO 0) -- size of data package
);
END COMPONENT;
COMPONENT vme_dma_du
PORT (
rst : IN std_logic;
clk : IN std_logic;
dma_sta : IN std_logic_vector(9 DOWNTO 0);
irq_o : OUT std_logic; -- irq for cpu; asserted when done or error (if enabled)
arbit_slv : IN std_logic; -- if set, dma_slv has access and vica verse
slv_ack : IN std_logic; -- if set, write from slave side will be done
mstr_ack : IN std_logic; -- if set, write from master side will be done
-- slave signals
adr_i : IN std_logic_vector(6 DOWNTO 2);
sel_i : IN std_logic_vector(3 DOWNTO 0);
slv_dat_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_o : OUT std_logic_vector(31 DOWNTO 0);
we_i : IN std_logic;
ack_o : IN std_logic;
-- wb_master singals
adr_o : IN std_logic_vector(6 DOWNTO 2);
mstr_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- vme_dma_au
dma_act_bd : IN std_logic_vector(7 DOWNTO 4); -- active bd number
dma_dest_adr : OUT std_logic_vector(31 DOWNTO 2); -- active bd destination adress
dma_sour_adr : OUT std_logic_vector(31 DOWNTO 2); -- active bd source adress
dma_sour_device : OUT std_logic_vector(2 DOWNTO 0); -- selects the source device
dma_dest_device : OUT std_logic_vector(2 DOWNTO 0); -- selects the destination device
dma_vme_am : OUT std_logic_vector(4 DOWNTO 0); -- type of dma transmission
blk_sgl : OUT std_logic; -- indicates if DMA transfer should be done as block or single accesses
inc_sour : OUT std_logic; -- indicates if source adress should be incremented
inc_dest : OUT std_logic; -- indicates if destination adress should be incremented
dma_size : OUT std_logic_vector(15 DOWNTO 0); -- size of data package
clr_dma_act_bd : OUT std_logic; -- clears dma_act_bd if dma_mstr has done without error or
-- when dma_err will be cleared
-- dma_mstr
set_dma_err : IN std_logic; -- sets dma error bit if vme error
clr_dma_en : IN std_logic; -- clears dma en bit if dma_mstr has done
dma_en : OUT std_logic; -- starts dma_mstr, if 0 => clears dma_act_bd counter
dma_null : OUT std_logic; -- indicates the last bd
en_mstr_dat_i_reg : IN std_logic -- enable for data in
);
END COMPONENT;
COMPONENT vme_dma_mstr
PORT (
rst : IN std_logic;
clk : IN std_logic;
-- wb_master_bus
stb_o : OUT std_logic; -- request for wb_mstr_bus
ack_i : IN std_logic; -- acknoledge from wb_mstr_bus
err_i : IN std_logic; -- error answer from slave
cti : OUT std_logic_vector(2 DOWNTO 0);
-- fifo
fifo_empty : IN std_logic; -- indicates that no more data is available
fifo_full : in std_logic; -- indicates that no more data can be stored in fifo
fifo_almost_full : IN std_logic; -- indicates that only one data can be stored in the fifo
fifo_almost_empty : IN std_logic; -- indicates that only one data is stored in the fifo
fifo_wr : OUT std_logic; -- if asserted, fifo will be filled with another data
fifo_rd : OUT std_logic; -- if asserted, data will be read out from fifo
-- vme_dma_au
sour_dest : OUT std_logic; -- if set, source adress will be used, otherwise destination ad. for adr_o
inc_adr : OUT std_logic; -- flag indicates when adr should be incremented (depend on sour_dest and get_bd)
get_bd : OUT std_logic; -- if set, adress for next bd reading is switched to adr_o
reached_size : IN std_logic; -- if all data from one bd was read and stored in the fifo
dma_act_bd : IN std_logic_vector(7 DOWNTO 2); -- [7:3] = active bd number
load_cnt : OUT std_logic; -- after new bd was stored in register, counters must be loaded with new values
boundary : IN std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_boundary : IN std_logic; -- indicates 256 byte boundary if D16 or D32 burst
almost_reached_size : IN std_logic; -- if all data from one bd was read and stored in the fifo
we_o_int : IN std_logic;
-- vme_dma_du
start_dma : IN std_logic; -- flag starts dma-fsm and clears counters
set_dma_err : OUT std_logic; -- sets dma error bit if vme error
clr_dma_en : OUT std_logic; -- clears dma en bit if dma_mstr has done
dma_en : IN std_logic; -- starts dma_mstr, if 0 => clears dma_act_bd counter
dma_null : IN std_logic; -- indicates the last bd
en_mstr_dat_i_reg : OUT std_logic; -- enable for data in
inc_sour : IN std_logic; -- indicates if source adress should be incremented
inc_dest : IN std_logic; -- indicates if destination adress should be incremented
dma_size : IN std_logic_vector(15 DOWNTO 0); -- size of data package
-- arbiter
mstr_req : OUT std_logic -- request for internal register access
);
END COMPONENT;
COMPONENT vme_dma_fifo
PORT (
rst : IN std_logic;
clk : IN std_logic;
fifo_clr : IN std_logic;
fifo_wr : IN std_logic;
fifo_rd : IN std_logic;
fifo_dat_i : IN std_logic_vector(31 DOWNTO 0);
fifo_dat_o : OUT std_logic_vector(31 DOWNTO 0);
fifo_almost_full : OUT std_logic;
fifo_almost_empty : OUT std_logic;
fifo_full : OUT std_logic;
fifo_empty : OUT std_logic
);
END COMPONENT;
-- fifo
SIGNAL fifo_almost_full : std_logic;
SIGNAL fifo_almost_empty : std_logic;
SIGNAL fifo_empty : std_logic;
SIGNAL fifo_full : std_logic;
-- slv
SIGNAL slv_req : std_logic;
SIGNAL ack_o_int : std_logic;
-- arbiter
SIGNAL slv_ack : std_logic;
SIGNAL mstr_ack : std_logic;
SIGNAL arbit_slv : std_logic;
-- mstr
SIGNAL fifo_wr : std_logic;
SIGNAL fifo_rd : std_logic;
SIGNAL sour_dest : std_logic;
SIGNAL inc_adr : std_logic;
SIGNAL get_bd : std_logic;
SIGNAL load_cnt : std_logic;
SIGNAL set_dma_err_int : std_logic;
SIGNAL clr_dma_en_int : std_logic;
SIGNAL en_mstr_dat_i_reg : std_logic;
SIGNAL mstr_req : std_logic;
SIGNAL stb_o_int : std_logic;
-- du
SIGNAL dma_dest_adr : std_logic_vector(31 DOWNTO 2);
SIGNAL dma_sour_adr : std_logic_vector(31 DOWNTO 2);
SIGNAL dma_sour_device : std_logic_vector(2 DOWNTO 0);
SIGNAL dma_dest_device : std_logic_vector(2 DOWNTO 0);
SIGNAL dma_vme_am : std_logic_vector(4 DOWNTO 0);
SIGNAL blk_sgl : std_logic;
SIGNAL inc_sour : std_logic;
SIGNAL inc_dest : std_logic;
SIGNAL dma_size : std_logic_vector(15 DOWNTO 0);
SIGNAL start_dma : std_logic;
SIGNAL clr_fifo : std_logic;
SIGNAL dma_en : std_logic;
SIGNAL dma_null : std_logic;
SIGNAL clr_dma_act_bd : std_logic;
-- au
SIGNAL adr_o_int : std_logic_vector(31 DOWNTO 0);
SIGNAL reached_size : std_logic;
SIGNAL almost_reached_size : std_logic;
SIGNAL dma_act_bd_int : std_logic_vector(7 DOWNTO 2);
SIGNAL boundary : std_logic;
SIGNAL almost_boundary : std_logic;
SIGNAL we_o_int : std_logic;
BEGIN
adr_o <= adr_o_int;
ack_o <= ack_o_int;
stb_o <= stb_o_int;
we_o <= we_o_int;
clr_dma_en <= clr_dma_en_int;
set_dma_err <= set_dma_err_int;
dma_act_bd <= dma_act_bd_int(7 DOWNTO 4);
clr_fifo <= start_dma;
start_dma <= dma_sta(8);
dma_arb: vme_dma_arbiter
PORT MAP (
rst => rst ,
clk => clk ,
slv_req => slv_req ,
slv_ack => slv_ack ,
mstr_req => mstr_req ,
mstr_ack => mstr_ack ,
arbit_slv => arbit_slv
);
dma_slv: vme_dma_slv
PORT MAP (
rst => rst ,
clk => clk ,
stb_i => stb_i ,
ack_o => ack_o_int ,
we_i => we_i ,
cyc_i => cyc_i ,
slv_req => slv_req ,
slv_ack => slv_ack
);
dma_au: vme_dma_au
PORT MAP (
rst => rst ,
clk => clk ,
adr_o => adr_o_int ,
sel_o => sel_o ,
tga_o => tga_o,
we_o => we_o_int ,
boundary => boundary,
almost_boundary => almost_boundary,
cyc_o_sram => cyc_o_sram ,
cyc_o_pci => cyc_o_pci ,
cyc_o_vme => cyc_o_vme ,
stb_o => stb_o_int,
fifo_empty => fifo_empty,
fifo_full => fifo_full,
clr_dma_act_bd => clr_dma_act_bd,
sour_dest => sour_dest ,
inc_adr => inc_adr ,
get_bd => get_bd ,
reached_size => reached_size ,
almost_reached_size => almost_reached_size ,
load_cnt => load_cnt ,
start_dma => start_dma ,
dma_act_bd => dma_act_bd_int ,
dma_dest_adr => dma_dest_adr ,
dma_sour_adr => dma_sour_adr ,
dma_sour_device => dma_sour_device,
dma_dest_device => dma_dest_device,
dma_vme_am => dma_vme_am ,
blk_sgl => blk_sgl,
inc_sour => inc_sour ,
inc_dest => inc_dest ,
dma_size => dma_size
);
dma_du: vme_dma_du
PORT MAP (
rst => rst ,
clk => clk ,
dma_sta => dma_sta,
irq_o => irq_o ,
arbit_slv => arbit_slv ,
slv_ack => slv_ack ,
mstr_ack => mstr_ack ,
ack_o => ack_o_int ,
we_i => we_i,
adr_i => adr_i(6 DOWNTO 2) ,
sel_i => sel_i ,
slv_dat_i => slv_dat_i ,
slv_dat_o => slv_dat_o ,
clr_dma_act_bd => clr_dma_act_bd,
adr_o => adr_o_int(6 DOWNTO 2) ,
mstr_dat_i => mstr_dat_i ,
dma_act_bd => dma_act_bd_int(7 DOWNTO 4) ,
dma_dest_adr => dma_dest_adr ,
dma_sour_adr => dma_sour_adr ,
dma_sour_device => dma_sour_device ,
dma_dest_device => dma_dest_device ,
dma_vme_am => dma_vme_am ,
blk_sgl => blk_sgl,
inc_sour => inc_sour ,
inc_dest => inc_dest ,
dma_size => dma_size ,
-- start_dma => start_dma ,
set_dma_err => set_dma_err_int ,
clr_dma_en => clr_dma_en_int ,
dma_en => dma_en ,
dma_null => dma_null ,
en_mstr_dat_i_reg => en_mstr_dat_i_reg
);
dma_mstr: vme_dma_mstr
PORT MAP (
rst => rst ,
clk => clk ,
stb_o => stb_o_int ,
ack_i => ack_i ,
err_i => err_i ,
cti => cti,
fifo_empty => fifo_empty ,
fifo_full => fifo_full,
fifo_almost_full => fifo_almost_full ,
fifo_almost_empty => fifo_almost_empty ,
fifo_wr => fifo_wr ,
fifo_rd => fifo_rd ,
boundary => boundary,
almost_boundary => almost_boundary,
we_o_int => we_o_int,
sour_dest => sour_dest ,
inc_adr => inc_adr ,
get_bd => get_bd ,
reached_size => reached_size ,
almost_reached_size => almost_reached_size ,
dma_act_bd => dma_act_bd_int ,
load_cnt => load_cnt ,
start_dma => start_dma ,
set_dma_err => set_dma_err_int ,
clr_dma_en => clr_dma_en_int ,
dma_en => dma_en ,
inc_sour => inc_sour,
inc_dest => inc_dest,
dma_size => dma_size,
dma_null => dma_null ,
en_mstr_dat_i_reg => en_mstr_dat_i_reg ,
mstr_req => mstr_req
);
dma_fifo: vme_dma_fifo
PORT MAP (
rst => rst ,
clk => clk ,
fifo_clr => clr_fifo,
fifo_wr => fifo_wr ,
fifo_rd => fifo_rd ,
fifo_dat_i => mstr_dat_i ,
fifo_dat_o => mstr_dat_o ,
fifo_almost_full => fifo_almost_full ,
fifo_almost_empty => fifo_almost_empty,
fifo_full => fifo_full ,
fifo_empty => fifo_empty
);
END vme_dma_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity lshiftLEDs is
Port ( trigger : in STD_LOGIC;
leds : out STD_LOGIC_VECTOR (7 downto 0));
end lshiftLEDs;
architecture Behavioral of lshiftLEDs is
signal ileds : std_logic_vector(7 downto 0) := "00000001";
begin
leds <= ileds;
process(trigger)
begin
if rising_edge(trigger) then
ileds <= ileds(6 downto 0) & ileds(7);
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : Pipeline
-- Project :
-------------------------------------------------------------------------------
-- File : pipeline.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-06-10
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Pipeline with configurable width and depth
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-06-10 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity pipeline is
generic (
g_width : natural := 32;
g_depth : natural := 2
);
port (
data_i : in std_logic_vector(g_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
data_o : out std_logic_vector(g_width-1 downto 0)
);
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of pipeline : entity is "no";
end entity pipeline;
-------------------------------------------------------------------------------
architecture str of pipeline is
type slv_array is array(g_depth-1 downto 0) of std_logic_vector(g_width-1 downto 0);
signal pipe : slv_array;
begin -- architecture str
process(clk_i)
begin
if rising_edge(clk_i) then
if ce_i = '1' then
pipe(0) <= data_i;
for n in 1 to g_depth-1 loop
pipe(n) <= pipe(n-1);
end loop;
end if; --ce_i
end if; --clk_i
end process;
data_o <= pipe(g_depth-1);
end architecture str;
-------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: testlib
-- file: testlib.vhd
-- author: Marko Isomaki - Aeroflex Gaisler
-- description: package for common vhdl functions for testbenches
------------------------------------------------------------------------------
-- pragma translate_off
library std;
use std.standard.all;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library grlib;
use grlib.stdio.all;
use grlib.stdlib.tost;
-- pragma translate_on
package testlib is
-- pragma translate_off
type octet_vector is array (natural range <>) of std_logic_vector(7 downto 0);
subtype data_vector8 is octet_vector;
type data_vector16 is array (natural range <>) of std_logic_vector(15 downto 0);
type data_vector32 is array (natural range <>) of std_logic_vector(31 downto 0);
type data_vector64 is array (natural range <>) of std_logic_vector(63 downto 0);
type data_vector128 is array (natural range <>) of std_logic_vector(127 downto 0);
type data_vector256 is array (natural range <>) of std_logic_vector(255 downto 0);
type nibble_vector is array (natural range <>) of std_logic_vector(3 downto 0);
subtype data_vector is data_vector32;
-----------------------------------------------------------------------------
-- compare function handling '-'. c is the expected data parameter. If it is
--'-' or 'U' then this bit is not compared. Returns true if the vectors match
-----------------------------------------------------------------------------
function compare(o, c: in std_logic_vector) return boolean;
-----------------------------------------------------------------------------
-- compare function handling '-'
-----------------------------------------------------------------------------
function compare(o, c: in std_ulogic_vector) return boolean;
-----------------------------------------------------------------------------
-- this procedure prints a message to standard output. Also includes the time
-- at which it occurs.
-----------------------------------------------------------------------------
procedure print(
constant comment: in string := "-";
constant severe: in severity_level := note;
constant screen: in boolean := true);
-----------------------------------------------------------------------------
-- synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure synchronise(
signal clock: in std_ulogic;
constant offset: in time := 5 ns;
constant enable: in boolean := true);
-----------------------------------------------------------------------------
-- this procedure initialises the test error counters. Used in testbenches
-- with a test variable to check if a subtest has failed and at the end how
-- many subtests have failed. This procedure is called before the first
-- subtest
-----------------------------------------------------------------------------
procedure tinitialise(
variable test: inout boolean;
variable testcount: inout integer);
-----------------------------------------------------------------------------
-- this procedure completes the sub-test. Called at the end of each subtest
-----------------------------------------------------------------------------
procedure tintermediate(
variable test: inout boolean;
variable testcount: inout integer);
-----------------------------------------------------------------------------
-- this procedure completes the test. Called at the end of the complete test
-----------------------------------------------------------------------------
procedure tterminate(
variable test: inout boolean;
variable testcount: inout integer);
-----------------------------------------------------------------------------
-- check std_logic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic_vector;
constant expected: in std_logic_vector;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check std_logic
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic;
constant expected: in std_logic;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check std_ulogic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_ulogic_vector;
constant expected: in std_ulogic_vector;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check natural
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in natural;
constant expected: in natural;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check time
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in time;
constant expected: in time;
constant spread: in time;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check boolean
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in boolean;
constant expected: in boolean;
constant message: in string := "");
-----------------------------------------------------------------------------
-- Convert Data_Vector to Octet_Vector
-----------------------------------------------------------------------------
function conv_octet_vector(
constant d: in data_vector)
return octet_vector;
-----------------------------------------------------------------------------
-- Convert Octet_Vector to Data_Vector, with padding
-----------------------------------------------------------------------------
function conv_data_vector(
constant o: in octet_vector)
return data_vector;
procedure compare(
constant data: in octet_vector;
constant cxdata: in octet_vector;
variable tP: inout boolean);
----------------------------------------------------------------------------
-- Read file contents to octet vector
----------------------------------------------------------------------------
--Expects data only in hex with four bytes on each line.
procedure readfile(
constant filename: in string := "";
constant filetype: in integer := 0;
constant size: in integer := 0;
variable dataout: out octet_vector);
--Reads bytes from a file with the format packets are output from ethereal
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out octet_vector);
----------------------------------------------------------------------------
-- Read file contents to data_vector
----------------------------------------------------------------------------
--Expects data only in hex with four bytes on each line.
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out data_vector);
--generates an random integer from 0 to the maximum value specified with max
procedure gen_rand_int(
constant max : in real;
variable seed1 : inout positive;
variable seed2 : inout positive;
variable rand : out integer);
--reverses std_logic_vector
function reverse(din : std_logic_vector) return std_logic_vector;
-- Returns offset to start of valid data for an access of size 'size' in
-- AMBA data vector
function ahb_doff (
constant dw : integer;
constant size : integer; -- access size
constant addr : std_logic_vector(4 downto 0))
return integer;
-- pragma translate_on
end package testlib;
-- pragma translate_off
--============================================================================--
package body testlib is
-----------------------------------------------------------------------------
-- compare function handling '-'
-----------------------------------------------------------------------------
function compare(o, c: in std_logic_vector) return boolean is
variable t: std_logic_vector(o'range) := c;
variable result: boolean;
begin
result := true;
for i in o'range loop
if not (o(i)=t(i) or t(i)='-' or t(i)='U') then
result := false;
end if;
end loop;
return result;
end function compare;
-----------------------------------------------------------------------------
-- compare function handling '-'
-----------------------------------------------------------------------------
function compare(o, c: in std_ulogic_vector) return boolean is
variable t: std_ulogic_vector(o'range) := c;
variable result: boolean;
begin
result := true;
for i in o'range loop
if not (o(i)=t(i) or t(i)='-' or t(i)='U') then
result := false;
end if;
end loop;
return result;
end function compare;
-----------------------------------------------------------------------------
-- this procedure prints a message to standard output
-----------------------------------------------------------------------------
procedure print(
constant comment: in string := "-";
constant severe: in severity_level := note;
constant screen: in boolean := true) is
variable l: line;
begin
if screen then
write(l, now, right, 15);
write(l, " : " & comment);
if severe = warning then
write(l, string'(" # warning, "));
elsif severe = error then
write(l, string'(" # error, "));
elsif severe = failure then
write(l, string'(" # failure, "));
end if;
writeline(output, l);
end if;
end procedure print;
-----------------------------------------------------------------------------
-- synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure synchronise(
signal clock: in std_ulogic;
constant offset: in time := 5 ns;
constant enable: in boolean := true) is
begin
if enable then
wait until clock = '1'; -- synchronise
wait for offset; -- output offset delay
end if;
end procedure synchronise;
-----------------------------------------------------------------------------
-- this procedure initialises the test error counters
-----------------------------------------------------------------------------
procedure tinitialise(
variable test: inout boolean;
variable testcount: inout integer) is
begin
--------------------------------------------------------------------------
-- initialise test status
--------------------------------------------------------------------------
test := true; -- reset any errors
testcount := 0;
print("--=========================================================--");
print("*** test initialised ***");
print("--=========================================================--");
end procedure tinitialise;
-----------------------------------------------------------------------------
-- this procedure completes the sub-test
-----------------------------------------------------------------------------
procedure tintermediate(
variable test: inout boolean;
variable testcount: inout integer) is
variable l: line;
begin
--------------------------------------------------------------------------
-- report test status
--------------------------------------------------------------------------
wait for 10 us;
print("--=========================================================--");
if test then
print("*** sub-test completed successfully ***");
if testcount > 0 then
write(l, now, right, 15);
write(l, string'(" : "));
write(l, testcount);
write(l, string'(" sub-test(s) ended with one or more errors."));
writeline(output, l);
end if;
else
print("*** sub-test completed with errors -- # error # -- ***");
testcount := testcount + 1;
test := true;
if testcount > 0 then
write(l, now, right, 15);
write(l, string'(" : "));
write(l, testcount);
write(l, string'(" sub-test(s) ended with one or more errors."));
writeline(output, l);
end if;
end if;
print("--=========================================================--");
end procedure tintermediate;
-----------------------------------------------------------------------------
-- this procedure completes the test
-----------------------------------------------------------------------------
procedure tterminate(
variable test: inout boolean;
variable testcount: inout integer) is
variable l: line;
begin
--------------------------------------------------------------------------
-- end of test
--------------------------------------------------------------------------
wait for 1 ms;
print("--=========================================================--");
if testcount = 0 then
print("*** test completed successfully ***");
else
print("*** test completed with errors -- # error # -- ***");
write(l, now, right, 15);
write(l, string'(" : "));
write(l, testcount);
write(l, string'(" sub-test(s) ended with one or more errors."));
writeline(output, l);
end if;
print("--=========================================================--");
report "---- end of test ----"
severity failure;
wait;
end procedure tterminate;
-----------------------------------------------------------------------------
-- check std_logic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic_vector;
constant expected: in std_logic_vector;
constant message: in string := "") is
variable l: line;
constant padding: std_logic_vector(1 to
(4-(received'length mod 4))) :=
(others => '0');
begin
if not compare(received, expected) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, padding & std_logic_vector(received));
else
hwrite(l, std_logic_vector(received));
end if;
write(l, string'(" expected: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, padding & std_logic_vector(expected));
else
hwrite(l, std_logic_vector(expected));
end if;
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check std_logic
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic;
constant expected: in std_logic;
constant message: in string := "") is
variable l: line;
begin
if not (to_x01z(received)=to_x01z(expected)) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check std_ulogic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_ulogic_vector;
constant expected: in std_ulogic_vector;
constant message: in string := "") is
variable l: line;
constant padding: std_ulogic_vector(1 to
(4-(received'length mod 4))) :=
(others => '0');
begin
if not compare(received, expected) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, std_logic_vector(padding) & std_logic_vector(received));
else
hwrite(l, std_logic_vector(received));
end if;
write(l, string'(" expected: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, std_logic_vector(padding) & std_logic_vector(expected));
else
hwrite(l, std_logic_vector(expected));
end if;
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check natural
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in natural;
constant expected: in natural;
constant message: in string := "") is
variable l: line;
begin
if received /= expected then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check time
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in time;
constant expected: in time;
constant spread: in time;
constant message: in string := "") is
variable l: line;
begin
if (received > expected+spread) or
(received < expected-spread) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check boolean
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in boolean;
constant expected: in boolean;
constant message: in string := "") is
variable l: line;
begin
if received /= expected then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- Convert Data_Vector to Octet_Vector
-----------------------------------------------------------------------------
function conv_octet_vector(
constant d: in data_vector)
return octet_vector is
variable o: octet_vector(0 to d'Length*4-1);
begin
for i in o'range loop
o(i) := d(i/4)((3-(i mod 4))*8+7 downto (3-(i mod 4))*8);
end loop;
return o;
end function conv_octet_vector;
-----------------------------------------------------------------------------
-- Convert Octet_Vector to Data_Vector, with padding
-----------------------------------------------------------------------------
function conv_data_vector(
constant o: in octet_vector)
return data_vector is
variable d: data_vector(0 to (1+(o'Length-1)/4)-1);
begin
for i in o'Range loop
d(i/4)((3-(i mod 4))*8+7 downto (3-(i mod 4))*8) := o(i);
end loop;
return d;
end function conv_data_vector;
procedure compare(
constant data: in octet_vector;
constant cxdata: in octet_vector;
variable tp: inout boolean) is
begin
if (data'length /= cxdata'length) then
tp := false;
print("compare error: lengths do not match");
else
for i in data'low to data'low+data'length-1 loop
if not compare(data(i), cxdata(i)) then
tp := false;
print("compare error. index: " & tost(i) & " data: " & tost(data(i)) & " expected: " & tost(cxdata(i)));
end if;
end loop;
end if;
end compare;
function FromChar(C: Character) return Std_Logic_Vector is
variable R: Std_Logic_Vector(0 to 3);
begin
case C is
when '0' => R := "0000";
when '1' => R := "0001";
when '2' => R := "0010";
when '3' => R := "0011";
when '4' => R := "0100";
when '5' => R := "0101";
when '6' => R := "0110";
when '7' => R := "0111";
when '8' => R := "1000";
when '9' => R := "1001";
when 'A' => R := "1010";
when 'B' => R := "1011";
when 'C' => R := "1100";
when 'D' => R := "1101";
when 'E' => R := "1110";
when 'F' => R := "1111";
when 'a' => R := "1010";
when 'b' => R := "1011";
when 'c' => R := "1100";
when 'd' => R := "1101";
when 'e' => R := "1110";
when 'f' => R := "1111";
when others => R := "XXXX";
end case;
return R;
end FromChar;
procedure readfile(
constant filename: in string := "";
constant filetype: in integer := 0;
constant size: in integer := 0;
variable dataout: out octet_vector) is
file readfile: text;
variable l: line;
variable test: boolean := true;
variable count: integer := 0;
variable dtmp: std_logic_vector(31 downto 0);
variable data: octet_vector(0 to size-1);
variable i: integer := 0;
variable good: boolean := true;
variable c: character;
begin
if size /= 0 then
if filename = "" then
print("no file given");
else
if filetype = 0 then
file_open(readfile, filename, read_mode);
while not endfile(readfile) loop
readline(readfile, l);
hread(l, dtmp, test);
if (not test) then
print("illegal data in file");
exit;
end if;
for i in 0 to 3 loop
data(count) := dtmp(31-i*8 downto 24-i*8);
count := count + 1;
if count >= size then
exit;
end if;
end loop;
if count >= size then
exit;
end if;
end loop;
if count < size then
print("not enough data in file");
else
for i in 0 to size-1 loop
dataout(dataout'low+i) := data(i);
end loop;
end if;
else
file_open(readfile, filename, read_mode);
while not endfile(readfile) loop
readline(readfile, L);
while (i < 4) loop
Read(L, C, good);
if not good then
Print("Error in read data");
exit;
end if;
if (C = character'val(32)) or (C = character'val(160)) or (C = HT) then
next;
else
i := i + 1;
end if;
end loop;
i := 0;
while (i < 32) loop
Read(L, C, good);
if not good then
Print("Error in read data");
exit;
end if;
if (C = character'val(32)) or (C = character'val(160)) or (C = HT) then
next;
else
if (i mod 2) = 0 then
data(count)(7 downto 4) := fromchar(C);
else
data(count)(3 downto 0) := fromchar(C);
-- Print(tost(data(count)));
count := count + 1;
if count >= size then
exit;
end if;
end if;
i := i + 1;
end if;
end loop;
i := 0;
end loop;
if count < size then
Print("Not enough data in file");
else
dataout := data;
end if;
end if;
end if;
else
print("size is zero. no data read");
end if;
end procedure;
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out octet_vector) is
begin
readfile(filename, 0, size, dataout);
end procedure;
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out data_vector) is
file readfile: text;
variable l: line;
variable test: boolean := true;
variable count: integer := 0;
variable data: data_vector(0 to size/4);
begin
if size /= 0 then
if filename = "" then
print("no file given");
else
file_open(readfile, filename, read_mode);
while not endfile(readfile) loop
readline(readfile, l);
hread(l, data(count/4), test);
if (not test) then
print("illegal data in file");
exit;
end if;
count := count + 4;
if count >= size then
exit;
end if;
end loop;
if count < size then
print("not enough data in file");
else
if (size mod 4) = 0 then
dataout(dataout'low to dataout'low+data'high-1) :=
data(0 to data'high-1);
else
dataout(dataout'low to dataout'low+data'high) := data(0 to data'high);
end if;
end if;
end if;
else
print("size is zero. no data read");
end if;
end procedure;
procedure gen_rand_int(
constant max : in real;
variable seed1 : inout positive;
variable seed2 : inout positive;
variable rand : out integer) is
variable rand_tmp : real;
begin
uniform(seed1, seed2, rand_tmp);
rand := integer(floor(rand_tmp*max));
end procedure;
function reverse(din : std_logic_vector)
return std_logic_vector is
variable dout: std_logic_vector(din'REVERSE_RANGE);
begin
for i in din'RANGE loop dout(i) := din(i); end loop;
return dout;
end function reverse;
function ahb_doff (
constant dw : integer;
constant size : integer;
constant addr : std_logic_vector(4 downto 0))
return integer is
variable off : integer;
begin -- ahb_doff
if size < 256 and dw = 256 and addr(4) = '0' then off := 128; else off := 0; end if;
if size < 128 and dw >= 128 and addr(3) = '0' then off := off + 64; end if;
if size < 64 and dw >= 64 and addr(2) = '0' then off := off + 32; end if;
if size < 32 and addr(1) = '0' then off := off + 16; end if;
if size < 16 and addr(0) = '0' then off := off + 8; end if;
return off;
end ahb_doff;
end package body ; --=======================================--
-- pragma translate_on
|
entity test is
end test;
architecture only of test is
type integer_array is array ( natural range <> ) of integer;
function return_biggest ( inputs : integer_array )
return integer is
variable retval : integer := integer'left;
begin
for i in inputs'range loop
if inputs(i) > retval then
retval := inputs(i);
end if;
end loop; -- i
return retval;
end return_biggest;
subtype biggest_wins is return_biggest integer;
signal common : biggest_wins;
begin -- only
p1 : process
begin
common <= 1 after 1 ns;
wait;
end process;
p2 : process
begin
common <= 1 after 1 ns;
wait;
end process;
test: process
begin
wait for 2 ns;
assert common = 1 report "TEST FAILED" severity failure;
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
type integer_array is array ( natural range <> ) of integer;
function return_biggest ( inputs : integer_array )
return integer is
variable retval : integer := integer'left;
begin
for i in inputs'range loop
if inputs(i) > retval then
retval := inputs(i);
end if;
end loop; -- i
return retval;
end return_biggest;
subtype biggest_wins is return_biggest integer;
signal common : biggest_wins;
begin -- only
p1 : process
begin
common <= 1 after 1 ns;
wait;
end process;
p2 : process
begin
common <= 1 after 1 ns;
wait;
end process;
test: process
begin
wait for 2 ns;
assert common = 1 report "TEST FAILED" severity failure;
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
type integer_array is array ( natural range <> ) of integer;
function return_biggest ( inputs : integer_array )
return integer is
variable retval : integer := integer'left;
begin
for i in inputs'range loop
if inputs(i) > retval then
retval := inputs(i);
end if;
end loop; -- i
return retval;
end return_biggest;
subtype biggest_wins is return_biggest integer;
signal common : biggest_wins;
begin -- only
p1 : process
begin
common <= 1 after 1 ns;
wait;
end process;
p2 : process
begin
common <= 1 after 1 ns;
wait;
end process;
test: process
begin
wait for 2 ns;
assert common = 1 report "TEST FAILED" severity failure;
wait;
end process;
end only;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc417.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00417ent IS
END c03s02b01x01p19n01i00417ent;
ARCHITECTURE c03s02b01x01p19n01i00417arch OF c03s02b01x01p19n01i00417ent IS
type real_cons_vector is array (15 downto 0) of real;
constant C1 : real_cons_vector := (others => 3.0);
function complex_scalar(s : real_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return real_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : real_cons_vector;
signal S2 : real_cons_vector;
signal S3 : real_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00417"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00417 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00417arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc417.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00417ent IS
END c03s02b01x01p19n01i00417ent;
ARCHITECTURE c03s02b01x01p19n01i00417arch OF c03s02b01x01p19n01i00417ent IS
type real_cons_vector is array (15 downto 0) of real;
constant C1 : real_cons_vector := (others => 3.0);
function complex_scalar(s : real_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return real_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : real_cons_vector;
signal S2 : real_cons_vector;
signal S3 : real_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00417"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00417 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00417arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc417.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00417ent IS
END c03s02b01x01p19n01i00417ent;
ARCHITECTURE c03s02b01x01p19n01i00417arch OF c03s02b01x01p19n01i00417ent IS
type real_cons_vector is array (15 downto 0) of real;
constant C1 : real_cons_vector := (others => 3.0);
function complex_scalar(s : real_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return real_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : real_cons_vector;
signal S2 : real_cons_vector;
signal S3 : real_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00417"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00417 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00417arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Q8_4_ADD is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of Q8_4_ADD is
begin
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE OP1 : SIGNED(8 downto 0);
VARIABLE OP2 : SIGNED(8 downto 0);
VARIABLE OP3 : SIGNED(8 downto 0);
begin
OP1 := SIGNED( INPUT_1(7) & INPUT_1(7 downto 0) );
OP2 := SIGNED( INPUT_2(7) & INPUT_2(7 downto 0) );
OP3 := OP1 + OP2;
if( OP3 > TO_SIGNED(127, 8) ) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR(TO_SIGNED( 127, 32));
elsif( OP3 < TO_SIGNED(-128, 8) ) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR(TO_SIGNED(-128, 32));
else
OUTPUT_1 <= STD_LOGIC_VECTOR( RESIZE( OP3(7 downto 0), 32) );
end if;
END PROCESS;
-------------------------------------------------------------------------
end;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxtstr.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
configuration dlx_test_rtl of dlx_test is
for bench
for cg : clock_gen
use entity work.clock_gen(behavior)
generic map ( Tpw => 8 ns, Tps => 2 ns );
end for;
for mem : memory
use entity work.memory(preloaded)
generic map ( mem_size => 65536,
Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
end for;
for proc : dlx
use configuration work.dlx_rtl
generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
end for;
end for; -- bench of dlx_test
end configuration dlx_test_rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxtstr.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
configuration dlx_test_rtl of dlx_test is
for bench
for cg : clock_gen
use entity work.clock_gen(behavior)
generic map ( Tpw => 8 ns, Tps => 2 ns );
end for;
for mem : memory
use entity work.memory(preloaded)
generic map ( mem_size => 65536,
Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
end for;
for proc : dlx
use configuration work.dlx_rtl
generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
end for;
end for; -- bench of dlx_test
end configuration dlx_test_rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxtstr.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
configuration dlx_test_rtl of dlx_test is
for bench
for cg : clock_gen
use entity work.clock_gen(behavior)
generic map ( Tpw => 8 ns, Tps => 2 ns );
end for;
for mem : memory
use entity work.memory(preloaded)
generic map ( mem_size => 65536,
Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
end for;
for proc : dlx
use configuration work.dlx_rtl
generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
end for;
end for; -- bench of dlx_test
end configuration dlx_test_rtl;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- Dummy Cache Replacement Algorithm for Direct-Mapped Caches
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_l1mem_data_cache_replace_none_pkg.all;
entity cpu_l1mem_data_cache_replace_none is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_l1mem_data_cache_replace_none_ctrl_in : in cpu_l1mem_data_cache_replace_none_ctrl_in_type;
cpu_l1mem_data_cache_replace_none_ctrl_out : out cpu_l1mem_data_cache_replace_none_ctrl_out_type;
cpu_l1mem_data_cache_replace_none_dp_in : in cpu_l1mem_data_cache_replace_none_dp_in_type;
cpu_l1mem_data_cache_replace_none_dp_out : out cpu_l1mem_data_cache_replace_none_dp_out_type
);
end;
|
library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
-- 4 axis version with 48 I/O bits
entity HostMot5_4 is
port
(
LRD: in STD_LOGIC;
LWR: in STD_LOGIC;
LW_R: in STD_LOGIC;
ALE: in STD_LOGIC;
ADS: in STD_LOGIC;
BLAST: in STD_LOGIC;
WAITO: in STD_LOGIC;
LOCKO: in STD_LOGIC;
CS0: in STD_LOGIC;
CS1: in STD_LOGIC;
READY: out STD_LOGIC;
INT: out STD_LOGIC;
LAD: inout STD_LOGIC_VECTOR (31 downto 0); -- data/address bus
LA: in STD_LOGIC_VECTOR (8 downto 2); -- non-muxed address bus
lBE: in STD_LOGIC_VECTOR (3 downto 0); -- byte enables
SYNCLK: in STD_LOGIC;
LCLK: in STD_LOGIC;
-- I/O signals
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
IDX: in STD_LOGIC_VECTOR (3 downto 0);
PWM: inout STD_LOGIC_VECTOR (3 downto 0);
ENA: out STD_LOGIC_VECTOR (3 downto 0);
DIR: inout STD_LOGIC_VECTOR (3 downto 0);
IOBITSA: inout STD_LOGIC_VECTOR (23 downto 0);
IOBITSB: inout STD_LOGIC_VECTOR (23 downto 0);
-- led bits
LEDS: out STD_LOGIC_VECTOR(7 downto 0)
);
end HostMot5_4; -- for 5I20 or 4I65
architecture dataflow of Hostmot5_4 is
alias BLE: STD_LOGIC is LBE(0); -- 16 bit mode
alias BHE: STD_LOGIC is LBE(3); -- 16 bit mode
alias LA1: STD_LOGIC is LBE(1); -- 8/16 bit mode
alias LA0: STD_LOGIC is LBE(0); -- 8 bit mode
-- misc global signals --
signal D: STD_LOGIC_VECTOR (31 downto 0); -- internal data bus
signal LatchedA: STD_LOGIC_VECTOR (15 downto 0);
signal LatchedLBE: STD_LOGIC_VECTOR (3 downto 0);
signal PreFastRead: STD_LOGIC;
signal FastRead: STD_LOGIC;
-- Version specific constants --
constant counters :integer := 4;
constant HMID : STD_LOGIC_VECTOR (31 downto 0) := x"AA010004"; -- MSW = rev 1, LSW = 4 axis
constant MasterClock : STD_LOGIC_VECTOR (31 downto 0) := x"01FCA055"; -- = 33.3333 MHz
-- misc global signals --
signal CardSelect: STD_LOGIC; -- card select decode
signal LEDView: STD_LOGIC_VECTOR (7 downto 0); -- index register
-- irq related signals
signal IRQSource: STD_LOGIC;
signal IRQLatch: STD_LOGIC;
signal IRQMask: STD_LOGIC;
signal MissedIRQ: STD_LOGIC;
signal StopOnMissedIRQ: STD_LOGIC;
signal ClearMissedIRQ: STD_LOGIC;
signal LatchOnInterrupt: STD_LOGIC;
-- timeout related signals
signal ReloadWDCmd: STD_LOGIC;
signal StopOnTimeout: STD_LOGIC;
signal WDTimeOut: STD_LOGIC;
-- LEDView and id reg signals
signal LoadLEDViewCmd: STD_LOGIC;
signal ReadLEDViewCmd: STD_LOGIC;
signal Enasigs :STD_LOGIC_VECTOR (counters-1 downto 0);
signal IDSel: STD_LOGIC;
signal ReadIDCmd: STD_LOGIC;
signal MCSel: STD_LOGIC;
signal ReadMCCmd: STD_LOGIC;
-- irqdiv reg signals
signal ReadIRQDivCmd: STD_LOGIC;
signal LoadIRQDivCmd: STD_LOGIC;
signal ClearIRQCmd: STD_LOGIC;
-- irq sel reg signals
signal loadGCRCmd: STD_LOGIC;
signal LoadGMRCmd: STD_LOGIC;
signal ReadGMRCmd: STD_LOGIC;
-- timeout reg signals
signal loadTimeoutCmd: STD_LOGIC;
signal ReadTimeoutCmd: STD_LOGIC;
signal ReadTimerCmd: STD_LOGIC;
-- phase accumulator signals
signal ReadPhaseCmd: STD_LOGIC;
signal LoadPhaseCmd: STD_LOGIC;
-- counter signals --
signal CounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal GlobalCounterEnable: STD_LOGIC; -- enable counting
signal GlobalCountLatchcmd: STD_LOGIC; -- command to latch counter value
signal GlobalCountLatch: STD_LOGIC; -- command + irq generated latch count
signal CountLatchEdge1: STD_LOGIC;
signal CountLatchEdge2: STD_LOGIC;
signal CCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal CCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
signal GlobalCounterClear: STD_LOGIC; -- clear counter
-- secondary counter signals --
signal SCounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal SCCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal SCCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
-- pwm generator signals --
signal RefCountBus: STD_LOGIC_VECTOR (9 downto 0);
signal LoadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal ReadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal GlobalPWMEnable: STD_LOGIC;
signal GlobalClearPWM: STD_LOGIC;
signal GlobalClearPWMCmd: STD_LOGIC;
signal StopPWM: STD_LOGIC;
-- misc i/o signals
signal PortASel: STD_LOGIC;
signal DDRASel: STD_LOGIC;
signal LoadPortA: STD_LOGIC;
signal LoadDDRA: STD_LOGIC;
signal ReadDDRA: STD_LOGIC;
signal ReadPortA: STD_LOGIC;
signal PortBSel: STD_LOGIC;
signal DDRBSel: STD_LOGIC;
signal LoadPortB: STD_LOGIC;
signal LoadDDRB: STD_LOGIC;
signal ReadDDRB: STD_LOGIC;
signal ReadPortB: STD_LOGIC;
-- decodes --
signal LEDViewSel: STD_LOGIC;
signal IndexSel: STD_LOGIC;
signal GCRSel: STD_LOGIC;
signal GMRSel: STD_LOGIC;
signal CCRSel: STD_LOGIC;
signal SCCRSel: STD_LOGIC;
signal PCRSel: STD_LOGIC;
signal TimeOutSel: STD_LOGIC;
signal TimerSel: STD_LOGIC;
signal IRQDIVSel: STD_LOGIC;
signal PWMValSel: STD_LOGIC;
signal PhaseSel: STD_LOGIC;
signal CounterSel: STD_LOGIC;
signal SCounterSel: STD_LOGIC;
function OneOfFourDecode(ena : std_logic; dec : std_logic_vector(1 downto 0)) return std_logic_vector is
variable result : std_logic_vector(counters-1 downto 0);
begin
if ena = '1' then
case dec is
when "00" => result := "0001";
when "01" => result := "0010";
when "10" => result := "0100";
when "11" => result := "1000";
when others => result := "0000";
end case;
else
result := "0000";
end if;
return result;
end OneOfFourDecode;
function OneOfFourMux(sel: std_logic_vector (1 downto 0); input: std_logic_vector(counters-1 downto 0)) return std_logic is
variable result : std_logic;
begin
case sel is
when "00" => result := input(0);
when "01" => result := input(1);
when "10" => result := input(2);
when "11" => result := input(3);
when others => result := '0';
end case;
return result;
end OneOfFourMux;
component indexreg
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadindex: in STD_LOGIC;
readindex: in STD_LOGIC;
index: out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component counter
port (
obus: out STD_LOGIC_VECTOR (31 downto 0);
ibus: in STD_LOGIC_VECTOR (31 downto 0);
quada: in STD_LOGIC;
quadb: in STD_LOGIC;
index: in STD_LOGIC;
ccrloadcmd: in STD_LOGIC;
ccrreadcmd: in STD_LOGIC;
countoutreadcmd: in STD_LOGIC;
countlatchcmd: in STD_LOGIC;
countclearcmd: in STD_LOGIC;
countenable: in STD_LOGIC;
indexmask: in STD_LOGIC;
nads: in STD_LOGIC;
clk: in STD_LOGIC
);
end component;
component pwmgen
port (
clk: in STD_LOGIC;
refcount: in STD_LOGIC_VECTOR (9 downto 0);
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadpwmval: in STD_LOGIC;
readpwmval: in STD_LOGIC;
clearpwmval: in STD_LOGIC;
pcrloadcmd: STD_LOGIC;
pcrreadcmd: STD_LOGIC;
pwmout: out STD_LOGIC;
dirio: inout STD_LOGIC;
enablein: in STD_LOGIC;
enableout: out STD_LOGIC
);
end component pwmgen;
component pwmref is
port (
clk: in STD_LOGIC;
refcount: out STD_LOGIC_VECTOR (9 downto 0);
irqgen: out STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
irqdivload: in STD_LOGIC;
irqdivread: in STD_LOGIC;
phaseload: in STD_LOGIC;
phaseread: in STD_LOGIC
);
end component pwmref;
component globalcontrolreg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadgcr: in STD_LOGIC;
ctrclear: out STD_LOGIC;
ctrlatch: out STD_LOGIC;
pwmclear: out STD_LOGIC;
irqclear: out STD_LOGIC;
reloadwd: out STD_LOGIC
);
end component globalcontrolreg;
component globalmodereg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadglobalmode: in STD_LOGIC;
readglobalmode: in STD_LOGIC;
ctrena: out STD_LOGIC;
pwmena: out STD_LOGIC;
clearpwmena: in STD_LOGIC;
loi: out STD_LOGIC;
som: out STD_LOGIC;
sot: out STD_LOGIC;
miout: out STD_LOGIC;
miin: in STD_LOGIC;
irqmask: out STD_LOGIC;
irqstatus: in STD_LOGIC
);
end component globalmodereg;
component WordPR24 is
port (
clear: in STD_LOGIC;
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (23 downto 0);
obus: out STD_LOGIC_VECTOR (23 downto 0);
loadport: in STD_LOGIC;
loadddr: in STD_LOGIC;
readddr: in STD_LOGIC;
portdata: out STD_LOGIC_VECTOR (23 downto 0)
);
end component WordPR24;
component Word24RB is
Port (
obus: out STD_LOGIC_VECTOR (23 downto 0);
readport: in STD_LOGIC;
portdata: in STD_LOGIC_VECTOR (23 downto 0) );
end component Word24RB;
component Timeout is
Port ( clk : in std_logic;
ibus : in std_logic_vector(15 downto 0);
obus : out std_logic_vector(15 downto 0);
timeoutload : in std_logic;
timeoutread : in std_logic;
timerread : in std_logic;
reload : in std_logic;
timerz : out std_logic);
end component Timeout;
component idreadback is
Generic ( id : std_logic_vector(31 downto 0);
mc : std_logic_vector(31 downto 0));
Port ( readid : in std_logic;
readmc : in std_logic;
obus : out std_logic_vector(31 downto 0));
end component idreadback;
begin
makecounters: for i in 0 to (counters -1) generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => A(i),
quadb => B(i),
index => Idx(i),
ccrloadcmd => CCRLoadCmds(i),
ccrreadcmd => CCRReadCmds(i),
countoutreadcmd => CounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA(16 + i),
nads => ADS,
clk => LClk
);
end generate;
makescounters: for i in 0 to (counters -1) generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => IOBITSA((i*4)),
quadb => IOBITSA((i*4)+1),
index => IOBITSA((i*4)+2),
ccrloadcmd => SCCRLoadCmds(i),
ccrreadcmd => SCCRReadCmds(i),
countoutreadcmd => SCounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA((i*4) +3),
nads => ADS,
clk => LClk
);
end generate;
makepwmgen: for i in 0 to (counters -1) generate
pwmgenx: pwmgen port map (
clk => LClk,
refcount => RefCountBus,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadpwmval => LoadPWM(i),
readpwmval => ReadPWM(i),
clearpwmval => GlobalClearPWM,
pcrloadcmd => PCRLoadCmds(i),
pcrreadcmd => PCRReadCmds(i),
pwmout => PWM(i),
dirio => Dir(i),
enablein => GlobalPWMEnable,
enableout =>EnaSigs(i)
);
end generate;
oporta: WordPR24 port map (
clear => '0',
clk => LClk,
ibus => LAD(23 downto 0),
obus => D(23 downto 0),
loadport => LoadPortA,
loadddr => LoadDDRA,
readddr => ReadDDRA,
portdata => IOBITSA
);
iporta: Word24RB port map (
obus => D(23 downto 0),
readport => ReadPortA,
portdata => IOBITSA
);
oportb: WordPR24 port map (
clear => '0',
clk => LClk,
ibus => LAD(23 downto 0),
obus => D(23 downto 0),
loadport => LoadPortB,
loadddr => LoadDDRB,
readddr => ReadDDRB,
portdata => IOBITSB
);
iportb: Word24RB port map (
obus => D(23 downto 0),
readport => ReadPortB,
portdata => IOBitsB
);
pwmrefcount: pwmref port map (
clk => LClk,
refcount => RefCountBus,
irqgen => IRQSource,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
irqdivload => LoadIRQDivCmd,
irqdivread => ReadIRQDivCmd,
phaseload => LoadPhaseCmd,
phaseread => ReadPhaseCmd
);
gLedreg: indexreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadindex => LoadLEDViewCmd,
readindex => ReadLEDViewCmd,
index => LEDView
);
ggcontrolreg: globalcontrolreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
reset => '0',
loadgcr => LoadGCRCmd,
ctrclear => GlobalCounterClear,
ctrlatch => GlobalCountLatchCmd,
pwmclear => GlobalClearPWMCmd,
irqclear => ClearIRQCmd,
reloadwd => ReloadWDCmd
);
gglobalmodereg: globalmodereg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
reset => '0',
loadglobalmode => loadGMRCmd,
readglobalmode => ReadGMRCmd,
ctrena => GlobalCounterEnable,
pwmena => GlobalPWMEnable,
clearpwmena => StopPWM,
loi => LatchOnInterrupt,
som => StopOnMissedIRQ,
sot => StopOnTimeout,
miout => ClearMissedIRQ,
miin => MissedIRQ,
irqmask => IRQMask,
irqstatus => IRQLatch
);
atimeout: timeout port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
timeoutload => loadTimeOutCmd,
timeoutread => ReadTimeOutCmd,
timerread => ReadTimerCmd,
reload => ReLoadWDCmd,
timerz => WDTimeout
);
aidreadback: idreadback
generic map (
id => HMID,
mc => MasterClock
)
port map(
readid => ReadIDCmd,
readmc => ReadMCCmd,
obus => D
);
LADDrivers: process (D,FastRead)
begin
if FastRead ='1' then
LAD <= D;
else
LAD <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end if;
end process LADDrivers;
AddressLatch: process (lclk)
begin
if lclk'event and LClk = '1' then
if ADS = '0' then
LatchedA <= LAD(15 downto 0);
LatchedLBE <= LBE;
end if;
end if;
end process AddressLatch;
-- we generate an early read from ADS and LR_W
-- since the 10 nS LRD delay and 5 nS setup time
-- only give us 15 nS to provide data to the PLX chip
MakeFastRead: process (lclk,PreFastread,LRD)
begin
if lclk'event and LClk = '1' then
if ADS = '0' and LW_R = '0'then
PreFastRead <= '1';
else
PreFastRead <= '0';
end if;
end if;
FastRead <= PreFastRead or (not LRD);
end process MakeFastRead;
Decode: process (LatchedA)
begin
if LatchedA(7 downto 5) = "000" then -- 32 bit access
CounterSel <= '1';
else
CounterSel <= '0';
end if;
if LatchedA(7 downto 5) = "001" then -- 32 bit access
SCounterSel <= '1';
else
SCounterSel <= '0';
end if;
if LatchedA(7 downto 4) = "0100" then -- 16 bit access
CCRSel <= '1';
else
CCRSel <= '0';
end if;
if LatchedA(7 downto 4) = "0101" then -- 16 bit access
SCCRSel <= '1';
else
SCCRSel <= '0';
end if;
if LatchedA(7 downto 5) = "011" then -- 16 bit access
PWMValSel <= '1';
else
PWMValSel <= '0';
end if;
if LatchedA(7 downto 5) = "100" then -- 16 bit access
PCRSel <= '1';
else
PCRSel <= '0';
end if;
if LatchedA(7 downto 2) = "101000" then -- 32 bit access
PortASel <= '1';
else
PortASel <= '0';
end if;
if LatchedA(7 downto 2) = "101001" then -- 32 bit access
DDRASel <= '1';
else
DDRASel <= '0';
end if;
if LatchedA(7 downto 2) = "101010" then -- 32 bit access
PortBSel <= '1';
else
PortBSel <= '0';
end if;
if LatchedA(7 downto 2) = "101011" then -- 32 bit access
DDRBSel <= '1';
else
DDRBSel <= '0';
end if;
if LatchedA(7 downto 2) = "110100" then -- 32 bit access D0
IDSel <= '1';
else
IDSel <= '0';
end if;
if LatchedA(7 downto 2) = "110101" then -- 32 bit access D4
MCSel <= '1';
else
MCSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100000" then -- 16 bit access
GCRSel <= '1';
else
GCRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100001" then -- 16 bit access
GMRSel <= '1';
else
GMRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100010"then -- 16 bit access
IRQDivSel <= '1';
else
IRQDivSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100011"then -- 16 bit access
PhaseSel <= '1';
else
PhaseSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100100" then -- 16 bit access
TimeOutSel <= '1';
else
TimeOutSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100101" then -- 16 bit access
TimerSel <= '1';
else
TimerSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100110" then -- 16 bit access
LEDViewSel <= '1';
else
LEDViewSel <= '0';
end if;
end process;
SigsOut: process (EnaSigs)
begin
Ena <= EnaSigs;
end process;
CounterDecode: process (CounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
CounterRead <= OneOfFourDecode(CounterSel,LatchedA(3 downto 2));
else
CounterRead <= (others => '0');
end if;
end process;
SCounterDecode: process (SCounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
SCounterRead <= OneOfFourDecode(SCounterSel,LatchedA(3 downto 2));
else
SCounterRead <= (others => '0');
end if;
end process;
CCRegs: process (CCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
CCRReadCmds <= OneOfFourDecode(CCRSel,LatchedA(2 downto 1));
else
CCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
CCRLoadCmds <= OneOfFourDecode(CCRSel,LatchedA(2 downto 1));
else
CCRLoadCmds <= (others => '0');
end if;
end process;
SCCRegs: process (SCCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
SCCRReadCmds <= OneOfFourDecode(SCCRSel,LatchedA(2 downto 1));
else
SCCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
SCCRLoadCmds <= OneOfFourDecode(SCCRSel,LatchedA(2 downto 1));
else
SCCRLoadCmds <= (others => '0');
end if;
end process;
PWMdecode: process (PWMValSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
ReadPWM <= OneOfFourDecode(PWMValSel,LatchedA(2 downto 1));
else
ReadPWM <= (others => '0');
end if;
if LWR = '0' then
LoadPWM <= OneOfFourDecode(PWMValSel,LatchedA(2 downto 1));
else
LoadPWM <= (others => '0');
end if;
end process;
PCRegs: process (PCRSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
PCRReadCmds <= OneOfFourDecode(PCRSel,LatchedA(2 downto 1));
else
PCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
PCRLoadCmds <= OneOfFourDecode(PCRSel,LatchedA(2 downto 1));
else
PCRLoadCmds <= (others => '0');
end if;
end process;
PortADecode: process (PortASel,FastRead,LWR)
begin
if PortASel = '1' and LWR = '0' then
LoadPortA <= '1';
else
LoadPortA <= '0';
end if;
if PortASel = '1' and FastRead = '1' then
ReadPortA <= '1';
else
ReadPortA <= '0';
end if;
end process PortADecode;
DDRADecode: process (DDRASel,FastRead,LWR)
begin
if DDRASel = '1' and LWR = '0' then
LoadDDRA <= '1';
else
LoadDDRA <= '0';
end if;
if DDRASel = '1' and FastRead = '1' then
ReadDDRA <= '1';
else
ReadDDRA <= '0';
end if;
end process DDRADecode;
PortBDecode: process (PortBSel,FastRead,LWR)
begin
if PortBSel = '1' and LWR = '0' then
LoadPortB <= '1';
else
LoadPortB <= '0';
end if;
if PortBSel = '1' and FastRead = '1' then
ReadPortB <= '1';
else
ReadPortB <= '0';
end if;
end process PortBDecode;
DDRBDecode: process (DDRBSel,FastRead,LWR)
begin
if DDRBSel = '1' and LWR = '0' then
LoadDDRB <= '1';
else
LoadDDRB <= '0';
end if;
if DDRBSel = '1' and FastRead = '1' then
ReadDDRB <= '1';
else
ReadDDRB <= '0';
end if;
end process DDRBDecode;
GCRDecode: process (GCRSel,LWR)
begin
if GCRSel = '1' and LWR = '0' then
LoadGCRCmd <= '1';
else
LoadGCRCmd <= '0';
end if;
end process GCRDecode;
GMRDecode: process (GMRSel,FastRead,LWR)
begin
if GMRSel = '1' and LWR = '0' then
LoadGMRCmd <= '1';
else
LoadGMRCmd <= '0';
end if;
if GMRSel = '1' and FastRead = '1' then
ReadGMRCmd <= '1';
else
ReadGMRCmd <= '0';
end if;
end process GMRDecode;
TimeOutDecode: process (TimeOutSel,FastRead,LWR)
begin
if TimeoutSel = '1' and LWR = '0' then
LoadTimeOutCmd <= '1';
else
LoadTimeOutCmd <= '0';
end if;
if TimeOutSel = '1' and FastRead = '1' then
ReadTimeOutCmd <= '1';
else
ReadTimeOutCmd <= '0';
end if;
end process TimeOutDecode;
TimerDecode: process (TimerSel,FastRead,LWR)
begin
if TimerSel = '1' and FastRead = '1' then
ReadTimerCmd <= '1';
else
ReadTimerCmd <= '0';
end if;
end process TimerDecode;
LEDViewDecode: process (LedViewSel,FastRead,LWR)
begin
if LEDViewSel = '1' and LWR = '0' then
LoadLEDViewCmd <= '1';
else
LoadLEDViewCmd <= '0';
end if;
if LEDViewSel = '1' and FastRead= '1' then
ReadLEDViewCmd <= '1';
else
ReadLEDViewCmd <= '0';
end if;
end process LEDViewDecode;
IRQDivDecode: process (IRQDivSel,FastRead,LWR)
begin
if IRQDivSel = '1' and LWR = '0' then
LoadIRQDivCmd <= '1';
else
LoadIRQDivCmd <= '0';
end if;
if IRQDivSel = '1' and FastRead = '1' then
ReadIRQDivCmd <= '1';
else
ReadIRQDivCmd <= '0';
end if;
end process IrqDivDecode;
PhaseDecode: process (PhaseSel,FastRead,LWR)
begin
if PhaseSel = '1' and LWR = '0' then
LoadPhaseCmd <= '1';
else
LoadPhaseCmd <= '0';
end if;
if PhaseSel = '1' and FastRead = '1' then
ReadPhaseCmd <= '1';
else
ReadPhaseCmd <= '0';
end if;
end process PhaseDecode;
IDDecode: process (IDSel,FastRead)
begin
if IDSel = '1' and FastRead = '1' then
ReadIDCmd <= '1';
else
ReadIDCmd <= '0';
end if;
end process IDDecode;
MCDecode: process (MCSel,FastRead)
begin
if MCSel = '1' and FastRead = '1' then
ReadMCCmd <= '1';
else
ReadMCCmd <= '0';
end if;
end process MCDecode;
irqlogic: process (CardSelect,
IRQSource,
IrqLatch,
ClearMissedIRQ,
MissedIRQ,
StopOnMissedIRQ,
LatchOnInterrupt,
GlobalCountLatchCmd,
GlobalClearPWMCmd,
ClearIRQCmd)
begin
if IrqSource'event and IRQsource = '1' then
IRQLatch <= '1';
if IRQLatch = '1' then -- if IRQLatch is set and we get the next interrupt
MissedIRQ <= '1'; -- set Missed IRQ latch
end if;
end if;
if LClk'event and LClk = '1' then
if ((IRQLatch = '1') and (LatchOnInterrupt = '1')) or (GlobalCountLatchCmd = '1') then
CountLatchEdge1 <= '1';
else
CountLatchEdge1 <= '0';
end if;
CountLatchEdge2 <= CountLatchEdge1;
if CountLatchEdge2 = '0' and CountLatchEdge1 = '1' then
GlobalCountLatch <= '1';
else
GlobalCountLatch <= '0';
end if;
end if;
if ClearMissedIRQ = '1' then
MissedIRQ <= '0';
end if;
if ((MissedIRQ = '1') and (StopOnMissedIRQ = '1')) or
((WDTimeOut = '1') and (StopOnTimeout = '1')) then
StopPWM <= '1';
else
StopPWM <= '0';
end if;
if (StopPWM = '1') or (GlobalClearPWMCmd = '1') then -- either stop on pwm or global clear reset pwm gens
GlobalClearPWM <= '1';
else
GlobalClearPWM <= '0';
end if;
if ClearIRQCmd = '1' then -- clear IRQ
IRQLatch <= '0';
end if;
Int <= not (IRQLatch and IRQMask); -- drive our (active low) interrupt pin
Ready <= '0'; -- We're always ready
end process;
LEDDrive: process (A,B,Idx,Dir,PWM,IRQLatch,LedView)
begin
LEDS(7) <= not IRQLatch;
LEDS(6) <= not OneOfFourMux(LEDView(1 downto 0),A);
LEDS(5) <= not OneOfFourMux(LEDView(1 downto 0),B);
LEDS(4) <= not OneOfFourMux(LEDView(1 downto 0),Idx);
LEDS(3) <= not OneOfFourMux(LEDView(1 downto 0),Dir);
LEDS(2) <= not OneOfFourMux(LEDView(1 downto 0),PWM);
LEDS(1) <= OneOfFourMux(LEDView(1 downto 0),EnaSigs);
LEDS(0) <= not WDTimeout;
end process leddrive;
end dataflow;
|
-------------------------------------------------------------------------------
-- upcnt_n.vhd entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v1.01.b
--
-- Description:
-- This file contains a parameterizable N-bit up counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Data width of counter
--
-- Definition of Ports:
-- Clk -- System clock
-- Clr -- Active low clear
-- Data -- Serial data in
-- Cnt_en -- Count enable
-- Load -- Load line enable
-- Qout -- Shift register shift enable
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : integer :=9
);
port(
Clr : in std_logic;
Clk : in std_logic;
Data : in std_logic_vector (0 to C_SIZE-1);
Cnt_en : in std_logic;
Load : in std_logic;
Qout : inout std_logic_vector (0 to C_SIZE-1)
);
end upcnt_n;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of upcnt_n is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant enable_n : std_logic := '0';
signal q_int : unsigned (0 to C_SIZE-1);
begin
----------------------------------------------------------------------------
-- PROCESS: UP_COUNT_GEN
-- purpose: Up counter
----------------------------------------------------------------------------
UP_COUNT_GEN : process(Clk)
begin
if (Clk'event) and Clk = '1' then
if (Clr = enable_n) then -- Clear output register
q_int <= (others => '0');
elsif (Load = '1') then -- Load in start value
q_int <= unsigned(Data);
elsif Cnt_en = '1' then -- If count enable is high
q_int <= q_int + 1;
else
q_int <= q_int;
end if;
end if;
end process UP_COUNT_GEN;
Qout <= std_logic_vector(q_int);
end architecture RTL;
|
-------------------------------------------------------------------------------
-- upcnt_n.vhd entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v1.01.b
--
-- Description:
-- This file contains a parameterizable N-bit up counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Data width of counter
--
-- Definition of Ports:
-- Clk -- System clock
-- Clr -- Active low clear
-- Data -- Serial data in
-- Cnt_en -- Count enable
-- Load -- Load line enable
-- Qout -- Shift register shift enable
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : integer :=9
);
port(
Clr : in std_logic;
Clk : in std_logic;
Data : in std_logic_vector (0 to C_SIZE-1);
Cnt_en : in std_logic;
Load : in std_logic;
Qout : inout std_logic_vector (0 to C_SIZE-1)
);
end upcnt_n;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of upcnt_n is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant enable_n : std_logic := '0';
signal q_int : unsigned (0 to C_SIZE-1);
begin
----------------------------------------------------------------------------
-- PROCESS: UP_COUNT_GEN
-- purpose: Up counter
----------------------------------------------------------------------------
UP_COUNT_GEN : process(Clk)
begin
if (Clk'event) and Clk = '1' then
if (Clr = enable_n) then -- Clear output register
q_int <= (others => '0');
elsif (Load = '1') then -- Load in start value
q_int <= unsigned(Data);
elsif Cnt_en = '1' then -- If count enable is high
q_int <= q_int + 1;
else
q_int <= q_int;
end if;
end if;
end process UP_COUNT_GEN;
Qout <= std_logic_vector(q_int);
end architecture RTL;
|
-------------------------------------------------------------------------------
-- Title : Multiplier testbench
-- Project :
-------------------------------------------------------------------------------
-- File : multiplier_bench.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-02-01
-- Last update: 2015-03-11
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Multiplier testbench
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-02-01 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity multiplier_bench is
end entity multiplier_bench;
architecture test of multiplier_bench is
constant input_freq : real := 120.0e6;
constant clock_period : time := 1.0 sec /(2.0*input_freq);
signal clock : std_logic := '0';
signal endoffile : bit := '0';
signal a1 : std_logic_vector(15 downto 0);
signal b1 : std_logic_vector(15 downto 0);
signal p1 : std_logic_vector(15 downto 0);
component generic_multiplier is
generic (
g_a_width : natural;
g_b_width : natural;
g_signed : boolean;
g_p_width : natural);
port (
a_i : in std_logic_vector(g_a_width-1 downto 0);
b_i : in std_logic_vector(g_b_width-1 downto 0);
p_o : out std_logic_vector(g_p_width-1 downto 0);
ce_i : in std_logic;
clk_i : in std_logic;
rst_i : in std_logic);
end component generic_multiplier;
begin -- architecture test
clk_gen : process
begin
clock <= '0';
wait for clock_period;
clock <= '1';
wait for clock_period;
end process;
uut : generic_multiplier
generic map(
g_a_width => 16,
g_b_width => 16,
g_signed => true,
g_p_width => 16)
port map(
a_i => a1,
b_i => b1,
p_o => p1,
ce_i => '1',
clk_i => clock,
rst_i => '0');
b1 <= X"FFFF";
-- FIXME: too simple of a test, requiring manual inspection. Improve it.
single_test : process(clock)
variable a_test : integer := -1000;
begin
if rising_edge(clock) then
a1 <= std_logic_vector(to_signed(a_test, 16));
a_test := a_test + 20;
if a_test = 1000 then
assert(false) report "Input file finished." severity failure;
end if;
end if;
end process;
end architecture test;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1756.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b01x00p01n01i01756ent IS
END c09s05b01x00p01n01i01756ent;
ARCHITECTURE c09s05b01x00p01n01i01756arch OF c09s05b01x00p01n01i01756ent IS
type t_wlogic is (U, D, Z0, Z1, ZDX, DZX, ZX);
signal count : integer ;
signal ECLK : t_wlogic;
signal ECLK2 : t_wlogic;
signal ECL : integer := 1;
BEGIN
count <= 0 after 0 ns,
1 after 10 ns,
2 after 20 ns,
3 after 30 ns,
4 after 40 ns,
5 after 50 ns,
6 after 60 ns;
----------------------------------------------------------------------
ECLK <= U after 1 ns WHEN count=0 ELSE
D after 1 ns WHEN count=1 ELSE
Z0 after 1 ns WHEN count=2 ELSE
Z1 after 1 ns WHEN count=3 ELSE
ZDX after 1 ns WHEN count=4 ELSE
DZX after 1 ns WHEN count=5 ELSE
ZX after 1 ns ;
TESTING: PROCESS(count)
BEGIN
if count = 0 then
ECLK2 <= U after 1 ns;
elsif count = 1 then
ECLK2 <= D after 1 ns;
elsif count = 2 then
ECLK2 <= Z0 after 1 ns;
elsif count = 3 then
ECLK2 <= Z1 after 1 ns;
elsif count = 4 then
ECLK2 <= ZDX after 1 ns;
elsif count = 5 then
ECLK2 <= DZX after 1 ns;
else
ECLK2 <= ZX after 1 ns;
end if;
END PROCESS TESTING;
PROCESS(ECLK,ECLK2)
BEGIN
if now = 0 ns then
NULL;
elsif (now = 1 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 11 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 21 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 31 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 41 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 51 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 61 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
end if;
END PROCESS;
PROCESS(ECLK,ECLK2)
BEGIN
if (now > 60 ns) and (ECL = 1) then
assert FALSE
report "***PASSED TEST: c09s05b01x00p01n01i01756"
severity NOTE;
elsif (now > 60 ns) and (ECL = 0) then
assert FALSE
report "***FAILED TEST: c09s05b01x00p01n01i01756 - The conditional signal assignment represents a process statement in which the signal transform is an if statement."
severity ERROR;
end if;
END PROCESS;
END c09s05b01x00p01n01i01756arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1756.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b01x00p01n01i01756ent IS
END c09s05b01x00p01n01i01756ent;
ARCHITECTURE c09s05b01x00p01n01i01756arch OF c09s05b01x00p01n01i01756ent IS
type t_wlogic is (U, D, Z0, Z1, ZDX, DZX, ZX);
signal count : integer ;
signal ECLK : t_wlogic;
signal ECLK2 : t_wlogic;
signal ECL : integer := 1;
BEGIN
count <= 0 after 0 ns,
1 after 10 ns,
2 after 20 ns,
3 after 30 ns,
4 after 40 ns,
5 after 50 ns,
6 after 60 ns;
----------------------------------------------------------------------
ECLK <= U after 1 ns WHEN count=0 ELSE
D after 1 ns WHEN count=1 ELSE
Z0 after 1 ns WHEN count=2 ELSE
Z1 after 1 ns WHEN count=3 ELSE
ZDX after 1 ns WHEN count=4 ELSE
DZX after 1 ns WHEN count=5 ELSE
ZX after 1 ns ;
TESTING: PROCESS(count)
BEGIN
if count = 0 then
ECLK2 <= U after 1 ns;
elsif count = 1 then
ECLK2 <= D after 1 ns;
elsif count = 2 then
ECLK2 <= Z0 after 1 ns;
elsif count = 3 then
ECLK2 <= Z1 after 1 ns;
elsif count = 4 then
ECLK2 <= ZDX after 1 ns;
elsif count = 5 then
ECLK2 <= DZX after 1 ns;
else
ECLK2 <= ZX after 1 ns;
end if;
END PROCESS TESTING;
PROCESS(ECLK,ECLK2)
BEGIN
if now = 0 ns then
NULL;
elsif (now = 1 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 11 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 21 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 31 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 41 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 51 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 61 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
end if;
END PROCESS;
PROCESS(ECLK,ECLK2)
BEGIN
if (now > 60 ns) and (ECL = 1) then
assert FALSE
report "***PASSED TEST: c09s05b01x00p01n01i01756"
severity NOTE;
elsif (now > 60 ns) and (ECL = 0) then
assert FALSE
report "***FAILED TEST: c09s05b01x00p01n01i01756 - The conditional signal assignment represents a process statement in which the signal transform is an if statement."
severity ERROR;
end if;
END PROCESS;
END c09s05b01x00p01n01i01756arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1756.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b01x00p01n01i01756ent IS
END c09s05b01x00p01n01i01756ent;
ARCHITECTURE c09s05b01x00p01n01i01756arch OF c09s05b01x00p01n01i01756ent IS
type t_wlogic is (U, D, Z0, Z1, ZDX, DZX, ZX);
signal count : integer ;
signal ECLK : t_wlogic;
signal ECLK2 : t_wlogic;
signal ECL : integer := 1;
BEGIN
count <= 0 after 0 ns,
1 after 10 ns,
2 after 20 ns,
3 after 30 ns,
4 after 40 ns,
5 after 50 ns,
6 after 60 ns;
----------------------------------------------------------------------
ECLK <= U after 1 ns WHEN count=0 ELSE
D after 1 ns WHEN count=1 ELSE
Z0 after 1 ns WHEN count=2 ELSE
Z1 after 1 ns WHEN count=3 ELSE
ZDX after 1 ns WHEN count=4 ELSE
DZX after 1 ns WHEN count=5 ELSE
ZX after 1 ns ;
TESTING: PROCESS(count)
BEGIN
if count = 0 then
ECLK2 <= U after 1 ns;
elsif count = 1 then
ECLK2 <= D after 1 ns;
elsif count = 2 then
ECLK2 <= Z0 after 1 ns;
elsif count = 3 then
ECLK2 <= Z1 after 1 ns;
elsif count = 4 then
ECLK2 <= ZDX after 1 ns;
elsif count = 5 then
ECLK2 <= DZX after 1 ns;
else
ECLK2 <= ZX after 1 ns;
end if;
END PROCESS TESTING;
PROCESS(ECLK,ECLK2)
BEGIN
if now = 0 ns then
NULL;
elsif (now = 1 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 11 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 21 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 31 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 41 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 51 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 61 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
end if;
END PROCESS;
PROCESS(ECLK,ECLK2)
BEGIN
if (now > 60 ns) and (ECL = 1) then
assert FALSE
report "***PASSED TEST: c09s05b01x00p01n01i01756"
severity NOTE;
elsif (now > 60 ns) and (ECL = 0) then
assert FALSE
report "***FAILED TEST: c09s05b01x00p01n01i01756 - The conditional signal assignment represents a process statement in which the signal transform is an if statement."
severity ERROR;
end if;
END PROCESS;
END c09s05b01x00p01n01i01756arch;
|
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- ATA/ATAPI-5 PIO controller with write PingPong ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 8th, 2001. Initial release
--
-- CVS Log
--
-- $Id: atahost_pio_controller.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_pio_controller.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity atahost_pio_controller is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock in
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- control / registers
IDEctrl_IDEen,
IDEctrl_ppen,
IDEctrl_FATR0,
IDEctrl_FATR1 : in std_logic;
-- PIO registers
cmdport_T1,
cmdport_T2,
cmdport_T4,
cmdport_Teoc : in std_logic_vector(7 downto 0);
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
dport0_T1,
dport0_T2,
dport0_T4,
dport0_Teoc : in std_logic_vector(7 downto 0);
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
dport1_T1,
dport1_T2,
dport1_T4,
dport1_Teoc : in std_logic_vector(7 downto 0);
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
sel : in std_logic; -- PIO controller selected
ack : out std_logic; -- PIO controller acknowledge
a : in std_logic_vector(3 downto 0); -- lower address bits
we : in std_logic; -- write enable input
d : in std_logic_vector(15 downto 0);
q : out std_logic_vector(15 downto 0);
PIOreq : out std_logic; -- PIO transfer request
PPFull : out std_logic; -- PIO Write PingPong Full
go : in std_logic; -- start PIO transfer
done : out std_logic; -- done with PIO transfer
PIOa : out std_logic_vector(3 downto 0); -- PIO address, address lines towards ATA devices
PIOd : out std_logic_vector(15 downto 0); -- PIO data, data towards ATA devices
SelDev : out std_logic; -- Selected Device, Dev-bit in ATA Device/Head register
DDi : in std_logic_vector(15 downto 0);
DDoe : out std_logic;
DIOR : out std_logic;
DIOW : out std_logic;
IORDY : in std_logic
);
end entity atahost_pio_controller;
architecture structural of atahost_pio_controller is
--
-- component declarations
--
component atahost_pio_actrl is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
IDEctrl_FATR0,
IDEctrl_FATR1 : in std_logic;
cmdport_T1,
cmdport_T2,
cmdport_T4,
cmdport_Teoc : in std_logic_vector(7 downto 0);
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
dport0_T1,
dport0_T2,
dport0_T4,
dport0_Teoc : in std_logic_vector(7 downto 0);
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
dport1_T1,
dport1_T2,
dport1_T4,
dport1_Teoc : in std_logic_vector(7 downto 0);
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
SelDev : in std_logic; -- Selected device
go : in std_logic; -- Start transfer sequence
done : out std_logic; -- Transfer sequence done
dir : in std_logic; -- Transfer direction '1'=write, '0'=read
a : in std_logic_vector(3 downto 0); -- PIO transfer address
q : out std_logic_vector(15 downto 0); -- Data read from ATA devices
DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus
oe : out std_logic; -- DDbus output-enable signal
DIOR,
DIOW : out std_logic;
IORDY : in std_logic
);
end component atahost_pio_actrl;
--
-- signals
--
-- PIO pingpong signals
signal pp_d : std_logic_vector(15 downto 0);
signal pp_a : std_logic_vector(3 downto 0);
signal pp_we : std_logic;
signal idone : std_logic;
signal iSelDev : std_logic;
begin
--
-- generate selected device
--
gen_seldev: process(clk, pp_a)
variable Asel : std_logic; -- address selected
begin
Asel := not pp_a(3) and pp_a(2) and pp_a(1) and not pp_a(0); -- header/device register
if (clk'event and clk = '1') then
if ( (idone = '1') and (Asel = '1') and (pp_we = '1') ) then
iSelDev <= pp_d(4);
end if;
end if;
end process gen_seldev;
--
-- generate PIO write pingpong system
--
gen_pingpong: block
signal ping_d, pong_d : std_logic_vector(15 downto 0);
signal ping_a, pong_a : std_logic_vector(3 downto 0);
signal ping_we, pong_we : std_logic;
signal ping_valid, pong_valid : std_logic;
signal dping_valid, dpong_valid : std_logic;
signal wpp, rpp : std_logic;
signal dsel, sel_strb : std_logic;
signal iack : std_logic;
begin
-- generate PIO acknowledge
gen_ack: process(clk, ping_valid, dping_valid, pong_valid, dpong_valid, we)
variable ping_re, ping_fe, pong_re, pong_fe : std_logic;
begin
-- detect rising edge of ping_valid and pong_valid
ping_re := ping_valid and not dping_valid and we;
pong_re := pong_valid and not dpong_valid and we;
-- detect falling edge of ping_valid and pong_valid
ping_fe := not ping_valid and dping_valid;
pong_fe := not pong_valid and dpong_valid;
if (clk'event and clk = '1') then
if ((pp_we = '1') and (IDEctrl_ppen = '1')) then -- write sequence
if (wpp = '1') then
iack <= ping_re;
else
iack <= pong_re;
end if;
else -- read sequence
if (rpp = '1') then
iack <= ping_fe;
else
iack <= pong_fe;
end if;
end if;
end if;
end process gen_ack;
ack <= (iack or not IDEctrl_IDEen) and sel; -- acknowledge access when not enabled (discard access)
-- generate select-strobe, hold sel_strb until pingpong system ready for new data
gen_sel_strb: process(clk, nReset)
begin
if (nReset = '0') then
dsel <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
dsel <= '0';
else
dsel <= sel_strb or (dsel and sel);
end if;
end if;
end process gen_sel_strb;
sel_strb <= sel and not dsel and IDEctrl_IDEen and ((wpp and not ping_valid) or (not wpp and not pong_valid));
-- generate pingpong control
gen_pp : process(clk, nReset)
begin
if (nReset = '0') then
wpp <= '0';
rpp <= '0';
ping_valid <= '0';
pong_valid <= '0';
dping_valid <= '0';
dpong_valid <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
wpp <= '0';
rpp <= '0';
ping_valid <= '0';
pong_valid <= '0';
dping_valid <= '0';
dpong_valid <= '0';
else
wpp <= (wpp xor (iack and we)) and IDEctrl_ppen;
rpp <= (rpp xor (idone and pp_we)) and IDEctrl_ppen;
ping_valid <= (( wpp and sel_strb) or ping_valid) and not ( rpp and idone);
pong_valid <= ((not wpp and sel_strb) or pong_valid) and not (not rpp and idone);
dping_valid <= ping_valid;
dpong_valid <= pong_valid;
end if;
end if;
end process gen_pp;
-- generate pingpong full signal
PPFull <= (ping_valid and pong_valid) when (IDEctrl_ppen = '1') else pong_valid;
-- fill ping/pong registers
fill_pp: process(clk)
begin
if (clk'event and clk = '1') then
if (sel = '1') then
if (wpp = '1') then
if (ping_valid = '0') then
ping_d <= d;
ping_a <= a;
ping_we <= we;
end if;
else
if (pong_valid = '0') then
pong_d <= d;
pong_a <= a;
pong_we <= we;
end if;
end if;
end if;
end if;
end process fill_pp;
-- multiplex pingpong data to pp_d, pp_a, pp_we
pp_d <= d;
pp_a <= a;
pp_we <= we;
--edit by erik (no pp)
-- pp_d <= ping_d when (rpp = '1') else pong_d;
-- pp_a <= ping_a when (rpp = '1') else pong_a;
-- pp_we <= ping_we when (rpp = '1') else pong_we;
-- generate PIOreq
PIOreq <= (ping_valid and not idone) when (rpp = '1') else (pong_valid and not idone);
end block gen_pingpong;
--
-- Hookup PIO access controller
--
PIO_access_control: atahost_pio_actrl
generic map(
TWIDTH => TWIDTH,
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc
)
port map(
clk => clk,
nReset => nReset,
rst => rst,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
cmdport_T1 => cmdport_T1,
cmdport_T2 => cmdport_T2,
cmdport_T4 => cmdport_T4,
cmdport_Teoc => cmdport_Teoc,
cmdport_IORDYen => cmdport_IORDYen,
dport0_T1 => dport0_T1,
dport0_T2 => dport0_T2,
dport0_T4 => dport0_T4,
dport0_Teoc => dport0_Teoc,
dport0_IORDYen => dport0_IORDYen,
dport1_T1 => dport1_T1,
dport1_T2 => dport1_T2,
dport1_T4 => dport1_T4,
dport1_Teoc => dport1_Teoc,
dport1_IORDYen => dport1_IORDYen,
SelDev => iSelDev,
go => go,
done => idone,
dir => pp_we,
a => pp_a,
q => Q,
DDi => DDi,
oe => DDoe,
DIOR => dior,
DIOW => diow,
IORDY => IORDY
);
--
-- assign outputs
--
PIOa <= pp_a;
PIOd <= pp_d;
Done <= idone;
SelDev <= iSelDev;
end architecture structural;
|
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- ATA/ATAPI-5 PIO controller with write PingPong ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 8th, 2001. Initial release
--
-- CVS Log
--
-- $Id: atahost_pio_controller.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_pio_controller.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity atahost_pio_controller is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock in
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- control / registers
IDEctrl_IDEen,
IDEctrl_ppen,
IDEctrl_FATR0,
IDEctrl_FATR1 : in std_logic;
-- PIO registers
cmdport_T1,
cmdport_T2,
cmdport_T4,
cmdport_Teoc : in std_logic_vector(7 downto 0);
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
dport0_T1,
dport0_T2,
dport0_T4,
dport0_Teoc : in std_logic_vector(7 downto 0);
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
dport1_T1,
dport1_T2,
dport1_T4,
dport1_Teoc : in std_logic_vector(7 downto 0);
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
sel : in std_logic; -- PIO controller selected
ack : out std_logic; -- PIO controller acknowledge
a : in std_logic_vector(3 downto 0); -- lower address bits
we : in std_logic; -- write enable input
d : in std_logic_vector(15 downto 0);
q : out std_logic_vector(15 downto 0);
PIOreq : out std_logic; -- PIO transfer request
PPFull : out std_logic; -- PIO Write PingPong Full
go : in std_logic; -- start PIO transfer
done : out std_logic; -- done with PIO transfer
PIOa : out std_logic_vector(3 downto 0); -- PIO address, address lines towards ATA devices
PIOd : out std_logic_vector(15 downto 0); -- PIO data, data towards ATA devices
SelDev : out std_logic; -- Selected Device, Dev-bit in ATA Device/Head register
DDi : in std_logic_vector(15 downto 0);
DDoe : out std_logic;
DIOR : out std_logic;
DIOW : out std_logic;
IORDY : in std_logic
);
end entity atahost_pio_controller;
architecture structural of atahost_pio_controller is
--
-- component declarations
--
component atahost_pio_actrl is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
IDEctrl_FATR0,
IDEctrl_FATR1 : in std_logic;
cmdport_T1,
cmdport_T2,
cmdport_T4,
cmdport_Teoc : in std_logic_vector(7 downto 0);
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
dport0_T1,
dport0_T2,
dport0_T4,
dport0_Teoc : in std_logic_vector(7 downto 0);
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
dport1_T1,
dport1_T2,
dport1_T4,
dport1_Teoc : in std_logic_vector(7 downto 0);
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
SelDev : in std_logic; -- Selected device
go : in std_logic; -- Start transfer sequence
done : out std_logic; -- Transfer sequence done
dir : in std_logic; -- Transfer direction '1'=write, '0'=read
a : in std_logic_vector(3 downto 0); -- PIO transfer address
q : out std_logic_vector(15 downto 0); -- Data read from ATA devices
DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus
oe : out std_logic; -- DDbus output-enable signal
DIOR,
DIOW : out std_logic;
IORDY : in std_logic
);
end component atahost_pio_actrl;
--
-- signals
--
-- PIO pingpong signals
signal pp_d : std_logic_vector(15 downto 0);
signal pp_a : std_logic_vector(3 downto 0);
signal pp_we : std_logic;
signal idone : std_logic;
signal iSelDev : std_logic;
begin
--
-- generate selected device
--
gen_seldev: process(clk, pp_a)
variable Asel : std_logic; -- address selected
begin
Asel := not pp_a(3) and pp_a(2) and pp_a(1) and not pp_a(0); -- header/device register
if (clk'event and clk = '1') then
if ( (idone = '1') and (Asel = '1') and (pp_we = '1') ) then
iSelDev <= pp_d(4);
end if;
end if;
end process gen_seldev;
--
-- generate PIO write pingpong system
--
gen_pingpong: block
signal ping_d, pong_d : std_logic_vector(15 downto 0);
signal ping_a, pong_a : std_logic_vector(3 downto 0);
signal ping_we, pong_we : std_logic;
signal ping_valid, pong_valid : std_logic;
signal dping_valid, dpong_valid : std_logic;
signal wpp, rpp : std_logic;
signal dsel, sel_strb : std_logic;
signal iack : std_logic;
begin
-- generate PIO acknowledge
gen_ack: process(clk, ping_valid, dping_valid, pong_valid, dpong_valid, we)
variable ping_re, ping_fe, pong_re, pong_fe : std_logic;
begin
-- detect rising edge of ping_valid and pong_valid
ping_re := ping_valid and not dping_valid and we;
pong_re := pong_valid and not dpong_valid and we;
-- detect falling edge of ping_valid and pong_valid
ping_fe := not ping_valid and dping_valid;
pong_fe := not pong_valid and dpong_valid;
if (clk'event and clk = '1') then
if ((pp_we = '1') and (IDEctrl_ppen = '1')) then -- write sequence
if (wpp = '1') then
iack <= ping_re;
else
iack <= pong_re;
end if;
else -- read sequence
if (rpp = '1') then
iack <= ping_fe;
else
iack <= pong_fe;
end if;
end if;
end if;
end process gen_ack;
ack <= (iack or not IDEctrl_IDEen) and sel; -- acknowledge access when not enabled (discard access)
-- generate select-strobe, hold sel_strb until pingpong system ready for new data
gen_sel_strb: process(clk, nReset)
begin
if (nReset = '0') then
dsel <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
dsel <= '0';
else
dsel <= sel_strb or (dsel and sel);
end if;
end if;
end process gen_sel_strb;
sel_strb <= sel and not dsel and IDEctrl_IDEen and ((wpp and not ping_valid) or (not wpp and not pong_valid));
-- generate pingpong control
gen_pp : process(clk, nReset)
begin
if (nReset = '0') then
wpp <= '0';
rpp <= '0';
ping_valid <= '0';
pong_valid <= '0';
dping_valid <= '0';
dpong_valid <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
wpp <= '0';
rpp <= '0';
ping_valid <= '0';
pong_valid <= '0';
dping_valid <= '0';
dpong_valid <= '0';
else
wpp <= (wpp xor (iack and we)) and IDEctrl_ppen;
rpp <= (rpp xor (idone and pp_we)) and IDEctrl_ppen;
ping_valid <= (( wpp and sel_strb) or ping_valid) and not ( rpp and idone);
pong_valid <= ((not wpp and sel_strb) or pong_valid) and not (not rpp and idone);
dping_valid <= ping_valid;
dpong_valid <= pong_valid;
end if;
end if;
end process gen_pp;
-- generate pingpong full signal
PPFull <= (ping_valid and pong_valid) when (IDEctrl_ppen = '1') else pong_valid;
-- fill ping/pong registers
fill_pp: process(clk)
begin
if (clk'event and clk = '1') then
if (sel = '1') then
if (wpp = '1') then
if (ping_valid = '0') then
ping_d <= d;
ping_a <= a;
ping_we <= we;
end if;
else
if (pong_valid = '0') then
pong_d <= d;
pong_a <= a;
pong_we <= we;
end if;
end if;
end if;
end if;
end process fill_pp;
-- multiplex pingpong data to pp_d, pp_a, pp_we
pp_d <= d;
pp_a <= a;
pp_we <= we;
--edit by erik (no pp)
-- pp_d <= ping_d when (rpp = '1') else pong_d;
-- pp_a <= ping_a when (rpp = '1') else pong_a;
-- pp_we <= ping_we when (rpp = '1') else pong_we;
-- generate PIOreq
PIOreq <= (ping_valid and not idone) when (rpp = '1') else (pong_valid and not idone);
end block gen_pingpong;
--
-- Hookup PIO access controller
--
PIO_access_control: atahost_pio_actrl
generic map(
TWIDTH => TWIDTH,
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc
)
port map(
clk => clk,
nReset => nReset,
rst => rst,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
cmdport_T1 => cmdport_T1,
cmdport_T2 => cmdport_T2,
cmdport_T4 => cmdport_T4,
cmdport_Teoc => cmdport_Teoc,
cmdport_IORDYen => cmdport_IORDYen,
dport0_T1 => dport0_T1,
dport0_T2 => dport0_T2,
dport0_T4 => dport0_T4,
dport0_Teoc => dport0_Teoc,
dport0_IORDYen => dport0_IORDYen,
dport1_T1 => dport1_T1,
dport1_T2 => dport1_T2,
dport1_T4 => dport1_T4,
dport1_Teoc => dport1_Teoc,
dport1_IORDYen => dport1_IORDYen,
SelDev => iSelDev,
go => go,
done => idone,
dir => pp_we,
a => pp_a,
q => Q,
DDi => DDi,
oe => DDoe,
DIOR => dior,
DIOW => diow,
IORDY => IORDY
);
--
-- assign outputs
--
PIOa <= pp_a;
PIOd <= pp_d;
Done <= idone;
SelDev <= iSelDev;
end architecture structural;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY dataregfile IS
PORT(
dibus : IN std_logic_vector (15 DOWNTO 0);
selalua : IN std_logic_vector (3 DOWNTO 0);
selalub : IN std_logic_vector (3 DOWNTO 0);
seldreg : IN std_logic_vector (2 DOWNTO 0);
w : IN std_logic;
wrd : IN std_logic;
alu_inbusa : OUT std_logic_vector (15 DOWNTO 0);
alu_inbusb : OUT std_logic_vector (15 DOWNTO 0);
bp_s : OUT std_logic_vector (15 DOWNTO 0);
bx_s : OUT std_logic_vector (15 DOWNTO 0);
di_s : OUT std_logic_vector (15 DOWNTO 0);
si_s : OUT std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
clk : IN std_logic;
data_in : IN std_logic_vector (15 DOWNTO 0);
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
sp_s : OUT std_logic_vector (15 DOWNTO 0);
ax_s : OUT std_logic_vector (15 DOWNTO 0);
cx_s : OUT std_logic_vector (15 DOWNTO 0);
dx_s : OUT std_logic_vector (15 DOWNTO 0)
);
END dataregfile ;
architecture rtl of dataregfile is
signal axreg_s : std_logic_vector(15 downto 0);
signal cxreg_s : std_logic_vector(15 downto 0);
signal dxreg_s : std_logic_vector(15 downto 0);
signal bxreg_s : std_logic_vector(15 downto 0);
signal spreg_s : std_logic_vector(15 downto 0);
signal bpreg_s : std_logic_vector(15 downto 0);
signal sireg_s : std_logic_vector(15 downto 0);
signal direg_s : std_logic_vector(15 downto 0);
signal seldreg_s : std_logic_vector(3 downto 0); -- w & seldreg
signal selalua_s : std_logic_vector(4 downto 0); -- w & dibus & selalua
signal selalub_s : std_logic_vector(4 downto 0); -- w & dibus & selalub
signal alu_inbusb_s: std_logic_vector (15 downto 0);
begin
----------------------------------------------------------------------------
-- 8 registers of 16 bits each
----------------------------------------------------------------------------
seldreg_s <= w & seldreg;
process (clk,reset)
begin
if reset='1' then
axreg_s <= (others => '0');
cxreg_s <= (others => '0');
dxreg_s <= (others => '0');
bxreg_s <= (others => '0');
spreg_s <= (others => '0');
bpreg_s <= (others => '0');
sireg_s <= (others => '0');
direg_s <= (others => '0');
elsif rising_edge(clk) then
if (wrd='1') then
case seldreg_s is
when "0000" => axreg_s(7 downto 0) <= dibus(7 downto 0); -- w=0 8 bits write
when "0001" => cxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0010" => dxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0011" => bxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0100" => axreg_s(15 downto 8) <= dibus(7 downto 0);
when "0101" => cxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0110" => dxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0111" => bxreg_s(15 downto 8) <= dibus(7 downto 0);
when "1000" => axreg_s <= dibus; -- w=1 16 bits write
when "1001" => cxreg_s <= dibus;
when "1010" => dxreg_s <= dibus;
when "1011" => bxreg_s <= dibus;
when "1100" => spreg_s <= dibus;
when "1101" => bpreg_s <= dibus;
when "1110" => sireg_s <= dibus;
when others => direg_s <= dibus;
end case;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Output Port A
----------------------------------------------------------------------------
selalua_s <= w & selalua;
process (selalua_s,axreg_s,cxreg_s,dxreg_s,bxreg_s,spreg_s,bpreg_s,sireg_s,direg_s,mdbus_in)
begin
case selalua_s is
when "00000" => alu_inbusa <= X"00" & axreg_s(7 downto 0); -- Select 8 bits MSB=0
when "00001" => alu_inbusa <= X"00" & cxreg_s(7 downto 0);
when "00010" => alu_inbusa <= X"00" & dxreg_s(7 downto 0);
when "00011" => alu_inbusa <= X"00" & bxreg_s(7 downto 0);
when "00100" => alu_inbusa <= X"00" & axreg_s(15 downto 8); -- AH
when "00101" => alu_inbusa <= X"00" & cxreg_s(15 downto 8); -- CH
when "00110" => alu_inbusa <= X"00" & dxreg_s(15 downto 8); -- DH
when "00111" => alu_inbusa <= X"00" & bxreg_s(15 downto 8); -- BH
when "10000" => alu_inbusa <= axreg_s;
when "10001" => alu_inbusa <= cxreg_s;
when "10010" => alu_inbusa <= dxreg_s;
when "10011" => alu_inbusa <= bxreg_s;
when "10100" => alu_inbusa <= spreg_s;
when "10101" => alu_inbusa <= bpreg_s;
when "10110" => alu_inbusa <= sireg_s;
when "10111" => alu_inbusa <= direg_s;
when others => alu_inbusa <= mdbus_in(15 downto 0); -- Pass through
end case;
end process;
----------------------------------------------------------------------------
-- Output Port B
----------------------------------------------------------------------------
selalub_s <= w & selalub;
process (selalub_s,axreg_s,cxreg_s,dxreg_s,bxreg_s,spreg_s,bpreg_s,sireg_s,direg_s,mdbus_in,data_in)
begin
case selalub_s is
when "00000" => alu_inbusb_s <= X"00" & axreg_s(7 downto 0);
when "00001" => alu_inbusb_s <= X"00" & cxreg_s(7 downto 0);
when "00010" => alu_inbusb_s <= X"00" & dxreg_s(7 downto 0);
when "00011" => alu_inbusb_s <= X"00" & bxreg_s(7 downto 0);
when "00100" => alu_inbusb_s <= X"00" & axreg_s(15 downto 8);
when "00101" => alu_inbusb_s <= X"00" & cxreg_s(15 downto 8);
when "00110" => alu_inbusb_s <= X"00" & dxreg_s(15 downto 8);
when "00111" => alu_inbusb_s <= X"00" & bxreg_s(15 downto 8);
when "10000" => alu_inbusb_s <= axreg_s;
when "10001" => alu_inbusb_s <= cxreg_s;
when "10010" => alu_inbusb_s <= dxreg_s;
when "10011" => alu_inbusb_s <= bxreg_s;
when "10100" => alu_inbusb_s <= spreg_s;
when "10101" => alu_inbusb_s <= bpreg_s;
when "10110" => alu_inbusb_s <= sireg_s;
when "10111" => alu_inbusb_s <= direg_s;
when "01000" => alu_inbusb_s <= X"00"& data_in(7 downto 0); -- Pass data_in to ALU (port B only)
when "11000" => alu_inbusb_s <= data_in; -- Pass data_in to ALU (port B only)
when "01001" => alu_inbusb_s <= X"0001"; -- Used for INC/DEC byte function
when "11001" => alu_inbusb_s <= X"0001"; -- Used for INC/DEC word function
when "11010" => alu_inbusb_s <= X"0002"; -- Used for POP/PUSH function
when others => alu_inbusb_s <= mdbus_in(15 downto 0); -- Pass through
end case;
end process;
alu_inbusb <= alu_inbusb_s; -- connect to entity
bx_s <= bxreg_s; -- Used for EA calculation
bp_s <= bpreg_s;
si_s <= sireg_s;
di_s <= direg_s;
sp_s <= spreg_s; -- Used for eamux, PUSH and POP instructions
ax_s <= axreg_s; -- Used for datapath FSM
cx_s <= cxreg_s;
dx_s <= dxreg_s; -- Used for IN/OUT instructions & Divider
end rtl;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY dataregfile IS
PORT(
dibus : IN std_logic_vector (15 DOWNTO 0);
selalua : IN std_logic_vector (3 DOWNTO 0);
selalub : IN std_logic_vector (3 DOWNTO 0);
seldreg : IN std_logic_vector (2 DOWNTO 0);
w : IN std_logic;
wrd : IN std_logic;
alu_inbusa : OUT std_logic_vector (15 DOWNTO 0);
alu_inbusb : OUT std_logic_vector (15 DOWNTO 0);
bp_s : OUT std_logic_vector (15 DOWNTO 0);
bx_s : OUT std_logic_vector (15 DOWNTO 0);
di_s : OUT std_logic_vector (15 DOWNTO 0);
si_s : OUT std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
clk : IN std_logic;
data_in : IN std_logic_vector (15 DOWNTO 0);
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
sp_s : OUT std_logic_vector (15 DOWNTO 0);
ax_s : OUT std_logic_vector (15 DOWNTO 0);
cx_s : OUT std_logic_vector (15 DOWNTO 0);
dx_s : OUT std_logic_vector (15 DOWNTO 0)
);
END dataregfile ;
architecture rtl of dataregfile is
signal axreg_s : std_logic_vector(15 downto 0);
signal cxreg_s : std_logic_vector(15 downto 0);
signal dxreg_s : std_logic_vector(15 downto 0);
signal bxreg_s : std_logic_vector(15 downto 0);
signal spreg_s : std_logic_vector(15 downto 0);
signal bpreg_s : std_logic_vector(15 downto 0);
signal sireg_s : std_logic_vector(15 downto 0);
signal direg_s : std_logic_vector(15 downto 0);
signal seldreg_s : std_logic_vector(3 downto 0); -- w & seldreg
signal selalua_s : std_logic_vector(4 downto 0); -- w & dibus & selalua
signal selalub_s : std_logic_vector(4 downto 0); -- w & dibus & selalub
signal alu_inbusb_s: std_logic_vector (15 downto 0);
begin
----------------------------------------------------------------------------
-- 8 registers of 16 bits each
----------------------------------------------------------------------------
seldreg_s <= w & seldreg;
process (clk,reset)
begin
if reset='1' then
axreg_s <= (others => '0');
cxreg_s <= (others => '0');
dxreg_s <= (others => '0');
bxreg_s <= (others => '0');
spreg_s <= (others => '0');
bpreg_s <= (others => '0');
sireg_s <= (others => '0');
direg_s <= (others => '0');
elsif rising_edge(clk) then
if (wrd='1') then
case seldreg_s is
when "0000" => axreg_s(7 downto 0) <= dibus(7 downto 0); -- w=0 8 bits write
when "0001" => cxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0010" => dxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0011" => bxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0100" => axreg_s(15 downto 8) <= dibus(7 downto 0);
when "0101" => cxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0110" => dxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0111" => bxreg_s(15 downto 8) <= dibus(7 downto 0);
when "1000" => axreg_s <= dibus; -- w=1 16 bits write
when "1001" => cxreg_s <= dibus;
when "1010" => dxreg_s <= dibus;
when "1011" => bxreg_s <= dibus;
when "1100" => spreg_s <= dibus;
when "1101" => bpreg_s <= dibus;
when "1110" => sireg_s <= dibus;
when others => direg_s <= dibus;
end case;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Output Port A
----------------------------------------------------------------------------
selalua_s <= w & selalua;
process (selalua_s,axreg_s,cxreg_s,dxreg_s,bxreg_s,spreg_s,bpreg_s,sireg_s,direg_s,mdbus_in)
begin
case selalua_s is
when "00000" => alu_inbusa <= X"00" & axreg_s(7 downto 0); -- Select 8 bits MSB=0
when "00001" => alu_inbusa <= X"00" & cxreg_s(7 downto 0);
when "00010" => alu_inbusa <= X"00" & dxreg_s(7 downto 0);
when "00011" => alu_inbusa <= X"00" & bxreg_s(7 downto 0);
when "00100" => alu_inbusa <= X"00" & axreg_s(15 downto 8); -- AH
when "00101" => alu_inbusa <= X"00" & cxreg_s(15 downto 8); -- CH
when "00110" => alu_inbusa <= X"00" & dxreg_s(15 downto 8); -- DH
when "00111" => alu_inbusa <= X"00" & bxreg_s(15 downto 8); -- BH
when "10000" => alu_inbusa <= axreg_s;
when "10001" => alu_inbusa <= cxreg_s;
when "10010" => alu_inbusa <= dxreg_s;
when "10011" => alu_inbusa <= bxreg_s;
when "10100" => alu_inbusa <= spreg_s;
when "10101" => alu_inbusa <= bpreg_s;
when "10110" => alu_inbusa <= sireg_s;
when "10111" => alu_inbusa <= direg_s;
when others => alu_inbusa <= mdbus_in(15 downto 0); -- Pass through
end case;
end process;
----------------------------------------------------------------------------
-- Output Port B
----------------------------------------------------------------------------
selalub_s <= w & selalub;
process (selalub_s,axreg_s,cxreg_s,dxreg_s,bxreg_s,spreg_s,bpreg_s,sireg_s,direg_s,mdbus_in,data_in)
begin
case selalub_s is
when "00000" => alu_inbusb_s <= X"00" & axreg_s(7 downto 0);
when "00001" => alu_inbusb_s <= X"00" & cxreg_s(7 downto 0);
when "00010" => alu_inbusb_s <= X"00" & dxreg_s(7 downto 0);
when "00011" => alu_inbusb_s <= X"00" & bxreg_s(7 downto 0);
when "00100" => alu_inbusb_s <= X"00" & axreg_s(15 downto 8);
when "00101" => alu_inbusb_s <= X"00" & cxreg_s(15 downto 8);
when "00110" => alu_inbusb_s <= X"00" & dxreg_s(15 downto 8);
when "00111" => alu_inbusb_s <= X"00" & bxreg_s(15 downto 8);
when "10000" => alu_inbusb_s <= axreg_s;
when "10001" => alu_inbusb_s <= cxreg_s;
when "10010" => alu_inbusb_s <= dxreg_s;
when "10011" => alu_inbusb_s <= bxreg_s;
when "10100" => alu_inbusb_s <= spreg_s;
when "10101" => alu_inbusb_s <= bpreg_s;
when "10110" => alu_inbusb_s <= sireg_s;
when "10111" => alu_inbusb_s <= direg_s;
when "01000" => alu_inbusb_s <= X"00"& data_in(7 downto 0); -- Pass data_in to ALU (port B only)
when "11000" => alu_inbusb_s <= data_in; -- Pass data_in to ALU (port B only)
when "01001" => alu_inbusb_s <= X"0001"; -- Used for INC/DEC byte function
when "11001" => alu_inbusb_s <= X"0001"; -- Used for INC/DEC word function
when "11010" => alu_inbusb_s <= X"0002"; -- Used for POP/PUSH function
when others => alu_inbusb_s <= mdbus_in(15 downto 0); -- Pass through
end case;
end process;
alu_inbusb <= alu_inbusb_s; -- connect to entity
bx_s <= bxreg_s; -- Used for EA calculation
bp_s <= bpreg_s;
si_s <= sireg_s;
di_s <= direg_s;
sp_s <= spreg_s; -- Used for eamux, PUSH and POP instructions
ax_s <= axreg_s; -- Used for datapath FSM
cx_s <= cxreg_s;
dx_s <= dxreg_s; -- Used for IN/OUT instructions & Divider
end rtl;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY dataregfile IS
PORT(
dibus : IN std_logic_vector (15 DOWNTO 0);
selalua : IN std_logic_vector (3 DOWNTO 0);
selalub : IN std_logic_vector (3 DOWNTO 0);
seldreg : IN std_logic_vector (2 DOWNTO 0);
w : IN std_logic;
wrd : IN std_logic;
alu_inbusa : OUT std_logic_vector (15 DOWNTO 0);
alu_inbusb : OUT std_logic_vector (15 DOWNTO 0);
bp_s : OUT std_logic_vector (15 DOWNTO 0);
bx_s : OUT std_logic_vector (15 DOWNTO 0);
di_s : OUT std_logic_vector (15 DOWNTO 0);
si_s : OUT std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
clk : IN std_logic;
data_in : IN std_logic_vector (15 DOWNTO 0);
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
sp_s : OUT std_logic_vector (15 DOWNTO 0);
ax_s : OUT std_logic_vector (15 DOWNTO 0);
cx_s : OUT std_logic_vector (15 DOWNTO 0);
dx_s : OUT std_logic_vector (15 DOWNTO 0)
);
END dataregfile ;
architecture rtl of dataregfile is
signal axreg_s : std_logic_vector(15 downto 0);
signal cxreg_s : std_logic_vector(15 downto 0);
signal dxreg_s : std_logic_vector(15 downto 0);
signal bxreg_s : std_logic_vector(15 downto 0);
signal spreg_s : std_logic_vector(15 downto 0);
signal bpreg_s : std_logic_vector(15 downto 0);
signal sireg_s : std_logic_vector(15 downto 0);
signal direg_s : std_logic_vector(15 downto 0);
signal seldreg_s : std_logic_vector(3 downto 0); -- w & seldreg
signal selalua_s : std_logic_vector(4 downto 0); -- w & dibus & selalua
signal selalub_s : std_logic_vector(4 downto 0); -- w & dibus & selalub
signal alu_inbusb_s: std_logic_vector (15 downto 0);
begin
----------------------------------------------------------------------------
-- 8 registers of 16 bits each
----------------------------------------------------------------------------
seldreg_s <= w & seldreg;
process (clk,reset)
begin
if reset='1' then
axreg_s <= (others => '0');
cxreg_s <= (others => '0');
dxreg_s <= (others => '0');
bxreg_s <= (others => '0');
spreg_s <= (others => '0');
bpreg_s <= (others => '0');
sireg_s <= (others => '0');
direg_s <= (others => '0');
elsif rising_edge(clk) then
if (wrd='1') then
case seldreg_s is
when "0000" => axreg_s(7 downto 0) <= dibus(7 downto 0); -- w=0 8 bits write
when "0001" => cxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0010" => dxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0011" => bxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0100" => axreg_s(15 downto 8) <= dibus(7 downto 0);
when "0101" => cxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0110" => dxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0111" => bxreg_s(15 downto 8) <= dibus(7 downto 0);
when "1000" => axreg_s <= dibus; -- w=1 16 bits write
when "1001" => cxreg_s <= dibus;
when "1010" => dxreg_s <= dibus;
when "1011" => bxreg_s <= dibus;
when "1100" => spreg_s <= dibus;
when "1101" => bpreg_s <= dibus;
when "1110" => sireg_s <= dibus;
when others => direg_s <= dibus;
end case;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Output Port A
----------------------------------------------------------------------------
selalua_s <= w & selalua;
process (selalua_s,axreg_s,cxreg_s,dxreg_s,bxreg_s,spreg_s,bpreg_s,sireg_s,direg_s,mdbus_in)
begin
case selalua_s is
when "00000" => alu_inbusa <= X"00" & axreg_s(7 downto 0); -- Select 8 bits MSB=0
when "00001" => alu_inbusa <= X"00" & cxreg_s(7 downto 0);
when "00010" => alu_inbusa <= X"00" & dxreg_s(7 downto 0);
when "00011" => alu_inbusa <= X"00" & bxreg_s(7 downto 0);
when "00100" => alu_inbusa <= X"00" & axreg_s(15 downto 8); -- AH
when "00101" => alu_inbusa <= X"00" & cxreg_s(15 downto 8); -- CH
when "00110" => alu_inbusa <= X"00" & dxreg_s(15 downto 8); -- DH
when "00111" => alu_inbusa <= X"00" & bxreg_s(15 downto 8); -- BH
when "10000" => alu_inbusa <= axreg_s;
when "10001" => alu_inbusa <= cxreg_s;
when "10010" => alu_inbusa <= dxreg_s;
when "10011" => alu_inbusa <= bxreg_s;
when "10100" => alu_inbusa <= spreg_s;
when "10101" => alu_inbusa <= bpreg_s;
when "10110" => alu_inbusa <= sireg_s;
when "10111" => alu_inbusa <= direg_s;
when others => alu_inbusa <= mdbus_in(15 downto 0); -- Pass through
end case;
end process;
----------------------------------------------------------------------------
-- Output Port B
----------------------------------------------------------------------------
selalub_s <= w & selalub;
process (selalub_s,axreg_s,cxreg_s,dxreg_s,bxreg_s,spreg_s,bpreg_s,sireg_s,direg_s,mdbus_in,data_in)
begin
case selalub_s is
when "00000" => alu_inbusb_s <= X"00" & axreg_s(7 downto 0);
when "00001" => alu_inbusb_s <= X"00" & cxreg_s(7 downto 0);
when "00010" => alu_inbusb_s <= X"00" & dxreg_s(7 downto 0);
when "00011" => alu_inbusb_s <= X"00" & bxreg_s(7 downto 0);
when "00100" => alu_inbusb_s <= X"00" & axreg_s(15 downto 8);
when "00101" => alu_inbusb_s <= X"00" & cxreg_s(15 downto 8);
when "00110" => alu_inbusb_s <= X"00" & dxreg_s(15 downto 8);
when "00111" => alu_inbusb_s <= X"00" & bxreg_s(15 downto 8);
when "10000" => alu_inbusb_s <= axreg_s;
when "10001" => alu_inbusb_s <= cxreg_s;
when "10010" => alu_inbusb_s <= dxreg_s;
when "10011" => alu_inbusb_s <= bxreg_s;
when "10100" => alu_inbusb_s <= spreg_s;
when "10101" => alu_inbusb_s <= bpreg_s;
when "10110" => alu_inbusb_s <= sireg_s;
when "10111" => alu_inbusb_s <= direg_s;
when "01000" => alu_inbusb_s <= X"00"& data_in(7 downto 0); -- Pass data_in to ALU (port B only)
when "11000" => alu_inbusb_s <= data_in; -- Pass data_in to ALU (port B only)
when "01001" => alu_inbusb_s <= X"0001"; -- Used for INC/DEC byte function
when "11001" => alu_inbusb_s <= X"0001"; -- Used for INC/DEC word function
when "11010" => alu_inbusb_s <= X"0002"; -- Used for POP/PUSH function
when others => alu_inbusb_s <= mdbus_in(15 downto 0); -- Pass through
end case;
end process;
alu_inbusb <= alu_inbusb_s; -- connect to entity
bx_s <= bxreg_s; -- Used for EA calculation
bp_s <= bpreg_s;
si_s <= sireg_s;
di_s <= direg_s;
sp_s <= spreg_s; -- Used for eamux, PUSH and POP instructions
ax_s <= axreg_s; -- Used for datapath FSM
cx_s <= cxreg_s;
dx_s <= dxreg_s; -- Used for IN/OUT instructions & Divider
end rtl;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37088)
`protect data_block
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`protect end_protected
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#0d0007#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 1;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 1;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 1;
constant CFG_SPICTRL_FT : integer := 0;
-- SPI to AHB bridge
constant CFG_SPI2AHB : integer := 0;
constant CFG_SPI2AHB_APB : integer := 0;
constant CFG_SPI2AHB_ADDRH : integer := 16#0#;
constant CFG_SPI2AHB_ADDRL : integer := 16#0#;
constant CFG_SPI2AHB_MASKH : integer := 16#0#;
constant CFG_SPI2AHB_MASKL : integer := 16#0#;
constant CFG_SPI2AHB_RESEN : integer := 0;
constant CFG_SPI2AHB_FILTER : integer := 2;
constant CFG_SPI2AHB_CPOL : integer := 0;
constant CFG_SPI2AHB_CPHA : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fa IS
PORT(
a,b,Cin : IN std_logic;
S,Cout : OUT std_logic
);
END ENTITY;
ARCHITECTURE behavior OF fa IS
BEGIN
S <= a XOR b XOR Cin;
Cout <= (a AND b) OR ((a XOR b) AND Cin);
END ARCHITECTURE behavior; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.ALL;
entity fm_modulator is Port (
clk, clk_modulator : in STD_LOGIC;
data : in signed (8 downto 0);
fm_out : out STD_LOGIC);
end fm_modulator;
architecture Behavioral of fm_modulator is
constant input_clk : real := 256.0; -- MHz
constant accumulator_size : real := 2**32.0;
constant fm_frequency : real := 94.7; -- MHz
constant center_freq : signed(31 downto 0) := to_signed(integer(accumulator_size*fm_frequency/input_clk),32);
component phase_adder port (
clk: in std_logic;
a,b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
end component;
signal ph_shift_data,ph_shift: signed (31 downto 0);
signal sum : std_logic_vector (31 downto 0);
begin
process (clk) begin
if rising_edge(clk) then
ph_shift_data <= resize(data & x"000",32); -- right shift data 12 times so the full range is about +-10000000, which should equal a freq. dev. of +-75kHz
ph_shift <= center_freq + ph_shift_data;
end if;
end process;
fast_adder : phase_adder port map ( -- the adder IP is required to run this sum at 320MHz
clk => clk_modulator,
a => std_logic_vector(ph_shift), b => sum,
s => sum
);
fm_out <= sum(31);
end Behavioral;
|
entity repro is
end;
architecture behav of repro is
function f return natural is
begin
return 5;
end f;
constant cst : natural := f;
type rec1 is record
r : bit_vector (1 to cst);
end record;
type rec is record
v : bit_vector;
r : rec1;
end record;
procedure assign (signal s : out rec; val : rec) is
begin
s <= val;
end assign;
begin
end behav;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
-- $Id: nexys3_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys3_dummy - syn
-- Description: nexys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys3
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1 use nxcramlib
-- 2011-11-25 432 1.0 Initial version (derived from nexys2_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys3_fusp_dummy is -- NEXYS 3 dummy (base+fusp; loopback)
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end nexys3_fusp_dummy;
architecture syn of nexys3_fusp_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pr_axis_loopback is
generic (
DATAWIDTH : integer := 64
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
s_axis_data_tvalid : in std_logic;
m_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
m_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
m_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end pr_axis_loopback;
architecture rtl of pr_axis_loopback is
component axis_buffer is
generic (
DATAWIDTH : integer := DATAWIDTH;
BUFFER_SIZE : integer := 1
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH - 1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
s_axis_data_tvalid : in std_logic;
m_axis_data_tdata : out std_logic_vector(DATAWIDTH - 1 downto 0);
m_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
m_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end component;
begin
loopback: component axis_buffer
port map (
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tkeep => s_axis_data_tkeep,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
s_axis_data_tvalid => s_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tkeep => m_axis_data_tkeep,
m_axis_data_tready => m_axis_data_tready,
m_axis_data_tlast => m_axis_data_tlast,
m_axis_data_tvalid => m_axis_data_tvalid,
clk => clk
);
end architecture; |
architecture RTL of ENTITY_NAME is
begin
process
begin
SEL_LABEL : some target := some expression when some condition else
some expression when some condition else
some expression;
SEL_LABEL : some target := some expression when some condition;
some target := some expression when some condition else
some expression when some condition else
some expression;
some target := some expression when some condition;
end process;
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 10:34:28 09/09/2015
-- Design Name:
-- Module Name: Challenge1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Challenge 1, 4 Code input, a select in 0 means Binary to Gray
-- select in 1 means Gray to Binary.
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Challenge1 is
generic (n : Integer := 4);
Port ( Code : in STD_LOGIC_VECTOR (n-1 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0);
Sel : in STD_LOGIC;
Disp : out STD_LOGIC_VECTOR (3 downto 0));
end Challenge1;
architecture Behavioral of Challenge1 is
--embbeded signals
signal res_binary : STD_LOGIC_VECTOR (n-1 downto 0);
signal res_gray : STD_LOGIC_VECTOR (n-1 downto 0);
signal res_conversion : STD_LOGIC_VECTOR (n-1 downto 0);
begin
BinaryToGray: process(Code)
begin
res_gray(n-1) <= Code(n-1);
res_gray(n-2 downto 0) <= Code(n-2 downto 0) xor Code(n-1 downto 1);
end process BinaryToGray;
GrayToBinary: process(Code, res_binary)
VARIABLE aux: STD_LOGIC_VECTOR (n-1 downto 0);
begin
aux(n-1) := Code(n-1);
gen: for i in n-2 downto 0 loop
aux(i) := aux(i+1) xor Code(i);
end loop;
res_binary (n-1 downto 0) <= aux(n-1 downto 0);
end process GrayToBinary;
-- Multiplexor
res_conversion <= res_gray when sel = '0' else
res_binary;
decodercase: process(res_conversion)
VARIABLE bufer: STD_LOGIC_VECTOR (7 downto 0);
begin
case(res_conversion) is
when "0000" => bufer:= "11000000";
when "0001" => bufer:= "11111001";
when "0010" => bufer:= "10100100";
when "0011" => bufer:= "10110000";
when "0100" => bufer:= "10011001";
when "0101" => bufer:= "10010010";
when "0110" => bufer:= "10000010";
when "0111" => bufer:= "11111000";
when "1000" => bufer:= "10000000";
when "1001" => bufer:= "10011000";
when "1010" => bufer:= "10001000";
when "1011" => bufer:= "10000011";
when "1100" => bufer:= "11000110";
when "1101" => bufer:= "10100001";
when "1110" => bufer:= "10000110";
when "1111" => bufer:= "10001110";
when others => bufer:= "10111111";
end case;
Seg <= bufer;
end process decodercase;
Disp <= x"E";
end Behavioral;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sm.vhd
-- Description: This entity contains the MM2S DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sm is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_ftch_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_cmnd_idle : out std_logic ; --
mm2s_sts_idle : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : in std_logic ; --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
packet_in_progress : in std_logic ; --
--
-- DataMover Command --
mm2s_cmnd_wr : out std_logic ; --
mm2s_cmnd_data : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+64+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
mm2s_cache_info : in std_logic_vector
(32-1 downto 0); --
mm2s_desc_baddress : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : in std_logic ; --
mm2s_desc_sof : in std_logic --
);
end axi_dma_mm2s_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant MM2S_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant MM2S_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant MM2S_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_MM2S_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal mm2s_cs : SG_MM2S_STATE_TYPE;
signal mm2s_ns : SG_MM2S_STATE_TYPE;
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal mm2s_cmnd_wr_i : std_logic := '0';
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal mm2s_desc_flush_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_cmnd_wr <= mm2s_cmnd_wr_i;
mm2s_desc_flush <= mm2s_desc_flush_i;
-- Flush any fetch descriptors if stopped due to errors or soft reset
-- or if not in middle of packet and run/stop clears
mm2s_desc_flush_i <= '1' when (mm2s_stop = '1')
or (packet_in_progress = '0'
and mm2s_run_stop = '0')
else '0';
burst_type <= '1' and (not mm2s_keyhole);
-- A 0 on mm2s_kyhole means increment type burst
-- 1 means fixed burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(mm2s_cs,
mm2s_run_stop,
packet_in_progress,
desc_available,
updt_pending,
-- desc_fetch_done,
desc_update_done,
mm2s_cmnd_pending,
mm2s_stop,
mm2s_desc_flush_i
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
mm2s_cmnd_idle <= '0';
mm2s_ns <= mm2s_cs;
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running or Stopped but in middle of xfer and Descriptor
-- data available, No errors logged, and Room to queue more
-- commands, then fetch descriptor
-- if (updt_pending = '1') then
-- mm2s_ns <= IDLE;
if( (mm2s_run_stop = '1' or packet_in_progress = '1')
-- and desc_available = '1' and mm2s_stop = '0' and queue_more = '1' and updt_pending = '0') then
and desc_available = '1' and mm2s_stop = '0' and updt_pending = '0') then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- coverage off
mm2s_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
mm2s_cmnd_idle <= '1';
write_cmnd_cmb <= '0';
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- error detected or run/stop cleared
if(mm2s_desc_flush_i = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
-- descriptor fetch complete
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- mm2s_ns <= EXECUTE_XFER;
elsif(mm2s_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
mm2s_ns <= IDLE;
-- coverage off
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= WAIT_STATUS;
end if;
end if;
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '0';
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- error detected
-- if(mm2s_stop = '1')then
-- mm2s_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(mm2s_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- mm2s_ns <= IDLE;
-- else
-- mm2s_ns <= WAIT_STATUS;
-- end if;
-- else
-- mm2s_ns <= EXECUTE_XFER;
-- end if;
--
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(desc_update_done = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
else
mm2s_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cs <= IDLE;
else
mm2s_cs <= mm2s_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- register state machine signals
-------------------------------------------------------------------------------
--SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1'; --desc_fetch_req_cmb ;
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
-- & PAD_VALUE
-- & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
& PAD_VALUE
& mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
-- & mm2s_desc_blength;
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
& mm2s_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for mm2s is Idle.
-------------------------------------------------------------------------------
-- increment with each command written
count_incr <= '1' when mm2s_cmnd_wr_i = '1' and desc_update_done = '0'
else '0';
-- decrement with each status received
count_decr <= '1' when mm2s_cmnd_wr_i = '0' and desc_update_done = '1'
else '0';
-- count number of queued commands to keep track of what datamover is still
-- working on
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-- coverage off
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift(0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- coverage on
-- Indicate status is idle when no cmnd/sts queued
--mm2s_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
mm2s_sts_idle <= not cmnds_queued_shift (0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued_shift(3) /= '1') then -- < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift(C_PRMY_CMDFIFO_DEPTH-1));
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sm.vhd
-- Description: This entity contains the MM2S DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sm is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_ftch_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_cmnd_idle : out std_logic ; --
mm2s_sts_idle : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : in std_logic ; --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
packet_in_progress : in std_logic ; --
--
-- DataMover Command --
mm2s_cmnd_wr : out std_logic ; --
mm2s_cmnd_data : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+64+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
mm2s_cache_info : in std_logic_vector
(32-1 downto 0); --
mm2s_desc_baddress : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : in std_logic ; --
mm2s_desc_sof : in std_logic --
);
end axi_dma_mm2s_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant MM2S_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant MM2S_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant MM2S_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_MM2S_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal mm2s_cs : SG_MM2S_STATE_TYPE;
signal mm2s_ns : SG_MM2S_STATE_TYPE;
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal mm2s_cmnd_wr_i : std_logic := '0';
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal mm2s_desc_flush_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_cmnd_wr <= mm2s_cmnd_wr_i;
mm2s_desc_flush <= mm2s_desc_flush_i;
-- Flush any fetch descriptors if stopped due to errors or soft reset
-- or if not in middle of packet and run/stop clears
mm2s_desc_flush_i <= '1' when (mm2s_stop = '1')
or (packet_in_progress = '0'
and mm2s_run_stop = '0')
else '0';
burst_type <= '1' and (not mm2s_keyhole);
-- A 0 on mm2s_kyhole means increment type burst
-- 1 means fixed burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(mm2s_cs,
mm2s_run_stop,
packet_in_progress,
desc_available,
updt_pending,
-- desc_fetch_done,
desc_update_done,
mm2s_cmnd_pending,
mm2s_stop,
mm2s_desc_flush_i
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
mm2s_cmnd_idle <= '0';
mm2s_ns <= mm2s_cs;
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running or Stopped but in middle of xfer and Descriptor
-- data available, No errors logged, and Room to queue more
-- commands, then fetch descriptor
-- if (updt_pending = '1') then
-- mm2s_ns <= IDLE;
if( (mm2s_run_stop = '1' or packet_in_progress = '1')
-- and desc_available = '1' and mm2s_stop = '0' and queue_more = '1' and updt_pending = '0') then
and desc_available = '1' and mm2s_stop = '0' and updt_pending = '0') then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- coverage off
mm2s_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
mm2s_cmnd_idle <= '1';
write_cmnd_cmb <= '0';
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- error detected or run/stop cleared
if(mm2s_desc_flush_i = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
-- descriptor fetch complete
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- mm2s_ns <= EXECUTE_XFER;
elsif(mm2s_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
mm2s_ns <= IDLE;
-- coverage off
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= WAIT_STATUS;
end if;
end if;
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '0';
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- error detected
-- if(mm2s_stop = '1')then
-- mm2s_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(mm2s_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- mm2s_ns <= IDLE;
-- else
-- mm2s_ns <= WAIT_STATUS;
-- end if;
-- else
-- mm2s_ns <= EXECUTE_XFER;
-- end if;
--
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(desc_update_done = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
else
mm2s_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cs <= IDLE;
else
mm2s_cs <= mm2s_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- register state machine signals
-------------------------------------------------------------------------------
--SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1'; --desc_fetch_req_cmb ;
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
-- & PAD_VALUE
-- & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
& PAD_VALUE
& mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
-- & mm2s_desc_blength;
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
& mm2s_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for mm2s is Idle.
-------------------------------------------------------------------------------
-- increment with each command written
count_incr <= '1' when mm2s_cmnd_wr_i = '1' and desc_update_done = '0'
else '0';
-- decrement with each status received
count_decr <= '1' when mm2s_cmnd_wr_i = '0' and desc_update_done = '1'
else '0';
-- count number of queued commands to keep track of what datamover is still
-- working on
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-- coverage off
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift(0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- coverage on
-- Indicate status is idle when no cmnd/sts queued
--mm2s_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
mm2s_sts_idle <= not cmnds_queued_shift (0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued_shift(3) /= '1') then -- < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift(C_PRMY_CMDFIFO_DEPTH-1));
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sm.vhd
-- Description: This entity contains the MM2S DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sm is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_ftch_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_cmnd_idle : out std_logic ; --
mm2s_sts_idle : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : in std_logic ; --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
packet_in_progress : in std_logic ; --
--
-- DataMover Command --
mm2s_cmnd_wr : out std_logic ; --
mm2s_cmnd_data : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+64+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
mm2s_cache_info : in std_logic_vector
(32-1 downto 0); --
mm2s_desc_baddress : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : in std_logic ; --
mm2s_desc_sof : in std_logic --
);
end axi_dma_mm2s_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant MM2S_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant MM2S_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant MM2S_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_MM2S_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal mm2s_cs : SG_MM2S_STATE_TYPE;
signal mm2s_ns : SG_MM2S_STATE_TYPE;
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal mm2s_cmnd_wr_i : std_logic := '0';
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal mm2s_desc_flush_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_cmnd_wr <= mm2s_cmnd_wr_i;
mm2s_desc_flush <= mm2s_desc_flush_i;
-- Flush any fetch descriptors if stopped due to errors or soft reset
-- or if not in middle of packet and run/stop clears
mm2s_desc_flush_i <= '1' when (mm2s_stop = '1')
or (packet_in_progress = '0'
and mm2s_run_stop = '0')
else '0';
burst_type <= '1' and (not mm2s_keyhole);
-- A 0 on mm2s_kyhole means increment type burst
-- 1 means fixed burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(mm2s_cs,
mm2s_run_stop,
packet_in_progress,
desc_available,
updt_pending,
-- desc_fetch_done,
desc_update_done,
mm2s_cmnd_pending,
mm2s_stop,
mm2s_desc_flush_i
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
mm2s_cmnd_idle <= '0';
mm2s_ns <= mm2s_cs;
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running or Stopped but in middle of xfer and Descriptor
-- data available, No errors logged, and Room to queue more
-- commands, then fetch descriptor
-- if (updt_pending = '1') then
-- mm2s_ns <= IDLE;
if( (mm2s_run_stop = '1' or packet_in_progress = '1')
-- and desc_available = '1' and mm2s_stop = '0' and queue_more = '1' and updt_pending = '0') then
and desc_available = '1' and mm2s_stop = '0' and updt_pending = '0') then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- coverage off
mm2s_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
mm2s_cmnd_idle <= '1';
write_cmnd_cmb <= '0';
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- error detected or run/stop cleared
if(mm2s_desc_flush_i = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
-- descriptor fetch complete
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- mm2s_ns <= EXECUTE_XFER;
elsif(mm2s_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
mm2s_ns <= IDLE;
-- coverage off
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= WAIT_STATUS;
end if;
end if;
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '0';
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- error detected
-- if(mm2s_stop = '1')then
-- mm2s_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(mm2s_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- mm2s_ns <= IDLE;
-- else
-- mm2s_ns <= WAIT_STATUS;
-- end if;
-- else
-- mm2s_ns <= EXECUTE_XFER;
-- end if;
--
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(desc_update_done = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
else
mm2s_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cs <= IDLE;
else
mm2s_cs <= mm2s_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- register state machine signals
-------------------------------------------------------------------------------
--SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1'; --desc_fetch_req_cmb ;
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
-- & PAD_VALUE
-- & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
& PAD_VALUE
& mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
-- & mm2s_desc_blength;
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
& mm2s_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for mm2s is Idle.
-------------------------------------------------------------------------------
-- increment with each command written
count_incr <= '1' when mm2s_cmnd_wr_i = '1' and desc_update_done = '0'
else '0';
-- decrement with each status received
count_decr <= '1' when mm2s_cmnd_wr_i = '0' and desc_update_done = '1'
else '0';
-- count number of queued commands to keep track of what datamover is still
-- working on
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-- coverage off
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift(0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- coverage on
-- Indicate status is idle when no cmnd/sts queued
--mm2s_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
mm2s_sts_idle <= not cmnds_queued_shift (0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued_shift(3) /= '1') then -- < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift(C_PRMY_CMDFIFO_DEPTH-1));
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sm.vhd
-- Description: This entity contains the MM2S DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sm is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_ftch_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_cmnd_idle : out std_logic ; --
mm2s_sts_idle : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : in std_logic ; --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
packet_in_progress : in std_logic ; --
--
-- DataMover Command --
mm2s_cmnd_wr : out std_logic ; --
mm2s_cmnd_data : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+64+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
mm2s_cache_info : in std_logic_vector
(32-1 downto 0); --
mm2s_desc_baddress : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : in std_logic ; --
mm2s_desc_sof : in std_logic --
);
end axi_dma_mm2s_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant MM2S_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant MM2S_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant MM2S_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_MM2S_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal mm2s_cs : SG_MM2S_STATE_TYPE;
signal mm2s_ns : SG_MM2S_STATE_TYPE;
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal mm2s_cmnd_wr_i : std_logic := '0';
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal mm2s_desc_flush_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_cmnd_wr <= mm2s_cmnd_wr_i;
mm2s_desc_flush <= mm2s_desc_flush_i;
-- Flush any fetch descriptors if stopped due to errors or soft reset
-- or if not in middle of packet and run/stop clears
mm2s_desc_flush_i <= '1' when (mm2s_stop = '1')
or (packet_in_progress = '0'
and mm2s_run_stop = '0')
else '0';
burst_type <= '1' and (not mm2s_keyhole);
-- A 0 on mm2s_kyhole means increment type burst
-- 1 means fixed burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(mm2s_cs,
mm2s_run_stop,
packet_in_progress,
desc_available,
updt_pending,
-- desc_fetch_done,
desc_update_done,
mm2s_cmnd_pending,
mm2s_stop,
mm2s_desc_flush_i
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
mm2s_cmnd_idle <= '0';
mm2s_ns <= mm2s_cs;
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running or Stopped but in middle of xfer and Descriptor
-- data available, No errors logged, and Room to queue more
-- commands, then fetch descriptor
-- if (updt_pending = '1') then
-- mm2s_ns <= IDLE;
if( (mm2s_run_stop = '1' or packet_in_progress = '1')
-- and desc_available = '1' and mm2s_stop = '0' and queue_more = '1' and updt_pending = '0') then
and desc_available = '1' and mm2s_stop = '0' and updt_pending = '0') then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- coverage off
mm2s_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
mm2s_cmnd_idle <= '1';
write_cmnd_cmb <= '0';
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- error detected or run/stop cleared
if(mm2s_desc_flush_i = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
-- descriptor fetch complete
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- mm2s_ns <= EXECUTE_XFER;
elsif(mm2s_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
mm2s_ns <= IDLE;
-- coverage off
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= WAIT_STATUS;
end if;
end if;
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '0';
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- error detected
-- if(mm2s_stop = '1')then
-- mm2s_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(mm2s_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- mm2s_ns <= IDLE;
-- else
-- mm2s_ns <= WAIT_STATUS;
-- end if;
-- else
-- mm2s_ns <= EXECUTE_XFER;
-- end if;
--
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(desc_update_done = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
else
mm2s_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cs <= IDLE;
else
mm2s_cs <= mm2s_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- register state machine signals
-------------------------------------------------------------------------------
--SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1'; --desc_fetch_req_cmb ;
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
-- & PAD_VALUE
-- & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
& PAD_VALUE
& mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
-- & mm2s_desc_blength;
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
& mm2s_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for mm2s is Idle.
-------------------------------------------------------------------------------
-- increment with each command written
count_incr <= '1' when mm2s_cmnd_wr_i = '1' and desc_update_done = '0'
else '0';
-- decrement with each status received
count_decr <= '1' when mm2s_cmnd_wr_i = '0' and desc_update_done = '1'
else '0';
-- count number of queued commands to keep track of what datamover is still
-- working on
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-- coverage off
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift(0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- coverage on
-- Indicate status is idle when no cmnd/sts queued
--mm2s_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
mm2s_sts_idle <= not cmnds_queued_shift (0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued_shift(3) /= '1') then -- < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift(C_PRMY_CMDFIFO_DEPTH-1));
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
|
-------------------------------------------------------------------------------
-- Title : Register File
-- Project :
-------------------------------------------------------------------------------
-- File : reg_file.vhd
-- Author : Calle <calle@Alukiste>
-- Created : 2012-03-11
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-- Multiple 16-bit registers at the internal parallel data bus with address
-- decoding.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity reg_file is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#; -- Base address of the registers
REG_ADDR_BIT : natural := 0 -- number of bits not to compare in
-- address. Gives 2**n registers
);
port (
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
reg_o : out reg_file_type(2**REG_ADDR_BIT-1 downto 0);
reg_i : in reg_file_type(2**REG_ADDR_BIT-1 downto 0);
clk : in std_logic);
end reg_file;
-------------------------------------------------------------------------------
architecture str of reg_file is
constant BASE_ADDRESS_VECTOR : std_logic_vector(14 downto 0) :=
std_logic_vector(to_unsigned(BASE_ADDRESS, 15));
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal reg : reg_file_type(2**REG_ADDR_BIT-1 downto 0) := (others => (others => '0'));
signal data_out : std_logic_vector(15 downto 0) := (others => '0');
begin -- str
-----------------------------------------------------------------------------
-- Transfer data from bus to register
-----------------------------------------------------------------------------
reg_o <= reg;
process (clk)
variable index : integer := 0;
begin -- process
if rising_edge(clk) then
index := to_integer(unsigned(bus_i.addr(REG_ADDR_BIT-1 downto 0)));
if bus_i.addr(14 downto REG_ADDR_BIT) = BASE_ADDRESS_VECTOR(14 downto REG_ADDR_BIT) then
if bus_i.we = '1' then
reg(index) <= bus_i.data;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Output mux
-- (output (others => '0') if we are not selected)
-----------------------------------------------------------------------------
bus_o.data <= data_out;
process (clk)
variable index : integer := 0;
begin -- process
if rising_edge(clk) then
index := to_integer(unsigned(bus_i.addr(REG_ADDR_BIT-1 downto 0)));
if (bus_i.addr(14 downto REG_ADDR_BIT) = BASE_ADDRESS_VECTOR(14 downto REG_ADDR_BIT)) and bus_i.re = '1' then
data_out <= reg_i(index);
else
data_out <= (others => '0');
end if;
end if;
-- is there a problem with using a varibale in a assignment of a signal??
--bus_o.data <= (others => '0') when bus_i.re = '0' else reg_i(index);
end process;
end str;
-------------------------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_ok_5_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_ok_5_e-c.vhd,v 1.1 2006/11/22 10:40:09 wig Exp $
-- $Date: 2006/11/22 10:40:09 $
-- $Log: inst_shadow_ok_5_e-c.vhd,v $
-- Revision 1.1 2006/11/22 10:40:09 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_ok_5_rtl_conf / inst_shadow_ok_5_e
--
configuration inst_shadow_ok_5_rtl_conf of inst_shadow_ok_5_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_ok_5_rtl_conf;
--
-- End of Generated Configuration inst_shadow_ok_5_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
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