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----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/27/2017 08:36:56 AM
-- Module Name: regfile - Behavioral
-- Description:
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity regfile is
Port(
clk: in std_logic;
rst: in std_logic;
read_addr_1: in std_logic_vector(4 downto 0); -- Register source read_data_1
read_addr_2: in std_logic_vector(4 downto 0); -- Register source read_data_2
write_addr: in std_logic_vector(4 downto 0); -- Write dest write_data
write_data: in doubleword; -- Data to be written
halt: in std_logic; -- Control, do nothing on high
write_en: in std_logic; -- write_data is valid
read_data_1: out doubleword; -- Data from read_addr_1
read_data_2: out doubleword; -- Data from read_addr_2
write_error: out std_logic; -- Writing to constant, HW exception
debug_out: out regfile_arr -- Copy of regfile contents for debugger
);
end regfile;
architecture Behavioral of regfile is
-- Contents of regfile, all zeros
signal reggie: regfile_arr := (others => (others => '0'));
begin
-- Synchronous write
process(clk, rst)
begin
if('1' = halt) then
-- Do nothing
else
write_error <= '0';
if('1' = rst) then
reggie <= (others => (others => '0'));
elsif(rising_edge(clk)) then
if('1' = write_en) then
if("00000" = write_addr) then
write_error <= '1';
else
reggie(to_integer(unsigned(write_addr))) <= write_data;
end if; -- write_error
end if; -- write_en
end if; -- rst
end if; -- halt
end process;
-- Asynchronous read
read_data_1 <= reggie(to_integer(unsigned(read_addr_1)));
read_data_2 <= reggie(to_integer(unsigned(read_addr_2)));
-- Asynchronous debug out
debug_out <= reggie;
end Behavioral; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc515.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n01i00515ent IS
END c03s03b00x00p03n01i00515ent;
ARCHITECTURE c03s03b00x00p03n01i00515arch OF c03s03b00x00p03n01i00515ent IS
type A is access integer;
BEGIN
TESTING: PROCESS
variable V: A ;
BEGIN
assert NOT(V = null)
report "***PASSED TEST: c03s03b00x00p03n01i00515"
severity NOTE;
assert ( V = null )
report "***FAILED TEST: c03s03b00x00p03n01i00515 - The null value of an access type is the default initial value of the type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n01i00515arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc515.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n01i00515ent IS
END c03s03b00x00p03n01i00515ent;
ARCHITECTURE c03s03b00x00p03n01i00515arch OF c03s03b00x00p03n01i00515ent IS
type A is access integer;
BEGIN
TESTING: PROCESS
variable V: A ;
BEGIN
assert NOT(V = null)
report "***PASSED TEST: c03s03b00x00p03n01i00515"
severity NOTE;
assert ( V = null )
report "***FAILED TEST: c03s03b00x00p03n01i00515 - The null value of an access type is the default initial value of the type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n01i00515arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc515.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n01i00515ent IS
END c03s03b00x00p03n01i00515ent;
ARCHITECTURE c03s03b00x00p03n01i00515arch OF c03s03b00x00p03n01i00515ent IS
type A is access integer;
BEGIN
TESTING: PROCESS
variable V: A ;
BEGIN
assert NOT(V = null)
report "***PASSED TEST: c03s03b00x00p03n01i00515"
severity NOTE;
assert ( V = null )
report "***FAILED TEST: c03s03b00x00p03n01i00515 - The null value of an access type is the default initial value of the type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n01i00515arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity test2 is
port (
tx : out std_logic);
end entity;
architecture tb of test2 is
begin
process
-- variable boolobj: boolean; -- ADDED
procedure transmit(data: std_logic_vector; signal tx: out std_logic) is
variable norm: std_logic_vector(data'length - 1 downto 0) := data;
procedure send(value: std_logic) is
begin
tx <= value;
wait for 10 ns;
end procedure;
begin
-- report " boolobj = " & boolean'image(boolobj); -- ADDED
for i in norm'reverse_range loop
send(norm(i));
report integer'image(i); --- to_string(i); -- CHANGED
end loop;
end procedure;
variable norm: std_logic_vector(7 downto 0); -- ADDED
begin
transmit(x"55", tx);
for i in norm'reverse_range loop -- ADDED Loop statement
report "i = " & integer'image(i);
end loop;
wait;
end process;
end architecture;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' THEN
b <= '0';
elsif c = '1' THEN
b <= '1';
else
if x = '1' THEN
z <= '0';
elsif x = '0' THEN
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.PhoenixPackage.all;
package TablePackage is
constant NREG : integer := 6;
constant MEMORY_SIZE : integer := NREG;
constant NBITS : integer := 4;
constant CELL_SIZE : integer := 2*NPORT+4*NBITS;
subtype cell is std_logic_vector(CELL_SIZE-1 downto 0);
subtype regAddr is std_logic_vector(2*NBITS-1 downto 0);
type memory is array (0 to MEMORY_SIZE-1) of cell;
type tables is array (0 to NROT-1) of memory;
constant TAB: tables :=(
-- Router 0.0
(("10000000000010000010000100"),
( "10000000100000100010000001"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 0.1
(("11100000100000100000100001"),
("11001000000100100010000100"),
("10101000000000000000001000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 0.2
(("10101000000000000000101000"),
("11001000000110100010000100"),
("11100000100000100001000001"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 0.3
(("11100000100110010001100001"),
("11001000001000010010000100"),
("11100001100110100010000001"),
("10101000000000100001001000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 0.4
(("11000000101000010010000001"),
("10000001100000100010001001"),
("10001000000000010001101000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 1.0
(("10101000000000000000000010"),
("10010000000010001010000100"),
("10010001000000100010000001"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 1.1
(("10111000000000001000001000"),
("11001000000000000000100010"),
("11110001000000100000100001"),
("11001000000100100010000100"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 1.2
(("11110001000100010001000001"),
("10111000000000000000001000"),
("11001000000000000010000010"),
("11110001100100100010000001"),
("11001000100110100010000100"),
("10111000100000100000101000")
),
-- Router 1.3
(("11110001000110010001100001"),
("11011000101000010010000100"),
("11110001100110100010000001"),
("11101000000000000010000010"),
("10111000100000100001001000"),
("00000000000000000000000000")
),
-- Router 1.4
(("10001000001000000010000010"),
("10000001100000100010001001"),
("10001000000000010001101000"),
("11010001000000100010000001"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 2.0
(("10101000000000001000000010"),
("10010001100000100010000001"),
("10010000000010010010000100"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 2.1
(("10111000000000010000001000"),
("11110001100000100000100001"),
("11001000000000001000100010"),
("11001000000100100010000100"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 2.2
(("10111001000000010000101000"),
("10111000000000001000001000"),
("11001000000000001001000010"),
("11110001100000100010000001"),
("11001000000110100010000100"),
("00000000000000000000000000")
),
-- Router 2.3
(("10111000000000001000001000"),
("11001000001000010010000100"),
("11110001100110100010000001"),
("11001000000000001001100010"),
("10111001000000100001001000"),
("00000000000000000000000000")
),
-- Router 2.4
(("10010001000000010001101000"),
("10010001100000100010001000"),
("11000000000000001010000010"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.0
(("10101000000000010000000010"),
("10010010000000100010000001"),
("10010000000010011010000100"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.1
(("11110010000000100000100001"),
("10111000000000011000001000"),
("11001000000000010000100010"),
("11001000000100100010000100"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.2
(("11011001100110011010000100"),
("11110010000100100010000001"),
("10111001100000100000101000"),
("11101000000000010010000010"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.3
(("11011001101000011010000100"),
("11110010000110100010000001"),
("10101000000110010010000010"),
("10101000000000100001001000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.4
(("10000001100000011001101000"),
("10000010000000100010000001"),
("10000000000000010010001000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.0
(("10010000000010100010000100"),
("10100000000000011000000010"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.1
(("10110000000000100000001000"),
("11000000000000011000100010"),
("11000000000100100010000100"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.2
(("11010010000110100010000100"),
("10110010000000100000101000"),
("11100000000000011010000010"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.3
(("11010001101000100010000100"),
("10100000000110011010000010"),
("10100000000000100001001000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.4
(("11000001101000011010000010"),
("10010000000000010010001000"),
("10010001100000100001101000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
)
);
end TablePackage;
package body TablePackage is
end TablePackage;
|
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 11:09:53 05/16/2016
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use work.helpers.all;
entity dds is
Generic (clk_freq: natural:= 50000000; -- Clock frequency in hz
freq_res: natural:=17; -- width of frequency input (log2(max_freq))
adc_res: natural:=12; -- width of the output signal (=adc resolution)
acc_res: natural:=32; -- width of the phase accumulator
phase_res: natural:=10); -- effective phase resolution for sin lookup table
Port ( clk : in STD_LOGIC; -- Clock input
freq : in unsigned (freq_res-1 downto 0); -- Frequenzy input (treshould in Hz)
form : in unsigned (1 downto 0); -- Form selection (00=Rectancle, 01=Sawtooth, 10=Triangle, 11=Sine)
amp : out unsigned (adc_res-1 downto 0)); -- Signal Output (Amplitude)
end dds;
architecture Behavioral of dds is
signal m, idx : unsigned(acc_res -1 downto 0):= (others => '0'); -- phase jump size and accumulator (see Fundamentals of Direct Digital Synthesis for details about their function)
signal idx_phase : unsigned(phase_res-1 downto 0) := (others => '0'); -- relevant (=leftmost) bits of the phase acccumulator
signal amp_rect, amp_saw, amp_tria, amp_sin : unsigned (adc_res-1 downto 0); -- the current amplitudes of all 4 signal forms
-- Function to genenerate and store the sine wave in the rom.
-- Current code: Only store 1/4 of a sine wave and use symmetries.
-- Uncommented code: Store the entire sine wave (decrease adc_width to 8)
type storage is array (((2**phase_res)/4)-1 downto 0) of unsigned (adc_res-2 downto 0);
--type storage is array (((2**phase_res))-1 downto 0) of unsigned (adc_res-1 downto 0);
function gen_sin_wave return storage is
variable temp : storage;
begin
forLoop: for i in 0 to temp'high loop -- for each element in the array
temp(i) := to_unsigned(integer(real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI/2.0)/real(temp'high))),adc_res-1);
--temp(i) := to_unsigned(integer(real(2**(adc_res-1) -1) + real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI*2.0)/real(temp'high))),adc_res);
end loop;
return temp;
end function gen_sin_wave;
constant sin_wave : storage := gen_sin_wave; -- rom for sin wave
begin
-- Calculate jump size according to input frequency
-- m = fout*(2^n)/fclk = fout*((2^n)*(2^k)/fclk)/(2^k) with k=ceil(log2(fclk)), n=acc_res
m <= resize( (resize(freq,64)
*
(shift_left(to_unsigned(1,64),acc_res + log2_int(clk_freq)) / clk_freq))
/to_unsigned(2**log2_int(clk_freq),64),acc_res);
-- Amplitude of the square wave
amp_rect <= to_unsigned(0,adc_res) when idx(acc_res-1)='0' else -- 0 for half of the time
to_unsigned((2**adc_res)-1,adc_res); --1 for the rest
-- Amplitude of the sawtooth wave
amp_saw <= idx(acc_res -1 downto acc_res - adc_res); -- Exactly the value of the uppermost bits of the phase acc
-- Amplitude of the triangle wave
amp_tria <= idx(acc_res -2 downto acc_res - adc_res - 1) -- The value of the uppermost bits, except the uppermost one (= double the frequency)
when idx(acc_res-1)='0' else -- during half of the time
((2**adc_res)-1)- (idx(acc_res -2 downto acc_res - adc_res - 1)); -- and the complement, the rest of the time
idx_phase <= idx(acc_res -1 downto acc_res - phase_res); -- take only the uppermost bits for the sine lookup
-- Amplitude of the sine wave
-- Code if we had stored the whole sinewave:
-- amp_sin <= sin_wave(to_integer(idx_phase));
-- Current Code (only 1/4 of the sine wave stored)
amp_sin <= to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="00" else
to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="01" else
to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="10" else
to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0)));
-- Output the selected amplitue using a multiplexer (00=Rectancle, 01=Sawtooth, 10=Triangle, 11=Sine)
amp <= to_unsigned(0,adc_res) when freq = to_unsigned(0,freq_res) else
amp_rect when form = "00" else
amp_saw when form ="01" else
amp_tria when form = "10" else
amp_sin;
-- Process for the phase accumulator (sequential)
P1: process(clk)
begin
if(rising_edge(clk)) then
idx <= (idx+m); -- increment phase accumulator according to jump size. overflow is wanted.
end if;
end process P1;
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity MEM_stage is
port(
rst : in vl_logic;
DataMemoryAddress: in vl_logic_vector(15 downto 0);
DataMemoryWriteData: in vl_logic_vector(15 downto 0);
DataMemoryWriteEnable: in vl_logic;
DataMemoryOut : out vl_logic_vector(15 downto 0)
);
end MEM_stage;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_512x8x.vhd when simulating
-- the core, fifo_512x8x. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_512x8x IS
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
END fifo_512x8x;
ARCHITECTURE fifo_512x8x_a OF fifo_512x8x IS
-- synthesis translate_off
component wrapped_fifo_512x8x
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_512x8x use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 509,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 510,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "2kx9",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_512x8x
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
wr_data_count => wr_data_count);
-- synthesis translate_on
END fifo_512x8x_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_512x8x.vhd when simulating
-- the core, fifo_512x8x. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_512x8x IS
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
END fifo_512x8x;
ARCHITECTURE fifo_512x8x_a OF fifo_512x8x IS
-- synthesis translate_off
component wrapped_fifo_512x8x
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_512x8x use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 509,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 510,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "2kx9",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_512x8x
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
wr_data_count => wr_data_count);
-- synthesis translate_on
END fifo_512x8x_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_512x8x.vhd when simulating
-- the core, fifo_512x8x. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_512x8x IS
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
END fifo_512x8x;
ARCHITECTURE fifo_512x8x_a OF fifo_512x8x IS
-- synthesis translate_off
component wrapped_fifo_512x8x
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_512x8x use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 509,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 510,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "2kx9",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_512x8x
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
wr_data_count => wr_data_count);
-- synthesis translate_on
END fifo_512x8x_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_512x8x.vhd when simulating
-- the core, fifo_512x8x. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_512x8x IS
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
END fifo_512x8x;
ARCHITECTURE fifo_512x8x_a OF fifo_512x8x IS
-- synthesis translate_off
component wrapped_fifo_512x8x
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_512x8x use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 509,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 510,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "2kx9",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_512x8x
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
wr_data_count => wr_data_count);
-- synthesis translate_on
END fifo_512x8x_a;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity stub_ram_int is
Port ( memAddress : in STD_LOGIC_VECTOR (26 downto 0);
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0);
valid : in STD_LOGIC;
done : out STD_LOGIC;
write : in STD_LOGIC;
chip_select : in STD_LOGIC;
err : out STD_LOGIC;
clk, reset : in STD_LOGIC );
end stub_ram_int;
architecture Behavioral of stub_ram_int is
component stub_ram
port(
address : in STD_LOGIC_VECTOR (13 downto 0);
clock : in STD_LOGIC;
we : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal s_mem_address : STD_LOGIC_VECTOR (13 downto 0);
signal s_data_in : STD_LOGIC_VECTOR (7 downto 0);
signal s_mem_clock : STD_LOGIC;
signal s_write : STD_LOGIC;
signal s_mem_data_out : STD_LOGIC_VECTOR (7 downto 0);
type memState is ( WAITING, INVALID_REQUEST, MEM_CLOCK, FINISH );
signal curr_state : memState;
begin
MEM : stub_ram
port map ( address => s_mem_address,
clock => s_mem_clock,
we => s_write,
dataIn => s_data_in,
dataOut => s_mem_data_out);
process( clk, reset )
begin
if ( reset = '1' ) then
err <= '0';
done <= '0';
curr_state <= WAITING;
elsif ( rising_edge( clk ) ) then
case curr_state is
when WAITING =>
s_mem_clock <= '0';
done <= '0';
err <= '0';
if( (valid = '1') and (chip_select = '1') ) then
if( (memAddress < x"0700000") and (memAddress >= x"06FC000") ) then
s_mem_address <= memAddress(13 downto 0);
s_data_in <= dataIn;
s_write <= write;
curr_state <= MEM_CLOCK;
else
curr_state <= INVALID_REQUEST;
end if;
end if;
when INVALID_REQUEST =>
err <= '1';
done <= '1';
if( valid = '0' ) then
curr_state <= WAITING;
end if;
when MEM_CLOCK =>
s_mem_clock <= '1';
curr_state <= FINISH;
when FINISH =>
done <= '1';
err <= '0';
dataOut <= s_mem_data_out;
if( valid = '0' ) then
curr_state <= WAITING;
end if;
end case;
end if;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gbit
-- File: greth_gbit.vhd
-- Author: Marko Isomaki
-- Description: Gigabit Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greth_gbit is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth_gbit is
--host constants
constant fifosize : integer := 512;
constant fabits : integer := log2(fifosize);
constant fsize : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(fifosize, fabits+1);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, 0),
others => zero32);
constant ehconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0),
others => zero32);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufsize : integer := ebuf(log2(edclbufsz));
signal irq : std_ulogic;
signal gnd : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(8 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(8 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(8 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(8 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
-- Fix for wider bus
signal hwdata : std_logic_vector(31 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
begin
gnd <= '0';
gtxc0: greth_gbitc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
sim => sim,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => 0,
ramdebug => ramdebug,
mdiohold => mdiohold,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ahbmi.hgrant(hindex),
ehready => ahbmi.hready,
ehresp => ahbmi.hresp,
ehrdata => hrdata,
--edcl ahb mst out
ehbusreq => open,
ehlock => open,
ehtrans => open,
ehaddr => open,
ehwrite => open,
ehsize => open,
ehburst => open,
ehprot => open,
ehwdata => open,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
gtx_clk => ethi.gtx_clk,
tx_clk => ethi.tx_clk,
tx_dv => ethi.tx_dv,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd,
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
rx_en => ethi.rx_en,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd,
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => etho.mdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
testoen => ahbmi.testoen,
gbit => etho.gbit,
speed => etho.speed,
--cfg
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable);
etho.tx_clk <= '0'; -- driven in rgmii component
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, testen => scanen)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata, ahbmi.testin);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, testen => scanen)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata, ahbmi.testin);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16, 0, 0, scanen) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16), ahbmi.testin);
r1 : syncram_2p generic map (memtech, eabits, 16, 0, 0, scanen) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0), ahbmi.testin);
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100/1000 Mbit Ethernet MAC rev " &
tost(REVISION) & tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz*edcl) & " kbyte " & tost(fifosize) & " txfifo, " &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
|
------- binary to bcd converter
------- Uses the ADD-3 (or Double-Dabble) algorithm
------- 12 bit std_logic_vector in, 16 bit std_logic_vector out (4 BCD digits)
------- USAGE: BCD <= to_bcd(BIN);
-------
------- include this text at the beginning of the architecture body, after the signal declarations
-------
------- (adapted from an 8-bit design from http://vhdlguru.blogspot.ca/2010/04/8-bit-binary-to-bcd-converter-double.html)
-------
--
function to_bcd ( bin : std_logic_vector((11) downto 0) ) return std_logic_vector is
variable i : integer:=0;
variable j : integer:=1;
variable bcd : std_logic_vector((15) downto 0) := (others => '0');
variable bint : std_logic_vector((11) downto 0) := bin;
begin
for i in 0 to 11 loop -- repeating 12 times.
bcd((15) downto 1) := bcd((14) downto 0); --shifting the bits.
bcd(0) := bint(11);
bint((11) downto 1) := bint((10) downto 0);
bint(0) :='0';
l1: for j in 1 to 4 loop
if(i < 11 and bcd(((4*j)-1) downto ((4*j)-4)) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(((4*j)-1) downto ((4*j)-4)) := std_logic_vector(unsigned(bcd(((4*j)-1) downto ((4*j)-4))) + "0011");
end if;
end loop l1;
end loop;
return bcd;
end to_bcd; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:01 01/15/2015
-- Design Name:
-- Module Name: componant_2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity componant_2 is
Port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
rin : in STD_LOGIC;
rout : out STD_LOGIC;
s1 : out STD_LOGIC);
end componant_2;
architecture Behavioral of componant_2 is
component componant_1 is
Port ( e1 : in STD_LOGIC;
e2 : in STD_LOGIC;
s1 : out STD_LOGIC;
s2 : out STD_LOGIC);
end component;
signal n1, n2, n3 : std_logic;
begin
inst1 : componant_1 port map (e1=>a1,e2=>b1,s1=>n1,s2=>n2);
inst2 : componant_1 port map (e1=>n1,e2=>rin,s1=>s1,s2=>n3);
rout <= n2 or n3;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:01 01/15/2015
-- Design Name:
-- Module Name: componant_2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity componant_2 is
Port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
rin : in STD_LOGIC;
rout : out STD_LOGIC;
s1 : out STD_LOGIC);
end componant_2;
architecture Behavioral of componant_2 is
component componant_1 is
Port ( e1 : in STD_LOGIC;
e2 : in STD_LOGIC;
s1 : out STD_LOGIC;
s2 : out STD_LOGIC);
end component;
signal n1, n2, n3 : std_logic;
begin
inst1 : componant_1 port map (e1=>a1,e2=>b1,s1=>n1,s2=>n2);
inst2 : componant_1 port map (e1=>n1,e2=>rin,s1=>s1,s2=>n3);
rout <= n2 or n3;
end Behavioral;
|
-- NEED RESULT: ARCH00117.P1: Multi transport transactions occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00117: One transport transaction occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00117: Old transactions were removed on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00117
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00117(ARCH00117)
-- ENT00117_Test_Bench(ARCH00117_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00117 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00117 ;
--
architecture ARCH00117 of ENT00117 is
begin
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00117.P1" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00117" ,
"One transport transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00117" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00117" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
--
end ARCH00117 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00117_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00117_Test_Bench ;
--
architecture ARCH00117_Test_Bench of ENT00117_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00117 ( ARCH00117 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
) ;
end block L1 ;
end ARCH00117_Test_Bench ;
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-----------H----H--X----X-----CCCCC----22222----0000-----0000------11----------
----------H----H----X-X-----C--------------2---0----0---0----0--1--1-----------
---------HHHHHH-----X------C----------22222---0----0---0----0-----1------------
--------H----H----X--X----C----------2-------0----0---0----0-----1-------------
-------H----H---X-----X---CCCCC-----222222----0000-----0000----1111------------
-------------------------------------------------------------------------------
----------------------------------------- http://jeanfrancoisdelnero.free.fr --
--===========================================================================--
-- HxCFloppyEmu
-- Floppy drive emulator Project
--
-- http://jeanfrancoisdelnero.free.fr
-- HxC2001 - 2006 - 2008
--
-- Design units :
--
-- File name : HeadShifter.vhd
--
-- Purpose : MFM data shifter
--
--
-- Dependencies : IEEE.Std_Logic_1164
-- IEEE.std_logic_signed
--
--============================================================================-
-- --
-- Copyright (C) 2006, 2007, 2008 Jean-François DEL NERO --
-- --
-- This file is part of HxCFloppyEmulator. --
-- --
-- HxCFloppyEmulator may be used and distributed without restriction provided--
-- that this copyright statement is not removed from the file and that any --
-- derivative work contains the original copyright notice and the associated --
-- disclaimer. --
-- --
-- HxCFloppyEmulator is free software; you can redistribute it --
-- and/or modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 2 --
-- of the License, or (at your option) any later version. --
-- --
-- HxCFloppyEmulator is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. --
-- See the GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with HxCFloppyEmulator; if not, write to the Free Software --
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA--
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 1.0 Jean-François DEL NERO 23 march 2008 Major update:
--
-- MFM/FM output generator (HeadShifter) rewritten.
-- It can now do any bitrate between
-- 63kbit/s and 1Mbit/s with a 62.5ns step.
-- The emulator can now handle bitrate-protected floppies ;-)
--
-- The SRAM is now used like a ring buffer (1 buffer of 8KB).
--
-- The master state machine run now at 16Mhz
-- to allow fast opcode execution / mfm loading.
--
-- "Validate Track" opcode removed (same functionnality in "SENDTRACKCODE opcode".
-- "SETINDEX" opcode modified:
-- "SENDTRACKCODE" added (2 byte : 0x3 <track number>)
-- "SETBITRATE" opcode added (2 bytes: 0xD <period value>)
-- "NOP" opcode added (2 bytes : 0x7 XX)
-- "Disk Changed" and "Ready" signals
-- are now software driven
--
-- Track position register is now 8 bits.
--
-- SRAM_CS_not is now driven (for the SRAM standby mode)
--
-- 0.5 Jean-François DEL NERO 19 November 2006 Jumper-free drive select added
-- jeanfrancoisdelnero < > free.fr
-- 0.4 Jean-François DEL NERO 11 November 2006 500kbits/s support added
-- 2*1Ko and 2*2Ko buffer size available
-- Write protect signal added
-- Shugart and IBM PC mode available
-- 0.2 Jean-François DEL NERO 16 September 2006 MFM Pulse Generator rewritten
-- 0.1 Jean-François DEL NERO 25 June 2006 First public version
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- package HeadShifter
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------
-- MFM data shifter
--
entity HeadShifter is
port (
-- input // data bus
DATABUS: in std_logic_vector(3 downto 0);
SPEEDCONFIG: in std_logic_vector(7 downto 0);
DATALOADED: out std_logic;
FLOPPY_DATA: out std_logic; -- MFM data line
clock: in std_logic; -- Clock the shifter
reset_not: in std_logic
);
end HeadShifter;
------------------------------------------------------------------------------------------
architecture arch of HeadShifter is
--------------------------------------------
type state_shifter is (STATE0,STATE1,STATE2,STATE3);
signal FLOPPYDATAH0 : std_logic; -- shifter -> pulse generator link
signal speedcnt: std_logic_vector(7 downto 0);
signal tmp: std_logic_vector(3 downto 0);
signal bitcnt: state_shifter;
signal bitcounter: std_logic_vector(1 downto 0);
signal loadtoggle: std_logic;
------------------------------------------------------------------------------------------
BEGIN
process (speedcnt,SPEEDCONFIG,tmp,clock,reset_not)
begin
if (reset_not = '0')
then
speedcnt(7 downto 0)<="00000000";
bitcounter<="00";
loadtoggle<='0';
tmp<="0000";
elsif (clock'event and clock = '1')
then
if(speedcnt(7 downto 1)/="0000000")
then
-- decrement the bitrate prescaler
speedcnt(7 downto 1)<=speedcnt(7 downto 1)-"0000001";
else
-- test we have done a full mfm code (2 bits)
--
if(bitcounter(0)='0' or speedcnt(0)='0')
then
-- increment the bit counter
bitcounter<=bitcounter+"01";
-- shift the data register
tmp <= tmp(2 downto 0) & '0';
if(bitcounter="00")
then
-- we have done all the four bits (2 mfm bits)
-- we need to reload the shifter.
loadtoggle<=not(loadtoggle);
tmp<=DATABUS;
end if;
-- reload of the bitrate prescaler
if(SPEEDCONFIG(7 downto 0)<"00001110")
then
-- the bitrate can't be higher than 1Mbits/s
speedcnt<="00001110";
else
speedcnt<=SPEEDCONFIG;
end if;
else
-- to have the 62.5ns step precision for 2 bits (1 mfm bit).
if(speedcnt(0)='1')
then
speedcnt(0)<='0';
end if;
end if;
end if;
end if;
-- 25% duty cycle signal generator
if(speedcnt(7 downto 1)>('0' & SPEEDCONFIG(7 downto 2)))
then
FLOPPY_DATA <= tmp(3);
else
FLOPPY_DATA <= '0';
end if;
end process;
DATALOADED<=loadtoggle;
END arch; |
architecture RTL of FIFO is
begin
process
begin
a <= b; -- level 2
ab <= xy; -- level 2
-- level 2
if (a = b) then -- level 2
z <= y; -- level 3
-- level 2
elsif (a + b -c = z) then -- level 2
z <= x; -- level 3
end if; -- level 2
end process; -- level 1
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_24 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_24;
architecture BEHAVIORAL of dcm_32_24 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 24.000 = 32.000 * 15/20
CLKFX_DIVIDE => 20,
CLKFX_MULTIPLY => 15,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
entity access2 is
end entity;
architecture test of access2 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
subtype int_vec10 is int_vec(1 to 10);
type int_vec10_ptr is access int_vec10;
subtype one_to_3 is integer range 1 to 3;
begin
process is
variable p : int_vec_ptr;
variable q : int_vec10_ptr;
variable r : int_vec_ptr;
begin
p := new int_vec(1 to 5);
p(1) := 2;
assert p(1) = 2;
deallocate(p);
assert p = null;
q := new int_vec10;
q(3) := 5;
assert q(3) = 5;
deallocate(q);
r := new int_vec(one_to_3'range);
deallocate(r);
wait;
end process;
end architecture;
|
entity access2 is
end entity;
architecture test of access2 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
subtype int_vec10 is int_vec(1 to 10);
type int_vec10_ptr is access int_vec10;
subtype one_to_3 is integer range 1 to 3;
begin
process is
variable p : int_vec_ptr;
variable q : int_vec10_ptr;
variable r : int_vec_ptr;
begin
p := new int_vec(1 to 5);
p(1) := 2;
assert p(1) = 2;
deallocate(p);
assert p = null;
q := new int_vec10;
q(3) := 5;
assert q(3) = 5;
deallocate(q);
r := new int_vec(one_to_3'range);
deallocate(r);
wait;
end process;
end architecture;
|
entity access2 is
end entity;
architecture test of access2 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
subtype int_vec10 is int_vec(1 to 10);
type int_vec10_ptr is access int_vec10;
subtype one_to_3 is integer range 1 to 3;
begin
process is
variable p : int_vec_ptr;
variable q : int_vec10_ptr;
variable r : int_vec_ptr;
begin
p := new int_vec(1 to 5);
p(1) := 2;
assert p(1) = 2;
deallocate(p);
assert p = null;
q := new int_vec10;
q(3) := 5;
assert q(3) = 5;
deallocate(q);
r := new int_vec(one_to_3'range);
deallocate(r);
wait;
end process;
end architecture;
|
entity access2 is
end entity;
architecture test of access2 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
subtype int_vec10 is int_vec(1 to 10);
type int_vec10_ptr is access int_vec10;
subtype one_to_3 is integer range 1 to 3;
begin
process is
variable p : int_vec_ptr;
variable q : int_vec10_ptr;
variable r : int_vec_ptr;
begin
p := new int_vec(1 to 5);
p(1) := 2;
assert p(1) = 2;
deallocate(p);
assert p = null;
q := new int_vec10;
q(3) := 5;
assert q(3) = 5;
deallocate(q);
r := new int_vec(one_to_3'range);
deallocate(r);
wait;
end process;
end architecture;
|
entity access2 is
end entity;
architecture test of access2 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
subtype int_vec10 is int_vec(1 to 10);
type int_vec10_ptr is access int_vec10;
subtype one_to_3 is integer range 1 to 3;
begin
process is
variable p : int_vec_ptr;
variable q : int_vec10_ptr;
variable r : int_vec_ptr;
begin
p := new int_vec(1 to 5);
p(1) := 2;
assert p(1) = 2;
deallocate(p);
assert p = null;
q := new int_vec10;
q(3) := 5;
assert q(3) = 5;
deallocate(q);
r := new int_vec(one_to_3'range);
deallocate(r);
wait;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_t
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:34:27 2007
-- cmd: /home/wig/work/MIX/mix_0.pl ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-conf-c.vhd,v 1.1 2007/03/05 13:35:50 wig Exp $
-- $Date: 2007/03/05 13:35:50 $
-- $Log: ent_t-rtl-conf-c.vhd,v $
-- Revision 1.1 2007/03/05 13:35:50 wig
-- Reworked testcase sigport (changed case of generated files).
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_t_RTL_CONF / ent_t
--
configuration ent_t_RTL_CONF of ent_t is
for rtl
-- Generated Configuration
for inst_a : ent_a
use configuration work.ent_a_RTL_CONF;
end for;
for inst_b : ent_b
use configuration work.ent_b_RTL_CONF;
end for;
end for;
end ent_t_RTL_CONF;
--
-- End of Generated Configuration ent_t_RTL_CONF
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.pf_occ_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
By_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1);
almost_full : Out std_logic;
full : Out std_logic;
almost_empty : Out std_logic;
empty : Out std_logic
);
end entity pf_occ_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
Signal upper_cleared : std_logic;
Signal lower_set : std_logic;
Signal lower_cleared : std_logic;
Signal empty_state : std_logic_vector(0 to 2);
Signal full_state : std_logic_vector(0 to 3);
Signal sig_full : std_logic;
Signal sig_almost_full : std_logic;
Signal sig_going_full : std_logic;
Signal sig_empty : std_logic;
Signal sig_almost_empty : std_logic;
begin -- VHDL_RTL
full <= sig_full;
almost_full <= sig_almost_full;
empty <= sig_empty;
almost_empty <= sig_almost_empty;
-- Misc signal assignments
Count_Out <= sig_count_out;
sig_cnt_enable <= (Count_Up and not(sig_full))
xor (Count_Down and not(sig_empty));
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v3_00_a.pf_occ_counter
generic map (
C_COUNT_WIDTH
)
port map(
Clk => Clk,
Rst => Rst,
Carry_Out => sig_carry_out,
Load_In => Load_value,
Count_Enable => sig_cnt_enable,
Count_Load => Load_Enable,
Count_Down => sig_cnt_up_n_dwn,
Cnt_by_2 => By_2,
Count_Out => sig_count_out
);
TEST_UPPER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable loop_count : integer;
Begin
--loop_count := 0;
all_cleared := True;
for loop_count in 0 to C_COUNT_WIDTH-2 loop
If (sig_count_out(loop_count) = '1') Then
all_cleared := False;
else
null;
End if;
End loop;
-- -- Search through the upper counter bits starting with the MSB
-- while (loop_count < C_COUNT_WIDTH-2) loop
--
-- If (sig_count_out(loop_count) = '1') Then
-- all_cleared := False;
-- else
-- null;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
upper_cleared <= '1';
else
upper_cleared <= '0';
End if;
End process TEST_UPPER_BITS;
empty_state <= upper_cleared & sig_count_out(C_COUNT_WIDTH-2) &
sig_count_out(C_COUNT_WIDTH-1);
STATIC_EMPTY_DETECT : process (empty_state)
Begin
Case empty_state Is
When "100" =>
sig_empty <= '1';
sig_almost_empty <= '0';
When "101" =>
sig_empty <= '0';
sig_almost_empty <= '1';
When "110" =>
sig_empty <= '0';
sig_almost_empty <= '0';
When others =>
sig_empty <= '0';
sig_almost_empty <= '0';
End case;
End process STATIC_EMPTY_DETECT;
TEST_LOWER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable all_set : boolean;
Variable loop_count : integer;
Begin
--loop_count := 1;
all_set := True;
all_cleared := True;
for loop_count in 1 to C_COUNT_WIDTH-1 loop
If (sig_count_out(loop_count) = '0') Then
all_set := False;
else
all_cleared := False;
End if;
End loop;
-- -- Search through the lower counter bits starting with the MSB+1
-- while (loop_count < C_COUNT_WIDTH-1) loop
--
-- If (sig_count_out(loop_count) = '0') Then
-- all_set := False;
-- else
-- all_cleared := False;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
lower_cleared <= '1';
lower_set <= '0';
elsif (all_set) Then
lower_cleared <= '0';
lower_set <= '1';
else
lower_cleared <= '0';
lower_set <= '0';
End if;
End process TEST_LOWER_BITS;
full_state <= sig_count_out(0)
& lower_set
& lower_cleared
& sig_count_out(C_COUNT_WIDTH-1);
STATIC_FULL_DETECT : process (full_state, sig_count_out)
Begin
sig_full <= sig_count_out(0); -- MSB set implies full
Case full_state Is
When "0100" =>
sig_almost_full <= '0';
sig_going_full <= '1';
When "0101" =>
sig_almost_full <= '1';
sig_going_full <= '0';
When others =>
sig_almost_full <= '0';
sig_going_full <= '0';
End case;
End process STATIC_FULL_DETECT;
end architecture implementation;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
--Copyright 2017 Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.ALL;
entity mem_array_ROM is
GENERIC(
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 6;
INIT_FILE : string);
Port(
ADDR : in STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0)
);
end mem_array_ROM;
architecture dataflow of mem_array_ROM is
Type MEMORY_ARRAY is ARRAY (0 to 2**(ADDR_WIDTH)-1) of STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
impure function init_memory_wfile(mif_file_name : in string) return MEMORY_ARRAY is
file mif_file : text open read_mode is mif_file_name;
variable mif_line : line;
variable temp_bv : bit_vector(DATA_WIDTH-1 downto 0);
variable temp_mem : MEMORY_ARRAY;
begin
for i in MEMORY_ARRAY'range loop
readline(mif_file, mif_line);
read(mif_line, temp_bv);
temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
constant memory : MEMORY_ARRAY:=(init_memory_wfile(INIT_FILE));
begin
OUTPUT <= memory(to_integer(unsigned(ADDR)));
end dataflow; |
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7056)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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LGuAyzGOnA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7056)
`protect data_block
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|
`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.myDeclare.all;
ENTITY TB_com_scheduler IS
END TB_com_scheduler;
ARCHITECTURE behavior OF TB_com_scheduler IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT com_scheduler
PORT(
clk : IN std_logic;
reset : IN std_logic;
device_data_array : in device_data_array_type; -- Array of dimension (No. of device x 16bits) data, each 16bits corresponds to 1 device input stream
device_flag_array : in std_logic_vector(0 to NUMBEROFDEVICE-1);
serdes_data_out : OUT std_logic_vector(11 downto 0);
serdes_valid_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal device_data_array : device_data_array_type;
signal device_flag_array : std_logic_vector(0 to NUMBEROFDEVICE-1);
--Outputs
signal serdes_data_out : std_logic_vector(11 downto 0);
signal serdes_valid_out : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: com_scheduler PORT MAP (
clk => clk,
reset => reset,
device_data_array => device_data_array,
device_flag_array => device_flag_array,
serdes_data_out => serdes_data_out,
serdes_valid_out => serdes_valid_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- insert stimulus here
device_data_array(0) <= std_logic_vector(to_unsigned(172, 16));
device_data_array(1) <= std_logic_vector(to_unsigned(65, 16));
device_data_array(2) <= std_logic_vector(to_unsigned(32, 16));
device_data_array(3) <= std_logic_vector(to_unsigned(88, 16));
device_flag_array <= (others=>'1');
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
wait;
end process;
END;
|
-- $Id: rlinktblib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: rlinktblib
-- Description: rlink test environment components
--
-- Dependencies: -
-- Tool versions: xst 8.2-14.7; viv 2015.4-2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-13 730 4.1 drop tbcore_rlink component definition
-- 2014-08-28 588 4.0 now full rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-12-23 444 3.1 new clock iface for tbcore_rlink; drop .._dcm
-- 2010-12-29 351 3.0.1 add rbtba_aif;
-- 2010-12-24 347 3.0 rename rritblib->rlinktblib, CP_*->RL_*;
-- many rri->rlink renames; drop rbus parts;
-- 2010-11-13 338 2.5.2 add rritb_core_dcm
-- 2010-06-26 309 2.5.1 add rritb_sres_or_mon
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-05 301 2.1.2 renamed _rpmon -> _rbmon
-- 2010-05-02 287 2.1.1 rename CE_XSEC->CE_INT,RP_STAT->RB_STAT
-- drop RP_IINT signal from interfaces
-- add sbcntl_sbf_(cp|rp)mon defs
-- 2010-04-24 282 2.1 add rritb_core
-- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.1.5 CLK_CYCLE now 31 bits
-- 2007-12-23 105 1.1.4 add AP_LAM for rritb_rpmon(_sb)
-- 2007-11-24 98 1.1.3 add RP_IINT for rritb_rpmon(_sb)
-- 2007-09-01 78 1.1.2 add rricp_rp
-- 2007-08-25 75 1.1.1 add rritb_cpmon_sb, rritb_rpmon_sb
-- 2007-08-16 74 1.1 remove rritb_tt* component; some interface changes
-- 2007-08-03 71 1.0.2 use rrirp_acif; change generics for rritb_[cr]pmon
-- 2007-07-22 68 1.0.1 add rritb_cpmon rritb_rpmon monitors
-- 2007-07-15 66 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rlinklib.all;
package rlinktblib is
type rlink_tba_cntl_type is record -- rlink_tba control
cmd : slv3; -- command code
ena : slbit; -- command enable
addr : slv16; -- address
cnt : slv16; -- block size
eop : slbit; -- end packet after current command
end record rlink_tba_cntl_type;
constant rlink_tba_cntl_init : rlink_tba_cntl_type := (
(others=>'0'), -- cmd
'0', -- ena
(others=>'0'), -- addr
(others=>'0'), -- cnt
'0'); -- eop
type rlink_tba_stat_type is record -- rlink_tba status
busy : slbit; -- command busy
ack : slbit; -- command acknowledge
err : slbit; -- command error flag
stat : slv8; -- status flags
braddr : slv16; -- block read address (for wblk)
bre : slbit; -- block read enable (for wblk)
bwaddr : slv16; -- block write address (for rblk)
bwe : slbit; -- block write enable (for rblk)
dcnt : slv16; -- block done count
apend : slbit; -- attn pending (from stat)
ano : slbit; -- attn notify seen
apat : slv16; -- attn pattern
end record rlink_tba_stat_type;
constant rlink_tba_stat_init : rlink_tba_stat_type := (
'0','0','0', -- busy, ack, err
(others=>'0'), -- stat
(others=>'0'), -- braddr
'0', -- bre
(others=>'0'), -- bwaddr
'0', -- bwe
(others=>'0'), -- dcnt
'0','0', -- apend, ano
(others=>'0') -- apat
);
component rlink_tba is -- rlink test bench adapter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CNTL : in rlink_tba_cntl_type; -- control port
DI : in slv16; -- input data
STAT : out rlink_tba_stat_type; -- status port
DO : out slv16; -- output data
RL_DI : out slv9; -- rlink: data in
RL_ENA : out slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv9; -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : out slbit -- rlink: data hold
);
end component;
component rbtba_aif is -- rbus tba, abstract interface
-- no generics, no records
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ_aval : in slbit; -- rbus: request - aval
RB_MREQ_re : in slbit; -- rbus: request - re
RB_MREQ_we : in slbit; -- rbus: request - we
RB_MREQ_initt : in slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : in slv16; -- rbus: request - addr
RB_MREQ_din : in slv16; -- rbus: request - din
RB_SRES_ack : out slbit; -- rbus: response - ack
RB_SRES_busy : out slbit; -- rbus: response - busy
RB_SRES_err : out slbit; -- rbus: response - err
RB_SRES_dout : out slv16; -- rbus: response - dout
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv4 -- rbus: status flags
);
end component;
-- FIXME after this point !!
component rricp_rp is -- rri comm->reg port aif forwarder
-- implements rricp_aif, uses rrirp_aif
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit :='0'; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit := '0' -- rlink: data hold
);
end component;
end package rlinktblib;
|
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity alu is
port(
a, b: in std_logic_vector(31 downto 0);
alucontrol: in std_logic_vector(2 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic
);
end entity;
architecture behavior of alu is
begin
process(a,b,alucontrol)
variable temp: std_logic_vector(31 downto 0);
begin
case alucontrol is
when "000" =>
temp := a and b;
when "001" =>
temp := a or b;
when "010" =>
temp := a + b;
when "011" =>
temp := x"00000000"; --preguntar
when "100" =>
temp := a and not(b);
when "101" =>
temp := a or not(b);
when "110" =>
temp := a - b;
when "111" =>
if (a < b) then
temp := (others => '1');
elsif (a > b) then
temp := (others => '0');
end if;
when others =>
temp := x"00000000";
end case;
if (temp = x"00000000") then
zero <= '1';
else
zero <= '0';
end if;
result <= temp;
end process;
end behavior;
|
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 02/04/2018 01:13:09 PM
-- Module Name: control - Behavioral
-- Description: Control unit for RISCV core
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity control is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- System reset
instruction_ready: in std_logic; -- IM ready
writeback_ack: in std_logic; -- WB ready for input
writeback_request: out std_logic; -- Signal WB results waiting
MMU_load_complete: in std_logic; -- MMU load data is ready to be written back
ALU_halts: out std_logic_vector(4 downto 0); -- Signal ALU pipeline modules to halt
PC_select: out std_logic_vector(4 downto 0); -- Select for PCnext mux
instr_code: in instr_t; -- The current instruction from the decode module
instr: in doubleword; -- The instruction itself for CSR instruction access
RegFile_raddr: out std_logic_vector(4 downto 0);-- For CSR instrs, read address of regfile
RegFile_waddr: out std_logic_vector(4 downto 0);-- For CSR instrs, write back address of regfile
RegFile_rdata: in doubleword; -- For CSR instrs, read data from above address
RegFile_wdata: out doubleword; -- For CSR instrs, write data to above address
CSR_bits: in std_logic_vector(11 downto 0);-- For CSR instrs, address of CSR from spec
rs1: in reg_t;
rs2: in reg_t;
rs3: in reg_t;
rd: in reg_t
);
end control;
architecture Behavioral of control is
-- High-level states of operation (distinct from privilege modes)
type state is (setup, teardown, normal, waiting, exception);
signal curr_state, next_state: state;
-- Control status registers followed by scratch
type CSR_t is array (0 to 64) of doubleword;
signal CSR: CSR_t;
-- If in waiting state, reason determines actions on exit
signal waiting_reason: std_logic_vector(2 downto 0);
-- Handle complicated CSR read behaviors
-- @param CSR_bits - The 12 bit CSR address per the specification
-- @param value - The value to be read back
-- @param mode - What mode we encountered this instruction in
-- Notes: need to pass handle to CSR in because procedures are not allowed to modify signals without an explicit handle
-- TODO add in interrupt setting
-- TODO add in mode checking
-- TODO handle cycle and time readings externally
procedure CSR_read(CSR_bits: in std_logic_vector(11 downto 0); value: out doubleword; CSR: inout CSR_t; mode: in std_logic_vector(1 downto 0)) is
begin
-- TODO add checks for mode
-- TODO handle mode fails and offending instruction logging
case CSR_bits is
when CSR_ADDR_FFLAGS =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_MSTATUS) and x"000000000000001f";
end if;
when CSR_ADDR_FRM =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_MSTATUS) and x"00000000000000e0";
end if;
when CSR_ADDR_FCSR =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_MSTATUS) and x"0000000000006000";
end if;
when CSR_ADDR_CYCLE =>
if( (CSR(CSR_SCOUNTEREN)( 0 ) = '0') and true ) then
-- Error if user mode not allowed to read
-- TODO flip bad instruction exception bit
elsif( (CSR(CSR_MCOUNTEREN)( 0 ) = '0') and true ) then
-- Error if supervisor mode not allowed to read
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_MINSTRET);
end if;
when CSR_ADDR_TIME =>
if( (CSR(CSR_SCOUNTEREN)( 0 ) = '0') and true ) then
-- Error if user mode not allowed to read
-- TODO flip bad instruction exception bit
elsif( (CSR(CSR_MCOUNTEREN)( 0 ) = '0') and true ) then
-- Error if supervisor mode not allowed to read
-- TODO flip bad instruction exception bit
else
-- TODO tie this to external time signal
end if;
when CSR_ADDR_INSTRET =>
if( (CSR(CSR_SCOUNTEREN)( 0 ) = '0') and true ) then
-- Error if user mode not allowed to read
-- TODO flip bad instruction exception bit
elsif( (CSR(CSR_MCOUNTEREN)( 0 ) = '0') and true ) then
-- Error if supervisor mode not allowed to read
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_MINSTRET);
end if;
when CSR_ADDR_HPMCOUNTER3 | CSR_ADDR_HPMCOUNTER4 | CSR_ADDR_HPMCOUNTER5 | CSR_ADDR_HPMCOUNTER6 | CSR_ADDR_HPMCOUNTER7 |
CSR_ADDR_HPMCOUNTER8 | CSR_ADDR_HPMCOUNTER9 | CSR_ADDR_HPMCOUNTER10 | CSR_ADDR_HPMCOUNTER11 | CSR_ADDR_HPMCOUNTER12 |
CSR_ADDR_HPMCOUNTER13| CSR_ADDR_HPMCOUNTER14 | CSR_ADDR_HPMCOUNTER15 | CSR_ADDR_HPMCOUNTER16 | CSR_ADDR_HPMCOUNTER17 |
CSR_ADDR_HPMCOUNTER18| CSR_ADDR_HPMCOUNTER19 | CSR_ADDR_HPMCOUNTER20 | CSR_ADDR_HPMCOUNTER21 | CSR_ADDR_HPMCOUNTER22 |
CSR_ADDR_HPMCOUNTER23| CSR_ADDR_HPMCOUNTER24 | CSR_ADDR_HPMCOUNTER25 | CSR_ADDR_HPMCOUNTER26 | CSR_ADDR_HPMCOUNTER27 |
CSR_ADDR_HPMCOUNTER28| CSR_ADDR_HPMCOUNTER29 | CSR_ADDR_HPMCOUNTER30 | CSR_ADDR_HPMCOUNTER31 =>
-- From notes: *counteren(x) needs to be checked, where x = 1 << integer(address(4 downto 0))
-- Since this is always a single bit, just convert directly to an integer and use it to index the register
-- Example: hpmcounter17 -> x = 1 << 17 = (0100000000000000000)_2. Or, just use bit 17.
if( (CSR(CSR_SCOUNTEREN)( to_integer(unsigned(CSR_BITS(4 downto 0))) ) = '0') and true ) then
-- Error if user mode not allowed to read
-- TODO flip bad instruction exception bit
elsif( (CSR(CSR_MCOUNTEREN)( to_integer(unsigned(CSR_BITS(4 downto 0))) ) = '0') and true ) then
-- Error if supervisor mode not allowed to read
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_MINSTRET);
end if;
when CSR_ADDR_SSTATUS =>
if( CSR(CSR_MSTATUS)( 16 downto 15 ) = "11" or CSR(CSR_MSTATUS)( 14 downto 13 ) = "11") then
value := CSR(CSR_MSTATUS) and x"000000000005e122";
else
value := CSR(CSR_MSTATUS) and x"800000000005e122";
end if;
when CSR_ADDR_SIE =>
value := CSR(CSR_MIE) and CSR(CSR_MIDELEG);
when CSR_ADDR_STVEC =>
value := CSR(CSR_STVEC);
when CSR_ADDR_SCOUNTEREN =>
value := CSR(CSR_SCOUNTEREN);
when CSR_ADDR_SSCRATCH =>
value := CSR(CSR_SSCRATCH);
when CSR_ADDR_SEPC =>
value := CSR(CSR_SEPC);
when CSR_ADDR_SCAUSE =>
value := CSR(CSR_SCAUSE);
when CSR_ADDR_STVAL =>
value := CSR(CSR_STVAL);
when CSR_ADDR_SIP =>
value := CSR(CSR_MIP) and CSR(CSR_MIDELEG);
when CSR_ADDR_SATP =>
if(CSR(CSR_MSTATUS)( 20 ) = '1' and true) then
-- Check that we are in machine mode
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_SATP);
end if;
when CSR_ADDR_MVENDORID =>
value := zero_word & zero_word;
when CSR_ADDR_MARCHID =>
value := zero_word & zero_word;
when CSR_ADDR_MIMPID =>
value := zero_word & zero_word;
when CSR_ADDR_MHARTID =>
value := zero_word & zero_word;
when CSR_ADDR_MSTATUS =>
value := CSR(CSR_MSTATUS);
when CSR_ADDR_MISA =>
value := CSR(CSR_MISA);
when CSR_ADDR_MEDELEG =>
value := CSR(CSR_MEDELEG);
when CSR_ADDR_MIDELEG =>
value := CSR(CSR_MIDELEG);
when CSR_ADDR_MIE =>
value := CSR(CSR_MIE);
when CSR_ADDR_MTVEC =>
value := CSR(CSR_MTVEC);
when CSR_ADDR_MCOUNTEREN =>
value := CSR(CSR_MCOUNTEREN);
when CSR_ADDR_MSCRATCH =>
value := CSR(CSR_MSCRATCH);
when CSR_ADDR_MEPC =>
value := CSR(CSR_MEPC);
when CSR_ADDR_MCAUSE =>
value := CSR(CSR_MCAUSE);
when CSR_ADDR_MTVAL =>
value := CSR(CSR_MTVAL);
when CSR_ADDR_MIP =>
value := CSR(CSR_MIP);
when CSR_ADDR_MHPMCOUNTER3 | CSR_ADDR_MHPMCOUNTER4 | CSR_ADDR_MHPMCOUNTER5 | CSR_ADDR_MHPMCOUNTER6 |
CSR_ADDR_MHPMCOUNTER7 | CSR_ADDR_MHPMCOUNTER8 | CSR_ADDR_MHPMCOUNTER9 | CSR_ADDR_MHPMCOUNTER10 |
CSR_ADDR_MHPMCOUNTER11 | CSR_ADDR_MHPMCOUNTER12 | CSR_ADDR_MHPMCOUNTER13 | CSR_ADDR_MHPMCOUNTER14 |
CSR_ADDR_MHPMCOUNTER15 | CSR_ADDR_MHPMCOUNTER16 | CSR_ADDR_MHPMCOUNTER17 | CSR_ADDR_MHPMCOUNTER18 |
CSR_ADDR_MHPMCOUNTER19 | CSR_ADDR_MHPMCOUNTER20 | CSR_ADDR_MHPMCOUNTER21 | CSR_ADDR_MHPMCOUNTER22 |
CSR_ADDR_MHPMCOUNTER23 | CSR_ADDR_MHPMCOUNTER24 | CSR_ADDR_MHPMCOUNTER25 | CSR_ADDR_MHPMCOUNTER26 |
CSR_ADDR_MHPMCOUNTER27 | CSR_ADDR_MHPMCOUNTER28 | CSR_ADDR_MHPMCOUNTER29 | CSR_ADDR_MHPMCOUNTER30 |
CSR_ADDR_MHPMCOUNTER31 =>
value := zero_word & zero_word;
when CSR_ADDR_MHPMEVENT3 | CSR_ADDR_MHPMEVENT4 | CSR_ADDR_MHPMEVENT5 | CSR_ADDR_MHPMEVENT6 |
CSR_ADDR_MHPMEVENT7 | CSR_ADDR_MHPMEVENT8 | CSR_ADDR_MHPMEVENT9 | CSR_ADDR_MHPMEVENT10 |
CSR_ADDR_MHPMEVENT11 | CSR_ADDR_MHPMEVENT12 | CSR_ADDR_MHPMEVENT13 | CSR_ADDR_MHPMEVENT14 |
CSR_ADDR_MHPMEVENT15 | CSR_ADDR_MHPMEVENT16 | CSR_ADDR_MHPMEVENT17 | CSR_ADDR_MHPMEVENT18 |
CSR_ADDR_MHPMEVENT19 | CSR_ADDR_MHPMEVENT20 | CSR_ADDR_MHPMEVENT21 | CSR_ADDR_MHPMEVENT22 |
CSR_ADDR_MHPMEVENT23 | CSR_ADDR_MHPMEVENT24 | CSR_ADDR_MHPMEVENT25 | CSR_ADDR_MHPMEVENT26 |
CSR_ADDR_MHPMEVENT27 | CSR_ADDR_MHPMEVENT28 | CSR_ADDR_MHPMEVENT29 | CSR_ADDR_MHPMEVENT30 |
CSR_ADDR_MHPMEVENT31 =>
value := zero_word & zero_word;
when others =>
-- All others not implemented, set trap
-- TODO set bad instruction exception
end case;
end; -- CSR_read procedure
-- Handle complicated CSR write behaviors
-- @param CSR_bits - The 12 bit CSR address per the specification
-- @param value - The write value
-- @param mode - What mode we encountered this instruction in
-- Notes: need to pass handle to CSR in because procedures are not allowed to modify signals without an explicit handle
-- TODO handle cycle and time readings externally
procedure CSR_write(CSR_bits: in std_logic_vector(11 downto 0); value: in doubleword; CSR: inout CSR_t; mode: in std_logic_vector(1 downto 0)) is
begin
-- TODO add checks for mode
-- TODO handle mode fails and offending instruction logging
case CSR_bits is
when CSR_ADDR_FFLAGS =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
-- TODO flip bad instruction exception bit
else
CSR(CSR_MSTATUS)(14 downto 13) := "11"; -- Set FP dirty bits
CSR(CSR_MSTATUS)( 63 ) := '1'; -- Set flag indicating dirty bits
CSR(CSR_FCSR)(4 downto 0) := value(4 downto 0); -- Set FP flags passed in
end if;
when CSR_ADDR_FRM =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
-- TODO flip bad instruction exception bit
else
CSR(CSR_MSTATUS)(14 downto 13) := "11"; -- Set FP dirty bits
CSR(CSR_MSTATUS)( 63 ) := '1'; -- Set flag indicating dirty bits
CSR(CSR_FCSR)(7 downto 5) := value(2 downto 0); -- Set FP rounging mode passed in
end if;
when CSR_ADDR_FCSR =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
-- TODO flip bad instruction exception bit
else
CSR(CSR_MSTATUS)(14 downto 13) := "11"; -- Set FP dirty bits
CSR(CSR_MSTATUS)( 63 ) := '1'; -- Set flag indicating dirty bits
CSR(CSR_FCSR)(7 downto 0) := value(7 downto 0); -- Set FP rounging mode and flags passed in
end if;
when CSR_ADDR_SSTATUS =>
CSR(CSR_MSTATUS)( 18 ) := value(18); -- Update Smode portion of MSTATUS
CSR(CSR_MSTATUS)( 16 downto 15 ) := value(16 downto 15);
CSR(CSR_MSTATUS)( 14 downto 13 ) := value(14 downto 13);
CSR(CSR_MSTATUS)( 8 ) := value(8);
CSR(CSR_MSTATUS)( 5 ) := value(5);
CSR(CSR_MSTATUS)( 1 ) := value(1);
when CSR_ADDR_SIE => -- Update Smode interrupts to and of MIE and delegations
CSR(CSR_MIE)( 12 ) := value(12) and CSR(CSR_MIDELEG)( 12 );
CSR(CSR_MIE)( 9 ) := value(9) and CSR(CSR_MIDELEG)( 9 );
CSR(CSR_MIE)( 7 ) := value(7) and CSR(CSR_MIDELEG)( 7 );
CSR(CSR_MIE)( 5 ) := value(5) and CSR(CSR_MIDELEG)( 5 );
CSR(CSR_MIE)( 3 ) := value(3) and CSR(CSR_MIDELEG)( 3 );
CSR(CSR_MIE)( 1 ) := value(1) and CSR(CSR_MIDELEG)( 1 );
when CSR_ADDR_STVEC => -- update STVec to the shifted address in 63:2
CSR(CSR_STVEC)(63 downto 2) := value(63 downto 2);
when CSR_ADDR_SCOUNTEREN =>
CSR( CSR_SCOUNTEREN ) := value; -- Pass through new enbale value
when CSR_ADDR_SSCRATCH =>
CSR( CSR_SSCRATCH ) := value; -- Pass through new scratch value
when CSR_ADDR_SEPC =>
CSR( CSR_SEPC ) := value; -- Pass through new scratch value
when CSR_ADDR_SCAUSE =>
CSR( CSR_SCAUSE ) := value; -- Pass through new scratch value
when CSR_ADDR_STVAL =>
CSR( CSR_STVAL ) := value; -- Pass through new scratch value
when CSR_ADDR_SIP =>
CSR(CSR_MIP)( 1 ) := value(1) and CSR(CSR_MIDELEG)( 1 ); -- Pass through new scratch value
when CSR_ADDR_SATP =>
if(CSR(CSR_MSTATUS)(20) = '1') then
-- TODO set bad instruction exception
elsif( (value(63 downto 60) = "0000") or
(value(63 downto 60) = "1000") or
(value(63 downto 60) = "1001") ) then
-- This won't actually do anything, since we aren't implementing address translations for Smode
CSR(CSR_SATP)(63 downto 60) := value(63 downto 60);
CSR(CSR_SATP)(43 downto 0) := value(43 downto 0);
end if;
when CSR_ADDR_MSTATUS =>
-- update status
if(value(14 downto 13) = "00") then -- if not dirty
CSR(CSR_MSTATUS)(22 downto 17) := value(22 downto 17);
CSR(CSR_MSTATUS)(14 downto 11) := value(14 downto 11);
CSR(CSR_MSTATUS)( 8 ) := value(8);
CSR(CSR_MSTATUS)( 7 ) := value(7);
CSR(CSR_MSTATUS)( 5 ) := value(5);
CSR(CSR_MSTATUS)( 3 ) := value(3);
CSR(CSR_MSTATUS)( 1 ) := value(1);
CSR(CSR_MSTATUS)( 63 ) := '0';
else
CSR(CSR_MSTATUS)(22 downto 17) := value(22 downto 17);
CSR(CSR_MSTATUS)(14 downto 11) := value(14 downto 11);
CSR(CSR_MSTATUS)( 8 ) := value(8);
CSR(CSR_MSTATUS)( 7 ) := value(7);
CSR(CSR_MSTATUS)( 5 ) := value(5);
CSR(CSR_MSTATUS)( 3 ) := value(3);
CSR(CSR_MSTATUS)( 1 ) := value(1);
CSR(CSR_MSTATUS)( 63 ) := '1';
end if;
when CSR_ADDR_MISA => -- Do nothing
when CSR_ADDR_MEDELEG => -- Update delegation of synchronous exceptions
CSR( CSR_MEDELEG ) := value;
when CSR_ADDR_MIDELEG => -- Update delegation of aynschronous exceptions
CSR(CSR_MIDELEG)( 12 ) := value(12);
CSR(CSR_MIDELEG)( 9 ) := value(9);
CSR(CSR_MIDELEG)( 5 ) := value(5);
CSR(CSR_MIDELEG)( 1 ) := value(1);
when CSR_ADDR_MIE => -- Update enabled exceptions
CSR(CSR_MIE)( 12 ) := value(12);
CSR(CSR_MIE)( 9 ) := value(9);
CSR(CSR_MIE)( 7 ) := value(7);
CSR(CSR_MIE)( 5 ) := value(5);
CSR(CSR_MIE)( 3 ) := value(3);
CSR(CSR_MIE)( 1 ) := value(1);
when CSR_ADDR_MTVEC => -- Update shifted base address for machine mode trap handler
-- Note: bit 1 is reserved because reasons
CSR(CSR_MTVEC)(63 downto 2) := value(63 downto 2);
CSR(CSR_MTVEC)( 0 ) := value(0);
when CSR_ADDR_MCOUNTEREN => -- Pass through new counter enable bit
CSR( CSR_MCOUNTEREN ) := value;
when CSR_ADDR_MSCRATCH => -- Pass through new scratch value
CSR( CSR_MSCRATCH ) := value;
when CSR_ADDR_MEPC => -- Pass through new exception PC
CSR( CSR_MEPC ) := value;
when CSR_ADDR_MCAUSE => -- Pass through new exception cause
CSR( CSR_MCAUSE ) := value;
when CSR_ADDR_MTVAL => -- Pass through address of the bad address for relevant interrupts (store/load misaligned, page fault)
CSR( CSR_MTVAL ) := value;
when CSR_ADDR_MIP => -- Allow Smode timer and software interrupts to be signalled
CSR(CSR_MIP)( 5 ) := value(5);
CSR(CSR_MIP)( 1 ) := value(1);
when CSR_ADDR_MHPMCOUNTER3 => -- Ignore writes
when CSR_ADDR_MHPMCOUNTER4 =>
when CSR_ADDR_MHPMCOUNTER5 =>
when CSR_ADDR_MHPMCOUNTER6 =>
when CSR_ADDR_MHPMCOUNTER7 =>
when CSR_ADDR_MHPMCOUNTER8 =>
when CSR_ADDR_MHPMCOUNTER9 =>
when CSR_ADDR_MHPMCOUNTER10 =>
when CSR_ADDR_MHPMCOUNTER11 =>
when CSR_ADDR_MHPMCOUNTER12 =>
when CSR_ADDR_MHPMCOUNTER13 =>
when CSR_ADDR_MHPMCOUNTER14 =>
when CSR_ADDR_MHPMCOUNTER15 =>
when CSR_ADDR_MHPMCOUNTER16 =>
when CSR_ADDR_MHPMCOUNTER17 =>
when CSR_ADDR_MHPMCOUNTER18 =>
when CSR_ADDR_MHPMCOUNTER19 =>
when CSR_ADDR_MHPMCOUNTER20 =>
when CSR_ADDR_MHPMCOUNTER21 =>
when CSR_ADDR_MHPMCOUNTER22 =>
when CSR_ADDR_MHPMCOUNTER23 =>
when CSR_ADDR_MHPMCOUNTER24 =>
when CSR_ADDR_MHPMCOUNTER25 =>
when CSR_ADDR_MHPMCOUNTER26 =>
when CSR_ADDR_MHPMCOUNTER27 =>
when CSR_ADDR_MHPMCOUNTER28 =>
when CSR_ADDR_MHPMCOUNTER29 =>
when CSR_ADDR_MHPMCOUNTER30 =>
when CSR_ADDR_MHPMCOUNTER31 =>
when CSR_ADDR_MHPMEVENT3 =>
when CSR_ADDR_MHPMEVENT4 =>
when CSR_ADDR_MHPMEVENT5 =>
when CSR_ADDR_MHPMEVENT6 =>
when CSR_ADDR_MHPMEVENT7 =>
when CSR_ADDR_MHPMEVENT8 =>
when CSR_ADDR_MHPMEVENT9 =>
when CSR_ADDR_MHPMEVENT10 =>
when CSR_ADDR_MHPMEVENT11 =>
when CSR_ADDR_MHPMEVENT12 =>
when CSR_ADDR_MHPMEVENT13 =>
when CSR_ADDR_MHPMEVENT14 =>
when CSR_ADDR_MHPMEVENT15 =>
when CSR_ADDR_MHPMEVENT16 =>
when CSR_ADDR_MHPMEVENT17 =>
when CSR_ADDR_MHPMEVENT18 =>
when CSR_ADDR_MHPMEVENT19 =>
when CSR_ADDR_MHPMEVENT20 =>
when CSR_ADDR_MHPMEVENT21 =>
when CSR_ADDR_MHPMEVENT22 =>
when CSR_ADDR_MHPMEVENT23 =>
when CSR_ADDR_MHPMEVENT24 =>
when CSR_ADDR_MHPMEVENT25 =>
when CSR_ADDR_MHPMEVENT26 =>
when CSR_ADDR_MHPMEVENT27 =>
when CSR_ADDR_MHPMEVENT28 =>
when CSR_ADDR_MHPMEVENT29 =>
when CSR_ADDR_MHPMEVENT30 =>
when CSR_ADDR_MHPMEVENT31 =>
when others =>
-- All others not implemented, set trap
-- TODO set bad isntruction exception
end case;
end; -- CSR_write procedure
begin
-- Advance state
update_state: process(clk,rst)
begin
if(rising_edge(clk)) then
if('1' = rst) then
curr_state <= setup;
else
curr_state <= next_state;
end if;
end if;
end process;
-- Compute outputs
update_signals: process(curr_state)
-- CSR temporary
variable tempVal: doubleword;
variable CSRVal: doubleword;
variable CSR_bits: std_logic_vector(11 downto 0) := instr(31 downto 20);
begin
-- default outputs
next_state <= curr_state;
-- adjust next state and outputs
case curr_state is
when setup => -- Bootloader code
-- Reset CSR
-- CSR <= (others => (zero_word & zero_word));
when teardown => -- Maybe superflous
when waiting =>
case waiting_reason is
when "000" => -- Waiting on MMU instruction
if('1' = instruction_ready) then
-- Resume normal mode
next_state <= normal;
end if;
when "001" => -- Waiting on MMU to clear WB (store instructions)
if('1' = writeback_ack) then
next_state <= normal;
end if;
when "010" => -- Waiting on mulhsu (one cycle)
-- always go back to normal, stalled one cycle
next_state <= normal;
when "011" => -- Waiting on MMU load data
if('1' = MMU_load_complete) then
next_state <= normal;
end if;
when others => -- Waiting for interrupt (special state when no work exists)
end case;
when exception => -- Interrupt to take
-- Determine which of supervisor/machine interrupt vector to use
-- Switch in exception address and perform jump
-- return to normal mode to execute handler instructions
next_state <= normal;
when others => -- Normal operation
-- Determine the appropriate pipeline for the active instruction
case instr_code is
-- Handle privileged instructions here
when instr_FENCE =>
-- NOT IMPLEMENTED - fence memory and I/O
when instr_FENCEI =>
-- NOT IMPLEMENTED - fence instruction stream
when instr_ECALL =>
-- Raise environment call exception
-- TODO implement me
when instr_EBREAK =>
-- NOT IMPLEMENTED - raise breakpoint exception
when instr_CSRRW =>
-- CSR read and then write
-- Write the value of the CSR to x[rd], then set the CSR to x[rs1]
RegFile_raddr <= x"0"; -- rs1 address
tempVal := RegFile_rdata;
CSRVal := CSR(to_integer(unsigned(CSR_bits)));
RegFile_waddr <= x"0";
RegFile_wdata <= CSR_read(to_integer(unsigned(CSR_bits)), CSRVal);
when instr_CSRRS =>
-- CSR read and set
-- Write the value fo the CSR to x[rd], then overwrite the CSR to the OR of the CSR value and the value of x[rs1]
-- TODO implement me
when instr_CSRRC =>
-- CSR read and clear
-- Write the value of the CSR to x[rd], get the contents of x[rs1], flip all its bits, and overwrite the CSR with the AND of its contents and the result.
-- Less insane explanation: CSR = CSR & ~x[rs1], The bits set in x[rs1] are the bits to clear in the CSR contents.
-- TODO implement me
when instr_CSRRWI =>
-- CSR read and then write immediate
-- Write the value of the CSR to x[rd], then set the CSR to the zero-extended immediate value.
-- TODO implement me
when instr_CSRRSI =>
-- CSR read and set immediate
-- Write the value of the CSR to x[rd], then overwrite the CSR to the OR of the CSR value and the (zero-extended) immediate value
-- TODO implement me
when instr_CSRRCI =>
-- CSR Read and clear immediate
-- Write the value of the CSR to x[rd], zero extend the immediate value, flip all its bits, and overwrite the CSR with the AND of its contents and the result.
-- Less insane explanation: The immediate value represents which of the 5 LSBs of the CSR should be set to zero. So zimm = "00100" means clear bit 2.
-- TODO implement me
when others =>
end case;
next_state <= normal;
end case;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SeqDetFSM_Tb is
end SeqDetFSM_Tb;
architecture Stimulus of SeqDetFSM_Tb is
signal s_clk : std_logic;
signal s_xin, s_yout : std_logic;
begin
uut: entity work.SeqDetFSM(MealyArch)
port map(clk => s_clk,
xin => s_xin,
yout=> s_yout);
clk_proc: process
begin
s_clk <= '1';
wait for 25 ns;
s_clk <= '0';
wait for 25 ns;
end process;
stim_proc: process
begin
s_xin <= '1';
wait for 35 ns;
s_xin <= '0';
wait for 20 ns;
s_xin <= '1';
wait for 20 ns;
s_xin <= '0';
wait for 20 ns;
s_xin <= '1';
wait for 20 ns;
s_xin <= '1';
wait for 20 ns;
s_xin <= '1';
wait for 20 ns;
end process;
end Stimulus; |
entity attr14 is
end entity;
architecture test of attr14 is
type rec is record
x : bit_vector(7 downto 0);
end record;
signal s : rec;
signal t : bit_vector(3 downto 0);
begin
p1: process is
begin
wait for 1 ns;
s.x(4) <= '1';
wait for 1 ns;
s.x(4) <= '1';
wait;
end process;
p2: process is
begin
wait on s.x;
assert now = 1 ns;
assert s.x'event;
assert s.x'last_event = 0 ns;
assert s.x'last_active = 0 ns;
assert s.x(4) = '1';
wait on s.x;
assert s.x'active;
assert not s.x'event;
assert s.x'last_event = 1 ns;
assert s.x'last_active = 0 ns;
assert s.x(4) = '1';
wait;
end process;
end architecture;
|
--
-- Inferrable Synchronous SRAM for XST synthesis
--
-- Version : 0220
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
-- 0208 : Initial release
-- 0218 : Fixed data out at write
-- 0220 : Added support for XST
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SSRAM is
generic(
AddrWidth : integer := 11;
DataWidth : integer := 8
);
port(
Clk : in std_logic;
CE_n : in std_logic;
WE_n : in std_logic;
A : in std_logic_vector(AddrWidth - 1 downto 0);
DIn : in std_logic_vector(DataWidth - 1 downto 0);
DOut : out std_logic_vector(DataWidth - 1 downto 0)
);
end SSRAM;
architecture behaviour of SSRAM is
type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if (CE_n nor WE_n) = '1' then
RAM(to_integer(unsigned(A))) <= DIn;
end if;
A_r <= A;
end if;
end process;
DOut <= RAM(to_integer(unsigned(A_r)))
-- pragma translate_off
when not is_x(A_r) else (others => '-')
-- pragma translate_on
;
end;
|
--
-- Inferrable Synchronous SRAM for XST synthesis
--
-- Version : 0220
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
-- 0208 : Initial release
-- 0218 : Fixed data out at write
-- 0220 : Added support for XST
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SSRAM is
generic(
AddrWidth : integer := 11;
DataWidth : integer := 8
);
port(
Clk : in std_logic;
CE_n : in std_logic;
WE_n : in std_logic;
A : in std_logic_vector(AddrWidth - 1 downto 0);
DIn : in std_logic_vector(DataWidth - 1 downto 0);
DOut : out std_logic_vector(DataWidth - 1 downto 0)
);
end SSRAM;
architecture behaviour of SSRAM is
type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if (CE_n nor WE_n) = '1' then
RAM(to_integer(unsigned(A))) <= DIn;
end if;
A_r <= A;
end if;
end process;
DOut <= RAM(to_integer(unsigned(A_r)))
-- pragma translate_off
when not is_x(A_r) else (others => '-')
-- pragma translate_on
;
end;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00444
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.4 (2)
-- 7.2.4 (11)
-- 7.2.4 (12)
-- 7.2.4 (13)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00444(ARCH00444)
-- ENT00444_Test_Bench(ARCH00444_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.ARITHMETIC.ALL ;
entity ENT00444 is
generic (
i_real_1 : real := c_real_1 ;
i_real_2 : real := c_real_2 ;
i_t_real_1 : t_real := c_t_real_1 ;
i_t_real_2 : t_real := c_t_real_2 ;
i_st_real_1 : st_real := c_st_real_1 ;
i_st_real_2 : st_real := c_st_real_2
) ;
port ( locally_static_correct : out boolean ;
globally_static_correct : out boolean ;
dynamic_correct : out boolean ) ;
end ENT00444 ;
architecture ARCH00444 of ENT00444 is
constant c2_real_1 : real :=
10.4 * i_real_1 + i_real_1 * i_real_2 + i_real_1 * i_real_1 -
i_real_2 * c_real_2 ;
constant c2_t_real_1 : t_real :=
(1.0) * 500.2 + (i_t_real_1 / 2.0) * i_t_real_2 + i_t_real_1 * 2.0 -
i_t_real_2 * i_t_real_2 ;
constant c2_st_real_1 : st_real :=
(-0.0) * i_st_real_2 + i_st_real_1 * (i_t_real_1 / 10.8) +
(i_t_real_2 * i_st_real_1) - (i_st_real_2 / 10.7) * i_t_real_2 ;
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_real_1, v2_real_1 : real := i_real_1 ;
variable v_real_2, v2_real_2 : real := i_real_2 ;
variable v_t_real_1, v2_t_real_1 : t_real := i_t_real_1 ;
variable v_t_real_2, v2_t_real_2 : t_real := i_t_real_2 ;
variable v_st_real_1, v2_st_real_1 : st_real := i_st_real_1 ;
variable v_st_real_2, v2_st_real_2 : st_real := i_st_real_2 ;
--
begin
-- static expression
case bool is
when (
abs (
10.4 * c_real_1 + c_real_1 * c_real_2 + c_real_1 * c_real_1 -
c_real_2 * c_real_2
- 89.51) < acceptable_error and
abs (
(1.0) * 500.2 + (c_t_real_1 / 2.0) * c_t_real_2 + c_t_real_1 * 2.0 -
c_t_real_2 * c_t_real_2
- 612.95) < t_acceptable_error and
abs (
(-0.0) * c_st_real_2 + c_st_real_1 * (c_t_real_1 / 10.8) +
(c_t_real_2 * c_st_real_1) - (c_st_real_2 / 10.7) * c_t_real_2
- 121.6243 ) < t_acceptable_error
) =>
null ;
when others =>
cons_correct := false ;
end case ;
-- generic expression
gen_correct := abs (c2_real_1 - 89.51) < acceptable_error and
abs (c2_t_real_1 - 612.95) < t_acceptable_error and
abs (c2_st_real_1 - 121.6243) < t_acceptable_error ;
-- dynamic expression
v2_real_1 :=
10.4 * v_real_1 + v_real_1 * v_real_2 + v_real_1 * v_real_1 -
v_real_2 * c_real_2 ;
v2_t_real_1 :=
(1.0) * 500.2 + (v_t_real_1 / 2.0) * v_t_real_2 + v_t_real_1 * 2.0 -
v_t_real_2 * v_t_real_2 ;
v2_st_real_1 :=
(-0.0) * v_st_real_2 + v_st_real_1 * (v_t_real_1 / 10.8) +
(v_t_real_2 * v_st_real_1) - (v_st_real_2 / 10.7) * v_t_real_2 ;
dyn_correct := abs (v2_real_1 - 89.51) < acceptable_error and
abs (v2_t_real_1 - 612.95) < t_acceptable_error and
abs (v2_st_real_1 - 121.6243) < t_acceptable_error ;
locally_static_correct <= cons_correct ;
globally_static_correct <= gen_correct ;
dynamic_correct <= dyn_correct ;
wait ;
end process ;
end ARCH00444 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00444_Test_Bench is
end ENT00444_Test_Bench ;
architecture ARCH00444_Test_Bench of ENT00444_Test_Bench is
begin
L1:
block
signal locally_static_correct, globally_static_correct,
dynamic_correct : boolean := false ;
component UUT
port ( locally_static_correct : out boolean := false ;
globally_static_correct : out boolean := false ;
dynamic_correct : out boolean := false ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00444 ( ARCH00444 ) ;
begin
CIS1 : UUT
port map ( locally_static_correct,
globally_static_correct,
dynamic_correct ) ;
process ( locally_static_correct, globally_static_correct,
dynamic_correct )
begin
if locally_static_correct and globally_static_correct and
dynamic_correct then
test_report ( "ARCH00444" ,
"* predefined for real types" ,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00444_Test_Bench ;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_pkg.ALL;
ENTITY fifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library hdl_library_CommonFunctions;
--use hdl_library_CommonFunctions.CommonFunctions.all;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.MathHelpers.all;
entity ClockGenerator is
generic
(
G_CLOCK_FREQUENCY : integer;
G_CLOCK_DIVIDER : integer
);
port
(
clock : in std_logic;
enable : in std_logic;
clock_output : out std_logic;
clock_output_n : out std_logic
);
end entity; --ClockGenerator
architecture arch of ClockGenerator is
signal i_counter : std_logic_vector(log2(G_CLOCK_DIVIDER) downto 0) := (others => '0');
signal i_clock_output : std_logic := '0';
signal i_index : integer := 0;
begin
PowerOF2: if (isPow2(G_CLOCK_DIVIDER) = true) and (G_CLOCK_FREQUENCY/G_CLOCK_DIVIDER > 1) generate
--i_index <= log2(G_CLOCK_FREQUENCY/G_CLOCK_DIVIDER);
pow2_divider:process(clock)
begin
if rising_edge(clock) then
if enable = '1' then
i_counter <= i_counter + 1;
else
i_clock_output <= '0';
end if;
i_clock_output <= i_counter(log2(G_CLOCK_DIVIDER));
end if;
end process pow2_divider;
end generate PowerOF2;
clock_output <= i_clock_output;
clock_output_n <= not i_clock_output;
NotPowerOF2: if (isPow2(G_CLOCK_DIVIDER) = false) and (G_CLOCK_FREQUENCY/G_CLOCK_DIVIDER > 1) generate
clock_counter:process(clock)
begin
if rising_edge(clock) then
if enable = '1' then
i_counter <= i_counter + 1;
if i_counter = (G_CLOCK_DIVIDER) - 1 then
i_clock_output <= not i_clock_output;
i_counter <= (others => '0');
end if;
else
i_clock_output <= '0';
end if;
end if;
end process clock_counter; -- clock_counter
end generate NotPowerOF2;
end architecture; -- arch |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity somadorSubtrator is
Port ( a0 : in STD_LOGIC;
a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
b0 : in STD_LOGIC;
b1 : in STD_LOGIC;
b2 : in STD_LOGIC;
sel : in STD_LOGIC;
s0 : out STD_LOGIC;
s1 : out STD_LOGIC;
s2 : out STD_LOGIC;
cout : out STD_LOGIC;
E : out STD_LOGIC);
end somadorSubtrator;
architecture Behavioral of somadorSubtrator is
begin
process (a0,a1,a2,b0,b1,b2, sel)
begin
if (sel = '0') then
--soma
s0 <= (a0 xor (b0 xor '0'));
else
--subtrai
end if;
end process;
end Behavioral;
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_port is
end entity alt_dspbuilder_port;
architecture rtl of alt_dspbuilder_port is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_port is
end entity alt_dspbuilder_port;
architecture rtl of alt_dspbuilder_port is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_port is
end entity alt_dspbuilder_port;
architecture rtl of alt_dspbuilder_port is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_port is
end entity alt_dspbuilder_port;
architecture rtl of alt_dspbuilder_port is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_port is
end entity alt_dspbuilder_port;
architecture rtl of alt_dspbuilder_port is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_port is
end entity alt_dspbuilder_port;
architecture rtl of alt_dspbuilder_port is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_port is
end entity alt_dspbuilder_port;
architecture rtl of alt_dspbuilder_port is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_port is
end entity alt_dspbuilder_port;
architecture rtl of alt_dspbuilder_port is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_port is
end entity alt_dspbuilder_port;
architecture rtl of alt_dspbuilder_port is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_port is
end entity alt_dspbuilder_port;
architecture rtl of alt_dspbuilder_port is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
entity repro is
end;
architecture behav of repro
is
procedure test (l : natural) is
variable v : bit_vector (l - 1 downto 0);
begin
assert v (l / 2) = '0';
assert v (0) = '0';
assert v (l - 1) = '0';
end test;
begin
process
begin
test (128 * 1024);
wait;
end process;
end behav;
|
-- $Id: serport_xontx.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_xontx - syn
-- Description: serial port: xon/xoff logic tx path
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 425 1.0 Initial version
-- 2011-10-22 417 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
entity serport_xontx is -- serial port: xon/xoff logic tx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_TXDATA : out slv8; -- uart data in
UART_TXENA : out slbit; -- uart data enable
UART_TXBUSY : in slbit; -- uart data busy
TXDATA : in slv8; -- user data in
TXENA : in slbit; -- user data enable
TXBUSY : out slbit; -- user data busy
RXOK : in slbit; -- rx channel ok
TXOK : in slbit -- tx channel ok
);
end serport_xontx;
architecture syn of serport_xontx is
type regs_type is record
ibuf : slv8; -- input buffer
ival : slbit; -- ibuf has valid data
obuf : slv8; -- output buffer
oval : slbit; -- obuf has valid data
rxok : slbit; -- rx channel ok state
enaxon_1 : slbit; -- last enaxon
escpend : slbit; -- escape pending
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'),'0', -- ibuf,ival
(others=>'0'),'0', -- obuf,oval
'1', -- rxok (startup default is ok !!)
'0', -- enaxon_1
'0' -- escpend
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_TXBUSY,
TXDATA, TXENA, RXOK, TXOK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if TXENA='1' and r.ival='0' then
n.ibuf := TXDATA;
n.ival := '1';
end if;
if r.oval = '0' then
if ENAXON='1' and r.rxok/=RXOK then
n.rxok := RXOK;
n.oval := '1';
if r.rxok = '0' then
n.obuf := c_serport_xon;
else
n.obuf := c_serport_xoff;
end if;
elsif TXOK = '1' then
if r.escpend = '1' then
n.obuf := not r.ibuf;
n.oval := '1';
n.escpend := '0';
n.ival := '0';
elsif r.ival = '1' then
if ENAESC='1' and (r.ibuf=c_serport_xon or
r.ibuf=c_serport_xoff or
r.ibuf=c_serport_xesc)
then
n.obuf := c_serport_xesc;
n.oval := '1';
n.escpend := '1';
else
n.obuf := r.ibuf;
n.oval := '1';
n.ival := '0';
end if;
end if;
end if;
end if;
if r.oval='1' and UART_TXBUSY='0' then
n.oval := '0';
end if;
-- FIXME: document this hack
n.enaxon_1 := ENAXON;
if ENAXON='1' and r.enaxon_1='0' then
n.rxok := not RXOK;
end if;
N_REGS <= n;
TXBUSY <= r.ival;
UART_TXDATA <= r.obuf;
UART_TXENA <= r.oval;
end process proc_next;
end syn;
|
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Contains a testbench for the generic UART entity.
--
-- To Do:
-- -
--
-- Author(s):
-- - Magnus Rosenius, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TestUart.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for TestUart.
-------------------------------------------------------------------------------
entity TestUart is
end entity;
-------------------------------------------------------------------------------
-- Architecture for TestUart.
-------------------------------------------------------------------------------
architecture TestUartImpl of TestUart is
component Uart is
generic(
DIVISOR_WIDTH : natural;
DATA_WIDTH : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
divisor_i : in std_logic_vector(DIVISOR_WIDTH-1 downto 0);
serial_i : in std_logic;
serial_o : out std_logic;
empty_o : out std_logic;
read_i : in std_logic;
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
full_o : out std_logic;
write_i : in std_logic;
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal clk : std_logic;
signal areset_n : std_logic;
signal rxSerial : std_logic;
signal txSerial : std_logic;
signal rxEmpty : std_logic;
signal rxRead : std_logic;
signal rxData : std_logic_vector(7 downto 0);
signal txFull : std_logic;
signal txWrite : std_logic;
signal txData : std_logic_vector(7 downto 0);
begin
-----------------------------------------------------------------------------
-- Clock generation.
-----------------------------------------------------------------------------
ClockGenerator: process
begin
clk <= '0';
wait for 20 ns;
clk <= '1';
wait for 20 ns;
end process;
-----------------------------------------------------------------------------
-- Serial port emulator.
-----------------------------------------------------------------------------
TestDriver: process
procedure SerialSend(
constant data : in std_logic_vector(7 downto 0)) is
variable outgoing : std_logic_vector(9 downto 0);
begin
-- Create the complete transmission character.
outgoing(0) := '0';
for i in 0 to 7 loop
outgoing(i+1) := data(i);
end loop;
outgoing(9) := '1';
-- Send the character.
for i in 0 to 9 loop
txSerial <= outgoing(i);
wait for 500 ns;
end loop;
end procedure;
procedure SerialReceive(
constant data : in std_logic_vector(7 downto 0)) is
variable incomming : std_logic_vector(9 downto 0);
begin
-- Receive the character.
wait until rxSerial = '0';
incomming(0) := '0';
for i in 1 to 9 loop
wait for 500 ns;
incomming(i) := rxSerial;
end loop;
-- Check if the received character is expected.
assert (incomming(0) = '0') report "Start bit." severity error;
assert (incomming(8 downto 1) = data) report "Data bit" severity error;
assert (incomming(9) = '1') report "Stop bit." severity error;
end procedure;
begin
txSerial <= '1';
txWrite <= '0';
rxRead <= '0';
areset_n <= '0';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
areset_n <= '1';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
---------------------------------------------------------------------------
-- Send byte to uart.
---------------------------------------------------------------------------
SerialSend(x"55");
wait until rxEmpty = '0' and clk'event and clk = '1';
rxRead <= '1';
wait until clk'event and clk = '1';
rxRead <= '0';
wait until clk'event and clk = '1';
assert rxData = x"55" report "rxData" severity error;
SerialSend(x"62");
wait until rxEmpty = '0' and clk'event and clk = '1';
rxRead <= '1';
wait until clk'event and clk = '1';
rxRead <= '0';
wait until clk'event and clk = '1';
assert rxData = x"62" report "rxData" severity error;
wait until txFull = '0' and clk'event and clk = '1';
txWrite <= '1';
txData <= x"55";
wait until clk'event and clk = '1';
txWrite <= '0';
SerialReceive(x"55");
wait until txFull = '0' and clk'event and clk = '1';
txWrite <= '1';
txData <= x"62";
wait until clk'event and clk = '1';
txWrite <= '0';
SerialReceive(x"62");
-- REMARK: Formalize the tests and write more testcases...
---------------------------------------------------------------------------
-- Test completed.
---------------------------------------------------------------------------
TestEnd;
end process;
-----------------------------------------------------------------------------
-- Instantiate the uart.
-----------------------------------------------------------------------------
UartInst: Uart
generic map(DIVISOR_WIDTH=>4, DATA_WIDTH=>8)
port map(
clk=>clk, areset_n=>areset_n,
divisor_i=>"1011",
serial_i=>txSerial, serial_o=>rxSerial,
empty_o=>rxEmpty, read_i=>rxRead, data_o=>rxData,
full_o=>txFull, write_i=>txWrite, data_i=>txData);
end architecture;
|
---------------------------------------------------------------------
-- TITLE: Memory Controller
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mem_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Memory controller for the Plasma CPU.
-- Supports Big or Little Endian mode.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity mem_ctrl is
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
mem_address : out std_logic_vector(31 downto 2);
mem_data_w : out std_logic_vector(31 downto 0);
mem_data_r : in std_logic_vector(31 downto 0);
mem_byte_we : out std_logic_vector(3 downto 0));
end; --entity mem_ctrl
architecture logic of mem_ctrl is
--"00" = big_endian; "11" = little_endian
constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "11";
signal opcode_reg : std_logic_vector(31 downto 0);
signal next_opcode_reg : std_logic_vector(31 downto 0);
signal mem_state_reg : std_logic;
constant STATE_ADDR : std_logic := '0';
constant STATE_ACCESS : std_logic := '1';
begin
mem_proc: process(clk, reset_in, pause_in, nullify_op,
address_pc, address_in, mem_source, data_write,
mem_data_r, opcode_reg, next_opcode_reg, mem_state_reg)
variable address_var : std_logic_vector(31 downto 2);
variable data_read_var : std_logic_vector(31 downto 0);
variable data_write_var : std_logic_vector(31 downto 0);
variable opcode_next : std_logic_vector(31 downto 0);
variable byte_sel_var : std_logic_vector(3 downto 0);
variable mem_state_next : std_logic;
variable pause_var : std_logic;
variable bits : std_logic_vector(1 downto 0);
begin
byte_sel_var := "0000";
pause_var := '0';
data_read_var := ZERO;
data_write_var := ZERO;
mem_state_next := mem_state_reg;
opcode_next := opcode_reg;
case mem_source is
when MEM_READ32 =>
data_read_var := mem_data_r;
when MEM_READ16 | MEM_READ16S =>
if address_in(1) = ENDIAN_MODE(1) then
data_read_var(15 downto 0) := mem_data_r(31 downto 16);
else
data_read_var(15 downto 0) := mem_data_r(15 downto 0);
end if;
if mem_source = MEM_READ16 or data_read_var(15) = '0' then
data_read_var(31 downto 16) := ZERO(31 downto 16);
else
data_read_var(31 downto 16) := ONES(31 downto 16);
end if;
when MEM_READ8 | MEM_READ8S =>
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" => data_read_var(7 downto 0) := mem_data_r(31 downto 24);
when "01" => data_read_var(7 downto 0) := mem_data_r(23 downto 16);
when "10" => data_read_var(7 downto 0) := mem_data_r(15 downto 8);
when others => data_read_var(7 downto 0) := mem_data_r(7 downto 0);
end case;
if mem_source = MEM_READ8 or data_read_var(7) = '0' then
data_read_var(31 downto 8) := ZERO(31 downto 8);
else
data_read_var(31 downto 8) := ONES(31 downto 8);
end if;
when MEM_WRITE32 =>
data_write_var := data_write;
byte_sel_var := "1111";
when MEM_WRITE16 =>
data_write_var := data_write(15 downto 0) & data_write(15 downto 0);
if address_in(1) = ENDIAN_MODE(1) then
byte_sel_var := "1100";
else
byte_sel_var := "0011";
end if;
when MEM_WRITE8 =>
data_write_var := data_write(7 downto 0) & data_write(7 downto 0) &
data_write(7 downto 0) & data_write(7 downto 0);
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" =>
byte_sel_var := "1000";
when "01" =>
byte_sel_var := "0100";
when "10" =>
byte_sel_var := "0010";
when others =>
byte_sel_var := "0001";
end case;
when others =>
end case;
if mem_source = MEM_FETCH then --opcode fetch
address_var := address_pc;
opcode_next := mem_data_r;
mem_state_next := STATE_ADDR;
else
if mem_state_reg = STATE_ADDR then
if pause_in = '0' then
address_var := address_in(31 downto 2);
mem_state_next := STATE_ACCESS;
pause_var := '1';
else
address_var := address_pc;
byte_sel_var := "0000";
end if;
else --STATE_ACCESS
if pause_in = '0' then
address_var := address_pc;
opcode_next := next_opcode_reg;
mem_state_next := STATE_ADDR;
byte_sel_var := "0000";
else
address_var := address_in(31 downto 2);
byte_sel_var := "0000";
end if;
end if;
end if;
if nullify_op = '1' and pause_in = '0' then
opcode_next := ZERO; --NOP after beql
end if;
if reset_in = '1' then
mem_state_reg <= STATE_ADDR;
opcode_reg <= ZERO;
next_opcode_reg <= ZERO;
elsif rising_edge(clk) then
if pause_in = '0' then
mem_state_reg <= mem_state_next;
opcode_reg <= opcode_next;
if mem_state_reg = STATE_ADDR then
next_opcode_reg <= mem_data_r;
end if;
end if;
end if;
mem_address <= address_var;
opcode_out <= opcode_reg;
data_read <= data_read_var;
pause_out <= pause_var;
mem_data_w <= data_write_var;
mem_byte_we <= byte_sel_var;
end process; --data_proc
end; --architecture logic
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hardware_tester_fsm is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0)
);
end hardware_tester_fsm;
architecture Behavioral of hardware_tester_fsm is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component fsm_prac4 PORT (
X : IN STD_LOGIC;
RESET : IN STD_LOGIC;
clk100mhz : IN STD_LOGIC;
Z : OUT STD_LOGIC;
DEBUG_CHECK : OUT STD_LOGIC_VECTOR(3 downto 0);
DEBUG_OUT : OUT STD_LOGIC_VECTOR(3 downto 0));
end component;
signal masterReset : std_logic;
signal button1 : std_logic;
signal button2 : std_logic;
signal submitButton : std_logic;
signal displayKey : std_logic_vector(15 downto 0);
signal digit5 : std_logic_vector(3 downto 0);
signal digit6 : std_logic_vector(3 downto 0);
signal digit7 : std_logic_vector(3 downto 0);
signal digit8 : std_logic_vector(3 downto 0);
signal clockScalers : std_logic_vector (26 downto 0);
signal X,RESET,Z : std_logic;
signal DEBUG_CHECK, DEBUG_OUT : std_logic_vector (3 downto 0) := (others => '0');
subtype counter_bit_int is integer range 0 to 31;
signal shift_pattern : std_logic_vector (15 downto 0) := (others => '0');
--signal counting_vect : std_logic_vector (3 downto 0) := (others => '0');
begin
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayKey (3 downto 0),
digit2_p => displayKey (7 downto 4),
digit3_p => displayKey (11 downto 8),
digit4_p => displayKey (15 downto 12),
digit5_p => digit5,
digit6_p => digit6,
digit7_p => digit7,
digit8_p => digit8
);
u2 : fsm_prac4 port map (X, RESET, clockScalers(11), Z, DEBUG_CHECK, DEBUG_OUT);
masterReset <= pushButtons(3);
submitButton <= pushButtons(2);
button1 <= pushButtons(1);
button2 <= pushButtons(0);
LEDs (15 downto 0) <= clockScalers(26 downto 11);
logic_analyzer(0) <= Z;
--logic_analyzer(1) <= X;
logic_analyzer(2) <= clk100mHz;
logic_analyzer(3) <= clockScalers(11);
logic_analyzer(7 downto 4) <= DEBUG_CHECK;
--RESET <= NOT(masterReset);
RESET <= '1';
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
displayKey <= shift_pattern;
process(masterReset, clockScalers(11), button1) begin
if (masterReset = '1') then
shift_pattern <= (others => '0');
elsif (clockScalers(11)'event and clockScalers(11) = '1') then
if (button1 = '1') then
shift_pattern <= slideSwitches;
end if;
end if;
end process;
process (clockScalers(11))
--variable counter : counter_bit_int := 15;
variable counting_vect : integer := 0;
begin
--wait until submitButton'event and submitButton = '1' ;
if (clockScalers(11)'event and clockScalers(11) = '1') then
if (counting_vect >= 0) then
X <= shift_pattern(counting_vect);
logic_analyzer(1) <= shift_pattern(counting_vect);
counting_vect := counting_vect - 1;
else
counting_vect := 15;
end if;
end if;
end process;
end Behavioral; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library hynix;
use hynix.components.all;
use work.debug.all;
use work.config.all;
library hynix;
use hynix.components.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 37 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk200p : std_logic := '1';
signal clk200n : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- Select signal for SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_mosi : std_logic;
-- Output signals for LEDs
signal led : std_logic_vector(2 downto 0);
signal brdyn : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
rst <= '1', '0' after 100 ns;
dsubre <= '0';
urxd <= 'H';
spi_sel_n <= 'H';
spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => rst,
reset_o1 => rstn1,
reset_o2 => rstn2,
clk27 => clk,
clk200_p => clk200p,
clk200_n => clk200n,
errorn => error,
-- PROM
address => address(23 downto 0),
data => data(31 downto 24),
romsn => romsn,
oen => oen,
writen => writen,
iosn => iosn,
testdata => data(23 downto 0),
-- DDR2
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_we => ddr_we,
ddr_ras => ddr_ras,
ddr_cas => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
ddr_odt => ddr_odt,
ddr_rzq => ddr_rzq,
ddr_zio => ddr_zio,
-- Debug Unit
dsubre => dsubre,
-- AHB Uart
dsutx => dsutx,
dsurx => dsurx,
-- PHY
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxdt(7 downto 0),
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxdt(7 downto 0),
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc,
emdio => emdio,
-- SPI flash select
-- spi_sel_n => spi_sel_n,
-- spi_clk => spi_clk,
-- spi_mosi => spi_mosi,
-- Output signals for LEDs
led => led
);
migddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr2mem0 : for i in 0 to 0 generate
u1 : HY5PS121621F
generic map (TimingCheckFlag => true, PUSCheckFlag => false,
index => i, bbits => 16, fname => sdramfile,
fdelay => 150)
port map (DQ => ddr_dq(i*16+15 downto i*16),
LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2),
UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1),
LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas,
RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba(1 downto 0),
ADDR => ddr_ad(12 downto 0), CKE => ddr_cke,
CLK => ddr_clk, CLKB => ddr_clkb, UDM => ddr_dm(i*2+1));
end generate;
end generate;
ddr2mem : if (CFG_DDR2SP /= 0) generate
ddr2mem0 : for i in 0 to 0 generate
u1 : HY5PS121621F
generic map (TimingCheckFlag => true, PUSCheckFlag => false,
index => i, bbits => 16, fname => sdramfile)
port map (DQ => ddr_dq2(i*16+15 downto i*16),
LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2),
UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1),
LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas,
RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba(1 downto 0),
ADDR => ddr_ad(12 downto 0), CKE => ddr_cke,
CLK => ddr_clk, CLKB => ddr_clkb, UDM => ddr_dm(i*2+1));
end generate;
ddr2delay0 : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 10.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
prom0 : sram
generic map (index => 6, abits => 24, fname => promfile)
port map (address(23 downto 0), data(31 downto 24), romsn, writen, oen);
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (address => 1)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, '0');
end generate;
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0) -- Dual output is not supported in this design
port map (spi_clk, spi_mosi, data(24), spi_sel_n);
end generate spimem0;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data, iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.7
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : gtpa1_dual_wrapper.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module GTPA1_DUAL_WRAPPER (a GTP Wrapper)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity GTPA1_DUAL_WRAPPER is
generic
(
-- Simulation attributes
WRAPPER_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
WRAPPER_CLK25_DIVIDER_0 : integer := 4;
WRAPPER_CLK25_DIVIDER_1 : integer := 4;
WRAPPER_PLL_DIVSEL_FB_0 : integer := 5;
WRAPPER_PLL_DIVSEL_FB_1 : integer := 5;
WRAPPER_PLL_DIVSEL_REF_0 : integer := 2;
WRAPPER_PLL_DIVSEL_REF_1 : integer := 2;
WRAPPER_SIMULATION : integer := 0 -- Set to 1 for simulation
);
port
(
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X0_Y0)
------------------------ Loopback and Powerdown Ports ----------------------
TILE0_RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TILE0_RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
TILE0_TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TILE0_TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
--------------------------------- PLL Ports --------------------------------
TILE0_CLK00_IN : in std_logic;
TILE0_CLK01_IN : in std_logic;
TILE0_GTPRESET0_IN : in std_logic;
TILE0_GTPRESET1_IN : in std_logic;
TILE0_PLLLKDET0_OUT : out std_logic;
TILE0_PLLLKDET1_OUT : out std_logic;
TILE0_RESETDONE0_OUT : out std_logic;
TILE0_RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
TILE0_RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
TILE0_RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
TILE0_RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
TILE0_RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
---------------------- Receive Ports - Clock Correction --------------------
TILE0_RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
TILE0_RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
TILE0_RXENMCOMMAALIGN0_IN : in std_logic;
TILE0_RXENMCOMMAALIGN1_IN : in std_logic;
TILE0_RXENPCOMMAALIGN0_IN : in std_logic;
TILE0_RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
TILE0_RXDATA0_OUT : out std_logic_vector(15 downto 0);
TILE0_RXDATA1_OUT : out std_logic_vector(15 downto 0);
TILE0_RXRESET0_IN : in std_logic;
TILE0_RXRESET1_IN : in std_logic;
TILE0_RXUSRCLK0_IN : in std_logic;
TILE0_RXUSRCLK1_IN : in std_logic;
TILE0_RXUSRCLK20_IN : in std_logic;
TILE0_RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
TILE0_GATERXELECIDLE0_IN : in std_logic;
TILE0_GATERXELECIDLE1_IN : in std_logic;
TILE0_IGNORESIGDET0_IN : in std_logic;
TILE0_IGNORESIGDET1_IN : in std_logic;
TILE0_RXELECIDLE0_OUT : out std_logic;
TILE0_RXELECIDLE1_OUT : out std_logic;
TILE0_RXN0_IN : in std_logic;
TILE0_RXN1_IN : in std_logic;
TILE0_RXP0_IN : in std_logic;
TILE0_RXP1_IN : in std_logic;
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
TILE0_RXSTATUS0_OUT : out std_logic_vector(2 downto 0);
TILE0_RXSTATUS1_OUT : out std_logic_vector(2 downto 0);
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
TILE0_PHYSTATUS0_OUT : out std_logic;
TILE0_PHYSTATUS1_OUT : out std_logic;
TILE0_RXVALID0_OUT : out std_logic;
TILE0_RXVALID1_OUT : out std_logic;
-------------------- Receive Ports - RX Polarity Control -------------------
TILE0_RXPOLARITY0_IN : in std_logic;
TILE0_RXPOLARITY1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
TILE0_GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
TILE0_GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TILE0_TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARISK0_IN : in std_logic_vector(1 downto 0);
TILE0_TXCHARISK1_IN : in std_logic_vector(1 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TILE0_TXDATA0_IN : in std_logic_vector(15 downto 0);
TILE0_TXDATA1_IN : in std_logic_vector(15 downto 0);
TILE0_TXUSRCLK0_IN : in std_logic;
TILE0_TXUSRCLK1_IN : in std_logic;
TILE0_TXUSRCLK20_IN : in std_logic;
TILE0_TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TILE0_TXN0_OUT : out std_logic;
TILE0_TXN1_OUT : out std_logic;
TILE0_TXP0_OUT : out std_logic;
TILE0_TXP1_OUT : out std_logic;
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TILE0_TXDETECTRX0_IN : in std_logic;
TILE0_TXDETECTRX1_IN : in std_logic;
TILE0_TXELECIDLE0_IN : in std_logic;
TILE0_TXELECIDLE1_IN : in std_logic
);
end GTPA1_DUAL_WRAPPER;
architecture RTL of GTPA1_DUAL_WRAPPER is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of RTL : architecture is "GTPA1_DUAL_WRAPPER,s6_gtpwizard_v1_4,{gtp0_protocol_file=pcie,gtp1_protocol_file=Use_GTP0_settings}";
--***************************** Signal Declarations *****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tile0_plllkdet0_i : std_logic;
signal tile0_plllkdet1_i : std_logic;
signal tile0_plllkdet0_i2 : std_logic;
signal tile0_plllkdet1_i2 : std_logic;
--*************************** Component Declarations **************************
component GTPA1_DUAL_WRAPPER_TILE
generic
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 4;
TILE_CLK25_DIVIDER_1 : integer := 4;
TILE_PLL_DIVSEL_FB_0 : integer := 5;
TILE_PLL_DIVSEL_FB_1 : integer := 5;
TILE_PLL_DIVSEL_REF_0 : integer := 2;
TILE_PLL_DIVSEL_REF_1 : integer := 2;
--
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN0_IN : in std_logic;
RXENMCOMMAALIGN1_IN : in std_logic;
RXENPCOMMAALIGN0_IN : in std_logic;
RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(15 downto 0);
RXDATA1_OUT : out std_logic_vector(15 downto 0);
RXRESET0_IN : in std_logic;
RXRESET1_IN : in std_logic;
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0_IN : in std_logic;
GATERXELECIDLE1_IN : in std_logic;
IGNORESIGDET0_IN : in std_logic;
IGNORESIGDET1_IN : in std_logic;
RXELECIDLE0_OUT : out std_logic;
RXELECIDLE1_OUT : out std_logic;
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXSTATUS0_OUT : out std_logic_vector(2 downto 0);
RXSTATUS1_OUT : out std_logic_vector(2 downto 0);
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0_OUT : out std_logic;
PHYSTATUS1_OUT : out std_logic;
RXVALID0_OUT : out std_logic;
RXVALID1_OUT : out std_logic;
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0_IN : in std_logic;
RXPOLARITY1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
TXCHARISK0_IN : in std_logic_vector(1 downto 0);
TXCHARISK1_IN : in std_logic_vector(1 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(15 downto 0);
TXDATA1_IN : in std_logic_vector(15 downto 0);
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic;
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0_IN : in std_logic;
TXDETECTRX1_IN : in std_logic;
TXELECIDLE0_IN : in std_logic;
TXELECIDLE1_IN : in std_logic
);
end component;
--********************************* Main Body of Code**************************
begin
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
simulation : if WRAPPER_SIMULATION = 1 generate
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i2;
process
begin
wait until tile0_plllkdet0_i'event;
if(tile0_plllkdet0_i = '1') then
tile0_plllkdet0_i2 <= '1' after 100 ns;
else
tile0_plllkdet0_i2 <= tile0_plllkdet0_i;
end if;
end process;
TILE0_PLLLKDET1_OUT <= tile0_plllkdet1_i2;
process
begin
wait until tile0_plllkdet1_i'event;
if(tile0_plllkdet1_i = '1') then
tile0_plllkdet1_i2 <= '1' after 100 ns;
else
tile0_plllkdet1_i2 <= tile0_plllkdet1_i;
end if;
end process;
end generate simulation;
implementation : if WRAPPER_SIMULATION = 0 generate
TILE0_PLLLKDET0_OUT <= tile0_plllkdet0_i;
TILE0_PLLLKDET1_OUT <= tile0_plllkdet1_i;
end generate implementation;
--------------------------- Tile Instances -------------------------------
--_________________________________________________________________________
--_________________________________________________________________________
--TILE0 (X0_Y0)
tile0_gtpa1_dual_wrapper_i : GTPA1_DUAL_WRAPPER_TILE
generic map
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP => WRAPPER_SIM_GTPRESET_SPEEDUP,
TILE_CLK25_DIVIDER_0 => WRAPPER_CLK25_DIVIDER_0,
TILE_CLK25_DIVIDER_1 => WRAPPER_CLK25_DIVIDER_1,
TILE_PLL_DIVSEL_FB_0 => WRAPPER_PLL_DIVSEL_FB_0,
TILE_PLL_DIVSEL_FB_1 => WRAPPER_PLL_DIVSEL_FB_1,
TILE_PLL_DIVSEL_REF_0 => WRAPPER_PLL_DIVSEL_REF_0,
TILE_PLL_DIVSEL_REF_1 => WRAPPER_PLL_DIVSEL_REF_1,
--
TILE_PLL_SOURCE_0 => "PLL0",
TILE_PLL_SOURCE_1 => "PLL1"
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
RXPOWERDOWN0_IN => TILE0_RXPOWERDOWN0_IN,
RXPOWERDOWN1_IN => TILE0_RXPOWERDOWN1_IN,
TXPOWERDOWN0_IN => TILE0_TXPOWERDOWN0_IN,
TXPOWERDOWN1_IN => TILE0_TXPOWERDOWN1_IN,
--------------------------------- PLL Ports --------------------------------
CLK00_IN => TILE0_CLK00_IN,
CLK01_IN => TILE0_CLK01_IN,
GTPRESET0_IN => TILE0_GTPRESET0_IN,
GTPRESET1_IN => TILE0_GTPRESET1_IN,
PLLLKDET0_OUT => tile0_plllkdet0_i,
PLLLKDET1_OUT => tile0_plllkdet1_i,
RESETDONE0_OUT => TILE0_RESETDONE0_OUT,
RESETDONE1_OUT => TILE0_RESETDONE1_OUT,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT => TILE0_RXCHARISK0_OUT,
RXCHARISK1_OUT => TILE0_RXCHARISK1_OUT,
RXDISPERR0_OUT => TILE0_RXDISPERR0_OUT,
RXDISPERR1_OUT => TILE0_RXDISPERR1_OUT,
RXNOTINTABLE0_OUT => TILE0_RXNOTINTABLE0_OUT,
RXNOTINTABLE1_OUT => TILE0_RXNOTINTABLE1_OUT,
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0_OUT => TILE0_RXCLKCORCNT0_OUT,
RXCLKCORCNT1_OUT => TILE0_RXCLKCORCNT1_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN0_IN => TILE0_RXENMCOMMAALIGN0_IN,
RXENMCOMMAALIGN1_IN => TILE0_RXENMCOMMAALIGN1_IN,
RXENPCOMMAALIGN0_IN => TILE0_RXENPCOMMAALIGN0_IN,
RXENPCOMMAALIGN1_IN => TILE0_RXENPCOMMAALIGN1_IN,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT => TILE0_RXDATA0_OUT,
RXDATA1_OUT => TILE0_RXDATA1_OUT,
RXRESET0_IN => TILE0_RXRESET0_IN,
RXRESET1_IN => TILE0_RXRESET1_IN,
RXUSRCLK0_IN => TILE0_RXUSRCLK0_IN,
RXUSRCLK1_IN => TILE0_RXUSRCLK1_IN,
RXUSRCLK20_IN => TILE0_RXUSRCLK20_IN,
RXUSRCLK21_IN => TILE0_RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0_IN => TILE0_GATERXELECIDLE0_IN,
GATERXELECIDLE1_IN => TILE0_GATERXELECIDLE1_IN,
IGNORESIGDET0_IN => TILE0_IGNORESIGDET0_IN,
IGNORESIGDET1_IN => TILE0_IGNORESIGDET1_IN,
RXELECIDLE0_OUT => TILE0_RXELECIDLE0_OUT,
RXELECIDLE1_OUT => TILE0_RXELECIDLE1_OUT,
RXN0_IN => TILE0_RXN0_IN,
RXN1_IN => TILE0_RXN1_IN,
RXP0_IN => TILE0_RXP0_IN,
RXP1_IN => TILE0_RXP1_IN,
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXSTATUS0_OUT => TILE0_RXSTATUS0_OUT,
RXSTATUS1_OUT => TILE0_RXSTATUS1_OUT,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0_OUT => TILE0_PHYSTATUS0_OUT,
PHYSTATUS1_OUT => TILE0_PHYSTATUS1_OUT,
RXVALID0_OUT => TILE0_RXVALID0_OUT,
RXVALID1_OUT => TILE0_RXVALID1_OUT,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0_IN => TILE0_RXPOLARITY0_IN,
RXPOLARITY1_IN => TILE0_RXPOLARITY1_IN,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT => TILE0_GTPCLKOUT0_OUT,
GTPCLKOUT1_OUT => TILE0_GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARDISPMODE0_IN => TILE0_TXCHARDISPMODE0_IN,
TXCHARDISPMODE1_IN => TILE0_TXCHARDISPMODE1_IN,
TXCHARISK0_IN => TILE0_TXCHARISK0_IN,
TXCHARISK1_IN => TILE0_TXCHARISK1_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN => TILE0_TXDATA0_IN,
TXDATA1_IN => TILE0_TXDATA1_IN,
TXUSRCLK0_IN => TILE0_TXUSRCLK0_IN,
TXUSRCLK1_IN => TILE0_TXUSRCLK1_IN,
TXUSRCLK20_IN => TILE0_TXUSRCLK20_IN,
TXUSRCLK21_IN => TILE0_TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT => TILE0_TXN0_OUT,
TXN1_OUT => TILE0_TXN1_OUT,
TXP0_OUT => TILE0_TXP0_OUT,
TXP1_OUT => TILE0_TXP1_OUT,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0_IN => TILE0_TXDETECTRX0_IN,
TXDETECTRX1_IN => TILE0_TXDETECTRX1_IN,
TXELECIDLE0_IN => TILE0_TXELECIDLE0_IN,
TXELECIDLE1_IN => TILE0_TXELECIDLE1_IN
);
end RTL;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Pipeline_Polynomial_Calc_v3
-- Module Name: Pipeline_Polynomial_Calc_v3
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st and 3rd step in Goppa Code Decoding.
--
-- This circuit is to be used inside polynomial_syndrome_computing_n to evaluate polynomials
-- or generate the syndrome.
-- This circuit is the essential for 1 pipeline, therefor all stages are composed in here.
-- For more than 1 pipeline, only in polynomial_syndrome_computing_n with the shared components
-- for all pipelines.
--
-- For the computation this circuit applies the Horner scheme, where at each stage
-- an accumulator is multiplied by respective x and then added accumulated with coefficient.
-- In Horner scheme algorithm, it begin from the most significative coefficient until reaches
-- lesser significative coefficient.
--
-- For area reduction this circuit were optimized in version pipeline_polynomial_calc_v3
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- size :
--
-- The number of stages the pipeline has. More stages means more values of value_polynomial
-- are tested at once.
--
-- Dependencies:
-- VHDL-93
--
-- stage_polynomial_calc_v3 Rev 1.0
-- register_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pipeline_polynomial_calc_v3 is
Generic (
gf_2_m : integer range 1 to 20;
size : integer
);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((size - 1) downto 0);
reg_x_rst : in STD_LOGIC_VECTOR((size - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end pipeline_polynomial_calc_v3;
architecture Behavioral of pipeline_polynomial_calc_v3 is
component stage_polynomial_calc_v3
Generic(gf_2_m : integer range 1 to 20 := 11);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial_coefficient : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC;
mode_polynomial_syndrome : in STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component register_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
type array_std_logic_vector is array(integer range <>) of STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal acc_d : array_std_logic_vector((size) downto 0);
signal acc_q : array_std_logic_vector((size) downto 0);
signal x_d : array_std_logic_vector((size) downto 0);
signal x_q : array_std_logic_vector((size - 1) downto 0);
constant reg_x_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
begin
x_d(0) <= value_x;
acc_d(0) <= value_acc;
pipeline : for I in 0 to (size - 1) generate
reg_x_I : register_rst_nbits
Generic Map(size => gf_2_m)
Port Map(
d => x_d(I),
clk => clk,
ce => '1',
rst => reg_x_rst(I),
rst_value => reg_x_rst_value,
q => x_q(I)
);
reg_acc_I : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => acc_d(I),
clk => clk,
ce => '1',
q => acc_q(I)
);
stage_I : stage_polynomial_calc_v3
Generic Map(gf_2_m => gf_2_m)
Port Map (
value_x => x_q(I),
value_polynomial_coefficient => value_polynomial(((gf_2_m)*(I+1) - 1) downto ((gf_2_m)*(I))),
mode_polynomial_syndrome => mode_polynomial_syndrome,
value_acc => acc_q(I),
value_codeword => value_codeword(I),
new_value_syndrome => new_value_syndrome(((gf_2_m)*(I+1) - 1) downto ((gf_2_m)*(I))),
new_value_acc => acc_d(I+1)
);
x_d(I+1) <= x_q(I);
end generate;
reg_acc_last : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => acc_d(size),
clk => clk,
ce => '1',
q => acc_q(size)
);
new_value_acc <= acc_q(size);
end Behavioral; |
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Containing a bridge between a RapidIO network and a Wishbone bus. Packets
-- NWRITE and NREAD are currently supported.
--
-- To Do:
-- -
--
-- Author(s):
-- - Nader Kardouni, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.ALL;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- entity for RioWbBridge.
-------------------------------------------------------------------------------
Entity RioWbBridge is
generic(
DEVICE_IDENTITY : std_logic_vector(15 downto 0);
DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
DEVICE_REV : std_logic_vector(31 downto 0);
ASSY_IDENTITY : std_logic_vector(15 downto 0);
ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
ASSY_REV : std_logic_vector(15 downto 0);
DEFAULT_BASE_DEVICE_ID : std_logic_vector(15 downto 0) := x"ffff");
port(
clk : in std_logic; -- Main clock 25MHz
areset_n : in std_logic; -- Asynchronous reset, active low
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
readContent_o : out std_logic;
readContentEnd_i : in std_logic;
readContentData_i : in std_logic_vector(31 downto 0);
writeFrameFull_i : in std_logic;
writeFrame_o : out std_logic;
writeFrameAbort_o : out std_logic;
writeContent_o : out std_logic;
writeContentData_o : out std_logic_vector(31 downto 0);
-- interface to the peripherals module
wbStb_o : out std_logic; -- strob signal, active high
wbWe_o : out std_logic; -- write signal, active high
wbData_o : out std_logic_vector(7 downto 0); -- master data bus
wbAdr_o : out std_logic_vector(25 downto 0); -- master address bus
wbErr_i : in std_logic; -- error signal, high active
wbAck_i : in std_logic; -- slave acknowledge
wbData_i : in std_logic_vector(7 downto 0) -- slave data bus
);
end;
-------------------------------------------------------------------------------
-- Architecture for RioWbBridge.
-------------------------------------------------------------------------------
architecture rtl of RioWbBridge is
component Crc16CITT is
port(
d_i : in std_logic_vector(15 downto 0);
crc_i : in std_logic_vector(15 downto 0);
crc_o : out std_logic_vector(15 downto 0));
end component;
constant RST_LVL : std_logic := '0';
constant BERR_UNKNOWN_DATA : std_logic_vector(7 downto 0) := X"08"; -- not valid data
constant BERR_FRAME_SIZE : std_logic_vector(7 downto 0) := X"81"; -- Frame code size error
constant BERR_FRAME_CODE : std_logic_vector(7 downto 0) := X"80"; -- Frame code type error
constant BERR_NOT_RESPONSE : std_logic_vector(7 downto 0) := X"86"; -- Not response from the device
type state_type_RioBrige is (IDLE, WAIT_HEADER_0, HEADER_0, HEADER_1, CHECK_OPERATION,
READ_ADDRESS, READ_FROM_FIFO, CHECK_ERROR, WRITE_DATA,
WRITE_TO_WB, WAIT_IDLE, SEND_DONE_0, SEND_DONE_1,
SEND_DONE_2, READ_FROM_WB, APPEND_CRC,
SEND_TO_FIFO, SEND_ERROR, SEND_FRAME, APPEND_CRC_AND_SEND,
SEND_MAINTENANCE_READ_RESPONSE_0, SEND_MAINTENANCE_READ_RESPONSE_1,
SEND_MAINTENANCE_WRITE_RESPONSE_0, SEND_MAINTENANCE_WRITE_RESPONSE_1);
signal stateRB, nextStateRB : state_type_RioBrige;
type byteArray8 is array (0 to 7) of std_logic_vector(7 downto 0);
signal dataLane : byteArray8;
-- type byteArray4 is array (0 to 3) of std_logic_vector(7 downto 0);
-- signal dataLaneS : byteArray4;
signal pos, byteOffset : integer range 0 to 7;
signal numberOfByte, byteCnt, headLen : integer range 0 to 256;
signal endianMsb, reserved, ready : std_logic;
signal start : std_logic;
signal wdptr : std_logic;
signal wbStb : std_logic;
signal xamsbs : std_logic_vector(1 downto 0);
signal ftype : std_logic_vector(3 downto 0);
signal ttype : std_logic_vector(3 downto 0);
signal size : std_logic_vector(3 downto 0);
signal tid : std_logic_vector(7 downto 0);
signal tt : std_logic_vector(1 downto 0);
signal errorCode : std_logic_vector(7 downto 0);
signal sourceId : std_logic_vector(15 downto 0);
signal destinationId : std_logic_vector(15 downto 0);
signal writeContentData : std_logic_vector(31 downto 0);
signal crc16Current, crc16Temp, crc16Next: std_logic_vector(15 downto 0);
signal tempAddr : std_logic_vector(25 downto 0);
signal timeOutCnt : std_logic_vector(14 downto 0);
-- Configuration memory signal declaration.
signal configEnable : std_logic;
signal configWrite : std_logic;
signal configAddress : std_logic_vector(23 downto 0);
signal configDataWrite : std_logic_vector(31 downto 0);
signal configDataRead : std_logic_vector(31 downto 0);
signal componentTag : std_logic_vector(31 downto 0);
signal baseDeviceId : std_logic_vector(15 downto 0) := DEFAULT_BASE_DEVICE_ID;
signal hostBaseDeviceIdLocked : std_logic;
signal hostBaseDeviceId : std_logic_vector(15 downto 0) := (others => '1');
begin
wbStb_o <= wbStb;
writeContentData_o <= writeContentData;
Crc16High: Crc16CITT
port map(
d_i=>writeContentData(31 downto 16), crc_i=>crc16Current, crc_o=>crc16Temp);
Crc16Low: Crc16CITT
port map(
d_i=>writeContentData(15 downto 0), crc_i=>crc16Temp, crc_o=>crc16Next);
-----------------------------------------------------------------------------
-- wbInterfaceCtrl
-- This process handle the Wishbone interface to the RioWbBridge module.
-----------------------------------------------------------------------------
wbInterfaceCtrl: process(clk, areset_n)
variable Temp : std_logic_vector(2 downto 0);
begin
if areset_n = RST_LVL then
start <= '0';
wdptr <= '0';
wbStb <= '0';
wbWe_o <= '0';
byteCnt <= 0;
headLen <= 0;
byteOffset <= 0;
readFrame_o <= '0';
readContent_o <= '0';
writeFrame_o <= '0';
writeContent_o <= '0';
writeFrameAbort_o <= '0';
configWrite <= '0';
configEnable <= '0';
ready <= '0';
endianMsb <= '0';
stateRB <= IDLE;
nextStateRB <= IDLE;
tt <= (others => '0');
tid <= (others => '0');
size <= (others => '0');
ttype <= (others => '0');
ftype <= (others => '0');
xamsbs <= (others => '0');
sourceId <= (others => '0');
configDataWrite <= (others => '0');
destinationId <= (others => '0');
errorCode <= (others => '0');
tempAddr <= (others => '0');
wbAdr_o <= (others => '0');
wbData_o <= (others => '0');
writeContentData <= (others => '0');
dataLane <= (others =>(others => '0'));
-- dataLaneS <= (others =>(others => '0'));
crc16Current <= (others => '0');
timeOutCnt <= (others => '0');
Temp := (others => '0');
elsif clk'event and clk ='1' then
case stateRB is
when IDLE =>
if (readFrameEmpty_i = '0') and (writeFrameFull_i = '0') then
readContent_o <= '1';
byteCnt <= 0;
ready <= '0';
endianMsb <= '1';
timeOutCnt <= (others => '0');
crc16Current <= (others => '1');
stateRB <= WAIT_HEADER_0;
else
start <= '0';
readFrame_o <= '0';
readContent_o <= '0';
writeFrame_o <= '0';
writeContent_o <= '0';
writeFrameAbort_o <= '0';
errorCode <= (others => '0');
writeContentData <= (others => '0');
dataLane <= (others =>(others => '0'));
-- dataLaneS <= (others =>(others => '0'));
Temp := (others => '0');
end if;
when WAIT_HEADER_0 =>
stateRB <= HEADER_0;
when HEADER_0 =>
readContent_o <= '1'; -- read the header (frame 0)
tt <= readContentData_i(21 downto 20);
ftype <= readContentData_i(19 downto 16);
destinationId <= readContentData_i(15 downto 0);
stateRB <= HEADER_1;
when HEADER_1 => -- read the header (frame 1)
readContent_o <= '1';
ttype <= readContentData_i(15 downto 12);
size <= readContentData_i(11 downto 8);
tid <= readContentData_i(7 downto 0);
sourceId <= readContentData_i(31 downto 16);
stateRB <= READ_ADDRESS;
when READ_ADDRESS =>
readContent_o <= '0';
wdptr <= readContentData_i(2);
xamsbs <= readContentData_i(1 downto 0);
tempAddr <= readContentData_i(25 downto 3) & "000"; -- Wishbone address bus is 26 bits width
configAddress <= readContentData_i(23 downto 0); -- this line is in case of maintenance pakage (config-offset(21-bits)+wdptr(1-bit)+rsv(2-bits))
stateRB <= CHECK_ERROR;
when CHECK_ERROR =>
byteOffset <= pos; -- first byte position in the first payload
tempAddr <= tempAddr + pos; -- first address
if readContentEnd_i = '1' then -- check if data not valid i the switch buffer
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= BERR_UNKNOWN_DATA; -- not valid data
stateRB <= SEND_ERROR;
-- check if error in the frame size for write pakage
elsif (reserved = '1') and (ftype = FTYPE_WRITE_CLASS) then
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= BERR_FRAME_SIZE; -- Frame code size error
stateRB <= SEND_ERROR;
-- type 5 pakage formate, NWRITE transaction (write to peripherals) read payload from the buffer
elsif (ftype = FTYPE_WRITE_CLASS) and (ttype = "0100") and (tt = "01") then
readContent_o <= '1';
stateRB <= READ_FROM_FIFO; -- read the payload
nextStateRB <= SEND_ERROR; -- this is in case not valid data in switch buffer
headLen <= 12;
-- Type 2 pakage formate, NREAD transaction, (read from peripherals) write payload to the buffer
elsif (ftype = FTYPE_REQUEST_CLASS) and (ttype = "0100") and (tt = "01") then
writeContent_o <= '1'; -- write the header-0 of the Read Response pakage
writeContentData(15 downto 0) <= sourceId; -- write to the source address
writeContentData(19 downto 16) <= "1101"; -- Response pakage type 13, ftype Response
writeContentData(21 downto 20) <= "01"; -- tt
writeContentData(31 downto 22) <= "0000000000"; -- acckId, vc, cfr, prio
stateRB <= SEND_DONE_0; --
headLen <= 8;
-- Type 8 pakage formate, maintenance Read request
elsif (ftype = FTYPE_MAINTENANCE_CLASS) and (ttype = TTYPE_MAINTENANCE_READ_REQUEST) and (tt = "01") then
configWrite <= '0'; -- read config operation
configEnable <= '1'; -- enable signal to the memoryConfig process
writeContent_o <= '1';
-- write the header-0 of the Read Response pakage
writeContentData(15 downto 0) <= sourceId; -- write to the source address, this is a response pakage
writeContentData(19 downto 16) <= FTYPE_MAINTENANCE_CLASS; -- ftype, maintenance
writeContentData(21 downto 20) <= "01"; -- tt
writeContentData(31 downto 22) <= "0000000000"; -- acckId, vc, cfr, prio
stateRB <= SEND_MAINTENANCE_READ_RESPONSE_0;
-- Type 8 pakage formate, maintenance Write request
elsif (ftype = FTYPE_MAINTENANCE_CLASS) and (ttype = TTYPE_MAINTENANCE_WRITE_REQUEST) and (tt = "01") then
configWrite <= '1'; -- write config operation
writeContent_o <= '1'; -- write the header-0
writeContentData(15 downto 0) <= sourceId; -- write to the source address, this is a response pakage
writeContentData(19 downto 16) <= FTYPE_MAINTENANCE_CLASS; -- ftype, maintenance
writeContentData(21 downto 20) <= "01"; -- tt
writeContentData(31 downto 22) <= "0000000000"; -- acckId, vc, cfr, prio
stateRB <= SEND_MAINTENANCE_WRITE_RESPONSE_0;
-- Error: unexpected ftype or ttype
else
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= BERR_FRAME_CODE;
stateRB <= SEND_ERROR; -- next state after the dataLane is stored in the switch buffer
end if;
when SEND_MAINTENANCE_READ_RESPONSE_0 =>
byteCnt <= 0;
configEnable <= '0'; -- disable signal to the memoryConfig process
-- write the header-1 of the Read Response pakage
writeContentData(7 downto 0) <= tid;
writeContentData(11 downto 8) <= "0000"; -- size/status
writeContentData(15 downto 12) <= TTYPE_MAINTENANCE_READ_RESPONSE; -- transaction type, Maintenance Read Response
writeContentData(31 downto 16) <= baseDeviceId; -- destination address, because this is a response pakage
crc16Current <= crc16Next; -- first frame's CRC
stateRB <= SEND_MAINTENANCE_READ_RESPONSE_1;
when SEND_MAINTENANCE_READ_RESPONSE_1 =>
byteCnt <= byteCnt + 1; -- using byteCnt as a counter
if byteCnt = 0 then
writeContentData <= X"FF" & X"000000"; -- write the filed with HOP + reserved
crc16Current <= crc16Next; -- second frame's CRC
elsif byteCnt = 1 then
if configAddress(2) = '0' then -- check the wdptr bit in the config offset field
writeContentData <= configDataRead; -- write payload-0 with data if wdptr='0'
else
writeContentData <= (others => '0'); -- write zeros
end if;
crc16Current <= crc16Next; -- third frame's CRC
elsif byteCnt = 2 then
if configAddress(2) = '0' then -- check the wdptr bit in the config offset field
writeContentData <= (others => '0'); -- write zeros
else
writeContentData <= configDataRead; -- write payload-1 with data if wdptr='1'
end if;
crc16Current <= crc16Next; -- forth frame's CRC
elsif byteCnt = 3 then
writeContentData <= crc16Next & X"0000"; -- write the CRC field
else
writeContent_o <= '0';
stateRB <= SEND_FRAME;
end if;
when SEND_MAINTENANCE_WRITE_RESPONSE_0 =>
byteCnt <= 0;
readContent_o <= '1'; -- read the config offset
if configAddress(2) = '0' then -- check the wdptr bit in the config offset field
configDataWrite <= readContentData_i; -- copy payload-0 if wdptr='0'
else
configDataWrite <= configDataWrite; -- do nothing
end if;
writeContentData(7 downto 0) <= tid;
writeContentData(11 downto 8) <= "0000"; -- size/status
writeContentData(15 downto 12) <= TTYPE_MAINTENANCE_WRITE_RESPONSE; -- transaction type, Maintenance Write Response
writeContentData(31 downto 16) <= baseDeviceId; -- destination address, because this is a response pakage
crc16Current <= crc16Next; -- first frame's CRC
stateRB <= SEND_MAINTENANCE_WRITE_RESPONSE_1;
when SEND_MAINTENANCE_WRITE_RESPONSE_1 =>
byteCnt <= byteCnt + 1; -- using byteCnt as a counter
if byteCnt = 0 then
writeContentData <= X"FF" & X"000000"; -- write the filed with HOP + reserved
crc16Current <= crc16Next; -- second frame's CRC
elsif byteCnt = 1 then
configEnable <= '1'; -- enable signal to the memoryConfig process
writeContentData <= crc16Next & X"0000"; -- write the CRC field
if configAddress(2) = '0' then -- check the wdptr bit in the config offset field
configDataWrite <= configDataWrite; -- do nothing
else
configDataWrite <= readContentData_i; -- copy payload-1 if wdptr='1'
end if;
else
configEnable <= '0'; -- disable signal to the memoryConfig process
readContent_o <= '0'; -- at this point even the frame's CRC is read from the buffer
writeContent_o <= '0';
stateRB <= SEND_FRAME;
end if;
when SEND_DONE_0 =>
writeContent_o <= '1';
writeContentData(7 downto 0) <= tid;
writeContentData(11 downto 8) <= "0000"; -- size/status
writeContentData(15 downto 12) <= "1000"; -- ttype
writeContentData(31 downto 16) <= baseDeviceId;
crc16Current <= crc16Next; -- first frame's CRC
stateRB <= SEND_DONE_1;
when SEND_DONE_1 =>
byteCnt <= 0;
dataLane <= (others =>(others => '0'));
writeContent_o <= '0'; -- this line is to make sure that the CRC is complete read
crc16Current <= crc16Next; -- second frame's CRC
wbAdr_o <= tempAddr;
tempAddr <= tempAddr + 1;
wbStb <= '1';
wbWe_o <= '0';
byteOffset <= pos;
stateRB <= READ_FROM_WB;
when READ_FROM_WB =>
if wbAck_i = '1' then
timeOutCnt <= (others => '0'); -- reset the time out conter
if wbErr_i = '0' then -- check if no error occur
if (byteCnt < numberOfByte - 1) then -- check if reach the last data byte
byteCnt <= byteCnt + 1;
if (byteCnt + headLen = 80) then -- when current position in payload is a CRC position
dataLane(0) <= crc16Current(15 downto 8);
dataLane(1) <= crc16Current(7 downto 0);
dataLane(2) <= wbData_i;
byteOffset <= 3;
elsif byteOffset < 7 then
dataLane(byteOffset) <= wbData_i;
byteOffset <= byteOffset + 1;
else -- dataLane vector is ready to send to fifo
dataLane(7) <= wbData_i;
byteOffset <= 0; -- Here, sets byteOffset for other response
stateRB <= SEND_TO_FIFO;
nextStateRB <= READ_FROM_WB; --
end if;
else -- get last data from Wishbone
wbStb <= '0';
byteCnt <= 0; -- Here, using byteCnt and reset it for other response
dataLane(byteOffset) <= wbData_i;
stateRB <= APPEND_CRC_AND_SEND;
if byteOffset < 7 then -- checking for CRC appending position
byteOffset <= byteOffset + 1;
else
byteOffset <= 0;
end if;
end if;
-- when Wishbone error occur
else
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= wbData_i;
stateRB <= SEND_ERROR;
end if;
else -- when no acknowledge received
if timeOutCnt(13) = '1' then -- when waiting more than 1 ms for response from the device
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= BERR_NOT_RESPONSE;
stateRB <= SEND_ERROR;
else
timeOutCnt <= timeOutCnt + 1;
end if;
end if;
-- appending CRC and write to the fifo when frame is shorter then 80 bytes
when APPEND_CRC_AND_SEND =>
writeContent_o <= '0';
byteCnt <= byteCnt + 1;
-- check if frame is shorter than 80 bytes
if (numberOfByte < 65) then
-- Yes, frame is shorter then 80 bytes
if byteCnt = 0 then
-- first write the current double word to the fifo
-- then put the CRC in the next double word
byteOffset <= 0;
stateRB <= SEND_TO_FIFO;
nextStateRB <= APPEND_CRC_AND_SEND;
elsif byteCnt = 1 then
-- append the CRC
writeContent_o <= '1';
writeContentData <= crc16Current & X"0000";
else
stateRB <= SEND_FRAME; -- store in the switch buffer
end if;
else
--No, appending CRC and write to the fifo when frame is longer then 80 bytes
if byteCnt = 0 then
-- check if the last byte was placed in the second half of the double word,
-- in that case write the first word to the fifo.
writeContentData <= dataLane(0) & dataLane(1) & dataLane(2) & dataLane(3);
elsif byteCnt = 1 then
crc16Current <= crc16Temp; -- calcylate the crc for the 16 most significant bits
elsif byteCnt = 2 then
writeContent_o <= '1';
writeContentData <= dataLane(0) & dataLane(1) & crc16Current;
else
stateRB <= SEND_FRAME; -- store in the switch buffer
end if;
end if;
when SEND_TO_FIFO =>
if byteOffset = 0 then -- using byteOffset as a counter
byteOffset <= 1;
writeContent_o <= '1';
writeContentData <= dataLane(0) & dataLane(1) & dataLane(2) & dataLane(3);
elsif byteOffset = 1 then -- using byteOffset as a counter
byteOffset <= 2;
writeContent_o <= '0';
crc16Current <= crc16Next; -- calcylate the crc
elsif byteOffset = 2 then
byteOffset <= 3;
writeContent_o <= '1';
writeContentData <= dataLane(4) & dataLane(5) & dataLane(6) & dataLane(7);
elsif byteOffset = 3 then
crc16Current <= crc16Next; -- calcylate the crc
writeContent_o <= '0';
byteOffset <= 0;
stateRB <= nextStateRB;
dataLane <= (others =>(others => '0'));
end if;
when READ_FROM_FIFO =>
if (endianMsb = '1') then
if (readContentEnd_i = '0') then
endianMsb <= '0';
dataLane(0 to 3) <= (readContentData_i(31 downto 24), readContentData_i(23 downto 16),
readContentData_i(15 downto 8), readContentData_i(7 downto 0));
else
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
readContent_o <= '0';
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= BERR_FRAME_SIZE;
stateRB <= SEND_ERROR;
-- stateRB <= IDLE;
end if;
else
endianMsb <= '1';
readContent_o <= '0';
dataLane(4 to 7) <= (readContentData_i(31 downto 24), readContentData_i(23 downto 16),
readContentData_i(15 downto 8), readContentData_i(7 downto 0));
if ready = '1' then
stateRB <= nextStateRB;
else
stateRB <= WRITE_TO_WB;
end if;
end if;
when WRITE_TO_WB =>
if wbStb = '0' then
wbStb <= '1';
wbWe_o <= '1';
byteCnt <= 1;
byteOffset <= byteOffset + 1; -- increase number of counted byte
tempAddr <= tempAddr + 1; -- increase the memory sddress address
wbAdr_o <= tempAddr;
wbData_o <= dataLane(byteOffset);
else
if wbAck_i = '1' then
timeOutCnt <= (others => '0'); -- reset the time out conter
if wbErr_i = '0' then -- check the peripherals error signal
if byteCnt < numberOfByte then
tempAddr <= tempAddr + 1; -- increase the memory sddress address
wbAdr_o <= tempAddr;
wbData_o <= dataLane(byteOffset);
byteCnt <= byteCnt + 1; -- increase number of counted byte
if byteOffset < 7 then
if (byteCnt + headLen = 79) then -- check for the CRC-byte position 80 in the frame
byteOffset <= byteOffset + 3;
else
byteOffset <= byteOffset + 1;
end if;
else
if (byteCnt + headLen = 79) then -- check for the CRC-byte position 80 in the frame
byteOffset <= 2;
else
byteOffset <= 0;
end if;
if byteCnt < numberOfByte - 1 then
readContent_o <= '1';
stateRB <= READ_FROM_FIFO;
end if;
end if;
else -- no more data to send to the peripherals
wbStb <= '0';
wbWe_o <= '0';
ready <= '1';
stateRB <= SEND_FRAME;
end if;
else -- if the peripheral generates an error, send an error Response
wbStb <= '0';
wbWe_o <= '0';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= wbData_i;
stateRB <= SEND_ERROR;
end if;
else
-- if readContentEnd_i = '1' then -- when unvalid data in the switch buffer
-- wbStb <= '0';
-- wbWe_o <= '0';
-- readFrame_o <= '1';
-- byteOffset <= 0;
-- writeFrameAbort_o <= '1'; -- over write the frame with an error frame
-- errorCode <= BERR_FRAME_SIZE; -- more data content is expected, Frame size error
-- stateRB <= SEND_ERROR;
-- else
if timeOutCnt(13) = '1' then -- when waiting more than 1 ms for response from the device
wbStb <= '0';
wbWe_o <= '0';
readFrame_o <= '1';
byteOffset <= 0;
writeFrameAbort_o <= '1'; -- over write the frame with an error frame
errorCode <= BERR_NOT_RESPONSE;
stateRB <= SEND_ERROR;
else
timeOutCnt <= timeOutCnt + 1;
end if;
-- end if;
end if;
end if;
when SEND_ERROR => -- Generate a Response Class, an error pakage ftype=13, ttype=8, status="1111"
readFrame_o <= '0';
writeFrameAbort_o <= '0';
byteOffset <= byteOffset + 1;
if byteOffset = 0 then
writeContent_o <= '1'; -- start write to the buffer
crc16Current <= (others => '1');
writeContentData <= "00000000" & "00" & "01" & "1101" & sourceId;
elsif byteOffset = 1 then
writeContentData <= baseDeviceId & "1000" & "1111" & tid;
crc16Current <= crc16Next; -- first frame's CRC
elsif byteOffset = 2 then
writeContentData <= errorCode & x"000000";
crc16Current <= crc16Next; -- second frame's CRC
elsif byteOffset = 3 then
writeContentData <= x"00000000";
crc16Current <= crc16Next; -- third frame's CRC
elsif byteOffset = 4 then
writeContentData <= crc16Next & X"0000"; -- write the CRC field
else
writeContent_o <= '0';
writeFrame_o <= '1';
readFrame_o <= '1';
stateRB <= WAIT_IDLE;
end if;
when SEND_FRAME =>
if (ftype = FTYPE_WRITE_CLASS) and (ttype = TTYPE_NWRITE_TRANSACTION) and (tt = "01") then -- check what type of pakage we got
readFrame_o <= '1';
elsif (ftype = FTYPE_REQUEST_CLASS) and (ttype = TTYPE_NREAD_TRANSACTION) and (tt = "01") then -- write payload to the buffer is done
readFrame_o <= '1';
writeFrame_o <= '1';
else -- the operation was not valid
readFrame_o <= '1';
writeFrame_o <= '1';
end if;
stateRB <= WAIT_IDLE;
when WAIT_IDLE =>
readFrame_o <= '0';
writeFrame_o <= '0';
readContent_o <= '0'; -- this line is to make sure that the CRC is complete read
stateRB <= IDLE;
when others =>
stateRB <= IDLE;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- Configuration memory.
-----------------------------------------------------------------------------
memoryConfig : process(clk, areset_n)
begin
if (areset_n = '0') then
configDataRead <= (others => '0');
baseDeviceId <= DEFAULT_BASE_DEVICE_ID;
componentTag <= (others => '0');
hostBaseDeviceIdLocked <= '0';
hostBaseDeviceId <= (others => '1');
elsif (clk'event and clk = '1') then
if (configEnable = '1') then
case (configAddress) is
when x"000000" =>
-- Device Identity CAR. Read-only.
configDataRead(31 downto 16) <= DEVICE_IDENTITY;
configDataRead(15 downto 0) <= DEVICE_VENDOR_IDENTITY;
when x"000004" =>
-- Device Information CAR. Read-only.
configDataRead(31 downto 0) <= DEVICE_REV;
when x"000008" =>
-- Assembly Identity CAR. Read-only.
configDataRead(31 downto 16) <= ASSY_IDENTITY;
configDataRead(15 downto 0) <= ASSY_VENDOR_IDENTITY;
when x"00000c" =>
-- Assembly Informaiton CAR. Read-only.
-- Extended features pointer to "0000".
configDataRead(31 downto 16) <= ASSY_REV;
configDataRead(15 downto 0) <= x"0000";
when x"000010" =>
-- Processing Element Features CAR. Read-only.
-- Bridge(31), Memory(30), Processor(29), Switch(28).
configDataRead(31) <= '1';
configDataRead(30 downto 4) <= (others => '0');
configDataRead(3) <= '1'; -- support 16 bits common transport large system
configDataRead(2 downto 0) <= "001"; -- support 34 bits address
when x"000018" =>
-- Source Operations CAR. Read-only.
configDataRead(31 downto 0) <= (others => '0');
when x"00001C" =>
-- Destination Operations CAR. Read-only.
configDataRead(31 downto 16) <= (others => '0');
configDataRead(15) <= '1';
configDataRead(14) <= '1';
configDataRead(13 downto 0) <= (others => '0');
when x"00004C" =>
-- Processing Element Logical Layer Control CSR.
configDataRead(31 downto 3) <= (others => '0');
configDataRead(2 downto 0) <= "001"; -- support 34 bits address
when x"000060" =>
-- Base Device ID CSR.
-- Only valid for end point devices.
if (configWrite = '1') then
baseDeviceId <= configDataWrite(15 downto 0);
else
configDataRead(15 downto 0) <= baseDeviceId;
end if;
when x"000068" =>
-- Host Base Device ID Lock CSR.
if (configWrite = '1') then
-- Check if this field has been written before.
if (hostBaseDeviceIdLocked = '0') then
-- The field has not been written.
-- Lock the field and set the host base device id.
hostBaseDeviceIdLocked <= '1';
hostBaseDeviceId <= configDataWrite(15 downto 0);
else
-- The field has been written.
-- Check if the written data is the same as the stored.
if (hostBaseDeviceId = configDataWrite(15 downto 0)) then
-- Same as stored, reset the value to its initial value.
hostBaseDeviceIdLocked <= '0';
hostBaseDeviceId <= (others => '1');
else
-- Not writing the same as the stored value.
-- Ignore the write.
end if;
end if;
else
configDataRead(31 downto 16) <= (others => '0');
configDataRead(15 downto 0) <= hostBaseDeviceId;
end if;
when x"00006C" =>
-- Component TAG CSR.
if (configWrite = '1') then
componentTag <= configDataWrite;
else
configDataRead <= componentTag;
end if;
when others =>
configDataRead <= (others => '0');
end case;
else
-- Config memory not enabled.
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- findInPayload
-- find out number of the bytes and first byte's position in the payload.
-----------------------------------------------------------------------------
findInPayload: process(wdptr, size)
begin
case size is
when "0000" =>
reserved <= '0';
numberOfByte <= 1;
if wdptr = '1' then
pos <= 4;
else
pos <= 0;
end if;
when "0001" =>
reserved <= '0';
numberOfByte <= 1;
if wdptr = '1' then
pos <= 5;
else
pos <= 1;
end if;
when "0010" =>
reserved <= '0';
numberOfByte <= 1;
if wdptr = '1' then
pos <= 6;
else
pos <= 2;
end if;
when "0011" =>
reserved <= '0';
numberOfByte <= 1;
if wdptr = '1' then
pos <= 7;
else
pos <= 3;
end if;
when "0100" =>
reserved <= '0';
numberOfByte <= 2;
if wdptr = '1' then
pos <= 4;
else
pos <= 0;
end if;
when "0101" =>
reserved <= '0';
numberOfByte <= 3;
if wdptr = '1' then
pos <= 5;
else
pos <= 0;
end if;
when "0110" =>
reserved <= '0';
numberOfByte <= 2;
if wdptr = '1' then
pos <= 6;
else
pos <= 2;
end if;
when "0111" =>
reserved <= '0';
numberOfByte <= 5;
if wdptr = '1' then
pos <= 3;
else
pos <= 0;
end if;
when "1000" =>
reserved <= '0';
numberOfByte <= 4;
if wdptr = '1' then
pos <= 4;
else
pos <= 0;
end if;
when "1001" =>
reserved <= '0';
numberOfByte <= 6;
if wdptr = '1' then
pos <= 2;
else
pos <= 0;
end if;
when "1010" =>
reserved <= '0';
numberOfByte <= 7;
if wdptr = '1' then
pos <= 1;
else
pos <= 0;
end if;
when "1011" =>
reserved <= '0';
if wdptr = '1' then
numberOfByte <= 16;
else
numberOfByte <= 8;
end if;
pos <= 0;
when "1100" =>
reserved <= '0';
if wdptr = '1' then
numberOfByte <= 64;
else
numberOfByte <= 32;
end if;
pos <= 0;
when "1101" =>
if wdptr = '1' then
reserved <= '0';
numberOfByte <= 128;
else
reserved <= '1';
numberOfByte <= 96;
end if;
pos <= 0;
when "1110" =>
if wdptr = '1' then
numberOfByte <= 192;
else
numberOfByte <= 160;
end if;
reserved <= '1';
pos <= 0;
when "1111" =>
if wdptr = '1' then
reserved <= '0';
numberOfByte <= 256;
else
reserved <= '1';
numberOfByte <= 224;
end if;
pos <= 0;
when others =>
reserved <= '1';
numberOfByte <= 0;
pos <= 0;
end case;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end ScanRegister;
architecture ScanRegister_arch of ScanRegister is
signal and_ce, and_se, and_ue: std_logic;
signal internal_si: std_logic_vector(Size downto 0);
signal cs_reg: std_logic_vector(Size-1 downto 0);
signal u_reg: std_logic_vector(Size-1 downto 0):=ResetValue;
signal se_mux, ce_mux, ue_mux: std_logic_vector(Size-1 downto 0);
begin
-- Basic Combinational Logic
and_ce <= CE and SEL;
and_se <= SE and SEL;
and_ue <= UE and SEL;
internal_si(Size) <= SI;
-- TDR Shift Register Core
SCAN_REGISTER: for i in Size-1 downto 0 generate
-- Multiplexers
se_mux(i) <= internal_si(i+1) when and_se = '1' else cs_reg(i);
ce_mux(i) <= CaptureSource(i) when and_ce = '1' else se_mux(i);
ue_mux(i) <= cs_reg(i) when and_ue = '1' else u_reg(i);
-- Flip-Flops
cs_reg(i) <= ce_mux(i) when TCK'event and TCK = '1';
process(RST,TCK)
begin
if RST = '1' then
u_reg(i) <= ResetValue(Size-1-i);
elsif TCK'event and TCK = '0' then
u_reg(i) <= ue_mux(i);
end if;
end process;
-- Internal Connections
internal_si(i) <= cs_reg(i);
end generate;
-- Outputs
MSBLSB_SO : if BitOrder = "MSBLSB" generate
SO <= internal_si(SOSource);
end generate;
LSBMSB_SO : if BitOrder = "LSBMSB" generate
SO <= internal_si(Size-1-SOSource);
end generate;
ScanRegister_out <= u_reg;
end ScanRegister_arch; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end ScanRegister;
architecture ScanRegister_arch of ScanRegister is
signal and_ce, and_se, and_ue: std_logic;
signal internal_si: std_logic_vector(Size downto 0);
signal cs_reg: std_logic_vector(Size-1 downto 0);
signal u_reg: std_logic_vector(Size-1 downto 0):=ResetValue;
signal se_mux, ce_mux, ue_mux: std_logic_vector(Size-1 downto 0);
begin
-- Basic Combinational Logic
and_ce <= CE and SEL;
and_se <= SE and SEL;
and_ue <= UE and SEL;
internal_si(Size) <= SI;
-- TDR Shift Register Core
SCAN_REGISTER: for i in Size-1 downto 0 generate
-- Multiplexers
se_mux(i) <= internal_si(i+1) when and_se = '1' else cs_reg(i);
ce_mux(i) <= CaptureSource(i) when and_ce = '1' else se_mux(i);
ue_mux(i) <= cs_reg(i) when and_ue = '1' else u_reg(i);
-- Flip-Flops
cs_reg(i) <= ce_mux(i) when TCK'event and TCK = '1';
process(RST,TCK)
begin
if RST = '1' then
u_reg(i) <= ResetValue(Size-1-i);
elsif TCK'event and TCK = '0' then
u_reg(i) <= ue_mux(i);
end if;
end process;
-- Internal Connections
internal_si(i) <= cs_reg(i);
end generate;
-- Outputs
MSBLSB_SO : if BitOrder = "MSBLSB" generate
SO <= internal_si(SOSource);
end generate;
LSBMSB_SO : if BitOrder = "LSBMSB" generate
SO <= internal_si(Size-1-SOSource);
end generate;
ScanRegister_out <= u_reg;
end ScanRegister_arch; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ScanRegister is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end ScanRegister;
architecture ScanRegister_arch of ScanRegister is
signal and_ce, and_se, and_ue: std_logic;
signal internal_si: std_logic_vector(Size downto 0);
signal cs_reg: std_logic_vector(Size-1 downto 0);
signal u_reg: std_logic_vector(Size-1 downto 0):=ResetValue;
signal se_mux, ce_mux, ue_mux: std_logic_vector(Size-1 downto 0);
begin
-- Basic Combinational Logic
and_ce <= CE and SEL;
and_se <= SE and SEL;
and_ue <= UE and SEL;
internal_si(Size) <= SI;
-- TDR Shift Register Core
SCAN_REGISTER: for i in Size-1 downto 0 generate
-- Multiplexers
se_mux(i) <= internal_si(i+1) when and_se = '1' else cs_reg(i);
ce_mux(i) <= CaptureSource(i) when and_ce = '1' else se_mux(i);
ue_mux(i) <= cs_reg(i) when and_ue = '1' else u_reg(i);
-- Flip-Flops
cs_reg(i) <= ce_mux(i) when TCK'event and TCK = '1';
process(RST,TCK)
begin
if RST = '1' then
u_reg(i) <= ResetValue(Size-1-i);
elsif TCK'event and TCK = '0' then
u_reg(i) <= ue_mux(i);
end if;
end process;
-- Internal Connections
internal_si(i) <= cs_reg(i);
end generate;
-- Outputs
MSBLSB_SO : if BitOrder = "MSBLSB" generate
SO <= internal_si(SOSource);
end generate;
LSBMSB_SO : if BitOrder = "LSBMSB" generate
SO <= internal_si(Size-1-SOSource);
end generate;
ScanRegister_out <= u_reg;
end ScanRegister_arch; |
-------------------------------------------------------------------------------
-- Title : AHB2HPI bus bridge
-- Project : LEON3MINI
-------------------------------------------------------------------------------
-- $Id: ahb2hpi.vhd,v 1.23 2005/09/28 14:50:25 tame Mod $
-------------------------------------------------------------------------------
-- Author : Thomas Ameseder
-- Company : Gleichmann Electronics
-- Created : 2005-08-19
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- This module implements an AHB slave that communicates with a
-- Host Peripheral Interface (HPI) device such as the CY7C67300 USB controller.
-- Supports Big Endian and Little Endian.
--
-- Restrictions: Do not use a data width other than 16 at the moment.
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2hpi is
generic (
counter_width : integer := 4;
data_width : integer := 16;
address_width : integer := 2;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#
);
port (
-- AHB port
HCLK : in std_ulogic;
HRESETn : in std_ulogic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
-- HPI port
ADDR : out std_logic_vector(address_width-1 downto 0);
DATA : inout std_logic_vector(data_width-1 downto 0);
nCS : out std_ulogic;
nWR : out std_ulogic;
nRD : out std_ulogic;
INT : in std_ulogic;
-- debug port
dbg_equal : out std_ulogic
);
end ahb2hpi;
architecture rtl of ahb2hpi is
constant CONFIGURATION_VERSION : integer := 0;
constant VERSION : integer := 0;
constant INTERRUPT_NUMBER : integer := 5;
-- register file address is the base address plus the
-- ahb memory space reserved for the device itself
-- its size is 64 bytes as defined with 16#fff# for its
-- mask below
constant REGFILE_ADDRESS : integer := 16#340#;
-- big endian/little endian architecture selection
constant BIG_ENDIAN : boolean := true;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg
(VENDOR_GLEICHMANN, GLEICHMANN_HPI,
CONFIGURATION_VERSION, VERSION, INTERRUPT_NUMBER),
4 => ahb_iobar(haddr, hmask),
5 => ahb_iobar(REGFILE_ADDRESS, 16#fff#),
others => (others => '0'));
type reg_type is
record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(address_width-1 downto 0);
counter : unsigned(counter_width-1 downto 0);
Din : std_logic_vector(data_width-1 downto 0);
Dout : std_logic_vector(data_width-1 downto 0);
nWR, nRD, nCS : std_ulogic;
INT : std_ulogic;
ctrlreg : std_logic_vector(data_width-1 downto 0);
data_acquisition : std_ulogic;
end record;
-- combinatorial, registered and
-- double-registered signals
signal c, r, rr : reg_type;
-- signals for probing input and output data
signal in_data_probe, out_data_probe : std_logic_vector(data_width-1 downto 0);
signal equality_probe : std_ulogic;
-- signal data_acquisition : std_ulogic;
-- keep registers for debug purposes
attribute syn_preserve: boolean;
attribute syn_preserve of in_data_probe, out_data_probe, equality_probe : signal is true;
begin
comb : process (INT, DATA, HRESETn, ahbsi, r, rr)
variable v : reg_type;
-- register fields
variable tAtoCSlow : unsigned(1 downto 0); -- address to chip select (CS) low
variable tCStoCTRLlow : unsigned(1 downto 0); -- CS low to control (read/write) low
variable tCTRLlowDvalid : unsigned(1 downto 0); -- control (read) low to data valid
variable tCTRLlow : unsigned(1 downto 0); -- control low to control high
variable tCTRLhighCShigh : unsigned(1 downto 0); -- control high to CS high
variable tCShighREC : unsigned(1 downto 0); -- CS high to next CS recovery
variable tCNT : unsigned(counter_width-1 downto 0); -- timing counter
begin
-- assign values from the register in the beginning
-- lateron, assign new values by looking at the new
-- inputs from the bus
v := r;
-- data_acquisition <= '0';
if HRESETn = '0' then
v.hwrite := '0';
v.hready := '1';
v.hsel := '0';
v.addr := (others => '-');
v.counter := conv_unsigned(0, counter_width);
v.Din := (others => '-');
v.Dout := (others => '-');
v.nWR := '1';
v.nRD := '1';
v.nCS := '1';
v.INT := '0';
-- bit 12 is reserved for the interrupt
v.ctrlreg(15 downto 13) := (others => '0');
v.ctrlreg(11 downto 0) := (others => '0');
-- v.data_acquisition := '0';
end if;
-- assert data_acquisition for not longer than one cycle
v.data_acquisition := '0';
-- bit 12 of control register holds registered interrupt
v.ctrlreg(12) := INT;
v.INT := INT;
-- assign register fields to signals
tAtoCSlow := (unsigned(r.ctrlreg(11 downto 10)));
tCStoCTRLlow := (unsigned(r.ctrlreg(9 downto 8)));
tCTRLlowDvalid := (unsigned(r.ctrlreg(7 downto 6)));
tCTRLlow := (unsigned(r.ctrlreg(5 downto 4)));
tCTRLhighCShigh := (unsigned(r.ctrlreg(3 downto 2)));
tCShighREC := (unsigned(r.ctrlreg(1 downto 0)));
tCNT := conv_unsigned(conv_unsigned(0, counter_width) + tAtoCSlow + tCStoCTRLlow + tCTRLlow + tCTRLhighCShigh + tCShighREC + '1', counter_width);
-- is bus free to use?
if ahbsi.hready = '1' then
-- gets selected when HSEL signal for the right slave
-- is asserted and the transfer type is SEQ or NONSEQ
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
else
v.hsel := '0';
end if;
-- a valid cycle starts, so all relevant bus signals
-- are registered and the timer is started
if v.hsel = '1' and v.counter = conv_unsigned(0, counter_width) then
v.hwrite := ahbsi.hwrite and v.hsel;
v.hready := '0';
v.counter := conv_unsigned(tCNT, counter_width);
v.nWR := '1'; --not v.hwrite;
v.nRD := '1'; --v.hwrite;
v.nCS := '1';
if (conv_integer(ahbsi.haddr(19 downto 8)) = REGFILE_ADDRESS) then
if ahbsi.haddr(7 downto 0) = X"00" then
-- disable HPI signals, read/write register data
-- and manage AHB handshake
if v.hwrite = '1' then
-- take data from AHB write data bus but skip interrupt bit
if BIG_ENDIAN then
-- v.ctrlreg := ahbsi.hwdata(31 downto 31-data_width+1);
v.ctrlreg(15 downto 13) := ahbsi.hwdata(31 downto 29);
v.ctrlreg(11 downto 0) := ahbsi.hwdata(27 downto 16);
else
-- v.ctrlreg := ahbsi.hwdata(31-data_width downto 0);
v.ctrlreg(15 downto 13) := ahbsi.hwdata(15 downto 13);
v.ctrlreg(11 downto 0) := ahbsi.hwdata(11 downto 0);
end if;
else
v.Din := v.ctrlreg;
end if;
end if;
-- go to last cycle which signals ahb ready
v.counter := conv_unsigned(0, counter_width); --(tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow - tCTRLhighCShigh - tCShighREC);
else
-- the LSB of 16-bit AHB addresses is always zero,
-- so the address is shifted in order to be able
-- to access data with a short* in C
v.addr := ahbsi.haddr(address_width downto 1);
-- v.size := ahbsi.hsize(1 downto 0);
-- fetch input data according to the AMBA specification
-- for big/little endian architectures
-- only relevant for 16-bit accesses
if v.addr(0) = '0' then
if BIG_ENDIAN then
v.Dout := ahbsi.hwdata(31 downto 31-data_width+1);
else
v.Dout := ahbsi.hwdata(31-data_width downto 0);
end if;
else
if BIG_ENDIAN then
v.Dout := ahbsi.hwdata(31-data_width downto 0);
else
v.Dout := ahbsi.hwdata(31 downto 31-data_width+1);
end if;
end if;
end if;
end if;
-- check if counter has just been re-initialized; if so,
-- decrement it until it reaches zero and set control signals
-- accordingly
if v.counter > conv_unsigned(0, counter_width) then
if v.counter = (tCNT - tAtoCSlow) then
v.nCS := '0';
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow) then
v.nWR := not v.hwrite;
v.nRD := v.hwrite;
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlowDvalid) then
if v.nRD = '0' then
v.Din := DATA;
v.data_acquisition := '1';
-- in_data_probe <= DATA;
end if;
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow) then
v.nWR := '1';
v.nRD := '1';
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow - tCTRLhighCShigh) then
v.nCS := '1';
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow
- tCTRLhighCShigh - tCShighREC) then
v.hready := '1';
end if;
-- note: since the counter is queried and immediately
-- decremented afterwards, the value in hardware
-- is one lower than given in the if statement
v.counter := v.counter - 1;
else
v.hready := '1';
end if;
-- assign variable to a signal
c <= v;
-- HPI outputs
ADDR <= r.addr;
nCS <= r.nCS;
nWR <= r.nWR;
nRD <= r.nRD;
-- three-state buffer: drive bus during a write cycle
-- and hold data for one more clock cycle, then
-- shut off from the bus
if ((r.nCS = '0' and r.nWR = '0') or (rr.nCS = '0' and r.nWR = '0') or
(r.nCS = '0' and rr.nWR = '0') or (rr.nCS = '0' and rr.nWR = '0')) then
DATA <= r.Dout;
else
DATA <= (others => 'Z');
end if;
-- output data is assigned to the both the high and the
-- low word of the 32-bit data bus
ahbso.hrdata(31 downto 31-data_width+1) <= r.Din;
ahbso.hrdata(31-data_width downto 0) <= r.Din; --(others => '-');
-- if v.addr(0) = '0' then
-- if BIG_ENDIAN then
-- ahbso.hrdata(31 downto 31-data_width+1) <= r.Din;
-- ahbso.hrdata(31-data_width downto 0) <= (others => '-');
-- else
-- ahbso.hrdata(31 downto 31-data_width+1) <= (others => '-');
-- ahbso.hrdata(31-data_width downto 0) <= r.Din;
-- end if;
-- else
-- if BIG_ENDIAN then
-- ahbso.hrdata(31 downto 31-data_width+1) <= (others => '-');
-- ahbso.hrdata(31-data_width downto 0) <= r.Din;
-- else
-- ahbso.hrdata(31 downto 31-data_width+1) <= r.Din;
-- ahbso.hrdata(31-data_width downto 0) <= (others => '-');
-- end if;
-- end if;
ahbso.hready <= r.hready;
ahbso.hirq <= (INTERRUPT_NUMBER => r.ctrlreg(12), others => '0'); -- propagate registered interrupt
-- ahbso.hirq <= (others => '0');
-- ahbso.hirq(INTERRUPT_NUMBER) <= r.ctrlreg(12);
end process comb;
-- constant AHB outputs
ahbso.hresp <= "00"; -- answer OK by default
ahbso.hsplit <= (others => '0'); -- no SPLIT transactions
ahbso.hcache <= '0'; -- cacheable yes/no
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (HCLK)
begin
if rising_edge(HCLK) then
r <= c;
rr <= r;
end if;
end process;
---------------------------------------------------------------------------------------
-- DEBUG SECTION for triggering on read/write inconsistency
-- use a C program that writes data AND reads it immediately afterwards
-- dbg_equal start with being '0' after reset, then goes high during the transaction
-- it should not have a falling edge during the transactions
-- -> trigger on that event
-- note regarding HPI data transactions:
-- the address is written first before writing/reading at address B"10"
-- the data register is at address B"00"
---------------------------------------------------------------------------------------
-- read at the rising edge of the read signal
-- (before the next read data is received)
-- data_acquisition <= '1' when rr.nrd = '1' and r.nrd = '0' else
-- '0';
-- read data to compare to
in_data_probe <= r.din;
check_data : process (HCLK, HRESETn)
begin
if HRESETn = '0' then
out_data_probe <= (others => '0');
equality_probe <= '0';
elsif rising_edge(HCLK) then
-- is data being written to the *data* register?
if r.nwr = '0' and r.ncs = '0' and r.addr = "00" then
out_data_probe <= r.dout;
end if;
if r.data_acquisition = '1' then
if in_data_probe = out_data_probe then
equality_probe <= '1';
else
equality_probe <= '0';
end if;
end if;
end if;
end process;
dbg_equal <= equality_probe;
-- pragma translate_off
bootmsg : report_version
generic map ("ahb2hpi" & tost(hindex) &
": AHB-to-HPI Bridge, irq " &
tost(INTERRUPT_NUMBER));
-- pragma translate_on
end rtl;
|
-------------------------------------------------------------------------------
-- Title : AHB2HPI bus bridge
-- Project : LEON3MINI
-------------------------------------------------------------------------------
-- $Id: ahb2hpi.vhd,v 1.23 2005/09/28 14:50:25 tame Mod $
-------------------------------------------------------------------------------
-- Author : Thomas Ameseder
-- Company : Gleichmann Electronics
-- Created : 2005-08-19
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- This module implements an AHB slave that communicates with a
-- Host Peripheral Interface (HPI) device such as the CY7C67300 USB controller.
-- Supports Big Endian and Little Endian.
--
-- Restrictions: Do not use a data width other than 16 at the moment.
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2hpi is
generic (
counter_width : integer := 4;
data_width : integer := 16;
address_width : integer := 2;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#
);
port (
-- AHB port
HCLK : in std_ulogic;
HRESETn : in std_ulogic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
-- HPI port
ADDR : out std_logic_vector(address_width-1 downto 0);
DATA : inout std_logic_vector(data_width-1 downto 0);
nCS : out std_ulogic;
nWR : out std_ulogic;
nRD : out std_ulogic;
INT : in std_ulogic;
-- debug port
dbg_equal : out std_ulogic
);
end ahb2hpi;
architecture rtl of ahb2hpi is
constant CONFIGURATION_VERSION : integer := 0;
constant VERSION : integer := 0;
constant INTERRUPT_NUMBER : integer := 5;
-- register file address is the base address plus the
-- ahb memory space reserved for the device itself
-- its size is 64 bytes as defined with 16#fff# for its
-- mask below
constant REGFILE_ADDRESS : integer := 16#340#;
-- big endian/little endian architecture selection
constant BIG_ENDIAN : boolean := true;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg
(VENDOR_GLEICHMANN, GLEICHMANN_HPI,
CONFIGURATION_VERSION, VERSION, INTERRUPT_NUMBER),
4 => ahb_iobar(haddr, hmask),
5 => ahb_iobar(REGFILE_ADDRESS, 16#fff#),
others => (others => '0'));
type reg_type is
record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(address_width-1 downto 0);
counter : unsigned(counter_width-1 downto 0);
Din : std_logic_vector(data_width-1 downto 0);
Dout : std_logic_vector(data_width-1 downto 0);
nWR, nRD, nCS : std_ulogic;
INT : std_ulogic;
ctrlreg : std_logic_vector(data_width-1 downto 0);
data_acquisition : std_ulogic;
end record;
-- combinatorial, registered and
-- double-registered signals
signal c, r, rr : reg_type;
-- signals for probing input and output data
signal in_data_probe, out_data_probe : std_logic_vector(data_width-1 downto 0);
signal equality_probe : std_ulogic;
-- signal data_acquisition : std_ulogic;
-- keep registers for debug purposes
attribute syn_preserve: boolean;
attribute syn_preserve of in_data_probe, out_data_probe, equality_probe : signal is true;
begin
comb : process (INT, DATA, HRESETn, ahbsi, r, rr)
variable v : reg_type;
-- register fields
variable tAtoCSlow : unsigned(1 downto 0); -- address to chip select (CS) low
variable tCStoCTRLlow : unsigned(1 downto 0); -- CS low to control (read/write) low
variable tCTRLlowDvalid : unsigned(1 downto 0); -- control (read) low to data valid
variable tCTRLlow : unsigned(1 downto 0); -- control low to control high
variable tCTRLhighCShigh : unsigned(1 downto 0); -- control high to CS high
variable tCShighREC : unsigned(1 downto 0); -- CS high to next CS recovery
variable tCNT : unsigned(counter_width-1 downto 0); -- timing counter
begin
-- assign values from the register in the beginning
-- lateron, assign new values by looking at the new
-- inputs from the bus
v := r;
-- data_acquisition <= '0';
if HRESETn = '0' then
v.hwrite := '0';
v.hready := '1';
v.hsel := '0';
v.addr := (others => '-');
v.counter := conv_unsigned(0, counter_width);
v.Din := (others => '-');
v.Dout := (others => '-');
v.nWR := '1';
v.nRD := '1';
v.nCS := '1';
v.INT := '0';
-- bit 12 is reserved for the interrupt
v.ctrlreg(15 downto 13) := (others => '0');
v.ctrlreg(11 downto 0) := (others => '0');
-- v.data_acquisition := '0';
end if;
-- assert data_acquisition for not longer than one cycle
v.data_acquisition := '0';
-- bit 12 of control register holds registered interrupt
v.ctrlreg(12) := INT;
v.INT := INT;
-- assign register fields to signals
tAtoCSlow := (unsigned(r.ctrlreg(11 downto 10)));
tCStoCTRLlow := (unsigned(r.ctrlreg(9 downto 8)));
tCTRLlowDvalid := (unsigned(r.ctrlreg(7 downto 6)));
tCTRLlow := (unsigned(r.ctrlreg(5 downto 4)));
tCTRLhighCShigh := (unsigned(r.ctrlreg(3 downto 2)));
tCShighREC := (unsigned(r.ctrlreg(1 downto 0)));
tCNT := conv_unsigned(conv_unsigned(0, counter_width) + tAtoCSlow + tCStoCTRLlow + tCTRLlow + tCTRLhighCShigh + tCShighREC + '1', counter_width);
-- is bus free to use?
if ahbsi.hready = '1' then
-- gets selected when HSEL signal for the right slave
-- is asserted and the transfer type is SEQ or NONSEQ
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
else
v.hsel := '0';
end if;
-- a valid cycle starts, so all relevant bus signals
-- are registered and the timer is started
if v.hsel = '1' and v.counter = conv_unsigned(0, counter_width) then
v.hwrite := ahbsi.hwrite and v.hsel;
v.hready := '0';
v.counter := conv_unsigned(tCNT, counter_width);
v.nWR := '1'; --not v.hwrite;
v.nRD := '1'; --v.hwrite;
v.nCS := '1';
if (conv_integer(ahbsi.haddr(19 downto 8)) = REGFILE_ADDRESS) then
if ahbsi.haddr(7 downto 0) = X"00" then
-- disable HPI signals, read/write register data
-- and manage AHB handshake
if v.hwrite = '1' then
-- take data from AHB write data bus but skip interrupt bit
if BIG_ENDIAN then
-- v.ctrlreg := ahbsi.hwdata(31 downto 31-data_width+1);
v.ctrlreg(15 downto 13) := ahbsi.hwdata(31 downto 29);
v.ctrlreg(11 downto 0) := ahbsi.hwdata(27 downto 16);
else
-- v.ctrlreg := ahbsi.hwdata(31-data_width downto 0);
v.ctrlreg(15 downto 13) := ahbsi.hwdata(15 downto 13);
v.ctrlreg(11 downto 0) := ahbsi.hwdata(11 downto 0);
end if;
else
v.Din := v.ctrlreg;
end if;
end if;
-- go to last cycle which signals ahb ready
v.counter := conv_unsigned(0, counter_width); --(tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow - tCTRLhighCShigh - tCShighREC);
else
-- the LSB of 16-bit AHB addresses is always zero,
-- so the address is shifted in order to be able
-- to access data with a short* in C
v.addr := ahbsi.haddr(address_width downto 1);
-- v.size := ahbsi.hsize(1 downto 0);
-- fetch input data according to the AMBA specification
-- for big/little endian architectures
-- only relevant for 16-bit accesses
if v.addr(0) = '0' then
if BIG_ENDIAN then
v.Dout := ahbsi.hwdata(31 downto 31-data_width+1);
else
v.Dout := ahbsi.hwdata(31-data_width downto 0);
end if;
else
if BIG_ENDIAN then
v.Dout := ahbsi.hwdata(31-data_width downto 0);
else
v.Dout := ahbsi.hwdata(31 downto 31-data_width+1);
end if;
end if;
end if;
end if;
-- check if counter has just been re-initialized; if so,
-- decrement it until it reaches zero and set control signals
-- accordingly
if v.counter > conv_unsigned(0, counter_width) then
if v.counter = (tCNT - tAtoCSlow) then
v.nCS := '0';
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow) then
v.nWR := not v.hwrite;
v.nRD := v.hwrite;
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlowDvalid) then
if v.nRD = '0' then
v.Din := DATA;
v.data_acquisition := '1';
-- in_data_probe <= DATA;
end if;
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow) then
v.nWR := '1';
v.nRD := '1';
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow - tCTRLhighCShigh) then
v.nCS := '1';
end if;
if v.counter = (tCNT - tAtoCSlow - tCStoCTRLlow - tCTRLlow
- tCTRLhighCShigh - tCShighREC) then
v.hready := '1';
end if;
-- note: since the counter is queried and immediately
-- decremented afterwards, the value in hardware
-- is one lower than given in the if statement
v.counter := v.counter - 1;
else
v.hready := '1';
end if;
-- assign variable to a signal
c <= v;
-- HPI outputs
ADDR <= r.addr;
nCS <= r.nCS;
nWR <= r.nWR;
nRD <= r.nRD;
-- three-state buffer: drive bus during a write cycle
-- and hold data for one more clock cycle, then
-- shut off from the bus
if ((r.nCS = '0' and r.nWR = '0') or (rr.nCS = '0' and r.nWR = '0') or
(r.nCS = '0' and rr.nWR = '0') or (rr.nCS = '0' and rr.nWR = '0')) then
DATA <= r.Dout;
else
DATA <= (others => 'Z');
end if;
-- output data is assigned to the both the high and the
-- low word of the 32-bit data bus
ahbso.hrdata(31 downto 31-data_width+1) <= r.Din;
ahbso.hrdata(31-data_width downto 0) <= r.Din; --(others => '-');
-- if v.addr(0) = '0' then
-- if BIG_ENDIAN then
-- ahbso.hrdata(31 downto 31-data_width+1) <= r.Din;
-- ahbso.hrdata(31-data_width downto 0) <= (others => '-');
-- else
-- ahbso.hrdata(31 downto 31-data_width+1) <= (others => '-');
-- ahbso.hrdata(31-data_width downto 0) <= r.Din;
-- end if;
-- else
-- if BIG_ENDIAN then
-- ahbso.hrdata(31 downto 31-data_width+1) <= (others => '-');
-- ahbso.hrdata(31-data_width downto 0) <= r.Din;
-- else
-- ahbso.hrdata(31 downto 31-data_width+1) <= r.Din;
-- ahbso.hrdata(31-data_width downto 0) <= (others => '-');
-- end if;
-- end if;
ahbso.hready <= r.hready;
ahbso.hirq <= (INTERRUPT_NUMBER => r.ctrlreg(12), others => '0'); -- propagate registered interrupt
-- ahbso.hirq <= (others => '0');
-- ahbso.hirq(INTERRUPT_NUMBER) <= r.ctrlreg(12);
end process comb;
-- constant AHB outputs
ahbso.hresp <= "00"; -- answer OK by default
ahbso.hsplit <= (others => '0'); -- no SPLIT transactions
ahbso.hcache <= '0'; -- cacheable yes/no
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (HCLK)
begin
if rising_edge(HCLK) then
r <= c;
rr <= r;
end if;
end process;
---------------------------------------------------------------------------------------
-- DEBUG SECTION for triggering on read/write inconsistency
-- use a C program that writes data AND reads it immediately afterwards
-- dbg_equal start with being '0' after reset, then goes high during the transaction
-- it should not have a falling edge during the transactions
-- -> trigger on that event
-- note regarding HPI data transactions:
-- the address is written first before writing/reading at address B"10"
-- the data register is at address B"00"
---------------------------------------------------------------------------------------
-- read at the rising edge of the read signal
-- (before the next read data is received)
-- data_acquisition <= '1' when rr.nrd = '1' and r.nrd = '0' else
-- '0';
-- read data to compare to
in_data_probe <= r.din;
check_data : process (HCLK, HRESETn)
begin
if HRESETn = '0' then
out_data_probe <= (others => '0');
equality_probe <= '0';
elsif rising_edge(HCLK) then
-- is data being written to the *data* register?
if r.nwr = '0' and r.ncs = '0' and r.addr = "00" then
out_data_probe <= r.dout;
end if;
if r.data_acquisition = '1' then
if in_data_probe = out_data_probe then
equality_probe <= '1';
else
equality_probe <= '0';
end if;
end if;
end if;
end process;
dbg_equal <= equality_probe;
-- pragma translate_off
bootmsg : report_version
generic map ("ahb2hpi" & tost(hindex) &
": AHB-to-HPI Bridge, irq " &
tost(INTERRUPT_NUMBER));
-- pragma translate_on
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_splitter is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS:natural := 6
);
port (
number_in: in std_logic_vector(TOTAL_BITS-1 downto 0);
sign_out: out std_logic;
exp_out: out std_logic_vector(EXP_BITS-1 downto 0);
mant_out: out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0)
);
end;
architecture number_splitter_arq of number_splitter is
begin
process(number_in)
begin
sign_out <= number_in(TOTAL_BITS-1);
exp_out <= number_in(TOTAL_BITS-2 downto TOTAL_BITS-1-EXP_BITS);
mant_out <= number_in(TOTAL_BITS-EXP_BITS-2 downto 0);
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : BPM Mixer
-- Project :
-------------------------------------------------------------------------------
-- File : mixer.vhd
-- Author : Gustavo BM Bruno
-- Company : LNLS - CNPEM
-- Created : 2014-01-21
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Mixer at input stage for BPM
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-01-21 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.dsp_cores_pkg.all;
use work.bpm_cores_pkg.all;
entity mixer is
generic(
g_sin_file : string := "./dds_sin.nif";
g_cos_file : string := "./dds_cos.nif";
g_number_of_points : natural := 6;
g_input_width : natural := 16;
g_dds_width : natural := 16;
g_output_width : natural := 32;
g_tag_width : natural := 1; -- Input data tag width
g_mult_levels : natural := 7
);
port(
rst_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
signal_i : in std_logic_vector(g_input_width-1 downto 0);
valid_i : in std_logic;
tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
I_out : out std_logic_vector(g_output_width-1 downto 0);
I_tag_out : out std_logic_vector(g_tag_width-1 downto 0);
Q_out : out std_logic_vector(g_output_width-1 downto 0);
Q_tag_out : out std_logic_vector(g_tag_width-1 downto 0);
valid_o : out std_logic);
end entity mixer;
architecture rtl of mixer is
signal sine : std_logic_vector(g_dds_width-1 downto 0);
signal cosine : std_logic_vector(g_dds_width-1 downto 0);
signal dds_valid : std_logic;
signal I_valid_out : std_logic;
signal Q_valid_out : std_logic;
begin
cmp_dds : fixed_dds
generic map (
g_number_of_points => g_number_of_points,
g_output_width => g_dds_width,
g_sin_file => g_sin_file,
g_cos_file => g_cos_file)
port map (
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
valid_i => valid_i,
sin_o => sine,
cos_o => cosine,
valid_o => dds_valid);
cmp_mult_I : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_dds_width,
g_tag_width => g_tag_width,
g_signed => true,
g_p_width => g_output_width,
g_round_convergent => 1)
port map (
a_i => signal_i,
b_i => cosine,
tag_i => tag_i,
valid_i => dds_valid,
p_o => I_out,
valid_o => I_valid_out,
tag_o => I_tag_out,
ce_i => ce_i,
clk_i => clk_i,
rst_i => rst_i);
cmp_mult_Q : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_dds_width,
g_tag_width => g_tag_width,
g_signed => true,
g_p_width => g_output_width,
g_round_convergent => 1)
port map (
a_i => signal_i,
b_i => sine,
tag_i => tag_i,
valid_i => dds_valid,
p_o => Q_out,
valid_o => Q_valid_out,
tag_o => Q_tag_out,
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i);
-- Any valid, either from I or Q is fine.
valid_o <= I_valid_out;
end rtl;
|
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- local ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a > b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk, reset)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
elsif rising_edge(clk) then
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end process;
end Behavioral;
|
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- local ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a > b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk, reset)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
elsif rising_edge(clk) then
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end process;
end Behavioral;
|
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- local ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a > b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk, reset)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
elsif rising_edge(clk) then
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end process;
end Behavioral;
|
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- local ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a > b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk, reset)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
elsif rising_edge(clk) then
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2989.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s05b00x00p06n01i02989pkg is
constant c1 : INTEGER;
function f return INTEGER;
procedure p(x : inout INTEGER);
end c02s05b00x00p06n01i02989pkg;
package body c02s05b00x00p06n01i02989pkg is
constant c1 : INTEGER := 10;
constant c2 : INTEGER := 20;
function f return INTEGER is
begin
return c1 + c2;
end;
procedure p( x: inout INTEGER) is
begin
x := c1 + c2;
end;
end c02s05b00x00p06n01i02989pkg;
ENTITY c02s05b00x00p06n01i02989ent IS
END c02s05b00x00p06n01i02989ent;
ARCHITECTURE c02s05b00x00p06n01i02989arch OF c02s05b00x00p06n01i02989ent IS
signal s1 : INTEGER := WORK.c02s05b00x00p06n01i02989pkg.c1;
signal s2 : INTEGER := WORK.c02s05b00x00p06n01i02989pkg.c1;
BEGIN
TESTING: PROCESS
variable temp : INTEGER;
BEGIN
s1 <= WORK.c02s05b00x00p06n01i02989pkg.F;
WORK.c02s05b00x00p06n01i02989pkg.P(temp);
s2 <= temp;
wait for 5 ns;
assert NOT( s1 = 30 and s2 = 30 )
report "***PASSED TEST: c02s05b00x00p06n01i02989"
severity NOTE;
assert ( s1 = 30 and s2 = 30 )
report "***FAILED TEST: c02s05b00x00p06n01i02989 - Package declaration visibility test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s05b00x00p06n01i02989arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2989.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s05b00x00p06n01i02989pkg is
constant c1 : INTEGER;
function f return INTEGER;
procedure p(x : inout INTEGER);
end c02s05b00x00p06n01i02989pkg;
package body c02s05b00x00p06n01i02989pkg is
constant c1 : INTEGER := 10;
constant c2 : INTEGER := 20;
function f return INTEGER is
begin
return c1 + c2;
end;
procedure p( x: inout INTEGER) is
begin
x := c1 + c2;
end;
end c02s05b00x00p06n01i02989pkg;
ENTITY c02s05b00x00p06n01i02989ent IS
END c02s05b00x00p06n01i02989ent;
ARCHITECTURE c02s05b00x00p06n01i02989arch OF c02s05b00x00p06n01i02989ent IS
signal s1 : INTEGER := WORK.c02s05b00x00p06n01i02989pkg.c1;
signal s2 : INTEGER := WORK.c02s05b00x00p06n01i02989pkg.c1;
BEGIN
TESTING: PROCESS
variable temp : INTEGER;
BEGIN
s1 <= WORK.c02s05b00x00p06n01i02989pkg.F;
WORK.c02s05b00x00p06n01i02989pkg.P(temp);
s2 <= temp;
wait for 5 ns;
assert NOT( s1 = 30 and s2 = 30 )
report "***PASSED TEST: c02s05b00x00p06n01i02989"
severity NOTE;
assert ( s1 = 30 and s2 = 30 )
report "***FAILED TEST: c02s05b00x00p06n01i02989 - Package declaration visibility test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s05b00x00p06n01i02989arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2989.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s05b00x00p06n01i02989pkg is
constant c1 : INTEGER;
function f return INTEGER;
procedure p(x : inout INTEGER);
end c02s05b00x00p06n01i02989pkg;
package body c02s05b00x00p06n01i02989pkg is
constant c1 : INTEGER := 10;
constant c2 : INTEGER := 20;
function f return INTEGER is
begin
return c1 + c2;
end;
procedure p( x: inout INTEGER) is
begin
x := c1 + c2;
end;
end c02s05b00x00p06n01i02989pkg;
ENTITY c02s05b00x00p06n01i02989ent IS
END c02s05b00x00p06n01i02989ent;
ARCHITECTURE c02s05b00x00p06n01i02989arch OF c02s05b00x00p06n01i02989ent IS
signal s1 : INTEGER := WORK.c02s05b00x00p06n01i02989pkg.c1;
signal s2 : INTEGER := WORK.c02s05b00x00p06n01i02989pkg.c1;
BEGIN
TESTING: PROCESS
variable temp : INTEGER;
BEGIN
s1 <= WORK.c02s05b00x00p06n01i02989pkg.F;
WORK.c02s05b00x00p06n01i02989pkg.P(temp);
s2 <= temp;
wait for 5 ns;
assert NOT( s1 = 30 and s2 = 30 )
report "***PASSED TEST: c02s05b00x00p06n01i02989"
severity NOTE;
assert ( s1 = 30 and s2 = 30 )
report "***FAILED TEST: c02s05b00x00p06n01i02989 - Package declaration visibility test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s05b00x00p06n01i02989arch;
|
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
-- Failures below
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2055.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02055ent IS
END c07s02b04x00p01n01i02055ent;
ARCHITECTURE c07s02b04x00p01n01i02055arch OF c07s02b04x00p01n01i02055ent IS
BEGIN
TESTING: PROCESS
type MEMORY is array(INTEGER range <>) of BIT;
type ADDRESS is access MEMORY;
variable ADDRESSV: ADDRESS;
BEGIN
ADDRESSV := ADDRESSV + NULL;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02055 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02055arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2055.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02055ent IS
END c07s02b04x00p01n01i02055ent;
ARCHITECTURE c07s02b04x00p01n01i02055arch OF c07s02b04x00p01n01i02055ent IS
BEGIN
TESTING: PROCESS
type MEMORY is array(INTEGER range <>) of BIT;
type ADDRESS is access MEMORY;
variable ADDRESSV: ADDRESS;
BEGIN
ADDRESSV := ADDRESSV + NULL;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02055 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02055arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2055.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02055ent IS
END c07s02b04x00p01n01i02055ent;
ARCHITECTURE c07s02b04x00p01n01i02055arch OF c07s02b04x00p01n01i02055ent IS
BEGIN
TESTING: PROCESS
type MEMORY is array(INTEGER range <>) of BIT;
type ADDRESS is access MEMORY;
variable ADDRESSV: ADDRESS;
BEGIN
ADDRESSV := ADDRESSV + NULL;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02055 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02055arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:12 09/26/2017
-- Design Name:
-- Module Name: firstrpart - arqfirstrpart
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity firstrpart is
Port ( Resetext : in STD_LOGIC;
Clkinext : in STD_LOGIC;
Adressext : out STD_LOGIC_VECTOR (31 downto 0));
end firstrpart;
architecture arqfirstrpart of firstrpart is
COMPONENT Sumador32bit
PORT(
Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Result : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT NPC
PORT(
inNPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outNPC : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT PC
PORT(
inPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outPC : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT IM
PORT(
Address : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT CU
PORT(
Instruction : in STD_LOGIC_VECTOR (31 downto 0);
ALUOP : out STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT SEU
PORT(
Instruction : in STD_LOGIC_VECTOR (31 downto 0);
OUTSEU : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT MUX32
PORT(
SEUIMM : in STD_LOGIC_VECTOR (31 downto 0);
CRS2 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : out STD_LOGIC_VECTOR (31 downto 0);
Instruction : in STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT ALU
PORT(
OPER1 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : in STD_LOGIC_VECTOR (31 downto 0);
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
dwr : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
signal aux1,aux2,aux3,aux4,aux6,aux7,aux8,aux9,aux10: std_logic_vector(31 downto 0);
signal aux5: std_logic_vector(5 downto 0);
begin
U0: NPC PORT MAP(
inNPC => aux1,
Reset => Resetext,
Clk => Clkinext,
outNPC => aux2
);
U1: PC PORT MAP(
inPC => aux2,
Reset => Resetext,
Clk => Clkinext,
outPC => aux3
);
U2: Sumador32bit PORT MAP(
Oper1 => aux3,
Result => aux1
);
U3: IM PORT MAP(
Address => aux3,
Reset => Resetext,
Instruction => aux4
);
U4: CU PORT MAP(
Instruction => aux4,
ALUOP => aux5
);
U5: SEU PORT MAP(
Instruction =>aux4,
OUTSEU =>aux6
);
U6: MUX32 PORT MAP(
SEUIMM => aux6,
CRS2 => aux7,
OPER2 => aux9,
Instruction => aux4
);
U7: ALU PORT MAP(
OPER1 => aux8,
OPER2 => aux9,
ALURESULT => aux10,
ALUOP => aux5
);
U8: RF PORT MAP(
rs1 => aux4(18 downto 14),
rs2 => aux4(4 downto 0),
rd => aux4(29 downto 25),
dwr => aux10,
rst => Resetext,
crs1 => aux8,
crs2 => aux7
);
Adressext<=aux10;
end arqfirstrpart;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1532.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p09n02i01532ent IS
END c08s09b00x00p09n02i01532ent;
ARCHITECTURE c08s09b00x00p09n02i01532arch OF c08s09b00x00p09n02i01532ent IS
BEGIN
TESTING: PROCESS
BEGIN
--
-- Loop must have discrete parameters
--
L1: for c in 1.2 to 2.54 loop -- parameters must be discrete
null;
end loop L1;
assert FALSE
report "***FAILED TEST: c08s09b00x00p09n02i01532 - Loop parameters must be discrete."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p09n02i01532arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1532.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p09n02i01532ent IS
END c08s09b00x00p09n02i01532ent;
ARCHITECTURE c08s09b00x00p09n02i01532arch OF c08s09b00x00p09n02i01532ent IS
BEGIN
TESTING: PROCESS
BEGIN
--
-- Loop must have discrete parameters
--
L1: for c in 1.2 to 2.54 loop -- parameters must be discrete
null;
end loop L1;
assert FALSE
report "***FAILED TEST: c08s09b00x00p09n02i01532 - Loop parameters must be discrete."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p09n02i01532arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1532.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p09n02i01532ent IS
END c08s09b00x00p09n02i01532ent;
ARCHITECTURE c08s09b00x00p09n02i01532arch OF c08s09b00x00p09n02i01532ent IS
BEGIN
TESTING: PROCESS
BEGIN
--
-- Loop must have discrete parameters
--
L1: for c in 1.2 to 2.54 loop -- parameters must be discrete
null;
end loop L1;
assert FALSE
report "***FAILED TEST: c08s09b00x00p09n02i01532 - Loop parameters must be discrete."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p09n02i01532arch;
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_INST_na.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_INST_na IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_INST_na;
ARCHITECTURE SYN OF ram_dq_inst_na IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_na",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "N_na"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_na"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_INST_na.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_INST_na IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_INST_na;
ARCHITECTURE SYN OF ram_dq_inst_na IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_na",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "N_na"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_na"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_na_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
spw_rxd : in std_logic_vector(0 to 1);
spw_rxs : in std_logic_vector(0 to 1);
spw_txd : out std_logic_vector(0 to 1);
spw_txs : out std_logic_vector(0 to 1)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal resetnl, clk2x, spw_clkl : std_logic;
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
constant IOAEN : integer := 0;
constant sysfreq : integer := (CFG_CLKMUL*40000/CFG_CLKDIV);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, sysfreq)
port map (lclk, pci_lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech)
port map (sdclk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, resetnl);
rst0 : rstgen -- reset generator
port map (resetnl, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mctrl2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 8, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(8));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(8) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 8)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#, irq => 4,
ioaddr => 16#400#, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, irq => 4)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 0)-- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => sysfreq/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw_clkl <= clk2x;
spw : if CFG_SPW_EN > 0 generate
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, rmap => CFG_SPW_RMAP,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT,
netlist => CFG_SPW_NETLIST, ports => 1, dmachan => CFG_SPW_DMACHAN,
spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME, rxunaligned => CFG_SPW_RXUNAL)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(2*sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad generic map (padtech)
port map (spw_rxd(i), dtmp(i));
spw_rxs_pad : inpad generic map (padtech)
port map (spw_rxs(i), stmp(i));
spw_txd_pad : outpad generic map (padtech)
port map (spw_txd(i), spwo(i).d(0));
spw_txs_pad : outpad generic map (padtech)
port map (spw_txs(i), spwo(i).s(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-PCI-XC2V3000 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity zeroReg is
port(
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0)
);
end zeroReg;
architecture bhv of zeroReg is
begin
process(clk, rst)
begin
if rst = '1' then
output <= (others => '0');
elsif (clk = '1' and clk'event) then
if (en = '1') then
output <= input;
end if;
end if;
end process;
end bhv;
|
entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2) := ( 6, 7 );
assert v(2 to 3) = ( 7, 4 );
wait for 1 ns;
x <= ( 1, 2, 3, 4 );
x(1 to 2) <= ( 6, 7 );
assert x(2 to 3) = ( 7, 4 );
wait for 1 ns;
u := ( 1, 2, 3, 4);
u(4 downto 3) := ( 6, 7 );
assert u(3 downto 2) = ( 7, 4 );
wait;
end process;
end architecture;
|
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