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-- DDS Frequency Synthesizer
--
-- Output frequency is f=ftw_i/2^ftw_width*fclk
-- Output initial phase is phi=phase_i/2^phase_width*2*pi
--
-- Copyright (C) 2009 Martin Kumm
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
use work.sine_lut_pkg.all;
package dds_synthesizer_pkg is
component dds_synthesizer
generic(
ftw_width : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
ftw_i : in std_logic_vector(ftw_width-1 downto 0);
phase_i : in std_logic_vector(PHASE_WIDTH-1 downto 0);
phase_o : out std_logic_vector(PHASE_WIDTH-1 downto 0);
ampl_o : out std_logic_vector(AMPL_WIDTH-1 downto 0)
);
end component;
end dds_synthesizer_pkg;
package body dds_synthesizer_pkg is
end dds_synthesizer_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
use work.sine_lut_pkg.all;
entity dds_synthesizer is
generic(
ftw_width : integer := 32
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
ftw_i : in std_logic_vector(ftw_width-1 downto 0);
phase_i : in std_logic_vector(PHASE_WIDTH-1 downto 0);
phase_o : out std_logic_vector(PHASE_WIDTH-1 downto 0);
ampl_o : out std_logic_vector(AMPL_WIDTH-1 downto 0)
);
end dds_synthesizer;
architecture dds_synthesizer_arch of dds_synthesizer is
signal ftw_accu : std_logic_vector(ftw_width-1 downto 0);
signal phase : std_logic_vector(PHASE_WIDTH-1 downto 0);
signal lut_in : std_logic_vector(PHASE_WIDTH-3 downto 0);
signal lut_out : std_logic_vector(AMPL_WIDTH-1 downto 0);
signal lut_out_delay : std_logic_vector(AMPL_WIDTH-1 downto 0);
signal lut_out_inv_delay : std_logic_vector(AMPL_WIDTH-1 downto 0);
signal quadrant_2_or_4 : std_logic;
signal quadrant_3_or_4 : std_logic;
signal quadrant_3_or_4_delay : std_logic;
signal quadrant_3_or_4_2delay : std_logic;
begin
phase_o <= phase;
quadrant_2_or_4 <= phase(PHASE_WIDTH-2);
quadrant_3_or_4 <= phase(PHASE_WIDTH-1);
lut_in <= phase(PHASE_WIDTH-3 downto 0) when quadrant_2_or_4 = '0' else conv_std_logic_vector(2**(PHASE_WIDTH-2)-conv_integer(phase(PHASE_WIDTH-3 downto 0)), PHASE_WIDTH-2);
ampl_o <= lut_out_delay when quadrant_3_or_4_2delay = '0' else lut_out_inv_delay;
process (clk_i, rst_i)
begin
if rst_i = '1' then
ftw_accu <= (others => '0');
phase <= (others => '0');
elsif clk_i'event and clk_i = '1' then
ftw_accu <= conv_std_logic_vector(conv_integer(ftw_accu) + conv_integer(ftw_i), ftw_width);
phase <= conv_std_logic_vector(conv_integer(ftw_accu(ftw_width-1 downto ftw_width-PHASE_WIDTH)) + conv_integer(phase_i), PHASE_WIDTH);
if quadrant_2_or_4 = '1' and phase(PHASE_WIDTH - 3 downto 0) = conv_std_logic_vector (0, PHASE_WIDTH - 2) then
lut_out <= conv_std_logic_vector(2**(AMPL_WIDTH - 1) - 1, AMPL_WIDTH);
else
lut_out <= sine_lut(conv_integer(lut_in));
end if;
quadrant_3_or_4_delay <= quadrant_3_or_4;
quadrant_3_or_4_2delay <= quadrant_3_or_4_delay;
lut_out_inv_delay <= conv_std_logic_vector(-1*conv_integer(lut_out), AMPL_WIDTH);
lut_out_delay <= lut_out;
end if;
end process;
end dds_synthesizer_arch;
|
-- $Id: fifo_simple_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fifo_simple_dram - syn
-- Description: FIFO, CE/WE interface, distributed RAM based
--
-- Dependencies: ram_1swar_gen
--
-- Test bench: tb/tb_fifo_simple_dram
-- Target Devices: generic Spartan, Artix
-- Tool versions: ise 14.7; viv 2017.2-2018.3; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-09 1109 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.memlib.all;
entity fifo_simple_dram is -- fifo, CE/WE interface, dram based
generic (
AWIDTH : positive := 6; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE : in slbit; -- clock enable
WE : in slbit; -- write enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
EMPTY : out slbit; -- fifo empty status
FULL : out slbit; -- fifo full status
SIZE : out slv(AWIDTH-1 downto 0) -- number of used slots
);
end fifo_simple_dram;
architecture syn of fifo_simple_dram is
type regs_type is record
waddr : slv(AWIDTH-1 downto 0); -- write address
raddr : slv(AWIDTH-1 downto 0); -- read address
empty : slbit; -- empty flag
full : slbit; -- full flag
end record regs_type;
constant memsize : positive := 2**AWIDTH;
constant regs_init : regs_type := (
slv(to_unsigned(0,AWIDTH)), -- waddr
slv(to_unsigned(0,AWIDTH)), -- raddr
'1','0' -- empty,full
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal RAM_WE : slbit := '0';
signal RAM_ADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
RAM : ram_1swar_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLK,
WE => RAM_WE,
ADDR => RAM_ADDR,
DI => DI,
DO => DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RESET, CE, WE)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iram_we : slbit := '0';
variable iram_addr : slv(AWIDTH-1 downto 0) := (others=>'0');
variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
iram_we := '0';
if WE = '1' then -- select RAM address
iram_addr := r.waddr; -- for write
else
iram_addr := r.raddr; -- for read
end if;
isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
if CE = '1' then -- do read or write
if WE = '1' then -- do write
if r.full = '0' then -- only if not full
iram_we := '1'; -- assert write enable
n.waddr := slv(unsigned(r.waddr) + 1); -- advance address
n.empty := '0'; -- can't be empty after write
if unsigned(isize) = memsize-2 then -- check for full
n.full := '1';
end if;
end if;
else -- do read
if r.empty = '0' then -- only if not empty
n.raddr := slv(unsigned(r.raddr) + 1); -- advance address
n.full := '0'; -- can't be full after read
if unsigned(isize) = 1 then -- check for empty
n.empty := '1';
end if;
end if;
end if;
end if;
N_REGS <= n;
RAM_ADDR <= iram_addr;
RAM_WE <= iram_we;
EMPTY <= r.empty;
FULL <= r.full;
SIZE <= isize;
end process proc_next;
-- synthesis translate_off
proc_moni: process (CLK)
variable oline : line;
begin
if rising_edge(CLK) then
if RESET='0' and CE='1' then -- not in reset and active
if WE = '0' then
if R_REGS.empty='1' then -- read on empty fifo
write(oline, now, right, 12);
write(oline, string'(" read on empty fifo - FAIL in "));
write(oline, fifo_simple_dram'path_name);
writeline(output, oline);
end if;
else
if R_REGS.full='1' then -- write on full fifo
write(oline, now, right, 12);
write(oline, string'(" write on full fifo - FAIL in "));
write(oline, fifo_simple_dram'path_name);
writeline(output, oline);
end if;
end if;
end if;
end if;
end process proc_moni;
-- synthesis translate_on
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity my_gpio_v1_0_S00_AXI is
generic (
-- Users to add parameters here
gpio_size : natural := 8;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
pad : inout std_logic_vector(gpio_size-1 downto 0);
irq : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end my_gpio_v1_0_S00_AXI;
architecture arch_imp of my_gpio_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal reg_pad_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --pad_out register
signal reg_pad_rw_n :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --read write_n register
signal reg_pad_en :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --pad_en register
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --inutilizzato
signal reg_im :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --interrupt mask register
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --inutilizzato
signal reg_ack :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --interrupt ack register
signal reg_gie :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); --global interrupt register
signal status_register :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); -- interrupt status register
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
component gpio_array is
generic(gpio_size : natural := gpio_size);
Port ( pad_out : in STD_LOGIC_VECTOR (gpio_size-1 downto 0);
pad_rw_n : in STD_LOGIC_VECTOR (gpio_size-1 downto 0);
pad_en : in STD_LOGIC_VECTOR (gpio_size-1 downto 0);
pad_in : out STD_LOGIC_VECTOR (gpio_size-1 downto 0);
pad : inout STD_LOGIC_VECTOR (gpio_size-1 downto 0));
end component;
signal periph_pad_in : std_logic_vector(gpio_size-1 downto 0):=(others=>'0');
signal pad_intr_temp : std_logic_vector(gpio_size-1 downto 0):=(others=>'0');
signal new_intr : std_logic_vector(gpio_size-1 downto 0):=(others=>'0');
signal one_bit_status : std_logic:='0';
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
reg_pad_out <= (others => '0');
reg_pad_rw_n <= (others => '0');
reg_pad_en <= (others => '0');
slv_reg3 <= (others => '0');
reg_im <= (others => '0');
slv_reg5 <= (others => '0');
reg_ack <= (others => '0');
reg_gie <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
reg_ack <= (others => '0');
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
reg_pad_out(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
reg_pad_rw_n(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
reg_pad_en(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3 (not used)
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
reg_im(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5 (not used)
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
reg_ack(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
reg_gie(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
reg_pad_out <= reg_pad_out;
reg_pad_rw_n <= reg_pad_rw_n;
reg_pad_en <= reg_pad_en;
slv_reg3 <= slv_reg3;
reg_im <= reg_im;
slv_reg5 <= slv_reg5;
reg_ack <= (others=>'0');
reg_gie <= reg_gie;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (reg_pad_out, reg_pad_rw_n, reg_pad_en, periph_pad_in, reg_im, status_register, reg_ack, reg_gie, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000" =>
reg_data_out <= reg_pad_out;
when b"001" =>
reg_data_out <= reg_pad_rw_n;
when b"010" =>
reg_data_out <= reg_pad_en;
when b"011" =>
--reg_data_out <= slv_reg3;
reg_data_out <= (others => '0');
reg_data_out(gpio_size-1 downto 0) <= periph_pad_in;
when b"100" =>
reg_data_out <= reg_im;
when b"101" =>
--reg_data_out <= slv_reg5
reg_data_out <= (others=>'0');
reg_data_out(gpio_size-1 downto 0) <= status_register(gpio_size-1 downto 0);
when b"110" =>
reg_data_out <= reg_ack;
when b"111" =>
reg_data_out <= reg_gie;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
--istanza gpio
GPIO_ARRAY_INST: gpio_array port map(
pad_out => reg_pad_out(gpio_size-1 downto 0),
pad_rw_n => reg_pad_rw_n(gpio_size-1 downto 0),
pad_en => reg_pad_en(gpio_size-1 downto 0),
pad_in => periph_pad_in,
pad => pad);
--Implementazione della logica di interrupt
--il segnale di interrupt deve essere ottenuto solo mediante una and bit a bit tra il segnale in ingresso (pad) e il registro delle interrupt mascherate (reg_im),
--inoltre poiché un interrupt è desiderabile solo se esso avviene mediante una periferica di input è necessario eseguire un'altra and bit a bit col registro di
--read_write_n (reg_pad_rw_n)
pad_intr_temp <= (pad and reg_im(gpio_size-1 downto 0)) and reg_pad_rw_n(gpio_size-1 downto 0);
--il segnale di output (irq) è alto se esiste almeno una interrupt pendente e la global interrupt è attiva (reg_gie)
irq <= or_reduce(status_register(gpio_size-1 downto 0)) and reg_gie(0);
--logica di scrittura all'interno dello statur register:
--se vi è almeno un bit alto di ack (reg_ack) allora si pulisce tutto il registro di stato, se invece non è arrivato alcun ack ma la global interrupt è attiva,
--allora voglio salvare nello status ulteriori bit di pending altrimenti voglio tener memoria del valore precedente.
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
status_register <= (others => '0');
else
if(or_reduce(reg_ack(gpio_size-1 downto 0))='1')then
status_register(gpio_size-1 downto 0) <= status_register(gpio_size-1 downto 0) xor (reg_ack(gpio_size-1 downto 0)and status_register(gpio_size-1 downto 0));
else
if(reg_gie(0)='1')then
new_intr <= pad_intr_temp;
else
new_intr <= (others => '0');
end if;
status_register(gpio_size-1 downto 0) <= status_register(gpio_size -1 downto 0) or new_intr;
end if;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 09:14:00 09/15/2015
-- Design Name:
-- Module Name: SN74Ls42 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: A SN74LS42 desription
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SN74Ls42 is
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (9 downto 0));
end SN74Ls42;
architecture Behavioral of SN74Ls42 is
signal input: STD_LOGIC_VECTOR(3 downto 0);
begin
-- just in case the user is configuring bad the Constrains
-- in other case we could use a vector.
input <= D & C & B & A;
with input select
output <= "1111111110" when "0000", --0
"1111111101" when "0001", --1
"1111111011" when "0010", --2
"1111110111" when "0011", --3
"1111101111" when "0100", --4
"1111011111" when "0101", --5
"1110111111" when "0110", --6
"1101111111" when "0111", --7
"1011111111" when "1000", --8
"0111111111" when "1001", --9
"1111111111" when others;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1842.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01842ent IS
type small_int is range 0 to 7;
END c07s01b00x00p08n01i01842ent;
ARCHITECTURE c07s01b00x00p08n01i01842arch OF c07s01b00x00p08n01i01842ent IS
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
assert s_int > TESTING -- process label illegal here
report "process label accepted as primary in a condition."
severity note ;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01842 - Process lables are not permitted as primaries in a condition expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01842arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1842.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01842ent IS
type small_int is range 0 to 7;
END c07s01b00x00p08n01i01842ent;
ARCHITECTURE c07s01b00x00p08n01i01842arch OF c07s01b00x00p08n01i01842ent IS
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
assert s_int > TESTING -- process label illegal here
report "process label accepted as primary in a condition."
severity note ;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01842 - Process lables are not permitted as primaries in a condition expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01842arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1842.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01842ent IS
type small_int is range 0 to 7;
END c07s01b00x00p08n01i01842ent;
ARCHITECTURE c07s01b00x00p08n01i01842arch OF c07s01b00x00p08n01i01842ent IS
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
assert s_int > TESTING -- process label illegal here
report "process label accepted as primary in a condition."
severity note ;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01842 - Process lables are not permitted as primaries in a condition expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01842arch;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ram_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END ram_exdes;
ARCHITECTURE xilinx OF ram_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT ram IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : ram
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
package pkg is
-- function identifier return integer;
procedure identifier;
alias identifier_alias_fun is identifier[return integer];
-- alias identifier_alias_proc is identifier[];
end package;
|
package pkg is
-- function identifier return integer;
procedure identifier;
alias identifier_alias_fun is identifier[return integer];
-- alias identifier_alias_proc is identifier[];
end package;
|
package pkg is
-- function identifier return integer;
procedure identifier;
alias identifier_alias_fun is identifier[return integer];
-- alias identifier_alias_proc is identifier[];
end package;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out std_logic_vector(7 downto 0);
CS : in std_logic;
CLK : in std_logic
-- SCL : in std_logic;
-- SDA : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= std_logic_vector( pb_buf ) when CS = '1' else (others => 'Z');
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out std_logic_vector(7 downto 0);
CS : in std_logic;
CLK : in std_logic
-- SCL : in std_logic;
-- SDA : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= std_logic_vector( pb_buf ) when CS = '1' else (others => 'Z');
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out std_logic_vector(7 downto 0);
CS : in std_logic;
CLK : in std_logic
-- SCL : in std_logic;
-- SDA : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= std_logic_vector( pb_buf ) when CS = '1' else (others => 'Z');
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out std_logic_vector(7 downto 0);
CS : in std_logic;
CLK : in std_logic
-- SCL : in std_logic;
-- SDA : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= std_logic_vector( pb_buf ) when CS = '1' else (others => 'Z');
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out std_logic_vector(7 downto 0);
CS : in std_logic;
CLK : in std_logic
-- SCL : in std_logic;
-- SDA : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= std_logic_vector( pb_buf ) when CS = '1' else (others => 'Z');
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
end if;
end process dpUCECHO;
end RTL;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out std_logic_vector(7 downto 0);
CS : in std_logic;
CLK : in std_logic
-- SCL : in std_logic;
-- SDA : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= std_logic_vector( pb_buf ) when CS = '1' else (others => 'Z');
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
end if;
end process dpUCECHO;
end RTL;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 09:10:21 09/04/2015
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: 14.7
-- Description: Implementation of a Arithmetic Logic Unit
-- Pedroni's book page 76
-- Dependencies: Nope
--
-- Revision: 1.0
-- Revision 0.01 - File Created
-- Additional Comments: Divide and conquer using KISS principle
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_unsigned.all;
entity ALU is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
cin : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Behavioral of ALU is
--embbeded signals
-- Result from Logic Unit
signal res_LU : STD_LOGIC_VECTOR (7 downto 0);
-- Result from Arithmetic Unit
signal res_AU : STD_LOGIC_VECTOR (7 downto 0);
begin
ArithmeticUnit: process(a, b, cin, sel)
VARIABLE bufer: STD_LOGIC_VECTOR (2 downto 0);
begin
bufer := sel(0) & sel(1) & sel(2);
case bufer is
when "000" =>
res_AU <= a;
when "001" =>
res_AU <= a + x"01";
when "010" =>
res_AU <= a - x"01";
when "011" =>
res_AU <= b;
when "100" =>
res_AU <= b + x"01";
when "101" =>
res_AU <= b - x"01";
when "110" =>
res_AU <= a + b;
when others =>
res_AU <= a + b + cin;
end case;
end process ArithmeticUnit;
LogicUnit: process(a, b, sel)
VARIABLE bufer: STD_LOGIC_VECTOR (2 downto 0);
begin
bufer := sel(0) & sel(1) & sel(2);
case bufer is
when "000" =>
res_LU <= not a;
when "001" =>
res_LU <= not b;
when "010" =>
res_LU <= a and b;
when "011" =>
res_LU <= a or b;
when "100" =>
res_LU <= a nand b;
when "101" =>
res_LU <= a nor b;
when "110" =>
res_LU <= a xor b;
when others =>
res_LU <= a xnor b;
end case;
end process LogicUnit;
-- Multiplexor
y <= res_AU when sel(3) = '0' else
res_LU;
end Behavioral;
|
--Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Company: LCR
-- Engineer: Emmanuel Bello
--
-- Create Date: 16:44:33 10/24/2013
-- Design Name:
-- Module Name: rom_coe - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.RetinaParameters.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rom_coe is
port(
clk: in std_logic;
address: in std_logic_vector(N_GAUSS_KERNEL_BW-1 downto 0);
data_out: out std_logic_vector(KERNEL_ROM_BW-1 downto 0)
);
end rom_coe;
architecture Behavioral of rom_coe is
type rom_coe_type is array (NUMBER_OF_KERNELS-1 downto 0) of std_logic_vector (KERNEL_ROM_BW-1 downto 0);
constant rom_coe_data : rom_coe_type :=
(
0 => ("0000101001000001010010000010100010000101000000001001110"),
1 => ("0000111011000001110110000011101000000111000000001101011"),
2 => ("0001001100100010011000000100100100001000101000000000000"),
3 => ("0001101011100011010010000110000110000000000000000000000"),
4 => ("0010110000000101010000000000000000000000000000000000000"),
5 => ("0010110110000101001010000000000000000000000000000000000"),
6 => ("1000000000000000000000000000000000000000000000000000000"),
7 => ("0000111010000001110100000011100110000111000100001101111"),
8 => ("0001001011000010010101000100100100001000111000000000000"),
9 => ("0001101001000011001111000110010000000000000000000000000"),
10 => ("0010101101100101010011000000000000000000000000000000000"),
11 => ("0010110000000101010000000000000000000000000000000000000"),
12 => ("0010110110000101001010000000000000000000000000000000000"),
13 => ("1000000000000000000000000000000000000000000000000000000"),
14 => ("0001001010000010010100000100100100001001000000000000000"),
15 => ("0001001011000010010101000100100100001000111000000000000"),
16 => ("0001101001000011001111000110010000000000000000000000000"),
17 => ("0010101101100101010011000000000000000000000000000000000"),
18 => ("0010110000000101010000000000000000000000000000000000000"),
19 => ("1000000000000000000000000000000000000000000000000000000"),
20 => ("1000000000000000000000000000000000000000000000000000000")
);
begin
rom: process(clk)
begin
if rising_edge(clk) then
data_out <=rom_coe_data(to_integer(resize(unsigned(address),N_GAUSS_KERNEL_BW)));
-- data_out <=rom_coe_data(0);
end if;
end process rom;
end architecture Behavioral;
|
-- file: dcm50MHz.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.143______0.000______50.0______598.860____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________27____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm50MHz is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end dcm50MHz;
architecture xilinx of dcm50MHz is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm50MHz,clk_wiz_v3_6,{component_name=dcm50MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=37.037,clkin2_period=37.037,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 7,
CLKFX_MULTIPLY => 13,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 37.037,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => RESET,
-- Unused pin, tie low
DSSEN => '0');
LOCKED <= locked_internal;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkfx);
end xilinx;
|
-- ipif_monitor.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ipif_monitor is
generic (
DWIDTH : integer := 32
);
port (
CLK : in std_logic;
RST : in std_logic;
IP2Bus_Data : in std_logic_vector(DWIDTH - 1 downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic;
IPIF_BUSY : in std_logic;
IPIF_READ : in std_logic;
IPIF_DONE : out std_logic
);
end entity;
architecture full of ipif_monitor is
signal ack_active : std_logic;
begin
ack_active <= IP2Bus_WrAck or IP2Bus_RdAck;
IPIF_DONE <= ack_active;
assert (ack_active = '1' and IP2Bus_Error = '0') or ack_active = '0'
report "Error is asserted durning Ack"
severity warning;
checkp : process(CLK, RST)
begin
if rising_edge(CLK) then
if RST = '0' then
if IP2Bus_WrAck = '1' then
assert IPIF_BUSY = '1'
report "WrAck asserted when no transaction is active"
severity failure;
assert IPIF_READ = '0'
report "Invalid acknowladge, expected RdAck"
severity failure;
end if;
if IP2Bus_RdAck = '1' then
assert IPIF_BUSY = '1'
report "RdAck asserted when no transaction is active"
severity failure;
assert IPIF_READ = '1'
report "Invalid acknowladge, expected WrAck"
severity failure;
end if;
if IP2Bus_WrAck = IP2Bus_RdAck and ack_active = '1' then
assert false
report "WrAck and RdAck are asserted at once"
severity failure;
end if;
end if;
end if;
end process;
writep : process(CLK, RST, IP2Bus_RdAck, IP2Bus_Error, IP2Bus_Data)
variable i : integer := 0;
begin
if rising_edge(CLK) then
if RST = '0' then
if IP2Bus_RdAck = '1' and IP2Bus_Error = '0' then
report "Data (OK): "
& integer'image(conv_integer(IP2Bus_Data(31 downto 16))) & " "
& integer'image(conv_integer(IP2Bus_Data(15 downto 0)));
elsif IP2Bus_RdAck = '1' and IP2Bus_Error = '1' then
report "Data (ER): "
& integer'image(conv_integer(IP2Bus_Data(31 downto 16))) & " "
& integer'image(conv_integer(IP2Bus_Data(15 downto 0)));
end if;
end if;
end if;
end process;
end architecture;
|
-----------------------------------------------------------------------------
-- Simple UART with 1 byte buffer and without hardware flowcontrol.
-- by Joerg Bornschein ([email protected])
--
-- divisor parametrizes the baundrate:
--
-- divisor = 50 MHz / 115200 Baud = 434
-- divisor = 32 MHz / 115200 Baud = 278
--
-- All files under GPLv2
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------
-- UART ---------------------------------------------------------------------
entity uart is
generic (
divisor : integer := 278 );
port (
clk : in std_logic;
reset : in std_logic;
--
txdata : in std_logic_vector(7 downto 0);
rxdata : out std_logic_vector(7 downto 0);
wr : in std_logic;
rd : in std_logic;
tx_avail : out std_logic;
tx_busy : out std_logic;
rx_avail : out std_logic;
rx_full : out std_logic;
rx_error : out std_logic;
--
uart_rxd : in std_logic;
uart_txd : out std_logic );
end uart;
-----------------------------------------------------------------------------
-- implementation -----------------------------------------------------------
architecture rtl of uart is
-----------------------------------------------------------------------------
-- component declarations ---------------------------------------------------
component uart_rx is
generic (
fullbit : integer );
port (
clk : in std_logic;
reset : in std_logic;
--
dout : out std_logic_vector(7 downto 0);
avail : out std_logic;
error : out std_logic;
clear : in std_logic;
--
rxd : in std_logic );
end component;
component uart_tx is
generic (
fullbit : integer );
port (
clk : in std_logic;
reset : in std_logic;
--
din : in std_logic_vector(7 downto 0);
wr : in std_logic;
busy : out std_logic;
--
txd : out std_logic );
end component;
-----------------------------------------------------------------------------
-- local signals ------------------------------------------------------------
signal utx_busy : std_logic;
signal utx_wr : std_logic;
signal urx_dout : std_logic_vector(7 downto 0);
signal urx_avail : std_logic;
signal urx_clear : std_logic;
signal urx_error : std_logic;
signal txbuf : std_logic_vector(7 downto 0);
signal txbuf_full : std_logic;
signal rxbuf : std_logic_vector(7 downto 0);
signal rxbuf_full : std_logic;
begin
iotxproc: process(clk, reset) is
begin
if reset='1' then
utx_wr <= '0';
txbuf_full <= '0';
urx_clear <= '0';
rxbuf_full <= '0';
elsif clk'event and clk='1' then
-- TX Buffer Logic
if wr='1' then
txbuf <= txdata;
txbuf_full <= '1';
end if;
if txbuf_full='1' and utx_busy='0' then
utx_wr <= '1';
txbuf_full <= '0';
else
utx_wr <= '0';
end if;
-- RX Buffer Logic
if rd='1' then
rxbuf_full <= '0';
end if;
if urx_avail='1' and rxbuf_full='0' then
rxbuf <= urx_dout;
rxbuf_full <= '1';
urx_clear <= '1';
else
urx_clear <= '0';
end if;
end if;
end process;
uart_rx0: uart_rx
generic map (
fullbit => divisor )
port map (
clk => clk,
reset => reset,
--
dout => urx_dout,
avail => urx_avail,
error => urx_error,
clear => urx_clear,
--
rxd => uart_rxd );
uart_tx0: uart_tx
generic map (
fullbit => divisor )
port map (
clk => clk,
reset => reset,
--
din => txbuf,
wr => utx_wr,
busy => utx_busy,
--
txd => uart_txd );
rxdata <= rxbuf;
rx_avail <= rxbuf_full and not rd;
rx_full <= rxbuf_full and urx_avail and not rd;
rx_error <= urx_error;
tx_busy <= utx_busy or txbuf_full or wr;
tx_avail <= not txbuf_full;
end rtl;
|
-----------------------------------------------------------------------------
-- Simple UART with 1 byte buffer and without hardware flowcontrol.
-- by Joerg Bornschein ([email protected])
--
-- divisor parametrizes the baundrate:
--
-- divisor = 50 MHz / 115200 Baud = 434
-- divisor = 32 MHz / 115200 Baud = 278
--
-- All files under GPLv2
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------
-- UART ---------------------------------------------------------------------
entity uart is
generic (
divisor : integer := 278 );
port (
clk : in std_logic;
reset : in std_logic;
--
txdata : in std_logic_vector(7 downto 0);
rxdata : out std_logic_vector(7 downto 0);
wr : in std_logic;
rd : in std_logic;
tx_avail : out std_logic;
tx_busy : out std_logic;
rx_avail : out std_logic;
rx_full : out std_logic;
rx_error : out std_logic;
--
uart_rxd : in std_logic;
uart_txd : out std_logic );
end uart;
-----------------------------------------------------------------------------
-- implementation -----------------------------------------------------------
architecture rtl of uart is
-----------------------------------------------------------------------------
-- component declarations ---------------------------------------------------
component uart_rx is
generic (
fullbit : integer );
port (
clk : in std_logic;
reset : in std_logic;
--
dout : out std_logic_vector(7 downto 0);
avail : out std_logic;
error : out std_logic;
clear : in std_logic;
--
rxd : in std_logic );
end component;
component uart_tx is
generic (
fullbit : integer );
port (
clk : in std_logic;
reset : in std_logic;
--
din : in std_logic_vector(7 downto 0);
wr : in std_logic;
busy : out std_logic;
--
txd : out std_logic );
end component;
-----------------------------------------------------------------------------
-- local signals ------------------------------------------------------------
signal utx_busy : std_logic;
signal utx_wr : std_logic;
signal urx_dout : std_logic_vector(7 downto 0);
signal urx_avail : std_logic;
signal urx_clear : std_logic;
signal urx_error : std_logic;
signal txbuf : std_logic_vector(7 downto 0);
signal txbuf_full : std_logic;
signal rxbuf : std_logic_vector(7 downto 0);
signal rxbuf_full : std_logic;
begin
iotxproc: process(clk, reset) is
begin
if reset='1' then
utx_wr <= '0';
txbuf_full <= '0';
urx_clear <= '0';
rxbuf_full <= '0';
elsif clk'event and clk='1' then
-- TX Buffer Logic
if wr='1' then
txbuf <= txdata;
txbuf_full <= '1';
end if;
if txbuf_full='1' and utx_busy='0' then
utx_wr <= '1';
txbuf_full <= '0';
else
utx_wr <= '0';
end if;
-- RX Buffer Logic
if rd='1' then
rxbuf_full <= '0';
end if;
if urx_avail='1' and rxbuf_full='0' then
rxbuf <= urx_dout;
rxbuf_full <= '1';
urx_clear <= '1';
else
urx_clear <= '0';
end if;
end if;
end process;
uart_rx0: uart_rx
generic map (
fullbit => divisor )
port map (
clk => clk,
reset => reset,
--
dout => urx_dout,
avail => urx_avail,
error => urx_error,
clear => urx_clear,
--
rxd => uart_rxd );
uart_tx0: uart_tx
generic map (
fullbit => divisor )
port map (
clk => clk,
reset => reset,
--
din => txbuf,
wr => utx_wr,
busy => utx_busy,
--
txd => uart_txd );
rxdata <= rxbuf;
rx_avail <= rxbuf_full and not rd;
rx_full <= rxbuf_full and urx_avail and not rd;
rx_error <= urx_error;
tx_busy <= utx_busy or txbuf_full or wr;
tx_avail <= not txbuf_full;
end rtl;
|
-------------------------------------------------------------------------------
-- axi_vdma_genlock_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_genlock_mngr.vhd
--
-- Description: This entity encompasses the Gen Lock Manager
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_vdma_genlock_mngr is
generic(
C_GENLOCK_MODE : integer range 0 to 3 := 0 ;
-- Specifies Gen-Lock Mode of operation
-- 0 = Master - Channel configured to be Gen-Lock Master
-- 1 = Slave - Channel configured to be Gen-Lock Slave
C_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1 ;
-- Number of Gen-Lock masters capable of controlling Gen-Lock Slave
C_INTERNAL_GENLOCK_ENABLE : integer range 0 to 1 := 0 ;
-- Enable internal genlock bus
-- 0 = disable internal genlock bus
-- 1 = enable internal genlock bus
C_NUM_FSTORES : integer range 1 to 32 := 5
-- Number of Frame Stores
);
port (
-- Secondary Clock Domain
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- Dynamic Frame Store Support --
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
num_fstore_minus1 : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Gen-Lock Slave Signals --
mstr_in_control : in std_logic_vector(3 downto 0) ; --
genlock_select : in std_logic ; --
frame_ptr_in : in std_logic_vector --
((C_GENLOCK_NUM_MASTERS --
*NUM_FRM_STORE_WIDTH)-1 downto 0) ; --
internal_frame_ptr_in : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
slv_frame_ref_out : out std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
fsize_mismatch_err_flag : in std_logic ;
--
-- Gen-Lock Master Signals --
dmasr_halt : in std_logic ; --
circular_prk_mode : in std_logic ; --
mstr_frame_update : in std_logic ; --
mstr_frame_ref_in : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
mstrfrm_tstsync_out : out std_logic ; --
frame_ptr_out : out std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) --
);
end axi_vdma_genlock_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_genlock_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Zero vector for tying off unused inputs
constant ZERO_VALUE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
-- Number of bits to analyze for grey code enconding and decoding
constant GREY_NUM_BITS : integer := max2(1,clog2(C_NUM_FSTORES));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Slave only signals
signal grey_frame_ptr : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal grey_frmstr_adjusted : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal partial_frame_ptr : std_logic_vector(GREY_NUM_BITS-1 downto 0) := (others => '0');
signal padded_partial_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
-- Master and Slave signals
signal s_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal ds_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal dm_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal rvc_frame_ref_in : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal dm_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal ds_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal reg_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal grey_frame_ptr_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s_frame_ptr_out : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal num_fstore_equal_one : std_logic := '0';
signal dm_mstr_reverse_order : std_logic := '0';
signal dm_mstr_reverse_order_d1 : std_logic := '0';
signal s_mstr_reverse_order : std_logic := '0';
signal ds_mstr_reverse_order : std_logic := '0';
signal s_mstr_reverse_order_d1 : std_logic := '0';
signal ds_mstr_reverse_order_d1 : std_logic := '0';
signal mstr_reverse_order : std_logic := '0';
signal mstr_reverse_order_d1 : std_logic := '0';
signal mstr_reverse_order_d2 : std_logic := '0';
-- Test signals
signal mstrfrm_tstsync_d1 : std_logic := '0';
signal mstrfrm_tstsync_d2 : std_logic := '0';
signal mstrfrm_tstsync_d3 : std_logic := '0';
signal mstrfrm_tstsync_d4 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Number of fstore value set in register is 0x01.
num_fstore_equal_one <= '1' when num_fstore_minus1 = ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0)
else '0';
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for slave
-------------------------------------------------------------------------------
GENLOCK_FOR_SLAVE : if C_GENLOCK_MODE = 1 generate
begin
-----------------------------------------------------------------------------------------------------------------------------------
--Output GenLock Slave's working frame number in grey
-----------------------------------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
-------------------------------------------------------------------------------------------------------------------
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
S_GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
S_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= '0';
s_inv_raw_frame_ptr(2) <= '0';
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= '0';
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
s_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
s_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process S_PARTIAL_NOT_P2;
-- Register to break long timing paths
S_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s_binary_frame_ptr <= (others => '0');
else
s_binary_frame_ptr <= s_inv_raw_frame_ptr;
end if;
end if;
end process S_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
s_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
s_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
s_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
S_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s_mstr_reverse_order_d1 <= '1';
else
s_mstr_reverse_order_d1 <= s_mstr_reverse_order;
end if;
end if;
end process S_REG_DELAY_FLAG;
FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(s_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(s_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= s_binary_frame_ptr;
end if;
end if;
end process FRAME_CONVERT_P3;
mstrfrm_tstsync_out <= '0'; -- Not used for slaves
end generate GENLOCK_FOR_SLAVE;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for master
-------------------------------------------------------------------------------
GENLOCK_FOR_MASTER : if C_GENLOCK_MODE = 0 generate
begin
-- Only used for slave mode
slv_frame_ref_out <= (others => '0');
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate GENLOCK_FOR_MASTER;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for master
-------------------------------------------------------------------------------
DYNAMIC_GENLOCK_FOR_MASTER : if C_GENLOCK_MODE = 2 generate
begin
----------------------------------------------------------------------------------------------------------
--un-greying Dynamic slave's (internal or external) frame number
----------------------------------------------------------------------------------------------------------
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
DM_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= '0';
dm_inv_raw_frame_ptr(2) <= '0';
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= '0';
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
dm_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
dm_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process DM_PARTIAL_NOT_P2;
-- Register to break long timing paths
DM_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dm_binary_frame_ptr <= (others => '0');
else
dm_binary_frame_ptr <= dm_inv_raw_frame_ptr;
end if;
end if;
end process DM_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
DM_REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
dm_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
dm_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
dm_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
dm_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
dm_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
dm_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process DM_REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
DM_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dm_mstr_reverse_order_d1 <= '1';
else
dm_mstr_reverse_order_d1 <= dm_mstr_reverse_order;
end if;
end if;
end process DM_REG_DELAY_FLAG;
DM_FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(dm_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(dm_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= dm_binary_frame_ptr;
end if;
end if;
end process DM_FRAME_CONVERT_P3;
-----------------------------------------------------------------------------------------------------------
--grey frame number out for dynamic genlock master
-----------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate DYNAMIC_GENLOCK_FOR_MASTER;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for Dynamic slave
-------------------------------------------------------------------------------
DYNAMIC_GENLOCK_FOR_SLAVE : if C_GENLOCK_MODE = 3 generate
begin
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
DS_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= '0';
ds_inv_raw_frame_ptr(2) <= '0';
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= '0';
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
ds_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
ds_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process DS_PARTIAL_NOT_P2;
-- Register to break long timing paths
DS_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ds_binary_frame_ptr <= (others => '0');
else
ds_binary_frame_ptr <= ds_inv_raw_frame_ptr;
end if;
end if;
end process DS_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
DS_REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
ds_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
ds_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
ds_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
ds_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
ds_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
ds_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process DS_REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
DS_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ds_mstr_reverse_order_d1 <= '1';
else
ds_mstr_reverse_order_d1 <= ds_mstr_reverse_order;
end if;
end if;
end process DS_REG_DELAY_FLAG;
DS_FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(ds_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(ds_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= ds_binary_frame_ptr;
end if;
end if;
end process DS_FRAME_CONVERT_P3;
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
--Output Dynamic GenLock Slave's working frame number in grey
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
DS2_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process DS2_REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate DYNAMIC_GENLOCK_FOR_SLAVE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_genlock_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_genlock_mngr.vhd
--
-- Description: This entity encompasses the Gen Lock Manager
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_vdma_genlock_mngr is
generic(
C_GENLOCK_MODE : integer range 0 to 3 := 0 ;
-- Specifies Gen-Lock Mode of operation
-- 0 = Master - Channel configured to be Gen-Lock Master
-- 1 = Slave - Channel configured to be Gen-Lock Slave
C_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1 ;
-- Number of Gen-Lock masters capable of controlling Gen-Lock Slave
C_INTERNAL_GENLOCK_ENABLE : integer range 0 to 1 := 0 ;
-- Enable internal genlock bus
-- 0 = disable internal genlock bus
-- 1 = enable internal genlock bus
C_NUM_FSTORES : integer range 1 to 32 := 5
-- Number of Frame Stores
);
port (
-- Secondary Clock Domain
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- Dynamic Frame Store Support --
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
num_fstore_minus1 : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Gen-Lock Slave Signals --
mstr_in_control : in std_logic_vector(3 downto 0) ; --
genlock_select : in std_logic ; --
frame_ptr_in : in std_logic_vector --
((C_GENLOCK_NUM_MASTERS --
*NUM_FRM_STORE_WIDTH)-1 downto 0) ; --
internal_frame_ptr_in : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
slv_frame_ref_out : out std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
fsize_mismatch_err_flag : in std_logic ;
--
-- Gen-Lock Master Signals --
dmasr_halt : in std_logic ; --
circular_prk_mode : in std_logic ; --
mstr_frame_update : in std_logic ; --
mstr_frame_ref_in : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
mstrfrm_tstsync_out : out std_logic ; --
frame_ptr_out : out std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) --
);
end axi_vdma_genlock_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_genlock_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Zero vector for tying off unused inputs
constant ZERO_VALUE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
-- Number of bits to analyze for grey code enconding and decoding
constant GREY_NUM_BITS : integer := max2(1,clog2(C_NUM_FSTORES));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Slave only signals
signal grey_frame_ptr : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal grey_frmstr_adjusted : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal partial_frame_ptr : std_logic_vector(GREY_NUM_BITS-1 downto 0) := (others => '0');
signal padded_partial_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
-- Master and Slave signals
signal s_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal ds_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal dm_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal rvc_frame_ref_in : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal dm_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal ds_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal reg_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal grey_frame_ptr_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s_frame_ptr_out : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal num_fstore_equal_one : std_logic := '0';
signal dm_mstr_reverse_order : std_logic := '0';
signal dm_mstr_reverse_order_d1 : std_logic := '0';
signal s_mstr_reverse_order : std_logic := '0';
signal ds_mstr_reverse_order : std_logic := '0';
signal s_mstr_reverse_order_d1 : std_logic := '0';
signal ds_mstr_reverse_order_d1 : std_logic := '0';
signal mstr_reverse_order : std_logic := '0';
signal mstr_reverse_order_d1 : std_logic := '0';
signal mstr_reverse_order_d2 : std_logic := '0';
-- Test signals
signal mstrfrm_tstsync_d1 : std_logic := '0';
signal mstrfrm_tstsync_d2 : std_logic := '0';
signal mstrfrm_tstsync_d3 : std_logic := '0';
signal mstrfrm_tstsync_d4 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Number of fstore value set in register is 0x01.
num_fstore_equal_one <= '1' when num_fstore_minus1 = ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0)
else '0';
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for slave
-------------------------------------------------------------------------------
GENLOCK_FOR_SLAVE : if C_GENLOCK_MODE = 1 generate
begin
-----------------------------------------------------------------------------------------------------------------------------------
--Output GenLock Slave's working frame number in grey
-----------------------------------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
-------------------------------------------------------------------------------------------------------------------
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
S_GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
S_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= '0';
s_inv_raw_frame_ptr(2) <= '0';
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= '0';
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
s_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
s_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process S_PARTIAL_NOT_P2;
-- Register to break long timing paths
S_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s_binary_frame_ptr <= (others => '0');
else
s_binary_frame_ptr <= s_inv_raw_frame_ptr;
end if;
end if;
end process S_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
s_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
s_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
s_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
S_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s_mstr_reverse_order_d1 <= '1';
else
s_mstr_reverse_order_d1 <= s_mstr_reverse_order;
end if;
end if;
end process S_REG_DELAY_FLAG;
FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(s_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(s_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= s_binary_frame_ptr;
end if;
end if;
end process FRAME_CONVERT_P3;
mstrfrm_tstsync_out <= '0'; -- Not used for slaves
end generate GENLOCK_FOR_SLAVE;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for master
-------------------------------------------------------------------------------
GENLOCK_FOR_MASTER : if C_GENLOCK_MODE = 0 generate
begin
-- Only used for slave mode
slv_frame_ref_out <= (others => '0');
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate GENLOCK_FOR_MASTER;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for master
-------------------------------------------------------------------------------
DYNAMIC_GENLOCK_FOR_MASTER : if C_GENLOCK_MODE = 2 generate
begin
----------------------------------------------------------------------------------------------------------
--un-greying Dynamic slave's (internal or external) frame number
----------------------------------------------------------------------------------------------------------
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
DM_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= '0';
dm_inv_raw_frame_ptr(2) <= '0';
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= '0';
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
dm_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
dm_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process DM_PARTIAL_NOT_P2;
-- Register to break long timing paths
DM_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dm_binary_frame_ptr <= (others => '0');
else
dm_binary_frame_ptr <= dm_inv_raw_frame_ptr;
end if;
end if;
end process DM_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
DM_REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
dm_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
dm_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
dm_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
dm_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
dm_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
dm_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process DM_REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
DM_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dm_mstr_reverse_order_d1 <= '1';
else
dm_mstr_reverse_order_d1 <= dm_mstr_reverse_order;
end if;
end if;
end process DM_REG_DELAY_FLAG;
DM_FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(dm_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(dm_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= dm_binary_frame_ptr;
end if;
end if;
end process DM_FRAME_CONVERT_P3;
-----------------------------------------------------------------------------------------------------------
--grey frame number out for dynamic genlock master
-----------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate DYNAMIC_GENLOCK_FOR_MASTER;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for Dynamic slave
-------------------------------------------------------------------------------
DYNAMIC_GENLOCK_FOR_SLAVE : if C_GENLOCK_MODE = 3 generate
begin
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
DS_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= '0';
ds_inv_raw_frame_ptr(2) <= '0';
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= '0';
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
ds_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
ds_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process DS_PARTIAL_NOT_P2;
-- Register to break long timing paths
DS_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ds_binary_frame_ptr <= (others => '0');
else
ds_binary_frame_ptr <= ds_inv_raw_frame_ptr;
end if;
end if;
end process DS_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
DS_REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
ds_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
ds_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
ds_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
ds_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
ds_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
ds_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process DS_REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
DS_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ds_mstr_reverse_order_d1 <= '1';
else
ds_mstr_reverse_order_d1 <= ds_mstr_reverse_order;
end if;
end if;
end process DS_REG_DELAY_FLAG;
DS_FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(ds_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(ds_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= ds_binary_frame_ptr;
end if;
end if;
end process DS_FRAME_CONVERT_P3;
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
--Output Dynamic GenLock Slave's working frame number in grey
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
DS2_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process DS2_REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate DYNAMIC_GENLOCK_FOR_SLAVE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_genlock_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_genlock_mngr.vhd
--
-- Description: This entity encompasses the Gen Lock Manager
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_vdma_genlock_mngr is
generic(
C_GENLOCK_MODE : integer range 0 to 3 := 0 ;
-- Specifies Gen-Lock Mode of operation
-- 0 = Master - Channel configured to be Gen-Lock Master
-- 1 = Slave - Channel configured to be Gen-Lock Slave
C_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1 ;
-- Number of Gen-Lock masters capable of controlling Gen-Lock Slave
C_INTERNAL_GENLOCK_ENABLE : integer range 0 to 1 := 0 ;
-- Enable internal genlock bus
-- 0 = disable internal genlock bus
-- 1 = enable internal genlock bus
C_NUM_FSTORES : integer range 1 to 32 := 5
-- Number of Frame Stores
);
port (
-- Secondary Clock Domain
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- Dynamic Frame Store Support --
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
num_fstore_minus1 : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Gen-Lock Slave Signals --
mstr_in_control : in std_logic_vector(3 downto 0) ; --
genlock_select : in std_logic ; --
frame_ptr_in : in std_logic_vector --
((C_GENLOCK_NUM_MASTERS --
*NUM_FRM_STORE_WIDTH)-1 downto 0) ; --
internal_frame_ptr_in : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
slv_frame_ref_out : out std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
fsize_mismatch_err_flag : in std_logic ;
--
-- Gen-Lock Master Signals --
dmasr_halt : in std_logic ; --
circular_prk_mode : in std_logic ; --
mstr_frame_update : in std_logic ; --
mstr_frame_ref_in : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
mstrfrm_tstsync_out : out std_logic ; --
frame_ptr_out : out std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) --
);
end axi_vdma_genlock_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_genlock_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Zero vector for tying off unused inputs
constant ZERO_VALUE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
-- Number of bits to analyze for grey code enconding and decoding
constant GREY_NUM_BITS : integer := max2(1,clog2(C_NUM_FSTORES));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Slave only signals
signal grey_frame_ptr : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal grey_frmstr_adjusted : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal partial_frame_ptr : std_logic_vector(GREY_NUM_BITS-1 downto 0) := (others => '0');
signal padded_partial_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
-- Master and Slave signals
signal s_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal ds_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal dm_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal rvc_frame_ref_in : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal dm_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal ds_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal reg_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal grey_frame_ptr_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s_frame_ptr_out : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal num_fstore_equal_one : std_logic := '0';
signal dm_mstr_reverse_order : std_logic := '0';
signal dm_mstr_reverse_order_d1 : std_logic := '0';
signal s_mstr_reverse_order : std_logic := '0';
signal ds_mstr_reverse_order : std_logic := '0';
signal s_mstr_reverse_order_d1 : std_logic := '0';
signal ds_mstr_reverse_order_d1 : std_logic := '0';
signal mstr_reverse_order : std_logic := '0';
signal mstr_reverse_order_d1 : std_logic := '0';
signal mstr_reverse_order_d2 : std_logic := '0';
-- Test signals
signal mstrfrm_tstsync_d1 : std_logic := '0';
signal mstrfrm_tstsync_d2 : std_logic := '0';
signal mstrfrm_tstsync_d3 : std_logic := '0';
signal mstrfrm_tstsync_d4 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Number of fstore value set in register is 0x01.
num_fstore_equal_one <= '1' when num_fstore_minus1 = ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0)
else '0';
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for slave
-------------------------------------------------------------------------------
GENLOCK_FOR_SLAVE : if C_GENLOCK_MODE = 1 generate
begin
-----------------------------------------------------------------------------------------------------------------------------------
--Output GenLock Slave's working frame number in grey
-----------------------------------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
-------------------------------------------------------------------------------------------------------------------
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
S_GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
S_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= '0';
s_inv_raw_frame_ptr(2) <= '0';
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= '0';
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
s_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
s_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process S_PARTIAL_NOT_P2;
-- Register to break long timing paths
S_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s_binary_frame_ptr <= (others => '0');
else
s_binary_frame_ptr <= s_inv_raw_frame_ptr;
end if;
end if;
end process S_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
s_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
s_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
s_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
S_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s_mstr_reverse_order_d1 <= '1';
else
s_mstr_reverse_order_d1 <= s_mstr_reverse_order;
end if;
end if;
end process S_REG_DELAY_FLAG;
FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(s_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(s_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= s_binary_frame_ptr;
end if;
end if;
end process FRAME_CONVERT_P3;
mstrfrm_tstsync_out <= '0'; -- Not used for slaves
end generate GENLOCK_FOR_SLAVE;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for master
-------------------------------------------------------------------------------
GENLOCK_FOR_MASTER : if C_GENLOCK_MODE = 0 generate
begin
-- Only used for slave mode
slv_frame_ref_out <= (others => '0');
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate GENLOCK_FOR_MASTER;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for master
-------------------------------------------------------------------------------
DYNAMIC_GENLOCK_FOR_MASTER : if C_GENLOCK_MODE = 2 generate
begin
----------------------------------------------------------------------------------------------------------
--un-greying Dynamic slave's (internal or external) frame number
----------------------------------------------------------------------------------------------------------
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
DM_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= '0';
dm_inv_raw_frame_ptr(2) <= '0';
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= '0';
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
dm_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
dm_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process DM_PARTIAL_NOT_P2;
-- Register to break long timing paths
DM_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dm_binary_frame_ptr <= (others => '0');
else
dm_binary_frame_ptr <= dm_inv_raw_frame_ptr;
end if;
end if;
end process DM_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
DM_REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
dm_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
dm_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
dm_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
dm_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
dm_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
dm_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process DM_REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
DM_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dm_mstr_reverse_order_d1 <= '1';
else
dm_mstr_reverse_order_d1 <= dm_mstr_reverse_order;
end if;
end if;
end process DM_REG_DELAY_FLAG;
DM_FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(dm_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(dm_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= dm_binary_frame_ptr;
end if;
end if;
end process DM_FRAME_CONVERT_P3;
-----------------------------------------------------------------------------------------------------------
--grey frame number out for dynamic genlock master
-----------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate DYNAMIC_GENLOCK_FOR_MASTER;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for Dynamic slave
-------------------------------------------------------------------------------
DYNAMIC_GENLOCK_FOR_SLAVE : if C_GENLOCK_MODE = 3 generate
begin
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
DS_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= '0';
ds_inv_raw_frame_ptr(2) <= '0';
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= '0';
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
ds_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
ds_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process DS_PARTIAL_NOT_P2;
-- Register to break long timing paths
DS_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ds_binary_frame_ptr <= (others => '0');
else
ds_binary_frame_ptr <= ds_inv_raw_frame_ptr;
end if;
end if;
end process DS_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
DS_REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
ds_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
ds_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
ds_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
ds_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
ds_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
ds_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process DS_REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
DS_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ds_mstr_reverse_order_d1 <= '1';
else
ds_mstr_reverse_order_d1 <= ds_mstr_reverse_order;
end if;
end if;
end process DS_REG_DELAY_FLAG;
DS_FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(ds_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(ds_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= ds_binary_frame_ptr;
end if;
end if;
end process DS_FRAME_CONVERT_P3;
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
--Output Dynamic GenLock Slave's working frame number in grey
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
DS2_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process DS2_REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate DYNAMIC_GENLOCK_FOR_SLAVE;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_genlock_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_genlock_mngr.vhd
--
-- Description: This entity encompasses the Gen Lock Manager
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_vdma_genlock_mngr is
generic(
C_GENLOCK_MODE : integer range 0 to 3 := 0 ;
-- Specifies Gen-Lock Mode of operation
-- 0 = Master - Channel configured to be Gen-Lock Master
-- 1 = Slave - Channel configured to be Gen-Lock Slave
C_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1 ;
-- Number of Gen-Lock masters capable of controlling Gen-Lock Slave
C_INTERNAL_GENLOCK_ENABLE : integer range 0 to 1 := 0 ;
-- Enable internal genlock bus
-- 0 = disable internal genlock bus
-- 1 = enable internal genlock bus
C_NUM_FSTORES : integer range 1 to 32 := 5
-- Number of Frame Stores
);
port (
-- Secondary Clock Domain
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- Dynamic Frame Store Support --
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
num_fstore_minus1 : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Gen-Lock Slave Signals --
mstr_in_control : in std_logic_vector(3 downto 0) ; --
genlock_select : in std_logic ; --
frame_ptr_in : in std_logic_vector --
((C_GENLOCK_NUM_MASTERS --
*NUM_FRM_STORE_WIDTH)-1 downto 0) ; --
internal_frame_ptr_in : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
slv_frame_ref_out : out std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
fsize_mismatch_err_flag : in std_logic ;
--
-- Gen-Lock Master Signals --
dmasr_halt : in std_logic ; --
circular_prk_mode : in std_logic ; --
mstr_frame_update : in std_logic ; --
mstr_frame_ref_in : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
mstrfrm_tstsync_out : out std_logic ; --
frame_ptr_out : out std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) --
);
end axi_vdma_genlock_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_genlock_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Zero vector for tying off unused inputs
constant ZERO_VALUE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
-- Number of bits to analyze for grey code enconding and decoding
constant GREY_NUM_BITS : integer := max2(1,clog2(C_NUM_FSTORES));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Slave only signals
signal grey_frame_ptr : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal grey_frmstr_adjusted : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal partial_frame_ptr : std_logic_vector(GREY_NUM_BITS-1 downto 0) := (others => '0');
signal padded_partial_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
-- Master and Slave signals
signal s_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal ds_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal dm_binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal binary_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal rvc_frame_ref_in : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal dm_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal ds_inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal inv_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal reg_raw_frame_ptr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal grey_frame_ptr_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s_frame_ptr_out : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal num_fstore_equal_one : std_logic := '0';
signal dm_mstr_reverse_order : std_logic := '0';
signal dm_mstr_reverse_order_d1 : std_logic := '0';
signal s_mstr_reverse_order : std_logic := '0';
signal ds_mstr_reverse_order : std_logic := '0';
signal s_mstr_reverse_order_d1 : std_logic := '0';
signal ds_mstr_reverse_order_d1 : std_logic := '0';
signal mstr_reverse_order : std_logic := '0';
signal mstr_reverse_order_d1 : std_logic := '0';
signal mstr_reverse_order_d2 : std_logic := '0';
-- Test signals
signal mstrfrm_tstsync_d1 : std_logic := '0';
signal mstrfrm_tstsync_d2 : std_logic := '0';
signal mstrfrm_tstsync_d3 : std_logic := '0';
signal mstrfrm_tstsync_d4 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Number of fstore value set in register is 0x01.
num_fstore_equal_one <= '1' when num_fstore_minus1 = ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0)
else '0';
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for slave
-------------------------------------------------------------------------------
GENLOCK_FOR_SLAVE : if C_GENLOCK_MODE = 1 generate
begin
-----------------------------------------------------------------------------------------------------------------------------------
--Output GenLock Slave's working frame number in grey
-----------------------------------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
-------------------------------------------------------------------------------------------------------------------
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
S_GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
S_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= '0';
s_inv_raw_frame_ptr(2) <= '0';
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= '0';
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= '0';
s_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
s_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
s_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
s_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
s_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
s_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
s_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process S_PARTIAL_NOT_P2;
-- Register to break long timing paths
S_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s_binary_frame_ptr <= (others => '0');
else
s_binary_frame_ptr <= s_inv_raw_frame_ptr;
end if;
end if;
end process S_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
s_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
s_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
s_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
S_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s_mstr_reverse_order_d1 <= '1';
else
s_mstr_reverse_order_d1 <= s_mstr_reverse_order;
end if;
end if;
end process S_REG_DELAY_FLAG;
FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(s_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(s_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= s_binary_frame_ptr;
end if;
end if;
end process FRAME_CONVERT_P3;
mstrfrm_tstsync_out <= '0'; -- Not used for slaves
end generate GENLOCK_FOR_SLAVE;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for master
-------------------------------------------------------------------------------
GENLOCK_FOR_MASTER : if C_GENLOCK_MODE = 0 generate
begin
-- Only used for slave mode
slv_frame_ref_out <= (others => '0');
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate GENLOCK_FOR_MASTER;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for master
-------------------------------------------------------------------------------
DYNAMIC_GENLOCK_FOR_MASTER : if C_GENLOCK_MODE = 2 generate
begin
----------------------------------------------------------------------------------------------------------
--un-greying Dynamic slave's (internal or external) frame number
----------------------------------------------------------------------------------------------------------
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
DM_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= '0';
dm_inv_raw_frame_ptr(2) <= '0';
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= '0';
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= '0';
dm_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
dm_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
dm_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
dm_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
dm_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
dm_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
dm_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process DM_PARTIAL_NOT_P2;
-- Register to break long timing paths
DM_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dm_binary_frame_ptr <= (others => '0');
else
dm_binary_frame_ptr <= dm_inv_raw_frame_ptr;
end if;
end if;
end process DM_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
DM_REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
dm_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
dm_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
dm_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
dm_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
dm_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
dm_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process DM_REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
DM_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dm_mstr_reverse_order_d1 <= '1';
else
dm_mstr_reverse_order_d1 <= dm_mstr_reverse_order;
end if;
end if;
end process DM_REG_DELAY_FLAG;
DM_FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(dm_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(dm_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= dm_binary_frame_ptr;
end if;
end if;
end process DM_FRAME_CONVERT_P3;
-----------------------------------------------------------------------------------------------------------
--grey frame number out for dynamic genlock master
-----------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate DYNAMIC_GENLOCK_FOR_MASTER;
-------------------------------------------------------------------------------
-- Generate genlock decoding logic for Dynamic slave
-------------------------------------------------------------------------------
DYNAMIC_GENLOCK_FOR_SLAVE : if C_GENLOCK_MODE = 3 generate
begin
-- Mux frame pointer in from Master based on master in control
GENLOCK_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mux
generic map(
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
mstr_in_control => mstr_in_control ,
genlock_select => genlock_select ,
internal_frame_ptr_in => internal_frame_ptr_in ,
frame_ptr_in => frame_ptr_in ,
frame_ptr_out => grey_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 1:
-- Decode Grey coded frame pointer
---------------------------------------------------------------------------
ADJUST_4_FRM_STRS : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= '0';
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= '0';
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= '0';
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= '0';
grey_frmstr_adjusted(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others => -- 17 to 32
grey_frmstr_adjusted(0) <= grey_frame_ptr(0);
grey_frmstr_adjusted(1) <= grey_frame_ptr(1);
grey_frmstr_adjusted(2) <= grey_frame_ptr(2);
grey_frmstr_adjusted(3) <= grey_frame_ptr(3);
grey_frmstr_adjusted(4) <= grey_frame_ptr(4);
grey_frmstr_adjusted(5) <= '0';
end case;
end process ADJUST_4_FRM_STRS;
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => GREY_NUM_BITS
)
port map(
-- Grey Encode
binary_in => ZERO_VALUE(GREY_NUM_BITS - 1 downto 0) ,
grey_out => open ,
-- Grey Decode
grey_in => grey_frmstr_adjusted(GREY_NUM_BITS - 1 downto 0) ,
binary_out => partial_frame_ptr
);
---------------------------------------------------------------------------
-- Phase 2:
-- Invert partial frame pointer and pad to full frame pointer width
---------------------------------------------------------------------------
-- FSTORES = 1 or 2 therefore pad decoded frame pointer with 4 bits
-- CR604657 - shifted FSTORE 2 case to the correct padding location
GEN_FSTORES_12 : if C_NUM_FSTORES = 1 or C_NUM_FSTORES = 2 generate
begin
padded_partial_frame_ptr <= "0000" & partial_frame_ptr;
end generate GEN_FSTORES_12;
-- FSTORES = 3 or 4 therefore pad decoded frame pointer with 3 bits
GEN_FSTORES_34 : if C_NUM_FSTORES > 2 and C_NUM_FSTORES < 5 generate
begin
padded_partial_frame_ptr <= "000" & partial_frame_ptr;
end generate GEN_FSTORES_34;
-- FSTORES = 5,6,7 or 8 therefore pad decoded frame pointer with 2 bit
GEN_FSTORES_5678 : if C_NUM_FSTORES > 4 and C_NUM_FSTORES < 9 generate
begin
padded_partial_frame_ptr <= "00" & partial_frame_ptr;
end generate GEN_FSTORES_5678;
-- FSTORES = 9 to 16 therefore pad decoded frame pointer with 1 bit
GEN_FSTORES_9TO16 : if C_NUM_FSTORES > 8 and C_NUM_FSTORES < 17 generate
begin
padded_partial_frame_ptr <= '0' & partial_frame_ptr;
end generate GEN_FSTORES_9TO16;
-- FSTORES > 16 therefore no need to pad decoded frame pointer
GEN_FSTORES_17NUP : if C_NUM_FSTORES > 16 generate
begin
padded_partial_frame_ptr <= partial_frame_ptr;
end generate GEN_FSTORES_17NUP;
-- CR604640 - fixed wrong signal in sensitivity list.
-- CR604657 - shifted FSTORE 2 to the correct inverse
DS_PARTIAL_NOT_P2 : process(num_frame_store,padded_partial_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= '0';
ds_inv_raw_frame_ptr(2) <= '0';
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= '0';
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= '0';
ds_inv_raw_frame_ptr(4) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
ds_inv_raw_frame_ptr(4) <= '0';
when others => -- 17 to 32
ds_inv_raw_frame_ptr(0) <= not padded_partial_frame_ptr(0);
ds_inv_raw_frame_ptr(1) <= not padded_partial_frame_ptr(1);
ds_inv_raw_frame_ptr(2) <= not padded_partial_frame_ptr(2);
ds_inv_raw_frame_ptr(3) <= not padded_partial_frame_ptr(3);
ds_inv_raw_frame_ptr(4) <= not padded_partial_frame_ptr(4);
end case;
end process DS_PARTIAL_NOT_P2;
-- Register to break long timing paths
DS_REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ds_binary_frame_ptr <= (others => '0');
else
ds_binary_frame_ptr <= ds_inv_raw_frame_ptr;
end if;
end if;
end process DS_REG_P2;
---------------------------------------------------------------------------
-- Phase 3:
-- Convert to frame pointer (i.e. reverse if need or pass through)
---------------------------------------------------------------------------
-- Reverse order indication
-- 1 = frame order reversed, 0 = frame order normal
--mstr_reverse_order <= not grey_frame_ptr(GREY_NUM_BITS);
DS_REVERSE_INDICATOR : process(num_frame_store,grey_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
ds_mstr_reverse_order <= not grey_frame_ptr(0);
-- Number of Frame Stores = 2
when "000010" =>
ds_mstr_reverse_order <= not grey_frame_ptr(1);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
ds_mstr_reverse_order <= not grey_frame_ptr(2);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
ds_mstr_reverse_order <= not grey_frame_ptr(3);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
ds_mstr_reverse_order <= not grey_frame_ptr(4);
-- Number of Frame Stores = 16 to 32
when others =>
ds_mstr_reverse_order <= not grey_frame_ptr(5);
end case;
end process DS_REVERSE_INDICATOR;
-- Register reverse flag to align flag with phase 3 process
DS_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ds_mstr_reverse_order_d1 <= '1';
else
ds_mstr_reverse_order_d1 <= ds_mstr_reverse_order;
end if;
end if;
end process DS_REG_DELAY_FLAG;
DS_FRAME_CONVERT_P3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
slv_frame_ref_out <= (others => '0');
-- reverse order frames (reverse the frame)
elsif(ds_mstr_reverse_order_d1='1' and num_fstore_equal_one = '0')then
slv_frame_ref_out <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(ds_binary_frame_ptr));
-- reverse order frames with only 1 frame store (reverse the frame)
-- CR607439 - If 1 fstore then frame is always just 0
elsif(num_fstore_equal_one = '1')then
slv_frame_ref_out <= (others => '0');
-- forward order frame (simply pass through)
else
slv_frame_ref_out <= ds_binary_frame_ptr;
end if;
end if;
end process DS_FRAME_CONVERT_P3;
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
--Output Dynamic GenLock Slave's working frame number in grey
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
-- Create flag to indicate when to reverse frame order for genlock output
-- 0= normal frame order, 1= reverse frame order
RVRS_ORDER_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
--if(prmry_resetn = '0' )then
mstr_reverse_order <= '1';
-- On update if at frame 0 then toggle reverse order flag.
-- Do not toggle flag if in park mode.
elsif(fsize_mismatch_err_flag = '0' and mstr_frame_update = '1' and mstr_frame_ref_in = num_fstore_minus1
and circular_prk_mode = '1')then
mstr_reverse_order <= not mstr_reverse_order; -- toggle reverse flag
end if;
end if;
end process RVRS_ORDER_FLAG;
-- Register reverse flag twice to align flag with phase 4 grey encoded tag
-- process
DS2_REG_DELAY_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstr_reverse_order_d1 <= '1';
mstr_reverse_order_d2 <= '1';
else
mstr_reverse_order_d1 <= mstr_reverse_order;
mstr_reverse_order_d2 <= mstr_reverse_order_d1;
end if;
end if;
end process DS2_REG_DELAY_FLAG;
-- For FSTORE > 1 then gray coding is needed for proper clock crossing
-- in Gen-Lock slave. (CR578234 - added generate for fstores > 1)
GEN_FSTORES_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
---------------------------------------------------------------------------
-- Phase 1: Based on reverse order flag convert master frame in into a
-- reverse order frame number (i.e. 3,2,1,0)
-- or normal order (i.e. 0,1,2,3)
---------------------------------------------------------------------------
--rvc_frame_ref_in <= std_logic_vector((C_NUM_FSTORES - 1) - unsigned(mstr_frame_ref_in));
rvc_frame_ref_in <= std_logic_vector(unsigned(num_fstore_minus1) - unsigned(mstr_frame_ref_in));
FRAME_CONVERT_P1 : process(mstr_reverse_order,mstr_frame_ref_in,rvc_frame_ref_in,num_fstore_equal_one)
begin
if(mstr_reverse_order = '1' and num_fstore_equal_one = '0')then
raw_frame_ptr <= rvc_frame_ref_in;
else
raw_frame_ptr <= mstr_frame_ref_in;
end if;
end process FRAME_CONVERT_P1;
-- Register to break long timing paths
REG_P1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_raw_frame_ptr <= (others => '0');
else
reg_raw_frame_ptr <= raw_frame_ptr;
end if;
end if;
end process REG_P1;
---------------------------------------------------------------------------
-- Phase 2: Partial Invert of raw frame pointer (invert only the
-- log2(C_NUM_FSTORE) bits
-- GREY_NUM_BITS = 1 which is C_NUM_FSTORE = 1 to 2 then invert 1 LSB
-- GREY_NUM_BITS = 2 which is C_NUM_FSTORE = 3 to 4, then invert 2 LSBs
-- GREY_NUM_BITS = 3 which is C_NUM_FSTORE = 5 to 8, then invert 3 LSBs
-- GREY_NUM_BITS = 4 which is C_NUM_FSTORE = 9 to 16, then invert 4 LSBs
-- GREY_NUM_BITS = 5 which is C_NUM_FSTORE = 17 to 32, then invert 5 LSBs (all bits)
---------------------------------------------------------------------------
-- CR604657 - shifted FSTORE 2 to the correct inverse
PARTIAL_NOT_P2 : process(num_frame_store,reg_raw_frame_ptr)
begin
case num_frame_store is
-- Number of Frame Stores = 1 and 2
when "000001" | "000010" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 5, 6, 7, and 8
when "000101" | "000110" | "000111" | "001000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= reg_raw_frame_ptr(4);
-- Number of Frame Stores = 17 to 32
when others =>
inv_raw_frame_ptr(0) <= not reg_raw_frame_ptr(0);
inv_raw_frame_ptr(1) <= not reg_raw_frame_ptr(1);
inv_raw_frame_ptr(2) <= not reg_raw_frame_ptr(2);
inv_raw_frame_ptr(3) <= not reg_raw_frame_ptr(3);
inv_raw_frame_ptr(4) <= not reg_raw_frame_ptr(4);
end case;
end process PARTIAL_NOT_P2;
-- Register pratial not to break timing paths
REG_P2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
binary_frame_ptr <= (others => '0');
else
binary_frame_ptr <= inv_raw_frame_ptr;
end if;
end if;
end process REG_P2;
---------------------------------------------------------------------------
-- Phase 3 : Grey Encode
-- Encode binary coded frame pointer
---------------------------------------------------------------------------
GREY_CODER_I : entity axi_vdma_v6_2_8.axi_vdma_greycoder
generic map(
C_DWIDTH => FRAME_NUMBER_WIDTH
)
port map(
-- Grey Encode
binary_in => binary_frame_ptr ,
grey_out => grey_frame_ptr_out ,
-- Grey Decode
grey_in => ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0) ,
binary_out => open
);
---------------------------------------------------------------------------
-- Phase 4 : Tag Grey Encoded Pointer
-- Tag grey code with the inverse of the reverse flag. This provides
-- two sets of grey codes representing 2 passes through frame buffer.
---------------------------------------------------------------------------
-- If C_NUM_FSTORES is 17 to 32 then all 5 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_5_BITS : if GREY_NUM_BITS = 5 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
-- Number of Frame Stores = 1
when "000001" =>
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 2
when "000010" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 3 and 4
when "000011" | "000100" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 5 to 8
when "000101" | "000110" | "000111" | "001000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 9 to 16
when "001001" | "001010" | "001011" | "001100" | "001101"
| "001110" | "001111" | "010000" =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
-- Number of Frame Stores = 17 to 32
when others =>
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= grey_frame_ptr_out(4);
s_frame_ptr_out(5) <= not mstr_reverse_order_d2;
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_5_BITS;
-- If C_NUM_FSTORES is 8 to 16 then all 4 bits are used of frame number therefore
-- no need to pad grey encoded result
GEN_EQL_4_BITS : if GREY_NUM_BITS = 4 generate
begin
-- CR606861
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000101" | "000110" | "000111" | "001000" => -- 5, 6, 7, and 8
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 9 to 16
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= grey_frame_ptr_out(3);
s_frame_ptr_out(4) <= not mstr_reverse_order_d2;
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_4_BITS;
-- C_NUM_FSTORES = 4 to 7
GEN_EQL_3_BITS : if GREY_NUM_BITS = 3 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000011" | "000100" => -- 3 and 4
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- 5 to 7
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= grey_frame_ptr_out(2);
s_frame_ptr_out(3) <= not mstr_reverse_order_d2;
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_3_BITS;
-- C_NUM_FSTORES = 3
GEN_EQL_2_BITS : if GREY_NUM_BITS = 2 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when "000010" => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 3
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= grey_frame_ptr_out(1);
s_frame_ptr_out(2) <= not mstr_reverse_order_d2;
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_2_BITS;
-- C_NUM_FSTORES = 2
GEN_EQL_1_BITS : if GREY_NUM_BITS = 1 generate
begin
S_FRM_PTR_OUT_PROCESS : process(num_frame_store,grey_frame_ptr_out,mstr_reverse_order_d2)
begin
case num_frame_store is
when "000001" => -- Number of Frame Stores = 1
s_frame_ptr_out(0) <= not mstr_reverse_order_d2;
s_frame_ptr_out(1) <= '0';
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
when others => -- Number of Frame Stores = 2
s_frame_ptr_out(0) <= grey_frame_ptr_out(0);
s_frame_ptr_out(1) <= not mstr_reverse_order_d2;
s_frame_ptr_out(2) <= '0';
s_frame_ptr_out(3) <= '0';
s_frame_ptr_out(4) <= '0';
s_frame_ptr_out(5) <= '0';
end case;
end process S_FRM_PTR_OUT_PROCESS;
end generate GEN_EQL_1_BITS;
end generate GEN_FSTORES_GRTR_ONE;
-- CR606861
-- For FSTORE = 1 then gray coding is not needed. Simply
-- pass the reverse order flag out.
-- (CR578234 - added generate for fstores = 1)
GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
s_frame_ptr_out <= "00000" & not(mstr_reverse_order_d2);
end generate GEN_FSTORES_EQL_ONE;
-- Register Master Frame Pointer Out
REG_FRAME_PTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_ptr_out <= (others => '0');
else
frame_ptr_out <= s_frame_ptr_out;
end if;
end if;
end process REG_FRAME_PTR_OUT;
--*********************************************************************
--** TEST VECTOR SIGNALS - For Xilinx Internal Testing Only
--*********************************************************************
-- Coverage Off
REG_SCNDRY_TSTSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mstrfrm_tstsync_d1 <= '0';
mstrfrm_tstsync_d2 <= '0';
mstrfrm_tstsync_d3 <= '0';
mstrfrm_tstsync_d4 <= '0';
else
mstrfrm_tstsync_d1 <= mstr_frame_update;
mstrfrm_tstsync_d2 <= mstrfrm_tstsync_d1;
mstrfrm_tstsync_d3 <= mstrfrm_tstsync_d2;
mstrfrm_tstsync_d4 <= mstrfrm_tstsync_d3;
end if;
end if;
end process REG_SCNDRY_TSTSYNC_OUT;
mstrfrm_tstsync_out <= mstrfrm_tstsync_d4;
-- Coverage On
--*********************************************************************
--** END TEST SECTION
--*********************************************************************
end generate DYNAMIC_GENLOCK_FOR_SLAVE;
end implementation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1899.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01899pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01899pkg;
use work.c07s01b00x00p08n01i01899pkg.all;
entity c07s01b00x00p08n01i01899ent_a is
generic ( constant bus_width : small_int);
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
end c07s01b00x00p08n01i01899ent_a;
architecture c07s01b00x00p08n01i01899arch_a of c07s01b00x00p08n01i01899ent_a is
begin
assert true ;
end c07s01b00x00p08n01i01899arch_a;
use work.c07s01b00x00p08n01i01899pkg.all;
ENTITY c07s01b00x00p08n01i01899ent IS
END c07s01b00x00p08n01i01899ent;
ARCHITECTURE c07s01b00x00p08n01i01899arch OF c07s01b00x00p08n01i01899ent IS
constant bus_width : natural := 8;
signal s_int : small_int := 0;
signal ibus, obus, obus2 : cmd_bus(small_int);
component test
generic ( constant bus_width : small_int := 5 );
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width));
signal out_bus : out cmd_bus (0 to small_int(bus_width)));
end component;
BEGIN
b: block ( s_int = 0 )
signal bool : boolean := false;
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 =>
tmp := 0;
when others =>
tmp := 1;
end case;
return tmp;
end value;
for c : test use entity work.c07s01b00x00p08n01i01899ent_a(c07s01b00x00p08n01i01899arch_a);
begin
obus <= (0 => 1, others => value) after 5 ns;
s: bool <= s_int = ibus'right(1) after 5 ns;
c : test
generic map ( b ) --block labels illegal here
port map ( ibus, obus2 );
p: process ( s_int )
begin
l: for i in small_int loop
assert false
report "body name accepted as primary in a component instantiation generic map expression."
severity note ;
exit l;
end loop l;
end process p;
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01899d - Block labels are not permitted as primaries in a component instantiation generic map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01899arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1899.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01899pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01899pkg;
use work.c07s01b00x00p08n01i01899pkg.all;
entity c07s01b00x00p08n01i01899ent_a is
generic ( constant bus_width : small_int);
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
end c07s01b00x00p08n01i01899ent_a;
architecture c07s01b00x00p08n01i01899arch_a of c07s01b00x00p08n01i01899ent_a is
begin
assert true ;
end c07s01b00x00p08n01i01899arch_a;
use work.c07s01b00x00p08n01i01899pkg.all;
ENTITY c07s01b00x00p08n01i01899ent IS
END c07s01b00x00p08n01i01899ent;
ARCHITECTURE c07s01b00x00p08n01i01899arch OF c07s01b00x00p08n01i01899ent IS
constant bus_width : natural := 8;
signal s_int : small_int := 0;
signal ibus, obus, obus2 : cmd_bus(small_int);
component test
generic ( constant bus_width : small_int := 5 );
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width));
signal out_bus : out cmd_bus (0 to small_int(bus_width)));
end component;
BEGIN
b: block ( s_int = 0 )
signal bool : boolean := false;
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 =>
tmp := 0;
when others =>
tmp := 1;
end case;
return tmp;
end value;
for c : test use entity work.c07s01b00x00p08n01i01899ent_a(c07s01b00x00p08n01i01899arch_a);
begin
obus <= (0 => 1, others => value) after 5 ns;
s: bool <= s_int = ibus'right(1) after 5 ns;
c : test
generic map ( b ) --block labels illegal here
port map ( ibus, obus2 );
p: process ( s_int )
begin
l: for i in small_int loop
assert false
report "body name accepted as primary in a component instantiation generic map expression."
severity note ;
exit l;
end loop l;
end process p;
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01899d - Block labels are not permitted as primaries in a component instantiation generic map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01899arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1899.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01899pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01899pkg;
use work.c07s01b00x00p08n01i01899pkg.all;
entity c07s01b00x00p08n01i01899ent_a is
generic ( constant bus_width : small_int);
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
end c07s01b00x00p08n01i01899ent_a;
architecture c07s01b00x00p08n01i01899arch_a of c07s01b00x00p08n01i01899ent_a is
begin
assert true ;
end c07s01b00x00p08n01i01899arch_a;
use work.c07s01b00x00p08n01i01899pkg.all;
ENTITY c07s01b00x00p08n01i01899ent IS
END c07s01b00x00p08n01i01899ent;
ARCHITECTURE c07s01b00x00p08n01i01899arch OF c07s01b00x00p08n01i01899ent IS
constant bus_width : natural := 8;
signal s_int : small_int := 0;
signal ibus, obus, obus2 : cmd_bus(small_int);
component test
generic ( constant bus_width : small_int := 5 );
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width));
signal out_bus : out cmd_bus (0 to small_int(bus_width)));
end component;
BEGIN
b: block ( s_int = 0 )
signal bool : boolean := false;
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 =>
tmp := 0;
when others =>
tmp := 1;
end case;
return tmp;
end value;
for c : test use entity work.c07s01b00x00p08n01i01899ent_a(c07s01b00x00p08n01i01899arch_a);
begin
obus <= (0 => 1, others => value) after 5 ns;
s: bool <= s_int = ibus'right(1) after 5 ns;
c : test
generic map ( b ) --block labels illegal here
port map ( ibus, obus2 );
p: process ( s_int )
begin
l: for i in small_int loop
assert false
report "body name accepted as primary in a component instantiation generic map expression."
severity note ;
exit l;
end loop l;
end process p;
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01899d - Block labels are not permitted as primaries in a component instantiation generic map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01899arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2180.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02180ent IS
END c07s02b05x00p01n02i02180ent;
ARCHITECTURE c07s02b05x00p01n02i02180arch OF c07s02b05x00p01n02i02180ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 5;
BEGIN
k := abs m;
assert NOT( k = 5 )
report "***PASSED TEST: c07s02b05x00p01n02i02180"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c07s02b05x00p01n02i02180 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02180arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2180.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02180ent IS
END c07s02b05x00p01n02i02180ent;
ARCHITECTURE c07s02b05x00p01n02i02180arch OF c07s02b05x00p01n02i02180ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 5;
BEGIN
k := abs m;
assert NOT( k = 5 )
report "***PASSED TEST: c07s02b05x00p01n02i02180"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c07s02b05x00p01n02i02180 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02180arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2180.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02180ent IS
END c07s02b05x00p01n02i02180ent;
ARCHITECTURE c07s02b05x00p01n02i02180arch OF c07s02b05x00p01n02i02180ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 5;
BEGIN
k := abs m;
assert NOT( k = 5 )
report "***PASSED TEST: c07s02b05x00p01n02i02180"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c07s02b05x00p01n02i02180 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02180arch;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - FIFO
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A simple unidirectional FIFO accessible on both sides
-- from the hardware via the known FIFO interface.
--
-- REMARK: Different clocks for FIFO-Rd and FIFO-Wr are
-- not supported yet. FIFO_S_Clk is used and
-- FIFO_M_Clk are just added for the future.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity reconos_fifo is
generic (
-- FIFO parameters
C_FIFO_DEPTH : integer := 32;
C_FIFO_WIDTH : integer := 32
);
port (
-- FIFO ports
FIFO_S_Clk : in std_logic;
FIFO_S_Data : out std_logic_vector(31 downto 0);
FIFO_S_Fill : out std_logic_vector(15 downto 0);
FIFO_S_Empty : out std_logic;
FIFO_S_RE : in std_logic;
FIFO_M_Clk : in std_logic;
FIFO_M_Data : in std_logic_vector(31 downto 0);
FIFO_M_Rem : out std_logic_vector(15 downto 0);
FIFO_M_Full : out std_logic;
FIFO_M_WE : in std_logic;
FIFO_Rst : in std_logic;
FIFO_Has_Data : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of FIFO_S_Clk : signal is "Clk";
attribute SIGIS of FIFO_M_Clk : signal is "Clk";
attribute SIGIS of FIFO_Rst : signal is "Rst";
attribute SIGIS of FIFO_Has_Data : signal is "Intr_Level_High";
end entity reconos_fifo;
architecture implementation of reconos_fifo is
-- Definition of FIFO-Memory
-- No Block-RAM because the FIFO depth should be small (around 32)
type MEM_T is array (0 to C_FIFO_DEPTH - 1) of std_logic_vector(31 downto 0);
signal fifo : MEM_T;
signal m_wrptr : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal s_rdptr : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal s_fill : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal m_rem : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal s_empty : std_logic;
signal m_full : std_logic;
signal s_dout : std_logic_vector(31 downto 0);
signal m_din : std_logic_vector(31 downto 0);
signal pad_16 : std_logic_vector(15 - clog2(C_FIFO_DEPTH) downto 0);
signal clk : std_logic;
signal rst : std_logic;
begin
-- this has the intended effect in sythesis (it is infact the same signal)
-- but causes a different behaviour in simulation
clk <= FIFO_S_Clk;
rst <= FIFO_Rst;
pad_16 <= (others => '0');
FIFO_Has_Data <= not s_empty;
FIFO_S_Data <= s_dout;
m_din <= FIFO_M_Data;
FIFO_S_Fill <= pad_16 & s_fill;
FIFO_M_Rem <= pad_16 & m_rem;
FIFO_S_Empty <= s_empty;
FIFO_M_Full <= m_full;
s_fill <= m_wrptr - s_rdptr - 1;
m_rem <= s_rdptr - m_wrptr - 1;
fifo_proc : process(clk,rst) is
begin
if rst = '1' then
s_rdptr <= (others => '0');
m_wrptr <= (others => '0');
s_empty <= '1';
m_full <= '0';
elsif rising_edge(clk) then
-- writing into fifo which is not full
if FIFO_M_WE = '1' and m_full = '0' then
fifo(CONV_INTEGER(m_wrptr)) <= m_din;
m_wrptr <= m_wrptr + 1;
if or_reduce(m_rem) = '0' then
m_full <= '1';
end if;
-- since reading from an empty FIFO has no effect
-- after writing into a FIFO its never empty
s_empty <= '0';
end if;
-- reading from fifo which is not empty
if FIFO_S_RE = '1' and s_empty = '0' then
s_rdptr <= s_rdptr + 1;
if or_reduce(s_fill) = '0' then
s_empty <= '1';
end if;
-- since writing into a full FIFO has no effect
-- after reading from a FIFO its never full
m_full <= '0';
end if;
-- do not change status if reading and writing concurrently
if (FIFO_M_WE = '1' and m_full = '0')
and (FIFO_S_RE = '1' and s_empty = '0') then
s_empty <= s_empty;
m_full <= m_full;
end if;
end if;
end process fifo_proc;
s_dout <= fifo(CONV_INTEGER(s_rdptr));
end implementation;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - FIFO
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A simple unidirectional FIFO accessible on both sides
-- from the hardware via the known FIFO interface.
--
-- REMARK: Different clocks for FIFO-Rd and FIFO-Wr are
-- not supported yet. FIFO_S_Clk is used and
-- FIFO_M_Clk are just added for the future.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity reconos_fifo is
generic (
-- FIFO parameters
C_FIFO_DEPTH : integer := 32;
C_FIFO_WIDTH : integer := 32
);
port (
-- FIFO ports
FIFO_S_Clk : in std_logic;
FIFO_S_Data : out std_logic_vector(31 downto 0);
FIFO_S_Fill : out std_logic_vector(15 downto 0);
FIFO_S_Empty : out std_logic;
FIFO_S_RE : in std_logic;
FIFO_M_Clk : in std_logic;
FIFO_M_Data : in std_logic_vector(31 downto 0);
FIFO_M_Rem : out std_logic_vector(15 downto 0);
FIFO_M_Full : out std_logic;
FIFO_M_WE : in std_logic;
FIFO_Rst : in std_logic;
FIFO_Has_Data : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of FIFO_S_Clk : signal is "Clk";
attribute SIGIS of FIFO_M_Clk : signal is "Clk";
attribute SIGIS of FIFO_Rst : signal is "Rst";
attribute SIGIS of FIFO_Has_Data : signal is "Intr_Level_High";
end entity reconos_fifo;
architecture implementation of reconos_fifo is
-- Definition of FIFO-Memory
-- No Block-RAM because the FIFO depth should be small (around 32)
type MEM_T is array (0 to C_FIFO_DEPTH - 1) of std_logic_vector(31 downto 0);
signal fifo : MEM_T;
signal m_wrptr : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal s_rdptr : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal s_fill : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal m_rem : std_logic_vector(clog2(C_FIFO_DEPTH) - 1 downto 0);
signal s_empty : std_logic;
signal m_full : std_logic;
signal s_dout : std_logic_vector(31 downto 0);
signal m_din : std_logic_vector(31 downto 0);
signal pad_16 : std_logic_vector(15 - clog2(C_FIFO_DEPTH) downto 0);
signal clk : std_logic;
signal rst : std_logic;
begin
-- this has the intended effect in sythesis (it is infact the same signal)
-- but causes a different behaviour in simulation
clk <= FIFO_S_Clk;
rst <= FIFO_Rst;
pad_16 <= (others => '0');
FIFO_Has_Data <= not s_empty;
FIFO_S_Data <= s_dout;
m_din <= FIFO_M_Data;
FIFO_S_Fill <= pad_16 & s_fill;
FIFO_M_Rem <= pad_16 & m_rem;
FIFO_S_Empty <= s_empty;
FIFO_M_Full <= m_full;
s_fill <= m_wrptr - s_rdptr - 1;
m_rem <= s_rdptr - m_wrptr - 1;
fifo_proc : process(clk,rst) is
begin
if rst = '1' then
s_rdptr <= (others => '0');
m_wrptr <= (others => '0');
s_empty <= '1';
m_full <= '0';
elsif rising_edge(clk) then
-- writing into fifo which is not full
if FIFO_M_WE = '1' and m_full = '0' then
fifo(CONV_INTEGER(m_wrptr)) <= m_din;
m_wrptr <= m_wrptr + 1;
if or_reduce(m_rem) = '0' then
m_full <= '1';
end if;
-- since reading from an empty FIFO has no effect
-- after writing into a FIFO its never empty
s_empty <= '0';
end if;
-- reading from fifo which is not empty
if FIFO_S_RE = '1' and s_empty = '0' then
s_rdptr <= s_rdptr + 1;
if or_reduce(s_fill) = '0' then
s_empty <= '1';
end if;
-- since writing into a full FIFO has no effect
-- after reading from a FIFO its never full
m_full <= '0';
end if;
-- do not change status if reading and writing concurrently
if (FIFO_M_WE = '1' and m_full = '0')
and (FIFO_S_RE = '1' and s_empty = '0') then
s_empty <= s_empty;
m_full <= m_full;
end if;
end if;
end process fifo_proc;
s_dout <= fifo(CONV_INTEGER(s_rdptr));
end implementation;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY formatter IS
PORT(
lutbus : IN std_logic_vector (15 DOWNTO 0);
mux_addr : OUT std_logic_vector (2 DOWNTO 0);
mux_data : OUT std_logic_vector (3 DOWNTO 0);
mux_reg : OUT std_logic_vector (2 DOWNTO 0);
nbreq : OUT std_logic_vector (2 DOWNTO 0)
);
END formatter ;
ARCHITECTURE struct OF formatter IS
-- Architecture declarations
SIGNAL dout : std_logic_vector(15 DOWNTO 0);
SIGNAL dout4 : std_logic_vector(7 DOWNTO 0);
SIGNAL dout5 : std_logic_vector(7 DOWNTO 0);
SIGNAL muxout : std_logic_vector(7 DOWNTO 0);
SIGNAL mw_I1temp_din : std_logic_vector(15 DOWNTO 0);
-- Component Declarations
COMPONENT a_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT d_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT m_table
PORT (
ireg : IN std_logic_vector (7 DOWNTO 0);
modrrm : IN std_logic_vector (7 DOWNTO 0);
muxout : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT n_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT r_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
dout <= dout4 & muxout;
mw_I1temp_din <= lutbus;
i1combo_proc: PROCESS (mw_I1temp_din)
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
BEGIN
temp_din := mw_I1temp_din(15 DOWNTO 0);
dout5 <= temp_din(7 DOWNTO 0);
dout4 <= temp_din(15 DOWNTO 8);
END PROCESS i1combo_proc;
-- Instance port mappings.
I2 : a_table
PORT MAP (
addr => dout,
dout => mux_addr
);
I3 : d_table
PORT MAP (
addr => dout,
dout => mux_data
);
I6 : m_table
PORT MAP (
ireg => dout4,
modrrm => dout5,
muxout => muxout
);
I4 : n_table
PORT MAP (
addr => dout,
dout => nbreq
);
I5 : r_table
PORT MAP (
addr => dout,
dout => mux_reg
);
END struct;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY formatter IS
PORT(
lutbus : IN std_logic_vector (15 DOWNTO 0);
mux_addr : OUT std_logic_vector (2 DOWNTO 0);
mux_data : OUT std_logic_vector (3 DOWNTO 0);
mux_reg : OUT std_logic_vector (2 DOWNTO 0);
nbreq : OUT std_logic_vector (2 DOWNTO 0)
);
END formatter ;
ARCHITECTURE struct OF formatter IS
-- Architecture declarations
SIGNAL dout : std_logic_vector(15 DOWNTO 0);
SIGNAL dout4 : std_logic_vector(7 DOWNTO 0);
SIGNAL dout5 : std_logic_vector(7 DOWNTO 0);
SIGNAL muxout : std_logic_vector(7 DOWNTO 0);
SIGNAL mw_I1temp_din : std_logic_vector(15 DOWNTO 0);
-- Component Declarations
COMPONENT a_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT d_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT m_table
PORT (
ireg : IN std_logic_vector (7 DOWNTO 0);
modrrm : IN std_logic_vector (7 DOWNTO 0);
muxout : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT n_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT r_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
dout <= dout4 & muxout;
mw_I1temp_din <= lutbus;
i1combo_proc: PROCESS (mw_I1temp_din)
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
BEGIN
temp_din := mw_I1temp_din(15 DOWNTO 0);
dout5 <= temp_din(7 DOWNTO 0);
dout4 <= temp_din(15 DOWNTO 8);
END PROCESS i1combo_proc;
-- Instance port mappings.
I2 : a_table
PORT MAP (
addr => dout,
dout => mux_addr
);
I3 : d_table
PORT MAP (
addr => dout,
dout => mux_data
);
I6 : m_table
PORT MAP (
ireg => dout4,
modrrm => dout5,
muxout => muxout
);
I4 : n_table
PORT MAP (
addr => dout,
dout => nbreq
);
I5 : r_table
PORT MAP (
addr => dout,
dout => mux_reg
);
END struct;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY formatter IS
PORT(
lutbus : IN std_logic_vector (15 DOWNTO 0);
mux_addr : OUT std_logic_vector (2 DOWNTO 0);
mux_data : OUT std_logic_vector (3 DOWNTO 0);
mux_reg : OUT std_logic_vector (2 DOWNTO 0);
nbreq : OUT std_logic_vector (2 DOWNTO 0)
);
END formatter ;
ARCHITECTURE struct OF formatter IS
-- Architecture declarations
SIGNAL dout : std_logic_vector(15 DOWNTO 0);
SIGNAL dout4 : std_logic_vector(7 DOWNTO 0);
SIGNAL dout5 : std_logic_vector(7 DOWNTO 0);
SIGNAL muxout : std_logic_vector(7 DOWNTO 0);
SIGNAL mw_I1temp_din : std_logic_vector(15 DOWNTO 0);
-- Component Declarations
COMPONENT a_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT d_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT m_table
PORT (
ireg : IN std_logic_vector (7 DOWNTO 0);
modrrm : IN std_logic_vector (7 DOWNTO 0);
muxout : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT n_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT r_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
dout <= dout4 & muxout;
mw_I1temp_din <= lutbus;
i1combo_proc: PROCESS (mw_I1temp_din)
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
BEGIN
temp_din := mw_I1temp_din(15 DOWNTO 0);
dout5 <= temp_din(7 DOWNTO 0);
dout4 <= temp_din(15 DOWNTO 8);
END PROCESS i1combo_proc;
-- Instance port mappings.
I2 : a_table
PORT MAP (
addr => dout,
dout => mux_addr
);
I3 : d_table
PORT MAP (
addr => dout,
dout => mux_data
);
I6 : m_table
PORT MAP (
ireg => dout4,
modrrm => dout5,
muxout => muxout
);
I4 : n_table
PORT MAP (
addr => dout,
dout => nbreq
);
I5 : r_table
PORT MAP (
addr => dout,
dout => mux_reg
);
END struct;
|
-- tracking_camera_system_green_leds_s1_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_green_leds_s1_translator is
generic (
AV_ADDRESS_W : integer := 2;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(1 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(0 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_green_leds_s1_translator;
architecture rtl of tracking_camera_system_green_leds_s1_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
green_leds_s1_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_chipselect => av_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_green_leds_s1_translator
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity atombasic is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of atombasic is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(11 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"3C";
when x"001" => DATA <= x"3D";
when x"002" => DATA <= x"3E";
when x"003" => DATA <= x"FE";
when x"004" => DATA <= x"2D";
when x"005" => DATA <= x"2B";
when x"006" => DATA <= x"C8";
when x"007" => DATA <= x"23";
when x"008" => DATA <= x"28";
when x"009" => DATA <= x"21";
when x"00A" => DATA <= x"3F";
when x"00B" => DATA <= x"52";
when x"00C" => DATA <= x"54";
when x"00D" => DATA <= x"4C";
when x"00E" => DATA <= x"43";
when x"00F" => DATA <= x"41";
when x"010" => DATA <= x"50";
when x"011" => DATA <= x"45";
when x"012" => DATA <= x"47";
when x"013" => DATA <= x"42";
when x"014" => DATA <= x"46";
when x"015" => DATA <= x"F0";
when x"016" => DATA <= x"54";
when x"017" => DATA <= x"FF";
when x"018" => DATA <= x"4F";
when x"019" => DATA <= x"CB";
when x"01A" => DATA <= x"53";
when x"01B" => DATA <= x"CB";
when x"01C" => DATA <= x"54";
when x"01D" => DATA <= x"45";
when x"01E" => DATA <= x"50";
when x"01F" => DATA <= x"CB";
when x"020" => DATA <= x"54";
when x"021" => DATA <= x"C3";
when x"022" => DATA <= x"48";
when x"023" => DATA <= x"45";
when x"024" => DATA <= x"4E";
when x"025" => DATA <= x"C3";
when x"026" => DATA <= x"22";
when x"027" => DATA <= x"24";
when x"028" => DATA <= x"CE";
when x"029" => DATA <= x"CE";
when x"02A" => DATA <= x"CC";
when x"02B" => DATA <= x"24";
when x"02C" => DATA <= x"2C";
when x"02D" => DATA <= x"C5";
when x"02E" => DATA <= x"24";
when x"02F" => DATA <= x"26";
when x"030" => DATA <= x"3B";
when x"031" => DATA <= x"0D";
when x"032" => DATA <= x"2C";
when x"033" => DATA <= x"C3";
when x"034" => DATA <= x"C5";
when x"035" => DATA <= x"C2";
when x"036" => DATA <= x"3E";
when x"037" => DATA <= x"C7";
when x"038" => DATA <= x"3D";
when x"039" => DATA <= x"C7";
when x"03A" => DATA <= x"C7";
when x"03B" => DATA <= x"C7";
when x"03C" => DATA <= x"3D";
when x"03D" => DATA <= x"C7";
when x"03E" => DATA <= x"C7";
when x"03F" => DATA <= x"C8";
when x"040" => DATA <= x"52";
when x"041" => DATA <= x"C7";
when x"042" => DATA <= x"C7";
when x"043" => DATA <= x"4F";
when x"044" => DATA <= x"41";
when x"045" => DATA <= x"FE";
when x"046" => DATA <= x"24";
when x"047" => DATA <= x"C7";
when x"048" => DATA <= x"48";
when x"049" => DATA <= x"C9";
when x"04A" => DATA <= x"45";
when x"04B" => DATA <= x"4E";
when x"04C" => DATA <= x"C9";
when x"04D" => DATA <= x"4E";
when x"04E" => DATA <= x"44";
when x"04F" => DATA <= x"C7";
when x"050" => DATA <= x"C9";
when x"051" => DATA <= x"C9";
when x"052" => DATA <= x"C9";
when x"053" => DATA <= x"C9";
when x"054" => DATA <= x"4E";
when x"055" => DATA <= x"44";
when x"056" => DATA <= x"C9";
when x"057" => DATA <= x"4F";
when x"058" => DATA <= x"50";
when x"059" => DATA <= x"C9";
when x"05A" => DATA <= x"4F";
when x"05B" => DATA <= x"55";
when x"05C" => DATA <= x"4E";
when x"05D" => DATA <= x"54";
when x"05E" => DATA <= x"C9";
when x"05F" => DATA <= x"42";
when x"060" => DATA <= x"53";
when x"061" => DATA <= x"C9";
when x"062" => DATA <= x"54";
when x"063" => DATA <= x"52";
when x"064" => DATA <= x"CF";
when x"065" => DATA <= x"58";
when x"066" => DATA <= x"54";
when x"067" => DATA <= x"CF";
when x"068" => DATA <= x"45";
when x"069" => DATA <= x"54";
when x"06A" => DATA <= x"CF";
when x"06B" => DATA <= x"47";
when x"06C" => DATA <= x"45";
when x"06D" => DATA <= x"54";
when x"06E" => DATA <= x"CF";
when x"06F" => DATA <= x"49";
when x"070" => DATA <= x"4E";
when x"071" => DATA <= x"CF";
when x"072" => DATA <= x"4F";
when x"073" => DATA <= x"55";
when x"074" => DATA <= x"54";
when x"075" => DATA <= x"CF";
when x"076" => DATA <= x"C3";
when x"077" => DATA <= x"C3";
when x"078" => DATA <= x"52";
when x"079" => DATA <= x"49";
when x"07A" => DATA <= x"4E";
when x"07B" => DATA <= x"54";
when x"07C" => DATA <= x"C3";
when x"07D" => DATA <= x"4E";
when x"07E" => DATA <= x"4C";
when x"07F" => DATA <= x"55";
when x"080" => DATA <= x"4E";
when x"081" => DATA <= x"49";
when x"082" => DATA <= x"47";
when x"083" => DATA <= x"52";
when x"084" => DATA <= x"46";
when x"085" => DATA <= x"21";
when x"086" => DATA <= x"3F";
when x"087" => DATA <= x"24";
when x"088" => DATA <= x"50";
when x"089" => DATA <= x"44";
when x"08A" => DATA <= x"4C";
when x"08B" => DATA <= x"53";
when x"08C" => DATA <= x"42";
when x"08D" => DATA <= x"2A";
when x"08E" => DATA <= x"45";
when x"08F" => DATA <= x"F0";
when x"090" => DATA <= x"41";
when x"091" => DATA <= x"56";
when x"092" => DATA <= x"45";
when x"093" => DATA <= x"CF";
when x"094" => DATA <= x"45";
when x"095" => DATA <= x"57";
when x"096" => DATA <= x"C2";
when x"097" => DATA <= x"4F";
when x"098" => DATA <= x"CC";
when x"099" => DATA <= x"45";
when x"09A" => DATA <= x"54";
when x"09B" => DATA <= x"C3";
when x"09C" => DATA <= x"49";
when x"09D" => DATA <= x"4E";
when x"09E" => DATA <= x"4B";
when x"09F" => DATA <= x"C3";
when x"0A0" => DATA <= x"49";
when x"0A1" => DATA <= x"53";
when x"0A2" => DATA <= x"54";
when x"0A3" => DATA <= x"CA";
when x"0A4" => DATA <= x"4F";
when x"0A5" => DATA <= x"41";
when x"0A6" => DATA <= x"44";
when x"0A7" => DATA <= x"CE";
when x"0A8" => DATA <= x"4E";
when x"0A9" => DATA <= x"54";
when x"0AA" => DATA <= x"49";
when x"0AB" => DATA <= x"4C";
when x"0AC" => DATA <= x"CC";
when x"0AD" => DATA <= x"45";
when x"0AE" => DATA <= x"58";
when x"0AF" => DATA <= x"54";
when x"0B0" => DATA <= x"CA";
when x"0B1" => DATA <= x"46";
when x"0B2" => DATA <= x"C5";
when x"0B3" => DATA <= x"4E";
when x"0B4" => DATA <= x"50";
when x"0B5" => DATA <= x"55";
when x"0B6" => DATA <= x"54";
when x"0B7" => DATA <= x"CC";
when x"0B8" => DATA <= x"4F";
when x"0B9" => DATA <= x"53";
when x"0BA" => DATA <= x"55";
when x"0BB" => DATA <= x"42";
when x"0BC" => DATA <= x"CB";
when x"0BD" => DATA <= x"4F";
when x"0BE" => DATA <= x"54";
when x"0BF" => DATA <= x"4F";
when x"0C0" => DATA <= x"CC";
when x"0C1" => DATA <= x"45";
when x"0C2" => DATA <= x"54";
when x"0C3" => DATA <= x"55";
when x"0C4" => DATA <= x"52";
when x"0C5" => DATA <= x"4E";
when x"0C6" => DATA <= x"CB";
when x"0C7" => DATA <= x"45";
when x"0C8" => DATA <= x"4D";
when x"0C9" => DATA <= x"C5";
when x"0CA" => DATA <= x"55";
when x"0CB" => DATA <= x"4E";
when x"0CC" => DATA <= x"F1";
when x"0CD" => DATA <= x"4F";
when x"0CE" => DATA <= x"52";
when x"0CF" => DATA <= x"CB";
when x"0D0" => DATA <= x"4E";
when x"0D1" => DATA <= x"44";
when x"0D2" => DATA <= x"CD";
when x"0D3" => DATA <= x"47";
when x"0D4" => DATA <= x"45";
when x"0D5" => DATA <= x"54";
when x"0D6" => DATA <= x"CF";
when x"0D7" => DATA <= x"50";
when x"0D8" => DATA <= x"55";
when x"0D9" => DATA <= x"54";
when x"0DA" => DATA <= x"CF";
when x"0DB" => DATA <= x"48";
when x"0DC" => DATA <= x"55";
when x"0DD" => DATA <= x"54";
when x"0DE" => DATA <= x"CF";
when x"0DF" => DATA <= x"50";
when x"0E0" => DATA <= x"55";
when x"0E1" => DATA <= x"54";
when x"0E2" => DATA <= x"CF";
when x"0E3" => DATA <= x"54";
when x"0E4" => DATA <= x"52";
when x"0E5" => DATA <= x"CF";
when x"0E6" => DATA <= x"55";
when x"0E7" => DATA <= x"54";
when x"0E8" => DATA <= x"CF";
when x"0E9" => DATA <= x"C3";
when x"0EA" => DATA <= x"C4";
when x"0EB" => DATA <= x"CD";
when x"0EC" => DATA <= x"C4";
when x"0ED" => DATA <= x"2C";
when x"0EE" => DATA <= x"FE";
when x"0EF" => DATA <= x"36";
when x"0F0" => DATA <= x"3B";
when x"0F1" => DATA <= x"3C";
when x"0F2" => DATA <= x"C0";
when x"0F3" => DATA <= x"3F";
when x"0F4" => DATA <= x"06";
when x"0F5" => DATA <= x"DC";
when x"0F6" => DATA <= x"50";
when x"0F7" => DATA <= x"51";
when x"0F8" => DATA <= x"52";
when x"0F9" => DATA <= x"53";
when x"0FA" => DATA <= x"54";
when x"0FB" => DATA <= x"57";
when x"0FC" => DATA <= x"4A";
when x"0FD" => DATA <= x"5A";
when x"0FE" => DATA <= x"5F";
when x"0FF" => DATA <= x"62";
when x"100" => DATA <= x"65";
when x"101" => DATA <= x"68";
when x"102" => DATA <= x"6B";
when x"103" => DATA <= x"6F";
when x"104" => DATA <= x"2E";
when x"105" => DATA <= x"18";
when x"106" => DATA <= x"AC";
when x"107" => DATA <= x"17";
when x"108" => DATA <= x"81";
when x"109" => DATA <= x"1C";
when x"10A" => DATA <= x"BE";
when x"10B" => DATA <= x"17";
when x"10C" => DATA <= x"17";
when x"10D" => DATA <= x"17";
when x"10E" => DATA <= x"A2";
when x"10F" => DATA <= x"22";
when x"110" => DATA <= x"1B";
when x"111" => DATA <= x"17";
when x"112" => DATA <= x"17";
when x"113" => DATA <= x"17";
when x"114" => DATA <= x"1B";
when x"115" => DATA <= x"29";
when x"116" => DATA <= x"28";
when x"117" => DATA <= x"B6";
when x"118" => DATA <= x"BF";
when x"119" => DATA <= x"B6";
when x"11A" => DATA <= x"2A";
when x"11B" => DATA <= x"B7";
when x"11C" => DATA <= x"58";
when x"11D" => DATA <= x"76";
when x"11E" => DATA <= x"77";
when x"11F" => DATA <= x"34";
when x"120" => DATA <= x"34";
when x"121" => DATA <= x"7C";
when x"122" => DATA <= x"3F";
when x"123" => DATA <= x"4A";
when x"124" => DATA <= x"78";
when x"125" => DATA <= x"38";
when x"126" => DATA <= x"6D";
when x"127" => DATA <= x"3A";
when x"128" => DATA <= x"64";
when x"129" => DATA <= x"74";
when x"12A" => DATA <= x"5B";
when x"12B" => DATA <= x"3E";
when x"12C" => DATA <= x"7B";
when x"12D" => DATA <= x"82";
when x"12E" => DATA <= x"C1";
when x"12F" => DATA <= x"45";
when x"130" => DATA <= x"22";
when x"131" => DATA <= x"31";
when x"132" => DATA <= x"40";
when x"133" => DATA <= x"4D";
when x"134" => DATA <= x"4D";
when x"135" => DATA <= x"42";
when x"136" => DATA <= x"53";
when x"137" => DATA <= x"15";
when x"138" => DATA <= x"D2";
when x"139" => DATA <= x"15";
when x"13A" => DATA <= x"15";
when x"13B" => DATA <= x"BD";
when x"13C" => DATA <= x"45";
when x"13D" => DATA <= x"45";
when x"13E" => DATA <= x"14";
when x"13F" => DATA <= x"0A";
when x"140" => DATA <= x"44";
when x"141" => DATA <= x"5F";
when x"142" => DATA <= x"4C";
when x"143" => DATA <= x"15";
when x"144" => DATA <= x"15";
when x"145" => DATA <= x"86";
when x"146" => DATA <= x"15";
when x"147" => DATA <= x"15";
when x"148" => DATA <= x"73";
when x"149" => DATA <= x"48";
when x"14A" => DATA <= x"15";
when x"14B" => DATA <= x"15";
when x"14C" => DATA <= x"15";
when x"14D" => DATA <= x"7A";
when x"14E" => DATA <= x"15";
when x"14F" => DATA <= x"15";
when x"150" => DATA <= x"02";
when x"151" => DATA <= x"15";
when x"152" => DATA <= x"15";
when x"153" => DATA <= x"29";
when x"154" => DATA <= x"15";
when x"155" => DATA <= x"15";
when x"156" => DATA <= x"28";
when x"157" => DATA <= x"15";
when x"158" => DATA <= x"15";
when x"159" => DATA <= x"66";
when x"15A" => DATA <= x"15";
when x"15B" => DATA <= x"15";
when x"15C" => DATA <= x"15";
when x"15D" => DATA <= x"5B";
when x"15E" => DATA <= x"72";
when x"15F" => DATA <= x"15";
when x"160" => DATA <= x"A6";
when x"161" => DATA <= x"15";
when x"162" => DATA <= x"15";
when x"163" => DATA <= x"15";
when x"164" => DATA <= x"A7";
when x"165" => DATA <= x"90";
when x"166" => DATA <= x"35";
when x"167" => DATA <= x"E3";
when x"168" => DATA <= x"8F";
when x"169" => DATA <= x"8F";
when x"16A" => DATA <= x"8F";
when x"16B" => DATA <= x"34";
when x"16C" => DATA <= x"94";
when x"16D" => DATA <= x"A0";
when x"16E" => DATA <= x"A8";
when x"16F" => DATA <= x"AD";
when x"170" => DATA <= x"B1";
when x"171" => DATA <= x"BD";
when x"172" => DATA <= x"C1";
when x"173" => DATA <= x"CD";
when x"174" => DATA <= x"E9";
when x"175" => DATA <= x"EA";
when x"176" => DATA <= x"EB";
when x"177" => DATA <= x"78";
when x"178" => DATA <= x"97";
when x"179" => DATA <= x"99";
when x"17A" => DATA <= x"D3";
when x"17B" => DATA <= x"DF";
when x"17C" => DATA <= x"EC";
when x"17D" => DATA <= x"D0";
when x"17E" => DATA <= x"4B";
when x"17F" => DATA <= x"8F";
when x"180" => DATA <= x"8F";
when x"181" => DATA <= x"8F";
when x"182" => DATA <= x"0A";
when x"183" => DATA <= x"8F";
when x"184" => DATA <= x"AD";
when x"185" => DATA <= x"AD";
when x"186" => DATA <= x"8F";
when x"187" => DATA <= x"F0";
when x"188" => DATA <= x"9C";
when x"189" => DATA <= x"8F";
when x"18A" => DATA <= x"25";
when x"18B" => DATA <= x"8F";
when x"18C" => DATA <= x"8F";
when x"18D" => DATA <= x"8F";
when x"18E" => DATA <= x"B2";
when x"18F" => DATA <= x"A4";
when x"190" => DATA <= x"9C";
when x"191" => DATA <= x"8F";
when x"192" => DATA <= x"51";
when x"193" => DATA <= x"99";
when x"194" => DATA <= x"8F";
when x"195" => DATA <= x"8F";
when x"196" => DATA <= x"ED";
when x"197" => DATA <= x"8F";
when x"198" => DATA <= x"8F";
when x"199" => DATA <= x"8F";
when x"19A" => DATA <= x"8F";
when x"19B" => DATA <= x"D2";
when x"19C" => DATA <= x"8F";
when x"19D" => DATA <= x"8F";
when x"19E" => DATA <= x"8F";
when x"19F" => DATA <= x"CD";
when x"1A0" => DATA <= x"B3";
when x"1A1" => DATA <= x"66";
when x"1A2" => DATA <= x"8F";
when x"1A3" => DATA <= x"8F";
when x"1A4" => DATA <= x"8F";
when x"1A5" => DATA <= x"8F";
when x"1A6" => DATA <= x"81";
when x"1A7" => DATA <= x"8F";
when x"1A8" => DATA <= x"8F";
when x"1A9" => DATA <= x"8F";
when x"1AA" => DATA <= x"8F";
when x"1AB" => DATA <= x"D2";
when x"1AC" => DATA <= x"8F";
when x"1AD" => DATA <= x"B8";
when x"1AE" => DATA <= x"8F";
when x"1AF" => DATA <= x"05";
when x"1B0" => DATA <= x"CA";
when x"1B1" => DATA <= x"C7";
when x"1B2" => DATA <= x"8F";
when x"1B3" => DATA <= x"8F";
when x"1B4" => DATA <= x"8F";
when x"1B5" => DATA <= x"EC";
when x"1B6" => DATA <= x"8F";
when x"1B7" => DATA <= x"8F";
when x"1B8" => DATA <= x"75";
when x"1B9" => DATA <= x"8F";
when x"1BA" => DATA <= x"8F";
when x"1BB" => DATA <= x"41";
when x"1BC" => DATA <= x"8F";
when x"1BD" => DATA <= x"8F";
when x"1BE" => DATA <= x"57";
when x"1BF" => DATA <= x"8F";
when x"1C0" => DATA <= x"8F";
when x"1C1" => DATA <= x"98";
when x"1C2" => DATA <= x"D7";
when x"1C3" => DATA <= x"8F";
when x"1C4" => DATA <= x"8F";
when x"1C5" => DATA <= x"E3";
when x"1C6" => DATA <= x"DB";
when x"1C7" => DATA <= x"8F";
when x"1C8" => DATA <= x"8F";
when x"1C9" => DATA <= x"C5";
when x"1CA" => DATA <= x"90";
when x"1CB" => DATA <= x"8F";
when x"1CC" => DATA <= x"8F";
when x"1CD" => DATA <= x"B6";
when x"1CE" => DATA <= x"8F";
when x"1CF" => DATA <= x"8F";
when x"1D0" => DATA <= x"8F";
when x"1D1" => DATA <= x"8F";
when x"1D2" => DATA <= x"E6";
when x"1D3" => DATA <= x"8F";
when x"1D4" => DATA <= x"47";
when x"1D5" => DATA <= x"8F";
when x"1D6" => DATA <= x"8F";
when x"1D7" => DATA <= x"95";
when x"1D8" => DATA <= x"EE";
when x"1D9" => DATA <= x"06";
when x"1DA" => DATA <= x"5C";
when x"1DB" => DATA <= x"0F";
when x"1DC" => DATA <= x"35";
when x"1DD" => DATA <= x"2D";
when x"1DE" => DATA <= x"2B";
when x"1DF" => DATA <= x"7C";
when x"1E0" => DATA <= x"3A";
when x"1E1" => DATA <= x"FE";
when x"1E2" => DATA <= x"2A";
when x"1E3" => DATA <= x"2F";
when x"1E4" => DATA <= x"25";
when x"1E5" => DATA <= x"21";
when x"1E6" => DATA <= x"3F";
when x"1E7" => DATA <= x"26";
when x"1E8" => DATA <= x"FE";
when x"1E9" => DATA <= x"29";
when x"1EA" => DATA <= x"FF";
when x"1EB" => DATA <= x"3D";
when x"1EC" => DATA <= x"FF";
when x"1ED" => DATA <= x"21";
when x"1EE" => DATA <= x"3F";
when x"1EF" => DATA <= x"24";
when x"1F0" => DATA <= x"FF";
when x"1F1" => DATA <= x"3D";
when x"1F2" => DATA <= x"21";
when x"1F3" => DATA <= x"3F";
when x"1F4" => DATA <= x"FF";
when x"1F5" => DATA <= x"27";
when x"1F6" => DATA <= x"22";
when x"1F7" => DATA <= x"FE";
when x"1F8" => DATA <= x"B7";
when x"1F9" => DATA <= x"9A";
when x"1FA" => DATA <= x"D3";
when x"1FB" => DATA <= x"EF";
when x"1FC" => DATA <= x"EF";
when x"1FD" => DATA <= x"13";
when x"1FE" => DATA <= x"5E";
when x"1FF" => DATA <= x"70";
when x"200" => DATA <= x"B3";
when x"201" => DATA <= x"9C";
when x"202" => DATA <= x"7B";
when x"203" => DATA <= x"7B";
when x"204" => DATA <= x"78";
when x"205" => DATA <= x"78";
when x"206" => DATA <= x"78";
when x"207" => DATA <= x"78";
when x"208" => DATA <= x"EE";
when x"209" => DATA <= x"06";
when x"20A" => DATA <= x"5C";
when x"20B" => DATA <= x"5C";
when x"20C" => DATA <= x"E5";
when x"20D" => DATA <= x"75";
when x"20E" => DATA <= x"7B";
when x"20F" => DATA <= x"7B";
when x"210" => DATA <= x"6F";
when x"211" => DATA <= x"7A";
when x"212" => DATA <= x"C7";
when x"213" => DATA <= x"C7";
when x"214" => DATA <= x"C7";
when x"215" => DATA <= x"C7";
when x"216" => DATA <= x"C7";
when x"217" => DATA <= x"C8";
when x"218" => DATA <= x"C8";
when x"219" => DATA <= x"C8";
when x"21A" => DATA <= x"C8";
when x"21B" => DATA <= x"C8";
when x"21C" => DATA <= x"C8";
when x"21D" => DATA <= x"C8";
when x"21E" => DATA <= x"C2";
when x"21F" => DATA <= x"C2";
when x"220" => DATA <= x"C2";
when x"221" => DATA <= x"C2";
when x"222" => DATA <= x"C3";
when x"223" => DATA <= x"C4";
when x"224" => DATA <= x"CD";
when x"225" => DATA <= x"CD";
when x"226" => DATA <= x"C3";
when x"227" => DATA <= x"CD";
when x"228" => DATA <= x"CD";
when x"229" => DATA <= x"CD";
when x"22A" => DATA <= x"C3";
when x"22B" => DATA <= x"C3";
when x"22C" => DATA <= x"20";
when x"22D" => DATA <= x"3E";
when x"22E" => DATA <= x"CF";
when x"22F" => DATA <= x"84";
when x"230" => DATA <= x"0F";
when x"231" => DATA <= x"A2";
when x"232" => DATA <= x"ED";
when x"233" => DATA <= x"A4";
when x"234" => DATA <= x"03";
when x"235" => DATA <= x"88";
when x"236" => DATA <= x"C8";
when x"237" => DATA <= x"B1";
when x"238" => DATA <= x"05";
when x"239" => DATA <= x"C9";
when x"23A" => DATA <= x"20";
when x"23B" => DATA <= x"F0";
when x"23C" => DATA <= x"F9";
when x"23D" => DATA <= x"84";
when x"23E" => DATA <= x"5E";
when x"23F" => DATA <= x"85";
when x"240" => DATA <= x"52";
when x"241" => DATA <= x"E8";
when x"242" => DATA <= x"BD";
when x"243" => DATA <= x"FF";
when x"244" => DATA <= x"BF";
when x"245" => DATA <= x"30";
when x"246" => DATA <= x"24";
when x"247" => DATA <= x"C5";
when x"248" => DATA <= x"52";
when x"249" => DATA <= x"D0";
when x"24A" => DATA <= x"F6";
when x"24B" => DATA <= x"BD";
when x"24C" => DATA <= x"EE";
when x"24D" => DATA <= x"C0";
when x"24E" => DATA <= x"AA";
when x"24F" => DATA <= x"E8";
when x"250" => DATA <= x"C8";
when x"251" => DATA <= x"BD";
when x"252" => DATA <= x"FF";
when x"253" => DATA <= x"BF";
when x"254" => DATA <= x"30";
when x"255" => DATA <= x"15";
when x"256" => DATA <= x"D1";
when x"257" => DATA <= x"05";
when x"258" => DATA <= x"F0";
when x"259" => DATA <= x"F5";
when x"25A" => DATA <= x"B1";
when x"25B" => DATA <= x"05";
when x"25C" => DATA <= x"C9";
when x"25D" => DATA <= x"2E";
when x"25E" => DATA <= x"F0";
when x"25F" => DATA <= x"04";
when x"260" => DATA <= x"A4";
when x"261" => DATA <= x"5E";
when x"262" => DATA <= x"10";
when x"263" => DATA <= x"E7";
when x"264" => DATA <= x"E8";
when x"265" => DATA <= x"BD";
when x"266" => DATA <= x"FF";
when x"267" => DATA <= x"BF";
when x"268" => DATA <= x"10";
when x"269" => DATA <= x"FA";
when x"26A" => DATA <= x"C8";
when x"26B" => DATA <= x"C9";
when x"26C" => DATA <= x"FE";
when x"26D" => DATA <= x"B0";
when x"26E" => DATA <= x"3B";
when x"26F" => DATA <= x"85";
when x"270" => DATA <= x"53";
when x"271" => DATA <= x"BD";
when x"272" => DATA <= x"EE";
when x"273" => DATA <= x"C0";
when x"274" => DATA <= x"90";
when x"275" => DATA <= x"29";
when x"276" => DATA <= x"A6";
when x"277" => DATA <= x"04";
when x"278" => DATA <= x"60";
when x"279" => DATA <= x"A2";
when x"27A" => DATA <= x"0E";
when x"27B" => DATA <= x"A4";
when x"27C" => DATA <= x"03";
when x"27D" => DATA <= x"88";
when x"27E" => DATA <= x"C8";
when x"27F" => DATA <= x"B1";
when x"280" => DATA <= x"05";
when x"281" => DATA <= x"C9";
when x"282" => DATA <= x"20";
when x"283" => DATA <= x"F0";
when x"284" => DATA <= x"F9";
when x"285" => DATA <= x"DD";
when x"286" => DATA <= x"DD";
when x"287" => DATA <= x"C1";
when x"288" => DATA <= x"F0";
when x"289" => DATA <= x"0C";
when x"28A" => DATA <= x"85";
when x"28B" => DATA <= x"52";
when x"28C" => DATA <= x"E8";
when x"28D" => DATA <= x"BD";
when x"28E" => DATA <= x"DD";
when x"28F" => DATA <= x"C1";
when x"290" => DATA <= x"30";
when x"291" => DATA <= x"16";
when x"292" => DATA <= x"C5";
when x"293" => DATA <= x"52";
when x"294" => DATA <= x"D0";
when x"295" => DATA <= x"F6";
when x"296" => DATA <= x"BD";
when x"297" => DATA <= x"12";
when x"298" => DATA <= x"C2";
when x"299" => DATA <= x"85";
when x"29A" => DATA <= x"53";
when x"29B" => DATA <= x"BD";
when x"29C" => DATA <= x"F8";
when x"29D" => DATA <= x"C1";
when x"29E" => DATA <= x"C8";
when x"29F" => DATA <= x"85";
when x"2A0" => DATA <= x"52";
when x"2A1" => DATA <= x"84";
when x"2A2" => DATA <= x"03";
when x"2A3" => DATA <= x"A6";
when x"2A4" => DATA <= x"04";
when x"2A5" => DATA <= x"6C";
when x"2A6" => DATA <= x"52";
when x"2A7" => DATA <= x"00";
when x"2A8" => DATA <= x"C9";
when x"2A9" => DATA <= x"FE";
when x"2AA" => DATA <= x"F0";
when x"2AB" => DATA <= x"CA";
when x"2AC" => DATA <= x"00";
when x"2AD" => DATA <= x"20";
when x"2AE" => DATA <= x"E4";
when x"2AF" => DATA <= x"C4";
when x"2B0" => DATA <= x"D0";
when x"2B1" => DATA <= x"04";
when x"2B2" => DATA <= x"A9";
when x"2B3" => DATA <= x"29";
when x"2B4" => DATA <= x"85";
when x"2B5" => DATA <= x"12";
when x"2B6" => DATA <= x"A9";
when x"2B7" => DATA <= x"0D";
when x"2B8" => DATA <= x"A4";
when x"2B9" => DATA <= x"12";
when x"2BA" => DATA <= x"84";
when x"2BB" => DATA <= x"0E";
when x"2BC" => DATA <= x"A0";
when x"2BD" => DATA <= x"00";
when x"2BE" => DATA <= x"84";
when x"2BF" => DATA <= x"0D";
when x"2C0" => DATA <= x"91";
when x"2C1" => DATA <= x"0D";
when x"2C2" => DATA <= x"A9";
when x"2C3" => DATA <= x"FF";
when x"2C4" => DATA <= x"C8";
when x"2C5" => DATA <= x"91";
when x"2C6" => DATA <= x"0D";
when x"2C7" => DATA <= x"C8";
when x"2C8" => DATA <= x"84";
when x"2C9" => DATA <= x"0D";
when x"2CA" => DATA <= x"A9";
when x"2CB" => DATA <= x"08";
when x"2CC" => DATA <= x"8D";
when x"2CD" => DATA <= x"21";
when x"2CE" => DATA <= x"03";
when x"2CF" => DATA <= x"A9";
when x"2D0" => DATA <= x"3E";
when x"2D1" => DATA <= x"D8";
when x"2D2" => DATA <= x"20";
when x"2D3" => DATA <= x"0F";
when x"2D4" => DATA <= x"CD";
when x"2D5" => DATA <= x"A2";
when x"2D6" => DATA <= x"01";
when x"2D7" => DATA <= x"86";
when x"2D8" => DATA <= x"06";
when x"2D9" => DATA <= x"CA";
when x"2DA" => DATA <= x"86";
when x"2DB" => DATA <= x"05";
when x"2DC" => DATA <= x"86";
when x"2DD" => DATA <= x"01";
when x"2DE" => DATA <= x"86";
when x"2DF" => DATA <= x"02";
when x"2E0" => DATA <= x"A9";
when x"2E1" => DATA <= x"D8";
when x"2E2" => DATA <= x"8D";
when x"2E3" => DATA <= x"02";
when x"2E4" => DATA <= x"02";
when x"2E5" => DATA <= x"A9";
when x"2E6" => DATA <= x"C9";
when x"2E7" => DATA <= x"8D";
when x"2E8" => DATA <= x"03";
when x"2E9" => DATA <= x"02";
when x"2EA" => DATA <= x"A9";
when x"2EB" => DATA <= x"E7";
when x"2EC" => DATA <= x"85";
when x"2ED" => DATA <= x"10";
when x"2EE" => DATA <= x"A9";
when x"2EF" => DATA <= x"C9";
when x"2F0" => DATA <= x"85";
when x"2F1" => DATA <= x"11";
when x"2F2" => DATA <= x"A2";
when x"2F3" => DATA <= x"FF";
when x"2F4" => DATA <= x"9A";
when x"2F5" => DATA <= x"A9";
when x"2F6" => DATA <= x"00";
when x"2F7" => DATA <= x"85";
when x"2F8" => DATA <= x"04";
when x"2F9" => DATA <= x"85";
when x"2FA" => DATA <= x"03";
when x"2FB" => DATA <= x"85";
when x"2FC" => DATA <= x"15";
when x"2FD" => DATA <= x"85";
when x"2FE" => DATA <= x"13";
when x"2FF" => DATA <= x"85";
when x"300" => DATA <= x"14";
when x"301" => DATA <= x"A2";
when x"302" => DATA <= x"34";
when x"303" => DATA <= x"9D";
when x"304" => DATA <= x"8C";
when x"305" => DATA <= x"03";
when x"306" => DATA <= x"CA";
when x"307" => DATA <= x"D0";
when x"308" => DATA <= x"FA";
when x"309" => DATA <= x"20";
when x"30A" => DATA <= x"34";
when x"30B" => DATA <= x"C4";
when x"30C" => DATA <= x"B0";
when x"30D" => DATA <= x"21";
when x"30E" => DATA <= x"20";
when x"30F" => DATA <= x"6A";
when x"310" => DATA <= x"C4";
when x"311" => DATA <= x"90";
when x"312" => DATA <= x"03";
when x"313" => DATA <= x"4C";
when x"314" => DATA <= x"C9";
when x"315" => DATA <= x"CD";
when x"316" => DATA <= x"A2";
when x"317" => DATA <= x"7D";
when x"318" => DATA <= x"4C";
when x"319" => DATA <= x"33";
when x"31A" => DATA <= x"C2";
when x"31B" => DATA <= x"20";
when x"31C" => DATA <= x"34";
when x"31D" => DATA <= x"C4";
when x"31E" => DATA <= x"B0";
when x"31F" => DATA <= x"0F";
when x"320" => DATA <= x"A2";
when x"321" => DATA <= x"7F";
when x"322" => DATA <= x"4C";
when x"323" => DATA <= x"33";
when x"324" => DATA <= x"C2";
when x"325" => DATA <= x"20";
when x"326" => DATA <= x"34";
when x"327" => DATA <= x"C4";
when x"328" => DATA <= x"B0";
when x"329" => DATA <= x"05";
when x"32A" => DATA <= x"A2";
when x"32B" => DATA <= x"10";
when x"32C" => DATA <= x"4C";
when x"32D" => DATA <= x"7B";
when x"32E" => DATA <= x"C2";
when x"32F" => DATA <= x"A2";
when x"330" => DATA <= x"14";
when x"331" => DATA <= x"4C";
when x"332" => DATA <= x"7B";
when x"333" => DATA <= x"C2";
when x"334" => DATA <= x"38";
when x"335" => DATA <= x"66";
when x"336" => DATA <= x"0F";
when x"337" => DATA <= x"20";
when x"338" => DATA <= x"72";
when x"339" => DATA <= x"C3";
when x"33A" => DATA <= x"A2";
when x"33B" => DATA <= x"2E";
when x"33C" => DATA <= x"4C";
when x"33D" => DATA <= x"33";
when x"33E" => DATA <= x"C2";
when x"33F" => DATA <= x"20";
when x"340" => DATA <= x"8B";
when x"341" => DATA <= x"C7";
when x"342" => DATA <= x"20";
when x"343" => DATA <= x"CB";
when x"344" => DATA <= x"C3";
when x"345" => DATA <= x"A5";
when x"346" => DATA <= x"0F";
when x"347" => DATA <= x"30";
when x"348" => DATA <= x"21";
when x"349" => DATA <= x"A2";
when x"34A" => DATA <= x"00";
when x"34B" => DATA <= x"86";
when x"34C" => DATA <= x"27";
when x"34D" => DATA <= x"A0";
when x"34E" => DATA <= x"00";
when x"34F" => DATA <= x"B9";
when x"350" => DATA <= x"52";
when x"351" => DATA <= x"00";
when x"352" => DATA <= x"48";
when x"353" => DATA <= x"29";
when x"354" => DATA <= x"0F";
when x"355" => DATA <= x"95";
when x"356" => DATA <= x"45";
when x"357" => DATA <= x"68";
when x"358" => DATA <= x"4A";
when x"359" => DATA <= x"4A";
when x"35A" => DATA <= x"4A";
when x"35B" => DATA <= x"4A";
when x"35C" => DATA <= x"E8";
when x"35D" => DATA <= x"95";
when x"35E" => DATA <= x"45";
when x"35F" => DATA <= x"E8";
when x"360" => DATA <= x"C8";
when x"361" => DATA <= x"C0";
when x"362" => DATA <= x"04";
when x"363" => DATA <= x"90";
when x"364" => DATA <= x"EA";
when x"365" => DATA <= x"20";
when x"366" => DATA <= x"C8";
when x"367" => DATA <= x"C5";
when x"368" => DATA <= x"30";
when x"369" => DATA <= x"CD";
when x"36A" => DATA <= x"20";
when x"36B" => DATA <= x"89";
when x"36C" => DATA <= x"C5";
when x"36D" => DATA <= x"30";
when x"36E" => DATA <= x"C8";
when x"36F" => DATA <= x"20";
when x"370" => DATA <= x"54";
when x"371" => DATA <= x"CD";
when x"372" => DATA <= x"A2";
when x"373" => DATA <= x"18";
when x"374" => DATA <= x"4C";
when x"375" => DATA <= x"7B";
when x"376" => DATA <= x"C2";
when x"377" => DATA <= x"20";
when x"378" => DATA <= x"4C";
when x"379" => DATA <= x"CA";
when x"37A" => DATA <= x"B1";
when x"37B" => DATA <= x"05";
when x"37C" => DATA <= x"C8";
when x"37D" => DATA <= x"C9";
when x"37E" => DATA <= x"0D";
when x"37F" => DATA <= x"F0";
when x"380" => DATA <= x"1C";
when x"381" => DATA <= x"84";
when x"382" => DATA <= x"03";
when x"383" => DATA <= x"C9";
when x"384" => DATA <= x"22";
when x"385" => DATA <= x"D0";
when x"386" => DATA <= x"F0";
when x"387" => DATA <= x"B1";
when x"388" => DATA <= x"05";
when x"389" => DATA <= x"C9";
when x"38A" => DATA <= x"22";
when x"38B" => DATA <= x"D0";
when x"38C" => DATA <= x"E5";
when x"38D" => DATA <= x"C8";
when x"38E" => DATA <= x"B0";
when x"38F" => DATA <= x"E7";
when x"390" => DATA <= x"20";
when x"391" => DATA <= x"8B";
when x"392" => DATA <= x"C7";
when x"393" => DATA <= x"20";
when x"394" => DATA <= x"CB";
when x"395" => DATA <= x"C3";
when x"396" => DATA <= x"05";
when x"397" => DATA <= x"54";
when x"398" => DATA <= x"05";
when x"399" => DATA <= x"53";
when x"39A" => DATA <= x"F0";
when x"39B" => DATA <= x"0E";
when x"39C" => DATA <= x"A0";
when x"39D" => DATA <= x"00";
when x"39E" => DATA <= x"B1";
when x"39F" => DATA <= x"52";
when x"3A0" => DATA <= x"C9";
when x"3A1" => DATA <= x"0D";
when x"3A2" => DATA <= x"F0";
when x"3A3" => DATA <= x"93";
when x"3A4" => DATA <= x"20";
when x"3A5" => DATA <= x"4C";
when x"3A6" => DATA <= x"CA";
when x"3A7" => DATA <= x"C8";
when x"3A8" => DATA <= x"D0";
when x"3A9" => DATA <= x"F4";
when x"3AA" => DATA <= x"A5";
when x"3AB" => DATA <= x"52";
when x"3AC" => DATA <= x"20";
when x"3AD" => DATA <= x"4C";
when x"3AE" => DATA <= x"CA";
when x"3AF" => DATA <= x"4C";
when x"3B0" => DATA <= x"37";
when x"3B1" => DATA <= x"C3";
when x"3B2" => DATA <= x"20";
when x"3B3" => DATA <= x"C8";
when x"3B4" => DATA <= x"C3";
when x"3B5" => DATA <= x"20";
when x"3B6" => DATA <= x"E4";
when x"3B7" => DATA <= x"C4";
when x"3B8" => DATA <= x"AD";
when x"3B9" => DATA <= x"22";
when x"3BA" => DATA <= x"03";
when x"3BB" => DATA <= x"AE";
when x"3BC" => DATA <= x"39";
when x"3BD" => DATA <= x"03";
when x"3BE" => DATA <= x"AC";
when x"3BF" => DATA <= x"3A";
when x"3C0" => DATA <= x"03";
when x"3C1" => DATA <= x"20";
when x"3C2" => DATA <= x"A5";
when x"3C3" => DATA <= x"C2";
when x"3C4" => DATA <= x"D8";
when x"3C5" => DATA <= x"4C";
when x"3C6" => DATA <= x"5B";
when x"3C7" => DATA <= x"C5";
when x"3C8" => DATA <= x"20";
when x"3C9" => DATA <= x"BC";
when x"3CA" => DATA <= x"C8";
when x"3CB" => DATA <= x"A0";
when x"3CC" => DATA <= x"52";
when x"3CD" => DATA <= x"CA";
when x"3CE" => DATA <= x"86";
when x"3CF" => DATA <= x"04";
when x"3D0" => DATA <= x"B5";
when x"3D1" => DATA <= x"16";
when x"3D2" => DATA <= x"99";
when x"3D3" => DATA <= x"00";
when x"3D4" => DATA <= x"00";
when x"3D5" => DATA <= x"B5";
when x"3D6" => DATA <= x"25";
when x"3D7" => DATA <= x"99";
when x"3D8" => DATA <= x"01";
when x"3D9" => DATA <= x"00";
when x"3DA" => DATA <= x"B5";
when x"3DB" => DATA <= x"34";
when x"3DC" => DATA <= x"99";
when x"3DD" => DATA <= x"02";
when x"3DE" => DATA <= x"00";
when x"3DF" => DATA <= x"B5";
when x"3E0" => DATA <= x"43";
when x"3E1" => DATA <= x"99";
when x"3E2" => DATA <= x"03";
when x"3E3" => DATA <= x"00";
when x"3E4" => DATA <= x"60";
when x"3E5" => DATA <= x"20";
when x"3E6" => DATA <= x"E1";
when x"3E7" => DATA <= x"C4";
when x"3E8" => DATA <= x"20";
when x"3E9" => DATA <= x"2F";
when x"3EA" => DATA <= x"CA";
when x"3EB" => DATA <= x"4C";
when x"3EC" => DATA <= x"5B";
when x"3ED" => DATA <= x"C5";
when x"3EE" => DATA <= x"20";
when x"3EF" => DATA <= x"BC";
when x"3F0" => DATA <= x"C8";
when x"3F1" => DATA <= x"20";
when x"3F2" => DATA <= x"93";
when x"3F3" => DATA <= x"CE";
when x"3F4" => DATA <= x"B5";
when x"3F5" => DATA <= x"26";
when x"3F6" => DATA <= x"C8";
when x"3F7" => DATA <= x"91";
when x"3F8" => DATA <= x"52";
when x"3F9" => DATA <= x"C8";
when x"3FA" => DATA <= x"B5";
when x"3FB" => DATA <= x"35";
when x"3FC" => DATA <= x"91";
when x"3FD" => DATA <= x"52";
when x"3FE" => DATA <= x"C8";
when x"3FF" => DATA <= x"B5";
when x"400" => DATA <= x"44";
when x"401" => DATA <= x"91";
when x"402" => DATA <= x"52";
when x"403" => DATA <= x"4C";
when x"404" => DATA <= x"5B";
when x"405" => DATA <= x"C5";
when x"406" => DATA <= x"20";
when x"407" => DATA <= x"BC";
when x"408" => DATA <= x"C8";
when x"409" => DATA <= x"20";
when x"40A" => DATA <= x"93";
when x"40B" => DATA <= x"CE";
when x"40C" => DATA <= x"4C";
when x"40D" => DATA <= x"5B";
when x"40E" => DATA <= x"C5";
when x"40F" => DATA <= x"A2";
when x"410" => DATA <= x"00";
when x"411" => DATA <= x"B1";
when x"412" => DATA <= x"05";
when x"413" => DATA <= x"9D";
when x"414" => DATA <= x"00";
when x"415" => DATA <= x"01";
when x"416" => DATA <= x"84";
when x"417" => DATA <= x"03";
when x"418" => DATA <= x"C8";
when x"419" => DATA <= x"E8";
when x"41A" => DATA <= x"C9";
when x"41B" => DATA <= x"0D";
when x"41C" => DATA <= x"D0";
when x"41D" => DATA <= x"F3";
when x"41E" => DATA <= x"20";
when x"41F" => DATA <= x"F7";
when x"420" => DATA <= x"FF";
when x"421" => DATA <= x"4C";
when x"422" => DATA <= x"58";
when x"423" => DATA <= x"C5";
when x"424" => DATA <= x"AD";
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when x"426" => DATA <= x"D0";
when x"427" => DATA <= x"C9";
when x"428" => DATA <= x"AA";
when x"429" => DATA <= x"D0";
when x"42A" => DATA <= x"38";
when x"42B" => DATA <= x"4A";
when x"42C" => DATA <= x"CD";
when x"42D" => DATA <= x"01";
when x"42E" => DATA <= x"D0";
when x"42F" => DATA <= x"D0";
when x"430" => DATA <= x"32";
when x"431" => DATA <= x"A4";
when x"432" => DATA <= x"5E";
when x"433" => DATA <= x"60";
when x"434" => DATA <= x"A4";
when x"435" => DATA <= x"03";
when x"436" => DATA <= x"10";
when x"437" => DATA <= x"03";
when x"438" => DATA <= x"C8";
when x"439" => DATA <= x"84";
when x"43A" => DATA <= x"03";
when x"43B" => DATA <= x"B1";
when x"43C" => DATA <= x"05";
when x"43D" => DATA <= x"C9";
when x"43E" => DATA <= x"20";
when x"43F" => DATA <= x"F0";
when x"440" => DATA <= x"F7";
when x"441" => DATA <= x"C9";
when x"442" => DATA <= x"5B";
when x"443" => DATA <= x"B0";
when x"444" => DATA <= x"1E";
when x"445" => DATA <= x"E9";
when x"446" => DATA <= x"3F";
when x"447" => DATA <= x"90";
when x"448" => DATA <= x"1B";
when x"449" => DATA <= x"A6";
when x"44A" => DATA <= x"04";
when x"44B" => DATA <= x"95";
when x"44C" => DATA <= x"16";
when x"44D" => DATA <= x"C8";
when x"44E" => DATA <= x"B1";
when x"44F" => DATA <= x"05";
when x"450" => DATA <= x"C9";
when x"451" => DATA <= x"2E";
when x"452" => DATA <= x"F0";
when x"453" => DATA <= x"0F";
when x"454" => DATA <= x"C9";
when x"455" => DATA <= x"5B";
when x"456" => DATA <= x"B0";
when x"457" => DATA <= x"04";
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when x"459" => DATA <= x"40";
when x"45A" => DATA <= x"B0";
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when x"45C" => DATA <= x"E8";
when x"45D" => DATA <= x"86";
when x"45E" => DATA <= x"04";
when x"45F" => DATA <= x"38";
when x"460" => DATA <= x"84";
when x"461" => DATA <= x"03";
when x"462" => DATA <= x"60";
when x"463" => DATA <= x"18";
when x"464" => DATA <= x"60";
when x"465" => DATA <= x"20";
when x"466" => DATA <= x"34";
when x"467" => DATA <= x"C4";
when x"468" => DATA <= x"B0";
when x"469" => DATA <= x"BB";
when x"46A" => DATA <= x"A2";
when x"46B" => DATA <= x"00";
when x"46C" => DATA <= x"A4";
when x"46D" => DATA <= x"03";
when x"46E" => DATA <= x"86";
when x"46F" => DATA <= x"52";
when x"470" => DATA <= x"86";
when x"471" => DATA <= x"53";
when x"472" => DATA <= x"86";
when x"473" => DATA <= x"54";
when x"474" => DATA <= x"86";
when x"475" => DATA <= x"55";
when x"476" => DATA <= x"88";
when x"477" => DATA <= x"C8";
when x"478" => DATA <= x"B1";
when x"479" => DATA <= x"05";
when x"47A" => DATA <= x"38";
when x"47B" => DATA <= x"E9";
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when x"47D" => DATA <= x"30";
when x"47E" => DATA <= x"54";
when x"47F" => DATA <= x"C9";
when x"480" => DATA <= x"0A";
when x"481" => DATA <= x"B0";
when x"482" => DATA <= x"50";
when x"483" => DATA <= x"A6";
when x"484" => DATA <= x"53";
when x"485" => DATA <= x"48";
when x"486" => DATA <= x"A5";
when x"487" => DATA <= x"55";
when x"488" => DATA <= x"48";
when x"489" => DATA <= x"A5";
when x"48A" => DATA <= x"54";
when x"48B" => DATA <= x"48";
when x"48C" => DATA <= x"A5";
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when x"48E" => DATA <= x"0A";
when x"48F" => DATA <= x"26";
when x"490" => DATA <= x"53";
when x"491" => DATA <= x"26";
when x"492" => DATA <= x"54";
when x"493" => DATA <= x"26";
when x"494" => DATA <= x"55";
when x"495" => DATA <= x"30";
when x"496" => DATA <= x"D4";
when x"497" => DATA <= x"0A";
when x"498" => DATA <= x"26";
when x"499" => DATA <= x"53";
when x"49A" => DATA <= x"26";
when x"49B" => DATA <= x"54";
when x"49C" => DATA <= x"26";
when x"49D" => DATA <= x"55";
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when x"49F" => DATA <= x"CB";
when x"4A0" => DATA <= x"65";
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when x"4A2" => DATA <= x"85";
when x"4A3" => DATA <= x"52";
when x"4A4" => DATA <= x"8A";
when x"4A5" => DATA <= x"65";
when x"4A6" => DATA <= x"53";
when x"4A7" => DATA <= x"85";
when x"4A8" => DATA <= x"53";
when x"4A9" => DATA <= x"68";
when x"4AA" => DATA <= x"65";
when x"4AB" => DATA <= x"54";
when x"4AC" => DATA <= x"85";
when x"4AD" => DATA <= x"54";
when x"4AE" => DATA <= x"68";
when x"4AF" => DATA <= x"65";
when x"4B0" => DATA <= x"55";
when x"4B1" => DATA <= x"06";
when x"4B2" => DATA <= x"52";
when x"4B3" => DATA <= x"26";
when x"4B4" => DATA <= x"53";
when x"4B5" => DATA <= x"26";
when x"4B6" => DATA <= x"54";
when x"4B7" => DATA <= x"2A";
when x"4B8" => DATA <= x"30";
when x"4B9" => DATA <= x"B1";
when x"4BA" => DATA <= x"85";
when x"4BB" => DATA <= x"55";
when x"4BC" => DATA <= x"68";
when x"4BD" => DATA <= x"65";
when x"4BE" => DATA <= x"52";
when x"4BF" => DATA <= x"85";
when x"4C0" => DATA <= x"52";
when x"4C1" => DATA <= x"90";
when x"4C2" => DATA <= x"0C";
when x"4C3" => DATA <= x"E6";
when x"4C4" => DATA <= x"53";
when x"4C5" => DATA <= x"D0";
when x"4C6" => DATA <= x"08";
when x"4C7" => DATA <= x"E6";
when x"4C8" => DATA <= x"54";
when x"4C9" => DATA <= x"D0";
when x"4CA" => DATA <= x"04";
when x"4CB" => DATA <= x"E6";
when x"4CC" => DATA <= x"55";
when x"4CD" => DATA <= x"30";
when x"4CE" => DATA <= x"9C";
when x"4CF" => DATA <= x"A2";
when x"4D0" => DATA <= x"FF";
when x"4D1" => DATA <= x"D0";
when x"4D2" => DATA <= x"A4";
when x"4D3" => DATA <= x"8A";
when x"4D4" => DATA <= x"F0";
when x"4D5" => DATA <= x"8D";
when x"4D6" => DATA <= x"38";
when x"4D7" => DATA <= x"84";
when x"4D8" => DATA <= x"03";
when x"4D9" => DATA <= x"A0";
when x"4DA" => DATA <= x"52";
when x"4DB" => DATA <= x"4C";
when x"4DC" => DATA <= x"9F";
when x"4DD" => DATA <= x"C9";
when x"4DE" => DATA <= x"20";
when x"4DF" => DATA <= x"79";
when x"4E0" => DATA <= x"C2";
when x"4E1" => DATA <= x"20";
when x"4E2" => DATA <= x"8B";
when x"4E3" => DATA <= x"C7";
when x"4E4" => DATA <= x"A4";
when x"4E5" => DATA <= x"03";
when x"4E6" => DATA <= x"88";
when x"4E7" => DATA <= x"C8";
when x"4E8" => DATA <= x"B1";
when x"4E9" => DATA <= x"05";
when x"4EA" => DATA <= x"C9";
when x"4EB" => DATA <= x"20";
when x"4EC" => DATA <= x"F0";
when x"4ED" => DATA <= x"F9";
when x"4EE" => DATA <= x"C9";
when x"4EF" => DATA <= x"3B";
when x"4F0" => DATA <= x"F0";
when x"4F1" => DATA <= x"04";
when x"4F2" => DATA <= x"C9";
when x"4F3" => DATA <= x"0D";
when x"4F4" => DATA <= x"D0";
when x"4F5" => DATA <= x"66";
when x"4F6" => DATA <= x"18";
when x"4F7" => DATA <= x"98";
when x"4F8" => DATA <= x"65";
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when x"4FA" => DATA <= x"85";
when x"4FB" => DATA <= x"05";
when x"4FC" => DATA <= x"90";
when x"4FD" => DATA <= x"02";
when x"4FE" => DATA <= x"E6";
when x"4FF" => DATA <= x"06";
when x"500" => DATA <= x"A0";
when x"501" => DATA <= x"01";
when x"502" => DATA <= x"84";
when x"503" => DATA <= x"03";
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when x"506" => DATA <= x"B0";
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when x"508" => DATA <= x"20";
when x"509" => DATA <= x"F0";
when x"50A" => DATA <= x"3C";
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when x"50C" => DATA <= x"20";
when x"50D" => DATA <= x"E4";
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when x"50F" => DATA <= x"88";
when x"510" => DATA <= x"B1";
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when x"512" => DATA <= x"C9";
when x"513" => DATA <= x"3B";
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when x"515" => DATA <= x"F5";
when x"516" => DATA <= x"A5";
when x"517" => DATA <= x"06";
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when x"519" => DATA <= x"01";
when x"51A" => DATA <= x"F0";
when x"51B" => DATA <= x"7A";
when x"51C" => DATA <= x"C8";
when x"51D" => DATA <= x"B1";
when x"51E" => DATA <= x"05";
when x"51F" => DATA <= x"30";
when x"520" => DATA <= x"3B";
when x"521" => DATA <= x"85";
when x"522" => DATA <= x"02";
when x"523" => DATA <= x"C8";
when x"524" => DATA <= x"B1";
when x"525" => DATA <= x"05";
when x"526" => DATA <= x"85";
when x"527" => DATA <= x"01";
when x"528" => DATA <= x"C8";
when x"529" => DATA <= x"B1";
when x"52A" => DATA <= x"05";
when x"52B" => DATA <= x"88";
when x"52C" => DATA <= x"C9";
when x"52D" => DATA <= x"61";
when x"52E" => DATA <= x"90";
when x"52F" => DATA <= x"C7";
when x"530" => DATA <= x"E9";
when x"531" => DATA <= x"61";
when x"532" => DATA <= x"C9";
when x"533" => DATA <= x"1B";
when x"534" => DATA <= x"B0";
when x"535" => DATA <= x"C0";
when x"536" => DATA <= x"C8";
when x"537" => DATA <= x"0A";
when x"538" => DATA <= x"AA";
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when x"53A" => DATA <= x"F6";
when x"53B" => DATA <= x"C4";
when x"53C" => DATA <= x"A5";
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when x"53E" => DATA <= x"9D";
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when x"540" => DATA <= x"03";
when x"541" => DATA <= x"A5";
when x"542" => DATA <= x"06";
when x"543" => DATA <= x"9D";
when x"544" => DATA <= x"8E";
when x"545" => DATA <= x"03";
when x"546" => DATA <= x"60";
when x"547" => DATA <= x"4C";
when x"548" => DATA <= x"CF";
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when x"54A" => DATA <= x"88";
when x"54B" => DATA <= x"20";
when x"54C" => DATA <= x"F6";
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when x"54F" => DATA <= x"0B";
when x"550" => DATA <= x"20";
when x"551" => DATA <= x"24";
when x"552" => DATA <= x"C4";
when x"553" => DATA <= x"90";
when x"554" => DATA <= x"03";
when x"555" => DATA <= x"6C";
when x"556" => DATA <= x"02";
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when x"559" => DATA <= x"E4";
when x"55A" => DATA <= x"C4";
when x"55B" => DATA <= x"A0";
when x"55C" => DATA <= x"00";
when x"55D" => DATA <= x"B1";
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when x"55F" => DATA <= x"C9";
when x"560" => DATA <= x"3B";
when x"561" => DATA <= x"D0";
when x"562" => DATA <= x"1A";
when x"563" => DATA <= x"4C";
when x"564" => DATA <= x"1B";
when x"565" => DATA <= x"C3";
when x"566" => DATA <= x"20";
when x"567" => DATA <= x"0C";
when x"568" => DATA <= x"C7";
when x"569" => DATA <= x"CA";
when x"56A" => DATA <= x"86";
when x"56B" => DATA <= x"04";
when x"56C" => DATA <= x"B5";
when x"56D" => DATA <= x"16";
when x"56E" => DATA <= x"F0";
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when x"570" => DATA <= x"A2";
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when x"572" => DATA <= x"4C";
when x"573" => DATA <= x"33";
when x"574" => DATA <= x"C2";
when x"575" => DATA <= x"A9";
when x"576" => DATA <= x"0D";
when x"577" => DATA <= x"88";
when x"578" => DATA <= x"C8";
when x"579" => DATA <= x"D1";
when x"57A" => DATA <= x"05";
when x"57B" => DATA <= x"D0";
when x"57C" => DATA <= x"FB";
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when x"57F" => DATA <= x"C9";
when x"580" => DATA <= x"01";
when x"581" => DATA <= x"F0";
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when x"583" => DATA <= x"20";
when x"584" => DATA <= x"1C";
when x"585" => DATA <= x"C5";
when x"586" => DATA <= x"4C";
when x"587" => DATA <= x"1B";
when x"588" => DATA <= x"C3";
when x"589" => DATA <= x"A5";
when x"58A" => DATA <= x"43";
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when x"58C" => DATA <= x"27";
when x"58D" => DATA <= x"10";
when x"58E" => DATA <= x"04";
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when x"590" => DATA <= x"20";
when x"591" => DATA <= x"C4";
when x"592" => DATA <= x"C8";
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when x"594" => DATA <= x"09";
when x"595" => DATA <= x"A9";
when x"596" => DATA <= x"00";
when x"597" => DATA <= x"95";
when x"598" => DATA <= x"45";
when x"599" => DATA <= x"38";
when x"59A" => DATA <= x"A5";
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when x"59C" => DATA <= x"FD";
when x"59D" => DATA <= x"08";
when x"59E" => DATA <= x"C6";
when x"59F" => DATA <= x"48";
when x"5A0" => DATA <= x"A5";
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when x"5A2" => DATA <= x"FD";
when x"5A3" => DATA <= x"10";
when x"5A4" => DATA <= x"C6";
when x"5A5" => DATA <= x"48";
when x"5A6" => DATA <= x"A5";
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when x"5A8" => DATA <= x"FD";
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when x"5AA" => DATA <= x"C6";
when x"5AB" => DATA <= x"A8";
when x"5AC" => DATA <= x"A5";
when x"5AD" => DATA <= x"43";
when x"5AE" => DATA <= x"FD";
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when x"5B0" => DATA <= x"C6";
when x"5B1" => DATA <= x"90";
when x"5B2" => DATA <= x"0E";
when x"5B3" => DATA <= x"85";
when x"5B4" => DATA <= x"43";
when x"5B5" => DATA <= x"84";
when x"5B6" => DATA <= x"34";
when x"5B7" => DATA <= x"68";
when x"5B8" => DATA <= x"85";
when x"5B9" => DATA <= x"25";
when x"5BA" => DATA <= x"68";
when x"5BB" => DATA <= x"85";
when x"5BC" => DATA <= x"16";
when x"5BD" => DATA <= x"F6";
when x"5BE" => DATA <= x"45";
when x"5BF" => DATA <= x"D0";
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when x"5C1" => DATA <= x"68";
when x"5C2" => DATA <= x"68";
when x"5C3" => DATA <= x"CA";
when x"5C4" => DATA <= x"10";
when x"5C5" => DATA <= x"CF";
when x"5C6" => DATA <= x"A2";
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when x"5C8" => DATA <= x"CA";
when x"5C9" => DATA <= x"F0";
when x"5CA" => DATA <= x"04";
when x"5CB" => DATA <= x"B5";
when x"5CC" => DATA <= x"45";
when x"5CD" => DATA <= x"F0";
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when x"5CF" => DATA <= x"86";
when x"5D0" => DATA <= x"52";
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when x"5D2" => DATA <= x"27";
when x"5D3" => DATA <= x"10";
when x"5D4" => DATA <= x"02";
when x"5D5" => DATA <= x"E6";
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when x"5D7" => DATA <= x"38";
when x"5D8" => DATA <= x"AD";
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when x"5DA" => DATA <= x"03";
when x"5DB" => DATA <= x"F0";
when x"5DC" => DATA <= x"02";
when x"5DD" => DATA <= x"E9";
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when x"5DF" => DATA <= x"E5";
when x"5E0" => DATA <= x"52";
when x"5E1" => DATA <= x"F0";
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when x"5E3" => DATA <= x"90";
when x"5E4" => DATA <= x"09";
when x"5E5" => DATA <= x"A8";
when x"5E6" => DATA <= x"A9";
when x"5E7" => DATA <= x"20";
when x"5E8" => DATA <= x"20";
when x"5E9" => DATA <= x"4C";
when x"5EA" => DATA <= x"CA";
when x"5EB" => DATA <= x"88";
when x"5EC" => DATA <= x"D0";
when x"5ED" => DATA <= x"F8";
when x"5EE" => DATA <= x"24";
when x"5EF" => DATA <= x"27";
when x"5F0" => DATA <= x"10";
when x"5F1" => DATA <= x"05";
when x"5F2" => DATA <= x"A9";
when x"5F3" => DATA <= x"2D";
when x"5F4" => DATA <= x"20";
when x"5F5" => DATA <= x"4C";
when x"5F6" => DATA <= x"CA";
when x"5F7" => DATA <= x"B5";
when x"5F8" => DATA <= x"45";
when x"5F9" => DATA <= x"C9";
when x"5FA" => DATA <= x"0A";
when x"5FB" => DATA <= x"90";
when x"5FC" => DATA <= x"02";
when x"5FD" => DATA <= x"69";
when x"5FE" => DATA <= x"06";
when x"5FF" => DATA <= x"69";
when x"600" => DATA <= x"30";
when x"601" => DATA <= x"20";
when x"602" => DATA <= x"4C";
when x"603" => DATA <= x"CA";
when x"604" => DATA <= x"CA";
when x"605" => DATA <= x"10";
when x"606" => DATA <= x"F0";
when x"607" => DATA <= x"60";
when x"608" => DATA <= x"01";
when x"609" => DATA <= x"0A";
when x"60A" => DATA <= x"64";
when x"60B" => DATA <= x"E8";
when x"60C" => DATA <= x"10";
when x"60D" => DATA <= x"A0";
when x"60E" => DATA <= x"40";
when x"60F" => DATA <= x"80";
when x"610" => DATA <= x"00";
when x"611" => DATA <= x"00";
when x"612" => DATA <= x"00";
when x"613" => DATA <= x"03";
when x"614" => DATA <= x"27";
when x"615" => DATA <= x"86";
when x"616" => DATA <= x"42";
when x"617" => DATA <= x"96";
when x"618" => DATA <= x"E1";
when x"619" => DATA <= x"CA";
when x"61A" => DATA <= x"00";
when x"61B" => DATA <= x"00";
when x"61C" => DATA <= x"00";
when x"61D" => DATA <= x"00";
when x"61E" => DATA <= x"00";
when x"61F" => DATA <= x"01";
when x"620" => DATA <= x"0F";
when x"621" => DATA <= x"98";
when x"622" => DATA <= x"F5";
when x"623" => DATA <= x"9A";
when x"624" => DATA <= x"00";
when x"625" => DATA <= x"00";
when x"626" => DATA <= x"00";
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when x"630" => DATA <= x"A6";
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when x"640" => DATA <= x"D0";
when x"641" => DATA <= x"FB";
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when x"660" => DATA <= x"60";
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when x"6CC" => DATA <= x"68";
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when x"6D5" => DATA <= x"68";
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when x"820" => DATA <= x"18";
when x"821" => DATA <= x"98";
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when x"824" => DATA <= x"A8";
when x"825" => DATA <= x"A5";
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when x"828" => DATA <= x"54";
when x"829" => DATA <= x"85";
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when x"82E" => DATA <= x"55";
when x"82F" => DATA <= x"85";
when x"830" => DATA <= x"5D";
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when x"833" => DATA <= x"65";
when x"834" => DATA <= x"56";
when x"835" => DATA <= x"29";
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when x"838" => DATA <= x"5E";
when x"839" => DATA <= x"06";
when x"83A" => DATA <= x"53";
when x"83B" => DATA <= x"26";
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when x"845" => DATA <= x"05";
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when x"847" => DATA <= x"05";
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when x"84A" => DATA <= x"CB";
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when x"855" => DATA <= x"28";
when x"856" => DATA <= x"10";
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when x"A49" => DATA <= x"72";
when x"A4A" => DATA <= x"03";
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when x"A4C" => DATA <= x"E6";
when x"A4D" => DATA <= x"07";
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when x"A50" => DATA <= x"02";
when x"A51" => DATA <= x"A9";
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when x"A53" => DATA <= x"20";
when x"A54" => DATA <= x"7C";
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when x"A56" => DATA <= x"A9";
when x"A57" => DATA <= x"FF";
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when x"A5B" => DATA <= x"85";
when x"A5C" => DATA <= x"04";
when x"A5D" => DATA <= x"A0";
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when x"A60" => DATA <= x"26";
when x"A61" => DATA <= x"20";
when x"A62" => DATA <= x"65";
when x"A63" => DATA <= x"C4";
when x"A64" => DATA <= x"90";
when x"A65" => DATA <= x"52";
when x"A66" => DATA <= x"20";
when x"A67" => DATA <= x"31";
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when x"A6B" => DATA <= x"20";
when x"A6C" => DATA <= x"65";
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when x"A70" => DATA <= x"86";
when x"A71" => DATA <= x"04";
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when x"A73" => DATA <= x"E4";
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when x"A75" => DATA <= x"20";
when x"A76" => DATA <= x"2E";
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when x"A78" => DATA <= x"90";
when x"A79" => DATA <= x"30";
when x"A7A" => DATA <= x"88";
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when x"A7D" => DATA <= x"A9";
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when x"A80" => DATA <= x"21";
when x"A81" => DATA <= x"03";
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when x"A83" => DATA <= x"89";
when x"A84" => DATA <= x"C5";
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when x"A86" => DATA <= x"08";
when x"A87" => DATA <= x"8D";
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when x"A8B" => DATA <= x"03";
when x"A8C" => DATA <= x"B1";
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when x"A8E" => DATA <= x"C9";
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when x"A91" => DATA <= x"06";
when x"A92" => DATA <= x"20";
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when x"A95" => DATA <= x"C8";
when x"A96" => DATA <= x"D0";
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when x"A98" => DATA <= x"20";
when x"A99" => DATA <= x"54";
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when x"A9B" => DATA <= x"20";
when x"A9C" => DATA <= x"A1";
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when x"A9E" => DATA <= x"B1";
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when x"AA0" => DATA <= x"85";
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when x"AA2" => DATA <= x"C8";
when x"AA3" => DATA <= x"B1";
when x"AA4" => DATA <= x"58";
when x"AA5" => DATA <= x"85";
when x"AA6" => DATA <= x"16";
when x"AA7" => DATA <= x"C8";
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when x"AA9" => DATA <= x"03";
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when x"AAC" => DATA <= x"18";
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when x"AAF" => DATA <= x"A5";
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when x"AB3" => DATA <= x"90";
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when x"AB5" => DATA <= x"4C";
when x"AB6" => DATA <= x"CF";
when x"AB7" => DATA <= x"C2";
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when x"AB9" => DATA <= x"31";
when x"ABA" => DATA <= x"C2";
when x"ABB" => DATA <= x"E6";
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when x"AC0" => DATA <= x"4C";
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when x"AC2" => DATA <= x"CA";
when x"AC3" => DATA <= x"A5";
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when x"AC5" => DATA <= x"A4";
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when x"ACA" => DATA <= x"26";
when x"ACB" => DATA <= x"B0";
when x"ACC" => DATA <= x"A1";
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when x"ACE" => DATA <= x"34";
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when x"AD2" => DATA <= x"F0";
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when x"ADA" => DATA <= x"D9";
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when x"ADD" => DATA <= x"F0";
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when x"AE0" => DATA <= x"84";
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when x"AE4" => DATA <= x"00";
when x"AE5" => DATA <= x"BE";
when x"AE6" => DATA <= x"3F";
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when x"AE8" => DATA <= x"18";
when x"AE9" => DATA <= x"BD";
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when x"AEC" => DATA <= x"79";
when x"AED" => DATA <= x"4A";
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when x"AEF" => DATA <= x"9D";
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when x"AF8" => DATA <= x"55";
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when x"AFE" => DATA <= x"53";
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when x"B00" => DATA <= x"57";
when x"B01" => DATA <= x"03";
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when x"B03" => DATA <= x"60";
when x"B04" => DATA <= x"02";
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when x"B10" => DATA <= x"9D";
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when x"B16" => DATA <= x"38";
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when x"B30" => DATA <= x"05";
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when x"B33" => DATA <= x"54";
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when x"B4E" => DATA <= x"06";
when x"B4F" => DATA <= x"4C";
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when x"B51" => DATA <= x"CB";
when x"B52" => DATA <= x"C6";
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when x"B54" => DATA <= x"4C";
when x"B55" => DATA <= x"58";
when x"B56" => DATA <= x"C5";
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when x"B59" => DATA <= x"C4";
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when x"B5B" => DATA <= x"11";
when x"B5C" => DATA <= x"20";
when x"B5D" => DATA <= x"79";
when x"B5E" => DATA <= x"C2";
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when x"B60" => DATA <= x"2C";
when x"B61" => DATA <= x"CA";
when x"B62" => DATA <= x"98";
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when x"B75" => DATA <= x"56";
when x"B76" => DATA <= x"02";
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when x"B7E" => DATA <= x"4C";
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when x"B80" => DATA <= x"C2";
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when x"B84" => DATA <= x"A4";
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when x"B91" => DATA <= x"82";
when x"B92" => DATA <= x"02";
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when x"B95" => DATA <= x"99";
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when x"BA0" => DATA <= x"33";
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when x"BA5" => DATA <= x"A4";
when x"BA6" => DATA <= x"15";
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when x"BAC" => DATA <= x"99";
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when x"BB1" => DATA <= x"99";
when x"BB2" => DATA <= x"56";
when x"BB3" => DATA <= x"02";
when x"BB4" => DATA <= x"B5";
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when x"BB6" => DATA <= x"99";
when x"BB7" => DATA <= x"61";
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when x"BBB" => DATA <= x"99";
when x"BBC" => DATA <= x"6C";
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when x"BC2" => DATA <= x"15";
when x"BC3" => DATA <= x"A5";
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when x"BC5" => DATA <= x"99";
when x"BC6" => DATA <= x"A3";
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when x"BC8" => DATA <= x"A5";
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when x"BCA" => DATA <= x"99";
when x"BCB" => DATA <= x"AE";
when x"BCC" => DATA <= x"02";
when x"BCD" => DATA <= x"E6";
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when x"BCF" => DATA <= x"4C";
when x"BD0" => DATA <= x"1B";
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when x"BD2" => DATA <= x"20";
when x"BD3" => DATA <= x"1F";
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when x"BDC" => DATA <= x"B0";
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when x"BE0" => DATA <= x"99";
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when x"BE2" => DATA <= x"02";
when x"BE3" => DATA <= x"A5";
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when x"BE5" => DATA <= x"99";
when x"BE6" => DATA <= x"DD";
when x"BE7" => DATA <= x"02";
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when x"BEA" => DATA <= x"90";
when x"BEB" => DATA <= x"1F";
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when x"BED" => DATA <= x"E4";
when x"BEE" => DATA <= x"C4";
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when x"BF0" => DATA <= x"14";
when x"BF1" => DATA <= x"F0";
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when x"BF3" => DATA <= x"C6";
when x"BF4" => DATA <= x"14";
when x"BF5" => DATA <= x"B9";
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when x"BFC" => DATA <= x"02";
when x"BFD" => DATA <= x"85";
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when x"C00" => DATA <= x"00";
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when x"C03" => DATA <= x"1B";
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when x"C05" => DATA <= x"20";
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when x"C08" => DATA <= x"20";
when x"C09" => DATA <= x"E4";
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when x"C0C" => DATA <= x"57";
when x"C0D" => DATA <= x"D0";
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when x"C0F" => DATA <= x"20";
when x"C10" => DATA <= x"2E";
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when x"C12" => DATA <= x"B0";
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when x"C14" => DATA <= x"A4";
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when x"C16" => DATA <= x"A5";
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when x"C18" => DATA <= x"84";
when x"C19" => DATA <= x"05";
when x"C1A" => DATA <= x"4C";
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when x"C1C" => DATA <= x"CB";
when x"C1D" => DATA <= x"00";
when x"C1E" => DATA <= x"C8";
when x"C1F" => DATA <= x"B1";
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when x"C21" => DATA <= x"C9";
when x"C22" => DATA <= x"20";
when x"C23" => DATA <= x"F0";
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when x"C25" => DATA <= x"C9";
when x"C26" => DATA <= x"61";
when x"C27" => DATA <= x"90";
when x"C28" => DATA <= x"50";
when x"C29" => DATA <= x"85";
when x"C2A" => DATA <= x"57";
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when x"C2C" => DATA <= x"61";
when x"C2D" => DATA <= x"C9";
when x"C2E" => DATA <= x"1B";
when x"C2F" => DATA <= x"B0";
when x"C30" => DATA <= x"48";
when x"C31" => DATA <= x"0A";
when x"C32" => DATA <= x"AA";
when x"C33" => DATA <= x"BD";
when x"C34" => DATA <= x"8D";
when x"C35" => DATA <= x"03";
when x"C36" => DATA <= x"85";
when x"C37" => DATA <= x"58";
when x"C38" => DATA <= x"20";
when x"C39" => DATA <= x"F6";
when x"C3A" => DATA <= x"C4";
when x"C3B" => DATA <= x"BD";
when x"C3C" => DATA <= x"8E";
when x"C3D" => DATA <= x"03";
when x"C3E" => DATA <= x"85";
when x"C3F" => DATA <= x"59";
when x"C40" => DATA <= x"05";
when x"C41" => DATA <= x"58";
when x"C42" => DATA <= x"D0";
when x"C43" => DATA <= x"34";
when x"C44" => DATA <= x"A8";
when x"C45" => DATA <= x"A5";
when x"C46" => DATA <= x"12";
when x"C47" => DATA <= x"85";
when x"C48" => DATA <= x"59";
when x"C49" => DATA <= x"88";
when x"C4A" => DATA <= x"A9";
when x"C4B" => DATA <= x"0D";
when x"C4C" => DATA <= x"C8";
when x"C4D" => DATA <= x"D1";
when x"C4E" => DATA <= x"58";
when x"C4F" => DATA <= x"D0";
when x"C50" => DATA <= x"FB";
when x"C51" => DATA <= x"C8";
when x"C52" => DATA <= x"B1";
when x"C53" => DATA <= x"58";
when x"C54" => DATA <= x"30";
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when x"C57" => DATA <= x"02";
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when x"C5B" => DATA <= x"85";
when x"C5C" => DATA <= x"01";
when x"C5D" => DATA <= x"C8";
when x"C5E" => DATA <= x"B1";
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when x"C60" => DATA <= x"88";
when x"C61" => DATA <= x"C5";
when x"C62" => DATA <= x"57";
when x"C63" => DATA <= x"F0";
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when x"C65" => DATA <= x"20";
when x"C66" => DATA <= x"A1";
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when x"C68" => DATA <= x"4C";
when x"C69" => DATA <= x"4A";
when x"C6A" => DATA <= x"CC";
when x"C6B" => DATA <= x"20";
when x"C6C" => DATA <= x"A2";
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when x"C6F" => DATA <= x"58";
when x"C70" => DATA <= x"9D";
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when x"C78" => DATA <= x"60";
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when x"C7A" => DATA <= x"BC";
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when x"C7C" => DATA <= x"A9";
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when x"C80" => DATA <= x"60";
when x"C81" => DATA <= x"20";
when x"C82" => DATA <= x"72";
when x"C83" => DATA <= x"C3";
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when x"C85" => DATA <= x"34";
when x"C86" => DATA <= x"C4";
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when x"C8C" => DATA <= x"33";
when x"C8D" => DATA <= x"C2";
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when x"C8F" => DATA <= x"09";
when x"C90" => DATA <= x"CD";
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when x"C93" => DATA <= x"48";
when x"C94" => DATA <= x"A5";
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when x"C96" => DATA <= x"48";
when x"C97" => DATA <= x"A5";
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when x"C9C" => DATA <= x"84";
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when x"CA0" => DATA <= x"06";
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when x"CAC" => DATA <= x"85";
when x"CAD" => DATA <= x"06";
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when x"CB4" => DATA <= x"33";
when x"CB5" => DATA <= x"C2";
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when x"CBA" => DATA <= x"54";
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when x"CBD" => DATA <= x"C3";
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when x"CBF" => DATA <= x"09";
when x"CC0" => DATA <= x"CD";
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when x"CC2" => DATA <= x"40";
when x"CC3" => DATA <= x"A0";
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when x"CC5" => DATA <= x"BD";
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when x"CC8" => DATA <= x"91";
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when x"CCA" => DATA <= x"C9";
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when x"CCC" => DATA <= x"F0";
when x"CCD" => DATA <= x"B3";
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when x"CCF" => DATA <= x"C8";
when x"CD0" => DATA <= x"D0";
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when x"CD2" => DATA <= x"20";
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when x"CD6" => DATA <= x"13";
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when x"CE0" => DATA <= x"C6";
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when x"CED" => DATA <= x"4C";
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when x"CF0" => DATA <= x"A6";
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when x"CF2" => DATA <= x"E0";
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when x"D14" => DATA <= x"84";
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when x"E3C" => DATA <= x"A9";
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when x"E3E" => DATA <= x"91";
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when x"E42" => DATA <= x"D0";
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when x"E44" => DATA <= x"0A";
when x"E45" => DATA <= x"91";
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when x"E49" => DATA <= x"D0";
when x"E4A" => DATA <= x"AB";
when x"E4B" => DATA <= x"B1";
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when x"E4D" => DATA <= x"91";
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when x"E4F" => DATA <= x"98";
when x"E50" => DATA <= x"D0";
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when x"E52" => DATA <= x"C6";
when x"E53" => DATA <= x"55";
when x"E54" => DATA <= x"C6";
when x"E55" => DATA <= x"53";
when x"E56" => DATA <= x"88";
when x"E57" => DATA <= x"98";
when x"E58" => DATA <= x"65";
when x"E59" => DATA <= x"54";
when x"E5A" => DATA <= x"A6";
when x"E5B" => DATA <= x"55";
when x"E5C" => DATA <= x"90";
when x"E5D" => DATA <= x"01";
when x"E5E" => DATA <= x"E8";
when x"E5F" => DATA <= x"C5";
when x"E60" => DATA <= x"58";
when x"E61" => DATA <= x"8A";
when x"E62" => DATA <= x"E5";
when x"E63" => DATA <= x"59";
when x"E64" => DATA <= x"B0";
when x"E65" => DATA <= x"E5";
when x"E66" => DATA <= x"A0";
when x"E67" => DATA <= x"01";
when x"E68" => DATA <= x"A5";
when x"E69" => DATA <= x"25";
when x"E6A" => DATA <= x"91";
when x"E6B" => DATA <= x"58";
when x"E6C" => DATA <= x"C8";
when x"E6D" => DATA <= x"A5";
when x"E6E" => DATA <= x"16";
when x"E6F" => DATA <= x"91";
when x"E70" => DATA <= x"58";
when x"E71" => DATA <= x"38";
when x"E72" => DATA <= x"20";
when x"E73" => DATA <= x"A2";
when x"E74" => DATA <= x"CE";
when x"E75" => DATA <= x"A0";
when x"E76" => DATA <= x"FF";
when x"E77" => DATA <= x"C8";
when x"E78" => DATA <= x"B1";
when x"E79" => DATA <= x"56";
when x"E7A" => DATA <= x"91";
when x"E7B" => DATA <= x"58";
when x"E7C" => DATA <= x"C9";
when x"E7D" => DATA <= x"0D";
when x"E7E" => DATA <= x"D0";
when x"E7F" => DATA <= x"F7";
when x"E80" => DATA <= x"4C";
when x"E81" => DATA <= x"CF";
when x"E82" => DATA <= x"C2";
when x"E83" => DATA <= x"20";
when x"E84" => DATA <= x"E4";
when x"E85" => DATA <= x"C4";
when x"E86" => DATA <= x"A0";
when x"E87" => DATA <= x"00";
when x"E88" => DATA <= x"84";
when x"E89" => DATA <= x"05";
when x"E8A" => DATA <= x"84";
when x"E8B" => DATA <= x"03";
when x"E8C" => DATA <= x"A5";
when x"E8D" => DATA <= x"12";
when x"E8E" => DATA <= x"85";
when x"E8F" => DATA <= x"06";
when x"E90" => DATA <= x"4C";
when x"E91" => DATA <= x"5B";
when x"E92" => DATA <= x"C5";
when x"E93" => DATA <= x"20";
when x"E94" => DATA <= x"DE";
when x"E95" => DATA <= x"C4";
when x"E96" => DATA <= x"CA";
when x"E97" => DATA <= x"20";
when x"E98" => DATA <= x"CB";
when x"E99" => DATA <= x"C3";
when x"E9A" => DATA <= x"A0";
when x"E9B" => DATA <= x"00";
when x"E9C" => DATA <= x"B5";
when x"E9D" => DATA <= x"17";
when x"E9E" => DATA <= x"91";
when x"E9F" => DATA <= x"52";
when x"EA0" => DATA <= x"60";
when x"EA1" => DATA <= x"18";
when x"EA2" => DATA <= x"98";
when x"EA3" => DATA <= x"65";
when x"EA4" => DATA <= x"58";
when x"EA5" => DATA <= x"85";
when x"EA6" => DATA <= x"58";
when x"EA7" => DATA <= x"90";
when x"EA8" => DATA <= x"02";
when x"EA9" => DATA <= x"E6";
when x"EAA" => DATA <= x"59";
when x"EAB" => DATA <= x"4C";
when x"EAC" => DATA <= x"00";
when x"EAD" => DATA <= x"C5";
when x"EAE" => DATA <= x"20";
when x"EAF" => DATA <= x"79";
when x"EB0" => DATA <= x"C2";
when x"EB1" => DATA <= x"A2";
when x"EB2" => DATA <= x"26";
when x"EB3" => DATA <= x"4C";
when x"EB4" => DATA <= x"33";
when x"EB5" => DATA <= x"C2";
when x"EB6" => DATA <= x"20";
when x"EB7" => DATA <= x"8B";
when x"EB8" => DATA <= x"C7";
when x"EB9" => DATA <= x"20";
when x"EBA" => DATA <= x"CB";
when x"EBB" => DATA <= x"C3";
when x"EBC" => DATA <= x"A4";
when x"EBD" => DATA <= x"03";
when x"EBE" => DATA <= x"60";
when x"EBF" => DATA <= x"20";
when x"EC0" => DATA <= x"F6";
when x"EC1" => DATA <= x"C4";
when x"EC2" => DATA <= x"84";
when x"EC3" => DATA <= x"53";
when x"EC4" => DATA <= x"88";
when x"EC5" => DATA <= x"A2";
when x"EC6" => DATA <= x"00";
when x"EC7" => DATA <= x"B1";
when x"EC8" => DATA <= x"05";
when x"EC9" => DATA <= x"C9";
when x"ECA" => DATA <= x"0D";
when x"ECB" => DATA <= x"F0";
when x"ECC" => DATA <= x"F9";
when x"ECD" => DATA <= x"9D";
when x"ECE" => DATA <= x"40";
when x"ECF" => DATA <= x"01";
when x"ED0" => DATA <= x"E8";
when x"ED1" => DATA <= x"C8";
when x"ED2" => DATA <= x"C9";
when x"ED3" => DATA <= x"22";
when x"ED4" => DATA <= x"D0";
when x"ED5" => DATA <= x"F1";
when x"ED6" => DATA <= x"B1";
when x"ED7" => DATA <= x"05";
when x"ED8" => DATA <= x"C9";
when x"ED9" => DATA <= x"22";
when x"EDA" => DATA <= x"F0";
when x"EDB" => DATA <= x"0E";
when x"EDC" => DATA <= x"A9";
when x"EDD" => DATA <= x"0D";
when x"EDE" => DATA <= x"9D";
when x"EDF" => DATA <= x"3F";
when x"EE0" => DATA <= x"01";
when x"EE1" => DATA <= x"84";
when x"EE2" => DATA <= x"03";
when x"EE3" => DATA <= x"A9";
when x"EE4" => DATA <= x"40";
when x"EE5" => DATA <= x"85";
when x"EE6" => DATA <= x"52";
when x"EE7" => DATA <= x"A6";
when x"EE8" => DATA <= x"04";
when x"EE9" => DATA <= x"60";
when x"EEA" => DATA <= x"C8";
when x"EEB" => DATA <= x"B0";
when x"EEC" => DATA <= x"DA";
when x"EED" => DATA <= x"20";
when x"EEE" => DATA <= x"FA";
when x"EEF" => DATA <= x"CE";
when x"EF0" => DATA <= x"88";
when x"EF1" => DATA <= x"84";
when x"EF2" => DATA <= x"56";
when x"EF3" => DATA <= x"38";
when x"EF4" => DATA <= x"20";
when x"EF5" => DATA <= x"E0";
when x"EF6" => DATA <= x"FF";
when x"EF7" => DATA <= x"4C";
when x"EF8" => DATA <= x"9B";
when x"EF9" => DATA <= x"CD";
when x"EFA" => DATA <= x"20";
when x"EFB" => DATA <= x"B1";
when x"EFC" => DATA <= x"CE";
when x"EFD" => DATA <= x"20";
when x"EFE" => DATA <= x"E4";
when x"EFF" => DATA <= x"C4";
when x"F00" => DATA <= x"88";
when x"F01" => DATA <= x"84";
when x"F02" => DATA <= x"54";
when x"F03" => DATA <= x"A5";
when x"F04" => DATA <= x"12";
when x"F05" => DATA <= x"85";
when x"F06" => DATA <= x"55";
when x"F07" => DATA <= x"A2";
when x"F08" => DATA <= x"52";
when x"F09" => DATA <= x"60";
when x"F0A" => DATA <= x"20";
when x"F0B" => DATA <= x"FA";
when x"F0C" => DATA <= x"CE";
when x"F0D" => DATA <= x"84";
when x"F0E" => DATA <= x"58";
when x"F0F" => DATA <= x"85";
when x"F10" => DATA <= x"59";
when x"F11" => DATA <= x"A5";
when x"F12" => DATA <= x"0D";
when x"F13" => DATA <= x"85";
when x"F14" => DATA <= x"5A";
when x"F15" => DATA <= x"A5";
when x"F16" => DATA <= x"0E";
when x"F17" => DATA <= x"85";
when x"F18" => DATA <= x"5B";
when x"F19" => DATA <= x"A9";
when x"F1A" => DATA <= x"B2";
when x"F1B" => DATA <= x"85";
when x"F1C" => DATA <= x"56";
when x"F1D" => DATA <= x"A9";
when x"F1E" => DATA <= x"C2";
when x"F1F" => DATA <= x"85";
when x"F20" => DATA <= x"57";
when x"F21" => DATA <= x"18";
when x"F22" => DATA <= x"20";
when x"F23" => DATA <= x"DD";
when x"F24" => DATA <= x"FF";
when x"F25" => DATA <= x"4C";
when x"F26" => DATA <= x"5B";
when x"F27" => DATA <= x"C5";
when x"F28" => DATA <= x"38";
when x"F29" => DATA <= x"A9";
when x"F2A" => DATA <= x"00";
when x"F2B" => DATA <= x"2A";
when x"F2C" => DATA <= x"48";
when x"F2D" => DATA <= x"20";
when x"F2E" => DATA <= x"3E";
when x"F2F" => DATA <= x"CF";
when x"F30" => DATA <= x"A2";
when x"F31" => DATA <= x"52";
when x"F32" => DATA <= x"68";
when x"F33" => DATA <= x"20";
when x"F34" => DATA <= x"DA";
when x"F35" => DATA <= x"FF";
when x"F36" => DATA <= x"A0";
when x"F37" => DATA <= x"52";
when x"F38" => DATA <= x"20";
when x"F39" => DATA <= x"9F";
when x"F3A" => DATA <= x"C9";
when x"F3B" => DATA <= x"95";
when x"F3C" => DATA <= x"42";
when x"F3D" => DATA <= x"60";
when x"F3E" => DATA <= x"20";
when x"F3F" => DATA <= x"BC";
when x"F40" => DATA <= x"C8";
when x"F41" => DATA <= x"B4";
when x"F42" => DATA <= x"15";
when x"F43" => DATA <= x"CA";
when x"F44" => DATA <= x"86";
when x"F45" => DATA <= x"04";
when x"F46" => DATA <= x"60";
when x"F47" => DATA <= x"20";
when x"F48" => DATA <= x"BC";
when x"F49" => DATA <= x"C8";
when x"F4A" => DATA <= x"20";
when x"F4B" => DATA <= x"DE";
when x"F4C" => DATA <= x"C4";
when x"F4D" => DATA <= x"20";
when x"F4E" => DATA <= x"CB";
when x"F4F" => DATA <= x"C3";
when x"F50" => DATA <= x"20";
when x"F51" => DATA <= x"41";
when x"F52" => DATA <= x"CF";
when x"F53" => DATA <= x"A2";
when x"F54" => DATA <= x"52";
when x"F55" => DATA <= x"20";
when x"F56" => DATA <= x"D7";
when x"F57" => DATA <= x"FF";
when x"F58" => DATA <= x"4C";
when x"F59" => DATA <= x"5B";
when x"F5A" => DATA <= x"C5";
when x"F5B" => DATA <= x"20";
when x"F5C" => DATA <= x"3E";
when x"F5D" => DATA <= x"CF";
when x"F5E" => DATA <= x"84";
when x"F5F" => DATA <= x"52";
when x"F60" => DATA <= x"20";
when x"F61" => DATA <= x"D4";
when x"F62" => DATA <= x"FF";
when x"F63" => DATA <= x"4C";
when x"F64" => DATA <= x"7C";
when x"F65" => DATA <= x"C9";
when x"F66" => DATA <= x"20";
when x"F67" => DATA <= x"5B";
when x"F68" => DATA <= x"CF";
when x"F69" => DATA <= x"A4";
when x"F6A" => DATA <= x"52";
when x"F6B" => DATA <= x"20";
when x"F6C" => DATA <= x"D4";
when x"F6D" => DATA <= x"FF";
when x"F6E" => DATA <= x"95";
when x"F6F" => DATA <= x"24";
when x"F70" => DATA <= x"20";
when x"F71" => DATA <= x"D4";
when x"F72" => DATA <= x"FF";
when x"F73" => DATA <= x"95";
when x"F74" => DATA <= x"33";
when x"F75" => DATA <= x"20";
when x"F76" => DATA <= x"D4";
when x"F77" => DATA <= x"FF";
when x"F78" => DATA <= x"95";
when x"F79" => DATA <= x"42";
when x"F7A" => DATA <= x"60";
when x"F7B" => DATA <= x"20";
when x"F7C" => DATA <= x"BC";
when x"F7D" => DATA <= x"C8";
when x"F7E" => DATA <= x"20";
when x"F7F" => DATA <= x"31";
when x"F80" => DATA <= x"C2";
when x"F81" => DATA <= x"20";
when x"F82" => DATA <= x"E1";
when x"F83" => DATA <= x"C4";
when x"F84" => DATA <= x"20";
when x"F85" => DATA <= x"CB";
when x"F86" => DATA <= x"C3";
when x"F87" => DATA <= x"20";
when x"F88" => DATA <= x"41";
when x"F89" => DATA <= x"CF";
when x"F8A" => DATA <= x"A5";
when x"F8B" => DATA <= x"52";
when x"F8C" => DATA <= x"6C";
when x"F8D" => DATA <= x"16";
when x"F8E" => DATA <= x"02";
when x"F8F" => DATA <= x"20";
when x"F90" => DATA <= x"7B";
when x"F91" => DATA <= x"CF";
when x"F92" => DATA <= x"4C";
when x"F93" => DATA <= x"5B";
when x"F94" => DATA <= x"C5";
when x"F95" => DATA <= x"20";
when x"F96" => DATA <= x"7B";
when x"F97" => DATA <= x"CF";
when x"F98" => DATA <= x"A2";
when x"F99" => DATA <= x"01";
when x"F9A" => DATA <= x"B5";
when x"F9B" => DATA <= x"52";
when x"F9C" => DATA <= x"20";
when x"F9D" => DATA <= x"D1";
when x"F9E" => DATA <= x"FF";
when x"F9F" => DATA <= x"E8";
when x"FA0" => DATA <= x"E0";
when x"FA1" => DATA <= x"04";
when x"FA2" => DATA <= x"90";
when x"FA3" => DATA <= x"F6";
when x"FA4" => DATA <= x"B0";
when x"FA5" => DATA <= x"EC";
when x"FA6" => DATA <= x"38";
when x"FA7" => DATA <= x"08";
when x"FA8" => DATA <= x"20";
when x"FA9" => DATA <= x"B1";
when x"FAA" => DATA <= x"CE";
when x"FAB" => DATA <= x"A2";
when x"FAC" => DATA <= x"52";
when x"FAD" => DATA <= x"28";
when x"FAE" => DATA <= x"20";
when x"FAF" => DATA <= x"CE";
when x"FB0" => DATA <= x"FF";
when x"FB1" => DATA <= x"A6";
when x"FB2" => DATA <= x"04";
when x"FB3" => DATA <= x"4C";
when x"FB4" => DATA <= x"7C";
when x"FB5" => DATA <= x"C9";
when x"FB6" => DATA <= x"20";
when x"FB7" => DATA <= x"BC";
when x"FB8" => DATA <= x"C8";
when x"FB9" => DATA <= x"20";
when x"FBA" => DATA <= x"E4";
when x"FBB" => DATA <= x"C4";
when x"FBC" => DATA <= x"20";
when x"FBD" => DATA <= x"41";
when x"FBE" => DATA <= x"CF";
when x"FBF" => DATA <= x"20";
when x"FC0" => DATA <= x"CB";
when x"FC1" => DATA <= x"FF";
when x"FC2" => DATA <= x"4C";
when x"FC3" => DATA <= x"5B";
when x"FC4" => DATA <= x"C5";
when x"FC5" => DATA <= x"20";
when x"FC6" => DATA <= x"2C";
when x"FC7" => DATA <= x"C2";
when x"FC8" => DATA <= x"20";
when x"FC9" => DATA <= x"B1";
when x"FCA" => DATA <= x"CE";
when x"FCB" => DATA <= x"20";
when x"FCC" => DATA <= x"E4";
when x"FCD" => DATA <= x"C4";
when x"FCE" => DATA <= x"88";
when x"FCF" => DATA <= x"B1";
when x"FD0" => DATA <= x"52";
when x"FD1" => DATA <= x"84";
when x"FD2" => DATA <= x"55";
when x"FD3" => DATA <= x"A4";
when x"FD4" => DATA <= x"0F";
when x"FD5" => DATA <= x"48";
when x"FD6" => DATA <= x"20";
when x"FD7" => DATA <= x"D1";
when x"FD8" => DATA <= x"FF";
when x"FD9" => DATA <= x"68";
when x"FDA" => DATA <= x"C9";
when x"FDB" => DATA <= x"0D";
when x"FDC" => DATA <= x"F0";
when x"FDD" => DATA <= x"E4";
when x"FDE" => DATA <= x"A4";
when x"FDF" => DATA <= x"55";
when x"FE0" => DATA <= x"C8";
when x"FE1" => DATA <= x"D0";
when x"FE2" => DATA <= x"EC";
when x"FE3" => DATA <= x"20";
when x"FE4" => DATA <= x"2C";
when x"FE5" => DATA <= x"C2";
when x"FE6" => DATA <= x"20";
when x"FE7" => DATA <= x"E1";
when x"FE8" => DATA <= x"C4";
when x"FE9" => DATA <= x"20";
when x"FEA" => DATA <= x"CB";
when x"FEB" => DATA <= x"C3";
when x"FEC" => DATA <= x"A0";
when x"FED" => DATA <= x"00";
when x"FEE" => DATA <= x"84";
when x"FEF" => DATA <= x"55";
when x"FF0" => DATA <= x"A4";
when x"FF1" => DATA <= x"0F";
when x"FF2" => DATA <= x"20";
when x"FF3" => DATA <= x"D4";
when x"FF4" => DATA <= x"FF";
when x"FF5" => DATA <= x"A4";
when x"FF6" => DATA <= x"55";
when x"FF7" => DATA <= x"91";
when x"FF8" => DATA <= x"52";
when x"FF9" => DATA <= x"C8";
when x"FFA" => DATA <= x"C9";
when x"FFB" => DATA <= x"0D";
when x"FFC" => DATA <= x"D0";
when x"FFD" => DATA <= x"F0";
when x"FFE" => DATA <= x"F0";
when x"FFF" => DATA <= x"C2";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity atombasic is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of atombasic is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(11 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"3C";
when x"001" => DATA <= x"3D";
when x"002" => DATA <= x"3E";
when x"003" => DATA <= x"FE";
when x"004" => DATA <= x"2D";
when x"005" => DATA <= x"2B";
when x"006" => DATA <= x"C8";
when x"007" => DATA <= x"23";
when x"008" => DATA <= x"28";
when x"009" => DATA <= x"21";
when x"00A" => DATA <= x"3F";
when x"00B" => DATA <= x"52";
when x"00C" => DATA <= x"54";
when x"00D" => DATA <= x"4C";
when x"00E" => DATA <= x"43";
when x"00F" => DATA <= x"41";
when x"010" => DATA <= x"50";
when x"011" => DATA <= x"45";
when x"012" => DATA <= x"47";
when x"013" => DATA <= x"42";
when x"014" => DATA <= x"46";
when x"015" => DATA <= x"F0";
when x"016" => DATA <= x"54";
when x"017" => DATA <= x"FF";
when x"018" => DATA <= x"4F";
when x"019" => DATA <= x"CB";
when x"01A" => DATA <= x"53";
when x"01B" => DATA <= x"CB";
when x"01C" => DATA <= x"54";
when x"01D" => DATA <= x"45";
when x"01E" => DATA <= x"50";
when x"01F" => DATA <= x"CB";
when x"020" => DATA <= x"54";
when x"021" => DATA <= x"C3";
when x"022" => DATA <= x"48";
when x"023" => DATA <= x"45";
when x"024" => DATA <= x"4E";
when x"025" => DATA <= x"C3";
when x"026" => DATA <= x"22";
when x"027" => DATA <= x"24";
when x"028" => DATA <= x"CE";
when x"029" => DATA <= x"CE";
when x"02A" => DATA <= x"CC";
when x"02B" => DATA <= x"24";
when x"02C" => DATA <= x"2C";
when x"02D" => DATA <= x"C5";
when x"02E" => DATA <= x"24";
when x"02F" => DATA <= x"26";
when x"030" => DATA <= x"3B";
when x"031" => DATA <= x"0D";
when x"032" => DATA <= x"2C";
when x"033" => DATA <= x"C3";
when x"034" => DATA <= x"C5";
when x"035" => DATA <= x"C2";
when x"036" => DATA <= x"3E";
when x"037" => DATA <= x"C7";
when x"038" => DATA <= x"3D";
when x"039" => DATA <= x"C7";
when x"03A" => DATA <= x"C7";
when x"03B" => DATA <= x"C7";
when x"03C" => DATA <= x"3D";
when x"03D" => DATA <= x"C7";
when x"03E" => DATA <= x"C7";
when x"03F" => DATA <= x"C8";
when x"040" => DATA <= x"52";
when x"041" => DATA <= x"C7";
when x"042" => DATA <= x"C7";
when x"043" => DATA <= x"4F";
when x"044" => DATA <= x"41";
when x"045" => DATA <= x"FE";
when x"046" => DATA <= x"24";
when x"047" => DATA <= x"C7";
when x"048" => DATA <= x"48";
when x"049" => DATA <= x"C9";
when x"04A" => DATA <= x"45";
when x"04B" => DATA <= x"4E";
when x"04C" => DATA <= x"C9";
when x"04D" => DATA <= x"4E";
when x"04E" => DATA <= x"44";
when x"04F" => DATA <= x"C7";
when x"050" => DATA <= x"C9";
when x"051" => DATA <= x"C9";
when x"052" => DATA <= x"C9";
when x"053" => DATA <= x"C9";
when x"054" => DATA <= x"4E";
when x"055" => DATA <= x"44";
when x"056" => DATA <= x"C9";
when x"057" => DATA <= x"4F";
when x"058" => DATA <= x"50";
when x"059" => DATA <= x"C9";
when x"05A" => DATA <= x"4F";
when x"05B" => DATA <= x"55";
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when x"064" => DATA <= x"CF";
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when x"100" => DATA <= x"65";
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when x"112" => DATA <= x"17";
when x"113" => DATA <= x"17";
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when x"1DF" => DATA <= x"7C";
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when x"1E2" => DATA <= x"2A";
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when x"1E5" => DATA <= x"21";
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when x"1F3" => DATA <= x"3F";
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when x"1F5" => DATA <= x"27";
when x"1F6" => DATA <= x"22";
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when x"1F8" => DATA <= x"B7";
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when x"1FA" => DATA <= x"D3";
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when x"1FC" => DATA <= x"EF";
when x"1FD" => DATA <= x"13";
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when x"204" => DATA <= x"78";
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when x"215" => DATA <= x"C7";
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when x"218" => DATA <= x"C8";
when x"219" => DATA <= x"C8";
when x"21A" => DATA <= x"C8";
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when x"21C" => DATA <= x"C8";
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when x"221" => DATA <= x"C2";
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when x"224" => DATA <= x"CD";
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when x"22F" => DATA <= x"84";
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when x"234" => DATA <= x"03";
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when x"239" => DATA <= x"C9";
when x"23A" => DATA <= x"20";
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when x"23D" => DATA <= x"84";
when x"23E" => DATA <= x"5E";
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when x"240" => DATA <= x"52";
when x"241" => DATA <= x"E8";
when x"242" => DATA <= x"BD";
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when x"246" => DATA <= x"24";
when x"247" => DATA <= x"C5";
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when x"249" => DATA <= x"D0";
when x"24A" => DATA <= x"F6";
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when x"24C" => DATA <= x"EE";
when x"24D" => DATA <= x"C0";
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when x"24F" => DATA <= x"E8";
when x"250" => DATA <= x"C8";
when x"251" => DATA <= x"BD";
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when x"254" => DATA <= x"30";
when x"255" => DATA <= x"15";
when x"256" => DATA <= x"D1";
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when x"258" => DATA <= x"F0";
when x"259" => DATA <= x"F5";
when x"25A" => DATA <= x"B1";
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when x"25C" => DATA <= x"C9";
when x"25D" => DATA <= x"2E";
when x"25E" => DATA <= x"F0";
when x"25F" => DATA <= x"04";
when x"260" => DATA <= x"A4";
when x"261" => DATA <= x"5E";
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when x"263" => DATA <= x"E7";
when x"264" => DATA <= x"E8";
when x"265" => DATA <= x"BD";
when x"266" => DATA <= x"FF";
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when x"269" => DATA <= x"FA";
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when x"26B" => DATA <= x"C9";
when x"26C" => DATA <= x"FE";
when x"26D" => DATA <= x"B0";
when x"26E" => DATA <= x"3B";
when x"26F" => DATA <= x"85";
when x"270" => DATA <= x"53";
when x"271" => DATA <= x"BD";
when x"272" => DATA <= x"EE";
when x"273" => DATA <= x"C0";
when x"274" => DATA <= x"90";
when x"275" => DATA <= x"29";
when x"276" => DATA <= x"A6";
when x"277" => DATA <= x"04";
when x"278" => DATA <= x"60";
when x"279" => DATA <= x"A2";
when x"27A" => DATA <= x"0E";
when x"27B" => DATA <= x"A4";
when x"27C" => DATA <= x"03";
when x"27D" => DATA <= x"88";
when x"27E" => DATA <= x"C8";
when x"27F" => DATA <= x"B1";
when x"280" => DATA <= x"05";
when x"281" => DATA <= x"C9";
when x"282" => DATA <= x"20";
when x"283" => DATA <= x"F0";
when x"284" => DATA <= x"F9";
when x"285" => DATA <= x"DD";
when x"286" => DATA <= x"DD";
when x"287" => DATA <= x"C1";
when x"288" => DATA <= x"F0";
when x"289" => DATA <= x"0C";
when x"28A" => DATA <= x"85";
when x"28B" => DATA <= x"52";
when x"28C" => DATA <= x"E8";
when x"28D" => DATA <= x"BD";
when x"28E" => DATA <= x"DD";
when x"28F" => DATA <= x"C1";
when x"290" => DATA <= x"30";
when x"291" => DATA <= x"16";
when x"292" => DATA <= x"C5";
when x"293" => DATA <= x"52";
when x"294" => DATA <= x"D0";
when x"295" => DATA <= x"F6";
when x"296" => DATA <= x"BD";
when x"297" => DATA <= x"12";
when x"298" => DATA <= x"C2";
when x"299" => DATA <= x"85";
when x"29A" => DATA <= x"53";
when x"29B" => DATA <= x"BD";
when x"29C" => DATA <= x"F8";
when x"29D" => DATA <= x"C1";
when x"29E" => DATA <= x"C8";
when x"29F" => DATA <= x"85";
when x"2A0" => DATA <= x"52";
when x"2A1" => DATA <= x"84";
when x"2A2" => DATA <= x"03";
when x"2A3" => DATA <= x"A6";
when x"2A4" => DATA <= x"04";
when x"2A5" => DATA <= x"6C";
when x"2A6" => DATA <= x"52";
when x"2A7" => DATA <= x"00";
when x"2A8" => DATA <= x"C9";
when x"2A9" => DATA <= x"FE";
when x"2AA" => DATA <= x"F0";
when x"2AB" => DATA <= x"CA";
when x"2AC" => DATA <= x"00";
when x"2AD" => DATA <= x"20";
when x"2AE" => DATA <= x"E4";
when x"2AF" => DATA <= x"C4";
when x"2B0" => DATA <= x"D0";
when x"2B1" => DATA <= x"04";
when x"2B2" => DATA <= x"A9";
when x"2B3" => DATA <= x"29";
when x"2B4" => DATA <= x"85";
when x"2B5" => DATA <= x"12";
when x"2B6" => DATA <= x"A9";
when x"2B7" => DATA <= x"0D";
when x"2B8" => DATA <= x"A4";
when x"2B9" => DATA <= x"12";
when x"2BA" => DATA <= x"84";
when x"2BB" => DATA <= x"0E";
when x"2BC" => DATA <= x"A0";
when x"2BD" => DATA <= x"00";
when x"2BE" => DATA <= x"84";
when x"2BF" => DATA <= x"0D";
when x"2C0" => DATA <= x"91";
when x"2C1" => DATA <= x"0D";
when x"2C2" => DATA <= x"A9";
when x"2C3" => DATA <= x"FF";
when x"2C4" => DATA <= x"C8";
when x"2C5" => DATA <= x"91";
when x"2C6" => DATA <= x"0D";
when x"2C7" => DATA <= x"C8";
when x"2C8" => DATA <= x"84";
when x"2C9" => DATA <= x"0D";
when x"2CA" => DATA <= x"A9";
when x"2CB" => DATA <= x"08";
when x"2CC" => DATA <= x"8D";
when x"2CD" => DATA <= x"21";
when x"2CE" => DATA <= x"03";
when x"2CF" => DATA <= x"A9";
when x"2D0" => DATA <= x"3E";
when x"2D1" => DATA <= x"D8";
when x"2D2" => DATA <= x"20";
when x"2D3" => DATA <= x"0F";
when x"2D4" => DATA <= x"CD";
when x"2D5" => DATA <= x"A2";
when x"2D6" => DATA <= x"01";
when x"2D7" => DATA <= x"86";
when x"2D8" => DATA <= x"06";
when x"2D9" => DATA <= x"CA";
when x"2DA" => DATA <= x"86";
when x"2DB" => DATA <= x"05";
when x"2DC" => DATA <= x"86";
when x"2DD" => DATA <= x"01";
when x"2DE" => DATA <= x"86";
when x"2DF" => DATA <= x"02";
when x"2E0" => DATA <= x"A9";
when x"2E1" => DATA <= x"D8";
when x"2E2" => DATA <= x"8D";
when x"2E3" => DATA <= x"02";
when x"2E4" => DATA <= x"02";
when x"2E5" => DATA <= x"A9";
when x"2E6" => DATA <= x"C9";
when x"2E7" => DATA <= x"8D";
when x"2E8" => DATA <= x"03";
when x"2E9" => DATA <= x"02";
when x"2EA" => DATA <= x"A9";
when x"2EB" => DATA <= x"E7";
when x"2EC" => DATA <= x"85";
when x"2ED" => DATA <= x"10";
when x"2EE" => DATA <= x"A9";
when x"2EF" => DATA <= x"C9";
when x"2F0" => DATA <= x"85";
when x"2F1" => DATA <= x"11";
when x"2F2" => DATA <= x"A2";
when x"2F3" => DATA <= x"FF";
when x"2F4" => DATA <= x"9A";
when x"2F5" => DATA <= x"A9";
when x"2F6" => DATA <= x"00";
when x"2F7" => DATA <= x"85";
when x"2F8" => DATA <= x"04";
when x"2F9" => DATA <= x"85";
when x"2FA" => DATA <= x"03";
when x"2FB" => DATA <= x"85";
when x"2FC" => DATA <= x"15";
when x"2FD" => DATA <= x"85";
when x"2FE" => DATA <= x"13";
when x"2FF" => DATA <= x"85";
when x"300" => DATA <= x"14";
when x"301" => DATA <= x"A2";
when x"302" => DATA <= x"34";
when x"303" => DATA <= x"9D";
when x"304" => DATA <= x"8C";
when x"305" => DATA <= x"03";
when x"306" => DATA <= x"CA";
when x"307" => DATA <= x"D0";
when x"308" => DATA <= x"FA";
when x"309" => DATA <= x"20";
when x"30A" => DATA <= x"34";
when x"30B" => DATA <= x"C4";
when x"30C" => DATA <= x"B0";
when x"30D" => DATA <= x"21";
when x"30E" => DATA <= x"20";
when x"30F" => DATA <= x"6A";
when x"310" => DATA <= x"C4";
when x"311" => DATA <= x"90";
when x"312" => DATA <= x"03";
when x"313" => DATA <= x"4C";
when x"314" => DATA <= x"C9";
when x"315" => DATA <= x"CD";
when x"316" => DATA <= x"A2";
when x"317" => DATA <= x"7D";
when x"318" => DATA <= x"4C";
when x"319" => DATA <= x"33";
when x"31A" => DATA <= x"C2";
when x"31B" => DATA <= x"20";
when x"31C" => DATA <= x"34";
when x"31D" => DATA <= x"C4";
when x"31E" => DATA <= x"B0";
when x"31F" => DATA <= x"0F";
when x"320" => DATA <= x"A2";
when x"321" => DATA <= x"7F";
when x"322" => DATA <= x"4C";
when x"323" => DATA <= x"33";
when x"324" => DATA <= x"C2";
when x"325" => DATA <= x"20";
when x"326" => DATA <= x"34";
when x"327" => DATA <= x"C4";
when x"328" => DATA <= x"B0";
when x"329" => DATA <= x"05";
when x"32A" => DATA <= x"A2";
when x"32B" => DATA <= x"10";
when x"32C" => DATA <= x"4C";
when x"32D" => DATA <= x"7B";
when x"32E" => DATA <= x"C2";
when x"32F" => DATA <= x"A2";
when x"330" => DATA <= x"14";
when x"331" => DATA <= x"4C";
when x"332" => DATA <= x"7B";
when x"333" => DATA <= x"C2";
when x"334" => DATA <= x"38";
when x"335" => DATA <= x"66";
when x"336" => DATA <= x"0F";
when x"337" => DATA <= x"20";
when x"338" => DATA <= x"72";
when x"339" => DATA <= x"C3";
when x"33A" => DATA <= x"A2";
when x"33B" => DATA <= x"2E";
when x"33C" => DATA <= x"4C";
when x"33D" => DATA <= x"33";
when x"33E" => DATA <= x"C2";
when x"33F" => DATA <= x"20";
when x"340" => DATA <= x"8B";
when x"341" => DATA <= x"C7";
when x"342" => DATA <= x"20";
when x"343" => DATA <= x"CB";
when x"344" => DATA <= x"C3";
when x"345" => DATA <= x"A5";
when x"346" => DATA <= x"0F";
when x"347" => DATA <= x"30";
when x"348" => DATA <= x"21";
when x"349" => DATA <= x"A2";
when x"34A" => DATA <= x"00";
when x"34B" => DATA <= x"86";
when x"34C" => DATA <= x"27";
when x"34D" => DATA <= x"A0";
when x"34E" => DATA <= x"00";
when x"34F" => DATA <= x"B9";
when x"350" => DATA <= x"52";
when x"351" => DATA <= x"00";
when x"352" => DATA <= x"48";
when x"353" => DATA <= x"29";
when x"354" => DATA <= x"0F";
when x"355" => DATA <= x"95";
when x"356" => DATA <= x"45";
when x"357" => DATA <= x"68";
when x"358" => DATA <= x"4A";
when x"359" => DATA <= x"4A";
when x"35A" => DATA <= x"4A";
when x"35B" => DATA <= x"4A";
when x"35C" => DATA <= x"E8";
when x"35D" => DATA <= x"95";
when x"35E" => DATA <= x"45";
when x"35F" => DATA <= x"E8";
when x"360" => DATA <= x"C8";
when x"361" => DATA <= x"C0";
when x"362" => DATA <= x"04";
when x"363" => DATA <= x"90";
when x"364" => DATA <= x"EA";
when x"365" => DATA <= x"20";
when x"366" => DATA <= x"C8";
when x"367" => DATA <= x"C5";
when x"368" => DATA <= x"30";
when x"369" => DATA <= x"CD";
when x"36A" => DATA <= x"20";
when x"36B" => DATA <= x"89";
when x"36C" => DATA <= x"C5";
when x"36D" => DATA <= x"30";
when x"36E" => DATA <= x"C8";
when x"36F" => DATA <= x"20";
when x"370" => DATA <= x"54";
when x"371" => DATA <= x"CD";
when x"372" => DATA <= x"A2";
when x"373" => DATA <= x"18";
when x"374" => DATA <= x"4C";
when x"375" => DATA <= x"7B";
when x"376" => DATA <= x"C2";
when x"377" => DATA <= x"20";
when x"378" => DATA <= x"4C";
when x"379" => DATA <= x"CA";
when x"37A" => DATA <= x"B1";
when x"37B" => DATA <= x"05";
when x"37C" => DATA <= x"C8";
when x"37D" => DATA <= x"C9";
when x"37E" => DATA <= x"0D";
when x"37F" => DATA <= x"F0";
when x"380" => DATA <= x"1C";
when x"381" => DATA <= x"84";
when x"382" => DATA <= x"03";
when x"383" => DATA <= x"C9";
when x"384" => DATA <= x"22";
when x"385" => DATA <= x"D0";
when x"386" => DATA <= x"F0";
when x"387" => DATA <= x"B1";
when x"388" => DATA <= x"05";
when x"389" => DATA <= x"C9";
when x"38A" => DATA <= x"22";
when x"38B" => DATA <= x"D0";
when x"38C" => DATA <= x"E5";
when x"38D" => DATA <= x"C8";
when x"38E" => DATA <= x"B0";
when x"38F" => DATA <= x"E7";
when x"390" => DATA <= x"20";
when x"391" => DATA <= x"8B";
when x"392" => DATA <= x"C7";
when x"393" => DATA <= x"20";
when x"394" => DATA <= x"CB";
when x"395" => DATA <= x"C3";
when x"396" => DATA <= x"05";
when x"397" => DATA <= x"54";
when x"398" => DATA <= x"05";
when x"399" => DATA <= x"53";
when x"39A" => DATA <= x"F0";
when x"39B" => DATA <= x"0E";
when x"39C" => DATA <= x"A0";
when x"39D" => DATA <= x"00";
when x"39E" => DATA <= x"B1";
when x"39F" => DATA <= x"52";
when x"3A0" => DATA <= x"C9";
when x"3A1" => DATA <= x"0D";
when x"3A2" => DATA <= x"F0";
when x"3A3" => DATA <= x"93";
when x"3A4" => DATA <= x"20";
when x"3A5" => DATA <= x"4C";
when x"3A6" => DATA <= x"CA";
when x"3A7" => DATA <= x"C8";
when x"3A8" => DATA <= x"D0";
when x"3A9" => DATA <= x"F4";
when x"3AA" => DATA <= x"A5";
when x"3AB" => DATA <= x"52";
when x"3AC" => DATA <= x"20";
when x"3AD" => DATA <= x"4C";
when x"3AE" => DATA <= x"CA";
when x"3AF" => DATA <= x"4C";
when x"3B0" => DATA <= x"37";
when x"3B1" => DATA <= x"C3";
when x"3B2" => DATA <= x"20";
when x"3B3" => DATA <= x"C8";
when x"3B4" => DATA <= x"C3";
when x"3B5" => DATA <= x"20";
when x"3B6" => DATA <= x"E4";
when x"3B7" => DATA <= x"C4";
when x"3B8" => DATA <= x"AD";
when x"3B9" => DATA <= x"22";
when x"3BA" => DATA <= x"03";
when x"3BB" => DATA <= x"AE";
when x"3BC" => DATA <= x"39";
when x"3BD" => DATA <= x"03";
when x"3BE" => DATA <= x"AC";
when x"3BF" => DATA <= x"3A";
when x"3C0" => DATA <= x"03";
when x"3C1" => DATA <= x"20";
when x"3C2" => DATA <= x"A5";
when x"3C3" => DATA <= x"C2";
when x"3C4" => DATA <= x"D8";
when x"3C5" => DATA <= x"4C";
when x"3C6" => DATA <= x"5B";
when x"3C7" => DATA <= x"C5";
when x"3C8" => DATA <= x"20";
when x"3C9" => DATA <= x"BC";
when x"3CA" => DATA <= x"C8";
when x"3CB" => DATA <= x"A0";
when x"3CC" => DATA <= x"52";
when x"3CD" => DATA <= x"CA";
when x"3CE" => DATA <= x"86";
when x"3CF" => DATA <= x"04";
when x"3D0" => DATA <= x"B5";
when x"3D1" => DATA <= x"16";
when x"3D2" => DATA <= x"99";
when x"3D3" => DATA <= x"00";
when x"3D4" => DATA <= x"00";
when x"3D5" => DATA <= x"B5";
when x"3D6" => DATA <= x"25";
when x"3D7" => DATA <= x"99";
when x"3D8" => DATA <= x"01";
when x"3D9" => DATA <= x"00";
when x"3DA" => DATA <= x"B5";
when x"3DB" => DATA <= x"34";
when x"3DC" => DATA <= x"99";
when x"3DD" => DATA <= x"02";
when x"3DE" => DATA <= x"00";
when x"3DF" => DATA <= x"B5";
when x"3E0" => DATA <= x"43";
when x"3E1" => DATA <= x"99";
when x"3E2" => DATA <= x"03";
when x"3E3" => DATA <= x"00";
when x"3E4" => DATA <= x"60";
when x"3E5" => DATA <= x"20";
when x"3E6" => DATA <= x"E1";
when x"3E7" => DATA <= x"C4";
when x"3E8" => DATA <= x"20";
when x"3E9" => DATA <= x"2F";
when x"3EA" => DATA <= x"CA";
when x"3EB" => DATA <= x"4C";
when x"3EC" => DATA <= x"5B";
when x"3ED" => DATA <= x"C5";
when x"3EE" => DATA <= x"20";
when x"3EF" => DATA <= x"BC";
when x"3F0" => DATA <= x"C8";
when x"3F1" => DATA <= x"20";
when x"3F2" => DATA <= x"93";
when x"3F3" => DATA <= x"CE";
when x"3F4" => DATA <= x"B5";
when x"3F5" => DATA <= x"26";
when x"3F6" => DATA <= x"C8";
when x"3F7" => DATA <= x"91";
when x"3F8" => DATA <= x"52";
when x"3F9" => DATA <= x"C8";
when x"3FA" => DATA <= x"B5";
when x"3FB" => DATA <= x"35";
when x"3FC" => DATA <= x"91";
when x"3FD" => DATA <= x"52";
when x"3FE" => DATA <= x"C8";
when x"3FF" => DATA <= x"B5";
when x"400" => DATA <= x"44";
when x"401" => DATA <= x"91";
when x"402" => DATA <= x"52";
when x"403" => DATA <= x"4C";
when x"404" => DATA <= x"5B";
when x"405" => DATA <= x"C5";
when x"406" => DATA <= x"20";
when x"407" => DATA <= x"BC";
when x"408" => DATA <= x"C8";
when x"409" => DATA <= x"20";
when x"40A" => DATA <= x"93";
when x"40B" => DATA <= x"CE";
when x"40C" => DATA <= x"4C";
when x"40D" => DATA <= x"5B";
when x"40E" => DATA <= x"C5";
when x"40F" => DATA <= x"A2";
when x"410" => DATA <= x"00";
when x"411" => DATA <= x"B1";
when x"412" => DATA <= x"05";
when x"413" => DATA <= x"9D";
when x"414" => DATA <= x"00";
when x"415" => DATA <= x"01";
when x"416" => DATA <= x"84";
when x"417" => DATA <= x"03";
when x"418" => DATA <= x"C8";
when x"419" => DATA <= x"E8";
when x"41A" => DATA <= x"C9";
when x"41B" => DATA <= x"0D";
when x"41C" => DATA <= x"D0";
when x"41D" => DATA <= x"F3";
when x"41E" => DATA <= x"20";
when x"41F" => DATA <= x"F7";
when x"420" => DATA <= x"FF";
when x"421" => DATA <= x"4C";
when x"422" => DATA <= x"58";
when x"423" => DATA <= x"C5";
when x"424" => DATA <= x"AD";
when x"425" => DATA <= x"00";
when x"426" => DATA <= x"D0";
when x"427" => DATA <= x"C9";
when x"428" => DATA <= x"AA";
when x"429" => DATA <= x"D0";
when x"42A" => DATA <= x"38";
when x"42B" => DATA <= x"4A";
when x"42C" => DATA <= x"CD";
when x"42D" => DATA <= x"01";
when x"42E" => DATA <= x"D0";
when x"42F" => DATA <= x"D0";
when x"430" => DATA <= x"32";
when x"431" => DATA <= x"A4";
when x"432" => DATA <= x"5E";
when x"433" => DATA <= x"60";
when x"434" => DATA <= x"A4";
when x"435" => DATA <= x"03";
when x"436" => DATA <= x"10";
when x"437" => DATA <= x"03";
when x"438" => DATA <= x"C8";
when x"439" => DATA <= x"84";
when x"43A" => DATA <= x"03";
when x"43B" => DATA <= x"B1";
when x"43C" => DATA <= x"05";
when x"43D" => DATA <= x"C9";
when x"43E" => DATA <= x"20";
when x"43F" => DATA <= x"F0";
when x"440" => DATA <= x"F7";
when x"441" => DATA <= x"C9";
when x"442" => DATA <= x"5B";
when x"443" => DATA <= x"B0";
when x"444" => DATA <= x"1E";
when x"445" => DATA <= x"E9";
when x"446" => DATA <= x"3F";
when x"447" => DATA <= x"90";
when x"448" => DATA <= x"1B";
when x"449" => DATA <= x"A6";
when x"44A" => DATA <= x"04";
when x"44B" => DATA <= x"95";
when x"44C" => DATA <= x"16";
when x"44D" => DATA <= x"C8";
when x"44E" => DATA <= x"B1";
when x"44F" => DATA <= x"05";
when x"450" => DATA <= x"C9";
when x"451" => DATA <= x"2E";
when x"452" => DATA <= x"F0";
when x"453" => DATA <= x"0F";
when x"454" => DATA <= x"C9";
when x"455" => DATA <= x"5B";
when x"456" => DATA <= x"B0";
when x"457" => DATA <= x"04";
when x"458" => DATA <= x"C9";
when x"459" => DATA <= x"40";
when x"45A" => DATA <= x"B0";
when x"45B" => DATA <= x"07";
when x"45C" => DATA <= x"E8";
when x"45D" => DATA <= x"86";
when x"45E" => DATA <= x"04";
when x"45F" => DATA <= x"38";
when x"460" => DATA <= x"84";
when x"461" => DATA <= x"03";
when x"462" => DATA <= x"60";
when x"463" => DATA <= x"18";
when x"464" => DATA <= x"60";
when x"465" => DATA <= x"20";
when x"466" => DATA <= x"34";
when x"467" => DATA <= x"C4";
when x"468" => DATA <= x"B0";
when x"469" => DATA <= x"BB";
when x"46A" => DATA <= x"A2";
when x"46B" => DATA <= x"00";
when x"46C" => DATA <= x"A4";
when x"46D" => DATA <= x"03";
when x"46E" => DATA <= x"86";
when x"46F" => DATA <= x"52";
when x"470" => DATA <= x"86";
when x"471" => DATA <= x"53";
when x"472" => DATA <= x"86";
when x"473" => DATA <= x"54";
when x"474" => DATA <= x"86";
when x"475" => DATA <= x"55";
when x"476" => DATA <= x"88";
when x"477" => DATA <= x"C8";
when x"478" => DATA <= x"B1";
when x"479" => DATA <= x"05";
when x"47A" => DATA <= x"38";
when x"47B" => DATA <= x"E9";
when x"47C" => DATA <= x"30";
when x"47D" => DATA <= x"30";
when x"47E" => DATA <= x"54";
when x"47F" => DATA <= x"C9";
when x"480" => DATA <= x"0A";
when x"481" => DATA <= x"B0";
when x"482" => DATA <= x"50";
when x"483" => DATA <= x"A6";
when x"484" => DATA <= x"53";
when x"485" => DATA <= x"48";
when x"486" => DATA <= x"A5";
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when x"4A3" => DATA <= x"52";
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when x"680" => DATA <= x"84";
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when x"699" => DATA <= x"57";
when x"69A" => DATA <= x"26";
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when x"6B3" => DATA <= x"A5";
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when x"6D3" => DATA <= x"02";
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when x"6D5" => DATA <= x"68";
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when x"8A2" => DATA <= x"20";
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when x"8A6" => DATA <= x"B5";
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when x"8AB" => DATA <= x"B5";
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when x"8AD" => DATA <= x"75";
when x"8AE" => DATA <= x"23";
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when x"8B1" => DATA <= x"53";
when x"8B2" => DATA <= x"C9";
when x"8B3" => DATA <= x"20";
when x"8B4" => DATA <= x"A2";
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when x"8B7" => DATA <= x"62";
when x"8B8" => DATA <= x"C9";
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when x"8BB" => DATA <= x"C8";
when x"8BC" => DATA <= x"A2";
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when x"8C0" => DATA <= x"C2";
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when x"8C2" => DATA <= x"DC";
when x"8C3" => DATA <= x"C8";
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when x"8C5" => DATA <= x"A9";
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when x"8C7" => DATA <= x"A8";
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when x"8CA" => DATA <= x"95";
when x"8CB" => DATA <= x"15";
when x"8CC" => DATA <= x"98";
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when x"8CF" => DATA <= x"95";
when x"8D0" => DATA <= x"24";
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when x"8D2" => DATA <= x"F5";
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when x"8D5" => DATA <= x"33";
when x"8D6" => DATA <= x"98";
when x"8D7" => DATA <= x"F5";
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when x"8D9" => DATA <= x"95";
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when x"8DB" => DATA <= x"60";
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when x"8DE" => DATA <= x"C4";
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when x"8E0" => DATA <= x"17";
when x"8E1" => DATA <= x"B4";
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when x"8E5" => DATA <= x"03";
when x"8E6" => DATA <= x"95";
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when x"8E8" => DATA <= x"B9";
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when x"8EA" => DATA <= x"03";
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when x"8F0" => DATA <= x"95";
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when x"8F4" => DATA <= x"03";
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when x"906" => DATA <= x"42";
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when x"910" => DATA <= x"86";
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when x"A8C" => DATA <= x"B1";
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when x"A91" => DATA <= x"06";
when x"A92" => DATA <= x"20";
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when x"A95" => DATA <= x"C8";
when x"A96" => DATA <= x"D0";
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when x"A98" => DATA <= x"20";
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when x"A9C" => DATA <= x"A1";
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when x"A9E" => DATA <= x"B1";
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when x"AA0" => DATA <= x"85";
when x"AA1" => DATA <= x"25";
when x"AA2" => DATA <= x"C8";
when x"AA3" => DATA <= x"B1";
when x"AA4" => DATA <= x"58";
when x"AA5" => DATA <= x"85";
when x"AA6" => DATA <= x"16";
when x"AA7" => DATA <= x"C8";
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when x"AA9" => DATA <= x"03";
when x"AAA" => DATA <= x"A5";
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when x"AAC" => DATA <= x"18";
when x"AAD" => DATA <= x"E5";
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when x"AAF" => DATA <= x"A5";
when x"AB0" => DATA <= x"25";
when x"AB1" => DATA <= x"E5";
when x"AB2" => DATA <= x"26";
when x"AB3" => DATA <= x"90";
when x"AB4" => DATA <= x"C8";
when x"AB5" => DATA <= x"4C";
when x"AB6" => DATA <= x"CF";
when x"AB7" => DATA <= x"C2";
when x"AB8" => DATA <= x"20";
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when x"ABB" => DATA <= x"E6";
when x"ABC" => DATA <= x"04";
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when x"ABE" => DATA <= x"65";
when x"ABF" => DATA <= x"C4";
when x"AC0" => DATA <= x"4C";
when x"AC1" => DATA <= x"6E";
when x"AC2" => DATA <= x"CA";
when x"AC3" => DATA <= x"A5";
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when x"AC5" => DATA <= x"A4";
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when x"AC9" => DATA <= x"84";
when x"ACA" => DATA <= x"26";
when x"ACB" => DATA <= x"B0";
when x"ACC" => DATA <= x"A1";
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when x"ACE" => DATA <= x"34";
when x"ACF" => DATA <= x"C4";
when x"AD0" => DATA <= x"A4";
when x"AD1" => DATA <= x"15";
when x"AD2" => DATA <= x"F0";
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when x"AD4" => DATA <= x"90";
when x"AD5" => DATA <= x"0F";
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when x"AD7" => DATA <= x"04";
when x"AD8" => DATA <= x"B5";
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when x"ADA" => DATA <= x"D9";
when x"ADB" => DATA <= x"3F";
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when x"ADD" => DATA <= x"F0";
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when x"AE0" => DATA <= x"84";
when x"AE1" => DATA <= x"15";
when x"AE2" => DATA <= x"D0";
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when x"AE4" => DATA <= x"00";
when x"AE5" => DATA <= x"BE";
when x"AE6" => DATA <= x"3F";
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when x"AE8" => DATA <= x"18";
when x"AE9" => DATA <= x"BD";
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when x"AEC" => DATA <= x"79";
when x"AED" => DATA <= x"4A";
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when x"AEF" => DATA <= x"9D";
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when x"AF3" => DATA <= x"52";
when x"AF4" => DATA <= x"BD";
when x"AF5" => DATA <= x"3C";
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when x"AF7" => DATA <= x"79";
when x"AF8" => DATA <= x"55";
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when x"AFD" => DATA <= x"85";
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when x"B00" => DATA <= x"57";
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when x"B03" => DATA <= x"60";
when x"B04" => DATA <= x"02";
when x"B05" => DATA <= x"9D";
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when x"B07" => DATA <= x"03";
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when x"B0A" => DATA <= x"BD";
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when x"B0C" => DATA <= x"03";
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when x"B0E" => DATA <= x"6B";
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when x"B10" => DATA <= x"9D";
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when x"B16" => DATA <= x"38";
when x"B17" => DATA <= x"F9";
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when x"B1C" => DATA <= x"A5";
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when x"B21" => DATA <= x"85";
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when x"B25" => DATA <= x"F9";
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when x"B28" => DATA <= x"85";
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when x"B2C" => DATA <= x"97";
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when x"B30" => DATA <= x"05";
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when x"B37" => DATA <= x"59";
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when x"B3A" => DATA <= x"59";
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when x"B4D" => DATA <= x"85";
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when x"B54" => DATA <= x"4C";
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when x"B59" => DATA <= x"C4";
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when x"B5C" => DATA <= x"20";
when x"B5D" => DATA <= x"79";
when x"B5E" => DATA <= x"C2";
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when x"B62" => DATA <= x"98";
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when x"B6E" => DATA <= x"99";
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when x"B72" => DATA <= x"61";
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when x"B7C" => DATA <= x"A2";
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when x"B7E" => DATA <= x"4C";
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when x"B80" => DATA <= x"C2";
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when x"B84" => DATA <= x"A4";
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when x"BCC" => DATA <= x"02";
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when x"C2D" => DATA <= x"C9";
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when x"C30" => DATA <= x"48";
when x"C31" => DATA <= x"0A";
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when x"C36" => DATA <= x"85";
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when x"C38" => DATA <= x"20";
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when x"C3C" => DATA <= x"8E";
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when x"C3E" => DATA <= x"85";
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when x"C48" => DATA <= x"59";
when x"C49" => DATA <= x"88";
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when x"C4C" => DATA <= x"C8";
when x"C4D" => DATA <= x"D1";
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when x"C4F" => DATA <= x"D0";
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when x"C51" => DATA <= x"C8";
when x"C52" => DATA <= x"B1";
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when x"C54" => DATA <= x"30";
when x"C55" => DATA <= x"45";
when x"C56" => DATA <= x"85";
when x"C57" => DATA <= x"02";
when x"C58" => DATA <= x"C8";
when x"C59" => DATA <= x"B1";
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when x"C5B" => DATA <= x"85";
when x"C5C" => DATA <= x"01";
when x"C5D" => DATA <= x"C8";
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when x"C60" => DATA <= x"88";
when x"C61" => DATA <= x"C5";
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when x"C63" => DATA <= x"F0";
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when x"C65" => DATA <= x"20";
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when x"C68" => DATA <= x"4C";
when x"C69" => DATA <= x"4A";
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when x"C6B" => DATA <= x"20";
when x"C6C" => DATA <= x"A2";
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when x"C70" => DATA <= x"9D";
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when x"C72" => DATA <= x"03";
when x"C73" => DATA <= x"A5";
when x"C74" => DATA <= x"59";
when x"C75" => DATA <= x"9D";
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when x"C77" => DATA <= x"03";
when x"C78" => DATA <= x"60";
when x"C79" => DATA <= x"20";
when x"C7A" => DATA <= x"BC";
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when x"C7C" => DATA <= x"A9";
when x"C7D" => DATA <= x"00";
when x"C7E" => DATA <= x"85";
when x"C7F" => DATA <= x"57";
when x"C80" => DATA <= x"60";
when x"C81" => DATA <= x"20";
when x"C82" => DATA <= x"72";
when x"C83" => DATA <= x"C3";
when x"C84" => DATA <= x"20";
when x"C85" => DATA <= x"34";
when x"C86" => DATA <= x"C4";
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when x"C88" => DATA <= x"05";
when x"C89" => DATA <= x"A2";
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when x"C8B" => DATA <= x"4C";
when x"C8C" => DATA <= x"33";
when x"C8D" => DATA <= x"C2";
when x"C8E" => DATA <= x"20";
when x"C8F" => DATA <= x"09";
when x"C90" => DATA <= x"CD";
when x"C91" => DATA <= x"A5";
when x"C92" => DATA <= x"05";
when x"C93" => DATA <= x"48";
when x"C94" => DATA <= x"A5";
when x"C95" => DATA <= x"06";
when x"C96" => DATA <= x"48";
when x"C97" => DATA <= x"A5";
when x"C98" => DATA <= x"03";
when x"C99" => DATA <= x"48";
when x"C9A" => DATA <= x"A0";
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when x"C9C" => DATA <= x"84";
when x"C9D" => DATA <= x"03";
when x"C9E" => DATA <= x"C8";
when x"C9F" => DATA <= x"84";
when x"CA0" => DATA <= x"06";
when x"CA1" => DATA <= x"A0";
when x"CA2" => DATA <= x"40";
when x"CA3" => DATA <= x"84";
when x"CA4" => DATA <= x"05";
when x"CA5" => DATA <= x"20";
when x"CA6" => DATA <= x"2C";
when x"CA7" => DATA <= x"CA";
when x"CA8" => DATA <= x"68";
when x"CA9" => DATA <= x"85";
when x"CAA" => DATA <= x"03";
when x"CAB" => DATA <= x"68";
when x"CAC" => DATA <= x"85";
when x"CAD" => DATA <= x"06";
when x"CAE" => DATA <= x"68";
when x"CAF" => DATA <= x"85";
when x"CB0" => DATA <= x"05";
when x"CB1" => DATA <= x"A2";
when x"CB2" => DATA <= x"2C";
when x"CB3" => DATA <= x"4C";
when x"CB4" => DATA <= x"33";
when x"CB5" => DATA <= x"C2";
when x"CB6" => DATA <= x"20";
when x"CB7" => DATA <= x"8B";
when x"CB8" => DATA <= x"C7";
when x"CB9" => DATA <= x"A0";
when x"CBA" => DATA <= x"54";
when x"CBB" => DATA <= x"20";
when x"CBC" => DATA <= x"CD";
when x"CBD" => DATA <= x"C3";
when x"CBE" => DATA <= x"20";
when x"CBF" => DATA <= x"09";
when x"CC0" => DATA <= x"CD";
when x"CC1" => DATA <= x"A2";
when x"CC2" => DATA <= x"40";
when x"CC3" => DATA <= x"A0";
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when x"CC6" => DATA <= x"00";
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when x"CCA" => DATA <= x"C9";
when x"CCB" => DATA <= x"0D";
when x"CCC" => DATA <= x"F0";
when x"CCD" => DATA <= x"B3";
when x"CCE" => DATA <= x"E8";
when x"CCF" => DATA <= x"C8";
when x"CD0" => DATA <= x"D0";
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when x"CD2" => DATA <= x"20";
when x"CD3" => DATA <= x"0C";
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when x"CD5" => DATA <= x"A4";
when x"CD6" => DATA <= x"13";
when x"CD7" => DATA <= x"F0";
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when x"CDA" => DATA <= x"86";
when x"CDB" => DATA <= x"04";
when x"CDC" => DATA <= x"B5";
when x"CDD" => DATA <= x"16";
when x"CDE" => DATA <= x"F0";
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when x"CE0" => DATA <= x"C6";
when x"CE1" => DATA <= x"13";
when x"CE2" => DATA <= x"4C";
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when x"CE4" => DATA <= x"C5";
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when x"CE6" => DATA <= x"B8";
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when x"CE8" => DATA <= x"85";
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when x"CEC" => DATA <= x"02";
when x"CED" => DATA <= x"4C";
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when x"CEF" => DATA <= x"CB";
when x"CF0" => DATA <= x"A6";
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when x"CF2" => DATA <= x"E0";
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when x"CFA" => DATA <= x"A5";
when x"CFB" => DATA <= x"05";
when x"CFC" => DATA <= x"9D";
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when x"CFF" => DATA <= x"A5";
when x"D00" => DATA <= x"06";
when x"D01" => DATA <= x"9D";
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when x"D03" => DATA <= x"02";
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when x"D0A" => DATA <= x"3F";
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when x"D0C" => DATA <= x"40";
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when x"D0F" => DATA <= x"A0";
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when x"D14" => DATA <= x"84";
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when x"D16" => DATA <= x"A4";
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when x"EAB" => DATA <= x"4C";
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when x"EB2" => DATA <= x"26";
when x"EB3" => DATA <= x"4C";
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when x"EB6" => DATA <= x"20";
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when x"EB9" => DATA <= x"20";
when x"EBA" => DATA <= x"CB";
when x"EBB" => DATA <= x"C3";
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when x"EBD" => DATA <= x"03";
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when x"EBF" => DATA <= x"20";
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when x"EC1" => DATA <= x"C4";
when x"EC2" => DATA <= x"84";
when x"EC3" => DATA <= x"53";
when x"EC4" => DATA <= x"88";
when x"EC5" => DATA <= x"A2";
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when x"EC7" => DATA <= x"B1";
when x"EC8" => DATA <= x"05";
when x"EC9" => DATA <= x"C9";
when x"ECA" => DATA <= x"0D";
when x"ECB" => DATA <= x"F0";
when x"ECC" => DATA <= x"F9";
when x"ECD" => DATA <= x"9D";
when x"ECE" => DATA <= x"40";
when x"ECF" => DATA <= x"01";
when x"ED0" => DATA <= x"E8";
when x"ED1" => DATA <= x"C8";
when x"ED2" => DATA <= x"C9";
when x"ED3" => DATA <= x"22";
when x"ED4" => DATA <= x"D0";
when x"ED5" => DATA <= x"F1";
when x"ED6" => DATA <= x"B1";
when x"ED7" => DATA <= x"05";
when x"ED8" => DATA <= x"C9";
when x"ED9" => DATA <= x"22";
when x"EDA" => DATA <= x"F0";
when x"EDB" => DATA <= x"0E";
when x"EDC" => DATA <= x"A9";
when x"EDD" => DATA <= x"0D";
when x"EDE" => DATA <= x"9D";
when x"EDF" => DATA <= x"3F";
when x"EE0" => DATA <= x"01";
when x"EE1" => DATA <= x"84";
when x"EE2" => DATA <= x"03";
when x"EE3" => DATA <= x"A9";
when x"EE4" => DATA <= x"40";
when x"EE5" => DATA <= x"85";
when x"EE6" => DATA <= x"52";
when x"EE7" => DATA <= x"A6";
when x"EE8" => DATA <= x"04";
when x"EE9" => DATA <= x"60";
when x"EEA" => DATA <= x"C8";
when x"EEB" => DATA <= x"B0";
when x"EEC" => DATA <= x"DA";
when x"EED" => DATA <= x"20";
when x"EEE" => DATA <= x"FA";
when x"EEF" => DATA <= x"CE";
when x"EF0" => DATA <= x"88";
when x"EF1" => DATA <= x"84";
when x"EF2" => DATA <= x"56";
when x"EF3" => DATA <= x"38";
when x"EF4" => DATA <= x"20";
when x"EF5" => DATA <= x"E0";
when x"EF6" => DATA <= x"FF";
when x"EF7" => DATA <= x"4C";
when x"EF8" => DATA <= x"9B";
when x"EF9" => DATA <= x"CD";
when x"EFA" => DATA <= x"20";
when x"EFB" => DATA <= x"B1";
when x"EFC" => DATA <= x"CE";
when x"EFD" => DATA <= x"20";
when x"EFE" => DATA <= x"E4";
when x"EFF" => DATA <= x"C4";
when x"F00" => DATA <= x"88";
when x"F01" => DATA <= x"84";
when x"F02" => DATA <= x"54";
when x"F03" => DATA <= x"A5";
when x"F04" => DATA <= x"12";
when x"F05" => DATA <= x"85";
when x"F06" => DATA <= x"55";
when x"F07" => DATA <= x"A2";
when x"F08" => DATA <= x"52";
when x"F09" => DATA <= x"60";
when x"F0A" => DATA <= x"20";
when x"F0B" => DATA <= x"FA";
when x"F0C" => DATA <= x"CE";
when x"F0D" => DATA <= x"84";
when x"F0E" => DATA <= x"58";
when x"F0F" => DATA <= x"85";
when x"F10" => DATA <= x"59";
when x"F11" => DATA <= x"A5";
when x"F12" => DATA <= x"0D";
when x"F13" => DATA <= x"85";
when x"F14" => DATA <= x"5A";
when x"F15" => DATA <= x"A5";
when x"F16" => DATA <= x"0E";
when x"F17" => DATA <= x"85";
when x"F18" => DATA <= x"5B";
when x"F19" => DATA <= x"A9";
when x"F1A" => DATA <= x"B2";
when x"F1B" => DATA <= x"85";
when x"F1C" => DATA <= x"56";
when x"F1D" => DATA <= x"A9";
when x"F1E" => DATA <= x"C2";
when x"F1F" => DATA <= x"85";
when x"F20" => DATA <= x"57";
when x"F21" => DATA <= x"18";
when x"F22" => DATA <= x"20";
when x"F23" => DATA <= x"DD";
when x"F24" => DATA <= x"FF";
when x"F25" => DATA <= x"4C";
when x"F26" => DATA <= x"5B";
when x"F27" => DATA <= x"C5";
when x"F28" => DATA <= x"38";
when x"F29" => DATA <= x"A9";
when x"F2A" => DATA <= x"00";
when x"F2B" => DATA <= x"2A";
when x"F2C" => DATA <= x"48";
when x"F2D" => DATA <= x"20";
when x"F2E" => DATA <= x"3E";
when x"F2F" => DATA <= x"CF";
when x"F30" => DATA <= x"A2";
when x"F31" => DATA <= x"52";
when x"F32" => DATA <= x"68";
when x"F33" => DATA <= x"20";
when x"F34" => DATA <= x"DA";
when x"F35" => DATA <= x"FF";
when x"F36" => DATA <= x"A0";
when x"F37" => DATA <= x"52";
when x"F38" => DATA <= x"20";
when x"F39" => DATA <= x"9F";
when x"F3A" => DATA <= x"C9";
when x"F3B" => DATA <= x"95";
when x"F3C" => DATA <= x"42";
when x"F3D" => DATA <= x"60";
when x"F3E" => DATA <= x"20";
when x"F3F" => DATA <= x"BC";
when x"F40" => DATA <= x"C8";
when x"F41" => DATA <= x"B4";
when x"F42" => DATA <= x"15";
when x"F43" => DATA <= x"CA";
when x"F44" => DATA <= x"86";
when x"F45" => DATA <= x"04";
when x"F46" => DATA <= x"60";
when x"F47" => DATA <= x"20";
when x"F48" => DATA <= x"BC";
when x"F49" => DATA <= x"C8";
when x"F4A" => DATA <= x"20";
when x"F4B" => DATA <= x"DE";
when x"F4C" => DATA <= x"C4";
when x"F4D" => DATA <= x"20";
when x"F4E" => DATA <= x"CB";
when x"F4F" => DATA <= x"C3";
when x"F50" => DATA <= x"20";
when x"F51" => DATA <= x"41";
when x"F52" => DATA <= x"CF";
when x"F53" => DATA <= x"A2";
when x"F54" => DATA <= x"52";
when x"F55" => DATA <= x"20";
when x"F56" => DATA <= x"D7";
when x"F57" => DATA <= x"FF";
when x"F58" => DATA <= x"4C";
when x"F59" => DATA <= x"5B";
when x"F5A" => DATA <= x"C5";
when x"F5B" => DATA <= x"20";
when x"F5C" => DATA <= x"3E";
when x"F5D" => DATA <= x"CF";
when x"F5E" => DATA <= x"84";
when x"F5F" => DATA <= x"52";
when x"F60" => DATA <= x"20";
when x"F61" => DATA <= x"D4";
when x"F62" => DATA <= x"FF";
when x"F63" => DATA <= x"4C";
when x"F64" => DATA <= x"7C";
when x"F65" => DATA <= x"C9";
when x"F66" => DATA <= x"20";
when x"F67" => DATA <= x"5B";
when x"F68" => DATA <= x"CF";
when x"F69" => DATA <= x"A4";
when x"F6A" => DATA <= x"52";
when x"F6B" => DATA <= x"20";
when x"F6C" => DATA <= x"D4";
when x"F6D" => DATA <= x"FF";
when x"F6E" => DATA <= x"95";
when x"F6F" => DATA <= x"24";
when x"F70" => DATA <= x"20";
when x"F71" => DATA <= x"D4";
when x"F72" => DATA <= x"FF";
when x"F73" => DATA <= x"95";
when x"F74" => DATA <= x"33";
when x"F75" => DATA <= x"20";
when x"F76" => DATA <= x"D4";
when x"F77" => DATA <= x"FF";
when x"F78" => DATA <= x"95";
when x"F79" => DATA <= x"42";
when x"F7A" => DATA <= x"60";
when x"F7B" => DATA <= x"20";
when x"F7C" => DATA <= x"BC";
when x"F7D" => DATA <= x"C8";
when x"F7E" => DATA <= x"20";
when x"F7F" => DATA <= x"31";
when x"F80" => DATA <= x"C2";
when x"F81" => DATA <= x"20";
when x"F82" => DATA <= x"E1";
when x"F83" => DATA <= x"C4";
when x"F84" => DATA <= x"20";
when x"F85" => DATA <= x"CB";
when x"F86" => DATA <= x"C3";
when x"F87" => DATA <= x"20";
when x"F88" => DATA <= x"41";
when x"F89" => DATA <= x"CF";
when x"F8A" => DATA <= x"A5";
when x"F8B" => DATA <= x"52";
when x"F8C" => DATA <= x"6C";
when x"F8D" => DATA <= x"16";
when x"F8E" => DATA <= x"02";
when x"F8F" => DATA <= x"20";
when x"F90" => DATA <= x"7B";
when x"F91" => DATA <= x"CF";
when x"F92" => DATA <= x"4C";
when x"F93" => DATA <= x"5B";
when x"F94" => DATA <= x"C5";
when x"F95" => DATA <= x"20";
when x"F96" => DATA <= x"7B";
when x"F97" => DATA <= x"CF";
when x"F98" => DATA <= x"A2";
when x"F99" => DATA <= x"01";
when x"F9A" => DATA <= x"B5";
when x"F9B" => DATA <= x"52";
when x"F9C" => DATA <= x"20";
when x"F9D" => DATA <= x"D1";
when x"F9E" => DATA <= x"FF";
when x"F9F" => DATA <= x"E8";
when x"FA0" => DATA <= x"E0";
when x"FA1" => DATA <= x"04";
when x"FA2" => DATA <= x"90";
when x"FA3" => DATA <= x"F6";
when x"FA4" => DATA <= x"B0";
when x"FA5" => DATA <= x"EC";
when x"FA6" => DATA <= x"38";
when x"FA7" => DATA <= x"08";
when x"FA8" => DATA <= x"20";
when x"FA9" => DATA <= x"B1";
when x"FAA" => DATA <= x"CE";
when x"FAB" => DATA <= x"A2";
when x"FAC" => DATA <= x"52";
when x"FAD" => DATA <= x"28";
when x"FAE" => DATA <= x"20";
when x"FAF" => DATA <= x"CE";
when x"FB0" => DATA <= x"FF";
when x"FB1" => DATA <= x"A6";
when x"FB2" => DATA <= x"04";
when x"FB3" => DATA <= x"4C";
when x"FB4" => DATA <= x"7C";
when x"FB5" => DATA <= x"C9";
when x"FB6" => DATA <= x"20";
when x"FB7" => DATA <= x"BC";
when x"FB8" => DATA <= x"C8";
when x"FB9" => DATA <= x"20";
when x"FBA" => DATA <= x"E4";
when x"FBB" => DATA <= x"C4";
when x"FBC" => DATA <= x"20";
when x"FBD" => DATA <= x"41";
when x"FBE" => DATA <= x"CF";
when x"FBF" => DATA <= x"20";
when x"FC0" => DATA <= x"CB";
when x"FC1" => DATA <= x"FF";
when x"FC2" => DATA <= x"4C";
when x"FC3" => DATA <= x"5B";
when x"FC4" => DATA <= x"C5";
when x"FC5" => DATA <= x"20";
when x"FC6" => DATA <= x"2C";
when x"FC7" => DATA <= x"C2";
when x"FC8" => DATA <= x"20";
when x"FC9" => DATA <= x"B1";
when x"FCA" => DATA <= x"CE";
when x"FCB" => DATA <= x"20";
when x"FCC" => DATA <= x"E4";
when x"FCD" => DATA <= x"C4";
when x"FCE" => DATA <= x"88";
when x"FCF" => DATA <= x"B1";
when x"FD0" => DATA <= x"52";
when x"FD1" => DATA <= x"84";
when x"FD2" => DATA <= x"55";
when x"FD3" => DATA <= x"A4";
when x"FD4" => DATA <= x"0F";
when x"FD5" => DATA <= x"48";
when x"FD6" => DATA <= x"20";
when x"FD7" => DATA <= x"D1";
when x"FD8" => DATA <= x"FF";
when x"FD9" => DATA <= x"68";
when x"FDA" => DATA <= x"C9";
when x"FDB" => DATA <= x"0D";
when x"FDC" => DATA <= x"F0";
when x"FDD" => DATA <= x"E4";
when x"FDE" => DATA <= x"A4";
when x"FDF" => DATA <= x"55";
when x"FE0" => DATA <= x"C8";
when x"FE1" => DATA <= x"D0";
when x"FE2" => DATA <= x"EC";
when x"FE3" => DATA <= x"20";
when x"FE4" => DATA <= x"2C";
when x"FE5" => DATA <= x"C2";
when x"FE6" => DATA <= x"20";
when x"FE7" => DATA <= x"E1";
when x"FE8" => DATA <= x"C4";
when x"FE9" => DATA <= x"20";
when x"FEA" => DATA <= x"CB";
when x"FEB" => DATA <= x"C3";
when x"FEC" => DATA <= x"A0";
when x"FED" => DATA <= x"00";
when x"FEE" => DATA <= x"84";
when x"FEF" => DATA <= x"55";
when x"FF0" => DATA <= x"A4";
when x"FF1" => DATA <= x"0F";
when x"FF2" => DATA <= x"20";
when x"FF3" => DATA <= x"D4";
when x"FF4" => DATA <= x"FF";
when x"FF5" => DATA <= x"A4";
when x"FF6" => DATA <= x"55";
when x"FF7" => DATA <= x"91";
when x"FF8" => DATA <= x"52";
when x"FF9" => DATA <= x"C8";
when x"FFA" => DATA <= x"C9";
when x"FFB" => DATA <= x"0D";
when x"FFC" => DATA <= x"D0";
when x"FFD" => DATA <= x"F0";
when x"FFE" => DATA <= x"F0";
when x"FFF" => DATA <= x"C2";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent93 is
end ent93;
architecture arch of ent93 is
begin
process
variable color: bit_vector(2 downto 0);
variable lcol: std_logic_vector(31 downto 0);
begin
lcol := (
23 downto 16 => color(2),
15 downto 8 => color(1),
7 downto 0 => color(0),
others=> '0'
);
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: dcache
-- File: dcache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use work.config.all;
use work.sparcv8.all; -- ASI declarations
use work.iface.all;
use work.macro.all; -- xorv()
entity dcache is
port (
rst : in std_logic;
clk : in clk_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_logic
);
end;
architecture rtl of dcache is
constant TAG_HIGH : integer := DTAG_HIGH;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH: integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
type rdatatype is (dtag, ddata, icache, memory); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_logic;
lock : std_logic;
end record;
type dcache_control_type is record -- all registers
read : std_logic; -- access direction
signed : std_logic; -- signed/unsigned read
asi : std_logic_vector(3 downto 0); -- asi
size : std_logic_vector(1 downto 0); -- access size
req, burst, holdn, nomds, stpend : std_logic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
valid : std_logic_vector(DLINE_SIZE - 1 downto 0); -- registered valid bits
dstate : std_logic_vector(2 downto 0); -- FSM vector
hit : std_logic;
flush : std_logic; -- flush in progress
mexc : std_logic; -- latched mexc
wb : write_buffer_type; -- write buffer
icenable : std_logic; -- icache diag access
end record;
signal r, c : dcache_control_type; -- r is registers, c is combinational
begin
dctrl : process(rst, r, dci, mcdo, ico, dcramo, fpuholdn)
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_logic;
variable twrite, tdiagwrite, ddiagwrite, dwrite : std_logic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : std_logic_vector(31 downto 0);
variable wdata : std_logic_vector(31 downto 0);
variable vmaskraw, vmask : std_logic_vector((DLINE_SIZE -1) downto 0);
variable vmaskdbl : std_logic_vector((DLINE_SIZE/2 -1) downto 0);
variable enable : std_logic;
variable mds : std_logic;
variable mexc : std_logic;
variable hit, valid, validraw, forcemiss : std_logic;
variable signed : std_logic;
variable flush : std_logic;
variable iflush : std_logic;
variable v : dcache_control_type;
variable eholdn : std_logic; -- external hold
variable tparerr : std_logic;
variable dparerr : std_logic;
begin
-- init local variables
v := r;
mds := '1'; v.req := '0'; dwrite := '0'; twrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn;
tparerr := '0'; dparerr := '0';
enable := '1';
rdatasel := ddata; -- read data from cache as default
-- generate access parameters during pipeline stall
if (r.holdn) = '0' then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0); signed := r.signed;
read := r.read; size := r.size; edata := dci.maddress;
else
maddress := dci.maddress(31 downto 0); signed := dci.signed;
read := dci.read; size := dci.size; edata := dci.edata;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
-- generate cache hit and valid bits
forcemiss := not dci.asi(3);
if (dcramo.dtramout.tag = dci.maddress(TAG_HIGH downto TAG_LOW)) then
hit := (not r.flush) and not tparerr;
else
hit := '0';
end if;
validraw := genmux(dci.maddress(LINE_HIGH downto LINE_LOW),
dcramo.dtramout.valid);
valid := validraw and not dparerr;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = "000") then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.asi := dci.asi(3 downto 0); v.size := dci.size;
v.signed := dci.signed;
end if;
-- Store buffer
wdata := r.wb.data1;
if r.stpend = '1' then
v.req := r.burst or (r.req and not mcdo.grant);
if mcdo.ready = '1' then
v.req := '0'; v.stpend := r.burst; v.burst := '0';
v.wb.addr(2) := '1'; v.wb.data1 := r.wb.data2;
end if;
end if;
if mcdo.ready = '1' then v.wb.addr(2) := '1'; end if;
-- main Dcache state machine
case r.dstate is
when "000" => -- Idle state
v.nomds := r.nomds and not eholdn; v.valid := dcramo.dtramout.valid;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(3 downto 0) is
when ASI_ITAG | ASI_IDATA => -- Read/write Icache tags
if ico.flush = '1' then mexc := '1';
else v.dstate := "101"; v.holdn := '0'; end if;
when ASI_IFLUSH => -- flush instruction cache
if dci.read = '0' then iflush := '1'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
rdatasel := dtag;
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when others =>
if (r.stpend = '0') or ((mcdo.ready and not r.burst)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.asi := dci.asi(3 downto 0); v.wb.read := dci.read;
v.wb.data1 := dci.edata; v.wb.lock := dci.lock;
end if;
if dci.read = '1' then -- read access
if (not ((mcdo.dcs(0) = '1')
and ((hit and valid and not forcemiss) = '1')))
then -- read miss
v.holdn := '0'; v.dstate := "001";
if ((r.stpend = '0') or ((mcdo.ready and not r.burst) = '1'))
then -- wait for store queue
v.req := '1';
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
end if;
end if;
else -- write access
if (r.stpend = '0') or ((mcdo.ready and not r.burst)= '1') then -- wait for store queue
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := "100"; end if; -- double store
else -- wait for store queue
v.dstate := "110"; v.holdn := '0';
end if;
if (mcdo.dcs(0) = '1') and ((hit and (dci.size(1) or valid)) = '1')
then -- write hit
twrite := '1'; dwrite := '1';
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
end case;
end if;
when "001" => -- read miss, wait for memory data
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
if r.stpend = '0' then
v.req := r.req; v.burst := r.req and r.burst;-- and not r.xaddress(2);
if mcdo.grant = '1' then v.req := v.burst; end if;
if mcdo.ready = '1' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
if (mcdo.dcs = "01") then twrite := mcdo.cache and r.hit;
elsif (mcdo.dcs(1) = '1') then twrite := mcdo.cache; end if;
dwrite := twrite; rdatasel := memory;
mexc := mcdo.mexc;
if r.burst = '0' then
if (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (mcdo.dcs(0) = '1') then
v.dstate := "011"; v.holdn := '0';
else v.dstate := "000"; end if;
else v.nomds := '1'; end if;
v.burst := '0'; v.req := '0';
end if;
v.mexc := mcdo.mexc; v.wb.data2 := mcdo.data;
else
if ((mcdo.ready and not r.burst) = '1') then -- wait for store queue
v.burst := r.size(1) and r.size(0) and not r.xaddress(2);
v.wb.addr := r.xaddress; v.wb.size := r.size; v.wb.asi := r.asi(3 downto 0);
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock;
end if;
end if;
when "011" => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
v.dstate := "000";
when "100" => -- second part of double store cycle
v.dstate := "000"; v.wb.data2 := dci.edata;
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (mcdo.dcs(0) = '1') and (r.hit = '1') then dwrite := '1'; end if;
when "101" => -- icache diag access
rdatasel := icache; v.icenable := '1'; v.holdn := '0';
if ico.diagrdy = '1' then
v.dstate := "011"; v.icenable := '0'; mds := not r.read;
end if;
when "110" => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if ((mcdo.ready and not r.burst) = '1') then -- store queue emptied
if (mcdo.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := '1';
end if;
v.dstate := "000";
v.req := '1'; v.burst := r.size(1) and r.size(0); v.stpend := '1';
v.wb.addr := r.xaddress; v.wb.size := r.size;
v.wb.asi := r.asi(3 downto 0);
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock;
v.wb.data2 := dci.edata;
if r.size = "11" then v.wb.addr(2) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when others => v.dstate := "000";
end case;
-- select data to return on read access
-- align if byte/half word read from cache or memory.
rdata := (others => '0');
align_data := (others => '0');
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when dtag =>
rdata(TAG_HIGH downto TAG_LOW) := dcramo.dtramout.tag;
rdata(DLINE_SIZE -1 downto 0) := dcramo.dtramout.valid;
when icache => rdata := ico.diagdata;
when ddata | memory =>
if rdatasel = ddata then align_data := dcramo.ddramout.data;
else align_data := mcdo.data; end if;
case size is
when "00" => -- byte read
case maddrlow is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if maddress(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
end case;
-- select which data to update the data cache with
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatain := edata(7 downto 0) & dcramo.ddramout.data(23 downto 0);
when "01" =>
ddatain := dcramo.ddramout.data(31 downto 24) & edata(7 downto 0) &
dcramo.ddramout.data(15 downto 0);
when "10" =>
ddatain := dcramo.ddramout.data(31 downto 16) & edata(7 downto 0) &
dcramo.ddramout.data(7 downto 0);
when others =>
ddatain := dcramo.ddramout.data(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatain := edata(15 downto 0) & dcramo.ddramout.data(15 downto 0);
else
ddatain := dcramo.ddramout.data(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatain := edata;
end case;
-- handle double load with pipeline hold
if (r.dstate = "000") and (r.nomds = '1') then
rdata := r.wb.data2; mexc := r.mexc;
end if;
-- Handle AHB retry
v.req := v.req or mcdo.retry;
-- Generate new valid bits
vmaskdbl := decode(maddress(LINE_HIGH downto LINE_LOW+1));
if (size = "11") and (read = '0') then
for i in 0 to (DLINE_SIZE - 1) loop vmaskraw(i) := vmaskdbl(i/2); end loop;
else
vmaskraw := decode(maddress(LINE_HIGH downto LINE_LOW));
end if;
vmask := vmaskraw;
if r.hit = '1' then vmask := r.valid or vmaskraw; end if;
if r.dstate = "000" then
vmask := dcramo.dtramout.valid or vmaskraw;
end if;
if (mcdo.mexc or r.flush) = '1' then
twrite := '0'; dwrite := '0';
end if;
if twrite = '1' then
v.valid := vmask; if (r.dstate = "001") then v.hit := mcdo.cache; end if;
end if;
if tdiagwrite = '1' then -- diagnostic tag write
vmask := dci.edata(DLINE_SIZE - 1 downto 0);
end if;
-- cache flush
if (dci.flush or flush) = '1' then
v.flush := '1'; v.faddr := (others => '0');
end if;
if r.flush = '1' then
twrite := '1'; vmask := (others => '0'); v.faddr := r.faddr +1;
newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
-- taddr(OFFSET_LOW-1 downto LINE_LOW) := (others => '0');
if (r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) = '1' then
v.flush := '0';
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then ddatain := mcdo.data; end if;
-- reset
if rst = '0' then
v.dstate := "000"; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0';
end if;
-- Drive signals
c <= v; -- register inputs
-- tag ram inputs
dcrami.dtramin.valid <= vmask;
dcrami.dtramin.tag <= newtag(TAG_HIGH downto TAG_LOW);
dcrami.dtramin.enable <= enable;
dcrami.dtramin.write <= twrite;
-- data ram inputs
dcrami.ddramin.enable <= enable;
dcrami.ddramin.address <= taddr;
dcrami.ddramin.data <= ddatain;
dcrami.ddramin.write <= dwrite;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.asi <= r.wb.asi;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.flush <= r.flush;
-- diagnostic instruction cache
dco.icdiag.flush <= iflush;
dco.icdiag.read <= read;
dco.icdiag.tag <= not r.asi(0);
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
-- IU data cache inputs
dco.data <= rdata;
dco.mexc <= mexc;
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
end process;
-- Local registers
dlat : process(clk)
begin if rising_edge(clk) then r <= c; end if; end process;
end ;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: dcache
-- File: dcache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use work.config.all;
use work.sparcv8.all; -- ASI declarations
use work.iface.all;
use work.macro.all; -- xorv()
entity dcache is
port (
rst : in std_logic;
clk : in clk_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_logic
);
end;
architecture rtl of dcache is
constant TAG_HIGH : integer := DTAG_HIGH;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH: integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
type rdatatype is (dtag, ddata, icache, memory); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_logic;
lock : std_logic;
end record;
type dcache_control_type is record -- all registers
read : std_logic; -- access direction
signed : std_logic; -- signed/unsigned read
asi : std_logic_vector(3 downto 0); -- asi
size : std_logic_vector(1 downto 0); -- access size
req, burst, holdn, nomds, stpend : std_logic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
valid : std_logic_vector(DLINE_SIZE - 1 downto 0); -- registered valid bits
dstate : std_logic_vector(2 downto 0); -- FSM vector
hit : std_logic;
flush : std_logic; -- flush in progress
mexc : std_logic; -- latched mexc
wb : write_buffer_type; -- write buffer
icenable : std_logic; -- icache diag access
end record;
signal r, c : dcache_control_type; -- r is registers, c is combinational
begin
dctrl : process(rst, r, dci, mcdo, ico, dcramo, fpuholdn)
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_logic;
variable twrite, tdiagwrite, ddiagwrite, dwrite : std_logic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : std_logic_vector(31 downto 0);
variable wdata : std_logic_vector(31 downto 0);
variable vmaskraw, vmask : std_logic_vector((DLINE_SIZE -1) downto 0);
variable vmaskdbl : std_logic_vector((DLINE_SIZE/2 -1) downto 0);
variable enable : std_logic;
variable mds : std_logic;
variable mexc : std_logic;
variable hit, valid, validraw, forcemiss : std_logic;
variable signed : std_logic;
variable flush : std_logic;
variable iflush : std_logic;
variable v : dcache_control_type;
variable eholdn : std_logic; -- external hold
variable tparerr : std_logic;
variable dparerr : std_logic;
begin
-- init local variables
v := r;
mds := '1'; v.req := '0'; dwrite := '0'; twrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn;
tparerr := '0'; dparerr := '0';
enable := '1';
rdatasel := ddata; -- read data from cache as default
-- generate access parameters during pipeline stall
if (r.holdn) = '0' then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0); signed := r.signed;
read := r.read; size := r.size; edata := dci.maddress;
else
maddress := dci.maddress(31 downto 0); signed := dci.signed;
read := dci.read; size := dci.size; edata := dci.edata;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
-- generate cache hit and valid bits
forcemiss := not dci.asi(3);
if (dcramo.dtramout.tag = dci.maddress(TAG_HIGH downto TAG_LOW)) then
hit := (not r.flush) and not tparerr;
else
hit := '0';
end if;
validraw := genmux(dci.maddress(LINE_HIGH downto LINE_LOW),
dcramo.dtramout.valid);
valid := validraw and not dparerr;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = "000") then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.asi := dci.asi(3 downto 0); v.size := dci.size;
v.signed := dci.signed;
end if;
-- Store buffer
wdata := r.wb.data1;
if r.stpend = '1' then
v.req := r.burst or (r.req and not mcdo.grant);
if mcdo.ready = '1' then
v.req := '0'; v.stpend := r.burst; v.burst := '0';
v.wb.addr(2) := '1'; v.wb.data1 := r.wb.data2;
end if;
end if;
if mcdo.ready = '1' then v.wb.addr(2) := '1'; end if;
-- main Dcache state machine
case r.dstate is
when "000" => -- Idle state
v.nomds := r.nomds and not eholdn; v.valid := dcramo.dtramout.valid;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(3 downto 0) is
when ASI_ITAG | ASI_IDATA => -- Read/write Icache tags
if ico.flush = '1' then mexc := '1';
else v.dstate := "101"; v.holdn := '0'; end if;
when ASI_IFLUSH => -- flush instruction cache
if dci.read = '0' then iflush := '1'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
rdatasel := dtag;
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when others =>
if (r.stpend = '0') or ((mcdo.ready and not r.burst)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.asi := dci.asi(3 downto 0); v.wb.read := dci.read;
v.wb.data1 := dci.edata; v.wb.lock := dci.lock;
end if;
if dci.read = '1' then -- read access
if (not ((mcdo.dcs(0) = '1')
and ((hit and valid and not forcemiss) = '1')))
then -- read miss
v.holdn := '0'; v.dstate := "001";
if ((r.stpend = '0') or ((mcdo.ready and not r.burst) = '1'))
then -- wait for store queue
v.req := '1';
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
end if;
end if;
else -- write access
if (r.stpend = '0') or ((mcdo.ready and not r.burst)= '1') then -- wait for store queue
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := "100"; end if; -- double store
else -- wait for store queue
v.dstate := "110"; v.holdn := '0';
end if;
if (mcdo.dcs(0) = '1') and ((hit and (dci.size(1) or valid)) = '1')
then -- write hit
twrite := '1'; dwrite := '1';
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
end case;
end if;
when "001" => -- read miss, wait for memory data
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
if r.stpend = '0' then
v.req := r.req; v.burst := r.req and r.burst;-- and not r.xaddress(2);
if mcdo.grant = '1' then v.req := v.burst; end if;
if mcdo.ready = '1' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
if (mcdo.dcs = "01") then twrite := mcdo.cache and r.hit;
elsif (mcdo.dcs(1) = '1') then twrite := mcdo.cache; end if;
dwrite := twrite; rdatasel := memory;
mexc := mcdo.mexc;
if r.burst = '0' then
if (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (mcdo.dcs(0) = '1') then
v.dstate := "011"; v.holdn := '0';
else v.dstate := "000"; end if;
else v.nomds := '1'; end if;
v.burst := '0'; v.req := '0';
end if;
v.mexc := mcdo.mexc; v.wb.data2 := mcdo.data;
else
if ((mcdo.ready and not r.burst) = '1') then -- wait for store queue
v.burst := r.size(1) and r.size(0) and not r.xaddress(2);
v.wb.addr := r.xaddress; v.wb.size := r.size; v.wb.asi := r.asi(3 downto 0);
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock;
end if;
end if;
when "011" => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
v.dstate := "000";
when "100" => -- second part of double store cycle
v.dstate := "000"; v.wb.data2 := dci.edata;
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (mcdo.dcs(0) = '1') and (r.hit = '1') then dwrite := '1'; end if;
when "101" => -- icache diag access
rdatasel := icache; v.icenable := '1'; v.holdn := '0';
if ico.diagrdy = '1' then
v.dstate := "011"; v.icenable := '0'; mds := not r.read;
end if;
when "110" => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if ((mcdo.ready and not r.burst) = '1') then -- store queue emptied
if (mcdo.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := '1';
end if;
v.dstate := "000";
v.req := '1'; v.burst := r.size(1) and r.size(0); v.stpend := '1';
v.wb.addr := r.xaddress; v.wb.size := r.size;
v.wb.asi := r.asi(3 downto 0);
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock;
v.wb.data2 := dci.edata;
if r.size = "11" then v.wb.addr(2) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when others => v.dstate := "000";
end case;
-- select data to return on read access
-- align if byte/half word read from cache or memory.
rdata := (others => '0');
align_data := (others => '0');
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when dtag =>
rdata(TAG_HIGH downto TAG_LOW) := dcramo.dtramout.tag;
rdata(DLINE_SIZE -1 downto 0) := dcramo.dtramout.valid;
when icache => rdata := ico.diagdata;
when ddata | memory =>
if rdatasel = ddata then align_data := dcramo.ddramout.data;
else align_data := mcdo.data; end if;
case size is
when "00" => -- byte read
case maddrlow is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if maddress(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
end case;
-- select which data to update the data cache with
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatain := edata(7 downto 0) & dcramo.ddramout.data(23 downto 0);
when "01" =>
ddatain := dcramo.ddramout.data(31 downto 24) & edata(7 downto 0) &
dcramo.ddramout.data(15 downto 0);
when "10" =>
ddatain := dcramo.ddramout.data(31 downto 16) & edata(7 downto 0) &
dcramo.ddramout.data(7 downto 0);
when others =>
ddatain := dcramo.ddramout.data(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatain := edata(15 downto 0) & dcramo.ddramout.data(15 downto 0);
else
ddatain := dcramo.ddramout.data(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatain := edata;
end case;
-- handle double load with pipeline hold
if (r.dstate = "000") and (r.nomds = '1') then
rdata := r.wb.data2; mexc := r.mexc;
end if;
-- Handle AHB retry
v.req := v.req or mcdo.retry;
-- Generate new valid bits
vmaskdbl := decode(maddress(LINE_HIGH downto LINE_LOW+1));
if (size = "11") and (read = '0') then
for i in 0 to (DLINE_SIZE - 1) loop vmaskraw(i) := vmaskdbl(i/2); end loop;
else
vmaskraw := decode(maddress(LINE_HIGH downto LINE_LOW));
end if;
vmask := vmaskraw;
if r.hit = '1' then vmask := r.valid or vmaskraw; end if;
if r.dstate = "000" then
vmask := dcramo.dtramout.valid or vmaskraw;
end if;
if (mcdo.mexc or r.flush) = '1' then
twrite := '0'; dwrite := '0';
end if;
if twrite = '1' then
v.valid := vmask; if (r.dstate = "001") then v.hit := mcdo.cache; end if;
end if;
if tdiagwrite = '1' then -- diagnostic tag write
vmask := dci.edata(DLINE_SIZE - 1 downto 0);
end if;
-- cache flush
if (dci.flush or flush) = '1' then
v.flush := '1'; v.faddr := (others => '0');
end if;
if r.flush = '1' then
twrite := '1'; vmask := (others => '0'); v.faddr := r.faddr +1;
newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
-- taddr(OFFSET_LOW-1 downto LINE_LOW) := (others => '0');
if (r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) = '1' then
v.flush := '0';
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then ddatain := mcdo.data; end if;
-- reset
if rst = '0' then
v.dstate := "000"; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0';
end if;
-- Drive signals
c <= v; -- register inputs
-- tag ram inputs
dcrami.dtramin.valid <= vmask;
dcrami.dtramin.tag <= newtag(TAG_HIGH downto TAG_LOW);
dcrami.dtramin.enable <= enable;
dcrami.dtramin.write <= twrite;
-- data ram inputs
dcrami.ddramin.enable <= enable;
dcrami.ddramin.address <= taddr;
dcrami.ddramin.data <= ddatain;
dcrami.ddramin.write <= dwrite;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.asi <= r.wb.asi;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.flush <= r.flush;
-- diagnostic instruction cache
dco.icdiag.flush <= iflush;
dco.icdiag.read <= read;
dco.icdiag.tag <= not r.asi(0);
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
-- IU data cache inputs
dco.data <= rdata;
dco.mexc <= mexc;
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
end process;
-- Local registers
dlat : process(clk)
begin if rising_edge(clk) then r <= c; end if; end process;
end ;
|
-- Processador Versao 3: 23/05/2013
-- Jeg e Ceg concertado!!
-- Video com 16 cores e tela de 40 colunas por 30 linhas
libraRY ieee;
use ieee.std_LOGIC_1164.all;
use ieee.std_LOGIC_ARITH.all;
use ieee.std_LOGIC_unsigned.all;
entity cpu is
port( clk : in std_LOGIC;
reset : in std_LOGIC;
Mem : in STD_LOGIC_VECTOR(15 downto 0);
M5 : out STD_LOGIC_VECTOR(15 downto 0);
M1 : out STD_LOGIC_VECTOR(15 downto 0);
RW : out std_LOGIC;
key : in STD_LOGIC_VECTOR(7 downto 0);
videoflag : out std_LOGIC;
vga_pos : out STD_LOGIC_VECTOR(15 downto 0);
vga_char : out STD_LOGIC_VECTOR(15 downto 0);
Ponto : out STD_LOGIC_VECTOR(2 downto 0);
halt_ack : out std_LOGIC;
halt_req : in std_LOGIC;
PC_data : out STD_LOGIC_VECTOR(15 downto 0);
break : out STD_LOGIC
);
end cpu;
ARCHITECTURE main of cpu is
TYPE STATES is (fetch, decode, exec, halted); -- Estados da Maquina de Controle do Processador
TYPE Registers is array(0 to 7) of STD_LOGIC_VECTOR(15 downto 0); -- Banco de Registradores
TYPE LoadRegisters is array(0 to 7) of std_LOGIC; -- Sinais de LOAD dos Registradores do Banco
-- INSTRUCTION SET: 29 INSTRUCTIONS
-- Data Manipulation Instructions: -- Usage -- Action -- Format
CONSTANT LOAD : STD_LOGIC_VECTOR(5 downto 0) := "110000"; -- LOAD RX END -- RX <- M[END] Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END
CONSTANT STORE : STD_LOGIC_VECTOR(5 downto 0) := "110001"; -- STORE END RX -- M[END] <- RX Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END
CONSTANT LOADIMED : STD_LOGIC_VECTOR(5 downto 0) := "111000"; -- LOADN RX Nr -- RX <- Nr Format: < inst(6) | RX(3) | xxxxxxb0 > + 16bit Numero
CONSTANT LOADINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111100"; -- LOADI RX RY -- RX <- M[RY] Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT STOREINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111101"; -- STOREI RX RY -- M[RX] <- RY Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT MOV : STD_LOGIC_VECTOR(5 downto 0) := "110011"; -- MOV RX RY -- RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 >
-- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 >
-- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 >
-- I/O Instructions:
CONSTANT OUTCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110010"; -- OUTCHAR RX RY -- Video[RY] <- Char(RX) Format: < inst(6) | RX(3) | RY(3) | xxxx >
-- RX contem o codigo do caracter de 0 a 127, sendo que 96 iniciais estao prontos com a tabela ASCII
-- RX(6 downto 0) + 32 = Caractere da tabela ASCII - Ver Manual PDF
-- RX(10 downto 7) = Cor : 0-branco, 1-marrom, 2-verde, 3-oliva, 4-azul marinho, 5-roxo, 6-teal, 7-prata, 8-cinza, 9-vermelho, 10-lima, 11-amarelo, 12-azul, 13-rosa, 14-aqua, 15-preto
-- RY(10 downto 0) = tamanho da tela = 30 linhas x 40 colunas: posicao continua de 0 a 1199 no RY
CONSTANT INCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110101"; -- INCHAR RX -- RX[5..0] <- KeyPressed RX[15..6] <- 0's Format: < inst(6) | RX(3) | xxxxxxx >
-- Se nao pressionar nenhuma tecla, RX recebe 00FF
CONSTANT ARITH : STD_LOGIC_VECTOR(1 downto 0) := "10";
-- Aritmethic Instructions(All should begin wiht "10"):
CONSTANT ADD : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- ADD RX RY RZ / ADDC RX RY RZ -- RX <- RY + RZ / RX <- RY + RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT SUB : STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- SUB RX RY RZ / SUBC RX RY RZ -- RX <- RY - RZ / RX <- RY - RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT MULT : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- MUL RX RY RZ / MUL RX RY RZ -- RX <- RY * RZ / RX <- RY * RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT DIV : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- DIV RX RY RZ -- RX <- RY / RZ / RX <- RY / RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT INC : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- INC RX / DEC RX -- RX <- RX + 1 / RX <- RX - 1 -- b6= INC/DEC : 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
CONSTANT LMOD : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- MOD RX RY RZ -- RX <- RY MOD RZ Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LOGIC : STD_LOGIC_VECTOR(1 downto 0) := "01";
-- LOGIC Instructions (All should begin wiht "01"):
CONSTANT LAND : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- AND RX RY RZ -- RZ <- RX AND RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LOR : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- OR RX RY RZ -- RZ <- RX OR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LXOR : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- XOR RX RY RZ -- RZ <- RX XOR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LNOT : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- NOT RX RY -- RX <- NOT(RY) Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT SHIFT : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- SHIFTL0 RX,n / SHIFTL1 RX,n / SHIFTR0 RX,n / SHIFTR1 RX,n / ROTL RX,n / ROTR RX,n
-- SHIFT/Rotate RX -- b6=shif/rotate: 0/1 b5=left/right: 0/1; b4=fill;
-- Format: < inst(6) | RX(3) | b6 b5 b4 | nnnn >
CONSTANT CMP : STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- CMP RX RY -- Compare RX and RY and set FR : Format: < inst(6) | RX(3) | RY(3) | xxxx > Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
-- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED)
-- FLOW CONTROL Instructions:
CONSTANT JMP : STD_LOGIC_VECTOR(5 downto 0) := "000010"; -- JMP END -- PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END
CONSTANT CALL : STD_LOGIC_VECTOR(5 downto 0) := "000011"; -- CALL END -- M[SP] <- PC | SP-- | PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END
CONSTANT RTS : STD_LOGIC_VECTOR(5 downto 0) := "000100"; -- RTS -- SP++ | PC <- M[SP] | b6=RX/FR: 1/0 Format: < inst(6) | xxxxxxxxxx >
CONSTANT PUSH : STD_LOGIC_VECTOR(5 downto 0) := "000101"; -- PUSH RX / PUSH FR -- M[SP] <- RX / M[SP] <- FR | SP-- : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
CONSTANT POP : STD_LOGIC_VECTOR(5 downto 0) := "000110"; -- POP RX / POP FR -- SP++ | RX <- M[SP] / FR <- M[SP] : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
-- Control Instructions:
CONSTANT NOP : STD_LOGIC_VECTOR(5 downto 0) := "000000"; -- NOP -- Do Nothing Format: < inst(6) | xxxxxxxxxx >
CONSTANT HALT : STD_LOGIC_VECTOR(5 downto 0) := "001111"; -- HALT -- StOP Here Format: < inst(6) | xxxxxxxxxx >
CONSTANT SETC : STD_LOGIC_VECTOR(5 downto 0) := "001000"; -- CLEARC / SETC -- Set/Clear CarRY: b9 = 1-set; 0-clear Format: < inst(6) | b9 | xxxxxxxxx >
CONSTANT BREAKP : STD_LOGIC_VECTOR(5 downto 0) := "001110"; -- BREAK POINT -- Switch to manual clock Format: < inst(6) | xxxxxxxxxx >
-- CONSTANTes para controle do Mux2: Estes sinais selecionam as respectivas entradas para o Mux2
CONSTANT sULA : STD_LOGIC_VECTOR (2 downto 0) := "000";
CONSTANT sMem : STD_LOGIC_VECTOR (2 downto 0) := "001";
CONSTANT sM4 : STD_LOGIC_VECTOR (2 downto 0) := "010";
CONSTANT sTECLADO : STD_LOGIC_VECTOR (2 downto 0) := "011"; -- nao tinha
CONSTANT sSP : STD_LOGIC_VECTOR (2 downto 0) := "100";
-- Sinais para o Processo da ULA
signal OP : STD_LOGIC_VECTOR(6 downto 0); -- OP(6) deve ser setado para OPeracoes com carRY
signal x, y, result : STD_LOGIC_VECTOR(15 downto 0);
signal FR : STD_LOGIC_VECTOR(15 downto 0); -- Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
signal auxFR : STD_LOGIC_VECTOR(15 downto 0); -- Representa um barramento conectando a ULA ao Mux6 para escrever no FR
begin
-- Maquina de Controle
process(clk, reset)
--Register Declaration:
variable PC : STD_LOGIC_VECTOR(15 downto 0); -- Program Counter
variable IR : STD_LOGIC_VECTOR(15 downto 0); -- Instruction Register
variable SP : STD_LOGIC_VECTOR(15 downto 0); -- Stack Pointer
variable MAR : STD_LOGIC_VECTOR(15 downto 0); -- Memory address Register
VARIABLE TECLADO :STD_LOGIC_VECTOR(15 downto 0); -- Registrador para receber dados do teclado -- nao tinha
variable reg : Registers;
-- Mux dos barramentos de dados internos
VARIABLE M2 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos barramentos de dados internos para os Registradores
VARIABLE M3, M4 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos Registradores para as entradas da ULA
-- Novos Sinais da Versao 2: Controle dos registradores internos (Load-Inc-Dec)
variable LoadReg : LoadRegisters;
variable LoadIR : std_LOGIC;
variable LoadMAR : std_LOGIC;
variable LoadPC : std_LOGIC;
variable IncPC : std_LOGIC;
VARIABLE LoadSP : STD_LOGIC;
variable IncSP : std_LOGIC;
variable DecSP : std_LOGIC;
-- Selecao dos Mux 2 e 6
variable selM2 : STD_LOGIC_VECTOR(2 downto 0);
variable selM6 : STD_LOGIC_VECTOR(2 downto 0);
VARIABLE BreakFlag : STD_LOGIC; -- Para sinalizar a mudanca para Clock manual/Clock Automatico para a nova instrucao Break
variable state : STATES; -- Estados do processador: fetch, decode, exec, halted
-- Seletores dos registradores para execussao das instrucoes
variable RX : integer;
variable RY : integer;
variable RZ : integer;
begin
if(reset = '1') then
state := fetch; -- inicializa o estado na busca!
M1(15 downto 0) <= x"0000"; -- inicializa na linha Zero da memoria -> Programa tem que comecar na linha Zero !!
videoflag <= '0';
RX := 0;
RY := 0;
RZ := 0;
RW <= '0';
LoadIR := '0';
LoadMAR := '0';
LoadPC := '0';
IncPC := '0';
IncSP := '0';
DecSP := '0';
selM2 := sMem;
selM6 := sULA;
LoadReg(0) := '0';
LoadReg(1) := '0';
LoadReg(2) := '0';
LoadReg(3) := '0';
LoadReg(4) := '0';
LoadReg(5) := '0';
LoadReg(6) := '0';
LoadReg(7) := '0';
REG(0) := x"0000";
REG(1) := x"0000";
REG(2) := x"0000";
REG(3) := x"0000";
REG(4) := x"0000";
REG(5) := x"0000";
REG(6) := x"0000";
REG(7) := x"0000";
PC := x"0000"; -- inicializa na linha Zero da memoria -> Programa tem que comecar na linha Zero !!
SP := x"3ffc"; -- Inicializa a Pilha no final da mem�ria: 7ffc
IR := x"0000";
MAR := x"0000";
BreakFlag:= '0'; -- Break Point Flag
BREAK <= '0'; -- Break Point output to switch to manual clock
-- Novo na Versao 3
HALT_ack <= '0';
elsif(clk'event and clk = '1') then
if(LoadIR = '1') then IR := Mem; end if;
if(LoadPC = '1') then PC := Mem; end if;
if(IncPC = '1') then PC := PC + x"0001"; end if;
if(LoadMAR = '1') then MAR := Mem; end if;
if(LoadSP = '1') then SP := M3; end if;
if(IncSP = '1') then SP := SP + x"0001"; end if;
if(DecSP = '1') then SP := SP - x"0001"; end if;
-- Selecao do Mux6
if (selM6 = sULA) THEN FR <= auxFR; -- Sempre recebe flags da ULA
ELSIF (selM6 = sMem) THEN FR <= Mem; END IF; -- A menos que seja POP FR, quando recebe da Memoria
-- Atualiza o nome dos registradores!!!
RX := conv_integer(IR(9 downto 7));
RY := conv_integer(IR(6 downto 4));
RZ := conv_integer(IR(3 downto 1));
-- Selecao do Mux2
if (selM2 = sULA) THEN M2 := RESULT;
ELSIF (selM2 = sMem) THEN M2 := Mem;
ELSIF (selM2 = sM4) THEN M2 := M4;
ELSIF (selM2 = sTECLADO)THEN M2 := TECLADO;
ELSIF (selM2 = sSP) THEN M2 := SP;
END IF;
-- Carrega dados do Mux 2 para os registradores
if(LoadReg(RX) = '1') then reg(RX) := M2; end if;
-- Reseta os sinais de controle APOS usa-los acima
-- Zera todos os sinais de controle, para depois ligar um por um nas instrucoes a medida que for necessario: a ultima atribuicao e' a que vale no processo!!!
LoadIR := '0';
LoadMAR := '0';
LoadPC := '0';
IncPC := '0';
IncSP := '0';
DecSP := '0';
LoadSP := '0';
selM6 := sULA; -- Sempre atualiza o FR da ULA, a nao ser que a instrucao seja POP FR
LoadReg(0) := '0';
LoadReg(1) := '0';
LoadReg(2) := '0';
LoadReg(3) := '0';
LoadReg(4) := '0';
LoadReg(5) := '0';
LoadReg(6) := '0';
LoadReg(7) := '0';
videoflag <= '0'; -- Abaixa o sinal para a "Placa de Video" : sobe a cada OUTCHAR
RW <= '0'; -- Sinal de Letura/Ecrita da mem�ria em Leitura
-- Novo na Versao 3
if(halt_req = '1') then state := halted; end if;
-- Novo na Versao 3: para escrever PC no LCD da placa
PC_data <= PC;
case state is
--************************************************************************
-- FETCH STATE
--************************************************************************
when fetch =>
PONTO <= "001";
-- Inicio das acoes do ciclo de Busca !!
M1 <= PC;
RW <= '0';
LoadIR := '1';
IncPC := '1';
STATE := decode;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- DECODE STATE
--************************************************************************
when decode =>
PONTO <= "010";
--========================================================================
-- INCHAR RX[7..0] <- KeyPressed RX[15..8] <- 0
--========================================================================
IF(IR(15 DOWNTO 10) = INCHAR) THEN -- Se nenhuma tecla for pressionada no momento da leitura, Rx <- x"00FF"
TECLADO(7 downto 0) := key(7 downto 0);
TECLADO(15 downto 8) := X"00";
selM2 := sTECLADO;
LoadReg(RX) := '1';
state := fetch;
END IF;
--========================================================================
-- OUTCHAR Video[RY] <- Char(RX)
--========================================================================
IF(IR(15 DOWNTO 10) = OUTCHAR) THEN
M3 := Reg(Rx); -- M3 <- Rx
M4 := Reg(Ry); -- M4 <- Ry
-- Este bloco troca a cor do preto pelo branco: agora a cor "0000" = Branco !
if( M3(11 downto 8) = "0000" ) then
M3(11 downto 8) := "1111";
elsif( M3(11 downto 8) = "1111" ) then
M3(11 downto 8) := "0000";
end if;
vga_char <= M3; --vga_char <= M3 : C�digo do Character vem do Rx via M3
vga_pos <= M4; -- Posicao na tela do Character vem do Ry via M4
videoflag <= '1'; -- Sobe o videoflag para gravar o charactere na mem�ria de video
state := fetch;
END IF;
--========================================================================
-- MOV RX/SP <- RY/SP
-- MOV RX RY RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 >
-- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 >
-- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 >
--========================================================================
IF(IR(15 DOWNTO 10) = MOV) THEN
state := fetch;
END IF;
--========================================================================
-- STORE DIReto M[END] <- RX
--========================================================================
IF(IR(15 DOWNTO 10) = STORE) THEN -- Busca o endereco
state := exec; -- Vai para o estado de Executa para gravar Registrador no endereco
END IF;
--========================================================================
-- STORE indexado por registrador M[RX] <- RY
--========================================================================
IF(IR(15 DOWNTO 10) = STOREINDEX) THEN
state := fetch;
END IF;
--========================================================================
-- LOAD Direto RX <- M[End]
--========================================================================
IF(IR(15 DOWNTO 10) = LOAD) THEN -- Busca o endereco
state := exec; -- Vai para o estado de Executa para buscar o dado do endereco
END IF;
--========================================================================
-- LOAD Imediato RX <- Nr
--========================================================================
IF(IR(15 DOWNTO 10) = LOADIMED) THEN
M1 <= PC; -- M1 <- PC
Rw <= '0'; -- Rw <= '0'
selM2 := sMeM; -- M2 <- MEM
LoadReg(RX) := '1'; -- LRx <- 1
IncPC := '1'; -- IncPC <- 1
state := fetch;
END IF;
--========================================================================
-- LOAD Indexado por registrador RX <- M(RY)
--========================================================================
IF(IR(15 DOWNTO 10) = LOADINDEX) THEN
state := fetch;
END IF;
--========================================================================
-- LOGIC OPERATION ('SHIFT', and 'CMP' NOT INCLUDED) RX <- RY (?) RZ
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) /= SHIFT AND IR(13 DOWNTO 10) /= CMP) THEN
state := fetch;
END IF;
--========================================================================
-- CMP RX, RY
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) = CMP) THEN
state := fetch;
END IF;
--========================================================================
-- SHIFT RX, RY RX <- SHIFT[ RY] ROTATE INCluded !
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC and (IR(13 DOWNTO 10) = SHIFT)) THEN
if(IR(6 DOWNTO 4) = "000") then -- SHIFT LEFT 0
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))sll conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 4) = "001") then -- SHIFT LEFT 1
Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))sll conv_integer(IR(3 DOWNTO 0))));
elsif(IR(6 DOWNTO 4) = "010") then -- SHIFT RIGHT 0
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))srl conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 4) = "011") then -- SHIFT RIGHT 0
Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))srl conv_integer(IR(3 DOWNTO 0))));
elsif(IR(6 DOWNTO 5) = "11") then -- ROTATE RIGHT
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))ror conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 5) = "10") then -- ROTATE LEFT
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))rol conv_integer(IR(3 DOWNTO 0)));
end if;
state := fetch;
end if;
--========================================================================
-- JMP END PC <- 16bit END : b9-b6 = COND
-- Flag Register: <...Negative|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
-- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED)
--========================================================================
IF(IR(15 DOWNTO 10) = JMP) THEN
state := fetch;
END IF;
--========================================================================
-- PUSH RX
--========================================================================
IF(IR(15 DOWNTO 10) = PUSH) THEN
state := fetch;
END IF;
--========================================================================
-- POP RX
--========================================================================
IF(IR(15 DOWNTO 10) = POP) THEN
state := exec;
END IF;
--========================================================================
-- CALL END PC <- 16bit END : b9-b6 = COND PUSH(PC)
-- Flag Register: <...Negative|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
-- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED)
--========================================================================
IF(IR(15 DOWNTO 10) = CALL) THEN
END IF;
--========================================================================
-- RTS PC <- Mem[SP]
--========================================================================
IF(IR(15 DOWNTO 10) = RTS) THEN
state := exec;
END IF;
--========================================================================
-- ARITH OPERATION ('INC' NOT INCLUDED) RX <- RY (?) RZ
--========================================================================
IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) /= INC) THEN
state := fetch;
END IF;
--========================================================================
-- INC/DEC RX <- RX (+ or -) 1
--========================================================================
IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) = INC) THEN
state := fetch;
END IF;
--========================================================================
-- NOP
--========================================================================
IF( IR(15 DOWNTO 10) = NOP) THEN
state := fetch;
end if;
--========================================================================
-- HALT
--========================================================================
IF( IR(15 DOWNTO 10) = HALT) THEN
state := halted;
END IF;
--========================================================================
-- SETC/CLEARC
--========================================================================
IF( IR(15 DOWNTO 10) = SETC) THEN
FR(4) <= IR(9); -- Bit 9 define se vai ser SET ou CLEAR
state := fetch;
end if;
--========================================================================
-- BREAKP
--========================================================================
IF( IR(15 DOWNTO 10) = BREAKP) THEN
BreakFlag := not(BreakFlag); -- Troca entre clock manual e clock autom�tico
BREAK <= BreakFlag;
state := fetch;
PONTO <= "101";
END IF;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- EXECUTE STATE
--************************************************************************
when exec =>
PONTO <= "100";
--========================================================================
-- EXEC STORE DIReto M[END] <- RX
--========================================================================
IF(IR(15 DOWNTO 10) = STORE) THEN
state := fetch;
END IF;
--========================================================================
-- EXEC LOAD DIReto RX <- M[END]
--========================================================================
IF(IR(15 DOWNTO 10) = LOAD) THEN
state := fetch;
END IF;
--========================================================================
-- EXEC POP RX/FR
--========================================================================
IF(IR(15 DOWNTO 10) = POP) THEN
state := fetch;
END IF;
--========================================================================
-- EXEC CALL Pilha <- PC e PC <- 16bit END :
--========================================================================
IF(IR(15 DOWNTO 10) = CALL) THEN
state := fetch;
END IF;
--========================================================================
-- EXEC RTS PC <- Mem[SP]
--========================================================================
IF(IR(15 DOWNTO 10) = RTS) THEN
state := fetch;
END IF;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- HALT STATE
--************************************************************************
WHEN halted =>
PONTO <= "111";
state := halted;
halt_ack <= '1';
WHEN OTHERS =>
state := fetch;
videoflag <= '0';
PONTO <= "000";
END CASE;
end if;
end process;
--************************************************************************
-- ULA ---> 3456 (3042)
--************************************************************************
PROCESS (OP, X, Y, reset)
VARIABLE AUX : STD_LOGIC_VECTOR(15 downto 0);
VARIABLE RESULT32 : STD_LOGIC_VECTOR(31 downto 0);
BEGIN
IF (reset = '1') THEN
auxFR <= x"0000";
RESULT <= x"0000";
else
auxFR <= FR;
--========================================================================
-- ARITH
--========================================================================
IF (OP (5 downto 4) = ARITH) THEN
CASE OP (3 downto 0) IS
WHEN ADD =>
IF (OP(6) = '1') THEN --Soma com carRY
AUX := X + Y + FR(4);
RESULT32 := (x"00000000" + X + Y + FR(4));
ELSE --Soma sem carRY
AUX := X + Y;
RESULT32 := (x"00000000" + X + Y);
end if;
if(RESULT32 > "01111111111111111") THEN -- CarRY
auxFR(4) <= '1';
ELSE
auxFR(4) <= '0';
end if;
WHEN SUB =>
AUX := X - Y;
WHEN MULT =>
RESULT32 := X * Y;
AUX := RESULT32(15 downto 0);
if(RESULT32 > x"0000FFFF") THEN -- ARITHmetic Overflow
auxFR(5) <= '1';
ELSE
auxFR(5) <= '0';
end if;
WHEN DIV =>
IF(Y = x"0000") THEN
AUX := x"0000";
auxFR(6) <= '1'; -- DIV by Zero
ELSE
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X)/CONV_INTEGER(Y), 16);
auxFR(6) <= '0';
END IF;
WHEN LMOD =>
IF(Y = x"0000") THEN
AUX := x"0000";
auxFR(6) <= '1'; -- DIV by Zero
ELSE
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X) mod CONV_INTEGER(Y), 16);
auxFR(6) <= '0';
END IF;
WHEN others => -- invalid operation, defaults to nothing
AUX := X;
END CASE;
if(AUX = x"0000") THEN
auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater>
ELSE
auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater>
end if;
if(AUX < x"0000") THEN -- NEGATIVO
auxFR(9) <= '1';
ELSE
auxFR(9) <= '0';
end if;
RESULT <= AUX;
ELSIF (OP (5 downto 4) = LOGIC) THEN
IF (OP (3 downto 0) = CMP) THEN
result <= x;
IF (x > y) THEN
auxFR(2 downto 0) <= "001"; -- FR = <...|zero|equal|lesser|greater>
ELSIF (x < y) THEN
auxFR(2 downto 0) <= "010"; -- FR = <...|zero|equal|lesser|greater>
ELSIF (x = y) THEN
auxFR(2 downto 0) <= "100"; -- FR = <...|zero|equal|lesser|greater>
END IF;
ELSE
CASE OP (3 downto 0) IS
WHEN LAND => result <= x and y;
WHEN LXOR => result <= x xor y;
WHEN LOR => result <= x or y;
WHEN LNOT => result <= not x;
WHEN others => -- invalid operation, defaults to nothing
RESULT <= X;
END CASE;
if(result = x"0000") THEN
auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater>
ELSE
auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater>
end if;
END IF;
END IF;
END IF; -- Reset
END PROCESS;
end main;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00225
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (6)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00225)
-- ENT00225_Test_Bench(ARCH00225_Test_Bench)
--
-- REVISION HISTORY:
--
-- 15-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES ;
use STANDARD_TYPES.test_report, STANDARD_TYPES.switch,
STANDARD_TYPES.up, STANDARD_TYPES.down, STANDARD_TYPES.toggle,
STANDARD_TYPES."=" ;
architecture ARCH00225 of GENERIC_STANDARD_TYPES is
signal i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
signal i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
signal i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal i_character_1, i_character_2 : character
:= c_character_1 ;
signal i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
signal i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
signal i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
signal i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal i_time_1, i_time_2 : time
:= c_time_1 ;
signal i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
signal i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal i_real_1, i_real_2 : real
:= c_real_1 ;
signal i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
signal i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1 ;
--
begin
L1:
block
port (
i_boolean_1, i_boolean_2 : in boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : in bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : in severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : in character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : in t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : in st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : in integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : in t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : in st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : in time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : in t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : in st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : in real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : in t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : in st_real1
:= c_st_real1_1
) ;
port map (
i_boolean_1, i_boolean_2,
i_bit_1, i_bit_2,
i_severity_level_1, i_severity_level_2,
i_character_1, i_character_2,
i_t_enum1_1, i_t_enum1_2,
i_st_enum1_1, i_st_enum1_2,
i_integer_1, i_integer_2,
i_t_int1_1, i_t_int1_2,
i_st_int1_1, i_st_int1_2,
i_time_1, i_time_2,
i_t_phys1_1, i_t_phys1_2,
i_st_phys1_1, i_st_phys1_2,
i_real_1, i_real_2,
i_t_real1_1, i_t_real1_2,
i_st_real1_1, i_st_real1_2
) ;
--
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_boolean_1 = c_boolean_1
and i_boolean_2 = c_boolean_1 ;
correct := correct and i_bit_1 = c_bit_1
and i_bit_2 = c_bit_1 ;
correct := correct and i_severity_level_1 = c_severity_level_1
and i_severity_level_2 = c_severity_level_1 ;
correct := correct and i_character_1 = c_character_1
and i_character_2 = c_character_1 ;
correct := correct and i_t_enum1_1 = c_t_enum1_1
and i_t_enum1_2 = c_t_enum1_1 ;
correct := correct and i_st_enum1_1 = c_st_enum1_1
and i_st_enum1_2 = c_st_enum1_1 ;
correct := correct and i_integer_1 = c_integer_1
and i_integer_2 = c_integer_1 ;
correct := correct and i_t_int1_1 = c_t_int1_1
and i_t_int1_2 = c_t_int1_1 ;
correct := correct and i_st_int1_1 = c_st_int1_1
and i_st_int1_2 = c_st_int1_1 ;
correct := correct and i_time_1 = c_time_1
and i_time_2 = c_time_1 ;
correct := correct and i_t_phys1_1 = c_t_phys1_1
and i_t_phys1_2 = c_t_phys1_1 ;
correct := correct and i_st_phys1_1 = c_st_phys1_1
and i_st_phys1_2 = c_st_phys1_1 ;
correct := correct and i_real_1 = c_real_1
and i_real_2 = c_real_1 ;
correct := correct and i_t_real1_1 = c_t_real1_1
and i_t_real1_2 = c_t_real1_1 ;
correct := correct and i_st_real1_1 = c_st_real1_1
and i_st_real1_2 = c_st_real1_1 ;
--
test_report ( "ENT00225" ,
"Associated scalar in ports with generic subtypes" ,
correct) ;
wait ;
end process ;
end block L1 ;
end ARCH00225 ;
--
entity ENT00225_Test_Bench is
end ENT00225_Test_Bench ;
--
architecture ARCH00225_Test_Bench of ENT00225_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00225 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00225_Test_Bench ;
|
-- A2601 Top Level Entity (ROM stored in on-chip RAM)
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
--
-- This top level entity supports a single cartridge ROM stored in FPGA built-in
-- memory (such as Xilinx Spartan BlockRAM). To generate the required cart_rom
-- entity, use bin2vhdl.py found in the util directory.
--
-- For more information, see the A2601 Rev B Board Schematics and project
-- website at <http://retromaster.wordpress.org/a2601>.
-- 9 pin d-sub joystick pinout:
-- pin 1: up
-- pin 2: down
-- pin 3: left
-- pin 4: right
-- pin 6: fire
-- Atari 2600, 6532 ports:
-- PA0: right joystick, up
-- PA1: right joystick, down
-- PA2: right joystick, left
-- PA3: right joystick, right
-- PA4: left joystick, up
-- PA5: left joystick, down
-- PA6: left joystick, left
-- PA7: left joystick, right
-- PB0: start
-- PB1: select
-- PB3: B/W, color
-- PB6: left difficulty
-- PB7: right difficulty
-- Atari 2600, TIA input:
-- I5: right joystick, fire
-- I6: left joystick, fire
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity A2601Master is
port (vid_clk: in std_logic;
pa_in: in std_logic_vector(7 downto 0);
pb_in: in std_logic_vector(7 downto 0);
inpt0_in: in std_logic;
inpt1_in: in std_logic;
inpt2_in: in std_logic;
inpt3_in: in std_logic;
inpt4_in: in std_logic;
inpt5_in: in std_logic;
d_in: in std_logic_vector(7 downto 0);
a_out: out std_logic_vector(12 downto 0);
cv: out std_logic_vector(7 downto 0);
vsyn: out std_logic;
hsyn: out std_logic;
au: out std_logic_vector(4 downto 0);
dump_pin:out std_logic;
res: in std_logic);
end A2601Master;
architecture arch of A2601Master is
component A2601 is
port(vid_clk: in std_logic;
rst: in std_logic;
d: inout std_logic_vector(7 downto 0);
a: out std_logic_vector(12 downto 0);
r: out std_logic;
pa: inout std_logic_vector(7 downto 0);
pb: inout std_logic_vector(7 downto 0);
paddle_0: in std_logic_vector(7 downto 0);
paddle_1: in std_logic_vector(7 downto 0);
paddle_2: in std_logic_vector(7 downto 0);
paddle_3: in std_logic_vector(7 downto 0);
paddle_ena: in std_logic;
inpt4: in std_logic;
inpt5: in std_logic;
colu: out std_logic_vector(6 downto 0);
csyn: out std_logic;
vsyn: out std_logic;
hsyn: out std_logic;
rgbx2: out std_logic_vector(23 downto 0);
cv: out std_logic_vector(7 downto 0);
au0: out std_logic;
au1: out std_logic;
av0: out std_logic_vector(3 downto 0);
av1: out std_logic_vector(3 downto 0);
ph0_out: out std_logic;
ph1_out: out std_logic;
pal: in std_logic);
end component;
component debounce is
GENERIC(
NDELAY : INTEGER := 10000;
NBITS : INTEGER := 20
);
Port (
reset : in std_logic;
clk : in std_logic;
noisy : in std_logic;
clean : out std_logic
);
end component;
signal clk : std_logic;
signal noisy : std_logic;
signal clean : std_logic;
signal dbounce_pb: std_logic_vector(1 downto 0) := "00";
--signal vid_clk: std_logic;
signal cpu_d: std_logic_vector(7 downto 0);
--signal d: std_logic_vector(7 downto 0);
signal cpu_a: std_logic_vector(12 downto 0);
--signal a: std_logic_vector(12 downto 0);
signal cpu_r: std_logic;
signal pa: std_logic_vector(7 downto 0);
signal pb: std_logic_vector(7 downto 0);
signal paddle_0: std_logic_vector(7 downto 0);
signal paddle_1: std_logic_vector(7 downto 0);
signal paddle_2: std_logic_vector(7 downto 0);
signal paddle_3: std_logic_vector(7 downto 0);
signal inpt4: std_logic;
signal inpt5: std_logic;
signal colu: std_logic_vector(6 downto 0);
signal csyn: std_logic;
signal au0: std_logic;
signal au1: std_logic;
signal av0: std_logic_vector(3 downto 0);
signal av1: std_logic_vector(3 downto 0);
signal auv0: unsigned(4 downto 0);
signal auv1: unsigned(4 downto 0);
-- signal rst: std_logic;
signal rst: std_logic := '1';
signal sys_clk_dvdr: unsigned(4 downto 0) := "00000";
signal ph0: std_logic;
signal ph1: std_logic;
signal pal: std_logic := '0'; -- NTSC
begin
-- ms_A2601: A2601
-- port map(vid_clk, rst, cpu_d, cpu_a, cpu_r,pa, pb,paddle_0, paddle_1, paddle_2, paddle_3, paddle_ena,inpt4, inpt5, open, open, vsyn, hsyn, rgbx2, cv,au0, au1, av0, av1, ph0, ph1, pal);
ms_A2601: A2601
port map(vid_clk, rst, cpu_d, cpu_a, cpu_r,pa, pb,paddle_0, paddle_1, paddle_2, paddle_3, '0' ,inpt4, inpt5, open, open, vsyn, hsyn, open, cv,au0, au1, av0, av1, ph0, ph1, pal);
a_out <= cpu_a;
process(cpu_a,d_in)
begin
if (cpu_a(12) = '1') then
cpu_d <= d_in;
else
cpu_d <= "ZZZZZZZZ";
end if;
end process;
--dump_pin <= ph0;
-- inpt0 <= inpt0_in;
-- inpt1 <= inpt1_in;
-- inpt2 <= inpt2_in;
-- inpt3 <= inpt3_in;
inpt4 <= inpt4_in;
--inpt5 <= inpt5_in;
inpt5 <= '1';
-- Atari 2600, 6532 ports:
-- PA0: right joystick, up
-- PA1: right joystick, down
-- PA2: right joystick, left
-- PA3: right joystick, right
-- PA4: left joystick, up
-- PA5: left joystick, down
-- PA6: left joystick, left
-- PA7: left joystick, right
-- PB0: start
-- PB1: select
-- PB3: B/W, color
-- PB6: left difficulty
-- PB7: right difficulty
pa(7 downto 4) <= pa_in(7 downto 4); -- left joystick
pa(3 downto 0) <= "1111"; -- right joystick
pb(7 downto 6) <= pb_in(7 downto 6); -- PB6: left difficulty ; PB7: right difficulty
pb(5 downto 4) <= "00";
pb(3) <= pb_in(3); -- B/W
pb(2) <= '0';
-- pb(1) <= pb_in(1); -- select
-- pb(0) <= pb_in(0); -- start
ms_dbounce0: debounce port map( res,vid_clk ,pb_in(0),pb(0));
ms_dbounce1: debounce port map( res,vid_clk ,pb_in(1),pb(1));
auv0 <= ("0" & unsigned(av0)) when (au0 = '1') else "00000";
auv1 <= ("0" & unsigned(av1)) when (au1 = '1') else "00000";
au <= std_logic_vector(auv0 + auv1);
process(vid_clk, sys_clk_dvdr)
begin
if (vid_clk'event and vid_clk = '1') then
sys_clk_dvdr <= sys_clk_dvdr + 1;
if (sys_clk_dvdr = "11101") then
rst <= '0';
end if;
end if;
end process;
-- process(vid_clk, sys_clk_dvdr,res)
-- begin
-- if (vid_clk'event and vid_clk = '1' ) then
--
-- if (res = '1') then
-- rst <= '1';
-- else
-- sys_clk_dvdr <= sys_clk_dvdr + 1;
-- end if;
--
-- if (sys_clk_dvdr = "100") then
-- rst <= '0';
-- sys_clk_dvdr <= "000";
-- end if;
--
-- end if;
--
--
-- end process;
end arch;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
entity opb_SynchManager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"00FFFFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_SynchManager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture imp of opb_SynchManager is
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - 2 to
C_OPB_AWIDTH - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_01, -- user logic address range 0 bank
1 => USER_02, -- user logic address range 1 bank
2 => USER_03, -- user logic address range 2 bank
3 => USER_04, -- user logic address range 3 bank
4 => USER_05, -- user logic address range 4 bank
5 => USER_06, -- user logic address range 5 bank
6 => USER_07 -- user logic address range 6 bank
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify data width for each target address range.
constant USER_AR0_DWIDTH : integer := 32;
constant USER_AR1_DWIDTH : integer := 32;
constant USER_AR2_DWIDTH : integer := 32;
constant USER_AR3_DWIDTH : integer := 32;
constant USER_AR4_DWIDTH : integer := 32;
constant USER_AR5_DWIDTH : integer := 32;
constant USER_AR6_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_AR0_DWIDTH, -- user logic address range 0 data width
1 => USER_AR1_DWIDTH, -- user logic address range 1 data width
2 => USER_AR2_DWIDTH, -- user logic address range 2 data width
3 => USER_AR3_DWIDTH, -- user logic address range 3 data width
4 => USER_AR4_DWIDTH, -- user logic address range 4 data width
5 => USER_AR5_DWIDTH, -- user logic address range 5 data width
6 => USER_AR6_DWIDTH -- user logic address range 6 data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0=>(others => 0), -- user logic address range 0 dependent properties (none defined)
1=>(others => 0), -- user logic address range 1 dependent properties (none defined)
2=>(others => 0), -- user logic address range 2 dependent properties (none defined)
3=>(others => 0), -- user logic address range 3 dependent properties (none defined)
4=>(others => 0), -- user logic address range 4 dependent properties (none defined)
5=>(others => 0), -- user logic address range 5 dependent properties (none defined)
6=>(others => 0) -- user logic address range 6 dependent properties (none defined)
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the opb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- opb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 0;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 64.
constant DEV_MAX_BURST_SIZE : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a opb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of opb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify arbitration scheme if both dma and user-logic masters are present,
-- following schemes are supported:
-- 0 - FAIR
-- 1 - DMA_PRIORITY
-- 2 - IP_PRIORITY
constant MASTER_ARB_MODEL : integer := 0;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify the size (must be power of 2) of burst that dma uses to
-- tranfer data on the bus, a value of one causes dma to use single
-- transactions (burst disabled).
constant DMA_BURST_SIZE : integer := 16;
-- specify whether to transfer the dma remanining data as a series of
-- single transactions or as a short burst.
constant DMA_SHORT_BURST_REMAINDER : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma (usually left at
-- default value), apply to software design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000000;
-- specify period of the opb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant OPB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the opb data bus width.
constant IPIF_DWIDTH : integer := C_OPB_DWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_OPB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iIP2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal iBus2IP_RNW : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Data : std_logic_vector(0 to IPIF_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iIP2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to 31) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_MstBE : std_logic_vector(0 to (C_OPB_DWIDTH/8) - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal iBus2IP_BE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1);
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_ADDR_RNG-1);
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
opb_ipif_i : entity opb_ipif_v2_00_h.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_MASTER_ARB_MODEL => MASTER_ARB_MODEL,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => DMA_SHORT_BURST_REMAINDER,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_CLK_PERIOD_PS => OPB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
Sln_DBus => Sl_DBus,
Mn_ABus => M_ABus,
IP2Bus_Addr => iIP2Bus_Addr,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_CS => iBus2IP_CS,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '1',
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2IP_Addr => iIP2IP_Addr,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_IPMstTrans => open,
Bus2IP_Burst => open,
Mn_request => M_request,
Mn_busLock => M_busLock,
Mn_select => M_select,
Mn_RNW => M_RNW,
Mn_BE => M_BE,
Mn_seqAddr => M_seqAddr,
OPB_MnGrant => OPB_MGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
Freeze => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_toutSup => Sl_toutSup,
Sln_retry => Sl_retry,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_DMA_Ack => open,
Bus2IP_Freeze => open,
Bus2IP_Reset => iBus2IP_Reset,
IP2Bus_Clk => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
OPB_Clk => OPB_Clk,
Reset => OPB_Rst
);
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_CS => uBus2IP_CS,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_RdCE(0 to USER_NUM_CE-1) <= iBus2IP_RdCE(0 to USER_NUM_CE-1);
uBus2IP_WrCE(0 to USER_NUM_CE-1) <= iBus2IP_WrCE(0 to USER_NUM_CE-1);
uBus2IP_CS <= iBus2IP_CS;
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end imp;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
entity opb_SynchManager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"00FFFFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_SynchManager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture imp of opb_SynchManager is
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - 2 to
C_OPB_AWIDTH - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_01, -- user logic address range 0 bank
1 => USER_02, -- user logic address range 1 bank
2 => USER_03, -- user logic address range 2 bank
3 => USER_04, -- user logic address range 3 bank
4 => USER_05, -- user logic address range 4 bank
5 => USER_06, -- user logic address range 5 bank
6 => USER_07 -- user logic address range 6 bank
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify data width for each target address range.
constant USER_AR0_DWIDTH : integer := 32;
constant USER_AR1_DWIDTH : integer := 32;
constant USER_AR2_DWIDTH : integer := 32;
constant USER_AR3_DWIDTH : integer := 32;
constant USER_AR4_DWIDTH : integer := 32;
constant USER_AR5_DWIDTH : integer := 32;
constant USER_AR6_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_AR0_DWIDTH, -- user logic address range 0 data width
1 => USER_AR1_DWIDTH, -- user logic address range 1 data width
2 => USER_AR2_DWIDTH, -- user logic address range 2 data width
3 => USER_AR3_DWIDTH, -- user logic address range 3 data width
4 => USER_AR4_DWIDTH, -- user logic address range 4 data width
5 => USER_AR5_DWIDTH, -- user logic address range 5 data width
6 => USER_AR6_DWIDTH -- user logic address range 6 data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0=>(others => 0), -- user logic address range 0 dependent properties (none defined)
1=>(others => 0), -- user logic address range 1 dependent properties (none defined)
2=>(others => 0), -- user logic address range 2 dependent properties (none defined)
3=>(others => 0), -- user logic address range 3 dependent properties (none defined)
4=>(others => 0), -- user logic address range 4 dependent properties (none defined)
5=>(others => 0), -- user logic address range 5 dependent properties (none defined)
6=>(others => 0) -- user logic address range 6 dependent properties (none defined)
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the opb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- opb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 0;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 64.
constant DEV_MAX_BURST_SIZE : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a opb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of opb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify arbitration scheme if both dma and user-logic masters are present,
-- following schemes are supported:
-- 0 - FAIR
-- 1 - DMA_PRIORITY
-- 2 - IP_PRIORITY
constant MASTER_ARB_MODEL : integer := 0;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify the size (must be power of 2) of burst that dma uses to
-- tranfer data on the bus, a value of one causes dma to use single
-- transactions (burst disabled).
constant DMA_BURST_SIZE : integer := 16;
-- specify whether to transfer the dma remanining data as a series of
-- single transactions or as a short burst.
constant DMA_SHORT_BURST_REMAINDER : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma (usually left at
-- default value), apply to software design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000000;
-- specify period of the opb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant OPB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the opb data bus width.
constant IPIF_DWIDTH : integer := C_OPB_DWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_OPB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iIP2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal iBus2IP_RNW : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Data : std_logic_vector(0 to IPIF_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iIP2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to 31) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_MstBE : std_logic_vector(0 to (C_OPB_DWIDTH/8) - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal iBus2IP_BE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1);
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_ADDR_RNG-1);
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
opb_ipif_i : entity opb_ipif_v2_00_h.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_MASTER_ARB_MODEL => MASTER_ARB_MODEL,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => DMA_SHORT_BURST_REMAINDER,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_CLK_PERIOD_PS => OPB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
Sln_DBus => Sl_DBus,
Mn_ABus => M_ABus,
IP2Bus_Addr => iIP2Bus_Addr,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_CS => iBus2IP_CS,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '1',
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2IP_Addr => iIP2IP_Addr,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_IPMstTrans => open,
Bus2IP_Burst => open,
Mn_request => M_request,
Mn_busLock => M_busLock,
Mn_select => M_select,
Mn_RNW => M_RNW,
Mn_BE => M_BE,
Mn_seqAddr => M_seqAddr,
OPB_MnGrant => OPB_MGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
Freeze => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_toutSup => Sl_toutSup,
Sln_retry => Sl_retry,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_DMA_Ack => open,
Bus2IP_Freeze => open,
Bus2IP_Reset => iBus2IP_Reset,
IP2Bus_Clk => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
OPB_Clk => OPB_Clk,
Reset => OPB_Rst
);
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_CS => uBus2IP_CS,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_RdCE(0 to USER_NUM_CE-1) <= iBus2IP_RdCE(0 to USER_NUM_CE-1);
uBus2IP_WrCE(0 to USER_NUM_CE-1) <= iBus2IP_WrCE(0 to USER_NUM_CE-1);
uBus2IP_CS <= iBus2IP_CS;
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end imp;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
entity opb_SynchManager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"00FFFFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_SynchManager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture imp of opb_SynchManager is
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - 2 to
C_OPB_AWIDTH - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_01, -- user logic address range 0 bank
1 => USER_02, -- user logic address range 1 bank
2 => USER_03, -- user logic address range 2 bank
3 => USER_04, -- user logic address range 3 bank
4 => USER_05, -- user logic address range 4 bank
5 => USER_06, -- user logic address range 5 bank
6 => USER_07 -- user logic address range 6 bank
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify data width for each target address range.
constant USER_AR0_DWIDTH : integer := 32;
constant USER_AR1_DWIDTH : integer := 32;
constant USER_AR2_DWIDTH : integer := 32;
constant USER_AR3_DWIDTH : integer := 32;
constant USER_AR4_DWIDTH : integer := 32;
constant USER_AR5_DWIDTH : integer := 32;
constant USER_AR6_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_AR0_DWIDTH, -- user logic address range 0 data width
1 => USER_AR1_DWIDTH, -- user logic address range 1 data width
2 => USER_AR2_DWIDTH, -- user logic address range 2 data width
3 => USER_AR3_DWIDTH, -- user logic address range 3 data width
4 => USER_AR4_DWIDTH, -- user logic address range 4 data width
5 => USER_AR5_DWIDTH, -- user logic address range 5 data width
6 => USER_AR6_DWIDTH -- user logic address range 6 data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0=>(others => 0), -- user logic address range 0 dependent properties (none defined)
1=>(others => 0), -- user logic address range 1 dependent properties (none defined)
2=>(others => 0), -- user logic address range 2 dependent properties (none defined)
3=>(others => 0), -- user logic address range 3 dependent properties (none defined)
4=>(others => 0), -- user logic address range 4 dependent properties (none defined)
5=>(others => 0), -- user logic address range 5 dependent properties (none defined)
6=>(others => 0) -- user logic address range 6 dependent properties (none defined)
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the opb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- opb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 0;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 64.
constant DEV_MAX_BURST_SIZE : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a opb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of opb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify arbitration scheme if both dma and user-logic masters are present,
-- following schemes are supported:
-- 0 - FAIR
-- 1 - DMA_PRIORITY
-- 2 - IP_PRIORITY
constant MASTER_ARB_MODEL : integer := 0;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify the size (must be power of 2) of burst that dma uses to
-- tranfer data on the bus, a value of one causes dma to use single
-- transactions (burst disabled).
constant DMA_BURST_SIZE : integer := 16;
-- specify whether to transfer the dma remanining data as a series of
-- single transactions or as a short burst.
constant DMA_SHORT_BURST_REMAINDER : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma (usually left at
-- default value), apply to software design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000000;
-- specify period of the opb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant OPB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the opb data bus width.
constant IPIF_DWIDTH : integer := C_OPB_DWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_OPB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iIP2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal iBus2IP_RNW : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Data : std_logic_vector(0 to IPIF_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iIP2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to 31) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_MstBE : std_logic_vector(0 to (C_OPB_DWIDTH/8) - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal iBus2IP_BE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1);
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_ADDR_RNG-1);
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
opb_ipif_i : entity opb_ipif_v2_00_h.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_MASTER_ARB_MODEL => MASTER_ARB_MODEL,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => DMA_SHORT_BURST_REMAINDER,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_CLK_PERIOD_PS => OPB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
Sln_DBus => Sl_DBus,
Mn_ABus => M_ABus,
IP2Bus_Addr => iIP2Bus_Addr,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_CS => iBus2IP_CS,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '1',
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2IP_Addr => iIP2IP_Addr,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_IPMstTrans => open,
Bus2IP_Burst => open,
Mn_request => M_request,
Mn_busLock => M_busLock,
Mn_select => M_select,
Mn_RNW => M_RNW,
Mn_BE => M_BE,
Mn_seqAddr => M_seqAddr,
OPB_MnGrant => OPB_MGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
Freeze => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_toutSup => Sl_toutSup,
Sln_retry => Sl_retry,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_DMA_Ack => open,
Bus2IP_Freeze => open,
Bus2IP_Reset => iBus2IP_Reset,
IP2Bus_Clk => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
OPB_Clk => OPB_Clk,
Reset => OPB_Rst
);
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_CS => uBus2IP_CS,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_RdCE(0 to USER_NUM_CE-1) <= iBus2IP_RdCE(0 to USER_NUM_CE-1);
uBus2IP_WrCE(0 to USER_NUM_CE-1) <= iBus2IP_WrCE(0 to USER_NUM_CE-1);
uBus2IP_CS <= iBus2IP_CS;
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end imp;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
entity opb_SynchManager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"00FFFFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_SynchManager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture imp of opb_SynchManager is
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - 2 to
C_OPB_AWIDTH - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_01, -- user logic address range 0 bank
1 => USER_02, -- user logic address range 1 bank
2 => USER_03, -- user logic address range 2 bank
3 => USER_04, -- user logic address range 3 bank
4 => USER_05, -- user logic address range 4 bank
5 => USER_06, -- user logic address range 5 bank
6 => USER_07 -- user logic address range 6 bank
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify data width for each target address range.
constant USER_AR0_DWIDTH : integer := 32;
constant USER_AR1_DWIDTH : integer := 32;
constant USER_AR2_DWIDTH : integer := 32;
constant USER_AR3_DWIDTH : integer := 32;
constant USER_AR4_DWIDTH : integer := 32;
constant USER_AR5_DWIDTH : integer := 32;
constant USER_AR6_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_AR0_DWIDTH, -- user logic address range 0 data width
1 => USER_AR1_DWIDTH, -- user logic address range 1 data width
2 => USER_AR2_DWIDTH, -- user logic address range 2 data width
3 => USER_AR3_DWIDTH, -- user logic address range 3 data width
4 => USER_AR4_DWIDTH, -- user logic address range 4 data width
5 => USER_AR5_DWIDTH, -- user logic address range 5 data width
6 => USER_AR6_DWIDTH -- user logic address range 6 data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0=>(others => 0), -- user logic address range 0 dependent properties (none defined)
1=>(others => 0), -- user logic address range 1 dependent properties (none defined)
2=>(others => 0), -- user logic address range 2 dependent properties (none defined)
3=>(others => 0), -- user logic address range 3 dependent properties (none defined)
4=>(others => 0), -- user logic address range 4 dependent properties (none defined)
5=>(others => 0), -- user logic address range 5 dependent properties (none defined)
6=>(others => 0) -- user logic address range 6 dependent properties (none defined)
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the opb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- opb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 0;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 64.
constant DEV_MAX_BURST_SIZE : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a opb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of opb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify arbitration scheme if both dma and user-logic masters are present,
-- following schemes are supported:
-- 0 - FAIR
-- 1 - DMA_PRIORITY
-- 2 - IP_PRIORITY
constant MASTER_ARB_MODEL : integer := 0;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify the size (must be power of 2) of burst that dma uses to
-- tranfer data on the bus, a value of one causes dma to use single
-- transactions (burst disabled).
constant DMA_BURST_SIZE : integer := 16;
-- specify whether to transfer the dma remanining data as a series of
-- single transactions or as a short burst.
constant DMA_SHORT_BURST_REMAINDER : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma (usually left at
-- default value), apply to software design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000000;
-- specify period of the opb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant OPB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the opb data bus width.
constant IPIF_DWIDTH : integer := C_OPB_DWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_OPB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iIP2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal iBus2IP_RNW : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Data : std_logic_vector(0 to IPIF_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iIP2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to 31) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_MstBE : std_logic_vector(0 to (C_OPB_DWIDTH/8) - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal iBus2IP_BE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1);
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_ADDR_RNG-1);
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
opb_ipif_i : entity opb_ipif_v2_00_h.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_MASTER_ARB_MODEL => MASTER_ARB_MODEL,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => DMA_SHORT_BURST_REMAINDER,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_CLK_PERIOD_PS => OPB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
Sln_DBus => Sl_DBus,
Mn_ABus => M_ABus,
IP2Bus_Addr => iIP2Bus_Addr,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_CS => iBus2IP_CS,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '1',
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2IP_Addr => iIP2IP_Addr,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_IPMstTrans => open,
Bus2IP_Burst => open,
Mn_request => M_request,
Mn_busLock => M_busLock,
Mn_select => M_select,
Mn_RNW => M_RNW,
Mn_BE => M_BE,
Mn_seqAddr => M_seqAddr,
OPB_MnGrant => OPB_MGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
Freeze => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_toutSup => Sl_toutSup,
Sln_retry => Sl_retry,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_DMA_Ack => open,
Bus2IP_Freeze => open,
Bus2IP_Reset => iBus2IP_Reset,
IP2Bus_Clk => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
OPB_Clk => OPB_Clk,
Reset => OPB_Rst
);
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_CS => uBus2IP_CS,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_RdCE(0 to USER_NUM_CE-1) <= iBus2IP_RdCE(0 to USER_NUM_CE-1);
uBus2IP_WrCE(0 to USER_NUM_CE-1) <= iBus2IP_WrCE(0 to USER_NUM_CE-1);
uBus2IP_CS <= iBus2IP_CS;
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end imp;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
entity opb_SynchManager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"00FFFFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_SynchManager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture imp of opb_SynchManager is
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - 2 to
C_OPB_AWIDTH - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_01, -- user logic address range 0 bank
1 => USER_02, -- user logic address range 1 bank
2 => USER_03, -- user logic address range 2 bank
3 => USER_04, -- user logic address range 3 bank
4 => USER_05, -- user logic address range 4 bank
5 => USER_06, -- user logic address range 5 bank
6 => USER_07 -- user logic address range 6 bank
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify data width for each target address range.
constant USER_AR0_DWIDTH : integer := 32;
constant USER_AR1_DWIDTH : integer := 32;
constant USER_AR2_DWIDTH : integer := 32;
constant USER_AR3_DWIDTH : integer := 32;
constant USER_AR4_DWIDTH : integer := 32;
constant USER_AR5_DWIDTH : integer := 32;
constant USER_AR6_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_AR0_DWIDTH, -- user logic address range 0 data width
1 => USER_AR1_DWIDTH, -- user logic address range 1 data width
2 => USER_AR2_DWIDTH, -- user logic address range 2 data width
3 => USER_AR3_DWIDTH, -- user logic address range 3 data width
4 => USER_AR4_DWIDTH, -- user logic address range 4 data width
5 => USER_AR5_DWIDTH, -- user logic address range 5 data width
6 => USER_AR6_DWIDTH -- user logic address range 6 data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0=>(others => 0), -- user logic address range 0 dependent properties (none defined)
1=>(others => 0), -- user logic address range 1 dependent properties (none defined)
2=>(others => 0), -- user logic address range 2 dependent properties (none defined)
3=>(others => 0), -- user logic address range 3 dependent properties (none defined)
4=>(others => 0), -- user logic address range 4 dependent properties (none defined)
5=>(others => 0), -- user logic address range 5 dependent properties (none defined)
6=>(others => 0) -- user logic address range 6 dependent properties (none defined)
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the opb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- opb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 0;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 64.
constant DEV_MAX_BURST_SIZE : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a opb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of opb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify arbitration scheme if both dma and user-logic masters are present,
-- following schemes are supported:
-- 0 - FAIR
-- 1 - DMA_PRIORITY
-- 2 - IP_PRIORITY
constant MASTER_ARB_MODEL : integer := 0;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify the size (must be power of 2) of burst that dma uses to
-- tranfer data on the bus, a value of one causes dma to use single
-- transactions (burst disabled).
constant DMA_BURST_SIZE : integer := 16;
-- specify whether to transfer the dma remanining data as a series of
-- single transactions or as a short burst.
constant DMA_SHORT_BURST_REMAINDER : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma (usually left at
-- default value), apply to software design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000000;
-- specify period of the opb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant OPB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the opb data bus width.
constant IPIF_DWIDTH : integer := C_OPB_DWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_OPB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iIP2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal iBus2IP_RNW : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Data : std_logic_vector(0 to IPIF_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iIP2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to 31) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_MstBE : std_logic_vector(0 to (C_OPB_DWIDTH/8) - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal iBus2IP_BE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1);
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_ADDR_RNG-1);
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
opb_ipif_i : entity opb_ipif_v2_00_h.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_MASTER_ARB_MODEL => MASTER_ARB_MODEL,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => DMA_SHORT_BURST_REMAINDER,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_CLK_PERIOD_PS => OPB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
Sln_DBus => Sl_DBus,
Mn_ABus => M_ABus,
IP2Bus_Addr => iIP2Bus_Addr,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_CS => iBus2IP_CS,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '1',
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2IP_Addr => iIP2IP_Addr,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_IPMstTrans => open,
Bus2IP_Burst => open,
Mn_request => M_request,
Mn_busLock => M_busLock,
Mn_select => M_select,
Mn_RNW => M_RNW,
Mn_BE => M_BE,
Mn_seqAddr => M_seqAddr,
OPB_MnGrant => OPB_MGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
Freeze => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_toutSup => Sl_toutSup,
Sln_retry => Sl_retry,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_DMA_Ack => open,
Bus2IP_Freeze => open,
Bus2IP_Reset => iBus2IP_Reset,
IP2Bus_Clk => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
OPB_Clk => OPB_Clk,
Reset => OPB_Rst
);
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_CS => uBus2IP_CS,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_RdCE(0 to USER_NUM_CE-1) <= iBus2IP_RdCE(0 to USER_NUM_CE-1);
uBus2IP_WrCE(0 to USER_NUM_CE-1) <= iBus2IP_WrCE(0 to USER_NUM_CE-1);
uBus2IP_CS <= iBus2IP_CS;
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end imp;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
entity opb_SynchManager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"00FFFFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_SynchManager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture imp of opb_SynchManager is
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - 2 to
C_OPB_AWIDTH - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_01, -- user logic address range 0 bank
1 => USER_02, -- user logic address range 1 bank
2 => USER_03, -- user logic address range 2 bank
3 => USER_04, -- user logic address range 3 bank
4 => USER_05, -- user logic address range 4 bank
5 => USER_06, -- user logic address range 5 bank
6 => USER_07 -- user logic address range 6 bank
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify data width for each target address range.
constant USER_AR0_DWIDTH : integer := 32;
constant USER_AR1_DWIDTH : integer := 32;
constant USER_AR2_DWIDTH : integer := 32;
constant USER_AR3_DWIDTH : integer := 32;
constant USER_AR4_DWIDTH : integer := 32;
constant USER_AR5_DWIDTH : integer := 32;
constant USER_AR6_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_AR0_DWIDTH, -- user logic address range 0 data width
1 => USER_AR1_DWIDTH, -- user logic address range 1 data width
2 => USER_AR2_DWIDTH, -- user logic address range 2 data width
3 => USER_AR3_DWIDTH, -- user logic address range 3 data width
4 => USER_AR4_DWIDTH, -- user logic address range 4 data width
5 => USER_AR5_DWIDTH, -- user logic address range 5 data width
6 => USER_AR6_DWIDTH -- user logic address range 6 data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0=>(others => 0), -- user logic address range 0 dependent properties (none defined)
1=>(others => 0), -- user logic address range 1 dependent properties (none defined)
2=>(others => 0), -- user logic address range 2 dependent properties (none defined)
3=>(others => 0), -- user logic address range 3 dependent properties (none defined)
4=>(others => 0), -- user logic address range 4 dependent properties (none defined)
5=>(others => 0), -- user logic address range 5 dependent properties (none defined)
6=>(others => 0) -- user logic address range 6 dependent properties (none defined)
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the opb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- opb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 0;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 64.
constant DEV_MAX_BURST_SIZE : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a opb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of opb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify arbitration scheme if both dma and user-logic masters are present,
-- following schemes are supported:
-- 0 - FAIR
-- 1 - DMA_PRIORITY
-- 2 - IP_PRIORITY
constant MASTER_ARB_MODEL : integer := 0;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify the size (must be power of 2) of burst that dma uses to
-- tranfer data on the bus, a value of one causes dma to use single
-- transactions (burst disabled).
constant DMA_BURST_SIZE : integer := 16;
-- specify whether to transfer the dma remanining data as a series of
-- single transactions or as a short burst.
constant DMA_SHORT_BURST_REMAINDER : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma (usually left at
-- default value), apply to software design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000000;
-- specify period of the opb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant OPB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the opb data bus width.
constant IPIF_DWIDTH : integer := C_OPB_DWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_OPB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iIP2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal iBus2IP_RNW : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Data : std_logic_vector(0 to IPIF_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iIP2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to 31) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_MstBE : std_logic_vector(0 to (C_OPB_DWIDTH/8) - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal iBus2IP_BE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1);
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_ADDR_RNG-1);
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
opb_ipif_i : entity opb_ipif_v2_00_h.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_MASTER_ARB_MODEL => MASTER_ARB_MODEL,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => DMA_SHORT_BURST_REMAINDER,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_CLK_PERIOD_PS => OPB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
Sln_DBus => Sl_DBus,
Mn_ABus => M_ABus,
IP2Bus_Addr => iIP2Bus_Addr,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_CS => iBus2IP_CS,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '1',
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2IP_Addr => iIP2IP_Addr,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_IPMstTrans => open,
Bus2IP_Burst => open,
Mn_request => M_request,
Mn_busLock => M_busLock,
Mn_select => M_select,
Mn_RNW => M_RNW,
Mn_BE => M_BE,
Mn_seqAddr => M_seqAddr,
OPB_MnGrant => OPB_MGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
Freeze => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_toutSup => Sl_toutSup,
Sln_retry => Sl_retry,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_DMA_Ack => open,
Bus2IP_Freeze => open,
Bus2IP_Reset => iBus2IP_Reset,
IP2Bus_Clk => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
OPB_Clk => OPB_Clk,
Reset => OPB_Rst
);
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_CS => uBus2IP_CS,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_RdCE(0 to USER_NUM_CE-1) <= iBus2IP_RdCE(0 to USER_NUM_CE-1);
uBus2IP_WrCE(0 to USER_NUM_CE-1) <= iBus2IP_WrCE(0 to USER_NUM_CE-1);
uBus2IP_CS <= iBus2IP_CS;
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end imp;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
entity opb_SynchManager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"00FFFFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_SynchManager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture imp of opb_SynchManager is
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - 2 to
C_OPB_AWIDTH - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_01, -- user logic address range 0 bank
1 => USER_02, -- user logic address range 1 bank
2 => USER_03, -- user logic address range 2 bank
3 => USER_04, -- user logic address range 3 bank
4 => USER_05, -- user logic address range 4 bank
5 => USER_06, -- user logic address range 5 bank
6 => USER_07 -- user logic address range 6 bank
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify data width for each target address range.
constant USER_AR0_DWIDTH : integer := 32;
constant USER_AR1_DWIDTH : integer := 32;
constant USER_AR2_DWIDTH : integer := 32;
constant USER_AR3_DWIDTH : integer := 32;
constant USER_AR4_DWIDTH : integer := 32;
constant USER_AR5_DWIDTH : integer := 32;
constant USER_AR6_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_AR0_DWIDTH, -- user logic address range 0 data width
1 => USER_AR1_DWIDTH, -- user logic address range 1 data width
2 => USER_AR2_DWIDTH, -- user logic address range 2 data width
3 => USER_AR3_DWIDTH, -- user logic address range 3 data width
4 => USER_AR4_DWIDTH, -- user logic address range 4 data width
5 => USER_AR5_DWIDTH, -- user logic address range 5 data width
6 => USER_AR6_DWIDTH -- user logic address range 6 data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0=>(others => 0), -- user logic address range 0 dependent properties (none defined)
1=>(others => 0), -- user logic address range 1 dependent properties (none defined)
2=>(others => 0), -- user logic address range 2 dependent properties (none defined)
3=>(others => 0), -- user logic address range 3 dependent properties (none defined)
4=>(others => 0), -- user logic address range 4 dependent properties (none defined)
5=>(others => 0), -- user logic address range 5 dependent properties (none defined)
6=>(others => 0) -- user logic address range 6 dependent properties (none defined)
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the opb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- opb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 0;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 64.
constant DEV_MAX_BURST_SIZE : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a opb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of opb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify arbitration scheme if both dma and user-logic masters are present,
-- following schemes are supported:
-- 0 - FAIR
-- 1 - DMA_PRIORITY
-- 2 - IP_PRIORITY
constant MASTER_ARB_MODEL : integer := 0;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify the size (must be power of 2) of burst that dma uses to
-- tranfer data on the bus, a value of one causes dma to use single
-- transactions (burst disabled).
constant DMA_BURST_SIZE : integer := 16;
-- specify whether to transfer the dma remanining data as a series of
-- single transactions or as a short burst.
constant DMA_SHORT_BURST_REMAINDER : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma (usually left at
-- default value), apply to software design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000000;
-- specify period of the opb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant OPB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the opb data bus width.
constant IPIF_DWIDTH : integer := C_OPB_DWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_OPB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iIP2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal iBus2IP_RNW : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Data : std_logic_vector(0 to IPIF_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iIP2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to 31) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_MstBE : std_logic_vector(0 to (C_OPB_DWIDTH/8) - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal iBus2IP_BE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1);
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_ADDR_RNG-1);
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
opb_ipif_i : entity opb_ipif_v2_00_h.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_MASTER_ARB_MODEL => MASTER_ARB_MODEL,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => DMA_SHORT_BURST_REMAINDER,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_CLK_PERIOD_PS => OPB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
Sln_DBus => Sl_DBus,
Mn_ABus => M_ABus,
IP2Bus_Addr => iIP2Bus_Addr,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_CS => iBus2IP_CS,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '1',
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2IP_Addr => iIP2IP_Addr,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_IPMstTrans => open,
Bus2IP_Burst => open,
Mn_request => M_request,
Mn_busLock => M_busLock,
Mn_select => M_select,
Mn_RNW => M_RNW,
Mn_BE => M_BE,
Mn_seqAddr => M_seqAddr,
OPB_MnGrant => OPB_MGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
Freeze => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_toutSup => Sl_toutSup,
Sln_retry => Sl_retry,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_DMA_Ack => open,
Bus2IP_Freeze => open,
Bus2IP_Reset => iBus2IP_Reset,
IP2Bus_Clk => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
OPB_Clk => OPB_Clk,
Reset => OPB_Rst
);
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_CS => uBus2IP_CS,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_RdCE(0 to USER_NUM_CE-1) <= iBus2IP_RdCE(0 to USER_NUM_CE-1);
uBus2IP_WrCE(0 to USER_NUM_CE-1) <= iBus2IP_WrCE(0 to USER_NUM_CE-1);
uBus2IP_CS <= iBus2IP_CS;
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end imp;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
entity opb_SynchManager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"00FFFFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_SynchManager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture imp of opb_SynchManager is
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - 2 to
C_OPB_AWIDTH - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_01, -- user logic address range 0 bank
1 => USER_02, -- user logic address range 1 bank
2 => USER_03, -- user logic address range 2 bank
3 => USER_04, -- user logic address range 3 bank
4 => USER_05, -- user logic address range 4 bank
5 => USER_06, -- user logic address range 5 bank
6 => USER_07 -- user logic address range 6 bank
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify data width for each target address range.
constant USER_AR0_DWIDTH : integer := 32;
constant USER_AR1_DWIDTH : integer := 32;
constant USER_AR2_DWIDTH : integer := 32;
constant USER_AR3_DWIDTH : integer := 32;
constant USER_AR4_DWIDTH : integer := 32;
constant USER_AR5_DWIDTH : integer := 32;
constant USER_AR6_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_AR0_DWIDTH, -- user logic address range 0 data width
1 => USER_AR1_DWIDTH, -- user logic address range 1 data width
2 => USER_AR2_DWIDTH, -- user logic address range 2 data width
3 => USER_AR3_DWIDTH, -- user logic address range 3 data width
4 => USER_AR4_DWIDTH, -- user logic address range 4 data width
5 => USER_AR5_DWIDTH, -- user logic address range 5 data width
6 => USER_AR6_DWIDTH -- user logic address range 6 data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0=>(others => 0), -- user logic address range 0 dependent properties (none defined)
1=>(others => 0), -- user logic address range 1 dependent properties (none defined)
2=>(others => 0), -- user logic address range 2 dependent properties (none defined)
3=>(others => 0), -- user logic address range 3 dependent properties (none defined)
4=>(others => 0), -- user logic address range 4 dependent properties (none defined)
5=>(others => 0), -- user logic address range 5 dependent properties (none defined)
6=>(others => 0) -- user logic address range 6 dependent properties (none defined)
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the opb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- opb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 0;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 64.
constant DEV_MAX_BURST_SIZE : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a opb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of opb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify arbitration scheme if both dma and user-logic masters are present,
-- following schemes are supported:
-- 0 - FAIR
-- 1 - DMA_PRIORITY
-- 2 - IP_PRIORITY
constant MASTER_ARB_MODEL : integer := 0;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify the size (must be power of 2) of burst that dma uses to
-- tranfer data on the bus, a value of one causes dma to use single
-- transactions (burst disabled).
constant DMA_BURST_SIZE : integer := 16;
-- specify whether to transfer the dma remanining data as a series of
-- single transactions or as a short burst.
constant DMA_SHORT_BURST_REMAINDER : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma (usually left at
-- default value), apply to software design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000000;
-- specify period of the opb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant OPB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the opb data bus width.
constant IPIF_DWIDTH : integer := C_OPB_DWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_OPB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iIP2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal iBus2IP_RNW : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Data : std_logic_vector(0 to IPIF_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iIP2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to 31) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_MstBE : std_logic_vector(0 to (C_OPB_DWIDTH/8) - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal iBus2IP_BE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1);
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_ADDR_RNG-1);
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
opb_ipif_i : entity opb_ipif_v2_00_h.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_MASTER_ARB_MODEL => MASTER_ARB_MODEL,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => DMA_SHORT_BURST_REMAINDER,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_CLK_PERIOD_PS => OPB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
Sln_DBus => Sl_DBus,
Mn_ABus => M_ABus,
IP2Bus_Addr => iIP2Bus_Addr,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_CS => iBus2IP_CS,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '1',
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2IP_Addr => iIP2IP_Addr,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_IPMstTrans => open,
Bus2IP_Burst => open,
Mn_request => M_request,
Mn_busLock => M_busLock,
Mn_select => M_select,
Mn_RNW => M_RNW,
Mn_BE => M_BE,
Mn_seqAddr => M_seqAddr,
OPB_MnGrant => OPB_MGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
Freeze => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_toutSup => Sl_toutSup,
Sln_retry => Sl_retry,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_DMA_Ack => open,
Bus2IP_Freeze => open,
Bus2IP_Reset => iBus2IP_Reset,
IP2Bus_Clk => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
OPB_Clk => OPB_Clk,
Reset => OPB_Rst
);
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_CS => uBus2IP_CS,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_RdCE(0 to USER_NUM_CE-1) <= iBus2IP_RdCE(0 to USER_NUM_CE-1);
uBus2IP_WrCE(0 to USER_NUM_CE-1) <= iBus2IP_WrCE(0 to USER_NUM_CE-1);
uBus2IP_CS <= iBus2IP_CS;
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end imp;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
entity opb_SynchManager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"00FFFFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_SynchManager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture imp of opb_SynchManager is
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_OPB_AWIDTH - MUTEX_BITS - 2 to
C_OPB_AWIDTH - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_OPB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_OPB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_01, -- user logic address range 0 bank
1 => USER_02, -- user logic address range 1 bank
2 => USER_03, -- user logic address range 2 bank
3 => USER_04, -- user logic address range 3 bank
4 => USER_05, -- user logic address range 4 bank
5 => USER_06, -- user logic address range 5 bank
6 => USER_07 -- user logic address range 6 bank
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify data width for each target address range.
constant USER_AR0_DWIDTH : integer := 32;
constant USER_AR1_DWIDTH : integer := 32;
constant USER_AR2_DWIDTH : integer := 32;
constant USER_AR3_DWIDTH : integer := 32;
constant USER_AR4_DWIDTH : integer := 32;
constant USER_AR5_DWIDTH : integer := 32;
constant USER_AR6_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_AR0_DWIDTH, -- user logic address range 0 data width
1 => USER_AR1_DWIDTH, -- user logic address range 1 data width
2 => USER_AR2_DWIDTH, -- user logic address range 2 data width
3 => USER_AR3_DWIDTH, -- user logic address range 3 data width
4 => USER_AR4_DWIDTH, -- user logic address range 4 data width
5 => USER_AR5_DWIDTH, -- user logic address range 5 data width
6 => USER_AR6_DWIDTH -- user logic address range 6 data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0=>(others => 0), -- user logic address range 0 dependent properties (none defined)
1=>(others => 0), -- user logic address range 1 dependent properties (none defined)
2=>(others => 0), -- user logic address range 2 dependent properties (none defined)
3=>(others => 0), -- user logic address range 3 dependent properties (none defined)
4=>(others => 0), -- user logic address range 4 dependent properties (none defined)
5=>(others => 0), -- user logic address range 5 dependent properties (none defined)
6=>(others => 0) -- user logic address range 6 dependent properties (none defined)
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the opb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- opb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 0;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 64.
constant DEV_MAX_BURST_SIZE : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a opb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of opb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify arbitration scheme if both dma and user-logic masters are present,
-- following schemes are supported:
-- 0 - FAIR
-- 1 - DMA_PRIORITY
-- 2 - IP_PRIORITY
constant MASTER_ARB_MODEL : integer := 0;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify the size (must be power of 2) of burst that dma uses to
-- tranfer data on the bus, a value of one causes dma to use single
-- transactions (burst disabled).
constant DMA_BURST_SIZE : integer := 16;
-- specify whether to transfer the dma remanining data as a series of
-- single transactions or as a short burst.
constant DMA_SHORT_BURST_REMAINDER : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma (usually left at
-- default value), apply to software design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000000;
-- specify period of the opb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant OPB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the opb data bus width.
constant IPIF_DWIDTH : integer := C_OPB_DWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_OPB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iIP2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal iBus2IP_RNW : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Data : std_logic_vector(0 to IPIF_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iIP2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to 31) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_MstBE : std_logic_vector(0 to (C_OPB_DWIDTH/8) - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal iBus2IP_BE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1);
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_ADDR_RNG-1);
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
opb_ipif_i : entity opb_ipif_v2_00_h.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_MASTER_ARB_MODEL => MASTER_ARB_MODEL,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => DMA_SHORT_BURST_REMAINDER,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_CLK_PERIOD_PS => OPB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
Sln_DBus => Sl_DBus,
Mn_ABus => M_ABus,
IP2Bus_Addr => iIP2Bus_Addr,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_CS => iBus2IP_CS,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '1',
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2IP_Addr => iIP2IP_Addr,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_IPMstTrans => open,
Bus2IP_Burst => open,
Mn_request => M_request,
Mn_busLock => M_busLock,
Mn_select => M_select,
Mn_RNW => M_RNW,
Mn_BE => M_BE,
Mn_seqAddr => M_seqAddr,
OPB_MnGrant => OPB_MGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
Freeze => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_toutSup => Sl_toutSup,
Sln_retry => Sl_retry,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_DMA_Ack => open,
Bus2IP_Freeze => open,
Bus2IP_Reset => iBus2IP_Reset,
IP2Bus_Clk => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
OPB_Clk => OPB_Clk,
Reset => OPB_Rst
);
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_CS => uBus2IP_CS,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_RdCE(0 to USER_NUM_CE-1) <= iBus2IP_RdCE(0 to USER_NUM_CE-1);
uBus2IP_WrCE(0 to USER_NUM_CE-1) <= iBus2IP_WrCE(0 to USER_NUM_CE-1);
uBus2IP_CS <= iBus2IP_CS;
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end imp;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2016
-- Module Name: VGA Data Decoder
-- Project Name: VGA Data Decoder
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Convert a 4 bit number to a ascii value
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Data_Decode is
Port ( HEXNUM : in STD_LOGIC_VECTOR (3 downto 0);
ASCIINUM : out STD_LOGIC_VECTOR (7 downto 0));
end Data_Decode;
architecture Structural of Data_Decode is
begin
--convert current hex to the ascii equivalent
with hexnum select
asciinum <=
x"30" when x"0", -- 0
x"31" when x"1", -- 1
x"32" when x"2", -- 2
x"33" when x"3", -- 3
x"34" when x"4", -- 4
x"35" when x"5", -- 5
x"36" when x"6", -- 6
x"37" when x"7", -- 7
x"38" when x"8", -- 8
x"39" when x"9", -- 9
x"41" when x"A", -- A
x"42" when x"B", -- B
x"43" when x"C", -- C
x"44" when x"D", -- D
x"45" when x"E", -- E
x"46" when x"F", -- F
X"00" when others; -- invalid
end Structural;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2016
-- Module Name: VGA Data Decoder
-- Project Name: VGA Data Decoder
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Convert a 4 bit number to a ascii value
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Data_Decode is
Port ( HEXNUM : in STD_LOGIC_VECTOR (3 downto 0);
ASCIINUM : out STD_LOGIC_VECTOR (7 downto 0));
end Data_Decode;
architecture Structural of Data_Decode is
begin
--convert current hex to the ascii equivalent
with hexnum select
asciinum <=
x"30" when x"0", -- 0
x"31" when x"1", -- 1
x"32" when x"2", -- 2
x"33" when x"3", -- 3
x"34" when x"4", -- 4
x"35" when x"5", -- 5
x"36" when x"6", -- 6
x"37" when x"7", -- 7
x"38" when x"8", -- 8
x"39" when x"9", -- 9
x"41" when x"A", -- A
x"42" when x"B", -- B
x"43" when x"C", -- C
x"44" when x"D", -- D
x"45" when x"E", -- E
x"46" when x"F", -- F
X"00" when others; -- invalid
end Structural;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity web_ps2_clk is
port(
clk, reset: in std_logic;
en: in std_logic;
ps2_clk: out std_logic;
rising: out std_logic;
falling: out std_logic
);
end web_ps2_clk;
architecture Behavioral of web_ps2_clk is
constant max_ps2_counter : natural := 50_000_000 / 20_000; -- 10 kHz, clock PS/2 = 10 - 16.7 kHz
signal ps2_counter: natural range 0 to max_ps2_counter := 0; -- счетчик для генерации частоты устройства
signal ps2_clock: std_logic;
begin
ps2_clk <= ps2_clock;
clk_gen: process(reset, clk)
begin
if reset = '1' then
ps2_clock <= '1';
ps2_counter <= 0;
rising <= '0';
falling <= '0';
elsif rising_edge(clk) then
rising <= '0';
falling <= '0';
if en = '1' then
if ps2_counter = max_ps2_counter then
ps2_counter <= 0;
if ps2_clock = '1' then
ps2_clock <= '0';
falling <= '1';
else
ps2_clock <= '1';
rising <= '1';
end if;
else
ps2_counter <= ps2_counter + 1;
end if;
else
ps2_clock <= '1';
ps2_counter <= 0;
end if;
end if;
end process;
end Behavioral; |
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`protect end_protected
|
entity file6 is
end entity;
architecture test of file6 is
type natural_vector is array (natural range <>) of natural;
type ft is file of natural_vector;
begin
process is
file f1, f2 : ft;
variable v : natural_vector(1 to 5);
variable len : natural;
begin
file_open(f1, "test.bin", WRITE_MODE);
v := (1, 2, 3, 4, 5);
write(f1, v);
flush(f1); -- Flush without closing
v := (others => 0);
file_open(f2, "test.bin", READ_MODE);
read(f2, v, len);
file_close(f2);
assert v = (1, 2, 3, 4, 5);
report integer'image(len);
assert len = 5;
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_V is
generic(
NUM_BITS : positive := 163
);
port(
R : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
X2 : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c_1 : in STD_LOGIC;
c_2 : in STD_LOGIC;
toV : out STD_LOGIC_VECTOR(NUM_BITS downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_V is
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
toV <= X2 when c_1 = '0' and c_2 = '0' else
(others => '0') when c_1 = '0' and c_2 = '1' else
R;
end behave; |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pack_mips.all;
entity ram is
generic (mem_size : natural := 256; -- Size of the memory in words
latency : time := 0 ns);
port(
req : in std_logic;
adr : in bus32;
data_inout : inout bus32;
r_w : in std_logic;
ready : out std_logic
);
end;
architecture bench of ram is
type storage_array is array(natural range 1024 to 1024+4*mem_size - 1) of bus8;
signal storage : storage_array; -- The memory
begin
process(adr, data_inout, r_w)
variable inadr : integer;
variable i : natural;
begin
inadr := to_integer(unsigned(adr));
if (inadr>=storage'low) and (inadr<=storage'high) then
ready <= '0', '1' after latency;
if req = '1' then
if r_w /= '1' then -- Reading in memory
for i in 0 to 3 loop
data_inout(8*(i+1)-1 downto 8*i) <= storage(inadr+(3-i)) after latency;
end loop;
else
for i in 0 to 3 loop
storage(inadr+(3-i)) <= data_inout(8*(i+1)-1 downto 8*i) after latency;
end loop;
data_inout <= (others => 'Z');
end if;
else
data_inout <= (others => 'Z');
end if;
else
data_inout <= (others => 'Z');
ready <= 'L';
end if;
end process;
end bench;
|
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`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect end_protected
|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
library verilog;
use verilog.vl_types.all;
entity cpu is
port(
clk : in vl_logic;
clk_n : in vl_logic;
reset : in vl_logic;
if_bus_rd_data : in vl_logic_vector(31 downto 0);
if_bus_rdy_n : in vl_logic;
if_bus_grant_n : in vl_logic;
if_bus_req_n : out vl_logic;
if_bus_addr : out vl_logic_vector(29 downto 0);
if_bus_as_n : out vl_logic;
if_bus_rw : out vl_logic;
if_bus_wr_data : out vl_logic_vector(31 downto 0);
mem_bus_rd_data : in vl_logic_vector(31 downto 0);
mem_bus_rdy_n : in vl_logic;
mem_bus_grant_n : in vl_logic;
mem_bus_req_n : out vl_logic;
mem_bus_addr : out vl_logic_vector(29 downto 0);
mem_bus_as_n : out vl_logic;
mem_bus_rw : out vl_logic;
mem_bus_wr_data : out vl_logic_vector(31 downto 0);
cpu_irq : in vl_logic_vector(7 downto 0)
);
end cpu;
|
architecture rtl of fifo is
begin
-- Valid formatting
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
-- Invalid formatting
process
begin
connect_ports(
port_1 => data,
port_2=> enable,
port_3 => overflow,
port_4 => underflow
);
end process;
connect_ports(
port_1=> data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
end architecture;
|
------------------ Behavioural_HA ---------------------
-------------- Library statements -------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration half_adder--
entity half_adder_behavioural is
port (a, b : in std_logic;
sum, carry : out std_logic
);
end half_adder_behavioural;
-- architecture behavioural --
architecture behavioural of half_adder_behavioural is
begin
process(a,b)
begin
if a = '1' then
if b = '1' then
sum <= '0';
carry <= '1';
else
sum <= '1';
carry <= '0';
end if;
else
carry <= '0';
sum <= b;
end if;
end process;
end behavioural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1941.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01941ent IS
END c07s02b01x00p01n04i01941ent;
ARCHITECTURE c07s02b01x00p01n04i01941arch OF c07s02b01x00p01n04i01941ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a xor b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01941 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01941arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1941.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01941ent IS
END c07s02b01x00p01n04i01941ent;
ARCHITECTURE c07s02b01x00p01n04i01941arch OF c07s02b01x00p01n04i01941ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a xor b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01941 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01941arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1941.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01941ent IS
END c07s02b01x00p01n04i01941ent;
ARCHITECTURE c07s02b01x00p01n04i01941arch OF c07s02b01x00p01n04i01941ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a xor b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01941 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01941arch;
|
--------------------------------------------------------------------------------
-- Author: Steffen.Reith ([email protected])
--
-- Creation Date: Thu Oct 13 20:44:40 GMT+2 2016
-- Creator: Steffen Reith
-- Module Name: J1SoC_TB - A simple testbench for the J1 SoC
-- Project Name: J1Sc - A simple J1 implementation in scala
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity J1Nexys4X_tb is
end J1Nexys4X_tb;
architecture Behavioral of J1Nexys4X_tb is
-- Clock period definition (100Mhz)
constant clk_period : time := 10 ns;
-- Interrupts
signal extInt : std_logic_vector(0 downto 0) := "0";
-- PModA-Interface
signal pmodA_read : std_logic_vector(7 downto 0);
signal pmodA_write : std_logic_vector(7 downto 0);
signal pmodA_writeEnable : std_logic_vector(7 downto 0);
-- UART signals
signal rx : std_logic := '0';
signal tx : std_logic;
-- I/O signals
signal leds : std_logic_vector(15 downto 0);
signal rgbLeds : std_logic_vector(5 downto 0);
signal segments_a : std_logic;
signal segments_b : std_logic;
signal segments_c : std_logic;
signal segments_d : std_logic;
signal segments_e : std_logic;
signal segments_f : std_logic;
signal segments_g : std_logic;
signal dot : std_logic;
signal selector : std_logic_vector(7 downto 0);
signal sSwitches : std_logic_vector(15 downto 0) := (others => '0');
signal pButtons : std_logic_vector(4 downto 0) := (others => '0');
-- Clock and reset
signal boardClkLocked : std_logic;
signal boardClk : std_logic;
signal reset : std_logic;
begin
uut : entity work.J1Nexys4X
port map (boardClk => boardClk,
boardClkLocked => boardClkLocked,
reset => reset,
extInt => extInt,
pmodA_read => pmodA_read,
pmodA_write => pmodA_write,
pmodA_writeEnable => pmodA_writeEnable,
rgbLeds => rgbLeds,
segments_a => segments_a,
segments_b => segments_b,
segments_c => segments_c,
segments_d => segments_d,
segments_e => segments_e,
segments_f => segments_f,
segments_g => segments_g,
dot => dot,
selector => selector,
sSwitches => sSwitches,
pButtons => pButtons,
rx => rx,
tx => tx,
leds => leds);
-- Clock process definitions
clk_process : process
begin
-- Tell that the clock is stable
boardClkLocked <= '1';
boardClk <= '0';
wait for clk_period/2;
boardClk <= '1';
wait for clk_period/2;
end process;
reboot_proc : process
begin
-- Init the read port of PModA
pmodA_read <= (others => '0');
-- Reset the CPU (asynchronous)
reset <= '1';
-- Wait 57ns
wait for 57 ns;
-- Revoke the the reset
reset <= '0';
-- Wait forever
wait;
end process;
-- Stimulus process
stim_proc : process
-- Text I/O
variable lineBuffer : line;
begin
-- Give a info message
write(lineBuffer, string'("Start the simulation of the CPU"));
writeline(output, lineBuffer);
-- Simply wait forever
wait;
end process;
end architecture;
|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23088)
`protect data_block
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We1ityhrOj5Ys9QAdDzUCEiiaO3FC0viL9wzeh3or2I2I0D4fCT7PP0wCBrzKWt9AQSSMX22WBNq
Km07VfasXPQwgg2pm+wlHgnaLaGjmAf7ugU6mJijj1f3J5CUmawf0aX1LWDSTI/6ZrH++qiLeoxn
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n9Zb31yBovPdUevJ01LRKPM548RHACkBGpQmBxD7KbWHJH2xQs8lAgDSa4hAHNRRZ03rqOn9xjT1
JGLE0fMxPNJTUzR2vddxY4E5uS2JIQVoUqGQO/Iwmblrvnhafp3ujFRqB7dgakKsdrcx35PWBmS3
dcnKLhUxtgXkW3uepkKKzWQRjJPfhT/CvNnvsZYaQzLGpIrj+JjWO/TwFwgrom9yCs7iwSqQGk27
ef0ioArgmiGXM3qAUZy8T7fSGhgLQ00xd/wuN7EsQep6tKK47zQAOD0yD8VH9j8CsEspWqgHibMl
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0BeBTrxsj0NAqAEj5av9TEHjy6+BCKXQnEKl2MfbkcwzZj13h7E1iWzr0q+EEHmQCdjgvWDWrK+S
8S8k
`protect end_protected
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_b
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:54:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\highlow.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-e.vhd,v 1.1 2004/04/06 11:07:27 wig Exp $
-- $Date: 2004/04/06 11:07:27 $
-- $Log: ent_b-e.vhd,v $
-- Revision 1.1 2004/04/06 11:07:27 wig
-- Adding result/highlow
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_b
--
entity ent_b is
-- Generics:
-- No Generated Generics for Entity ent_b
-- Generated Port Declaration:
-- No Generated Port for Entity ent_b
end ent_b;
--
-- End of Generated Entity ent_b
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- $Id: tb_serport_uart_rxtx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_serport_uart_rxtx - sim
-- Description: Test bench for serport_uart_rxtx
--
-- Dependencies: simlib/simclk
-- tbd_serport_uart_rxtx [UUT]
--
-- To test: serport_uart_rxtx
--
-- Target Devices: generic
--
-- Verified (with tb_serport_uart_rxtx_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-21 91 - 0.26 - - c:ok
-- 2007-10-14 89 - 0.26 - - c:ok
-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-12 88 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.2 use new simclk/simclkcnt
-- 2011-10-22 417 1.1.3 now numeric_std clean
-- 2010-04-24 281 1.1.2 use direct instatiation for tbd_
-- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits
-- 2007-10-21 91 1.1 now use 'send' command, self-checking (FAIL's)
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.serportlib.all;
entity tb_serport_uart_rxtx is
end tb_serport_uart_rxtx;
architecture sim of tb_serport_uart_rxtx is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv13 := slv(to_unsigned(15, 13));
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXSD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal N_MON_VAL : slbit := '0';
signal N_MON_DAT : slv8 := (others=>'0');
signal R_MON_VAL_1 : slbit := '0';
signal R_MON_DAT_1 : slv8 := (others=>'0');
signal R_MON_VAL_2 : slbit := '0';
signal R_MON_DAT_2 : slv8 := (others=>'0');
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT : entity work.tbd_serport_uart_rxtx
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => TXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_stim: process
file fstim : text open read_mode is "tb_serport_uart_rxtx_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable irate : integer := 16;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".rate " => -- .rate
read_ea(iline, irate);
CLKDIV <= slv(to_unsigned(irate-1, 13));
when "send " => -- send
read_ea(iline, idelta);
read_ea(iline, itxdata);
while TXBUSY='1' loop
wait for clock_period;
end loop;
wait for idelta*clock_period;
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, itxdata, right, 10);
writeline(output, oline);
TXDATA <= itxdata;
TXENA <= '1';
N_MON_VAL <= '1';
N_MON_DAT <= itxdata;
wait for clock_period;
TXENA <= '0';
N_MON_VAL <= '0';
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop
idelta := 0;
while TXBUSY='1' or RXACT='1' loop
wait for clock_period;
idelta := idelta + 1;
exit when idelta>3000;
end loop;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait for 12*irate*clock_period;
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MON_VAL_1 = '1' then
if R_MON_VAL_2 = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING DATA="));
write(oline, R_MON_DAT_2);
writeline(output, oline);
end if;
R_MON_VAL_2 <= R_MON_VAL_1;
R_MON_DAT_2 <= R_MON_DAT_1;
end if;
R_MON_VAL_1 <= N_MON_VAL;
R_MON_DAT_1 <= N_MON_DAT;
if RXVAL='1' or RXERR='1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, RXDATA, right, 10);
if RXERR = '1' then
write(oline, string'(" RXERR=1"));
end if;
if R_MON_VAL_2 = '0' then
write(oline, string'(" FAIL UNEXPECTED"));
else
write(oline, string'(" CHECK"));
R_MON_VAL_2 <= '0';
if R_MON_DAT_2 = RXDATA and
RXERR='0' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL"));
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
|
-------------------------------------------------------------------------------
-- vga2tmds.vhd
-- Joris van Rantwijk
--
-- This entity takes VGA signals as input (in the form of 8-bit RGB words
-- and HSYNC/VSYNC signals) and produces TMDS signals as output.
--
-- The input side of this entity may be connected to SVGACTRL or APBVGA
-- components from GRLIB. The output side of this entity may be connected
-- to a TMDS transmitter for a HDMI or DVI output port.
--
-- The output operates in DVI mode: no guard bands and no data islands
-- are sent. This is actually not allowed on HDMI links, but HDMI devices
-- should just accept it in DVI-compatibility mode.
--
------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library unisim;
use unisim.vcomponents.ODDR2;
entity vga2tmds is
generic (
tech : integer := 0
);
port (
-- VGA pixel clock.
vgaclk : in std_logic;
-- Fast clock at 5 times pixel clock frequency.
fastclk : in std_logic;
-- Output signals from APBVGA or SVGACTRL.
vgao : in apbvga_out_type;
-- TMDS output signals.
tmdsclk : out std_logic;
tmdsdat : out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of vga2tmds is
-- registers in video coding pipeline
type video_coder_regs is record
q0_dat : std_logic_vector(8 downto 0); -- stage 0: partial XOR
q1_dat : std_logic_vector(8 downto 0); -- stage 1: transition minimized
q2_dat : std_logic_vector(8 downto 0); -- stage 2: transition minimized
q2_nd : signed(3 downto 0); -- stage 2: (N1 - N0) / 2
q3_dat : std_logic_vector(9 downto 0); -- stage 3: final output
q3_cnt : signed(3 downto 0); -- stage 3: DC counter
end record;
-- registers in pixel clock domain
type pregs_type is record
blank : std_logic_vector(3 downto 0); -- pipeline for blanking signal
vcode0 : video_coder_regs; -- coding pipeline for ch0
vcode1 : video_coder_regs; -- coding pipeline for ch1
vcode2 : video_coder_regs; -- coding pipeline for ch2
bufptr : std_ulogic; -- current buffer slot
dbuf0 : std_logic_vector(29 downto 0); -- 2-slot output buffer
dbuf1 : std_logic_vector(29 downto 0);
end record;
-- registers in fast clock domain
type fregs_type is record
bufptr : std_logic_vector(1 downto 0); -- resynced bufptr
shiftstate : std_logic_vector(3 downto 0); -- one-hot state
tm0shift : std_logic_vector(9 downto 0); -- output shift registers
tm1shift : std_logic_vector(9 downto 0);
tm2shift : std_logic_vector(9 downto 0);
tm0out : std_logic_vector(1 downto 0); -- DDR output registers
tm1out : std_logic_vector(1 downto 0);
tm2out : std_logic_vector(1 downto 0);
tmcout : std_logic_vector(1 downto 0);
end record;
-- reset values
constant video_coder_regs_reset: video_coder_regs := (
q0_dat => (others => '0'),
q1_dat => (others => '0'),
q2_dat => (others => '0'),
q2_nd => (others => '0'),
q3_dat => (others => '0'),
q3_cnt => (others => '0') );
constant pregs_reset: pregs_type := (
blank => (others => '0'),
vcode0 => video_coder_regs_reset,
vcode1 => video_coder_regs_reset,
vcode2 => video_coder_regs_reset,
bufptr => '0',
dbuf0 => (others => '0'),
dbuf1 => (others => '0') );
-- registers in pixel clock domain
signal pr : pregs_type := pregs_reset;
signal prin : pregs_type;
-- registers in fast clock domain
signal fr, frin : fregs_type;
signal vcc, gnd: std_ulogic;
signal fastclk_n: std_ulogic;
-- Control Period Coding
constant tmds_ctrl_code_00: std_logic_vector(9 downto 0) := "1101010100";
constant tmds_ctrl_code_01: std_logic_vector(9 downto 0) := "0010101011";
constant tmds_ctrl_code_10: std_logic_vector(9 downto 0) := "0101010100";
constant tmds_ctrl_code_11: std_logic_vector(9 downto 0) := "1010101011";
-----------------------------------------------------------------------------
-- Video Coding pipeline
-----------------------------------------------------------------------------
function count_bits(d: in std_logic_vector; n: in integer)
return unsigned is
variable y: unsigned(n-1 downto 0);
begin
y := to_unsigned(0, n);
for i in d'range loop
if d(i) = '1' then
y := y + 1;
end if;
end loop;
return y;
end function;
procedure tmds_video_coder(din: in std_logic_vector(7 downto 0);
clrn: in std_ulogic;
regs: in video_coder_regs;
vregs: out video_coder_regs ) is
variable v_cnt_din: unsigned(2 downto 0);
begin
-- stage 1: XOR first 5 bits and choose between XOR/XNOR coding
vregs.q0_dat(0) := din(0);
vregs.q0_dat(1) := din(0) xor din(1);
vregs.q0_dat(2) := din(0) xor din(1) xor din(2);
vregs.q0_dat(3) := din(0) xor din(1) xor din(2) xor din(3);
vregs.q0_dat(4) := din(0) xor din(1) xor din(2) xor din(3) xor din(4);
vregs.q0_dat(7 downto 5) := din(7 downto 5);
v_cnt_din := count_bits(din(7 downto 1), 3);
if v_cnt_din > 3 then
vregs.q0_dat(8) := '0';
else
vregs.q0_dat(8) := '1';
end if;
-- stage 2: XOR last 3 bits and apply XNOR if needed
vregs.q1_dat(0) := regs.q0_dat(0);
vregs.q1_dat(1) := regs.q0_dat(1) xor regs.q0_dat(8) xor '1';
vregs.q1_dat(2) := regs.q0_dat(2);
vregs.q1_dat(3) := regs.q0_dat(3) xor regs.q0_dat(0) xor '1';
vregs.q1_dat(4) := regs.q0_dat(4);
vregs.q1_dat(5) := regs.q0_dat(4) xor regs.q0_dat(5) xor regs.q0_dat(8) xor '1';
vregs.q1_dat(6) := regs.q0_dat(4) xor regs.q0_dat(5) xor regs.q0_dat(6);
vregs.q1_dat(7) := regs.q0_dat(4) xor regs.q0_dat(5) xor regs.q0_dat(6) xor regs.q0_dat(7) xor regs.q0_dat(8) xor '1';
vregs.q1_dat(8) := regs.q0_dat(8);
-- stage 3: count difference between nr of 1 and 0 bits (divided by 2)
vregs.q2_dat := regs.q1_dat;
vregs.q2_nd := signed(count_bits(regs.q1_dat(7 downto 0), 4)) - 4;
-- stage 4: DC balance
if (regs.q3_cnt < 0 and regs.q2_nd < 0) or
((regs.q3_cnt = 0 or regs.q2_nd = 0) and (regs.q2_dat(8) = '0')) then
-- flip bits
vregs.q3_dat(7 downto 0) := not regs.q2_dat(7 downto 0);
vregs.q3_dat(8) := regs.q2_dat(8);
vregs.q3_dat(9) := '1';
if regs.q2_dat(8) = '1' then
vregs.q3_cnt := regs.q3_cnt - regs.q2_nd + 1;
else
vregs.q3_cnt := regs.q3_cnt - regs.q2_nd;
end if;
else
-- keep bits
vregs.q3_dat(7 downto 0) := regs.q2_dat(7 downto 0);
vregs.q3_dat(8) := regs.q2_dat(8);
vregs.q3_dat(9) := '0';
if regs.q2_dat(8) = '1' then
vregs.q3_cnt := regs.q3_cnt + regs.q2_nd;
else
vregs.q3_cnt := regs.q3_cnt + regs.q2_nd - 1;
end if;
end if;
-- reset DC counter
if clrn = '0' then
vregs.q3_cnt := "0000";
end if;
end procedure;
begin
vcc <= '1'; gnd <= '0';
fastclk_n <= not fastclk;
-----------------------------------------------------------------------------
-- DDR output registers
-----------------------------------------------------------------------------
-- It would of course be nicer to do this with ddr_oreg from techmap,
-- but it can not handle the rising -> falling data path fast enough.
ddr0: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsdat(0), C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tm0out(0), D1 => fr.tm0out(1), R => gnd, S => gnd );
ddr1: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsdat(1), C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tm1out(0), D1 => fr.tm1out(1), R => gnd, S => gnd );
ddr2: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsdat(2), C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tm2out(0), D1 => fr.tm2out(1), R => gnd, S => gnd );
ddrc: ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => tmdsclk, C0 => fastclk, C1 => fastclk_n, CE => vcc,
D0 => fr.tmcout(0), D1 => fr.tmcout(1), R => gnd, S => gnd );
-----------------------------------------------------------------------------
-- Combinatorial process for slow signals (TMDS encoder)
-----------------------------------------------------------------------------
pcomb: process (pr, vgao) is
variable v: pregs_type;
variable vtm0: std_logic_vector(9 downto 0);
variable vtm1: std_logic_vector(9 downto 0);
variable vtm2: std_logic_vector(9 downto 0);
begin
v := pr;
-- Video Data Coding pipeline.
v.blank := pr.blank(2 downto 0) & vgao.blank;
tmds_video_coder(vgao.video_out_b, pr.blank(2), pr.vcode0, v.vcode0);
tmds_video_coder(vgao.video_out_g, pr.blank(2), pr.vcode1, v.vcode1);
tmds_video_coder(vgao.video_out_r, pr.blank(2), pr.vcode2, v.vcode2);
if pr.blank(3) = '0' then
-- Display blanking; use Control Period Coding.
-- Send D0=HSYNC and D1=VSYNC via channel 0.
if vgao.vsync = '0' and vgao.hsync = '0' then
vtm0 := tmds_ctrl_code_00;
elsif vgao.vsync = '0' and vgao.hsync = '1' then
vtm0 := tmds_ctrl_code_01;
elsif vgao.vsync = '1' and vgao.hsync = '0' then
vtm0 := tmds_ctrl_code_10;
else
vtm0 := tmds_ctrl_code_11;
end if;
-- Send Video Data Preamble via channels 1 and 2.
vtm1 := tmds_ctrl_code_01;
vtm2 := tmds_ctrl_code_00;
else
-- Send Video Data; use 24-bit RGB pixel encoding.
vtm0 := pr.vcode0.q3_dat;
vtm1 := pr.vcode1.q3_dat;
vtm2 := pr.vcode2.q3_dat;
end if;
-- Store output in buffer.
v.bufptr := not pr.bufptr;
if pr.bufptr = '1' then
v.dbuf0 := vtm2 & vtm1 & vtm0;
else
v.dbuf1 := vtm2 & vtm1 & vtm0;
end if;
prin <= v;
end process;
-----------------------------------------------------------------------------
-- Combinatorial process for fast signals (TMDS serializer)
-----------------------------------------------------------------------------
fcomb: process (pr, fr) is
variable v: fregs_type;
begin
v := fr;
-- Resynchronize buffer pointer in fast clock domain.
v.bufptr := pr.bufptr & fr.bufptr(1 downto 1);
-- Update shift state.
if fr.shiftstate(0) = '1' then
v.shiftstate := (others => '0');
else
v.shiftstate := "1" & fr.shiftstate(fr.shiftstate'high downto 1);
end if;
-- Update data shift registers.
if fr.shiftstate(0) = '1' then
-- Pick up a new set of 10-bit words once per 5 clock cycles.
if pr.bufptr = '0' then
v.tm0shift := pr.dbuf0(9 downto 0);
v.tm1shift := pr.dbuf0(19 downto 10);
v.tm2shift := pr.dbuf0(29 downto 20);
else
v.tm0shift := pr.dbuf1(9 downto 0);
v.tm1shift := pr.dbuf1(19 downto 10);
v.tm2shift := pr.dbuf1(29 downto 20);
end if;
else
v.tm0shift := "00" & fr.tm0shift(9 downto 2);
v.tm1shift := "00" & fr.tm1shift(9 downto 2);
v.tm2shift := "00" & fr.tm2shift(9 downto 2);
end if;
-- Select 2 output bits per channel per clock cycle.
v.tm0out := fr.tm0shift(1 downto 0);
v.tm1out := fr.tm1shift(1 downto 0);
v.tm2out := fr.tm2shift(1 downto 0);
v.tmcout := fr.shiftstate(2 downto 1);
frin <= v;
end process;
-----------------------------------------------------------------------------
-- Synchronous process in pixel clock domain
-----------------------------------------------------------------------------
pregs: process (vgaclk) is
begin
if rising_edge(vgaclk) then
pr <= prin;
end if;
end process;
-----------------------------------------------------------------------------
-- Synchronous process in fast clock domain
-----------------------------------------------------------------------------
fregs: process (fastclk) is
begin
if rising_edge(fastclk) then
fr <= frin;
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------------------
--
-- Input file : std_Pkg.vhd
-- Design name : std_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Package with several standard components.
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
PACKAGE std_Pkg IS
----------------------------------------------------------------------------------------------
-- STANDARD COMPONENTS IN STD_PKG
----------------------------------------------------------------------------------------------
COMPONENT sram GENERIC
(
WIDTH : positive;
SIZE : positive
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT sram_4en GENERIC
(
WIDTH : positive;
SIZE : positive
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic_vector(3 DOWNTO 0);
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT dsram GENERIC
(
WIDTH : positive;
SIZE : positive
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
ena_i : IN std_ulogic;
dat_w_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_w_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
----------------------------------------------------------------------------------------------
-- FUNCTIONS IN STD_PKG
----------------------------------------------------------------------------------------------
FUNCTION v_or(d : std_ulogic_vector) RETURN std_ulogic;
FUNCTION is_zero(d : std_ulogic_vector) RETURN std_ulogic;
FUNCTION is_not_zero(d : std_ulogic_vector) RETURN std_ulogic;
FUNCTION my_conv_integer(a: std_ulogic_vector) RETURN integer;
FUNCTION notx(d : std_ulogic_vector) RETURN boolean;
FUNCTION compare(a, b : std_ulogic_vector) RETURN std_ulogic;
FUNCTION multiply(a, b : std_ulogic_vector) RETURN std_ulogic_vector;
FUNCTION sign_extend(value: std_ulogic_vector; fill: std_ulogic; size: positive) RETURN std_ulogic_vector;
FUNCTION add(a, b : std_ulogic_vector; ci: std_ulogic) RETURN std_ulogic_vector;
FUNCTION increment(a : std_ulogic_vector) RETURN std_ulogic_vector;
FUNCTION shift(value : std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); s: std_ulogic; t: std_ulogic) RETURN std_ulogic_vector;
FUNCTION shift_left(value : std_ulogic_vector(31 DOWNTO 0); shamt : std_ulogic_vector(4 DOWNTO 0)) RETURN std_ulogic_vector;
FUNCTION shift_right(value : std_ulogic_vector(31 DOWNTO 0); shamt : std_ulogic_vector(4 DOWNTO 0); padding: std_ulogic) RETURN std_ulogic_vector;
END std_Pkg;
PACKAGE BODY std_Pkg IS
-- Unary OR reduction
FUNCTION v_or(d : std_ulogic_vector) RETURN std_ulogic IS
VARIABLE z : std_ulogic;
BEGIN
z := '0';
IF notx (d) THEN
FOR i IN d'range LOOP
z := z OR d(i);
END LOOP;
END IF;
RETURN z;
END;
-- Check for ones in the vector
FUNCTION is_not_zero(d : std_ulogic_vector) RETURN std_ulogic IS
VARIABLE z : std_ulogic_vector(d'range);
BEGIN
z := (OTHERS => '0');
IF notx(d) THEN
IF d = z THEN
RETURN '0';
ELSE
RETURN '1';
END IF;
ELSE
RETURN '0';
END IF;
END;
-- Check for ones in the vector
FUNCTION is_zero(d : std_ulogic_vector) RETURN std_ulogic IS
BEGIN
RETURN NOT is_not_zero(d);
END;
-- rewrite conv_integer to avoid modelsim warnings
FUNCTION my_conv_integer(a : std_ulogic_vector) RETURN integer IS
VARIABLE res : integer RANGE 0 TO 2**a'length-1;
BEGIN
res := 0;
IF (notx(a)) THEN
res := to_integer(unsigned(a));
END IF;
RETURN res;
END;
FUNCTION compare(a, b : std_ulogic_vector) RETURN std_ulogic IS
VARIABLE z : std_ulogic;
BEGIN
IF notx(a & b) AND a = b THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END;
-- Unary NOT X test
FUNCTION notx(d : std_ulogic_vector) RETURN boolean IS
VARIABLE res : boolean;
BEGIN
res := true;
-- pragma translate_off
res := NOT is_x(d);
-- pragma translate_on
RETURN (res);
END;
-- -- 32 bit shifter
-- -- SYNOPSIS:
-- -- value: value to be shifted
-- -- shamt: shift amount
-- -- s 0 / 1: shift right / left
-- -- t 0 / 1: shift logical / arithmetic
-- -- PSEUDOCODE (from microblaze reference guide)
-- -- if S = 1 then
-- -- (rD) ← (rA) << (rB)[27:31]
-- -- else
-- -- if T = 1 then
-- -- if ((rB)[27:31]) ≠ 0 then
-- -- (rD)[0:(rB)[27:31]-1] ← (rA)[0]
-- -- (rD)[(rB)[27:31]:31] ← (rA) >> (rB)[27:31]
-- -- else
-- -- (rD) ← (rA)
-- -- else
-- -- (rD) ← (rA) >> (rB)[27:31]
FUNCTION shift(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); s: std_ulogic; t: std_ulogic) RETURN std_ulogic_vector IS
BEGIN
IF s = '1' THEN
-- left arithmetic or logical shift
RETURN shift_left(value, shamt);
ELSE
IF t = '1' THEN
-- right arithmetic shift
RETURN shift_right(value, shamt, value(31));
ELSE
-- right logical shift
RETURN shift_right(value, shamt, '0');
END IF;
END IF;
END;
FUNCTION shift_left(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0)) RETURN std_ulogic_vector IS
VARIABLE result: std_ulogic_vector(31 DOWNTO 0);
VARIABLE paddings: std_ulogic_vector(15 DOWNTO 0);
BEGIN
paddings := (OTHERS => '0');
result := value;
IF (shamt(4) = '1') THEN result := result(15 DOWNTO 0) & paddings(15 DOWNTO 0); END IF;
IF (shamt(3) = '1') THEN result := result(23 DOWNTO 0) & paddings( 7 DOWNTO 0); END IF;
IF (shamt(2) = '1') THEN result := result(27 DOWNTO 0) & paddings( 3 DOWNTO 0); END IF;
IF (shamt(1) = '1') THEN result := result(29 DOWNTO 0) & paddings( 1 DOWNTO 0); END IF;
IF (shamt(0) = '1') THEN result := result(30 DOWNTO 0) & paddings( 0 ); END IF;
RETURN result;
END;
FUNCTION shift_right(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); padding: std_ulogic) RETURN std_ulogic_vector IS
VARIABLE result: std_ulogic_vector(31 DOWNTO 0);
VARIABLE paddings: std_ulogic_vector(15 DOWNTO 0);
BEGIN
paddings := (OTHERS => padding);
result := value;
IF (shamt(4) = '1') THEN result := paddings(15 DOWNTO 0) & result(31 DOWNTO 16); END IF;
IF (shamt(3) = '1') THEN result := paddings( 7 DOWNTO 0) & result(31 DOWNTO 8); END IF;
IF (shamt(2) = '1') THEN result := paddings( 3 DOWNTO 0) & result(31 DOWNTO 4); END IF;
IF (shamt(1) = '1') THEN result := paddings( 1 DOWNTO 0) & result(31 DOWNTO 2); END IF;
IF (shamt(0) = '1') THEN result := paddings( 0 ) & result(31 DOWNTO 1); END IF;
RETURN result;
END;
FUNCTION multiply(a, b: std_ulogic_vector) RETURN std_ulogic_vector IS
VARIABLE x: std_ulogic_vector (a'length + b'length - 1 DOWNTO 0);
BEGIN
x := std_ulogic_vector(signed(a) * signed(b));
RETURN x(31 DOWNTO 0);
END;
FUNCTION sign_extend(value: std_ulogic_vector; fill: std_ulogic; size: positive) RETURN std_ulogic_vector IS
VARIABLE a: std_ulogic_vector (size - 1 DOWNTO 0);
BEGIN
a(size - 1 DOWNTO value'length) := (OTHERS => fill);
a(value'length - 1 DOWNTO 0) := value;
return a;
END;
FUNCTION add(a, b : std_ulogic_vector; ci: std_ulogic) RETURN std_ulogic_vector IS
VARIABLE x : std_ulogic_vector(a'length + 1 DOWNTO 0);
BEGIN
x := (OTHERS => '0');
IF notx (a & b & ci) THEN
x := std_ulogic_vector(signed('0' & a & '1') + signed('0' & b & ci));
END IF;
RETURN x(a'length + 1 DOWNTO 1);
END;
FUNCTION increment(a : std_ulogic_vector) RETURN std_ulogic_vector IS
VARIABLE x : std_ulogic_vector(a'length-1 DOWNTO 0);
BEGIN
x := (OTHERS => '0');
IF notx (a) THEN
x := std_ulogic_vector(signed(a) + 1);
END IF;
RETURN x;
END;
END std_Pkg; |
----------------------------------------------------------------------------------------------
--
-- Input file : std_Pkg.vhd
-- Design name : std_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Package with several standard components.
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
PACKAGE std_Pkg IS
----------------------------------------------------------------------------------------------
-- STANDARD COMPONENTS IN STD_PKG
----------------------------------------------------------------------------------------------
COMPONENT sram GENERIC
(
WIDTH : positive;
SIZE : positive
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT sram_4en GENERIC
(
WIDTH : positive;
SIZE : positive
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic_vector(3 DOWNTO 0);
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT dsram GENERIC
(
WIDTH : positive;
SIZE : positive
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
ena_i : IN std_ulogic;
dat_w_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_w_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
----------------------------------------------------------------------------------------------
-- FUNCTIONS IN STD_PKG
----------------------------------------------------------------------------------------------
FUNCTION v_or(d : std_ulogic_vector) RETURN std_ulogic;
FUNCTION is_zero(d : std_ulogic_vector) RETURN std_ulogic;
FUNCTION is_not_zero(d : std_ulogic_vector) RETURN std_ulogic;
FUNCTION my_conv_integer(a: std_ulogic_vector) RETURN integer;
FUNCTION notx(d : std_ulogic_vector) RETURN boolean;
FUNCTION compare(a, b : std_ulogic_vector) RETURN std_ulogic;
FUNCTION multiply(a, b : std_ulogic_vector) RETURN std_ulogic_vector;
FUNCTION sign_extend(value: std_ulogic_vector; fill: std_ulogic; size: positive) RETURN std_ulogic_vector;
FUNCTION add(a, b : std_ulogic_vector; ci: std_ulogic) RETURN std_ulogic_vector;
FUNCTION increment(a : std_ulogic_vector) RETURN std_ulogic_vector;
FUNCTION shift(value : std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); s: std_ulogic; t: std_ulogic) RETURN std_ulogic_vector;
FUNCTION shift_left(value : std_ulogic_vector(31 DOWNTO 0); shamt : std_ulogic_vector(4 DOWNTO 0)) RETURN std_ulogic_vector;
FUNCTION shift_right(value : std_ulogic_vector(31 DOWNTO 0); shamt : std_ulogic_vector(4 DOWNTO 0); padding: std_ulogic) RETURN std_ulogic_vector;
END std_Pkg;
PACKAGE BODY std_Pkg IS
-- Unary OR reduction
FUNCTION v_or(d : std_ulogic_vector) RETURN std_ulogic IS
VARIABLE z : std_ulogic;
BEGIN
z := '0';
IF notx (d) THEN
FOR i IN d'range LOOP
z := z OR d(i);
END LOOP;
END IF;
RETURN z;
END;
-- Check for ones in the vector
FUNCTION is_not_zero(d : std_ulogic_vector) RETURN std_ulogic IS
VARIABLE z : std_ulogic_vector(d'range);
BEGIN
z := (OTHERS => '0');
IF notx(d) THEN
IF d = z THEN
RETURN '0';
ELSE
RETURN '1';
END IF;
ELSE
RETURN '0';
END IF;
END;
-- Check for ones in the vector
FUNCTION is_zero(d : std_ulogic_vector) RETURN std_ulogic IS
BEGIN
RETURN NOT is_not_zero(d);
END;
-- rewrite conv_integer to avoid modelsim warnings
FUNCTION my_conv_integer(a : std_ulogic_vector) RETURN integer IS
VARIABLE res : integer RANGE 0 TO 2**a'length-1;
BEGIN
res := 0;
IF (notx(a)) THEN
res := to_integer(unsigned(a));
END IF;
RETURN res;
END;
FUNCTION compare(a, b : std_ulogic_vector) RETURN std_ulogic IS
VARIABLE z : std_ulogic;
BEGIN
IF notx(a & b) AND a = b THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END;
-- Unary NOT X test
FUNCTION notx(d : std_ulogic_vector) RETURN boolean IS
VARIABLE res : boolean;
BEGIN
res := true;
-- pragma translate_off
res := NOT is_x(d);
-- pragma translate_on
RETURN (res);
END;
-- -- 32 bit shifter
-- -- SYNOPSIS:
-- -- value: value to be shifted
-- -- shamt: shift amount
-- -- s 0 / 1: shift right / left
-- -- t 0 / 1: shift logical / arithmetic
-- -- PSEUDOCODE (from microblaze reference guide)
-- -- if S = 1 then
-- -- (rD) ← (rA) << (rB)[27:31]
-- -- else
-- -- if T = 1 then
-- -- if ((rB)[27:31]) ≠ 0 then
-- -- (rD)[0:(rB)[27:31]-1] ← (rA)[0]
-- -- (rD)[(rB)[27:31]:31] ← (rA) >> (rB)[27:31]
-- -- else
-- -- (rD) ← (rA)
-- -- else
-- -- (rD) ← (rA) >> (rB)[27:31]
FUNCTION shift(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); s: std_ulogic; t: std_ulogic) RETURN std_ulogic_vector IS
BEGIN
IF s = '1' THEN
-- left arithmetic or logical shift
RETURN shift_left(value, shamt);
ELSE
IF t = '1' THEN
-- right arithmetic shift
RETURN shift_right(value, shamt, value(31));
ELSE
-- right logical shift
RETURN shift_right(value, shamt, '0');
END IF;
END IF;
END;
FUNCTION shift_left(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0)) RETURN std_ulogic_vector IS
VARIABLE result: std_ulogic_vector(31 DOWNTO 0);
VARIABLE paddings: std_ulogic_vector(15 DOWNTO 0);
BEGIN
paddings := (OTHERS => '0');
result := value;
IF (shamt(4) = '1') THEN result := result(15 DOWNTO 0) & paddings(15 DOWNTO 0); END IF;
IF (shamt(3) = '1') THEN result := result(23 DOWNTO 0) & paddings( 7 DOWNTO 0); END IF;
IF (shamt(2) = '1') THEN result := result(27 DOWNTO 0) & paddings( 3 DOWNTO 0); END IF;
IF (shamt(1) = '1') THEN result := result(29 DOWNTO 0) & paddings( 1 DOWNTO 0); END IF;
IF (shamt(0) = '1') THEN result := result(30 DOWNTO 0) & paddings( 0 ); END IF;
RETURN result;
END;
FUNCTION shift_right(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); padding: std_ulogic) RETURN std_ulogic_vector IS
VARIABLE result: std_ulogic_vector(31 DOWNTO 0);
VARIABLE paddings: std_ulogic_vector(15 DOWNTO 0);
BEGIN
paddings := (OTHERS => padding);
result := value;
IF (shamt(4) = '1') THEN result := paddings(15 DOWNTO 0) & result(31 DOWNTO 16); END IF;
IF (shamt(3) = '1') THEN result := paddings( 7 DOWNTO 0) & result(31 DOWNTO 8); END IF;
IF (shamt(2) = '1') THEN result := paddings( 3 DOWNTO 0) & result(31 DOWNTO 4); END IF;
IF (shamt(1) = '1') THEN result := paddings( 1 DOWNTO 0) & result(31 DOWNTO 2); END IF;
IF (shamt(0) = '1') THEN result := paddings( 0 ) & result(31 DOWNTO 1); END IF;
RETURN result;
END;
FUNCTION multiply(a, b: std_ulogic_vector) RETURN std_ulogic_vector IS
VARIABLE x: std_ulogic_vector (a'length + b'length - 1 DOWNTO 0);
BEGIN
x := std_ulogic_vector(signed(a) * signed(b));
RETURN x(31 DOWNTO 0);
END;
FUNCTION sign_extend(value: std_ulogic_vector; fill: std_ulogic; size: positive) RETURN std_ulogic_vector IS
VARIABLE a: std_ulogic_vector (size - 1 DOWNTO 0);
BEGIN
a(size - 1 DOWNTO value'length) := (OTHERS => fill);
a(value'length - 1 DOWNTO 0) := value;
return a;
END;
FUNCTION add(a, b : std_ulogic_vector; ci: std_ulogic) RETURN std_ulogic_vector IS
VARIABLE x : std_ulogic_vector(a'length + 1 DOWNTO 0);
BEGIN
x := (OTHERS => '0');
IF notx (a & b & ci) THEN
x := std_ulogic_vector(signed('0' & a & '1') + signed('0' & b & ci));
END IF;
RETURN x(a'length + 1 DOWNTO 1);
END;
FUNCTION increment(a : std_ulogic_vector) RETURN std_ulogic_vector IS
VARIABLE x : std_ulogic_vector(a'length-1 DOWNTO 0);
BEGIN
x := (OTHERS => '0');
IF notx (a) THEN
x := std_ulogic_vector(signed(a) + 1);
END IF;
RETURN x;
END;
END std_Pkg; |
----------------------------------------------------------------------------------------------
--
-- Input file : std_Pkg.vhd
-- Design name : std_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Package with several standard components.
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
PACKAGE std_Pkg IS
----------------------------------------------------------------------------------------------
-- STANDARD COMPONENTS IN STD_PKG
----------------------------------------------------------------------------------------------
COMPONENT sram GENERIC
(
WIDTH : positive;
SIZE : positive
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT sram_4en GENERIC
(
WIDTH : positive;
SIZE : positive
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic_vector(3 DOWNTO 0);
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT dsram GENERIC
(
WIDTH : positive;
SIZE : positive
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
ena_i : IN std_ulogic;
dat_w_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_w_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
----------------------------------------------------------------------------------------------
-- FUNCTIONS IN STD_PKG
----------------------------------------------------------------------------------------------
FUNCTION v_or(d : std_ulogic_vector) RETURN std_ulogic;
FUNCTION is_zero(d : std_ulogic_vector) RETURN std_ulogic;
FUNCTION is_not_zero(d : std_ulogic_vector) RETURN std_ulogic;
FUNCTION my_conv_integer(a: std_ulogic_vector) RETURN integer;
FUNCTION notx(d : std_ulogic_vector) RETURN boolean;
FUNCTION compare(a, b : std_ulogic_vector) RETURN std_ulogic;
FUNCTION multiply(a, b : std_ulogic_vector) RETURN std_ulogic_vector;
FUNCTION sign_extend(value: std_ulogic_vector; fill: std_ulogic; size: positive) RETURN std_ulogic_vector;
FUNCTION add(a, b : std_ulogic_vector; ci: std_ulogic) RETURN std_ulogic_vector;
FUNCTION increment(a : std_ulogic_vector) RETURN std_ulogic_vector;
FUNCTION shift(value : std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); s: std_ulogic; t: std_ulogic) RETURN std_ulogic_vector;
FUNCTION shift_left(value : std_ulogic_vector(31 DOWNTO 0); shamt : std_ulogic_vector(4 DOWNTO 0)) RETURN std_ulogic_vector;
FUNCTION shift_right(value : std_ulogic_vector(31 DOWNTO 0); shamt : std_ulogic_vector(4 DOWNTO 0); padding: std_ulogic) RETURN std_ulogic_vector;
END std_Pkg;
PACKAGE BODY std_Pkg IS
-- Unary OR reduction
FUNCTION v_or(d : std_ulogic_vector) RETURN std_ulogic IS
VARIABLE z : std_ulogic;
BEGIN
z := '0';
IF notx (d) THEN
FOR i IN d'range LOOP
z := z OR d(i);
END LOOP;
END IF;
RETURN z;
END;
-- Check for ones in the vector
FUNCTION is_not_zero(d : std_ulogic_vector) RETURN std_ulogic IS
VARIABLE z : std_ulogic_vector(d'range);
BEGIN
z := (OTHERS => '0');
IF notx(d) THEN
IF d = z THEN
RETURN '0';
ELSE
RETURN '1';
END IF;
ELSE
RETURN '0';
END IF;
END;
-- Check for ones in the vector
FUNCTION is_zero(d : std_ulogic_vector) RETURN std_ulogic IS
BEGIN
RETURN NOT is_not_zero(d);
END;
-- rewrite conv_integer to avoid modelsim warnings
FUNCTION my_conv_integer(a : std_ulogic_vector) RETURN integer IS
VARIABLE res : integer RANGE 0 TO 2**a'length-1;
BEGIN
res := 0;
IF (notx(a)) THEN
res := to_integer(unsigned(a));
END IF;
RETURN res;
END;
FUNCTION compare(a, b : std_ulogic_vector) RETURN std_ulogic IS
VARIABLE z : std_ulogic;
BEGIN
IF notx(a & b) AND a = b THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END;
-- Unary NOT X test
FUNCTION notx(d : std_ulogic_vector) RETURN boolean IS
VARIABLE res : boolean;
BEGIN
res := true;
-- pragma translate_off
res := NOT is_x(d);
-- pragma translate_on
RETURN (res);
END;
-- -- 32 bit shifter
-- -- SYNOPSIS:
-- -- value: value to be shifted
-- -- shamt: shift amount
-- -- s 0 / 1: shift right / left
-- -- t 0 / 1: shift logical / arithmetic
-- -- PSEUDOCODE (from microblaze reference guide)
-- -- if S = 1 then
-- -- (rD) ← (rA) << (rB)[27:31]
-- -- else
-- -- if T = 1 then
-- -- if ((rB)[27:31]) ≠ 0 then
-- -- (rD)[0:(rB)[27:31]-1] ← (rA)[0]
-- -- (rD)[(rB)[27:31]:31] ← (rA) >> (rB)[27:31]
-- -- else
-- -- (rD) ← (rA)
-- -- else
-- -- (rD) ← (rA) >> (rB)[27:31]
FUNCTION shift(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); s: std_ulogic; t: std_ulogic) RETURN std_ulogic_vector IS
BEGIN
IF s = '1' THEN
-- left arithmetic or logical shift
RETURN shift_left(value, shamt);
ELSE
IF t = '1' THEN
-- right arithmetic shift
RETURN shift_right(value, shamt, value(31));
ELSE
-- right logical shift
RETURN shift_right(value, shamt, '0');
END IF;
END IF;
END;
FUNCTION shift_left(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0)) RETURN std_ulogic_vector IS
VARIABLE result: std_ulogic_vector(31 DOWNTO 0);
VARIABLE paddings: std_ulogic_vector(15 DOWNTO 0);
BEGIN
paddings := (OTHERS => '0');
result := value;
IF (shamt(4) = '1') THEN result := result(15 DOWNTO 0) & paddings(15 DOWNTO 0); END IF;
IF (shamt(3) = '1') THEN result := result(23 DOWNTO 0) & paddings( 7 DOWNTO 0); END IF;
IF (shamt(2) = '1') THEN result := result(27 DOWNTO 0) & paddings( 3 DOWNTO 0); END IF;
IF (shamt(1) = '1') THEN result := result(29 DOWNTO 0) & paddings( 1 DOWNTO 0); END IF;
IF (shamt(0) = '1') THEN result := result(30 DOWNTO 0) & paddings( 0 ); END IF;
RETURN result;
END;
FUNCTION shift_right(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); padding: std_ulogic) RETURN std_ulogic_vector IS
VARIABLE result: std_ulogic_vector(31 DOWNTO 0);
VARIABLE paddings: std_ulogic_vector(15 DOWNTO 0);
BEGIN
paddings := (OTHERS => padding);
result := value;
IF (shamt(4) = '1') THEN result := paddings(15 DOWNTO 0) & result(31 DOWNTO 16); END IF;
IF (shamt(3) = '1') THEN result := paddings( 7 DOWNTO 0) & result(31 DOWNTO 8); END IF;
IF (shamt(2) = '1') THEN result := paddings( 3 DOWNTO 0) & result(31 DOWNTO 4); END IF;
IF (shamt(1) = '1') THEN result := paddings( 1 DOWNTO 0) & result(31 DOWNTO 2); END IF;
IF (shamt(0) = '1') THEN result := paddings( 0 ) & result(31 DOWNTO 1); END IF;
RETURN result;
END;
FUNCTION multiply(a, b: std_ulogic_vector) RETURN std_ulogic_vector IS
VARIABLE x: std_ulogic_vector (a'length + b'length - 1 DOWNTO 0);
BEGIN
x := std_ulogic_vector(signed(a) * signed(b));
RETURN x(31 DOWNTO 0);
END;
FUNCTION sign_extend(value: std_ulogic_vector; fill: std_ulogic; size: positive) RETURN std_ulogic_vector IS
VARIABLE a: std_ulogic_vector (size - 1 DOWNTO 0);
BEGIN
a(size - 1 DOWNTO value'length) := (OTHERS => fill);
a(value'length - 1 DOWNTO 0) := value;
return a;
END;
FUNCTION add(a, b : std_ulogic_vector; ci: std_ulogic) RETURN std_ulogic_vector IS
VARIABLE x : std_ulogic_vector(a'length + 1 DOWNTO 0);
BEGIN
x := (OTHERS => '0');
IF notx (a & b & ci) THEN
x := std_ulogic_vector(signed('0' & a & '1') + signed('0' & b & ci));
END IF;
RETURN x(a'length + 1 DOWNTO 1);
END;
FUNCTION increment(a : std_ulogic_vector) RETURN std_ulogic_vector IS
VARIABLE x : std_ulogic_vector(a'length-1 DOWNTO 0);
BEGIN
x := (OTHERS => '0');
IF notx (a) THEN
x := std_ulogic_vector(signed(a) + 1);
END IF;
RETURN x;
END;
END std_Pkg; |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.uart_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--=================================================================================================
entity uart_rx_vvc is
generic (
GC_DATA_WIDTH : natural := 8;
GC_INSTANCE_IDX : natural := 1;
GC_CHANNEL : t_channel := RX;
GC_UART_CONFIG : t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
uart_vvc_rx : in std_logic
);
end entity uart_rx_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of uart_rx_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX) & "," & to_upper(to_string(GC_CHANNEL));
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, GC_CHANNEL);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_uart_vvc_config(RX, GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_uart_vvc_status(RX, GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_uart_transaction_info(RX, GC_INSTANCE_IDX);
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(RX, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(RX, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean;
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
if v_cmd.operation = RECEIVE or v_cmd.operation = EXPECT then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_command_is_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
when RECEIVE =>
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_cmd.data(GC_DATA_WIDTH - 1 downto 0);
-- Call the corresponding procedure in the BFM package.
uart_receive(data_value => v_read_data(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
rx => uart_vvc_rx,
terminate_loop => terminate_current_cmd.is_active,
config => vvc_config.bfm_config,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data );
when EXPECT =>
-- Normalise address and data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "uart_expect() called with to wide data. " & add_msg_delimiter(v_cmd.msg));
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
-- Call the corresponding procedure in the BFM package.
uart_expect(data_exp => v_normalised_data,
msg => format_msg(v_cmd),
rx => uart_vvc_rx,
terminate_loop => terminate_current_cmd.is_active,
max_receptions => v_cmd.max_receptions,
timeout => v_cmd.timeout,
alert_level => v_cmd.alert_level,
config => vvc_config.bfm_config,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel);
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.bit_time;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ram IS
GENERIC
(
ADDRESS_WIDTH : integer := 4;
DATA_WIDTH : integer := 8
);
PORT
(
clock : IN std_logic;
data : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
write_address : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
read_address : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
we : IN std_logic;
q : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0)
);
END ram;
ARCHITECTURE rtl OF ram IS
TYPE RAM IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
SIGNAL ram_block : RAM;
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we = '1') THEN
ram_block(to_integer(unsigned(write_address))) <= data;
END IF;
q <= ram_block(to_integer(unsigned(read_address)));
END IF;
END PROCESS;
END rtl;
|
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- If not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : nn_constants_pkg.vhd
-- PROJECT : FPGA_NEURAL-Network
-- PACKAGE : NN_CONSTANTS_pkg
--=============================================================================
-- AUTORS(s) : Barbosa, F
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : Dec 10, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use work.fixed_pkg.all; -- ieee_proposed for compatibility version
use work.NN_TYPES_pkg.all;
--=============================================================================
-- Package declaration for NN_TYPES_pkg
--=============================================================================
package NN_CONSTANTS_pkg is
constant A_SAMPLE_INPUT : ARRAY_OF_SFIXED := (
(to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE))
);
constant INPUT_LAYER_WEIGHTS_INSTANCE : INPUT_LAYER_WEIGHTS := (
(to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE)),
(to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE), to_sfixed(1,U_SIZE,L_SIZE), to_sfixed(0,U_SIZE,L_SIZE))
);
constant HIDDEN_LAYER_WEIGHTS_INSTANCE : HIDDEN_LAYER_WEIGHTS := (
-- (to_sfixed(22.5922,U_SIZE,L_SIZE), to_sfixed(43.5699,U_SIZE,L_SIZE), to_sfixed(43.0207,U_SIZE,L_SIZE), to_sfixed(97.9748,U_SIZE,L_SIZE), to_sfixed(25.8065,U_SIZE,L_SIZE), to_sfixed(26.2212,U_SIZE,L_SIZE), to_sfixed(22.1747,U_SIZE,L_SIZE), to_sfixed(31.8778,U_SIZE,L_SIZE), to_sfixed(8.5516,U_SIZE,L_SIZE), to_sfixed(2.9220,U_SIZE,L_SIZE), to_sfixed(48.8609,U_SIZE,L_SIZE), to_sfixed(45.8849,U_SIZE,L_SIZE), to_sfixed(52.1136,U_SIZE,L_SIZE), to_sfixed(9.8712,U_SIZE,L_SIZE)),
-- (to_sfixed(17.0708,U_SIZE,L_SIZE), to_sfixed(31.1102,U_SIZE,L_SIZE), to_sfixed(18.4816,U_SIZE,L_SIZE), to_sfixed(43.8870,U_SIZE,L_SIZE), to_sfixed(40.8720,U_SIZE,L_SIZE), to_sfixed(60.2843,U_SIZE,L_SIZE), to_sfixed(11.7418,U_SIZE,L_SIZE), to_sfixed(42.4167,U_SIZE,L_SIZE), to_sfixed(26.2482,U_SIZE,L_SIZE), to_sfixed(92.8854,U_SIZE,L_SIZE), to_sfixed(57.8525,U_SIZE,L_SIZE), to_sfixed(96.3089,U_SIZE,L_SIZE), to_sfixed(23.1594,U_SIZE,L_SIZE), to_sfixed(26.1871,U_SIZE,L_SIZE)),
-- (to_sfixed(22.7664,U_SIZE,L_SIZE), to_sfixed(92.3380,U_SIZE,L_SIZE), to_sfixed(90.4881,U_SIZE,L_SIZE), to_sfixed(11.1119,U_SIZE,L_SIZE), to_sfixed(59.4896,U_SIZE,L_SIZE), to_sfixed(71.1216,U_SIZE,L_SIZE), to_sfixed(29.6676,U_SIZE,L_SIZE), to_sfixed(50.7858,U_SIZE,L_SIZE), to_sfixed(80.1015,U_SIZE,L_SIZE), to_sfixed(73.0331,U_SIZE,L_SIZE), to_sfixed(23.7284,U_SIZE,L_SIZE), to_sfixed(54.6806,U_SIZE,L_SIZE), to_sfixed(48.8898,U_SIZE,L_SIZE), to_sfixed(33.5357,U_SIZE,L_SIZE))
(to_sfixed(1.5122,U_SIZE,L_SIZE), to_sfixed(0.6097,U_SIZE,L_SIZE), to_sfixed(0.9763,U_SIZE,L_SIZE), to_sfixed(-0.8762,U_SIZE,L_SIZE), to_sfixed(0.1932,U_SIZE,L_SIZE), to_sfixed(0.0908,U_SIZE,L_SIZE), to_sfixed(0.4391,U_SIZE,L_SIZE), to_sfixed(-0.0864,U_SIZE,L_SIZE), to_sfixed(-0.5696,U_SIZE,L_SIZE), to_sfixed(0.5749,U_SIZE,L_SIZE), to_sfixed(-0.4827,U_SIZE,L_SIZE), to_sfixed(0.6270,U_SIZE,L_SIZE), to_sfixed(1.7584,U_SIZE,L_SIZE), to_sfixed(0.5553,U_SIZE,L_SIZE)),
(to_sfixed(1.0114,U_SIZE,L_SIZE), to_sfixed(0.9375,U_SIZE,L_SIZE), to_sfixed(0.3523,U_SIZE,L_SIZE), to_sfixed(0.4041,U_SIZE,L_SIZE), to_sfixed(1.5389,U_SIZE,L_SIZE), to_sfixed(-0.9106,U_SIZE,L_SIZE), to_sfixed(-2.2535,U_SIZE,L_SIZE), to_sfixed(-0.0119,U_SIZE,L_SIZE), to_sfixed(-0.7724,U_SIZE,L_SIZE), to_sfixed(2.9647,U_SIZE,L_SIZE), to_sfixed(-1.4867,U_SIZE,L_SIZE), to_sfixed(-2.3596,U_SIZE,L_SIZE), to_sfixed(0.8667,U_SIZE,L_SIZE), to_sfixed(-1.2566,U_SIZE,L_SIZE)),
(to_sfixed(-0.7440,U_SIZE,L_SIZE), to_sfixed(-0.2641,U_SIZE,L_SIZE), to_sfixed(-1.0074,U_SIZE,L_SIZE), to_sfixed(0.7037,U_SIZE,L_SIZE), to_sfixed(-0.0806,U_SIZE,L_SIZE), to_sfixed(0.1825,U_SIZE,L_SIZE), to_sfixed(-0.3537,U_SIZE,L_SIZE), to_sfixed(0.8026,U_SIZE,L_SIZE), to_sfixed(-0.4890,U_SIZE,L_SIZE), to_sfixed(0.2165,U_SIZE,L_SIZE), to_sfixed(0.1458,U_SIZE,L_SIZE), to_sfixed(-0.8806,U_SIZE,L_SIZE), to_sfixed(-1.3739,U_SIZE,L_SIZE), to_sfixed(0.5034,U_SIZE,L_SIZE))
);
constant OUTPUT_LAYER_WEIGHTS_INSTANCE : OUTPUT_LAYER_WEIGHTS := (
-- (to_sfixed(62.4060,U_SIZE,L_SIZE), to_sfixed(36.7437,U_SIZE,L_SIZE), to_sfixed(88.5168,U_SIZE,L_SIZE), to_sfixed(67.9728,U_SIZE,L_SIZE)),
-- (to_sfixed(67.9136,U_SIZE,L_SIZE), to_sfixed(98.7982,U_SIZE,L_SIZE), to_sfixed(91.3287,U_SIZE,L_SIZE), to_sfixed(13.6553,U_SIZE,L_SIZE)),
-- (to_sfixed(39.5515,U_SIZE,L_SIZE), to_sfixed(3.7739,U_SIZE,L_SIZE), to_sfixed(79.6184,U_SIZE,L_SIZE), to_sfixed(72.1227,U_SIZE,L_SIZE))
(to_sfixed(1.9494,U_SIZE,L_SIZE), to_sfixed(-2.3810,U_SIZE,L_SIZE), to_sfixed(-1.1301,U_SIZE,L_SIZE), to_sfixed(0.0489,U_SIZE,L_SIZE)),
(to_sfixed(-2.9926,U_SIZE,L_SIZE), to_sfixed(-2.1257,U_SIZE,L_SIZE), to_sfixed(1.5242,U_SIZE,L_SIZE), to_sfixed(-0.1979,U_SIZE,L_SIZE)),
(to_sfixed(-0.8011,U_SIZE,L_SIZE), to_sfixed(4.6621,U_SIZE,L_SIZE), to_sfixed(1.2713,U_SIZE,L_SIZE), to_sfixed(-0.2438,U_SIZE,L_SIZE))
);
constant FIXED_WEIGHTS_MATRIX_INSTANCE: FIXED_WEIGHTS_MATRIX
:= (
INPUT_LAYER => INPUT_LAYER_WEIGHTS_INSTANCE,
HIDDEN_LAYER => HIDDEN_LAYER_WEIGHTS_INSTANCE,
OUTPUT_LAYER => OUTPUT_LAYER_WEIGHTS_INSTANCE
);
end;
--=============================================================================
-- package body declaration
--=============================================================================
package body NN_CONSTANTS_pkg is
end package body; |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity hls_contrast_stretch_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
-- user signals
height :out STD_LOGIC_VECTOR(15 downto 0);
width :out STD_LOGIC_VECTOR(15 downto 0);
min :out STD_LOGIC_VECTOR(7 downto 0);
max :out STD_LOGIC_VECTOR(7 downto 0)
);
end entity hls_contrast_stretch_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : reserved
-- 0x04 : reserved
-- 0x08 : reserved
-- 0x0c : reserved
-- 0x10 : Data signal of height
-- bit 15~0 - height[15:0] (Read/Write)
-- others - reserved
-- 0x14 : reserved
-- 0x18 : Data signal of width
-- bit 15~0 - width[15:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- 0x20 : Data signal of min
-- bit 7~0 - min[7:0] (Read/Write)
-- others - reserved
-- 0x24 : reserved
-- 0x28 : Data signal of max
-- bit 7~0 - max[7:0] (Read/Write)
-- others - reserved
-- 0x2c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of hls_contrast_stretch_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_HEIGHT_DATA_0 : INTEGER := 16#10#;
constant ADDR_HEIGHT_CTRL : INTEGER := 16#14#;
constant ADDR_WIDTH_DATA_0 : INTEGER := 16#18#;
constant ADDR_WIDTH_CTRL : INTEGER := 16#1c#;
constant ADDR_MIN_DATA_0 : INTEGER := 16#20#;
constant ADDR_MIN_CTRL : INTEGER := 16#24#;
constant ADDR_MAX_DATA_0 : INTEGER := 16#28#;
constant ADDR_MAX_CTRL : INTEGER := 16#2c#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_height : UNSIGNED(15 downto 0) := (others => '0');
signal int_width : UNSIGNED(15 downto 0) := (others => '0');
signal int_min : UNSIGNED(7 downto 0) := (others => '0');
signal int_max : UNSIGNED(7 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_HEIGHT_DATA_0 =>
rdata_data <= RESIZE(int_height(15 downto 0), 32);
when ADDR_WIDTH_DATA_0 =>
rdata_data <= RESIZE(int_width(15 downto 0), 32);
when ADDR_MIN_DATA_0 =>
rdata_data <= RESIZE(int_min(7 downto 0), 32);
when ADDR_MAX_DATA_0 =>
rdata_data <= RESIZE(int_max(7 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
height <= STD_LOGIC_VECTOR(int_height);
width <= STD_LOGIC_VECTOR(int_width);
min <= STD_LOGIC_VECTOR(int_min);
max <= STD_LOGIC_VECTOR(int_max);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_HEIGHT_DATA_0) then
int_height(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_height(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_WIDTH_DATA_0) then
int_width(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_width(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_MIN_DATA_0) then
int_min(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_min(7 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_MAX_DATA_0) then
int_max(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_max(7 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
--
-- MIT License
--
-- Copyright (c) 2017 Mathias Helsen, Arne Vansteenkiste
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progMem is
port(
instrOutput : out std_logic_vector(31 downto 0);
instrAddress: in std_logic_vector(31 downto 0);
clk : in std_logic
);
end entity;
architecture default of progMem is
type regFileType is array(3 downto 0) of std_logic_vector(31 downto 0);
begin
process(clk) begin
if (clk'event and clk='0') then
case instrAddress is
|
entity arith1 is
end entity;
architecture test of arith1 is
begin
proc1: process is
variable x, y : integer;
begin
x := 3;
y := 12;
wait for 1 ns;
assert x + y = 15;
assert x - y = -9;
assert x * y = 36;
assert x / 12 = 0;
assert x = 3;
assert y = 12;
assert x /= y;
assert x < y;
assert y > x;
assert x <= y;
assert y >= x;
assert (- x) = -3;
assert x ** y = 531441;
x := -34;
wait for 1 ns;
assert abs x = 34;
assert abs y = 12;
y := 3;
wait for 1 ns;
assert 5 mod y = 2;
assert 5 rem y = 2;
assert (-5) rem y = -2;
assert (-5) mod 3 = 1;
assert (-5) mod y = 1;
y := -8;
wait for 1 ns;
assert (-512) mod (-8) = 0;
assert (-512) mod y = 0;
assert (-510) mod (-8) = -6;
assert (-510) mod y = -6;
assert x = +x;
wait;
end process;
end architecture;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - Memory Controller
--
-- project: ReconOS
-- author: Christoph R??thing, University of Paderborn
-- description: A memory controller connecting the memory fifos with
-- the axi bus of the system.
--
-- ======================================================================
<<reconos_preproc>>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axi_master_burst_v2_0_7;
use axi_master_burst_v2_0_7.axi_master_burst;
entity reconos_memif_memory_controller is
--
-- Generic definitions
--
-- C_M_AXI_ - @see axi bus
--
-- C_MAX_BURST_LEN - maximal allowed burst length
--
-- C_MEMIF_DATA_WIDTH - width of the memif
--
generic (
C_M_AXI_ADDR_WIDTH : integer := 32;
C_M_AXI_DATA_WIDTH : integer := 32;
C_MAX_BURST_LEN : integer := 64;
C_MEMIF_DATA_WIDTH : integer := 32
);
--
-- Port definitions
--
-- MEMIF_Hwt2Mem_/MEMIF_Mem2Hwt_ - fifo signal inputs
--
-- M_AXI_ - @see axi bus
--
port (
MEMIF_Hwt2Mem_In_Data : in std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
MEMIF_Hwt2Mem_In_Empty : in std_logic;
MEMIF_Hwt2Mem_In_RE : out std_logic;
MEMIF_Mem2Hwt_In_Data : out std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
MEMIF_Mem2Hwt_In_Full : in std_logic;
MEMIF_Mem2Hwt_In_WE : out std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_ARVALID : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_RREADY : out std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH - 1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_AWVALID : out std_logic;
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_WREADY : in std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH - 1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH / 8 - 1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_BVALID : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_ARUSER : out std_logic_vector(4 downto 0);
DEBUG : out std_logic_vector(67 downto 0)
);
end entity reconos_memif_memory_controller;
architecture imp of reconos_memif_memory_controller is
-- Declare port attributes for the Vivado IP Packager
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of M_AXI_ACLK: SIGNAL is "xilinx.com:signal:clock:1.0 M_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER of M_AXI_ACLK: SIGNAL is "ASSOCIATED_BUSIF MEMIF_Hwt2Mem_In:MEMIF_Mem2Hwt_In:M_AXI";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Hwt2Mem_In_Data: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 MEMIF_Hwt2Mem_In FIFO_S_Data";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Hwt2Mem_In_Empty: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 MEMIF_Hwt2Mem_In FIFO_S_Empty";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Hwt2Mem_In_RE: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 MEMIF_Hwt2Mem_In FIFO_S_RE";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Mem2Hwt_In_Data: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 MEMIF_Mem2Hwt_In FIFO_M_Data";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Mem2Hwt_In_Full: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 MEMIF_Mem2Hwt_In FIFO_M_Full";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Mem2Hwt_In_WE: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 MEMIF_Mem2Hwt_In FIFO_M_WE";
--
-- Internal ipif signals
--
-- @see axi_master_burst_v1_00_a
--
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_mst_addr : std_logic_vector(31 downto 0);
signal ip2bus_mst_be : std_logic_vector(3 downto 0);
signal ip2bus_mst_length : std_logic_vector(11 downto 0);
signal ip2bus_mst_type : std_logic;
signal ip2bus_mst_lock : std_logic;
signal ip2bus_mst_reset : std_logic;
signal bus2ip_mst_cmdack : std_logic;
signal bus2ip_mst_cmplt : std_logic;
signal bus2ip_mst_error : std_logic;
signal ip2bus_mstrd_req : std_logic;
signal bus2ip_mstrd_d : std_logic_vector(31 downto 0);
signal bus2ip_mstrd_rem : std_logic_vector(3 downto 0);
signal bus2ip_mstrd_sof_n : std_logic;
signal bus2ip_mstrd_eof_n : std_logic;
signal bus2ip_mstrd_src_rdy_n : std_logic;
signal bus2ip_mstrd_src_dsc_n : std_logic;
signal ip2bus_mstrd_dst_rdy_n : std_logic;
signal ip2bus_mstrd_dst_dsc_n : std_logic;
signal ip2bus_mstwr_req : std_logic;
signal ip2bus_mstwr_d : std_logic_vector(31 downto 0);
signal ip2bus_mstwr_rem : std_logic_vector(3 downto 0);
signal ip2bus_mstwr_sof_n : std_logic;
signal ip2bus_mstwr_eof_n : std_logic;
signal ip2bus_mstwr_src_rdy_n : std_logic;
signal ip2bus_mstwr_src_dsc_n : std_logic;
signal bus2ip_mstwr_dst_rdy_n : std_logic;
signal bus2ip_mstwr_dst_dsc_n : std_logic;
signal MEMIF_Hwt2Mem_In_Data_d : std_logic_vector(31 downto 0);
signal MEMIF_Hwt2Mem_In_Empty_d : std_logic;
signal MEMIF_Hwt2Mem_In_RE_d : std_logic;
signal MEMIF_Mem2Hwt_In_Data_d : std_logic_vector(31 downto 0);
signal MEMIF_Mem2Hwt_In_Full_d : std_logic;
signal MEMIF_Mem2Hwt_In_WE_d : std_logic;
begin
-- == Static assignemnts of signals ===================================
M_AXI_AWCACHE <= (others => '1');
M_AXI_ARCACHE <= (others => '1');
M_AXI_AWUSER <= (others => '1');
M_AXI_ARUSER <= (others => '1');
bus2ip_clk <= M_AXI_ACLK;
bus2ip_resetn <= M_AXI_ARESETN;
MEMIF_Hwt2Mem_In_Data_d <= MEMIF_Hwt2Mem_In_Data;
MEMIF_Hwt2Mem_In_Empty_d <= MEMIF_Hwt2Mem_In_Empty;
MEMIF_Hwt2Mem_In_RE <= MEMIF_Hwt2Mem_In_RE_d;
MEMIF_Mem2Hwt_In_Data <= MEMIF_Mem2Hwt_In_Data_d;
MEMIF_Mem2Hwt_In_Full_d <= MEMIF_Mem2Hwt_In_Full;
MEMIF_Mem2Hwt_In_WE <= MEMIF_Mem2Hwt_In_WE_d;
DEBUG(67 downto 36) <= MEMIF_Hwt2Mem_In_Data_d;
DEBUG(35) <= MEMIF_Hwt2Mem_In_Empty_d;
DEBUG(34) <= MEMIF_Hwt2Mem_In_RE_d;
DEBUG(33 downto 2) <= MEMIF_Mem2Hwt_In_Data_d;
DEBUG(1) <= MEMIF_Mem2Hwt_In_Full_d;
DEBUG(0) <= MEMIF_Mem2Hwt_In_WE_d;
-- == Instantiation of components =====================================
--
-- Instantiation of axi_master_burst_v1_00_a
--
-- @see ds844_axi_master_burst.pdf
--
ipif : entity axi_master_burst_v2_0_7.axi_master_burst
generic map (
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_MAX_BURST_LEN => C_MAX_BURST_LEN
)
port map (
m_axi_aclk => M_AXI_ACLK,
m_axi_aresetn => M_AXI_ARESETN,
m_axi_arready => M_AXI_ARREADY,
m_axi_arvalid => M_AXI_ARVALID,
m_axi_araddr => M_AXI_ARADDR,
m_axi_arlen => M_AXI_ARLEN,
m_axi_arsize => M_AXI_ARSIZE,
m_axi_arburst => M_AXI_ARBURST,
m_axi_arprot => M_AXI_ARPROT,
m_axi_rready => M_AXI_RREADY,
m_axi_rvalid => M_AXI_RVALID,
m_axi_rdata => M_AXI_RDATA,
m_axi_rresp => M_AXI_RRESP,
m_axi_rlast => M_AXI_RLAST,
m_axi_awready => M_AXI_AWREADY,
m_axi_awvalid => M_AXI_AWVALID,
m_axi_awaddr => M_AXI_AWADDR,
m_axi_awlen => M_AXI_AWLEN,
m_axi_awsize => M_AXI_AWSIZE,
m_axi_awburst => M_AXI_AWBURST,
m_axi_awprot => M_AXI_AWPROT,
m_axi_wready => M_AXI_WREADY,
m_axi_wvalid => M_AXI_WVALID,
m_axi_wdata => M_AXI_WDATA,
m_axi_wstrb => M_AXI_WSTRB,
m_axi_wlast => M_AXI_WLAST,
m_axi_bready => M_AXI_BREADY,
m_axi_bvalid => M_AXI_BVALID,
m_axi_bresp => M_AXI_BRESP,
ip2bus_mst_addr => ip2bus_mst_addr,
ip2bus_mst_be => ip2bus_mst_be,
ip2bus_mst_length => ip2bus_mst_length,
ip2bus_mst_type => ip2bus_mst_type,
ip2bus_mst_lock => ip2bus_mst_lock,
ip2bus_mst_reset => ip2bus_mst_reset,
bus2ip_mst_cmdack => bus2ip_mst_cmdack,
bus2ip_mst_cmplt => bus2ip_mst_cmplt,
bus2ip_mst_error => bus2ip_mst_error,
ip2bus_mstrd_req => ip2bus_mstrd_req,
bus2ip_mstrd_d => bus2ip_mstrd_d,
bus2ip_mstrd_rem => bus2ip_mstrd_rem,
bus2ip_mstrd_sof_n => bus2ip_mstrd_sof_n,
bus2ip_mstrd_eof_n => bus2ip_mstrd_eof_n,
bus2ip_mstrd_src_rdy_n => bus2ip_mstrd_src_rdy_n,
bus2ip_mstrd_src_dsc_n => bus2ip_mstrd_src_dsc_n,
ip2bus_mstrd_dst_rdy_n => ip2bus_mstrd_dst_rdy_n,
ip2bus_mstrd_dst_dsc_n => ip2bus_mstrd_dst_dsc_n,
ip2bus_mstwr_req => ip2bus_mstwr_req,
ip2bus_mstwr_d => ip2bus_mstwr_d,
ip2bus_mstwr_rem => ip2bus_mstwr_rem,
ip2bus_mstwr_sof_n => ip2bus_mstwr_sof_n,
ip2bus_mstwr_eof_n => ip2bus_mstwr_eof_n,
ip2bus_mstwr_src_rdy_n => ip2bus_mstwr_src_rdy_n,
ip2bus_mstwr_src_dsc_n => ip2bus_mstwr_src_dsc_n,
bus2ip_mstwr_dst_rdy_n => bus2ip_mstwr_dst_rdy_n,
bus2ip_mstwr_dst_dsc_n => bus2ip_mstwr_dst_dsc_n
);
--
-- Instantiation of user logic
--
-- The user logic includes the actual implementation of the memory
-- controller.
--
ul : entity work.reconos_memif_memory_controller_user_logic
port map (
MEMIF_Hwt2Mem_In_Data => MEMIF_Hwt2Mem_In_Data_d,
MEMIF_Hwt2Mem_In_Empty => MEMIF_Hwt2Mem_In_Empty_d,
MEMIF_Hwt2Mem_In_RE => MEMIF_Hwt2Mem_In_RE_d,
MEMIF_Mem2Hwt_In_Data => MEMIF_Mem2Hwt_In_Data_d,
MEMIF_Mem2Hwt_In_Full => MEMIF_Mem2Hwt_In_Full_d,
MEMIF_Mem2Hwt_In_WE => MEMIF_Mem2Hwt_In_WE_d,
BUS2IP_Clk => bus2ip_clk,
BUS2IP_Resetn => bus2ip_resetn,
IP2BUS_Mst_Addr => ip2bus_mst_addr,
IP2BUS_Mst_BE => ip2bus_mst_be,
IP2BUS_Mst_Length => ip2bus_mst_length,
IP2BUS_Mst_Type => ip2bus_mst_type,
IP2BUS_Mst_Lock => ip2bus_mst_lock,
IP2BUS_Mst_Reset => ip2bus_mst_reset,
BUS2IP_Mst_CmdAck => bus2ip_mst_cmdack,
BUS2IP_Mst_Cmplt => bus2ip_mst_cmplt,
BUS2IP_Mst_Error => bus2ip_mst_error,
IP2BUS_MstRd_Req => ip2bus_mstrd_req,
BUS2IP_MstRd_D => bus2ip_mstrd_d,
BUS2IP_MstRd_Rem => bus2ip_mstrd_rem,
BUS2IP_MstRd_Sof_N => bus2ip_mstrd_sof_n,
BUS2IP_MstRd_Eof_N => bus2ip_mstrd_eof_n,
BUS2IP_MstRd_Src_Rdy_N => bus2ip_mstrd_src_rdy_n,
BUS2IP_MstRd_Src_Dsc_N => bus2ip_mstrd_src_dsc_n,
IP2BUS_MstRd_Dst_Rdy_N => ip2bus_mstrd_dst_rdy_n,
IP2BUS_MstRd_Dst_Dsc_N => ip2bus_mstrd_dst_dsc_n,
IP2BUS_MstWr_Req => ip2bus_mstwr_req,
IP2BUS_MstWr_D => ip2bus_mstwr_d,
IP2BUS_MstWr_Rem => ip2bus_mstwr_rem,
IP2BUS_MstWr_Sof_N => ip2bus_mstwr_sof_n,
IP2BUS_MstWr_Eof_N => ip2bus_mstwr_eof_n,
IP2BUS_MstWr_Src_Rdy_N => ip2bus_mstwr_src_rdy_n,
IP2BUS_MstWr_Src_Dsc_N => ip2bus_mstwr_src_dsc_n,
BUS2IP_MstWr_Dst_Rdy_N => bus2ip_mstwr_dst_rdy_n,
BUS2IP_MstWr_Dst_Dsc_N => bus2ip_mstwr_dst_dsc_n
);
end architecture imp; |
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_unsigned.all;
entity nes2bbb_testbench is
end nes2bbb_testbench;
architecture stimulus of nes2bbb_testbench is
constant powerup_time : time := 1500 ns;
constant reset_time : time := 1800 ns;
--DE1 base clock = 50 MHz
constant base_clock_time : time := 20 ns;
--i2c normal clock speed 100 KHz
constant i2c_clock_time : time := 10 us;
--i2c clock timing..
constant i2c_clk_0 : std_logic_vector(1 downto 0) := "00";
constant i2c_clk_1 : std_logic_vector(1 downto 0) := "01";
constant i2c_clk_2 : std_logic_vector(1 downto 0) := "10";
constant i2c_clk_3 : std_logic_vector(1 downto 0) := "11";
---https://wiki.nesdev.com/w/index.php/Clock_rate
--nes cpu clock = 1.789773 MHz
constant nes_clock_time : time := 558 ns;
constant bus_cycle : integer := 3;
---fifo status register
---bit
---7 always 0
---6 always 0
---5 read fifo full
---4 read fifo empty
---3 always 0
---2 always 0
---1 write fifo full
---0 write fifo empty
constant wfifo_empty_bit : integer := 0;
constant wfifo_full_bit : integer := 1;
constant rfifo_empty_bit : integer := 4;
constant rfifo_full_bit : integer := 5;
constant i2c_read : std_logic := '1';
constant i2c_write : std_logic := '0';
component duper_cartridge
port (
pi_reset_n : in std_logic;
pi_base_clk : in std_logic;
--nes side
pi_phi2 : in std_logic;
pi_prg_ce_n : in std_logic;
pi_prg_r_nw : in std_logic;
pi_prg_addr : in std_logic_vector(14 downto 0);
pio_prg_data : inout std_logic_vector(7 downto 0);
pi_chr_ce_n : in std_logic;
pi_chr_oe_n : in std_logic;
pi_chr_we_n : in std_logic;
pi_chr_addr : in std_logic_vector(12 downto 0);
po_chr_data : out std_logic_vector(7 downto 0);
--i2c side
pi_i2c_scl : in std_logic;
pio_i2c_sda : inout std_logic;
--bbb gpio
po_nes_f_full : out std_logic;
po_bbb_f_empty : out std_logic;
po_dbg_cnt : out std_logic_vector (63 downto 0)
);
end component ;
signal reset_input : std_logic;
signal base_clk : std_logic;
signal phi2 : std_logic;
signal prg_ce_n : std_logic;
signal prg_r_nw : std_logic;
signal prg_addr : std_logic_vector(14 downto 0);
signal prg_data : std_logic_vector(7 downto 0);
signal chr_ce_n : std_logic;
signal chr_oe_n : std_logic;
signal chr_we_n : std_logic;
signal chr_addr : std_logic_vector(12 downto 0);
signal chr_data : std_logic_vector(7 downto 0);
signal i2c_scl : std_logic;
signal i2c_scl_x4 : std_logic;
signal i2c_scl_type : std_logic_vector(1 downto 0);
signal i2c_sda : std_logic;
signal nes_f_full : std_logic;
signal bbb_f_empty : std_logic;
signal dbg_cnt : std_logic_vector (63 downto 0);
signal reg_rom_data : std_logic_vector(7 downto 0);
signal reg_bbb_data : std_logic_vector (7 downto 0);
signal start_scl : std_logic;
signal step_cnt : integer range 0 to 65535 := 0;
signal stage_cnt : integer range 0 to 65535 := 0;
signal i2c_step_cnt : integer range 0 to 65535 := 0;
signal addr_index : integer range 0 to 65535 := 0;
signal data_index : integer range 0 to 65535 := 0;
begin
---chrrom side disabled..
chr_ce_n <= 'Z';
chr_oe_n <= 'Z';
chr_we_n <= 'Z';
chr_addr <= (others => 'Z');
chr_data <= (others => 'Z');
sim_board : duper_cartridge port map (
reset_input,
base_clk,
phi2,
prg_ce_n,
prg_r_nw,
prg_addr,
prg_data,
chr_ce_n,
chr_oe_n,
chr_we_n,
chr_addr,
chr_data,
i2c_scl,
i2c_sda,
nes_f_full,
bbb_f_empty,
dbg_cnt);
--- input reset.
reset_p: process
begin
reset_input <= '1';
wait for powerup_time;
reset_input <= '0';
wait for reset_time;
reset_input <= '1';
wait;
end process;
--- generate base clock.
clock_p1 : process
begin
base_clk <= '1';
wait for base_clock_time / 2;
base_clk <= '0';
wait for base_clock_time / 2;
end process;
--- phi clock.
clock_phi : process
begin
phi2 <= '1';
wait for nes_clock_time / 2;
phi2 <= '0';
wait for nes_clock_time / 2;
end process;
--- i2c base clock.
clock_i2c_base : process
begin
i2c_scl_x4 <= '1';
wait for i2c_clock_time / 8;
i2c_scl_x4 <= '0';
wait for i2c_clock_time / 8;
end process;
--- i2c clock.
clock_i2c : process (reset_input, i2c_scl_x4)
begin
if (reset_input = '0') then
i2c_scl_type <= i2c_clk_0;
i2c_scl <= '1';
elsif (rising_edge(i2c_scl_x4)) then
i2c_scl_type <= i2c_scl_type + 1;
if(start_scl = '1') then
if (i2c_scl_type = i2c_clk_0) then
i2c_scl <= '1';
elsif (i2c_scl_type = i2c_clk_2) then
i2c_scl <= '0';
end if;
else
i2c_scl <= '1';
end if;
end if;
end process;
--- cpu bus emulation...
emu_cpu : process (reset_input, phi2)
procedure mem_read
(
addr : in std_logic_vector (14 downto 0)
) is
begin
prg_ce_n <= '0';
prg_r_nw <= '1';
prg_addr <= addr;
prg_data <= (others => 'Z');
end;
procedure bus_wait is
begin
prg_ce_n <= '1';
prg_r_nw <= 'Z';
prg_addr <= (others => 'Z');
prg_data <= (others => 'Z');
end;
begin
if (reset_input = '0') then
stage_cnt <= 0;
step_cnt <= 0;
elsif (rising_edge(phi2)) then
---stage 0: initialize....
if (stage_cnt = 0) then
if (step_cnt = 10) then
stage_cnt <= stage_cnt + 1;
step_cnt <= 0;
else
step_cnt <= step_cnt + 1;
end if;
---stage 1: rom read.....
elsif (stage_cnt = 1) then
if (step_cnt < 500) then
if (step_cnt mod bus_cycle = 0) then
--check status.
mem_read (conv_std_logic_vector(16#fff8#, 15));
else
bus_wait;
end if;
elsif (step_cnt < 2000) then
if (step_cnt mod bus_cycle = 0) then
--read fifo.
mem_read (conv_std_logic_vector(16#fff9#, 15));
else
bus_wait;
end if;
end if;
step_cnt <= step_cnt + 1;
end if;
end if;
end process;
--- i2c bus emulation...
i2c_cpu : process (reset_input, i2c_scl_x4)
procedure increment_cnt is
begin
if (i2c_scl_type = i2c_clk_0) then
i2c_step_cnt <= i2c_step_cnt + 1;
end if;
end;
procedure start_seq is
begin
if (i2c_scl_type = i2c_clk_1) then
i2c_sda <= '0';
end if;
end;
procedure output_addr
(
i : in integer;
addr : in std_logic_vector (6 downto 0)
) is
begin
if (i2c_scl_type = i2c_clk_3) then
i2c_sda <= addr(i);
end if;
end;
procedure set_rw
(
rw : in std_logic
) is
begin
if (i2c_scl_type = i2c_clk_3) then
i2c_sda <= rw;
end if;
end;
procedure ack_wait is
begin
if (i2c_scl_type = i2c_clk_3) then
i2c_sda <= 'Z';
end if;
end;
procedure output_data
(
i : in integer;
data : in std_logic_vector (7 downto 0)
) is
begin
if (i2c_scl_type = i2c_clk_3 and (i >= 0 and i < 8)) then
i2c_sda <= data(i);
end if;
end;
begin
if (reset_input = '0') then
i2c_step_cnt <= 0;
i2c_sda <= '1';
start_scl <= '0';
addr_index <= 0;
data_index <= 0;
elsif (rising_edge(i2c_scl_x4)) then
---stage 1: i2c read.....
if (stage_cnt = 1) then
increment_cnt;
if (i2c_step_cnt < 3) then
start_scl <= '1';
elsif (i2c_step_cnt = 3) then
addr_index <= i2c_step_cnt + 1;
elsif (i2c_step_cnt = addr_index) then
--start up seq...
start_seq;
--set i2c addr...
--addr output with write.....
--0x44 = 100 0101.
output_addr(6 - i2c_step_cnt + addr_index, conv_std_logic_vector(16#44#, 7));
elsif (i2c_step_cnt <= addr_index + 6) then
output_addr(6 - i2c_step_cnt + addr_index, conv_std_logic_vector(16#44#, 7));
elsif (i2c_step_cnt = addr_index + 7) then
set_rw(i2c_write);
elsif (i2c_step_cnt = addr_index + 8) then
--wait ack...
ack_wait;
data_index <= i2c_step_cnt + 1;
elsif (i2c_step_cnt = data_index + 9) then
if (i2c_scl_type = i2c_clk_2) then
---infinete repeat...
data_index <= data_index + 9;
end if;
elsif (i2c_step_cnt < data_index + 9) then
output_data(7 - i2c_step_cnt + data_index, conv_std_logic_vector(data_index mod 256, 8));
if (i2c_step_cnt = data_index + 8) then
ack_wait;
end if;
end if;
end if;
end if;
end process;
end stimulus;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:24:40 11/30/2015
-- Design Name:
-- Module Name: FSM_Ultrasonic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.PKG_ROBOT_SUMO.all;
entity FSM_Ultrasonic is
port (
in_pres_state : in ultrasonic_state_values;
in_rx : in STD_LOGIC;
out_next_state: out ultrasonic_state_values;
state_duration : out integer);
end FSM_Ultrasonic;
architecture Behavioral of FSM_Ultrasonic is
-- All times are expressed in micro-seconds
constant tStartPulse : integer := 5;
constant tWaitForNewStart : integer := 1_000_000;
begin
-- Proceso que describe el modulo "Next State Logic"
--agrupar las seniales de entrada
fsm : process (in_pres_state, in_rx)
begin
case (in_pres_state) is
-- ST0
when StartPulse =>
out_next_state <= WaitForResponse;
state_duration <= tStartPulse;
-- ST1
when WaitForResponse =>
if in_rx = '1' then
out_next_state <= UltraSonicResponse;
else
out_next_state <= WaitForResponse;
end if;
state_duration <= 1;
-- ST2
when UltraSonicResponse =>
if in_rx = '0' then
out_next_state <= WaitForNewStart;
else
out_next_state <= UltraSonicResponse;
end if;
state_duration <= 1;
-- ST3
when WaitForNewStart =>
out_next_state <= StartPulse;
state_duration <= tWaitForNewStart;
when others =>
out_next_state <= WaitForResponse;
state_duration <= tStartPulse;
end case;
end process fsm;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Integrates all componentes to provide a synthesizable application.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library SPI_Interface;
library SRAM_Controller;
use SPI_Interface.globals.all;
use work.FunctionGenerator_Declarations.all;
use work.ModulatedGenerator_Declarations.all;
entity Main is
generic
(
-- The width of the shared SRAM address and DAC data.
ram_addr_dac_data_width: natural := 19;
-- The width of the SRAM address and data.
ram_address_width: natural := 19;
ram_data_width: natural := 8;
-- The width of the DAC data.
dac_data_width: natural := modulated_generator_sample_width;
-- The number of DDS generators.
number_of_dds_generators: natural := 4
);
port
(
-- The system clock.
sysclk: in std_logic;
-- The internal SPI interface.
f_sck: in std_logic; --
f_rs: in std_logic; -- low during transmission
f_ds: in std_logic; -- low during transmission
f_mosi: in std_logic;
f_miso: out std_logic;
-- The external SPI interface.
ext_sck: in std_logic; --
ext_rs: in std_logic; -- low during transmission
ext_ds: in std_logic; -- low during transmission
ext_mosi: in std_logic;
ext_miso: out std_logic;
-- The test LED output.
test_led: out std_logic;
-- The external 1-bit width input.
external_in: in std_logic;
-- The DDS generators synchronization outputs.
dds_sync_out: out std_logic_vector(number_of_dds_generators-1 downto 0);
-- The pulse generator output.
pulse_out: out std_logic;
-- The SRAM data and control signals.
ram_we_n: out std_logic;
ram_oe_n: out std_logic;
-- The shared output for SRAM address and DAC data.
ram_addr_dac_data: out unsigned(ram_addr_dac_data_width-1 downto 0);
ram_data: inout std_logic_vector(ram_data_width-1 downto 0);
-- The DAC control signals.
dac_clk: out std_logic;
dac_channel_select: out std_logic;
dac_write_n: out std_logic
);
end entity;
architecture stdarch of Main is
-- Configuration constants
-----------------------------------------------------------------------------
-- SPI interface.
constant use_internal_spi: boolean := true;
constant use_external_spi: boolean := false;
constant address_width: positive := 5; -- max. 8 (for addresses 0..255)
constant number_of_data_buffers: positive := 2**address_width;
-- Signal generators and counter.
constant dds_generator_lookup_table_phase_width: natural := 12;
constant pulse_generator_counter_width: natural := 32;
constant dds_generator_phase_width: natural := modulated_generator_phase_width;
constant dds_generator_level_width: natural := modulated_generator_level_width;
constant dds_generator_sample_width: natural := dac_data_width;
constant dac_source_selector_width: natural := 4;
-- SRAM controller.
constant num_of_total_wait_states: natural := 9; -- 90ns @ 100MHz (min 70ns)
constant num_of_write_pulse_wait_states: natural := 6; -- 60ns @ 100MHz (min 50ns)
constant num_of_wait_states_before_write_after_read: natural := 4; -- 40ns @ 100MHz (min 30ns)
-- SPI sub-address constants
-----------------------------------------------------------------------------
type integer_vector is array (natural range <>) of integer;
-- Receiver.
constant dds_generator_base_subaddr: integer_vector(0 to number_of_dds_generators-1)
:= (0=>8, 1=>12, 2=>16, 3=>20); -- need n..n+2 each
constant peripheral_configuration_subaddr: integer := 7;
constant universal_counter_config_subaddr: integer := 1;
constant pulse_generator_high_duration_subaddr: integer := 6;
constant pulse_generator_low_duration_subaddr: integer := 5;
constant scope_config_subaddr: integer := 25;
-- Transmitter.
constant universal_counter_state_subaddr: integer := 2;
constant universal_counter_value_subaddr: integer := 3;
-- Bidirectional.
constant sram_subaddr: integer := 24;
-- Signals
-----------------------------------------------------------------------------
-- Clocks
signal clk_50mhz: std_logic;
signal clk_100mhz: std_logic;
-- SPI interfaces
type spi_in_type is record
mosi: std_logic;
sclk: std_logic;
ss_address: std_logic;
ss_data: std_logic;
end record;
signal selected_spi_in, internal_spi_in, external_spi_in, inactive_spi_in: spi_in_type :=
(
-- Initialize to proper idle values.
mosi => '0',
sclk => '1',
ss_address => '1',
ss_data => '1'
);
signal miso: std_logic;
-- DDS signal generators
signal dds_generator_configs_raw: data_buffer_vector(number_of_dds_generators-1 downto 0);
signal dds_generator_configs: modulated_generator_config_vector(number_of_dds_generators-1 downto 0);
signal dds_generator_phase_increments: modulated_generator_phase_vector(number_of_dds_generators-1 downto 0);
signal dds_generator_phase_shifts: modulated_generator_phase_vector(number_of_dds_generators-1 downto 0);
signal dds_generator_levels: modulated_generator_level_vector(number_of_dds_generators-1 downto 0);
signal dds_generator_phases: modulated_generator_phase_vector(number_of_dds_generators-1 downto 0);
signal dds_generator_samples: modulated_generator_sample_vector(number_of_dds_generators-1 downto 0);
signal dds_sync_int: std_logic_vector(number_of_dds_generators-1 downto 0);
-- Pulse generator
signal pulse_generator_high_duration, pulse_generator_low_duration:
unsigned(data_width-1 downto 0);
signal pulse_int: std_logic;
-- Universal counter
signal universal_counter_config: data_buffer;
signal universal_counter_input: std_logic;
signal universal_counter_value: unsigned(data_width-1 downto 0);
signal universal_counter_state: data_buffer;
signal update_universal_counter_output: std_logic;
-- Scope
signal scope_config: data_buffer;
subtype scope_input_value is signed(ram_data_width-1 downto 0);
signal scope_input: scope_input_value;
-- DAC
signal dac_channel_select_int: std_logic;
signal dac_write_int: std_logic;
subtype dac_channel_value is signed(dac_data_width-1 downto 0);
type dac_channel_value_vector is array (natural range <>) of dac_channel_value;
signal dac_channel_values: dac_channel_value_vector(1 downto 0);
signal dac_value: unsigned(dac_data_width-1 downto 0);
signal dac_data: std_logic_vector(dac_data_width-1 downto 0);
-- Memory controller
signal memory_connect: std_logic;
signal memory_read: std_logic;
signal memory_write: std_logic;
signal memory_ready: std_logic;
signal memory_auto_increment_address: std_logic;
signal memory_auto_increment_end_address_reached: std_logic;
signal memory_address: unsigned(ram_address_width-1 downto 0);
signal memory_data_in: std_logic_vector(ram_data_width-1 downto 0);
signal memory_data_out: std_logic_vector(ram_data_width-1 downto 0);
-- SRAM/DAC shared lines
type sram_dac_lines_type is record
ram_addr_dac_data: unsigned(ram_address_width-1 downto 0);
dac_clk: std_logic;
dac_channel_select: std_logic;
dac_write_n: std_logic;
ram_we_n: std_logic;
ram_oe_n: std_logic;
end record;
signal selected_sram_dac_lines, sram_lines, dac_lines: sram_dac_lines_type :=
(
-- Initialize to proper idle values.
ram_addr_dac_data => (others => '0'),
dac_clk => '1',
dac_channel_select => '1',
dac_write_n => '1',
ram_we_n => '1',
ram_oe_n => '1'
);
-- Peripheral (I/O) configuration
signal peripheral_config_raw: data_buffer;
subtype dac_channel_source is unsigned(dac_source_selector_width-1 downto 0);
type dac_channel_source_vector is array (natural range <>) of dac_channel_source;
type peripheral_configuration_type is record
dac_channel_sources: dac_channel_source_vector(0 to 1);
end record;
signal peripheral_configuration: peripheral_configuration_type :=
(
dac_channel_sources => (others => (others => '0'))
);
-- Interconnection
signal transmit_data_x: data_buffer_vector(number_of_data_buffers-1 downto 0)
:= (others => (others => '0'));
signal received_data_x: data_buffer_vector(number_of_data_buffers-1 downto 0);
signal ready_x: std_logic_vector(number_of_data_buffers-1 downto 0);
begin
--------------------------------------------------------------------------------
-- Connections to and from internal signals.
--------------------------------------------------------------------------------
-- NOTE: Reading to and writing from an SPI address always happen together. Each time
-- the SPI master reads a value from the slave's transmit register, it also writes a value
-- to the slave's receive register of the same address, overwriting any previous value.
--
-- If the internal SPI connection is used, the microcontroller of the c'Lab FPGA board
-- acts as the SPI master. It accesses a particular SPI adress as follows:
-- 1) If one of the Param or Value screens is selected on the panel, the microcontroller
-- accesses the SPI bus periodically to read the value from and write the parameter to
-- the according SPI address.
-- 2) When processing a c't Lab protocol set command, the microcontroller writes the
-- according parameter to the SPI slave and ignores the value read from the SPI slave.
-- 3) When processing a c't Lab protocol query command, the microcontroller writes an
-- arbitrary parameter to the SPI slave and returns the value read from the SPI slave.
-- It happens to be that the parameter sent most recently to the same or any other SPI
-- address is reused as this arbitrary parameter.
--
-- If the external SPI connection is used, it's up to the external SPI master how to handle
-- values read from the SPI slave and how to generate parameters written to the SPI slave.
-- SPI receiver data (index 0 to 3 are also available via the FPGA panel).
-----------------------------------------------------------------------------
-- DDS generators.
connect_dds_generators: for i in dds_generator_base_subaddr'range generate
dds_generator_configs_raw(i) <= received_data_x(dds_generator_base_subaddr(i)+0);
dds_generator_configs(i).generator.waveform <= dds_generator_configs_raw(i)(18 downto 16);
dds_generator_configs(i).FM_range <= unsigned(dds_generator_configs_raw(i)(12 downto 8));
dds_generator_configs(i).sync_source <= unsigned(dds_generator_configs_raw(i)(7 downto 6));
dds_generator_configs(i).PM_source <= unsigned(dds_generator_configs_raw(i)(5 downto 4));
dds_generator_configs(i).FM_source <= unsigned(dds_generator_configs_raw(i)(3 downto 2));
dds_generator_configs(i).AM_source <= unsigned(dds_generator_configs_raw(i)(1 downto 0));
dds_generator_phase_increments(i) <=
unsigned(received_data_x(dds_generator_base_subaddr(i)+1));
dds_generator_phase_shifts(i) <=
unsigned(received_data_x(dds_generator_base_subaddr(i)+2)(15 downto 0)) & x"0000";
dds_generator_levels(i) <=
signed(received_data_x(dds_generator_base_subaddr(i)+2)(dds_generator_level_width+15 downto 16));
end generate;
-- Pulse generator.
pulse_generator_high_duration <= unsigned(received_data_x(pulse_generator_high_duration_subaddr));
pulse_generator_low_duration <= unsigned(received_data_x(pulse_generator_low_duration_subaddr));
-- Universal counter.
universal_counter_config <= received_data_x(universal_counter_config_subaddr);
-- Scope
scope_config <= received_data_x(scope_config_subaddr);
-- Peripheral configuration.
peripheral_config_raw <= received_data_x(peripheral_configuration_subaddr);
peripheral_configuration.dac_channel_sources(0) <= unsigned(peripheral_config_raw(dac_source_selector_width-1 downto 0));
peripheral_configuration.dac_channel_sources(1) <= unsigned(peripheral_config_raw(2*dac_source_selector_width-1 downto dac_source_selector_width));
-- Memory controller
-- Combination of mode (5 bits), address (19 bits) and write data (8 bits).
-- Mode is sum of
-- bus select: 0 = DAC data, 16 = SRAM address
-- automatic address increment: 0 = off, 8 = on
-- memory access: 0 = off, 1 = read, 2 = write
memory_connect <= received_data_x(sram_subaddr)(data_buffer'high);
memory_auto_increment_address <= received_data_x(sram_subaddr)(data_buffer'high-1);
-- Here is 1 unused bit (data_buffer'high-2).
memory_write <= received_data_x(sram_subaddr)(data_buffer'high-3);
memory_read <= received_data_x(sram_subaddr)(data_buffer'high-4);
memory_address <= unsigned(received_data_x(sram_subaddr)(ram_address_width-1+ram_data_width downto ram_data_width));
memory_data_in <= received_data_x(sram_subaddr)(ram_data_width-1 downto 0);
-- Panel parameters (example only).
-- dac_channel_1_value <= signed(received_data_x(1)(dac_data_width-1 downto 0));
-- SPI transmitter data (index 0 to 3 are also available via the FPGA panel).
-----------------------------------------------------------------------------
-- Universal counter.
transmit_data_x(universal_counter_state_subaddr) <= std_logic_vector(universal_counter_state);
transmit_data_x(universal_counter_value_subaddr) <= std_logic_vector(universal_counter_value);
-- Memory controller
-- Combination of memory state (1 bit), memory auto-increment state (1 bit), '0' (1 bit),
-- partial mode loopback (2 bits), address loopback (19 bits) and read data (8 bits).
-- State is sum of
-- memory state: 0 = working, 16 = ready
-- memory auto-increment state: 0 = end address not reached, 8 = end address reached
-- mode loopback: 0 = off, 1 = reading, 2 = writing
transmit_data_x(sram_subaddr) <= memory_ready
& memory_auto_increment_end_address_reached
& '0'
& received_data_x(sram_subaddr)(data_buffer'high-3 downto ram_data_width)
& memory_data_out;
-- Panel values.
transmit_data_x(0) <= X"DEADBEEF";
-- transmit_data_x(0) <= universal_counter_config;
-- transmit_data_x(1) <= std_logic_vector(dds_generator_phase_increments(0));
-- transmit_data_x(2) <= std_logic_vector(dds_generator_phase_shifts(0));
-- transmit_data_x(3) <= std_logic_vector(dds_generator_phases(0));
-- Miscellaneous.
-----------------------------------------------------------------------------
-- Generate DDS synchronization signals (high during 1st half period, i.e.
-- the rising edge marks 0).
generate_sync: for i in 0 to number_of_dds_generators-1 generate
dds_sync_int(i) <= not dds_generator_phases(i)(dds_generator_phase_width-1);
end generate;
-- Freeze counter output while transmitting counter state or value.
update_universal_counter_output <= ready_x(4) and ready_x(5);
-- Provide the inverted DAC value to compensate the hardware inverter.
invert_dac_value: for i in dac_data'range generate
dac_data(i) <= not dac_value(i);
end generate;
--------------------------------------------------------------------------------
-- SPI input selection logic.
--------------------------------------------------------------------------------
-- The internal SPI bus (i.e. the one connected to the microcontroller of the
-- c'Lab FPGA board).
internal_spi_in.mosi <= f_mosi;
internal_spi_in.sclk <= f_sck;
internal_spi_in.ss_address <= f_rs;
internal_spi_in.ss_data <= f_ds;
-- The external SPI bus (i.e. the one connected to the expansion ports of the
-- c'Lab FPGA board).
external_spi_in.mosi <= ext_mosi;
external_spi_in.sclk <= ext_sck;
external_spi_in.ss_address <= ext_rs;
external_spi_in.ss_data <= ext_ds;
-- Select the SPI connection to use.
-- NOTE: If one of the Param or Value screens is selected on the panel, the microcontroller
-- of the c'Lab FPGA board accesses the SPI bus periodically to read the value from and write
-- the parameter to the according SPI address (SPI reading and writing always happen together).
-- Thus, when both connections are activated, while using the *external* connection, set the
-- panel to the file selection screen to avoid this interference.
-- Also, when both connections are activated, while using the *internal* connection, ensure
-- that the selection pins of the external connection (ext_rs and ext_ds) are pulled up properly.
-- If they are e.g. connected to the SPI interface of a Raspberry Pi, ensure that the latter is
-- switched on. Don't leave the pins unconnected, pull them up instead.
selected_spi_in <=
internal_spi_in when use_internal_spi and
(internal_spi_in.ss_address = '0' or internal_spi_in.ss_data = '0') else
external_spi_in when use_external_spi and
(external_spi_in.ss_address = '0' or external_spi_in.ss_data = '0') else
inactive_spi_in;
--------------------------------------------------------------------------------
-- SRAM/DAC output selection logic (they share the same pins and thus can only
-- be used alternatively).
--------------------------------------------------------------------------------
-- SRAM lines.
----------------------
-- sram_lines.ram_addr_dac_data => Directly connected to SRAM_Controller
sram_lines.dac_clk <= '1';
sram_lines.dac_channel_select <= '1';
sram_lines.dac_write_n <= '1';
-- sram_lines.ram_we_n => Directly connected to SRAM_Controller
-- sram_lines.ram_oe_n => Directly connected to SRAM_Controller
-- DAC lines.
----------------------
-- Apply data in reverse bit order, padded on the left.
generate_dac_data: for i in 0 to dac_data_width-1 generate
dac_lines.ram_addr_dac_data(i) <= dac_data(dac_data_width-1-i);
end generate;
dac_lines.ram_addr_dac_data(ram_addr_dac_data_width-1 downto dac_data_width) <= (others => '0');
-- Apply control signals for single or dual DAC. For the single DAC U2, we use
-- dac_channel_select as the clock. Thus, U2 always uses the value of channel 0.
dac_lines.dac_clk <= dac_channel_select_int; -- (single DAC U2 only)
dac_lines.dac_channel_select <= dac_channel_select_int; -- (dual DAC U5 only)
dac_lines.dac_write_n <= not dac_write_int; -- (dual DAC U5 only)
dac_lines.ram_we_n <= '1';
dac_lines.ram_oe_n <= '1';
-- Select the peripheral (SRAM or DAC) to use.
selected_sram_dac_lines <=
sram_lines when memory_connect = '1' else
dac_lines;
--------------------------------------------------------------------------------
-- Component instantiation.
--------------------------------------------------------------------------------
-- The clock manager generating the clocks used throughout the system.
clock_manager: entity work.ClockManager
port map
(
clk => sysclk,
clk_50mhz => clk_50mhz,
clk_100mhz => clk_100mhz
);
-- The slave of the SPI interface.
slave: entity SPI_Interface.SPI_Slave
generic map
(
address_width => address_width,
synchronize_data_to_clk => true
)
port map
(
clk => clk_50mhz,
sclk => selected_spi_in.sclk,
ss_address => selected_spi_in.ss_address,
ss_data => selected_spi_in.ss_data,
transmit_data_x => transmit_data_x,
mosi => selected_spi_in.mosi,
miso => miso,
received_data_x => received_data_x,
ready_x => ready_x
);
-- The universal counter for frequency and period measurements.
universal_counter: entity work.UniversalCounter
port map
(
clk => clk_50mhz,
update_output => update_universal_counter_output,
external_signal => universal_counter_input,
measure_period => universal_counter_config(4),
clk_division_mode => universal_counter_config(3 downto 0),
value => universal_counter_value,
overflow => universal_counter_state(1),
ready => universal_counter_state(0)
);
-- The pulse generator producing a rectangular signal with specific pulse
-- and pause durations.
pulse_generator: entity work.PulseGenerator
generic map
(
counter_width => pulse_generator_counter_width
)
port map
(
clk => clk_100mhz,
high_duration => pulse_generator_high_duration,
low_duration => pulse_generator_low_duration,
pulse_signal => pulse_int
);
-- The modulated DDS signal generator producing multiple signals with
-- miscellaneous waveforms.
dds_generator: entity work.ModulatedGenerator
generic map
(
number_of_generators => number_of_dds_generators,
phase_width => dds_generator_phase_width,
lookup_table_phase_width => dds_generator_lookup_table_phase_width,
level_width => dds_generator_level_width,
sample_width => dds_generator_sample_width
)
port map
(
clk => clk_100mhz,
configs => dds_generator_configs,
phase_increments => dds_generator_phase_increments,
phase_shifts => dds_generator_phase_shifts,
levels => dds_generator_levels,
phases => dds_generator_phases,
samples => dds_generator_samples
);
-- The DAC controller used to pass the signals to be D/A-converted to the DACs.
dac_controller: entity work.DACController
generic map
(
data_width => dac_data_width
)
port map
(
clk => clk_100mhz,
channel_0_value => dac_channel_values(0),
channel_1_value => dac_channel_values(1),
dac_channel_select => dac_channel_select_int,
dac_write => dac_write_int,
dac_value => dac_value
);
-- The SRAM controller.
sram: entity SRAM_Controller.SRAM_Controller
generic map
(
num_of_total_wait_states => num_of_total_wait_states,
num_of_write_pulse_wait_states => num_of_write_pulse_wait_states,
num_of_wait_states_before_write_after_read => num_of_wait_states_before_write_after_read,
data_width => ram_data_width,
address_width => ram_address_width
)
port map
(
clk => clk_100mhz,
read => memory_read,
write => memory_write,
ready => memory_ready,
auto_increment_address => memory_auto_increment_address,
auto_increment_end_address_reached => memory_auto_increment_end_address_reached,
address => memory_address,
data_in => std_logic_vector(scope_input),
data_out => memory_data_out,
ram_we_n => sram_lines.ram_we_n,
ram_oe_n => sram_lines.ram_oe_n,
ram_address => sram_lines.ram_addr_dac_data,
ram_data => ram_data
);
--------------------------------------------------------------------------------
-- Internal configuration logic.
--------------------------------------------------------------------------------
-- Connects the selected signals to the scope input.
connect_scope_input: process is
constant scope_source_pulse: integer := 4;
constant scope_source_external: integer := 5;
constant scope_source_data: integer := 6;
variable scope_source: integer;
begin
wait until rising_edge(clk_100mhz);
scope_source := to_integer(unsigned(scope_config(10 downto 8)));
case (scope_source) is
when scope_source_pulse =>
-- Connect a positive signal corresponding to the pulse.
scope_input <= (others => pulse_int);
scope_input(ram_data_width-1) <= '0';
when scope_source_external =>
-- Connect a positive signal corresponding to the external signal.
scope_input <= (others => external_in);
scope_input(ram_data_width-1) <= '0';
when scope_source_data =>
-- Connect the data.
scope_input <= signed(memory_data_in);
when others =>
-- Connect the DDS signal generator specified.
scope_input <= dds_generator_samples(scope_source)
(modulated_generator_sample_width-1 downto modulated_generator_sample_width-ram_data_width);
end case;
end process;
-- Connects the selected signals to the DACs inputs.
connect_dac_input: process is
constant dac_channel_source_pulse: integer := 4;
variable dac_channel_source: integer;
begin
wait until rising_edge(clk_100mhz);
for i in dac_channel_values'range loop
dac_channel_source := to_integer(peripheral_configuration.dac_channel_sources(i));
case (dac_channel_source) is
when dac_channel_source_pulse =>
-- Connect a positive signal corresponding to the pulse.
dac_channel_values(i) <= (others => pulse_int);
dac_channel_values(i)(dac_data_width-1) <= '0';
when others =>
-- Connect the DDS signal generator specified.
dac_channel_values(i) <= dds_generator_samples(dac_channel_source);
end case;
end loop;
end process;
-- Connects the selected signals to the universal counter input.
connect_counter_input: process is
constant universal_counter_source_pulse: integer := 4;
constant universal_counter_source_external: integer := 5;
variable universal_counter_source: integer;
begin
wait until rising_edge(clk_100mhz);
universal_counter_source := to_integer(unsigned(universal_counter_config(10 downto 8)));
case (universal_counter_source) is
when universal_counter_source_pulse =>
-- Connect the pulse signal.
universal_counter_input <= pulse_int;
when universal_counter_source_external =>
-- Connect the external signal.
universal_counter_input <= external_in;
when others =>
-- Connect the DDS signal generator specified.
universal_counter_input <= dds_sync_int(universal_counter_source);
end case;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
-- Pulse and DDS generators.
pulse_out <= pulse_int;
dds_sync_out <= dds_sync_int;
-- SPI & test LED.
f_miso <= miso when f_ds = '0' else 'Z';
ext_miso <= miso when ext_ds = '0' else 'Z';
test_led <= received_data_x(0)(0); -- LED is active low
-- SRAM address or DAC data.
ram_addr_dac_data <= selected_sram_dac_lines.ram_addr_dac_data;
dac_clk <= selected_sram_dac_lines.dac_clk;
dac_channel_select <= selected_sram_dac_lines.dac_channel_select;
dac_write_n <= selected_sram_dac_lines.dac_write_n;
ram_we_n <= selected_sram_dac_lines.ram_we_n;
ram_oe_n <= selected_sram_dac_lines.ram_oe_n;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity XOR_MIN_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of XOR_MIN_8b is
begin
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE rTemp1 : STD_LOGIC_VECTOR(7 downto 0);
VARIABLE rTemp2 : STD_LOGIC_VECTOR(7 downto 0);
VARIABLE rTemp3 : STD_LOGIC_VECTOR(7 downto 0);
VARIABLE rTemp4 : STD_LOGIC_VECTOR(7 downto 0);
begin
-- ON TRAITE LE PREMIER MOT DE 8 BITS CONTENU DANS LES OPERANDES
if( UNSIGNED(INPUT_1( 6 downto 0)) < UNSIGNED(INPUT_2( 6 downto 0)) ) then rTemp1(6 downto 0) := INPUT_1( 6 downto 0); else rTemp1(6 downto 0) := INPUT_2( 6 downto 0); end if;
rTemp1(7) := INPUT_1(7) xor INPUT_2(7);
-- ON TRAITE LE SECOND MOT DE 8 BITS CONTENU DANS LES OPERANDES
if( UNSIGNED(INPUT_1(14 downto 8)) < UNSIGNED(INPUT_2(14 downto 8)) ) then rTemp2(6 downto 0) := INPUT_1(14 downto 8); else rTemp2(6 downto 0) := INPUT_2(14 downto 8); end if;
rTemp2(7) := INPUT_1(15) xor INPUT_2(15);
-- ON TRAITE LE TROISIEME MOT DE 8 BITS CONTENU DANS LES OPERANDES
if( UNSIGNED(INPUT_1(22 downto 16)) < UNSIGNED(INPUT_2(22 downto 16)) ) then rTemp3(6 downto 0) := INPUT_1(22 downto 16); else rTemp3(6 downto 0) := INPUT_2(22 downto 16); end if;
rTemp3(7) := INPUT_1(23) xor INPUT_2(23);
-- ON TRAITE LE QUATRIEME MOT DE 8 BITS CONTENU DANS LES OPERANDES
if( UNSIGNED(INPUT_1(30 downto 24)) < UNSIGNED(INPUT_2(30 downto 24)) ) then rTemp4(6 downto 0) := INPUT_1(30 downto 24); else rTemp4(6 downto 0) := INPUT_2(30 downto 24); end if;
rTemp4(7) := INPUT_1(31) xor INPUT_2(31);
-- ON REGROUPE LES 4 MOTS AFIN DE RECONSTITUER LE RESULTAT SUR 32 BITS
OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1);
END PROCESS;
-------------------------------------------------------------------------
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:01 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Mux4x1_10_0_0/RAT_Mux4x1_10_0_0_stub.vhdl
-- Design : RAT_Mux4x1_10_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_Mux4x1_10_0_0 is
Port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
C : in STD_LOGIC_VECTOR ( 9 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
X : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end RAT_Mux4x1_10_0_0;
architecture stub of RAT_Mux4x1_10_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "A[9:0],B[9:0],C[9:0],D[9:0],SEL[1:0],X[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "Mux4x1_10,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:01 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Mux4x1_10_0_0/RAT_Mux4x1_10_0_0_stub.vhdl
-- Design : RAT_Mux4x1_10_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_Mux4x1_10_0_0 is
Port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
C : in STD_LOGIC_VECTOR ( 9 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
X : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end RAT_Mux4x1_10_0_0;
architecture stub of RAT_Mux4x1_10_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "A[9:0],B[9:0],C[9:0],D[9:0],SEL[1:0],X[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "Mux4x1_10,Vivado 2016.4";
begin
end;
|
-- megafunction wizard: %LPM_OR%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_or
-- ============================================================
-- File Name: lpm_or60.vhd
-- Megafunction Name(s):
-- lpm_or
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY lpm_or60 IS
PORT
(
data : IN STD_LOGIC_2D (59 DOWNTO 0, 0 DOWNTO 0);
result : OUT STD_LOGIC
);
END lpm_or60;
ARCHITECTURE SYN OF lpm_or60 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
BEGIN
sub_wire1 <= sub_wire0(0);
result <= sub_wire1;
lpm_or_component : lpm_or
GENERIC MAP (
lpm_size => 60,
lpm_type => "LPM_OR",
lpm_width => 1
)
PORT MAP (
data => data,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CompactSymbol NUMERIC "0"
-- Retrieval info: PRIVATE: GateFunction NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: InputAsBus NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WidthInput NUMERIC "1"
-- Retrieval info: PRIVATE: nInput NUMERIC "60"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "60"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_OR"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: data 60 0 1 0 INPUT NODEFVAL data[59..0][0..0]
-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result
-- Retrieval info: CONNECT: @data 60 0 1 0 data 60 0 1 0
-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_OR%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_or
-- ============================================================
-- File Name: lpm_or60.vhd
-- Megafunction Name(s):
-- lpm_or
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY lpm_or60 IS
PORT
(
data : IN STD_LOGIC_2D (59 DOWNTO 0, 0 DOWNTO 0);
result : OUT STD_LOGIC
);
END lpm_or60;
ARCHITECTURE SYN OF lpm_or60 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
BEGIN
sub_wire1 <= sub_wire0(0);
result <= sub_wire1;
lpm_or_component : lpm_or
GENERIC MAP (
lpm_size => 60,
lpm_type => "LPM_OR",
lpm_width => 1
)
PORT MAP (
data => data,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CompactSymbol NUMERIC "0"
-- Retrieval info: PRIVATE: GateFunction NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: InputAsBus NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WidthInput NUMERIC "1"
-- Retrieval info: PRIVATE: nInput NUMERIC "60"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "60"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_OR"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: data 60 0 1 0 INPUT NODEFVAL data[59..0][0..0]
-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result
-- Retrieval info: CONNECT: @data 60 0 1 0 data 60 0 1 0
-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_or60_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mul_61x61
-- File: mul_61x61.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: 61x61 multiplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity mul_61x61 is
generic (multech : integer := 0;
fabtech : integer := 0);
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of mul_61x61 is
component dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component axcel_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex4_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex6_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex7_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component kintex7_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
begin
gen0 : if multech = 0 generate
mul0 : gen_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
dw0 : if multech = 1 generate
mul0 : dw_mul_61x61 port map (A, B, CLK, PRODUCT);
end generate;
tech0 : if multech = 3 generate
axd0 : if fabtech = axdsp generate
mul0 : axcel_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
xc5v : if fabtech = virtex5 generate
mul0 : virtex4_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
xc6v : if fabtech = virtex6 generate
mul0 : virtex6_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
gen0 : if not ((fabtech = axdsp) or (fabtech = virtex5) or (fabtech = virtex6)) generate
mul0 : gen_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
end generate;
end;
|
package pack is
function func(x : integer) return integer;
procedure proc(x : integer);
end package;
-------------------------------------------------------------------------------
entity duplicate is
end entity;
use work.pack.all;
architecture test of duplicate is
function func(x : integer) return integer is
begin
return x + 1;
end function;
procedure proc(x : integer) is
begin
end procedure;
begin
process is
begin
assert func(2) = 3; -- OK
assert pack.func(2) = 3; -- OK
proc(2); -- OK
pack.proc(2); -- OK
wait;
end process;
end architecture;
|
package pack is
function func(x : integer) return integer;
procedure proc(x : integer);
end package;
-------------------------------------------------------------------------------
entity duplicate is
end entity;
use work.pack.all;
architecture test of duplicate is
function func(x : integer) return integer is
begin
return x + 1;
end function;
procedure proc(x : integer) is
begin
end procedure;
begin
process is
begin
assert func(2) = 3; -- OK
assert pack.func(2) = 3; -- OK
proc(2); -- OK
pack.proc(2); -- OK
wait;
end process;
end architecture;
|
package pack is
function func(x : integer) return integer;
procedure proc(x : integer);
end package;
-------------------------------------------------------------------------------
entity duplicate is
end entity;
use work.pack.all;
architecture test of duplicate is
function func(x : integer) return integer is
begin
return x + 1;
end function;
procedure proc(x : integer) is
begin
end procedure;
begin
process is
begin
assert func(2) = 3; -- OK
assert pack.func(2) = 3; -- OK
proc(2); -- OK
pack.proc(2); -- OK
wait;
end process;
end architecture;
|
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