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library ieee;
use ieee.std_logic_1164.all;
entity cpu is
port (
test : out std_logic_vector(7 downto 0)
);
end cpu;
architecture rtl of cpu is
begin
test <= "00000000";
end rtl;
|
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: dma.vhd
-- Module Name: dma_rx.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dma_rx is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Señales procedentes del bus del uP.
Databus : out STD_LOGIC_VECTOR (7 downto 0);
Address : out STD_LOGIC_VECTOR (7 downto 0);
ChipSelect : out STD_LOGIC;
WriteEnable : out STD_LOGIC;
OutputEnable : out STD_LOGIC;
-- Señales procedentes de la FSM del Controlador de Bus.
Start_RX : in STD_LOGIC;
End_RX : out STD_LOGIC;
-- Bus de datos y señales de handshake orientadas al receptor del
-- RS232.
DataIn : in STD_LOGIC_VECTOR (7 downto 0);
Read_DI : out STD_LOGIC;
Empty : in STD_LOGIC);
end dma_rx;
architecture Behavioral of dma_rx is
-- Definición de los posibles estados de la FSM del Transmisor:
type Receiver_ST is (idle, MVE_REGX, CPY_NEWINST);
signal RX_now, RX_next : Receiver_ST;
-- Tabla de direcciones:
-- El valor contenido en cada posición de la tabla será empleado como
-- dirección de memoria en la que se escribirá el dato de entrada,
-- utilizando como índice el orden de llegada de los bytes entrantes.
type table is array (natural range <>) of std_logic_vector(7 downto 0);
constant AddressTable : table := (X"00", X"01", X"02", X"03");
-- Señales usadas para inferir un contador que vaya barriendo la tabla de
-- direcciones para ir almacenando los datos recibidos en su respectiva
-- posición de memoria.
signal count : std_logic_vector(1 downto 0);
-- Señal de enable y clear del contador anterior.
signal count_enable, count_clear : std_logic;
begin
-- El Receptor nunca leerá un valor de memoria. Únicamente escribe los
-- datos recibidos en ella.
OutputEnable <= '0';
-- Proceso secuencial que describe el contador necesario para indexar la
-- tabla de direcciones del Receptor.
-- Dispone de una señal de Reset asíncrono activa a nivel bajo que
-- inicializa a 0 el valor del contador.
-- Además dispone de dos entradas de control síncronas y activas a nivel
-- alto (enable y clear), procedentes de la FSM del Receptor, desde las
-- cuales se gobernará el contador.
process(Clk, Reset)
begin
if (Reset = '0') then
count <= (others => '0');
elsif Clk'event and Clk = '1' then
if count_clear = '1' then
count <= (others => '0');
elsif count_enable = '1' then
count <= count + '1';
end if;
end if;
end process;
-- Proceso secuencial de la máquina de estados del Receptor.
-- Dispone de una señal de Reset asíncrono activa a nivel bajo. Mientras que
-- esta señal se mantenga activa, la FSM se mantiene en el estado de 'Idle'.
process(Clk, Reset)
begin
if (Reset = '0') then
RX_now <= idle;
elsif Clk'event and Clk = '1' then
RX_now <= RX_next;
end if;
end process;
-- Proceso combinacional de la máquina de estados.
process(RX_now, Start_RX, DataIn, Empty, count)
begin
-- Valores preasignados por defecto.
Databus <= DataIn;
Address <= X"00";
ChipSelect <= '0';
WriteEnable <= '0';
End_RX <= '0';
Read_DI <= '0';
count_enable <= '0';
count_clear <= '0';
case RX_now is
when idle =>
-- Si el Controlador de Bus da permiso para iniciar una nueva
-- recepción...
if Start_RX = '1' then
RX_next <= MVE_REGX;
else
RX_next <= idle;
end if;
when MVE_REGX =>
Address <= AddressTable(conv_integer(count));
ChipSelect <= '1';
WriteEnable <= '1';
Read_DI <= '1';
count_enable <= '1';
-- Si el RS232 ya no tiene más datos recibidos...
if (Empty = '1') then
-- No se realiza la transferencia .
ChipSelect <= '0';
WriteEnable <= '0';
Read_DI <= '0';
-- Ni se actualiza el contador.
count_enable <= '0';
-- Y se vuelve al estado de espera, devolviendo el control de
-- los buses.
End_RX <= '1';
RX_next <= idle;
-- Si se está recibiendo correctamente el LSB...
elsif (count = X"2") then
RX_next <= CPY_NEWINST;
else
RX_next <= MVE_REGX;
end if;
when CPY_NEWINST =>
Address <= AddressTable(conv_integer(count));
Databus <= X"FF";
ChipSelect <= '1';
WriteEnable <= '1';
-- Se reinicia el contador y se vuelve al estado de espera,
-- devolviendo el control de los buses.
count_clear <= '1';
End_RX <= '1';
RX_next <= idle;
end case;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------------------------
-- Testbench - GF(2^M) Extended Euclidean Inversion
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 22.06.2017
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE ieee.math_real.all; -- FOR UNIFORM, TRUNC
USE std.textio.ALL;
USE work.tld_ecdsa_package.all;
ENTITY tb_eea_inversion IS
END tb_eea_inversion;
ARCHITECTURE rtl OF tb_eea_inversion IS
-- Import entity e_gf2m_eea_inversion
COMPONENT e_gf2m_eea_inversion IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
a_i: IN std_logic_vector (M-1 DOWNTO 0);
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Import entity e_classic_gf2m_multiplier
COMPONENT e_gf2m_classic_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT (
a_i: IN std_logic_vector(M-1 DOWNTO 0);
b_i: IN std_logic_vector(M-1 DOWNTO 0);
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END COMPONENT;
-- Internal signals
SIGNAL x, z, z_by_x : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL clk, rst, enable, done: std_logic;
CONSTANT ZERO: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
CONSTANT ONE: std_logic_vector(M-1 DOWNTO 0) := (0 => '1', OTHERS=>'0');
CONSTANT DELAY : time := 100 ns;
CONSTANT PERIOD : time := 200 ns;
CONSTANT DUTY_CYCLE : real := 0.5;
CONSTANT OFFSET : time := 0 ns;
CONSTANT NUMBER_TESTS: natural := 20;
BEGIN
-- Instantiate eea inversion entity
uut1: e_gf2m_eea_inversion GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP (
clk_i => clk,
rst_i => rst,
enable_i => enable,
a_i => x,
z_o => z,
ready_o => done
);
-- Instantiate classic multiplication entity
uut2: e_gf2m_classic_multiplier GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP (
a_i => x,
b_i => z,
c_o => z_by_x
);
-- Create clock signal
PROCESS -- clock process FOR clk
BEGIN
WAIT FOR OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD *(1.0 - DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
-- Start test cases
tb : PROCESS
PROCEDURE gen_random(X : OUT std_logic_vector (M-1 DOWNTO 0); w: natural; s1, s2: inout Natural) IS
VARIABLE i_x, aux: integer;
VARIABLE rand: real;
BEGIN
aux := W/16;
FOR i IN 1 TO aux LOOP
UNIFORM(s1, s2, rand);
i_x := INTEGER(TRUNC(rand * real(65536)));-- real(2**16)));
x(i*16-1 DOWNTO (i-1)*16) := CONV_STD_LOGIC_VECTOR (i_x, 16);
END LOOP;
UNIFORM(s1, s2, rand);
i_x := INTEGER(TRUNC(rand * real(2**(w-aux*16))));
x(w-1 DOWNTO aux*16) := CONV_STD_LOGIC_VECTOR (i_x, (w-aux*16));
END PROCEDURE;
VARIABLE TX_LOC : LINE;
VARIABLE TX_STR : String(1 TO 4096);
VARIABLE seed1, seed2: positive;
VARIABLE i_x, i_y, i_p, i_z, i_yz_modp: integer;
VARIABLE cycles, max_cycles, min_cycles, total_cycles: integer := 0;
VARIABLE avg_cycles: real;
VARIABLE initial_time, final_time: time;
VARIABLE xx: std_logic_vector (M-1 DOWNTO 0) ;
BEGIN
min_cycles:= 2**20;
enable <= '0'; rst <= '1';
WAIT FOR PERIOD;
rst <= '0';
WAIT FOR PERIOD;
-- Generate random test cases
FOR I IN 1 TO NUMBER_TESTS LOOP
gen_random(xx, M, seed1, seed2);
WHILE (xx = ZERO) LOOP
gen_random(xx, M, seed1, seed2);
END LOOP;
x <= xx;
-- Check needed number of cycles
enable <= '1'; initial_time := now;
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL done = '1';
final_time := now;
cycles := (final_time - initial_time)/PERIOD;
total_cycles := total_cycles+cycles;
ASSERT (FALSE) REPORT "Number of Cycles: " & integer'image(cycles) &
" TotalCycles: " & integer'image(total_cycles) SEVERITY WARNING;
IF cycles > max_cycles THEN
max_cycles:= cycles;
END IF;
IF cycles < min_cycles THEN
min_cycles:= cycles;
END IF;
WAIT FOR 2*PERIOD;
-- Validate if x * x^-1 = 1
IF ( ONE /= z_by_x) THEN
write(TX_LOC,string'("ERROR!!! z_by_x=")); write(TX_LOC, z_by_x);
write(TX_LOC,string'("/= ONE="));
write(TX_LOC,string'("( z=")); write(TX_LOC, z);
write(TX_LOC,string'(") using: ( A =")); write(TX_LOC, x);
write(TX_LOC, string'(" )"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
END IF;
END LOOP;
WAIT FOR DELAY;
avg_cycles := real(total_cycles)/real(NUMBER_TESTS);
-- Report results
ASSERT (FALSE) REPORT
"Simulation successful!. MinCycles: " & integer'image(min_cycles) &
" MaxCycles: " & integer'image(max_cycles) & " TotalCycles: " & integer'image(total_cycles) &
" AvgCycles: " & real'image(avg_cycles)
SEVERITY FAILURE;
END PROCESS;
END; |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
entity axi_dma_cmd_split is
generic (
C_ADDR_WIDTH : integer range 32 to 64 := 32;
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
C_INCLUDE_S2MM : integer range 0 to 1 := 0
);
port (
clock : in std_logic;
sgresetn : in std_logic;
clock_sec : in std_logic;
aresetn : in std_logic;
-- command coming from _MNGR
s_axis_cmd_tvalid : in std_logic;
s_axis_cmd_tready : out std_logic;
s_axis_cmd_tdata : in std_logic_vector ((C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);
-- split command to DM
s_axis_cmd_tvalid_s : out std_logic;
s_axis_cmd_tready_s : in std_logic;
s_axis_cmd_tdata_s : out std_logic_vector ((C_ADDR_WIDTH+CMD_BASE_WIDTH+8)-1 downto 0);
-- Tvalid from Datamover
tvalid_from_datamover : in std_logic;
status_in : in std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
tvalid_unsplit : out std_logic;
status_out : out std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
-- Tlast of stream data from Datamover
tlast_stream_data : in std_logic;
tready_stream_data : in std_logic;
tlast_unsplit : out std_logic;
tlast_unsplit_user : out std_logic
);
end entity axi_dma_cmd_split;
architecture implementation of axi_dma_cmd_split is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
type SPLIT_MM2S_STATE_TYPE is (
IDLE,
SEND,
SPLIT
);
signal mm2s_cs : SPLIT_MM2S_STATE_TYPE;
signal mm2s_ns : SPLIT_MM2S_STATE_TYPE;
signal mm2s_cmd : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46-1 downto 0);
signal command_ns : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal command : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal cache_info : std_logic_vector (31 downto 0);
signal vsize_data : std_logic_vector (22 downto 0);
signal vsize_data_int : std_logic_vector (22 downto 0);
signal vsize : std_logic_vector (22 downto 0);
signal counter : std_logic_vector (22 downto 0);
signal counter_tlast : std_logic_vector (22 downto 0);
signal split_cmd : std_logic_vector (31+(C_ADDR_WIDTH-32) downto 0);
signal stride_data : std_logic_vector (22 downto 0);
signal vsize_over : std_logic;
signal cmd_proc_cdc_from : std_logic;
signal cmd_proc_cdc_to : std_logic;
signal cmd_proc_cdc : std_logic;
signal cmd_proc_ns : std_logic;
ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF cmd_proc_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF cmd_proc_cdc : SIGNAL IS "true";
signal cmd_out : std_logic;
signal cmd_out_ns : std_logic;
signal split_out : std_logic;
signal split_out_ns : std_logic;
signal command_valid : std_logic;
signal command_valid_ns : std_logic;
signal command_ready : std_logic;
signal reset_lock : std_logic;
signal reset_lock_tlast : std_logic;
signal tvalid_unsplit_int : std_logic;
signal tlast_stream_data_int : std_logic;
signal ready_for_next_cmd : std_logic;
signal ready_for_next_cmd_tlast : std_logic;
signal ready_for_next_cmd_tlast_cdc_from : std_logic;
signal ready_for_next_cmd_tlast_cdc_to : std_logic;
signal ready_for_next_cmd_tlast_cdc : std_logic;
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc : SIGNAL IS "true";
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal tlast_int : std_logic;
signal eof_bit : std_logic;
signal eof_bit_cdc_from : std_logic;
signal eof_bit_cdc_to : std_logic;
signal eof_bit_cdc : std_logic;
signal eof_set : std_logic;
signal over_ns, over : std_logic;
signal cmd_in : std_logic;
signal status_out_int : std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
begin
s_axis_cmd_tvalid_s <= command_valid;
command_ready <= s_axis_cmd_tready_s;
s_axis_cmd_tdata_s <= command (103+(C_ADDR_WIDTH-32) downto 96+(C_ADDR_WIDTH-32)) & command (71+(C_ADDR_WIDTH-32) downto 0);
REGISTER_STATE_MM2S : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cs <= IDLE;
cmd_proc_cdc_from <= '0';
cmd_out <= '0';
command <= (others => '0');
command_valid <= '0';
split_out <= '0';
over <= '0';
else
mm2s_cs <= mm2s_ns;
cmd_proc_cdc_from <= cmd_proc_ns;
cmd_out <= cmd_out_ns;
command <= command_ns;
command_valid <= command_valid_ns;
split_out <= split_out_ns;
over <= over_ns;
end if;
end if;
end process REGISTER_STATE_MM2S;
-- grab the MM2S command coming from MM2S_mngr
REGISTER_MM2S_CMD : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cmd <= (others => '0');
s_axis_cmd_tready <= '0';
cache_info <= (others => '0');
vsize_data <= (others => '0');
vsize_data_int <= (others => '0');
stride_data <= (others => '0');
eof_bit_cdc_from <= '0';
cmd_in <= '0';
elsif (s_axis_cmd_tvalid = '1' and ready_for_next_cmd = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd_tlast_cdc = '1') then -- when there is no processing being done, means it is ready to accept
mm2s_cmd <= s_axis_cmd_tdata;
s_axis_cmd_tready <= '1';
cache_info <= s_axis_cmd_tdata (149+(C_ADDR_WIDTH-32) downto 118+(C_ADDR_WIDTH-32));
vsize_data <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32));
vsize_data_int <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32)) - '1';
stride_data <= s_axis_cmd_tdata (94+(C_ADDR_WIDTH-32) downto 72+(C_ADDR_WIDTH-32));
eof_bit_cdc_from <= s_axis_cmd_tdata (30);
cmd_in <= '1';
else
mm2s_cmd <= mm2s_cmd; --split_cmd;
vsize_data <= vsize_data;
vsize_data_int <= vsize_data_int;
stride_data <= stride_data;
cache_info <= cache_info;
s_axis_cmd_tready <= '0';
eof_bit_cdc_from <= eof_bit_cdc_from;
cmd_in <= '0';
end if;
end if;
end process REGISTER_MM2S_CMD;
REGISTER_DECR_VSIZE : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
vsize <= "00000000000000000000000";
elsif (command_valid = '1' and command_ready = '1' and (vsize < vsize_data_int)) then -- sending a cmd out to DM
vsize <= vsize + '1';
elsif (cmd_proc_cdc_from = '0') then -- idle or when all cmd are sent to DM
vsize <= "00000000000000000000000";
else
vsize <= vsize;
end if;
end if;
end process REGISTER_DECR_VSIZE;
vsize_over <= '1' when (vsize = vsize_data_int) else '0';
-- eof_set <= eof_bit when (vsize = vsize_data_int) else '0';
REGISTER_SPLIT : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
split_cmd <= (others => '0');
elsif (s_axis_cmd_tvalid = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd = '1' and ready_for_next_cmd_tlast_cdc = '1') then
split_cmd <= s_axis_cmd_tdata (63+(C_ADDR_WIDTH-32) downto 32); -- capture the ba when a new cmd arrives
elsif (split_out = '1') then -- add stride to previous ba
split_cmd <= split_cmd + stride_data;
else
split_cmd <= split_cmd;
end if;
end if;
end process REGISTER_SPLIT;
MM2S_MACHINE : process(mm2s_cs,
s_axis_cmd_tvalid,
cmd_proc_cdc_from,
vsize_over, command_ready,
cache_info, mm2s_cmd,
split_cmd, eof_set,
cmd_in, command
)
begin
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
mm2s_ns <= mm2s_cs;
command_ns <= command;
-- Default signal assignment
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
if (cmd_in = '1' and cmd_proc_cdc_from = '0') then
cmd_proc_ns <= '1'; -- new command has come in and i need to start processing
mm2s_ns <= SEND;
over_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
else
mm2s_ns <= IDLE;
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
end if;
-------------------------------------------------------------------
when SEND =>
cmd_out_ns <= '1';
command_ns <= command;
if (vsize_over = '1' and command_ready = '1') then
mm2s_ns <= IDLE;
cmd_proc_ns <= '1';
command_valid_ns <= '0';
split_out_ns <= '0';
over_ns <= '1';
elsif (command_ready = '0') then --(command_valid = '1' and command_ready = '0') then
mm2s_ns <= SEND;
command_valid_ns <= '1';
cmd_proc_ns <= '1';
split_out_ns <= '0';
over_ns <= '0';
else
mm2s_ns <= SPLIT;
command_valid_ns <= '0';
cmd_proc_ns <= '1';
over_ns <= '0';
split_out_ns <= '0';
end if;
-------------------------------------------------------------------
when SPLIT =>
cmd_proc_ns <= '1';
mm2s_ns <= SEND;
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
cmd_out_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
SWALLOW_TVALID : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
counter <= (others => '0');
-- tvalid_unsplit_int <= '0';
reset_lock <= '1';
ready_for_next_cmd <= '0';
elsif (vsize_data_int = "00000000000000000000000") then
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '1';
reset_lock <= '0';
elsif ((tvalid_from_datamover = '1') and (counter < vsize_data_int)) then
counter <= counter + '1';
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '0';
reset_lock <= '0';
elsif ((counter = vsize_data_int) and (reset_lock = '0') and (tvalid_from_datamover = '1')) then
counter <= (others => '0');
-- tvalid_unsplit_int <= '1';
ready_for_next_cmd <= '1';
else
counter <= counter;
-- tvalid_unsplit_int <= '0';
if (cmd_proc_cdc_from = '1') then
ready_for_next_cmd <= '0';
else
ready_for_next_cmd <= ready_for_next_cmd;
end if;
end if;
end if;
end process SWALLOW_TVALID;
tvalid_unsplit_int <= tvalid_from_datamover when (counter = vsize_data_int) else '0'; --tvalid_unsplit_int;
SWALLOW_TDATA : process(clock)
begin
if(clock'EVENT and clock = '1')then
if (sgresetn = '0' or cmd_in = '1') then
tvalid_unsplit <= '0';
status_out_int <= (others => '0');
else
tvalid_unsplit <= tvalid_unsplit_int;
if (tvalid_from_datamover = '1') then
status_out_int (C_DM_STATUS_WIDTH-2 downto 0) <= status_in (C_DM_STATUS_WIDTH-2 downto 0) or status_out_int (C_DM_STATUS_WIDTH-2 downto 0);
else
status_out_int <= status_out_int;
end if;
if (tvalid_unsplit_int = '1') then
status_out_int (C_DM_STATUS_WIDTH-1) <= status_in (C_DM_STATUS_WIDTH-1);
end if;
end if;
end if;
end process SWALLOW_TDATA;
status_out <= status_out_int;
SWALLOW_TLAST_GEN : if C_INCLUDE_S2MM = 0 generate
begin
eof_set <= '1'; --eof_bit when (vsize = vsize_data_int) else '0';
CDC_CMD_PROC1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => cmd_proc_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => cmd_proc_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC2 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => eof_bit_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => eof_bit_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC : process (clock_sec)
begin
if (clock_sec'EVENT and clock_sec = '1') then
if (aresetn = '0') then
-- cmd_proc_cdc_to <= '0';
-- cmd_proc_cdc <= '0';
-- eof_bit_cdc_to <= '0';
-- eof_bit_cdc <= '0';
ready_for_next_cmd_tlast_cdc_from <= '0';
else
-- cmd_proc_cdc_to <= cmd_proc_cdc_from;
-- cmd_proc_cdc <= cmd_proc_cdc_to;
-- eof_bit_cdc_to <= eof_bit_cdc_from;
-- eof_bit_cdc <= eof_bit_cdc_to;
ready_for_next_cmd_tlast_cdc_from <= ready_for_next_cmd_tlast;
end if;
end if;
end process CDC_CMD_PROC;
CDC_CMDTLAST_PROC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => ready_for_next_cmd_tlast_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock,
scndry_resetn => '0',
scndry_out => ready_for_next_cmd_tlast_cdc,
scndry_vect_out => open
);
--CDC_CMDTLAST_PROC : process (clock)
-- begin
-- if (clock'EVENT and clock = '1') then
-- if (sgresetn = '0') then
-- ready_for_next_cmd_tlast_cdc_to <= '0';
-- ready_for_next_cmd_tlast_cdc <= '0';
-- else
-- ready_for_next_cmd_tlast_cdc_to <= ready_for_next_cmd_tlast_cdc_from;
-- ready_for_next_cmd_tlast_cdc <= ready_for_next_cmd_tlast_cdc_to;
-- end if;
-- end if;
--end process CDC_CMDTLAST_PROC;
SWALLOW_TLAST : process(clock_sec)
begin
if(clock_sec'EVENT and clock_sec = '1')then
if(aresetn = '0')then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '0';
reset_lock_tlast <= '1';
ready_for_next_cmd_tlast <= '1';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and vsize_data_int = "00000000000000000000000") then
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '1';
reset_lock_tlast <= '0';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and (counter_tlast < vsize_data_int)) then
counter_tlast <= counter_tlast + '1';
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '0';
reset_lock_tlast <= '0';
elsif ((counter_tlast = vsize_data_int) and (reset_lock_tlast = '0') and (tlast_stream_data = '1' and tready_stream_data = '1')) then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '1';
ready_for_next_cmd_tlast <= '1';
else
counter_tlast <= counter_tlast;
tlast_stream_data_int <= '0';
if (cmd_proc_cdc = '1') then
ready_for_next_cmd_tlast <= '0';
else
ready_for_next_cmd_tlast <= ready_for_next_cmd_tlast;
end if;
end if;
end if;
end process SWALLOW_TLAST;
tlast_unsplit <= tlast_stream_data when (counter_tlast = vsize_data_int and eof_bit_cdc = '1') else '0';
tlast_unsplit_user <= tlast_stream_data when (counter_tlast = vsize_data_int) else '0';
-- tlast_unsplit <= tlast_stream_data; -- when (counter_tlast = vsize_data_int) else '0';
end generate SWALLOW_TLAST_GEN;
SWALLOW_TLAST_GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
eof_set <= eof_bit_cdc_from;
ready_for_next_cmd_tlast_cdc <= '1';
end generate SWALLOW_TLAST_GEN_S2MM;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
entity axi_dma_cmd_split is
generic (
C_ADDR_WIDTH : integer range 32 to 64 := 32;
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
C_INCLUDE_S2MM : integer range 0 to 1 := 0
);
port (
clock : in std_logic;
sgresetn : in std_logic;
clock_sec : in std_logic;
aresetn : in std_logic;
-- command coming from _MNGR
s_axis_cmd_tvalid : in std_logic;
s_axis_cmd_tready : out std_logic;
s_axis_cmd_tdata : in std_logic_vector ((C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);
-- split command to DM
s_axis_cmd_tvalid_s : out std_logic;
s_axis_cmd_tready_s : in std_logic;
s_axis_cmd_tdata_s : out std_logic_vector ((C_ADDR_WIDTH+CMD_BASE_WIDTH+8)-1 downto 0);
-- Tvalid from Datamover
tvalid_from_datamover : in std_logic;
status_in : in std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
tvalid_unsplit : out std_logic;
status_out : out std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
-- Tlast of stream data from Datamover
tlast_stream_data : in std_logic;
tready_stream_data : in std_logic;
tlast_unsplit : out std_logic;
tlast_unsplit_user : out std_logic
);
end entity axi_dma_cmd_split;
architecture implementation of axi_dma_cmd_split is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
type SPLIT_MM2S_STATE_TYPE is (
IDLE,
SEND,
SPLIT
);
signal mm2s_cs : SPLIT_MM2S_STATE_TYPE;
signal mm2s_ns : SPLIT_MM2S_STATE_TYPE;
signal mm2s_cmd : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46-1 downto 0);
signal command_ns : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal command : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal cache_info : std_logic_vector (31 downto 0);
signal vsize_data : std_logic_vector (22 downto 0);
signal vsize_data_int : std_logic_vector (22 downto 0);
signal vsize : std_logic_vector (22 downto 0);
signal counter : std_logic_vector (22 downto 0);
signal counter_tlast : std_logic_vector (22 downto 0);
signal split_cmd : std_logic_vector (31+(C_ADDR_WIDTH-32) downto 0);
signal stride_data : std_logic_vector (22 downto 0);
signal vsize_over : std_logic;
signal cmd_proc_cdc_from : std_logic;
signal cmd_proc_cdc_to : std_logic;
signal cmd_proc_cdc : std_logic;
signal cmd_proc_ns : std_logic;
ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF cmd_proc_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF cmd_proc_cdc : SIGNAL IS "true";
signal cmd_out : std_logic;
signal cmd_out_ns : std_logic;
signal split_out : std_logic;
signal split_out_ns : std_logic;
signal command_valid : std_logic;
signal command_valid_ns : std_logic;
signal command_ready : std_logic;
signal reset_lock : std_logic;
signal reset_lock_tlast : std_logic;
signal tvalid_unsplit_int : std_logic;
signal tlast_stream_data_int : std_logic;
signal ready_for_next_cmd : std_logic;
signal ready_for_next_cmd_tlast : std_logic;
signal ready_for_next_cmd_tlast_cdc_from : std_logic;
signal ready_for_next_cmd_tlast_cdc_to : std_logic;
signal ready_for_next_cmd_tlast_cdc : std_logic;
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc : SIGNAL IS "true";
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal tlast_int : std_logic;
signal eof_bit : std_logic;
signal eof_bit_cdc_from : std_logic;
signal eof_bit_cdc_to : std_logic;
signal eof_bit_cdc : std_logic;
signal eof_set : std_logic;
signal over_ns, over : std_logic;
signal cmd_in : std_logic;
signal status_out_int : std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
begin
s_axis_cmd_tvalid_s <= command_valid;
command_ready <= s_axis_cmd_tready_s;
s_axis_cmd_tdata_s <= command (103+(C_ADDR_WIDTH-32) downto 96+(C_ADDR_WIDTH-32)) & command (71+(C_ADDR_WIDTH-32) downto 0);
REGISTER_STATE_MM2S : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cs <= IDLE;
cmd_proc_cdc_from <= '0';
cmd_out <= '0';
command <= (others => '0');
command_valid <= '0';
split_out <= '0';
over <= '0';
else
mm2s_cs <= mm2s_ns;
cmd_proc_cdc_from <= cmd_proc_ns;
cmd_out <= cmd_out_ns;
command <= command_ns;
command_valid <= command_valid_ns;
split_out <= split_out_ns;
over <= over_ns;
end if;
end if;
end process REGISTER_STATE_MM2S;
-- grab the MM2S command coming from MM2S_mngr
REGISTER_MM2S_CMD : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cmd <= (others => '0');
s_axis_cmd_tready <= '0';
cache_info <= (others => '0');
vsize_data <= (others => '0');
vsize_data_int <= (others => '0');
stride_data <= (others => '0');
eof_bit_cdc_from <= '0';
cmd_in <= '0';
elsif (s_axis_cmd_tvalid = '1' and ready_for_next_cmd = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd_tlast_cdc = '1') then -- when there is no processing being done, means it is ready to accept
mm2s_cmd <= s_axis_cmd_tdata;
s_axis_cmd_tready <= '1';
cache_info <= s_axis_cmd_tdata (149+(C_ADDR_WIDTH-32) downto 118+(C_ADDR_WIDTH-32));
vsize_data <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32));
vsize_data_int <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32)) - '1';
stride_data <= s_axis_cmd_tdata (94+(C_ADDR_WIDTH-32) downto 72+(C_ADDR_WIDTH-32));
eof_bit_cdc_from <= s_axis_cmd_tdata (30);
cmd_in <= '1';
else
mm2s_cmd <= mm2s_cmd; --split_cmd;
vsize_data <= vsize_data;
vsize_data_int <= vsize_data_int;
stride_data <= stride_data;
cache_info <= cache_info;
s_axis_cmd_tready <= '0';
eof_bit_cdc_from <= eof_bit_cdc_from;
cmd_in <= '0';
end if;
end if;
end process REGISTER_MM2S_CMD;
REGISTER_DECR_VSIZE : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
vsize <= "00000000000000000000000";
elsif (command_valid = '1' and command_ready = '1' and (vsize < vsize_data_int)) then -- sending a cmd out to DM
vsize <= vsize + '1';
elsif (cmd_proc_cdc_from = '0') then -- idle or when all cmd are sent to DM
vsize <= "00000000000000000000000";
else
vsize <= vsize;
end if;
end if;
end process REGISTER_DECR_VSIZE;
vsize_over <= '1' when (vsize = vsize_data_int) else '0';
-- eof_set <= eof_bit when (vsize = vsize_data_int) else '0';
REGISTER_SPLIT : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
split_cmd <= (others => '0');
elsif (s_axis_cmd_tvalid = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd = '1' and ready_for_next_cmd_tlast_cdc = '1') then
split_cmd <= s_axis_cmd_tdata (63+(C_ADDR_WIDTH-32) downto 32); -- capture the ba when a new cmd arrives
elsif (split_out = '1') then -- add stride to previous ba
split_cmd <= split_cmd + stride_data;
else
split_cmd <= split_cmd;
end if;
end if;
end process REGISTER_SPLIT;
MM2S_MACHINE : process(mm2s_cs,
s_axis_cmd_tvalid,
cmd_proc_cdc_from,
vsize_over, command_ready,
cache_info, mm2s_cmd,
split_cmd, eof_set,
cmd_in, command
)
begin
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
mm2s_ns <= mm2s_cs;
command_ns <= command;
-- Default signal assignment
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
if (cmd_in = '1' and cmd_proc_cdc_from = '0') then
cmd_proc_ns <= '1'; -- new command has come in and i need to start processing
mm2s_ns <= SEND;
over_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
else
mm2s_ns <= IDLE;
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
end if;
-------------------------------------------------------------------
when SEND =>
cmd_out_ns <= '1';
command_ns <= command;
if (vsize_over = '1' and command_ready = '1') then
mm2s_ns <= IDLE;
cmd_proc_ns <= '1';
command_valid_ns <= '0';
split_out_ns <= '0';
over_ns <= '1';
elsif (command_ready = '0') then --(command_valid = '1' and command_ready = '0') then
mm2s_ns <= SEND;
command_valid_ns <= '1';
cmd_proc_ns <= '1';
split_out_ns <= '0';
over_ns <= '0';
else
mm2s_ns <= SPLIT;
command_valid_ns <= '0';
cmd_proc_ns <= '1';
over_ns <= '0';
split_out_ns <= '0';
end if;
-------------------------------------------------------------------
when SPLIT =>
cmd_proc_ns <= '1';
mm2s_ns <= SEND;
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
cmd_out_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
SWALLOW_TVALID : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
counter <= (others => '0');
-- tvalid_unsplit_int <= '0';
reset_lock <= '1';
ready_for_next_cmd <= '0';
elsif (vsize_data_int = "00000000000000000000000") then
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '1';
reset_lock <= '0';
elsif ((tvalid_from_datamover = '1') and (counter < vsize_data_int)) then
counter <= counter + '1';
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '0';
reset_lock <= '0';
elsif ((counter = vsize_data_int) and (reset_lock = '0') and (tvalid_from_datamover = '1')) then
counter <= (others => '0');
-- tvalid_unsplit_int <= '1';
ready_for_next_cmd <= '1';
else
counter <= counter;
-- tvalid_unsplit_int <= '0';
if (cmd_proc_cdc_from = '1') then
ready_for_next_cmd <= '0';
else
ready_for_next_cmd <= ready_for_next_cmd;
end if;
end if;
end if;
end process SWALLOW_TVALID;
tvalid_unsplit_int <= tvalid_from_datamover when (counter = vsize_data_int) else '0'; --tvalid_unsplit_int;
SWALLOW_TDATA : process(clock)
begin
if(clock'EVENT and clock = '1')then
if (sgresetn = '0' or cmd_in = '1') then
tvalid_unsplit <= '0';
status_out_int <= (others => '0');
else
tvalid_unsplit <= tvalid_unsplit_int;
if (tvalid_from_datamover = '1') then
status_out_int (C_DM_STATUS_WIDTH-2 downto 0) <= status_in (C_DM_STATUS_WIDTH-2 downto 0) or status_out_int (C_DM_STATUS_WIDTH-2 downto 0);
else
status_out_int <= status_out_int;
end if;
if (tvalid_unsplit_int = '1') then
status_out_int (C_DM_STATUS_WIDTH-1) <= status_in (C_DM_STATUS_WIDTH-1);
end if;
end if;
end if;
end process SWALLOW_TDATA;
status_out <= status_out_int;
SWALLOW_TLAST_GEN : if C_INCLUDE_S2MM = 0 generate
begin
eof_set <= '1'; --eof_bit when (vsize = vsize_data_int) else '0';
CDC_CMD_PROC1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => cmd_proc_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => cmd_proc_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC2 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => eof_bit_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => eof_bit_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC : process (clock_sec)
begin
if (clock_sec'EVENT and clock_sec = '1') then
if (aresetn = '0') then
-- cmd_proc_cdc_to <= '0';
-- cmd_proc_cdc <= '0';
-- eof_bit_cdc_to <= '0';
-- eof_bit_cdc <= '0';
ready_for_next_cmd_tlast_cdc_from <= '0';
else
-- cmd_proc_cdc_to <= cmd_proc_cdc_from;
-- cmd_proc_cdc <= cmd_proc_cdc_to;
-- eof_bit_cdc_to <= eof_bit_cdc_from;
-- eof_bit_cdc <= eof_bit_cdc_to;
ready_for_next_cmd_tlast_cdc_from <= ready_for_next_cmd_tlast;
end if;
end if;
end process CDC_CMD_PROC;
CDC_CMDTLAST_PROC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => ready_for_next_cmd_tlast_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock,
scndry_resetn => '0',
scndry_out => ready_for_next_cmd_tlast_cdc,
scndry_vect_out => open
);
--CDC_CMDTLAST_PROC : process (clock)
-- begin
-- if (clock'EVENT and clock = '1') then
-- if (sgresetn = '0') then
-- ready_for_next_cmd_tlast_cdc_to <= '0';
-- ready_for_next_cmd_tlast_cdc <= '0';
-- else
-- ready_for_next_cmd_tlast_cdc_to <= ready_for_next_cmd_tlast_cdc_from;
-- ready_for_next_cmd_tlast_cdc <= ready_for_next_cmd_tlast_cdc_to;
-- end if;
-- end if;
--end process CDC_CMDTLAST_PROC;
SWALLOW_TLAST : process(clock_sec)
begin
if(clock_sec'EVENT and clock_sec = '1')then
if(aresetn = '0')then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '0';
reset_lock_tlast <= '1';
ready_for_next_cmd_tlast <= '1';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and vsize_data_int = "00000000000000000000000") then
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '1';
reset_lock_tlast <= '0';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and (counter_tlast < vsize_data_int)) then
counter_tlast <= counter_tlast + '1';
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '0';
reset_lock_tlast <= '0';
elsif ((counter_tlast = vsize_data_int) and (reset_lock_tlast = '0') and (tlast_stream_data = '1' and tready_stream_data = '1')) then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '1';
ready_for_next_cmd_tlast <= '1';
else
counter_tlast <= counter_tlast;
tlast_stream_data_int <= '0';
if (cmd_proc_cdc = '1') then
ready_for_next_cmd_tlast <= '0';
else
ready_for_next_cmd_tlast <= ready_for_next_cmd_tlast;
end if;
end if;
end if;
end process SWALLOW_TLAST;
tlast_unsplit <= tlast_stream_data when (counter_tlast = vsize_data_int and eof_bit_cdc = '1') else '0';
tlast_unsplit_user <= tlast_stream_data when (counter_tlast = vsize_data_int) else '0';
-- tlast_unsplit <= tlast_stream_data; -- when (counter_tlast = vsize_data_int) else '0';
end generate SWALLOW_TLAST_GEN;
SWALLOW_TLAST_GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
eof_set <= eof_bit_cdc_from;
ready_for_next_cmd_tlast_cdc <= '1';
end generate SWALLOW_TLAST_GEN_S2MM;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
entity axi_dma_cmd_split is
generic (
C_ADDR_WIDTH : integer range 32 to 64 := 32;
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
C_INCLUDE_S2MM : integer range 0 to 1 := 0
);
port (
clock : in std_logic;
sgresetn : in std_logic;
clock_sec : in std_logic;
aresetn : in std_logic;
-- command coming from _MNGR
s_axis_cmd_tvalid : in std_logic;
s_axis_cmd_tready : out std_logic;
s_axis_cmd_tdata : in std_logic_vector ((C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);
-- split command to DM
s_axis_cmd_tvalid_s : out std_logic;
s_axis_cmd_tready_s : in std_logic;
s_axis_cmd_tdata_s : out std_logic_vector ((C_ADDR_WIDTH+CMD_BASE_WIDTH+8)-1 downto 0);
-- Tvalid from Datamover
tvalid_from_datamover : in std_logic;
status_in : in std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
tvalid_unsplit : out std_logic;
status_out : out std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
-- Tlast of stream data from Datamover
tlast_stream_data : in std_logic;
tready_stream_data : in std_logic;
tlast_unsplit : out std_logic;
tlast_unsplit_user : out std_logic
);
end entity axi_dma_cmd_split;
architecture implementation of axi_dma_cmd_split is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
type SPLIT_MM2S_STATE_TYPE is (
IDLE,
SEND,
SPLIT
);
signal mm2s_cs : SPLIT_MM2S_STATE_TYPE;
signal mm2s_ns : SPLIT_MM2S_STATE_TYPE;
signal mm2s_cmd : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46-1 downto 0);
signal command_ns : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal command : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal cache_info : std_logic_vector (31 downto 0);
signal vsize_data : std_logic_vector (22 downto 0);
signal vsize_data_int : std_logic_vector (22 downto 0);
signal vsize : std_logic_vector (22 downto 0);
signal counter : std_logic_vector (22 downto 0);
signal counter_tlast : std_logic_vector (22 downto 0);
signal split_cmd : std_logic_vector (31+(C_ADDR_WIDTH-32) downto 0);
signal stride_data : std_logic_vector (22 downto 0);
signal vsize_over : std_logic;
signal cmd_proc_cdc_from : std_logic;
signal cmd_proc_cdc_to : std_logic;
signal cmd_proc_cdc : std_logic;
signal cmd_proc_ns : std_logic;
ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF cmd_proc_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF cmd_proc_cdc : SIGNAL IS "true";
signal cmd_out : std_logic;
signal cmd_out_ns : std_logic;
signal split_out : std_logic;
signal split_out_ns : std_logic;
signal command_valid : std_logic;
signal command_valid_ns : std_logic;
signal command_ready : std_logic;
signal reset_lock : std_logic;
signal reset_lock_tlast : std_logic;
signal tvalid_unsplit_int : std_logic;
signal tlast_stream_data_int : std_logic;
signal ready_for_next_cmd : std_logic;
signal ready_for_next_cmd_tlast : std_logic;
signal ready_for_next_cmd_tlast_cdc_from : std_logic;
signal ready_for_next_cmd_tlast_cdc_to : std_logic;
signal ready_for_next_cmd_tlast_cdc : std_logic;
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc : SIGNAL IS "true";
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal tlast_int : std_logic;
signal eof_bit : std_logic;
signal eof_bit_cdc_from : std_logic;
signal eof_bit_cdc_to : std_logic;
signal eof_bit_cdc : std_logic;
signal eof_set : std_logic;
signal over_ns, over : std_logic;
signal cmd_in : std_logic;
signal status_out_int : std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
begin
s_axis_cmd_tvalid_s <= command_valid;
command_ready <= s_axis_cmd_tready_s;
s_axis_cmd_tdata_s <= command (103+(C_ADDR_WIDTH-32) downto 96+(C_ADDR_WIDTH-32)) & command (71+(C_ADDR_WIDTH-32) downto 0);
REGISTER_STATE_MM2S : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cs <= IDLE;
cmd_proc_cdc_from <= '0';
cmd_out <= '0';
command <= (others => '0');
command_valid <= '0';
split_out <= '0';
over <= '0';
else
mm2s_cs <= mm2s_ns;
cmd_proc_cdc_from <= cmd_proc_ns;
cmd_out <= cmd_out_ns;
command <= command_ns;
command_valid <= command_valid_ns;
split_out <= split_out_ns;
over <= over_ns;
end if;
end if;
end process REGISTER_STATE_MM2S;
-- grab the MM2S command coming from MM2S_mngr
REGISTER_MM2S_CMD : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cmd <= (others => '0');
s_axis_cmd_tready <= '0';
cache_info <= (others => '0');
vsize_data <= (others => '0');
vsize_data_int <= (others => '0');
stride_data <= (others => '0');
eof_bit_cdc_from <= '0';
cmd_in <= '0';
elsif (s_axis_cmd_tvalid = '1' and ready_for_next_cmd = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd_tlast_cdc = '1') then -- when there is no processing being done, means it is ready to accept
mm2s_cmd <= s_axis_cmd_tdata;
s_axis_cmd_tready <= '1';
cache_info <= s_axis_cmd_tdata (149+(C_ADDR_WIDTH-32) downto 118+(C_ADDR_WIDTH-32));
vsize_data <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32));
vsize_data_int <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32)) - '1';
stride_data <= s_axis_cmd_tdata (94+(C_ADDR_WIDTH-32) downto 72+(C_ADDR_WIDTH-32));
eof_bit_cdc_from <= s_axis_cmd_tdata (30);
cmd_in <= '1';
else
mm2s_cmd <= mm2s_cmd; --split_cmd;
vsize_data <= vsize_data;
vsize_data_int <= vsize_data_int;
stride_data <= stride_data;
cache_info <= cache_info;
s_axis_cmd_tready <= '0';
eof_bit_cdc_from <= eof_bit_cdc_from;
cmd_in <= '0';
end if;
end if;
end process REGISTER_MM2S_CMD;
REGISTER_DECR_VSIZE : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
vsize <= "00000000000000000000000";
elsif (command_valid = '1' and command_ready = '1' and (vsize < vsize_data_int)) then -- sending a cmd out to DM
vsize <= vsize + '1';
elsif (cmd_proc_cdc_from = '0') then -- idle or when all cmd are sent to DM
vsize <= "00000000000000000000000";
else
vsize <= vsize;
end if;
end if;
end process REGISTER_DECR_VSIZE;
vsize_over <= '1' when (vsize = vsize_data_int) else '0';
-- eof_set <= eof_bit when (vsize = vsize_data_int) else '0';
REGISTER_SPLIT : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
split_cmd <= (others => '0');
elsif (s_axis_cmd_tvalid = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd = '1' and ready_for_next_cmd_tlast_cdc = '1') then
split_cmd <= s_axis_cmd_tdata (63+(C_ADDR_WIDTH-32) downto 32); -- capture the ba when a new cmd arrives
elsif (split_out = '1') then -- add stride to previous ba
split_cmd <= split_cmd + stride_data;
else
split_cmd <= split_cmd;
end if;
end if;
end process REGISTER_SPLIT;
MM2S_MACHINE : process(mm2s_cs,
s_axis_cmd_tvalid,
cmd_proc_cdc_from,
vsize_over, command_ready,
cache_info, mm2s_cmd,
split_cmd, eof_set,
cmd_in, command
)
begin
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
mm2s_ns <= mm2s_cs;
command_ns <= command;
-- Default signal assignment
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
if (cmd_in = '1' and cmd_proc_cdc_from = '0') then
cmd_proc_ns <= '1'; -- new command has come in and i need to start processing
mm2s_ns <= SEND;
over_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
else
mm2s_ns <= IDLE;
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
end if;
-------------------------------------------------------------------
when SEND =>
cmd_out_ns <= '1';
command_ns <= command;
if (vsize_over = '1' and command_ready = '1') then
mm2s_ns <= IDLE;
cmd_proc_ns <= '1';
command_valid_ns <= '0';
split_out_ns <= '0';
over_ns <= '1';
elsif (command_ready = '0') then --(command_valid = '1' and command_ready = '0') then
mm2s_ns <= SEND;
command_valid_ns <= '1';
cmd_proc_ns <= '1';
split_out_ns <= '0';
over_ns <= '0';
else
mm2s_ns <= SPLIT;
command_valid_ns <= '0';
cmd_proc_ns <= '1';
over_ns <= '0';
split_out_ns <= '0';
end if;
-------------------------------------------------------------------
when SPLIT =>
cmd_proc_ns <= '1';
mm2s_ns <= SEND;
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
cmd_out_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
SWALLOW_TVALID : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
counter <= (others => '0');
-- tvalid_unsplit_int <= '0';
reset_lock <= '1';
ready_for_next_cmd <= '0';
elsif (vsize_data_int = "00000000000000000000000") then
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '1';
reset_lock <= '0';
elsif ((tvalid_from_datamover = '1') and (counter < vsize_data_int)) then
counter <= counter + '1';
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '0';
reset_lock <= '0';
elsif ((counter = vsize_data_int) and (reset_lock = '0') and (tvalid_from_datamover = '1')) then
counter <= (others => '0');
-- tvalid_unsplit_int <= '1';
ready_for_next_cmd <= '1';
else
counter <= counter;
-- tvalid_unsplit_int <= '0';
if (cmd_proc_cdc_from = '1') then
ready_for_next_cmd <= '0';
else
ready_for_next_cmd <= ready_for_next_cmd;
end if;
end if;
end if;
end process SWALLOW_TVALID;
tvalid_unsplit_int <= tvalid_from_datamover when (counter = vsize_data_int) else '0'; --tvalid_unsplit_int;
SWALLOW_TDATA : process(clock)
begin
if(clock'EVENT and clock = '1')then
if (sgresetn = '0' or cmd_in = '1') then
tvalid_unsplit <= '0';
status_out_int <= (others => '0');
else
tvalid_unsplit <= tvalid_unsplit_int;
if (tvalid_from_datamover = '1') then
status_out_int (C_DM_STATUS_WIDTH-2 downto 0) <= status_in (C_DM_STATUS_WIDTH-2 downto 0) or status_out_int (C_DM_STATUS_WIDTH-2 downto 0);
else
status_out_int <= status_out_int;
end if;
if (tvalid_unsplit_int = '1') then
status_out_int (C_DM_STATUS_WIDTH-1) <= status_in (C_DM_STATUS_WIDTH-1);
end if;
end if;
end if;
end process SWALLOW_TDATA;
status_out <= status_out_int;
SWALLOW_TLAST_GEN : if C_INCLUDE_S2MM = 0 generate
begin
eof_set <= '1'; --eof_bit when (vsize = vsize_data_int) else '0';
CDC_CMD_PROC1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => cmd_proc_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => cmd_proc_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC2 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => eof_bit_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => eof_bit_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC : process (clock_sec)
begin
if (clock_sec'EVENT and clock_sec = '1') then
if (aresetn = '0') then
-- cmd_proc_cdc_to <= '0';
-- cmd_proc_cdc <= '0';
-- eof_bit_cdc_to <= '0';
-- eof_bit_cdc <= '0';
ready_for_next_cmd_tlast_cdc_from <= '0';
else
-- cmd_proc_cdc_to <= cmd_proc_cdc_from;
-- cmd_proc_cdc <= cmd_proc_cdc_to;
-- eof_bit_cdc_to <= eof_bit_cdc_from;
-- eof_bit_cdc <= eof_bit_cdc_to;
ready_for_next_cmd_tlast_cdc_from <= ready_for_next_cmd_tlast;
end if;
end if;
end process CDC_CMD_PROC;
CDC_CMDTLAST_PROC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => ready_for_next_cmd_tlast_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock,
scndry_resetn => '0',
scndry_out => ready_for_next_cmd_tlast_cdc,
scndry_vect_out => open
);
--CDC_CMDTLAST_PROC : process (clock)
-- begin
-- if (clock'EVENT and clock = '1') then
-- if (sgresetn = '0') then
-- ready_for_next_cmd_tlast_cdc_to <= '0';
-- ready_for_next_cmd_tlast_cdc <= '0';
-- else
-- ready_for_next_cmd_tlast_cdc_to <= ready_for_next_cmd_tlast_cdc_from;
-- ready_for_next_cmd_tlast_cdc <= ready_for_next_cmd_tlast_cdc_to;
-- end if;
-- end if;
--end process CDC_CMDTLAST_PROC;
SWALLOW_TLAST : process(clock_sec)
begin
if(clock_sec'EVENT and clock_sec = '1')then
if(aresetn = '0')then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '0';
reset_lock_tlast <= '1';
ready_for_next_cmd_tlast <= '1';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and vsize_data_int = "00000000000000000000000") then
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '1';
reset_lock_tlast <= '0';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and (counter_tlast < vsize_data_int)) then
counter_tlast <= counter_tlast + '1';
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '0';
reset_lock_tlast <= '0';
elsif ((counter_tlast = vsize_data_int) and (reset_lock_tlast = '0') and (tlast_stream_data = '1' and tready_stream_data = '1')) then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '1';
ready_for_next_cmd_tlast <= '1';
else
counter_tlast <= counter_tlast;
tlast_stream_data_int <= '0';
if (cmd_proc_cdc = '1') then
ready_for_next_cmd_tlast <= '0';
else
ready_for_next_cmd_tlast <= ready_for_next_cmd_tlast;
end if;
end if;
end if;
end process SWALLOW_TLAST;
tlast_unsplit <= tlast_stream_data when (counter_tlast = vsize_data_int and eof_bit_cdc = '1') else '0';
tlast_unsplit_user <= tlast_stream_data when (counter_tlast = vsize_data_int) else '0';
-- tlast_unsplit <= tlast_stream_data; -- when (counter_tlast = vsize_data_int) else '0';
end generate SWALLOW_TLAST_GEN;
SWALLOW_TLAST_GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
eof_set <= eof_bit_cdc_from;
ready_for_next_cmd_tlast_cdc <= '1';
end generate SWALLOW_TLAST_GEN_S2MM;
end implementation;
|
-------------------------------------------------------------------------------
-- Title : mb_model
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Instruction level model of the microblaze
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mb_model is
generic (
g_io_mask : unsigned(31 downto 0) := X"FC000000" );
port (
clock : in std_logic;
reset : in std_logic;
io_addr : out unsigned(31 downto 0);
io_write : out std_logic;
io_read : out std_logic;
io_byte_en : out std_logic_vector(3 downto 0);
io_wdata : out std_logic_vector(31 downto 0);
io_rdata : in std_logic_vector(31 downto 0);
io_ack : in std_logic );
end entity;
architecture bfm of mb_model is
type t_word_array is array(natural range <>) of std_logic_vector(31 downto 0);
type t_signed_array is array(natural range <>) of signed(31 downto 0);
constant c_memory_size_bytes : natural := 20; -- 1 MB
constant c_memory_size_words : natural := c_memory_size_bytes - 2;
shared variable reg : t_signed_array(0 to 31) := (others => (others => '0'));
shared variable imem : t_word_array(0 to 2**c_memory_size_words -1);
alias dmem : t_word_array(0 to 2**c_memory_size_words -1) is imem;
signal pc_reg : unsigned(31 downto 0);
signal C_flag : std_logic;
signal I_flag : std_logic;
signal B_flag : std_logic;
signal D_flag : std_logic;
constant p : string := "PC: ";
constant i : string := ", Inst: ";
constant c : string := ", ";
constant ras : string := ", Ra=";
constant rbs : string := ", Rb=";
constant rds : string := ", Rd=";
impure function get_msr(len : natural) return std_logic_vector is
variable msr : std_logic_vector(31 downto 0);
begin
msr := (31 => C_flag,
3 => B_flag,
2 => C_flag,
1 => I_flag,
others => '0' );
return msr(len-1 downto 0);
end function;
function to_std(b : boolean) return std_logic is
begin
if b then return '1'; end if;
return '0';
end function;
begin
process
variable new_pc : unsigned(31 downto 0);
variable do_delay : std_logic := '0';
variable imm : signed(31 downto 0);
variable imm_lock : std_logic := '0';
variable ra : integer range 0 to 31;
variable rb : integer range 0 to 31;
variable rd : integer range 0 to 31;
procedure dbPrint(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); str : string) is
variable s : line;
begin
write(s, p);
write(s, hstr(pc));
write(s, i);
write(s, hstr(inst));
write(s, ras);
write(s, hstr(unsigned(reg(ra))));
write(s, rbs);
write(s, hstr(unsigned(reg(rb))));
write(s, rds);
write(s, hstr(unsigned(reg(rd))));
write(s, c);
write(s, str);
-- writeline(output, s);
end procedure;
procedure set_msr(a : std_logic_vector(13 downto 0)) is
begin
B_flag <= a(3);
C_flag <= a(2);
I_flag <= a(1);
end procedure;
procedure perform_add(a, b : signed(31 downto 0); carry : std_logic; upd_c : boolean) is
variable t33: signed(32 downto 0);
begin
if carry = '1' then
t33 := ('0' & a) + ('0' & b) + 1;
else
t33 := ('0' & a) + ('0' & b);
end if;
reg(rd) := t33(31 downto 0);
if upd_c then
C_flag <= t33(32);
end if;
end procedure;
procedure illegal(pc : unsigned) is
begin
report "Illegal instruction @ " & hstr(pc)
severity error;
end procedure;
procedure unimplemented(msg : string) is
begin
report msg;
end procedure;
procedure do_branch(pc : unsigned(31 downto 0); offset : signed(31 downto 0); delay, absolute, link : std_logic; chk : integer) is
variable take : boolean;
begin
case chk is
when 0 => take := (reg(ra) = 0);
when 1 => take := (reg(ra) /= 0);
when 2 => take := (reg(ra) < 0);
when 3 => take := (reg(ra) <= 0);
when 4 => take := (reg(ra) > 0);
when 5 => take := (reg(ra) >= 0);
when others => take := true;
end case;
if link='1' then
reg(rd) := signed(pc);
end if;
if take then
if absolute='1' then
new_pc := unsigned(offset);
else
new_pc := unsigned(signed(pc) + offset);
end if;
end if; -- else: default: new_pc := pc + 4;
if take then
do_delay := delay;
end if;
end procedure;
function is_io(addr : unsigned(31 downto 0)) return boolean is
begin
return (addr and g_io_mask) /= 0;
end function;
procedure load_byte(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_read <= '1';
io_addr <= unsigned(addr);
case addr(1 downto 0) is
when "00" => io_byte_en <= "1000";
when "01" => io_byte_en <= "0100";
when "10" => io_byte_en <= "0010";
when "11" => io_byte_en <= "0001";
when others => io_byte_en <= "0000";
end case;
wait until clock='1';
io_read <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
loaded := io_rdata;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
end if;
data := (others => '0');
case addr(1 downto 0) is
when "00" => data(7 downto 0) := loaded(31 downto 24);
when "01" => data(7 downto 0) := loaded(23 downto 16);
when "10" => data(7 downto 0) := loaded(15 downto 8);
when "11" => data(7 downto 0) := loaded(7 downto 0);
when others => data := (others => 'X');
end case;
end procedure;
procedure load_half(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_read <= '1';
io_addr <= unsigned(addr);
io_byte_en <= (others => '0');
case addr(1 downto 0) is
when "00" => io_byte_en <= "1100";
when "10" => io_byte_en <= "0011";
when others => null;
end case;
wait until clock='1';
io_read <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
loaded := io_rdata;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
end if;
data := (others => '0');
case addr(1 downto 0) is
when "00" => data(15 downto 0) := loaded(31 downto 16);
when "10" => data(15 downto 0) := loaded(15 downto 0);
when others => report "Unalligned halfword read" severity error;
end case;
end procedure;
procedure load_word(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_read <= '1';
io_addr <= unsigned(addr);
io_byte_en <= (others => '1');
wait until clock='1';
io_read <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
loaded := io_rdata;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
end if;
data := loaded;
assert addr(1 downto 0) = "00"
report "Unalligned dword read" severity error;
end procedure;
procedure store_byte(addr : unsigned(31 downto 0); data : std_logic_vector(7 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_write <= '1';
io_addr <= unsigned(addr);
io_wdata <= data & data & data & data;
case addr(1 downto 0) is
when "00" => io_byte_en <= "1000";
when "01" => io_byte_en <= "0100";
when "10" => io_byte_en <= "0010";
when "11" => io_byte_en <= "0001";
when others => io_byte_en <= "0000";
end case;
wait until clock='1';
io_write <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
case addr(1 downto 0) is
when "00" => loaded(31 downto 24) := data;
when "01" => loaded(23 downto 16) := data;
when "10" => loaded(15 downto 8) := data;
when "11" => loaded(7 downto 0) := data;
when others => null;
end case;
dmem(to_integer(addr(c_memory_size_bytes-1 downto 2))) := loaded;
end if;
end procedure;
procedure store_half(addr : unsigned(31 downto 0); data : std_logic_vector(15 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_write <= '1';
io_addr <= unsigned(addr);
io_wdata <= data & data;
case addr(1 downto 0) is
when "00" => io_byte_en <= "1100";
when "10" => io_byte_en <= "0011";
when others => io_byte_en <= "0000";
end case;
wait until clock='1';
io_write <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
case addr(1 downto 0) is
when "00" => loaded(31 downto 16) := data;
when "10" => loaded(15 downto 0) := data;
when others => report "Unalligned halfword write" severity error;
end case;
dmem(to_integer(addr(c_memory_size_bytes-1 downto 2))) := loaded;
end if;
assert addr(0) = '0'
report "Unalligned halfword write" severity error;
end procedure;
procedure store_word(addr : unsigned(31 downto 0); data : std_logic_vector(31 downto 0)) is
begin
if is_io(addr) then
io_write <= '1';
io_addr <= unsigned(addr);
io_wdata <= data;
io_byte_en <= "1111";
wait until clock='1';
io_write <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
else
dmem(to_integer(addr(c_memory_size_bytes-1 downto 2))) := data;
end if;
assert addr(1 downto 0) = "00"
report "Unalligned dword write" severity error;
end procedure;
procedure check_zero(a : std_logic_vector) is
begin
assert unsigned(a) = 0
report "Modifier bits not zero.. Illegal instruction?"
severity warning;
end procedure;
procedure dbPrint3(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); s : string) is
begin
dbPrint(pc, inst, s & "R" & str(rd) & ", R" & str(ra) & ", R" & str(rb));
end procedure;
procedure dbPrint2(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); s : string) is
begin
dbPrint(pc, inst, s & "R" & str(rd) & ", R" & str(ra));
end procedure;
procedure dbPrint2i(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); s : string) is
begin
dbPrint(pc, inst, s & "R" & str(rd) & ", R" & str(ra) & ", 0x" & hstr(unsigned(imm)));
end procedure;
procedure dbPrintBr(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); delay, absolute, link, immediate : std_logic; chk : integer) is
variable base : string(1 to 6) := " ";
variable n : integer := 4;
begin
case chk is
when 0 => base(1 to 3) := "BEQ";
when 1 => base(1 to 3) := "BNE";
when 2 => base(1 to 3) := "BLT";
when 3 => base(1 to 3) := "BLE";
when 4 => base(1 to 3) := "BGT";
when 5 => base(1 to 3) := "BGE";
when others => base(1 to 2) := "BR"; n := 3;
end case;
if absolute='1' then base(n) := 'A'; n := n + 1; end if;
if link='1' then base(n) := 'L'; n := n + 1; end if;
if immediate='1' then base(n) := 'I'; n := n + 1; end if;
if delay='1' then base(n) := 'D'; n := n + 1; end if;
if link='1' then
dbPrint(pc, inst, base & " R" & str(rd) & " => " & hstr(new_pc));
elsif chk = 15 then
dbPrint(pc, inst, base & " => " & hstr(new_pc));
else
dbPrint(pc, inst, base & " R" & str(ra) & " => " & hstr(new_pc));
end if;
end procedure;
procedure execute_instruction(pc : unsigned(31 downto 0)) is
variable inst : std_logic_vector(31 downto 0);
variable data : std_logic_vector(31 downto 0);
variable temp : std_logic;
begin
inst := imem(to_integer(pc(c_memory_size_bytes-1 downto 2)));
rd := to_integer(unsigned(inst(25 downto 21)));
ra := to_integer(unsigned(inst(20 downto 16)));
rb := to_integer(unsigned(inst(15 downto 11)));
reg(0) := (others => '0');
imm(15 downto 0) := signed(inst(15 downto 0));
if imm_lock='0' then
imm(31 downto 16) := (others => inst(15)); -- sign extend
end if;
imm_lock := '0';
io_write <= '0';
io_read <= '0';
io_addr <= (others => '0');
io_byte_en <= (others => '0');
new_pc := pc + 4;
case inst(31 downto 26) is
when "000000" => -- ADD Rd,Ra,Rb
dbPrint3(pc, inst, "ADD ");
perform_add(reg(ra), reg(rb), '0', true);
check_zero(inst(10 downto 0));
when "000001" => -- RSUB Rd,Ra,Rb
dbPrint3(pc, inst, "RSUB ");
perform_add(not reg(ra), reg(rb), '1', true);
check_zero(inst(10 downto 0));
when "000010" => -- ADDC Rd,Ra,Rb
dbPrint3(pc, inst, "ADDC ");
perform_add(reg(ra), reg(rb), C_flag, true);
check_zero(inst(10 downto 0));
when "000011" => -- RSUBC Rd,Ra,Rb
dbPrint3(pc, inst, "RSUBC ");
perform_add(not reg(ra), reg(rb), C_flag, true);
check_zero(inst(10 downto 0));
when "000100" => -- ADDK Rd,Ra,Rb
dbPrint3(pc, inst, "ADDK ");
perform_add(reg(ra), reg(rb), '0', false);
check_zero(inst(10 downto 0));
when "000101" => -- RSUBK Rd,Ra,Rb / CMP Rd,Ra,Rb / CMPU Rd,Ra,Rb
if inst(1 downto 0) = "01" then -- CMP
dbPrint3(pc, inst, "CMP ");
temp := not to_std(signed(reg(rb)) >= signed(reg(ra)));
perform_add(not reg(ra), reg(rb), '1', false);
reg(rd)(31) := temp;
elsif inst(1 downto 0) = "11" then -- CMPU
dbPrint3(pc, inst, "CMPU ");
temp := not to_std(unsigned(reg(rb)) >= unsigned(reg(ra)));
perform_add(not reg(ra), reg(rb), '1', false);
reg(rd)(31) := temp;
else
dbPrint3(pc, inst, "RSUBK ");
perform_add(not reg(ra), reg(rb), '1', false);
end if;
check_zero(inst(10 downto 2));
when "000110" => -- ADDKC Rd,Ra,Rb
dbPrint3(pc, inst, "ADDKC ");
perform_add(reg(ra), reg(rb), C_flag, false);
check_zero(inst(10 downto 0));
when "000111" => -- RSUBKC Rd,Ra,Rb
dbPrint3(pc, inst, "RSUBKC ");
perform_add(not reg(ra), reg(rb), C_flag, false);
when "001000" => -- ADDI Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDI ");
perform_add(reg(ra), imm, '0', true);
when "001001" => -- RSUBI Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBI ");
perform_add(not reg(ra), imm, '1', true);
when "001010" => -- ADDIC Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDIC ");
perform_add(reg(ra), imm, C_flag, true);
when "001011" => -- RSUBIC Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBIC ");
perform_add(not reg(ra), imm, C_flag, true);
when "001100" => -- ADDIK Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDIK ");
perform_add(reg(ra), imm, '0', false);
when "001101" => -- RSUBIK Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBIK ");
perform_add(not reg(ra), imm, '1', false);
when "001110" => -- ADDIKC Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDIKC ");
perform_add(reg(ra), imm, C_flag, false);
when "001111" => -- RSUBIKC Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBIKC ");
perform_add(not reg(ra), imm, C_flag, false);
when "010000" => -- MUL/MULH/MULHSU/MULHU Rd,Ra,Rb
unimplemented("MUL/MULH/MULHSU/MULHU Rd,Ra,Rb");
when "010001" => -- BSRA Rd,Ra,Rb / BSLL Rd,Ra,Rb (Barrel shift)
unimplemented("BSRA Rd,Ra,Rb / BSLL Rd,Ra,Rb (Barrel shift)");
when "010010" => -- IDIV Rd,Ra,Rb / IDIVU Rd,Ra,Rb
unimplemented("IDIV Rd,Ra,Rb / IDIVU Rd,Ra,Rb");
when "010011" => --
illegal(pc);
when "010100" => --
illegal(pc);
when "010101" => --
illegal(pc);
when "010110" => --
illegal(pc);
when "010111" => --
illegal(pc);
when "011000" => -- MULI Rd,Ra,Imm
unimplemented("MULI Rd,Ra,Imm");
when "011001" => -- BSRLI Rd,Ra,Imm / BSRAI Rd,Ra,Imm / BSLLI Rd,Ra,Imm
unimplemented("BSRLI Rd,Ra,Imm / BSRAI Rd,Ra,Imm / BSLLI Rd,Ra,Imm");
when "011010" => --
illegal(pc);
when "011011" => --
illegal(pc);
when "011100" => --
illegal(pc);
when "011101" => --
illegal(pc);
when "011110" => --
illegal(pc);
when "011111" => --
illegal(pc);
when "100000" => -- OR Rd,Ra,Rb / PCMPBF Rd,Ra,Rb
if inst(10)='1' then
unimplemented("PCMPBF Rd,Ra,Rb");
else
dbPrint3(pc, inst, "OR ");
reg(rd) := reg(ra) or reg(rb);
end if;
check_zero(inst(9 downto 0));
when "100001" => -- AND Rd,Ra,Rb
dbPrint3(pc, inst, "AND ");
reg(rd) := reg(ra) and reg(rb);
check_zero(inst(10 downto 0));
when "100010" => -- XOR Rd,Ra,Rb / PCMPEQ Rd,Ra,Rb
if inst(10)='1' then
unimplemented("PCMPEQ Rd,Ra,Rb");
else
dbPrint3(pc, inst, "XOR ");
reg(rd) := reg(ra) xor reg(rb);
end if;
check_zero(inst(9 downto 0));
when "100011" => -- ANDN Rd,Ra,Rb/ PCMPNE Rd,Ra,Rb
if inst(10)='1' then
unimplemented("PCMPNE Rd,Ra,Rb");
else
dbPrint3(pc, inst, "ANDN ");
reg(rd) := reg(ra) and not reg(rb);
end if;
check_zero(inst(9 downto 0));
when "100100" => -- SRA Rd,Ra / SRC Rd,Ra / SRL Rd,Ra/ SEXT8 Rd,Ra / SEXT16 Rd,Ra
case inst(15 downto 0) is
when X"0001" => -- SRA
dbPrint2(pc, inst, "SRA ");
C_flag <= reg(ra)(0);
reg(rd) := reg(ra)(31) & reg(ra)(31 downto 1);
when X"0021" => -- SRC
dbPrint2(pc, inst, "SRC ");
C_flag <= reg(ra)(0);
reg(rd) := C_flag & reg(ra)(31 downto 1);
when X"0041" => -- SRL
dbPrint2(pc, inst, "SRL ");
C_flag <= reg(ra)(0);
reg(rd) := '0' & reg(ra)(31 downto 1);
when X"0060" => -- SEXT8
dbPrint2(pc, inst, "SEXT8 ");
reg(rd)(31 downto 8) := (others => reg(ra)(7));
reg(rd)(7 downto 0) := reg(ra)(7 downto 0);
when X"0061" => -- SEXT16
dbPrint2(pc, inst, "SEXT16 ");
reg(rd)(31 downto 16) := (others => reg(ra)(15));
reg(rd)(15 downto 0) := reg(ra)(15 downto 0);
when others =>
illegal(pc);
end case;
when "100101" => -- MTS Sd,Ra / MFS Rd,Sa / MSRCLR Rd,Imm / MSRSET Rd,Imm
case inst(15 downto 14) is
when "00" => -- SET/CLR
reg(rd) := get_msr(32);
if inst(16)='0' then -- set
dbPrint(pc, inst, "MSRSET R" & str(rd) & ", " & hstr(inst(13 downto 0)));
set_msr(get_msr(14) or inst(13 downto 0));
else -- clear
dbPrint(pc, inst, "MSRCLR R" & str(rd) & ", " & hstr(inst(13 downto 0)));
set_msr(get_msr(14) and not inst(13 downto 0));
end if;
when "10" => -- MFS (read)
dbPrint(pc, inst, "MFS R" & str(rd) & ", " & hstr(inst(13 downto 0)));
case inst(15 downto 0) is
when X"4000" =>
reg(rd) := signed(pc);
when X"4001" =>
reg(rd) := signed(get_msr(32));
when others =>
unimplemented("MFS register type " & hstr(inst(13 downto 0)));
end case;
check_zero(inst(20 downto 16));
when "11" => -- MTS (write)
dbPrint(pc, inst, "MTS R" & str(rd) & ", " & hstr(inst(13 downto 0)));
case inst(15 downto 0) is
when X"C001" =>
set_msr(std_logic_vector(reg(ra)(13 downto 0)));
when others =>
unimplemented("MTS register type " & hstr(inst(13 downto 0)));
end case;
when others =>
illegal(pc);
end case;
when "100110" => -- BR(A)(L)(D) (Rb,)Rb / BRK Rd,Rb
do_branch(pc => pc, offset => reg(rb), delay => inst(20), absolute => inst(19), link => inst(18), chk => 15);
dbPrintBr(pc => pc, inst => inst, delay => inst(20), absolute => inst(19), link => inst(18), immediate => '0', chk => 15);
if (inst(20 downto 18) = "011") then
B_flag <= '1';
end if;
check_zero(inst(10 downto 0));
when "100111" => -- Bxx Ra,Rb (Rd = type of branch)
do_branch(pc => pc, offset => reg(rb), delay => inst(25), absolute => '0', link => '0', chk => to_integer(unsigned(inst(23 downto 21))));
dbPrintBr(pc => pc, inst => inst, delay => inst(25), absolute => '0', link => '0', immediate => '0', chk => to_integer(unsigned(inst(23 downto 21))));
check_zero(inst(10 downto 0));
when "101000" => -- ORI Rd,Ra,Imm
dbPrint2i(pc, inst, "ORI ");
reg(rd) := reg(ra) or imm;
when "101001" => -- ANDI Rd,Ra,Imm
dbPrint2i(pc, inst, "ANDI ");
reg(rd) := reg(ra) and imm;
when "101010" => -- XORI Rd,Ra,Imm
dbPrint2i(pc, inst, "XORI ");
reg(rd) := reg(ra) xor imm;
when "101011" => -- ANDNI Rd,Ra,Imm
dbPrint2i(pc, inst, "ANDNI ");
reg(rd) := reg(ra) and not imm;
when "101100" => -- IMM Imm
dbPrint(pc, inst, "IMM " & hstr(inst(15 downto 0)));
imm(31 downto 16) := signed(inst(15 downto 0));
imm_lock := '1';
check_zero(inst(25 downto 16));
when "101101" => -- RTSD Ra,Imm / RTID Ra,Imm / RTBD Ra,Imm / RTED Ra,Imm
case inst(25 downto 21) is
when "10000" =>
dbPrint(pc, inst, "RTSD R" & str(ra) & ", " & str(to_integer(imm)));
null;
when "10001" =>
dbPrint(pc, inst, "RTID R" & str(ra) & ", " & str(to_integer(imm)));
I_flag <= '1';
when "10010" =>
dbPrint(pc, inst, "RTBD R" & str(ra) & ", " & str(to_integer(imm)));
B_flag <= '0';
when "10100" =>
unimplemented("Return from exception RTED");
when others =>
illegal(pc);
end case;
new_pc := unsigned(reg(ra) + imm);
do_delay := '1';
when "101110" => -- BR(A)(L)I(D) Imm Ra / BRKI Rd,Imm
do_branch(pc => pc, offset => imm, delay => inst(20), absolute => inst(19), link => inst(18), chk => 15);
dbPrintBr(pc => pc, inst => inst, delay => inst(20), absolute => inst(19), link => inst(18), immediate => '1', chk => 15);
if (inst(20 downto 18) = "011") then
B_flag <= '1';
end if;
when "101111" => -- BxxI Ra,Imm (Rd = type of branch)
do_branch(pc => pc, offset => imm, delay => inst(25), absolute => '0', link => '0', chk => to_integer(unsigned(inst(23 downto 21))));
dbPrintBr(pc => pc, inst => inst, delay => inst(25), absolute => '0', link => '0', immediate => '1', chk => to_integer(unsigned(inst(23 downto 21))));
when "110000" => -- LBU Rd,Ra,Rb
dbPrint3(pc, inst, "LBU ");
load_byte(unsigned(reg(ra) + reg(rb)), data);
reg(rd) := signed(data);
check_zero(inst(10 downto 0));
when "110001" => -- LHU Rd,Ra,Rb
dbPrint3(pc, inst, "LHU ");
load_half(unsigned(reg(ra) + reg(rb)), data);
reg(rd) := signed(data);
check_zero(inst(10 downto 0));
when "110010" => -- LW Rd,Ra,Rb
dbPrint3(pc, inst, "LW ");
load_word(unsigned(reg(ra) + reg(rb)), data);
reg(rd) := signed(data);
check_zero(inst(10 downto 0));
when "110011" => --
illegal(pc);
when "110100" => -- SB Rd,Ra,Rb
dbPrint3(pc, inst, "SB ");
store_byte(unsigned(reg(ra) + reg(rb)), std_logic_vector(reg(rd)(7 downto 0)));
check_zero(inst(10 downto 0));
when "110101" => -- SH Rd,Ra,Rb
dbPrint3(pc, inst, "SH ");
store_half(unsigned(reg(ra) + reg(rb)), std_logic_vector(reg(rd)(15 downto 0)));
check_zero(inst(10 downto 0));
when "110110" => -- SW Rd,Ra,Rb
dbPrint3(pc, inst, "SW ");
store_word(unsigned(reg(ra) + reg(rb)), std_logic_vector(reg(rd)));
check_zero(inst(10 downto 0));
when "110111" => --
illegal(pc);
when "111000" => -- LBUI Rd,Ra,Imm
dbPrint2i(pc, inst, "LBUI ");
load_byte(unsigned(reg(ra) + imm), data);
reg(rd) := signed(data);
when "111001" => -- LHUI Rd,Ra,Imm
dbPrint2i(pc, inst, "LHUI ");
load_half(unsigned(reg(ra) + imm), data);
reg(rd) := signed(data);
when "111010" => -- LWI Rd,Ra,Imm
dbPrint2i(pc, inst, "LWI ");
load_word(unsigned(reg(ra) + imm), data);
reg(rd) := signed(data);
when "111011" => --
illegal(pc);
when "111100" => -- SBI Rd,Ra,Imm
dbPrint2i(pc, inst, "SBI ");
store_byte(unsigned(reg(ra) + imm), std_logic_vector(reg(rd)(7 downto 0)));
when "111101" => -- SHI Rd,Ra,Imm
dbPrint2i(pc, inst, "SHI ");
store_half(unsigned(reg(ra) + imm), std_logic_vector(reg(rd)(15 downto 0)));
when "111110" => -- SWI Rd,Ra,Imm
dbPrint2i(pc, inst, "SW ");
store_word(unsigned(reg(ra) + imm), std_logic_vector(reg(rd)));
when "111111" => --
illegal(pc);
when others =>
illegal(pc);
end case;
end procedure execute_instruction;
variable old_pc : unsigned(31 downto 0);
begin
if reset='1' then
pc_reg <= (others => '0');
io_addr <= (others => '0');
io_wdata <= (others => '0');
io_read <= '0';
io_write <= '0';
else
D_flag <= '0';
execute_instruction(pc_reg);
old_pc := pc_reg;
pc_reg <= new_pc;
if do_delay='1' then
wait until clock='1';
D_flag <= '1';
do_delay := '0';
execute_instruction(old_pc + 4); -- old PC + 4
end if;
end if;
wait until clock='1';
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : mb_model
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Instruction level model of the microblaze
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mb_model is
generic (
g_io_mask : unsigned(31 downto 0) := X"FC000000" );
port (
clock : in std_logic;
reset : in std_logic;
io_addr : out unsigned(31 downto 0);
io_write : out std_logic;
io_read : out std_logic;
io_byte_en : out std_logic_vector(3 downto 0);
io_wdata : out std_logic_vector(31 downto 0);
io_rdata : in std_logic_vector(31 downto 0);
io_ack : in std_logic );
end entity;
architecture bfm of mb_model is
type t_word_array is array(natural range <>) of std_logic_vector(31 downto 0);
type t_signed_array is array(natural range <>) of signed(31 downto 0);
constant c_memory_size_bytes : natural := 20; -- 1 MB
constant c_memory_size_words : natural := c_memory_size_bytes - 2;
shared variable reg : t_signed_array(0 to 31) := (others => (others => '0'));
shared variable imem : t_word_array(0 to 2**c_memory_size_words -1);
alias dmem : t_word_array(0 to 2**c_memory_size_words -1) is imem;
signal pc_reg : unsigned(31 downto 0);
signal C_flag : std_logic;
signal I_flag : std_logic;
signal B_flag : std_logic;
signal D_flag : std_logic;
constant p : string := "PC: ";
constant i : string := ", Inst: ";
constant c : string := ", ";
constant ras : string := ", Ra=";
constant rbs : string := ", Rb=";
constant rds : string := ", Rd=";
impure function get_msr(len : natural) return std_logic_vector is
variable msr : std_logic_vector(31 downto 0);
begin
msr := (31 => C_flag,
3 => B_flag,
2 => C_flag,
1 => I_flag,
others => '0' );
return msr(len-1 downto 0);
end function;
function to_std(b : boolean) return std_logic is
begin
if b then return '1'; end if;
return '0';
end function;
begin
process
variable new_pc : unsigned(31 downto 0);
variable do_delay : std_logic := '0';
variable imm : signed(31 downto 0);
variable imm_lock : std_logic := '0';
variable ra : integer range 0 to 31;
variable rb : integer range 0 to 31;
variable rd : integer range 0 to 31;
procedure dbPrint(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); str : string) is
variable s : line;
begin
write(s, p);
write(s, hstr(pc));
write(s, i);
write(s, hstr(inst));
write(s, ras);
write(s, hstr(unsigned(reg(ra))));
write(s, rbs);
write(s, hstr(unsigned(reg(rb))));
write(s, rds);
write(s, hstr(unsigned(reg(rd))));
write(s, c);
write(s, str);
-- writeline(output, s);
end procedure;
procedure set_msr(a : std_logic_vector(13 downto 0)) is
begin
B_flag <= a(3);
C_flag <= a(2);
I_flag <= a(1);
end procedure;
procedure perform_add(a, b : signed(31 downto 0); carry : std_logic; upd_c : boolean) is
variable t33: signed(32 downto 0);
begin
if carry = '1' then
t33 := ('0' & a) + ('0' & b) + 1;
else
t33 := ('0' & a) + ('0' & b);
end if;
reg(rd) := t33(31 downto 0);
if upd_c then
C_flag <= t33(32);
end if;
end procedure;
procedure illegal(pc : unsigned) is
begin
report "Illegal instruction @ " & hstr(pc)
severity error;
end procedure;
procedure unimplemented(msg : string) is
begin
report msg;
end procedure;
procedure do_branch(pc : unsigned(31 downto 0); offset : signed(31 downto 0); delay, absolute, link : std_logic; chk : integer) is
variable take : boolean;
begin
case chk is
when 0 => take := (reg(ra) = 0);
when 1 => take := (reg(ra) /= 0);
when 2 => take := (reg(ra) < 0);
when 3 => take := (reg(ra) <= 0);
when 4 => take := (reg(ra) > 0);
when 5 => take := (reg(ra) >= 0);
when others => take := true;
end case;
if link='1' then
reg(rd) := signed(pc);
end if;
if take then
if absolute='1' then
new_pc := unsigned(offset);
else
new_pc := unsigned(signed(pc) + offset);
end if;
end if; -- else: default: new_pc := pc + 4;
if take then
do_delay := delay;
end if;
end procedure;
function is_io(addr : unsigned(31 downto 0)) return boolean is
begin
return (addr and g_io_mask) /= 0;
end function;
procedure load_byte(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_read <= '1';
io_addr <= unsigned(addr);
case addr(1 downto 0) is
when "00" => io_byte_en <= "1000";
when "01" => io_byte_en <= "0100";
when "10" => io_byte_en <= "0010";
when "11" => io_byte_en <= "0001";
when others => io_byte_en <= "0000";
end case;
wait until clock='1';
io_read <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
loaded := io_rdata;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
end if;
data := (others => '0');
case addr(1 downto 0) is
when "00" => data(7 downto 0) := loaded(31 downto 24);
when "01" => data(7 downto 0) := loaded(23 downto 16);
when "10" => data(7 downto 0) := loaded(15 downto 8);
when "11" => data(7 downto 0) := loaded(7 downto 0);
when others => data := (others => 'X');
end case;
end procedure;
procedure load_half(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_read <= '1';
io_addr <= unsigned(addr);
io_byte_en <= (others => '0');
case addr(1 downto 0) is
when "00" => io_byte_en <= "1100";
when "10" => io_byte_en <= "0011";
when others => null;
end case;
wait until clock='1';
io_read <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
loaded := io_rdata;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
end if;
data := (others => '0');
case addr(1 downto 0) is
when "00" => data(15 downto 0) := loaded(31 downto 16);
when "10" => data(15 downto 0) := loaded(15 downto 0);
when others => report "Unalligned halfword read" severity error;
end case;
end procedure;
procedure load_word(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_read <= '1';
io_addr <= unsigned(addr);
io_byte_en <= (others => '1');
wait until clock='1';
io_read <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
loaded := io_rdata;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
end if;
data := loaded;
assert addr(1 downto 0) = "00"
report "Unalligned dword read" severity error;
end procedure;
procedure store_byte(addr : unsigned(31 downto 0); data : std_logic_vector(7 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_write <= '1';
io_addr <= unsigned(addr);
io_wdata <= data & data & data & data;
case addr(1 downto 0) is
when "00" => io_byte_en <= "1000";
when "01" => io_byte_en <= "0100";
when "10" => io_byte_en <= "0010";
when "11" => io_byte_en <= "0001";
when others => io_byte_en <= "0000";
end case;
wait until clock='1';
io_write <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
case addr(1 downto 0) is
when "00" => loaded(31 downto 24) := data;
when "01" => loaded(23 downto 16) := data;
when "10" => loaded(15 downto 8) := data;
when "11" => loaded(7 downto 0) := data;
when others => null;
end case;
dmem(to_integer(addr(c_memory_size_bytes-1 downto 2))) := loaded;
end if;
end procedure;
procedure store_half(addr : unsigned(31 downto 0); data : std_logic_vector(15 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_write <= '1';
io_addr <= unsigned(addr);
io_wdata <= data & data;
case addr(1 downto 0) is
when "00" => io_byte_en <= "1100";
when "10" => io_byte_en <= "0011";
when others => io_byte_en <= "0000";
end case;
wait until clock='1';
io_write <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
case addr(1 downto 0) is
when "00" => loaded(31 downto 16) := data;
when "10" => loaded(15 downto 0) := data;
when others => report "Unalligned halfword write" severity error;
end case;
dmem(to_integer(addr(c_memory_size_bytes-1 downto 2))) := loaded;
end if;
assert addr(0) = '0'
report "Unalligned halfword write" severity error;
end procedure;
procedure store_word(addr : unsigned(31 downto 0); data : std_logic_vector(31 downto 0)) is
begin
if is_io(addr) then
io_write <= '1';
io_addr <= unsigned(addr);
io_wdata <= data;
io_byte_en <= "1111";
wait until clock='1';
io_write <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
else
dmem(to_integer(addr(c_memory_size_bytes-1 downto 2))) := data;
end if;
assert addr(1 downto 0) = "00"
report "Unalligned dword write" severity error;
end procedure;
procedure check_zero(a : std_logic_vector) is
begin
assert unsigned(a) = 0
report "Modifier bits not zero.. Illegal instruction?"
severity warning;
end procedure;
procedure dbPrint3(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); s : string) is
begin
dbPrint(pc, inst, s & "R" & str(rd) & ", R" & str(ra) & ", R" & str(rb));
end procedure;
procedure dbPrint2(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); s : string) is
begin
dbPrint(pc, inst, s & "R" & str(rd) & ", R" & str(ra));
end procedure;
procedure dbPrint2i(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); s : string) is
begin
dbPrint(pc, inst, s & "R" & str(rd) & ", R" & str(ra) & ", 0x" & hstr(unsigned(imm)));
end procedure;
procedure dbPrintBr(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); delay, absolute, link, immediate : std_logic; chk : integer) is
variable base : string(1 to 6) := " ";
variable n : integer := 4;
begin
case chk is
when 0 => base(1 to 3) := "BEQ";
when 1 => base(1 to 3) := "BNE";
when 2 => base(1 to 3) := "BLT";
when 3 => base(1 to 3) := "BLE";
when 4 => base(1 to 3) := "BGT";
when 5 => base(1 to 3) := "BGE";
when others => base(1 to 2) := "BR"; n := 3;
end case;
if absolute='1' then base(n) := 'A'; n := n + 1; end if;
if link='1' then base(n) := 'L'; n := n + 1; end if;
if immediate='1' then base(n) := 'I'; n := n + 1; end if;
if delay='1' then base(n) := 'D'; n := n + 1; end if;
if link='1' then
dbPrint(pc, inst, base & " R" & str(rd) & " => " & hstr(new_pc));
elsif chk = 15 then
dbPrint(pc, inst, base & " => " & hstr(new_pc));
else
dbPrint(pc, inst, base & " R" & str(ra) & " => " & hstr(new_pc));
end if;
end procedure;
procedure execute_instruction(pc : unsigned(31 downto 0)) is
variable inst : std_logic_vector(31 downto 0);
variable data : std_logic_vector(31 downto 0);
variable temp : std_logic;
begin
inst := imem(to_integer(pc(c_memory_size_bytes-1 downto 2)));
rd := to_integer(unsigned(inst(25 downto 21)));
ra := to_integer(unsigned(inst(20 downto 16)));
rb := to_integer(unsigned(inst(15 downto 11)));
reg(0) := (others => '0');
imm(15 downto 0) := signed(inst(15 downto 0));
if imm_lock='0' then
imm(31 downto 16) := (others => inst(15)); -- sign extend
end if;
imm_lock := '0';
io_write <= '0';
io_read <= '0';
io_addr <= (others => '0');
io_byte_en <= (others => '0');
new_pc := pc + 4;
case inst(31 downto 26) is
when "000000" => -- ADD Rd,Ra,Rb
dbPrint3(pc, inst, "ADD ");
perform_add(reg(ra), reg(rb), '0', true);
check_zero(inst(10 downto 0));
when "000001" => -- RSUB Rd,Ra,Rb
dbPrint3(pc, inst, "RSUB ");
perform_add(not reg(ra), reg(rb), '1', true);
check_zero(inst(10 downto 0));
when "000010" => -- ADDC Rd,Ra,Rb
dbPrint3(pc, inst, "ADDC ");
perform_add(reg(ra), reg(rb), C_flag, true);
check_zero(inst(10 downto 0));
when "000011" => -- RSUBC Rd,Ra,Rb
dbPrint3(pc, inst, "RSUBC ");
perform_add(not reg(ra), reg(rb), C_flag, true);
check_zero(inst(10 downto 0));
when "000100" => -- ADDK Rd,Ra,Rb
dbPrint3(pc, inst, "ADDK ");
perform_add(reg(ra), reg(rb), '0', false);
check_zero(inst(10 downto 0));
when "000101" => -- RSUBK Rd,Ra,Rb / CMP Rd,Ra,Rb / CMPU Rd,Ra,Rb
if inst(1 downto 0) = "01" then -- CMP
dbPrint3(pc, inst, "CMP ");
temp := not to_std(signed(reg(rb)) >= signed(reg(ra)));
perform_add(not reg(ra), reg(rb), '1', false);
reg(rd)(31) := temp;
elsif inst(1 downto 0) = "11" then -- CMPU
dbPrint3(pc, inst, "CMPU ");
temp := not to_std(unsigned(reg(rb)) >= unsigned(reg(ra)));
perform_add(not reg(ra), reg(rb), '1', false);
reg(rd)(31) := temp;
else
dbPrint3(pc, inst, "RSUBK ");
perform_add(not reg(ra), reg(rb), '1', false);
end if;
check_zero(inst(10 downto 2));
when "000110" => -- ADDKC Rd,Ra,Rb
dbPrint3(pc, inst, "ADDKC ");
perform_add(reg(ra), reg(rb), C_flag, false);
check_zero(inst(10 downto 0));
when "000111" => -- RSUBKC Rd,Ra,Rb
dbPrint3(pc, inst, "RSUBKC ");
perform_add(not reg(ra), reg(rb), C_flag, false);
when "001000" => -- ADDI Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDI ");
perform_add(reg(ra), imm, '0', true);
when "001001" => -- RSUBI Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBI ");
perform_add(not reg(ra), imm, '1', true);
when "001010" => -- ADDIC Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDIC ");
perform_add(reg(ra), imm, C_flag, true);
when "001011" => -- RSUBIC Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBIC ");
perform_add(not reg(ra), imm, C_flag, true);
when "001100" => -- ADDIK Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDIK ");
perform_add(reg(ra), imm, '0', false);
when "001101" => -- RSUBIK Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBIK ");
perform_add(not reg(ra), imm, '1', false);
when "001110" => -- ADDIKC Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDIKC ");
perform_add(reg(ra), imm, C_flag, false);
when "001111" => -- RSUBIKC Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBIKC ");
perform_add(not reg(ra), imm, C_flag, false);
when "010000" => -- MUL/MULH/MULHSU/MULHU Rd,Ra,Rb
unimplemented("MUL/MULH/MULHSU/MULHU Rd,Ra,Rb");
when "010001" => -- BSRA Rd,Ra,Rb / BSLL Rd,Ra,Rb (Barrel shift)
unimplemented("BSRA Rd,Ra,Rb / BSLL Rd,Ra,Rb (Barrel shift)");
when "010010" => -- IDIV Rd,Ra,Rb / IDIVU Rd,Ra,Rb
unimplemented("IDIV Rd,Ra,Rb / IDIVU Rd,Ra,Rb");
when "010011" => --
illegal(pc);
when "010100" => --
illegal(pc);
when "010101" => --
illegal(pc);
when "010110" => --
illegal(pc);
when "010111" => --
illegal(pc);
when "011000" => -- MULI Rd,Ra,Imm
unimplemented("MULI Rd,Ra,Imm");
when "011001" => -- BSRLI Rd,Ra,Imm / BSRAI Rd,Ra,Imm / BSLLI Rd,Ra,Imm
unimplemented("BSRLI Rd,Ra,Imm / BSRAI Rd,Ra,Imm / BSLLI Rd,Ra,Imm");
when "011010" => --
illegal(pc);
when "011011" => --
illegal(pc);
when "011100" => --
illegal(pc);
when "011101" => --
illegal(pc);
when "011110" => --
illegal(pc);
when "011111" => --
illegal(pc);
when "100000" => -- OR Rd,Ra,Rb / PCMPBF Rd,Ra,Rb
if inst(10)='1' then
unimplemented("PCMPBF Rd,Ra,Rb");
else
dbPrint3(pc, inst, "OR ");
reg(rd) := reg(ra) or reg(rb);
end if;
check_zero(inst(9 downto 0));
when "100001" => -- AND Rd,Ra,Rb
dbPrint3(pc, inst, "AND ");
reg(rd) := reg(ra) and reg(rb);
check_zero(inst(10 downto 0));
when "100010" => -- XOR Rd,Ra,Rb / PCMPEQ Rd,Ra,Rb
if inst(10)='1' then
unimplemented("PCMPEQ Rd,Ra,Rb");
else
dbPrint3(pc, inst, "XOR ");
reg(rd) := reg(ra) xor reg(rb);
end if;
check_zero(inst(9 downto 0));
when "100011" => -- ANDN Rd,Ra,Rb/ PCMPNE Rd,Ra,Rb
if inst(10)='1' then
unimplemented("PCMPNE Rd,Ra,Rb");
else
dbPrint3(pc, inst, "ANDN ");
reg(rd) := reg(ra) and not reg(rb);
end if;
check_zero(inst(9 downto 0));
when "100100" => -- SRA Rd,Ra / SRC Rd,Ra / SRL Rd,Ra/ SEXT8 Rd,Ra / SEXT16 Rd,Ra
case inst(15 downto 0) is
when X"0001" => -- SRA
dbPrint2(pc, inst, "SRA ");
C_flag <= reg(ra)(0);
reg(rd) := reg(ra)(31) & reg(ra)(31 downto 1);
when X"0021" => -- SRC
dbPrint2(pc, inst, "SRC ");
C_flag <= reg(ra)(0);
reg(rd) := C_flag & reg(ra)(31 downto 1);
when X"0041" => -- SRL
dbPrint2(pc, inst, "SRL ");
C_flag <= reg(ra)(0);
reg(rd) := '0' & reg(ra)(31 downto 1);
when X"0060" => -- SEXT8
dbPrint2(pc, inst, "SEXT8 ");
reg(rd)(31 downto 8) := (others => reg(ra)(7));
reg(rd)(7 downto 0) := reg(ra)(7 downto 0);
when X"0061" => -- SEXT16
dbPrint2(pc, inst, "SEXT16 ");
reg(rd)(31 downto 16) := (others => reg(ra)(15));
reg(rd)(15 downto 0) := reg(ra)(15 downto 0);
when others =>
illegal(pc);
end case;
when "100101" => -- MTS Sd,Ra / MFS Rd,Sa / MSRCLR Rd,Imm / MSRSET Rd,Imm
case inst(15 downto 14) is
when "00" => -- SET/CLR
reg(rd) := get_msr(32);
if inst(16)='0' then -- set
dbPrint(pc, inst, "MSRSET R" & str(rd) & ", " & hstr(inst(13 downto 0)));
set_msr(get_msr(14) or inst(13 downto 0));
else -- clear
dbPrint(pc, inst, "MSRCLR R" & str(rd) & ", " & hstr(inst(13 downto 0)));
set_msr(get_msr(14) and not inst(13 downto 0));
end if;
when "10" => -- MFS (read)
dbPrint(pc, inst, "MFS R" & str(rd) & ", " & hstr(inst(13 downto 0)));
case inst(15 downto 0) is
when X"4000" =>
reg(rd) := signed(pc);
when X"4001" =>
reg(rd) := signed(get_msr(32));
when others =>
unimplemented("MFS register type " & hstr(inst(13 downto 0)));
end case;
check_zero(inst(20 downto 16));
when "11" => -- MTS (write)
dbPrint(pc, inst, "MTS R" & str(rd) & ", " & hstr(inst(13 downto 0)));
case inst(15 downto 0) is
when X"C001" =>
set_msr(std_logic_vector(reg(ra)(13 downto 0)));
when others =>
unimplemented("MTS register type " & hstr(inst(13 downto 0)));
end case;
when others =>
illegal(pc);
end case;
when "100110" => -- BR(A)(L)(D) (Rb,)Rb / BRK Rd,Rb
do_branch(pc => pc, offset => reg(rb), delay => inst(20), absolute => inst(19), link => inst(18), chk => 15);
dbPrintBr(pc => pc, inst => inst, delay => inst(20), absolute => inst(19), link => inst(18), immediate => '0', chk => 15);
if (inst(20 downto 18) = "011") then
B_flag <= '1';
end if;
check_zero(inst(10 downto 0));
when "100111" => -- Bxx Ra,Rb (Rd = type of branch)
do_branch(pc => pc, offset => reg(rb), delay => inst(25), absolute => '0', link => '0', chk => to_integer(unsigned(inst(23 downto 21))));
dbPrintBr(pc => pc, inst => inst, delay => inst(25), absolute => '0', link => '0', immediate => '0', chk => to_integer(unsigned(inst(23 downto 21))));
check_zero(inst(10 downto 0));
when "101000" => -- ORI Rd,Ra,Imm
dbPrint2i(pc, inst, "ORI ");
reg(rd) := reg(ra) or imm;
when "101001" => -- ANDI Rd,Ra,Imm
dbPrint2i(pc, inst, "ANDI ");
reg(rd) := reg(ra) and imm;
when "101010" => -- XORI Rd,Ra,Imm
dbPrint2i(pc, inst, "XORI ");
reg(rd) := reg(ra) xor imm;
when "101011" => -- ANDNI Rd,Ra,Imm
dbPrint2i(pc, inst, "ANDNI ");
reg(rd) := reg(ra) and not imm;
when "101100" => -- IMM Imm
dbPrint(pc, inst, "IMM " & hstr(inst(15 downto 0)));
imm(31 downto 16) := signed(inst(15 downto 0));
imm_lock := '1';
check_zero(inst(25 downto 16));
when "101101" => -- RTSD Ra,Imm / RTID Ra,Imm / RTBD Ra,Imm / RTED Ra,Imm
case inst(25 downto 21) is
when "10000" =>
dbPrint(pc, inst, "RTSD R" & str(ra) & ", " & str(to_integer(imm)));
null;
when "10001" =>
dbPrint(pc, inst, "RTID R" & str(ra) & ", " & str(to_integer(imm)));
I_flag <= '1';
when "10010" =>
dbPrint(pc, inst, "RTBD R" & str(ra) & ", " & str(to_integer(imm)));
B_flag <= '0';
when "10100" =>
unimplemented("Return from exception RTED");
when others =>
illegal(pc);
end case;
new_pc := unsigned(reg(ra) + imm);
do_delay := '1';
when "101110" => -- BR(A)(L)I(D) Imm Ra / BRKI Rd,Imm
do_branch(pc => pc, offset => imm, delay => inst(20), absolute => inst(19), link => inst(18), chk => 15);
dbPrintBr(pc => pc, inst => inst, delay => inst(20), absolute => inst(19), link => inst(18), immediate => '1', chk => 15);
if (inst(20 downto 18) = "011") then
B_flag <= '1';
end if;
when "101111" => -- BxxI Ra,Imm (Rd = type of branch)
do_branch(pc => pc, offset => imm, delay => inst(25), absolute => '0', link => '0', chk => to_integer(unsigned(inst(23 downto 21))));
dbPrintBr(pc => pc, inst => inst, delay => inst(25), absolute => '0', link => '0', immediate => '1', chk => to_integer(unsigned(inst(23 downto 21))));
when "110000" => -- LBU Rd,Ra,Rb
dbPrint3(pc, inst, "LBU ");
load_byte(unsigned(reg(ra) + reg(rb)), data);
reg(rd) := signed(data);
check_zero(inst(10 downto 0));
when "110001" => -- LHU Rd,Ra,Rb
dbPrint3(pc, inst, "LHU ");
load_half(unsigned(reg(ra) + reg(rb)), data);
reg(rd) := signed(data);
check_zero(inst(10 downto 0));
when "110010" => -- LW Rd,Ra,Rb
dbPrint3(pc, inst, "LW ");
load_word(unsigned(reg(ra) + reg(rb)), data);
reg(rd) := signed(data);
check_zero(inst(10 downto 0));
when "110011" => --
illegal(pc);
when "110100" => -- SB Rd,Ra,Rb
dbPrint3(pc, inst, "SB ");
store_byte(unsigned(reg(ra) + reg(rb)), std_logic_vector(reg(rd)(7 downto 0)));
check_zero(inst(10 downto 0));
when "110101" => -- SH Rd,Ra,Rb
dbPrint3(pc, inst, "SH ");
store_half(unsigned(reg(ra) + reg(rb)), std_logic_vector(reg(rd)(15 downto 0)));
check_zero(inst(10 downto 0));
when "110110" => -- SW Rd,Ra,Rb
dbPrint3(pc, inst, "SW ");
store_word(unsigned(reg(ra) + reg(rb)), std_logic_vector(reg(rd)));
check_zero(inst(10 downto 0));
when "110111" => --
illegal(pc);
when "111000" => -- LBUI Rd,Ra,Imm
dbPrint2i(pc, inst, "LBUI ");
load_byte(unsigned(reg(ra) + imm), data);
reg(rd) := signed(data);
when "111001" => -- LHUI Rd,Ra,Imm
dbPrint2i(pc, inst, "LHUI ");
load_half(unsigned(reg(ra) + imm), data);
reg(rd) := signed(data);
when "111010" => -- LWI Rd,Ra,Imm
dbPrint2i(pc, inst, "LWI ");
load_word(unsigned(reg(ra) + imm), data);
reg(rd) := signed(data);
when "111011" => --
illegal(pc);
when "111100" => -- SBI Rd,Ra,Imm
dbPrint2i(pc, inst, "SBI ");
store_byte(unsigned(reg(ra) + imm), std_logic_vector(reg(rd)(7 downto 0)));
when "111101" => -- SHI Rd,Ra,Imm
dbPrint2i(pc, inst, "SHI ");
store_half(unsigned(reg(ra) + imm), std_logic_vector(reg(rd)(15 downto 0)));
when "111110" => -- SWI Rd,Ra,Imm
dbPrint2i(pc, inst, "SW ");
store_word(unsigned(reg(ra) + imm), std_logic_vector(reg(rd)));
when "111111" => --
illegal(pc);
when others =>
illegal(pc);
end case;
end procedure execute_instruction;
variable old_pc : unsigned(31 downto 0);
begin
if reset='1' then
pc_reg <= (others => '0');
io_addr <= (others => '0');
io_wdata <= (others => '0');
io_read <= '0';
io_write <= '0';
else
D_flag <= '0';
execute_instruction(pc_reg);
old_pc := pc_reg;
pc_reg <= new_pc;
if do_delay='1' then
wait until clock='1';
D_flag <= '1';
do_delay := '0';
execute_instruction(old_pc + 4); -- old PC + 4
end if;
end if;
wait until clock='1';
end process;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci is
port(
D_valid : in vl_logic;
E_st_data : in vl_logic_vector(31 downto 0);
E_valid : in vl_logic;
F_pc : in vl_logic_vector(26 downto 0);
address_nxt : in vl_logic_vector(8 downto 0);
av_ld_data_aligned_filtered: in vl_logic_vector(31 downto 0);
byteenable_nxt : in vl_logic_vector(3 downto 0);
clk : in vl_logic;
d_address : in vl_logic_vector(28 downto 0);
d_read : in vl_logic;
d_waitrequest : in vl_logic;
d_write : in vl_logic;
debugaccess_nxt : in vl_logic;
hbreak_enabled : in vl_logic;
read_nxt : in vl_logic;
reset : in vl_logic;
reset_n : in vl_logic;
reset_req : in vl_logic;
test_ending : in vl_logic;
test_has_ended : in vl_logic;
write_nxt : in vl_logic;
writedata_nxt : in vl_logic_vector(31 downto 0);
jtag_debug_module_debugaccess_to_roms: out vl_logic;
oci_hbreak_req : out vl_logic;
oci_ienable : out vl_logic_vector(31 downto 0);
oci_single_step_mode: out vl_logic;
readdata : out vl_logic_vector(31 downto 0);
resetrequest : out vl_logic;
waitrequest : out vl_logic
);
end finalproject_cpu_nios2_oci;
|
library verilog;
use verilog.vl_types.all;
entity uart_ctrl is
port(
clk : in vl_logic;
reset : in vl_logic;
cs_n : in vl_logic;
as_n : in vl_logic;
rw : in vl_logic;
addr : in vl_logic_vector(0 downto 0);
wr_data : in vl_logic_vector(31 downto 0);
rd_data : out vl_logic_vector(31 downto 0);
rdy_n : out vl_logic;
irq_rx : out vl_logic;
irq_tx : out vl_logic;
rx_busy : in vl_logic;
rx_end : in vl_logic;
rx_data : in vl_logic_vector(7 downto 0);
tx_busy : in vl_logic;
tx_end : in vl_logic;
tx_start : out vl_logic;
tx_data : out vl_logic_vector(7 downto 0)
);
end uart_ctrl;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram.vhd
-- Date: 06/15/05
-- Purpose: File used to instantiate an inferred BRAM (single port)
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
signal BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for inferred BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) <= DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
end architecture implementation;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram.vhd
-- Date: 06/15/05
-- Purpose: File used to instantiate an inferred BRAM (single port)
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
signal BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for inferred BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) <= DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
end architecture implementation;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram.vhd
-- Date: 06/15/05
-- Purpose: File used to instantiate an inferred BRAM (single port)
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
signal BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for inferred BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) <= DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
end architecture implementation;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram.vhd
-- Date: 06/15/05
-- Purpose: File used to instantiate an inferred BRAM (single port)
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
signal BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for inferred BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) <= DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
end architecture implementation;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram.vhd
-- Date: 06/15/05
-- Purpose: File used to instantiate an inferred BRAM (single port)
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
signal BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for inferred BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) <= DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
end architecture implementation;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram.vhd
-- Date: 06/15/05
-- Purpose: File used to instantiate an inferred BRAM (single port)
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
signal BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for inferred BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) <= DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
end architecture implementation;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram.vhd
-- Date: 06/15/05
-- Purpose: File used to instantiate an inferred BRAM (single port)
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
signal BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for inferred BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) <= DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
end architecture implementation;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram.vhd
-- Date: 06/15/05
-- Purpose: File used to instantiate an inferred BRAM (single port)
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
signal BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for inferred BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) <= DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
end architecture implementation;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram.vhd
-- Date: 06/15/05
-- Purpose: File used to instantiate an inferred BRAM (single port)
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
signal BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for inferred BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) <= DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
end architecture implementation;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram.vhd
-- Date: 06/15/05
-- Purpose: File used to instantiate an inferred BRAM (single port)
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
signal BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for inferred BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) <= DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
end architecture implementation;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram.vhd
-- Date: 06/15/05
-- Purpose: File used to instantiate an inferred BRAM (single port)
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
signal BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for inferred BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) <= DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
end architecture implementation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc258.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00258ent IS
END c03s01b02x00p08n01i00258ent;
ARCHITECTURE c03s01b02x00p08n01i00258arch OF c03s01b02x00p08n01i00258ent IS
BEGIN
TESTING: PROCESS
variable V1 : integer := -2147483647; -- No_failure_here
variable V2 : integer := +2147483647; -- No_failure_here
BEGIN
assert NOT( V1 = -2147483647 and V2 = +2147483647 )
report "***PASSED TEST: c03s01b02x00p08n01i00258"
severity NOTE;
assert ( V1 = -2147483647 and V2 = +2147483647 )
report "***FAILED TEST: c03s01b02x00p08n01i00258 - Integer declared outside bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00258arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc258.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00258ent IS
END c03s01b02x00p08n01i00258ent;
ARCHITECTURE c03s01b02x00p08n01i00258arch OF c03s01b02x00p08n01i00258ent IS
BEGIN
TESTING: PROCESS
variable V1 : integer := -2147483647; -- No_failure_here
variable V2 : integer := +2147483647; -- No_failure_here
BEGIN
assert NOT( V1 = -2147483647 and V2 = +2147483647 )
report "***PASSED TEST: c03s01b02x00p08n01i00258"
severity NOTE;
assert ( V1 = -2147483647 and V2 = +2147483647 )
report "***FAILED TEST: c03s01b02x00p08n01i00258 - Integer declared outside bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00258arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc258.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00258ent IS
END c03s01b02x00p08n01i00258ent;
ARCHITECTURE c03s01b02x00p08n01i00258arch OF c03s01b02x00p08n01i00258ent IS
BEGIN
TESTING: PROCESS
variable V1 : integer := -2147483647; -- No_failure_here
variable V2 : integer := +2147483647; -- No_failure_here
BEGIN
assert NOT( V1 = -2147483647 and V2 = +2147483647 )
report "***PASSED TEST: c03s01b02x00p08n01i00258"
severity NOTE;
assert ( V1 = -2147483647 and V2 = +2147483647 )
report "***FAILED TEST: c03s01b02x00p08n01i00258 - Integer declared outside bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00258arch;
|
-------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- ExtInputs
Start : in std_logic;
Mode : in std_logic_vector(3 downto 0);
Size : in std_logic_vector(3 downto 0); -- only matters for last block decryption
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(127 downto 0);
Busy : out std_logic;
DataOut : out std_logic_vector(127 downto 0));
end entity Ascon_StateUpdate;
architecture structural of Ascon_StateUpdate is
-- Control signals
signal RoundNr : std_logic_vector(2 downto 0);
signal sel1,sel2,sel3,sel4 : std_logic_vector(1 downto 0);
signal sel0 : std_logic_vector(2 downto 0);
signal selout : std_logic;
signal Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : std_logic;
signal ActivateGen : std_logic;
signal GenSize : std_logic_vector(3 downto 0);
begin
control: entity work.Ascon_StateUpdate_control port map (Clk, Reset, RoundNr, sel1, sel2, sel3, sel4, sel0, selout, Reg0En,
Reg1En, Reg2En, Reg3En, Reg4En, RegOutEn, ActivateGen, GenSize, Start, Mode, Size, Busy);
datapath: entity work.Ascon_StateUpdate_datapath port map (Clk, Reset, RoundNr, sel1, sel2, sel3, sel4, sel0, selout, Reg0En,
Reg1En, Reg2En, Reg3En, Reg4En, RegOutEn, ActivateGen, GenSize, IV, Key, DataIn, DataOut);
end architecture structural;
|
entity test is
type t is record
foo, bar : baz;
end record;
end;
|
architecture RTL of FIFO is
shared variable SHAR_VAR1 : integer;
begin
process
variable VAR1 : integer;
begin
end process;
end architecture RTL;
-- Violations below
architecture RTL of FIFO is
shared variable SHAR_VAR1 : integer;
begin
process
variable VAR1 : integer;
begin
end process;
end architecture RTL;
|
-- VHDL de uma memoria do jogo da velha
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memoria_caractere is
port(
clock : in std_logic;
reset : in std_logic;
leitura : in std_logic;
escrita : in std_logic;
jogador : in std_logic;
enable_fim : in std_logic;
mensagem_fim : in std_logic_vector(48 downto 0);
endereco_leitura : in std_logic_vector(6 downto 0);
endereco_escrita : in std_logic_vector(6 downto 0);
saida : out std_logic_vector(6 downto 0)
);
end memoria_caractere;
architecture estrutural of memoria_caractere is
type memoria is array (0 to 76) of std_logic_vector(6 downto 0);
constant c_enter: std_logic_vector(6 downto 0) := "0001101";
constant c_espaco: std_logic_vector(6 downto 0) := "0100000";
constant c_hifen: std_logic_vector(6 downto 0) := "0101101";
constant c_mais: std_logic_vector(6 downto 0) := "0101011";
constant c_pipe: std_logic_vector(6 downto 0) := "1111100";
constant c_x: std_logic_vector(6 downto 0) := "1011000";
constant c_o: std_logic_vector(6 downto 0) := "1001111";
constant c_esc: std_logic_vector(6 downto 0) := "0011011";
constant c_zero: std_logic_vector(6 downto 0) := "0110000";
constant c_dois: std_logic_vector(6 downto 0) := "0110010";
constant c_abrechaves: std_logic_vector(6 downto 0) := "1011011";
constant c_pontovirgula: std_logic_vector(6 downto 0) := "0111011";
constant c_J: std_logic_vector(6 downto 0) := "1001010";
constant c_H: std_logic_vector(6 downto 0) := "1001000";
signal memoria_tabuleiro: memoria := (c_esc, c_abrechaves, c_dois, c_J,
c_esc, c_abrechaves, c_zero, c_pontovirgula, c_zero, c_H,
c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_enter,
c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_enter,
c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_enter,
c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_enter,
c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_enter,
c_espaco, c_espaco, c_espaco, c_espaco, c_espaco, c_espaco, c_espaco);
begin
process (clock, reset, leitura, escrita, jogador)
begin
if reset='1' then
memoria_tabuleiro <= (c_esc, c_abrechaves, c_dois, c_J,
c_esc, c_abrechaves, c_zero, c_pontovirgula, c_zero, c_H,
c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_enter,
c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_enter,
c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_enter,
c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_mais, c_hifen, c_hifen, c_hifen, c_enter,
c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_pipe, c_espaco, c_espaco, c_espaco, c_enter,
c_espaco, c_espaco, c_espaco, c_espaco, c_espaco, c_espaco, c_espaco);
elsif clock'event and clock='1' then
if leitura='1' then
saida <= memoria_tabuleiro(to_integer(unsigned(endereco_leitura)));
elsif escrita='1' then
if jogador='0' then
memoria_tabuleiro(to_integer(unsigned(endereco_escrita))) <= c_x;
else
memoria_tabuleiro(to_integer(unsigned(endereco_escrita))) <= c_o;
end if;
elsif enable_fim='1' then
memoria_tabuleiro(70) <= mensagem_fim(48 downto 42);
memoria_tabuleiro(71) <= mensagem_fim(41 downto 35);
memoria_tabuleiro(72) <= mensagem_fim(34 downto 28);
memoria_tabuleiro(73) <= mensagem_fim(27 downto 21);
memoria_tabuleiro(74) <= mensagem_fim(20 downto 14);
memoria_tabuleiro(75) <= mensagem_fim(13 downto 7);
memoria_tabuleiro(76) <= mensagem_fim(6 downto 0);
else
memoria_tabuleiro(70 to 76) <= (others => c_espaco);
end if;
end if;
end process;
end estrutural;
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_pntr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/20/10 v1_00_a
-- ^^^^^^
-- CR568950
-- Qualified reseting of sg_idle from axi_sg_ftch_pntr with associated channel's
-- flush control.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic --
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch1_fetch_address <= ch1_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0')then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch2_fetch_address <= ch2_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1')then
ch2_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_pntr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/20/10 v1_00_a
-- ^^^^^^
-- CR568950
-- Qualified reseting of sg_idle from axi_sg_ftch_pntr with associated channel's
-- flush control.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic --
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch1_fetch_address <= ch1_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0')then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch2_fetch_address <= ch2_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1')then
ch2_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_pntr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/20/10 v1_00_a
-- ^^^^^^
-- CR568950
-- Qualified reseting of sg_idle from axi_sg_ftch_pntr with associated channel's
-- flush control.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic --
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch1_fetch_address <= ch1_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0')then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch2_fetch_address <= ch2_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1')then
ch2_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_pntr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/20/10 v1_00_a
-- ^^^^^^
-- CR568950
-- Qualified reseting of sg_idle from axi_sg_ftch_pntr with associated channel's
-- flush control.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic --
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch1_fetch_address <= ch1_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0')then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch2_fetch_address <= ch2_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1')then
ch2_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
|
-------------------------------------------------------------------------------
-- Le langage VHDL : du langage au circuit, du circuit au langage.
-- Copyright (C) Jacques Weber, Sébastien Moutault et Maurice Meaudre, 2006.
--
-- Ce programme est libre, vous pouvez le redistribuer et/ou le modifier selon
-- les termes de la Licence Publique Générale GNU publiée par la Free Software
-- Foundation (version 2 ou bien toute autre version ultérieure choisie par
-- vous).
--
-- Ce programme est distribué car potentiellement utile, mais SANS AUCUNE
-- GARANTIE, ni explicite ni implicite, y compris les garanties de
-- commercialisation ou d'adaptation dans un but spécifique. Reportez-vous à
-- la Licence Publique Générale GNU pour plus de détails.
--
-- Vous devez avoir reçu une copie de la Licence Publique Générale GNU en même
-- temps que ce programme ; si ce n'est pas le cas, écrivez à la Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307,
-- États-Unis.
--
-- [email protected]
-- [email protected]
-------------------------------------------------------------------------------
-- Projet :
-- Design :
-- Fichier : rompkg.vhd
-- Module : PACKAGE rompkg
-- Descript. :
-- Auteur : J.Weber
-- Date : 03/03/07
-- Version : 1.0
-- Depend. :
-- Simulation : ModelSim 6.0d
-- Synthèse :
-- Remarques :
--
--
-------------------------------------------------------------------------------
-- Date | Rév | Description
-- 01/08/06 | 1.0 | Première version stable utilisée pour le livre.
-- 03/03/07 | | Pas de modifications du design.
-- | | Preparation pour la mise en ligne.
-- | |
-- | |
-------------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
PACKAGE rompkg IS
CONSTANT ad_nb_bits : INTEGER := 3 ; -- e
CONSTANT size: INTEGER := 2**ad_nb_bits ; -- 8 bytes
SUBTYPE byte IS STD_LOGIC_VECTOR(7 DOWNTO 0) ;
TYPE rom_tbl IS ARRAY(NATURAL RANGE <>) OF byte ;
END PACKAGE rompkg ;
|
-------------------------------------------------------------------------------
-- Le langage VHDL : du langage au circuit, du circuit au langage.
-- Copyright (C) Jacques Weber, Sébastien Moutault et Maurice Meaudre, 2006.
--
-- Ce programme est libre, vous pouvez le redistribuer et/ou le modifier selon
-- les termes de la Licence Publique Générale GNU publiée par la Free Software
-- Foundation (version 2 ou bien toute autre version ultérieure choisie par
-- vous).
--
-- Ce programme est distribué car potentiellement utile, mais SANS AUCUNE
-- GARANTIE, ni explicite ni implicite, y compris les garanties de
-- commercialisation ou d'adaptation dans un but spécifique. Reportez-vous à
-- la Licence Publique Générale GNU pour plus de détails.
--
-- Vous devez avoir reçu une copie de la Licence Publique Générale GNU en même
-- temps que ce programme ; si ce n'est pas le cas, écrivez à la Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307,
-- États-Unis.
--
-- [email protected]
-- [email protected]
-------------------------------------------------------------------------------
-- Projet :
-- Design :
-- Fichier : rompkg.vhd
-- Module : PACKAGE rompkg
-- Descript. :
-- Auteur : J.Weber
-- Date : 03/03/07
-- Version : 1.0
-- Depend. :
-- Simulation : ModelSim 6.0d
-- Synthèse :
-- Remarques :
--
--
-------------------------------------------------------------------------------
-- Date | Rév | Description
-- 01/08/06 | 1.0 | Première version stable utilisée pour le livre.
-- 03/03/07 | | Pas de modifications du design.
-- | | Preparation pour la mise en ligne.
-- | |
-- | |
-------------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
PACKAGE rompkg IS
CONSTANT ad_nb_bits : INTEGER := 3 ; -- e
CONSTANT size: INTEGER := 2**ad_nb_bits ; -- 8 bytes
SUBTYPE byte IS STD_LOGIC_VECTOR(7 DOWNTO 0) ;
TYPE rom_tbl IS ARRAY(NATURAL RANGE <>) OF byte ;
END PACKAGE rompkg ;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
ENTITY ram IS
PORT (
Clk : in std_logic;
Reset : in std_logic;
write_en : in std_logic;
oe : in std_logic;
address : in std_logic_vector(7 downto 0);
databus : inout std_logic_vector(7 downto 0);
Switches : out std_logic_vector(7 downto 0);
Temp_L : out std_logic_vector(6 downto 0);
Temp_H : out std_logic_vector(6 downto 0));
END ram;
ARCHITECTURE behavior OF ram IS
SIGNAL contents_ram_general : array8_ram(191 downto 0); -- 192 posiciones de memoria desde X"40" hasta X"FF"
SIGNAL contents_ram_specific : array8_ram(63 downto 0); -- 64 posiciones de memoria desde X"00" hasta X"3F"
SIGNAL valor_Switch : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL memory_election : STD_LOGIC;
BEGIN
-------------------------------------------------------------------------
-- Eleccion de Memoria
-------------------------------------------------------------------------
election : process (address)
begin
--if clk'event and clk = '1' then
if address > X"3F" then -- Memoria general
memory_election <= '0';
elsif address < X"40" then -- Memoria específica
memory_election <= '1';
end if;
--end if;
end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- Memoria de propósito general
-------------------------------------------------------------------------
p_ram : process (clk) -- no reset
begin
if clk'event and clk = '1' then
if write_en = '1' and memory_election = '0' then
contents_ram_general(conv_Integer(address)) <= databus;
end if;
end if;
end process;
databus <= contents_ram_general(conv_integer(address)) when (oe = '0' and memory_election = '0') else
contents_ram_specific(conv_integer(address)) when (oe = '0' and memory_election = '1') else (others => 'Z');
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- Memoria de propósito específico
-------------------------------------------------------------------------
pe_ram : process (clk, Reset)
begin
if reset = '0' then
contents_ram_specific(conv_Integer(DMA_RX_BUFFER_MSB)) <= (others => '0'); -- Valor de la instrucción Rx
contents_ram_specific(conv_Integer(DMA_RX_BUFFER_MID)) <= (others => '0'); -- Valor del parámetro 1 Rx
contents_ram_specific(conv_Integer(DMA_RX_BUFFER_LSB)) <= (others => '0'); -- Valor del parámetro 2 Rx
contents_ram_specific(conv_Integer(NEW_INST)) <= (others => '0'); -- Flag que indica llegada de un nuevo comando
contents_ram_specific(conv_Integer(DMA_TX_BUFFER_MSB)) <= (others => '0'); -- Valor 1 de la Tx
contents_ram_specific(conv_Integer(DMA_TX_BUFFER_LSB)) <= (others => '0'); -- Valor 2 de la Tx
contents_ram_specific(conv_Integer(SWITCH_BASE)) <= (others => '0'); -- Valores de control de los interruptores
contents_ram_specific(conv_Integer(SWITCH_BASE+1)) <= (others => '0');
contents_ram_specific(conv_Integer(SWITCH_BASE+2)) <= (others => '0');
contents_ram_specific(conv_Integer(SWITCH_BASE+3)) <= (others => '0');
contents_ram_specific(conv_Integer(SWITCH_BASE+4)) <= (others => '0');
contents_ram_specific(conv_Integer(SWITCH_BASE+5)) <= (others => '0');
contents_ram_specific(conv_Integer(SWITCH_BASE+6)) <= (others => '0');
contents_ram_specific(conv_Integer(SWITCH_BASE+7)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE)) <= (others => '0'); -- Valores de control de los actuadores
contents_ram_specific(conv_Integer(LEVER_BASE+1)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+2)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+3)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+4)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+5)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+6)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+7)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+8)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+9)) <= (others => '0');
contents_ram_specific(conv_Integer(T_STAT)) <= "00100000"; -- Valor de la temperatura en BCD
elsif reset = '1' then
if clk'event and clk = '1' then
if write_en = '1' and memory_election = '1' then
contents_ram_specific(conv_Integer(address)) <= databus;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- Decodificador de BCD a 7 segmentos
-------------------------------------------------------------------------
temp : process(clk)
begin
if clk'event and clk='1' then
case contents_ram_specific(conv_Integer(T_STAT))(7 downto 4) is
when "0001" => Temp_H <= "0000110"; -- 1
when "0010" => Temp_H <= "1011011"; -- 2
when "0011" => Temp_H <= "1001111"; -- 3
when "0100" => Temp_H <= "1100110"; -- 4
when "0101" => Temp_H <= "1101101"; -- 5
when "0110" => Temp_H <= "1111101"; -- 6
when "0111" => Temp_H <= "0000111"; -- 7
when "1000" => Temp_H <= "1111111"; -- 8
when "1001" => Temp_H <= "1101111"; -- 9
when "1010" => Temp_H <= "1110111"; -- A
when "1011" => Temp_H <= "1111100"; -- B
when "1100" => Temp_H <= "0111001"; -- C
when "1101" => Temp_H <= "1011110"; -- D
when "1110" => Temp_H <= "1111001"; -- E
when "1111" => Temp_H <= "1110001"; -- F
when others => Temp_H <= "0111111"; -- 0
end case;
case contents_ram_specific(conv_Integer(T_STAT))(3 downto 0) is
when "0001" => Temp_L <= "0000110"; -- 1
when "0010" => Temp_L <= "1011011"; -- 2
when "0011" => Temp_L <= "1001111"; -- 3
when "0100" => Temp_L <= "1100110"; -- 4
when "0101" => Temp_L <= "1101101"; -- 5
when "0110" => Temp_L <= "1111101"; -- 6
when "0111" => Temp_L <= "0000111"; -- 7
when "1000" => Temp_L <= "1111111"; -- 8
when "1001" => Temp_L <= "1101111"; -- 9
when "1010" => Temp_L <= "1110111"; -- A
when "1011" => Temp_L <= "1111100"; -- B
when "1100" => Temp_L <= "0111001"; -- C
when "1101" => Temp_L <= "1011110"; -- D
when "1110" => Temp_L <= "1111001"; -- E
when "1111" => Temp_L <= "1110001"; -- F
when others => Temp_L <= "0111111"; -- 0
end case;
for i in 0 to 7 loop
valor_Switch(i) <= contents_ram_specific(conv_Integer(SWITCH_BASE+i))(0);
end loop;
Switches <= valor_Switch;
end if;
end process;
-------------------------------------------------------------------------
END behavior;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc108.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00108ent IS
port ( signal S : out bit) ;
END c04s03b02x00p29n06i00108ent;
ARCHITECTURE c04s03b02x00p29n06i00108arch OF c04s03b02x00p29n06i00108ent IS
BEGIN
TESTING: PROCESS
variable T : TIME := 10 ns;
BEGIN
if (S'LAST_VALUE = bit'('1')) then -- Failure_here
end if;
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n06i00108 - The attribute LAST_VALUE of a signal of mode out cannot be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00108arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc108.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00108ent IS
port ( signal S : out bit) ;
END c04s03b02x00p29n06i00108ent;
ARCHITECTURE c04s03b02x00p29n06i00108arch OF c04s03b02x00p29n06i00108ent IS
BEGIN
TESTING: PROCESS
variable T : TIME := 10 ns;
BEGIN
if (S'LAST_VALUE = bit'('1')) then -- Failure_here
end if;
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n06i00108 - The attribute LAST_VALUE of a signal of mode out cannot be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00108arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc108.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00108ent IS
port ( signal S : out bit) ;
END c04s03b02x00p29n06i00108ent;
ARCHITECTURE c04s03b02x00p29n06i00108arch OF c04s03b02x00p29n06i00108ent IS
BEGIN
TESTING: PROCESS
variable T : TIME := 10 ns;
BEGIN
if (S'LAST_VALUE = bit'('1')) then -- Failure_here
end if;
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n06i00108 - The attribute LAST_VALUE of a signal of mode out cannot be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00108arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY Pointer IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(27 DOWNTO 0)
);
END Pointer;
ARCHITECTURE Pointer_arch OF Pointer IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Pointer_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "Pointer.mif",
C_INIT_FILE => "Pointer.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 28,
C_READ_WIDTH_A => 28,
C_WRITE_DEPTH_A => 30,
C_READ_DEPTH_A => 30,
C_ADDRA_WIDTH => 5,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 28,
C_READ_WIDTH_B => 28,
C_WRITE_DEPTH_B => 30,
C_READ_DEPTH_B => 30,
C_ADDRB_WIDTH => 5,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.2088 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 28)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 28)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 28)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END Pointer_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:22:45 05/10/2015
-- Design Name:
-- Module Name: MyClk - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_CLK is
port (
clk: in std_logic;
nreset: in std_logic;
clk1, nclk1: out std_logic;
clk2, nclk2: out std_logic;
w0, w1, w2, w3: out std_logic);
end module_CLK;
architecture Behavioral of module_CLK is
signal count1: integer range 0 to 3;
signal count2: integer range 0 to 3;
signal count3: std_logic;
begin
clk1 <= clk;
nclk1 <= not clk;
clk2 <= count3;
nclk2 <= not count3;
process(nreset, clk)
begin
if nreset = '0' then
count1 <= 0;
count2 <= 0;
count3 <= '0';
w0 <= '0';w1 <= '0';w2 <= '0';w3 <= '0';
elsif rising_edge(clk) then
count3 <= not count3;
if count1 = 0 then
if count2 = 0 then
w0 <= '1';w1 <= '0';w2 <= '0';w3 <= '0';
elsif count2 = 1 then
w0 <= '0';w1 <= '1';w2 <= '0';w3 <= '0';
elsif count2 = 2 then
w0 <= '0';w1 <= '0';w2 <= '1';w3 <= '0';
else
w0 <= '0';w1 <= '0';w2 <= '0';w3 <= '1';
end if;
if count2 = 3 then
count2 <= 0;
else
count2 <= count2 + 1;
end if;
end if;
if count1 = 1 then
count1 <= 0;
else
count1 <= count1 + 1;
end if;
end if;
end process;
end Behavioral;
|
-- tracking_camera_system_sram_0_avalon_sram_slave_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_sram_0_avalon_sram_slave_translator is
generic (
AV_ADDRESS_W : integer := 18;
AV_DATA_W : integer := 16;
UAV_DATA_W : integer := 16;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 2;
UAV_BYTEENABLE_W : integer := 2;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 2;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 2;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- .readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(17 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(15 downto 0); -- .writedata
av_byteenable : out std_logic_vector(1 downto 0); -- .byteenable
av_readdatavalid : in std_logic := '0'; -- .readdatavalid
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(1 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_sram_0_avalon_sram_slave_translator;
architecture rtl of tracking_camera_system_sram_0_avalon_sram_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(17 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
sram_0_avalon_sram_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_readdatavalid => av_readdatavalid, -- .readdatavalid
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_sram_0_avalon_sram_slave_translator
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ios_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ios_e-rtl-a.vhd,v 1.3 2005/07/19 07:13:10 wig Exp $
-- $Date: 2005/07/19 07:13:10 $
-- $Log: ios_e-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:10 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ios_e
--
architecture rtl of ios_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioblock0_e --
-- No Generated Generics
port (
-- Generated Port for Entity ioblock0_e
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_6_gi : in std_ulogic;
p_mix_iosel_7_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic
-- End of Generated Port for Entity ioblock0_e
);
end component;
-- ---------
component ioblock1_e --
-- No Generated Generics
port (
-- Generated Port for Entity ioblock1_e
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_iosel_ms_min_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic
-- End of Generated Port for Entity ioblock1_e
);
end component;
-- ---------
component ioblock2_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ioblock3_e --
-- No Generated Generics
port (
-- Generated Port for Entity ioblock3_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ioblock3_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal d9_di : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_do : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_en : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_pu : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i33 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i34 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o35 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o36 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal di2 : std_ulogic_vector(8 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2_en : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_bus : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_disp : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_d9_di_go <= d9_di; -- __I_O_BUS_PORT
d9_do <= p_mix_d9_do_gi; -- __I_I_BUS_PORT
d9_en <= p_mix_d9_en_gi; -- __I_I_BUS_PORT
d9_pu <= p_mix_d9_pu_gi; -- __I_I_BUS_PORT
p_mix_data_i1_go <= data_i1; -- __I_O_BUS_PORT
p_mix_data_i33_go <= data_i33; -- __I_O_BUS_PORT
p_mix_data_i34_go <= data_i34; -- __I_O_BUS_PORT
data_o1 <= p_mix_data_o1_gi; -- __I_I_BUS_PORT
data_o35 <= p_mix_data_o35_gi; -- __I_I_BUS_PORT
data_o36 <= p_mix_data_o36_gi; -- __I_I_BUS_PORT
p_mix_di2_1_0_go(1 downto 0) <= di2(1 downto 0); -- __I_O_SLICE_PORT
p_mix_di2_7_3_go(4 downto 0) <= di2(7 downto 3); -- __I_O_SLICE_PORT
disp2(1 downto 0) <= p_mix_disp2_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2(7 downto 3) <= p_mix_disp2_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(7 downto 3) <= p_mix_disp2_en_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(1 downto 0) <= p_mix_disp2_en_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ls_hr <= p_mix_display_ls_hr_gi; -- __I_I_BUS_PORT
display_ls_min <= p_mix_display_ls_min_gi; -- __I_I_BUS_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
display_ms_hr <= p_mix_display_ms_hr_gi; -- __I_I_BUS_PORT
display_ms_min <= p_mix_display_ms_min_gi; -- __I_I_BUS_PORT
iosel_0 <= p_mix_iosel_0_gi; -- __I_I_BIT_PORT
iosel_1 <= p_mix_iosel_1_gi; -- __I_I_BIT_PORT
iosel_2 <= p_mix_iosel_2_gi; -- __I_I_BIT_PORT
iosel_3 <= p_mix_iosel_3_gi; -- __I_I_BIT_PORT
iosel_4 <= p_mix_iosel_4_gi; -- __I_I_BIT_PORT
iosel_5 <= p_mix_iosel_5_gi; -- __I_I_BIT_PORT
iosel_6 <= p_mix_iosel_6_gi; -- __I_I_BIT_PORT
iosel_7 <= p_mix_iosel_7_gi; -- __I_I_BIT_PORT
iosel_bus <= p_mix_iosel_bus_gi; -- __I_I_BUS_PORT
iosel_disp <= p_mix_iosel_disp_gi; -- __I_I_BIT_PORT
iosel_ls_hr <= p_mix_iosel_ls_hr_gi; -- __I_I_BIT_PORT
iosel_ls_min <= p_mix_iosel_ls_min_gi; -- __I_I_BIT_PORT
iosel_ms_hr <= p_mix_iosel_ms_hr_gi; -- __I_I_BIT_PORT
iosel_ms_min <= p_mix_iosel_ms_min_gi; -- __I_I_BIT_PORT
pad_di_1 <= p_mix_pad_di_1_gi; -- __I_I_BIT_PORT
pad_di_12 <= p_mix_pad_di_12_gi; -- __I_I_BIT_PORT
pad_di_13 <= p_mix_pad_di_13_gi; -- __I_I_BIT_PORT
pad_di_14 <= p_mix_pad_di_14_gi; -- __I_I_BIT_PORT
pad_di_15 <= p_mix_pad_di_15_gi; -- __I_I_BIT_PORT
pad_di_16 <= p_mix_pad_di_16_gi; -- __I_I_BIT_PORT
pad_di_17 <= p_mix_pad_di_17_gi; -- __I_I_BIT_PORT
pad_di_18 <= p_mix_pad_di_18_gi; -- __I_I_BIT_PORT
pad_di_31 <= p_mix_pad_di_31_gi; -- __I_I_BIT_PORT
pad_di_32 <= p_mix_pad_di_32_gi; -- __I_I_BIT_PORT
pad_di_33 <= p_mix_pad_di_33_gi; -- __I_I_BIT_PORT
pad_di_34 <= p_mix_pad_di_34_gi; -- __I_I_BIT_PORT
pad_di_39 <= p_mix_pad_di_39_gi; -- __I_I_BIT_PORT
pad_di_40 <= p_mix_pad_di_40_gi; -- __I_I_BIT_PORT
p_mix_pad_do_12_go <= pad_do_12; -- __I_O_BIT_PORT
p_mix_pad_do_13_go <= pad_do_13; -- __I_O_BIT_PORT
p_mix_pad_do_14_go <= pad_do_14; -- __I_O_BIT_PORT
p_mix_pad_do_15_go <= pad_do_15; -- __I_O_BIT_PORT
p_mix_pad_do_16_go <= pad_do_16; -- __I_O_BIT_PORT
p_mix_pad_do_17_go <= pad_do_17; -- __I_O_BIT_PORT
p_mix_pad_do_18_go <= pad_do_18; -- __I_O_BIT_PORT
p_mix_pad_do_2_go <= pad_do_2; -- __I_O_BIT_PORT
p_mix_pad_do_31_go <= pad_do_31; -- __I_O_BIT_PORT
p_mix_pad_do_32_go <= pad_do_32; -- __I_O_BIT_PORT
p_mix_pad_do_35_go <= pad_do_35; -- __I_O_BIT_PORT
p_mix_pad_do_36_go <= pad_do_36; -- __I_O_BIT_PORT
p_mix_pad_do_39_go <= pad_do_39; -- __I_O_BIT_PORT
p_mix_pad_do_40_go <= pad_do_40; -- __I_O_BIT_PORT
p_mix_pad_en_12_go <= pad_en_12; -- __I_O_BIT_PORT
p_mix_pad_en_13_go <= pad_en_13; -- __I_O_BIT_PORT
p_mix_pad_en_14_go <= pad_en_14; -- __I_O_BIT_PORT
p_mix_pad_en_15_go <= pad_en_15; -- __I_O_BIT_PORT
p_mix_pad_en_16_go <= pad_en_16; -- __I_O_BIT_PORT
p_mix_pad_en_17_go <= pad_en_17; -- __I_O_BIT_PORT
p_mix_pad_en_18_go <= pad_en_18; -- __I_O_BIT_PORT
p_mix_pad_en_2_go <= pad_en_2; -- __I_O_BIT_PORT
p_mix_pad_en_31_go <= pad_en_31; -- __I_O_BIT_PORT
p_mix_pad_en_32_go <= pad_en_32; -- __I_O_BIT_PORT
p_mix_pad_en_35_go <= pad_en_35; -- __I_O_BIT_PORT
p_mix_pad_en_36_go <= pad_en_36; -- __I_O_BIT_PORT
p_mix_pad_en_39_go <= pad_en_39; -- __I_O_BIT_PORT
p_mix_pad_en_40_go <= pad_en_40; -- __I_O_BIT_PORT
p_mix_pad_pu_31_go <= pad_pu_31; -- __I_O_BIT_PORT
p_mix_pad_pu_32_go <= pad_pu_32; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioblock_0
ioblock_0: ioblock0_e
port map (
p_mix_data_i1_go => data_i1, -- io data
p_mix_data_o1_gi => data_o1, -- io data
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_1_gi => iosel_1, -- IO_Select
p_mix_iosel_2_gi => iosel_2, -- IO_Select
p_mix_iosel_3_gi => iosel_3, -- IO_Select
p_mix_iosel_4_gi => iosel_4, -- IO_Select
p_mix_iosel_5_gi => iosel_5, -- IO_Select
p_mix_iosel_6_gi => iosel_6, -- IO_Select
p_mix_iosel_7_gi => iosel_7, -- IO_Select
p_mix_pad_di_1_gi => pad_di_1, -- data in from pad
p_mix_pad_do_2_go => pad_do_2, -- data out to pad
p_mix_pad_en_2_go => pad_en_2 -- pad output enable
);
-- End of Generated Instance Port Map for ioblock_0
-- Generated Instance Port Map for ioblock_1
ioblock_1: ioblock1_e
port map (
p_mix_di2_1_0_go => di2(1 downto 0), -- io data
p_mix_di2_7_3_go => di2(7 downto 3), -- io data
p_mix_disp2_1_0_gi => disp2(1 downto 0), -- io data
p_mix_disp2_7_3_gi => disp2(7 downto 3), -- io data
p_mix_disp2_en_1_0_gi => disp2_en(1 downto 0), -- io data
p_mix_disp2_en_7_3_gi => disp2_en(7 downto 3), -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ls_hr_gi => display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_gi => display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_display_ms_hr_gi => display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_gi => display_ms_min, -- Display storage buffer 1 ms_min
p_mix_iosel_disp_gi => iosel_disp, -- IO_Select
p_mix_iosel_ls_hr_gi => iosel_ls_hr, -- IO_Select
p_mix_iosel_ls_min_gi => iosel_ls_min, -- IO_Select
p_mix_iosel_ms_hr_gi => iosel_ms_hr, -- IO_Select
p_mix_iosel_ms_min_gi => iosel_ms_min, -- IO_Select
p_mix_pad_di_12_gi => pad_di_12, -- data in from pad
p_mix_pad_di_13_gi => pad_di_13, -- data in from pad
p_mix_pad_di_14_gi => pad_di_14, -- data in from pad
p_mix_pad_di_15_gi => pad_di_15, -- data in from pad
p_mix_pad_di_16_gi => pad_di_16, -- data in from pad
p_mix_pad_di_17_gi => pad_di_17, -- data in from pad
p_mix_pad_di_18_gi => pad_di_18, -- data in from pad
p_mix_pad_do_12_go => pad_do_12, -- data out to pad
p_mix_pad_do_13_go => pad_do_13, -- data out to pad
p_mix_pad_do_14_go => pad_do_14, -- data out to pad
p_mix_pad_do_15_go => pad_do_15, -- data out to pad
p_mix_pad_do_16_go => pad_do_16, -- data out to pad
p_mix_pad_do_17_go => pad_do_17, -- data out to pad
p_mix_pad_do_18_go => pad_do_18, -- data out to pad
p_mix_pad_en_12_go => pad_en_12, -- pad output enable
p_mix_pad_en_13_go => pad_en_13, -- pad output enable
p_mix_pad_en_14_go => pad_en_14, -- pad output enable
p_mix_pad_en_15_go => pad_en_15, -- pad output enable
p_mix_pad_en_16_go => pad_en_16, -- pad output enable
p_mix_pad_en_17_go => pad_en_17, -- pad output enable
p_mix_pad_en_18_go => pad_en_18 -- pad output enable
);
-- End of Generated Instance Port Map for ioblock_1
-- Generated Instance Port Map for ioblock_2
ioblock_2: ioblock2_e
;
-- End of Generated Instance Port Map for ioblock_2
-- Generated Instance Port Map for ioblock_3
ioblock_3: ioblock3_e
port map (
p_mix_d9_di_go => d9_di, -- d9io
p_mix_d9_do_gi => d9_do, -- d9io
p_mix_d9_en_gi => d9_en, -- d9io
p_mix_d9_pu_gi => d9_pu, -- d9io
p_mix_data_i33_go => data_i33, -- io data
p_mix_data_i34_go => data_i34, -- io data
p_mix_data_o35_gi => data_o35, -- io data
p_mix_data_o36_gi => data_o36, -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_bus_gi => iosel_bus, -- io data
p_mix_pad_di_31_gi => pad_di_31, -- data in from pad
p_mix_pad_di_32_gi => pad_di_32, -- data in from pad
p_mix_pad_di_33_gi => pad_di_33, -- data in from pad
p_mix_pad_di_34_gi => pad_di_34, -- data in from pad
p_mix_pad_di_39_gi => pad_di_39, -- data in from pad
p_mix_pad_di_40_gi => pad_di_40, -- data in from pad
p_mix_pad_do_31_go => pad_do_31, -- data out to pad
p_mix_pad_do_32_go => pad_do_32, -- data out to pad
p_mix_pad_do_35_go => pad_do_35, -- data out to pad
p_mix_pad_do_36_go => pad_do_36, -- data out to pad
p_mix_pad_do_39_go => pad_do_39, -- data out to pad
p_mix_pad_do_40_go => pad_do_40, -- data out to pad
p_mix_pad_en_31_go => pad_en_31, -- pad output enable
p_mix_pad_en_32_go => pad_en_32, -- pad output enable
p_mix_pad_en_35_go => pad_en_35, -- pad output enable
p_mix_pad_en_36_go => pad_en_36, -- pad output enable
p_mix_pad_en_39_go => pad_en_39, -- pad output enable
p_mix_pad_en_40_go => pad_en_40, -- pad output enable
p_mix_pad_pu_31_go => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_go => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for ioblock_3
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1351.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p02n01i01351ent IS
END c08s05b00x00p02n01i01351ent;
ARCHITECTURE c08s05b00x00p02n01i01351arch OF c08s05b00x00p02n01i01351ent IS
BEGIN
TESTING: PROCESS
function check (x : integer) return integer is
begin
return (10 * x);
end;
variable k : integer := 0;
variable p : integer := 12;
BEGIN
check(k) := check(p) + 24;
assert FALSE
report "***FAILED TEST: c08s05b00x00p02n01i01351 - Target of a variable assignment can only be a name or an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p02n01i01351arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1351.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p02n01i01351ent IS
END c08s05b00x00p02n01i01351ent;
ARCHITECTURE c08s05b00x00p02n01i01351arch OF c08s05b00x00p02n01i01351ent IS
BEGIN
TESTING: PROCESS
function check (x : integer) return integer is
begin
return (10 * x);
end;
variable k : integer := 0;
variable p : integer := 12;
BEGIN
check(k) := check(p) + 24;
assert FALSE
report "***FAILED TEST: c08s05b00x00p02n01i01351 - Target of a variable assignment can only be a name or an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p02n01i01351arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1351.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p02n01i01351ent IS
END c08s05b00x00p02n01i01351ent;
ARCHITECTURE c08s05b00x00p02n01i01351arch OF c08s05b00x00p02n01i01351ent IS
BEGIN
TESTING: PROCESS
function check (x : integer) return integer is
begin
return (10 * x);
end;
variable k : integer := 0;
variable p : integer := 12;
BEGIN
check(k) := check(p) + 24;
assert FALSE
report "***FAILED TEST: c08s05b00x00p02n01i01351 - Target of a variable assignment can only be a name or an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p02n01i01351arch;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v1.01.a
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library my_ipif;
use my_ipif.proc_common_pkg.clog2;
use my_ipif.ipif_pkg.SLV64_ARRAY_TYPE;
use my_ipif.ipif_pkg.INTEGER_ARRAY_TYPE;
use my_ipif.ipif_pkg.calc_num_ce;
use my_ipif.ipif_pkg.calc_start_ce_index;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity work.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity work.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v1.01.a
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library my_ipif;
use my_ipif.proc_common_pkg.clog2;
use my_ipif.ipif_pkg.SLV64_ARRAY_TYPE;
use my_ipif.ipif_pkg.INTEGER_ARRAY_TYPE;
use my_ipif.ipif_pkg.calc_num_ce;
use my_ipif.ipif_pkg.calc_start_ce_index;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity work.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity work.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc17.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p08n01i00017ent IS
END c04s02b00x00p08n01i00017ent;
ARCHITECTURE c04s02b00x00p08n01i00017arch OF c04s02b00x00p08n01i00017ent IS
-- Forward declaration of the function.
function WIRED_OR( S : BIT_VECTOR ) return BIT;
-- Declare the subtype.
subtype RBIT is WIRED_OR BIT;
-- Declare the actual function.
function WIRED_OR( S : BIT_VECTOR ) return BIT is
begin
assert FALSE
report "***PASSED TEST: c04s02b00x00p08n01i00017"
severity NOTE;
if ( (S(0) = '1') OR (S(1) = '1')) then
return '1';
end if;
return '0';
end WIRED_OR;
-- Declare a signal of that type. A resolved signal.
signal S : RBIT;
BEGIN
-- A concurrent signal assignment. Driver # 1.
S <= '1';
TESTING: PROCESS
BEGIN
-- Verify that resolution function getting called.
S <= '1' after 10 ns;
wait on S;
assert NOT( S = '1' )
report "***PASSED TEST: c04s02b00x00p08n01i00017"
severity NOTE;
assert ( S = '1' )
report "***FAILED TEST: c04s02b00x00p08n01i00017 - If a resolution function name appears in a subtype, all signals declared to be of that subtype are resolved by that function."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p08n01i00017arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc17.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p08n01i00017ent IS
END c04s02b00x00p08n01i00017ent;
ARCHITECTURE c04s02b00x00p08n01i00017arch OF c04s02b00x00p08n01i00017ent IS
-- Forward declaration of the function.
function WIRED_OR( S : BIT_VECTOR ) return BIT;
-- Declare the subtype.
subtype RBIT is WIRED_OR BIT;
-- Declare the actual function.
function WIRED_OR( S : BIT_VECTOR ) return BIT is
begin
assert FALSE
report "***PASSED TEST: c04s02b00x00p08n01i00017"
severity NOTE;
if ( (S(0) = '1') OR (S(1) = '1')) then
return '1';
end if;
return '0';
end WIRED_OR;
-- Declare a signal of that type. A resolved signal.
signal S : RBIT;
BEGIN
-- A concurrent signal assignment. Driver # 1.
S <= '1';
TESTING: PROCESS
BEGIN
-- Verify that resolution function getting called.
S <= '1' after 10 ns;
wait on S;
assert NOT( S = '1' )
report "***PASSED TEST: c04s02b00x00p08n01i00017"
severity NOTE;
assert ( S = '1' )
report "***FAILED TEST: c04s02b00x00p08n01i00017 - If a resolution function name appears in a subtype, all signals declared to be of that subtype are resolved by that function."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p08n01i00017arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc17.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p08n01i00017ent IS
END c04s02b00x00p08n01i00017ent;
ARCHITECTURE c04s02b00x00p08n01i00017arch OF c04s02b00x00p08n01i00017ent IS
-- Forward declaration of the function.
function WIRED_OR( S : BIT_VECTOR ) return BIT;
-- Declare the subtype.
subtype RBIT is WIRED_OR BIT;
-- Declare the actual function.
function WIRED_OR( S : BIT_VECTOR ) return BIT is
begin
assert FALSE
report "***PASSED TEST: c04s02b00x00p08n01i00017"
severity NOTE;
if ( (S(0) = '1') OR (S(1) = '1')) then
return '1';
end if;
return '0';
end WIRED_OR;
-- Declare a signal of that type. A resolved signal.
signal S : RBIT;
BEGIN
-- A concurrent signal assignment. Driver # 1.
S <= '1';
TESTING: PROCESS
BEGIN
-- Verify that resolution function getting called.
S <= '1' after 10 ns;
wait on S;
assert NOT( S = '1' )
report "***PASSED TEST: c04s02b00x00p08n01i00017"
severity NOTE;
assert ( S = '1' )
report "***FAILED TEST: c04s02b00x00p08n01i00017 - If a resolution function name appears in a subtype, all signals declared to be of that subtype are resolved by that function."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p08n01i00017arch;
|
architecture behavior of tb_SPIControl is
constant DataWidth : integer range 2 to 64 := 8;
-- Component Declaration for the Unit Under Test (UUT)
component SPIControl is
Generic (
DataWidth : integer range 2 to 64 := 8);
Port (
Reset_n : in STD_LOGIC;
Clk : in STD_LOGIC;
-- SPI config param
CPOL_i : in STD_LOGIC;
CPHA_i : in STD_LOGIC;
-- SPI clock output
SCK_o : out STD_LOGIC;
-- SPI control signals
Transmission_o : out STD_LOGIC;
EnFrqDivider_o : out STD_LOGIC;
NextStep_i : in STD_LOGIC;
LdShifter_o : out STD_LOGIC;
EnShift_o : out STD_LOGIC;
EnSample_o : out STD_LOGIC;
WrFIFOEmpty_i : in STD_LOGIC;
RdWriteFIFO_o : out STD_LOGIC;
RdFIFOFull_i : in STD_LOGIC;
LdReadFIFO_o : out STD_LOGIC);
end component;
-- Inputs
signal Reset_n : STD_LOGIC := '0';
signal Clk : STD_LOGIC := '0';
signal CPOL : STD_LOGIC := '0';
signal CPHA : STD_LOGIC := '0';
signal NextStep : STD_LOGIC := '1';
signal WrFIFOEmpty : STD_LOGIC := '1';
signal RdFIFOFull : STD_LOGIC := '0';
-- Outputs
signal SCK : STD_LOGIC;
signal Transmission : STD_LOGIC;
signal EnFrqDivider : STD_LOGIC;
signal LdShifter : STD_LOGIC;
signal EnShift : STD_LOGIC;
signal EnSample : STD_LOGIC;
signal RdWriteFIFO : STD_LOGIC;
signal LdReadFIFO : STD_LOGIC;
-- TB control signals
signal ClkDivby3 : STD_LOGIC := '0';
-- Clock period definitions
constant Clk_period : time := 10 us;
constant Clk_delay : time := Clk_period/10;
begin
-- Instantiate the Unit Under Test (UUT)
uut: SPIControl
Generic Map (
DataWidth => DataWidth)
Port Map (
Reset_n => Reset_n,
Clk => Clk,
CPOL_i => CPOL,
CPHA_i => CPHA,
SCK_o => SCK,
Transmission_o => Transmission,
EnFrqDivider_o => EnFrqDivider,
NextStep_i => NextStep,
LdShifter_o => LdShifter,
EnShift_o => EnShift,
EnSample_o => EnSample,
WrFIFOEmpty_i => WrFIFOEmpty,
RdWriteFIFO_o => RdWriteFIFO,
RdFIFOFull_i => RdFIFOFull,
LdReadFIFO_o => LdReadFIFO);
-- Clock process definitions
Clk_process: process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process Clk_process;
-- Clock Divider by 3
ClockkDividerby3: process
begin
if ClkDivby3 = '0' then
NextStep <= '1';
wait until Clk'event and Clk = '1';
else
NextStep <= '0';
wait until Clk'event and Clk = '1';
NextStep <= '0';
wait until Clk'event and Clk = '1';
NextStep <= '1';
wait until Clk'event and Clk = '1';
end if;
end process ClockkDividerby3;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for Clk_period*5.
wait for Clk_period*5;
Reset_n <= '1';
wait for Clk_period*5;
-- testcase 1: test for initial state
report "testcase 1" severity note;
assert SCK = '0'
report "SCK_o should be '0' after reset"
severity error;
assert Transmission = '0'
report "Transmission_o should be '0' after reset"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0' after reset"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0' after reset"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' after reset"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' after reset"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' after reset"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' after reset"
severity error;
-- end testcase 1;
-- testcase 2: idle - transmission - transmission - idle
-- baudrate = clk / 6
-- testcase 2a: CPOL = 0, CPHA = 0
report "testcase 2a" severity note;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
CPOL <= '0';
CPHA <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
ClkDivby3 <= '1';
WrFIFOEmpty <= '0'; -- start transmission
RdFIFOFull <= '0';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at start of testcase 2a"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' after transmission has started"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' after transmission has started"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at start of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at start of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at start of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at start of transmission"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' at start of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '0'; -- continue transmission
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1' at restart of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at restart of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at restart of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at restart of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at restart of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1' at end of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at end of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at end of transmission"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' at end of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at end of transmission"
severity error;
ClkDivby3 <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
-- end testcase 2a;
-- testcase 2b: CPOL = 1, CPHA = 0
report "testcase 2b" severity note;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
CPOL <= '1';
CPHA <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
ClkDivby3 <= '1';
WrFIFOEmpty <= '0'; -- start transmission
RdFIFOFull <= '0';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1' at start of testcase 2b"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' after transmission has started"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' after transmission has started"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at start of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at start of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at start of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at start of transmission"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' at start of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '0'; -- continue transmission
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at restart of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at restart of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at restart of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at restart of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at restart of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at end of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at end of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at end of transmission"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' at end of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at end of transmission"
severity error;
ClkDivby3 <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
-- end testcase 2b;
-- testcase 2c: CPOL = 0, CPHA = 1
report "testcase 2c" severity note;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
CPOL <= '0';
CPHA <= '1';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
ClkDivby3 <= '1';
WrFIFOEmpty <= '0'; -- start transmission
RdFIFOFull <= '0';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at start of testcase 2c"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' after transmission has started"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' after transmission has started"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at start of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at start of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at start of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at start of transmission"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' at start of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '0'; -- continue transmission
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at restart of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at restart of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at restart of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at restart of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at restart of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at end of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at end of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at end of transmission"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' at end of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at end of transmission"
severity error;
ClkDivby3 <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
-- end testcase 2c;
-- testcase 2d: CPOL = 1, CPHA = 1
report "testcase 2d" severity note;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
CPOL <= '1';
CPHA <= '1';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
ClkDivby3 <= '1';
WrFIFOEmpty <= '0'; -- start transmission
RdFIFOFull <= '0';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1' at start of testcase 2d"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' after transmission has started"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' after transmission has started"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at start of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at start of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at start of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at start of transmission"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' at start of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '0'; -- continue transmission
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1' at restart of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at restart of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at restart of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at restart of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at restart of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1' at end of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at end of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at end of transmission"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' at end of transmission"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at end of transmission"
severity error;
ClkDivby3 <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
-- end testcase 2d;
-- end testcase 2;
-- testcase 3: idle - transmission - suspend - suspend -
-- transmission - suspend - idle
-- baudrate = clk / 2
-- testcase 3a: CPOL = 0, CPHA = 0
report "testcase 3a" severity note;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
CPOL <= '0';
CPHA <= '0';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
ClkDivby3 <= '0';
WrFIFOEmpty <= '0'; -- start transmission
RdFIFOFull <= '1'; -- force suspend
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at start of testcase 3a"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' after transmission has started"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' after transmission has started"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at start of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at start of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at start of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at start of transmission"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' at start of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1'"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' before entering suspend mode"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0' before entering suspend mode"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0' before entering suspend mode"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' before entering suspend mode"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' before entering suspend mode"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' before entering suspend mode"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' before entering suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
RdFIFOFull <= '0'; -- release from suspend
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at recovering from suspend mode"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' at recovering from suspend mode"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' at recovering from suspend mode"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at recovering from suspend mode"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at recovering from suspend mode"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at recovering from suspend mode"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at recovering from suspend mode"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at recovering from suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
RdFIFOFull <= '1'; -- force suspend after transmission
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1'"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' before entering suspend mode"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0' before entering suspend mode"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0' before entering suspend mode"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' before entering suspend mode"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' before entering suspend mode"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' before entering suspend mode"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' before entering suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
RdFIFOFull <= '0'; -- release from suspend
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1'"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '0'
report "Transmission_o should be '0'"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
-- end testcase 3a;
-- testcase 3b: CPOL = 0, CPHA = 1
report "testcase 3b" severity note;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
CPOL <= '0';
CPHA <= '1';
wait until Clk'event and Clk = '1';
wait for Clk_delay;
ClkDivby3 <= '0';
WrFIFOEmpty <= '0'; -- start transmission
RdFIFOFull <= '1'; -- force suspend
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at start of testcase 3b"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' after transmission has started"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' after transmission has started"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at start of transmission"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at start of transmission"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at start of transmission"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at start of transmission"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' at start of transmission"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1'"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' before entering suspend mode"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0' before entering suspend mode"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0' before entering suspend mode"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' before entering suspend mode"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' before entering suspend mode"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' before entering suspend mode"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' before entering suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
RdFIFOFull <= '0'; -- release from suspend
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0' at recovering from suspend mode"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' at recovering from suspend mode"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1' at recovering from suspend mode"
severity error;
assert LdShifter = '1'
report "LdShifter_o should be '1' at recovering from suspend mode"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' at recovering from suspend mode"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' at recovering from suspend mode"
severity error;
assert RdWriteFIFO = '1'
report "RdWriteFIFO_o should be '1' at recovering from suspend mode"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1' at recovering from suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
WrFIFOEmpty <= '1';
RdFIFOFull <= '1'; -- force suspend after transmission
for BitCounter in DataWidth - 1 downto 1 loop
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert EnShift = '1'
report "EnShift_o should be '1'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
end loop;
assert SCK = '1'
report "SCK_o should be '1'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1'"
severity error;
assert EnFrqDivider = '1'
report "EnFrqDivider_o should be '1'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '1'
report "EnSample_o should be '1'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1' before entering suspend mode"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0' before entering suspend mode"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0' before entering suspend mode"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0' before entering suspend mode"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0' before entering suspend mode"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0' before entering suspend mode"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0' before entering suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert Transmission = '1'
report "Transmission_o should be '1' in suspend mode"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
RdFIFOFull <= '0'; -- release from suspend
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '1'
report "Transmission_o should be '1'"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '1'
report "LdReadFIFO_o should be '1'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
assert SCK = '0'
report "SCK_o should be '0'"
severity error;
assert Transmission = '0'
report "Transmission_o should be '0'"
severity error;
assert EnFrqDivider = '0'
report "EnFrqDivider_o should be '0'"
severity error;
assert LdShifter = '0'
report "LdShifter_o should be '0'"
severity error;
assert EnShift = '0'
report "EnShift_o should be '0'"
severity error;
assert EnSample = '0'
report "EnSample_o should be '0'"
severity error;
assert RdWriteFIFO = '0'
report "RdWriteFIFO_o should be '0'"
severity error;
assert LdReadFIFO = '0'
report "LdReadFIFO_o should be '0'"
severity error;
wait until Clk'event and Clk = '1';
wait for Clk_delay;
-- end testcase 3b;
-- end testcase 3;
-- insert some space time
wait for Clk_period*5;
-- end simulation
report "NONE. Simulation finished" severity failure; -- used to stop simulation
end process;
end behavior;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_1_0_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_slice_1_0_0;
ARCHITECTURE RAT_slice_1_0_0_arch OF RAT_slice_1_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_1_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT xlslice;
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 7,
DIN_TO => 0
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_1_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_1_0_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_slice_1_0_0;
ARCHITECTURE RAT_slice_1_0_0_arch OF RAT_slice_1_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_1_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT xlslice;
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 7,
DIN_TO => 0
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_1_0_0_arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_rgb2ycrcb:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_rgb2ycrcb_v7_1;
USE v_rgb2ycrcb_v7_1.v_rgb2ycrcb;
ENTITY tutorial_v_rgb2ycrcb_0_0 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
s_axis_video_tuser_sof : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser_sof : OUT STD_LOGIC
);
END tutorial_v_rgb2ycrcb_0_0;
ARCHITECTURE tutorial_v_rgb2ycrcb_0_0_arch OF tutorial_v_rgb2ycrcb_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_rgb2ycrcb_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_rgb2ycrcb IS
GENERIC (
C_S_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_FORMAT : INTEGER;
C_S_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_FORMAT : INTEGER;
C_M_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
c_s_axi_addr_width : INTEGER;
c_s_axi_data_width : INTEGER;
C_HAS_AXI4_LITE : INTEGER;
C_HAS_DEBUG : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_MAX_COLS : INTEGER;
C_ACTIVE_COLS : INTEGER;
C_ACTIVE_ROWS : INTEGER;
C_HAS_CLIP : INTEGER;
C_HAS_CLAMP : INTEGER;
C_ACOEF : INTEGER;
C_BCOEF : INTEGER;
C_CCOEF : INTEGER;
C_DCOEF : INTEGER;
C_YOFFSET : INTEGER;
C_CBOFFSET : INTEGER;
C_CROFFSET : INTEGER;
C_YMAX : INTEGER;
C_YMIN : INTEGER;
C_CBMAX : INTEGER;
C_CBMIN : INTEGER;
C_CRMAX : INTEGER;
C_CRMIN : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_FAMILY : STRING
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
irq : OUT STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
s_axis_video_tuser_sof : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser_sof : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT v_rgb2ycrcb;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_v_rgb2ycrcb_0_0_arch: ARCHITECTURE IS "v_rgb2ycrcb,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_v_rgb2ycrcb_0_0_arch : ARCHITECTURE IS "tutorial_v_rgb2ycrcb_0_0,v_rgb2ycrcb,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tutorial_v_rgb2ycrcb_0_0_arch: ARCHITECTURE IS "tutorial_v_rgb2ycrcb_0_0,v_rgb2ycrcb,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=v_rgb2ycrcb,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXIS_VIDEO_DATA_WIDTH=8,C_S_AXIS_VIDEO_FORMAT=2,C_S_AXIS_VIDEO_TDATA_WIDTH=24,C_M_AXIS_VIDEO_DATA_WIDTH=8,C_M_AXIS_VIDEO_FORMAT=1,C_M_AXIS_VIDEO_TDATA_WIDTH=24,c_s_axi_addr_width=9,c_s_axi_data_width=32,C_HAS_AXI4_LITE=0,C_HAS_DEBUG=0,C_HAS_INTC_IF=0,C_MAX_COLS=1920,C_ACTIVE_COLS=1920,C_ACTIVE_ROWS=1080,C_HAS_CLIP=1,C_HAS_CLAMP=1,C_ACOEF=19595,C_BCOEF=7471,C_CCOEF=46727,C_DCOEF=36962,C_YOFFSET=16,C_CBOFFSET=128,C_CROFFSET=128,C_YMAX=240,C_YMIN=16,C_CBMAX=240,C_CBMIN=16,C_CRMAX=240,C_CRMIN=16,C_S_AXI_CLK_FREQ_HZ=100000000,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tuser_sof: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tuser_sof: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TUSER";
BEGIN
U0 : v_rgb2ycrcb
GENERIC MAP (
C_S_AXIS_VIDEO_DATA_WIDTH => 8,
C_S_AXIS_VIDEO_FORMAT => 2,
C_S_AXIS_VIDEO_TDATA_WIDTH => 24,
C_M_AXIS_VIDEO_DATA_WIDTH => 8,
C_M_AXIS_VIDEO_FORMAT => 1,
C_M_AXIS_VIDEO_TDATA_WIDTH => 24,
c_s_axi_addr_width => 9,
c_s_axi_data_width => 32,
C_HAS_AXI4_LITE => 0,
C_HAS_DEBUG => 0,
C_HAS_INTC_IF => 0,
C_MAX_COLS => 1920,
C_ACTIVE_COLS => 1920,
C_ACTIVE_ROWS => 1080,
C_HAS_CLIP => 1,
C_HAS_CLAMP => 1,
C_ACOEF => 19595,
C_BCOEF => 7471,
C_CCOEF => 46727,
C_DCOEF => 36962,
C_YOFFSET => 16,
C_CBOFFSET => 128,
C_CROFFSET => 128,
C_YMAX => 240,
C_YMIN => 16,
C_CBMAX => 240,
C_CBMIN => 16,
C_CRMAX => 240,
C_CRMIN => 16,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_FAMILY => "zynq"
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
s_axi_aclk => '0',
s_axi_aclken => '1',
s_axi_aresetn => '1',
s_axis_video_tdata => s_axis_video_tdata,
s_axis_video_tready => s_axis_video_tready,
s_axis_video_tvalid => s_axis_video_tvalid,
s_axis_video_tlast => s_axis_video_tlast,
s_axis_video_tuser_sof => s_axis_video_tuser_sof,
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tlast => m_axis_video_tlast,
m_axis_video_tuser_sof => m_axis_video_tuser_sof,
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_arvalid => '0',
s_axi_rready => '0'
);
END tutorial_v_rgb2ycrcb_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity simple01 is
port (a, b, c : in std_logic;
z : out std_logic);
end simple01;
architecture behav of simple01 is
begin
process(A, B, C)
variable temp : std_logic;
begin
if is_x (a) then
z <= b;
else
z <= b or c;
end if;
end process;
end behav;
|
entity issue524 is
end entity;
architecture test of issue524 is
signal s : real := 0.0;
begin
main: process is
begin
for i in 1 to 5 loop
s <= s + 0.5;
wait for 1 ns;
end loop;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- module_1_coprocessor_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library coprocessor_v2_00_a;
use coprocessor_v2_00_a.all;
entity module_1_coprocessor_0_wrapper is
port (
LED_OUT : out std_logic_vector(7 downto 0);
SW_IN : in std_logic_vector(7 downto 0);
BTN_IN : in std_logic_vector(4 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_AWID : in std_logic_vector(11 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_BID : out std_logic_vector(11 downto 0);
S_AXI_ARID : in std_logic_vector(11 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_RID : out std_logic_vector(11 downto 0);
S_AXI_RLAST : out std_logic
);
end module_1_coprocessor_0_wrapper;
architecture STRUCTURE of module_1_coprocessor_0_wrapper is
component coprocessor is
generic (
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_RDATA_FIFO_DEPTH : INTEGER;
C_INCLUDE_TIMEOUT_CNT : INTEGER;
C_TIMEOUT_CNTR_VAL : INTEGER;
C_ALIGN_BE_RDADDR : INTEGER;
C_S_AXI_SUPPORTS_WRITE : INTEGER;
C_S_AXI_SUPPORTS_READ : INTEGER;
C_FAMILY : STRING;
C_S_AXI_MEM0_BASEADDR : std_logic_vector;
C_S_AXI_MEM0_HIGHADDR : std_logic_vector;
C_S_AXI_MEM1_BASEADDR : std_logic_vector;
C_S_AXI_MEM1_HIGHADDR : std_logic_vector;
C_S_AXI_MEM2_BASEADDR : std_logic_vector;
C_S_AXI_MEM2_HIGHADDR : std_logic_vector
);
port (
LED_OUT : out std_logic_vector(7 downto 0);
SW_IN : in std_logic_vector(7 downto 0);
BTN_IN : in std_logic_vector(4 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_AWID : in std_logic_vector((C_S_AXI_ID_WIDTH-1) downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_BID : out std_logic_vector((C_S_AXI_ID_WIDTH-1) downto 0);
S_AXI_ARID : in std_logic_vector((C_S_AXI_ID_WIDTH-1) downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_RID : out std_logic_vector((C_S_AXI_ID_WIDTH-1) downto 0);
S_AXI_RLAST : out std_logic
);
end component;
begin
coprocessor_0 : coprocessor
generic map (
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_RDATA_FIFO_DEPTH => 0,
C_INCLUDE_TIMEOUT_CNT => 1,
C_TIMEOUT_CNTR_VAL => 8,
C_ALIGN_BE_RDADDR => 0,
C_S_AXI_SUPPORTS_WRITE => 1,
C_S_AXI_SUPPORTS_READ => 1,
C_FAMILY => "zynq",
C_S_AXI_MEM0_BASEADDR => X"75800000",
C_S_AXI_MEM0_HIGHADDR => X"75800FFF",
C_S_AXI_MEM1_BASEADDR => X"75801000",
C_S_AXI_MEM1_HIGHADDR => X"75801FFF",
C_S_AXI_MEM2_BASEADDR => X"75802000",
C_S_AXI_MEM2_HIGHADDR => X"75802FFF"
)
port map (
LED_OUT => LED_OUT,
SW_IN => SW_IN,
BTN_IN => BTN_IN,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWLOCK => S_AXI_AWLOCK,
S_AXI_AWCACHE => S_AXI_AWCACHE,
S_AXI_AWPROT => S_AXI_AWPROT,
S_AXI_WLAST => S_AXI_WLAST,
S_AXI_BID => S_AXI_BID,
S_AXI_ARID => S_AXI_ARID,
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARLOCK => S_AXI_ARLOCK,
S_AXI_ARCACHE => S_AXI_ARCACHE,
S_AXI_ARPROT => S_AXI_ARPROT,
S_AXI_RID => S_AXI_RID,
S_AXI_RLAST => S_AXI_RLAST
);
end architecture STRUCTURE;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Tue May 13 22:55:34 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/lab_6/ip/clk_base/clk_base_stub.vhdl
-- Design : clk_base
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_base is
Port (
clk_raw : in STD_LOGIC;
clk_250MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end clk_base;
architecture stub of clk_base is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_raw,clk_250MHz,locked";
begin
end;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: centre_positions_memory_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity centre_positions_memory_top is
port (
clk : in std_logic;
wea : in std_logic_vector(0 to PARALLEL_UNITS-1);
addra : in par_centre_index_type;
dina : in par_data_type;
addrb : in par_centre_index_type;
doutb : out par_data_type
);
end centre_positions_memory_top;
architecture Behavioral of centre_positions_memory_top is
type p_addr_type is array(0 to PARALLEL_UNITS-1) of std_logic_vector(INDEX_BITWIDTH-1 downto 0);
type p_data_type is array(0 to PARALLEL_UNITS-1) of std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
component centre_positions_memory
port (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(D*COORD_BITWIDTH-1 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(D*COORD_BITWIDTH-1 DOWNTO 0)
);
end component;
signal p_addra : p_addr_type;
signal p_addrb : p_addr_type;
signal p_dina : p_data_type;
signal p_doutb : p_data_type;
begin
-- fixme: this memory parallelism could also be achieved by memory segmentation which would be muhch better... to be done
G_PAR_0: for I in 0 to PARALLEL_UNITS-1 generate
p_addra(I) <= std_logic_vector(addra(I));
p_addrb(I) <= std_logic_vector(addrb(I));
p_dina(I) <= datapoint_2_stdlogic(dina(I));
centre_positions_memory_inst : centre_positions_memory
port map(
clka => clk,
wea(0) => wea(I),
addra => p_addra(I),
dina => p_dina(I),
clkb => clk,
addrb => p_addrb(I),
doutb => p_doutb(I)
);
doutb(I) <= stdlogic_2_datapoint(p_doutb(I));
end generate G_PAR_0;
end Behavioral;
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff1.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff1 IS
PORT
(
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC
);
END lpm_dff1;
ARCHITECTURE SYN OF lpm_dff1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1 <= sub_wire0(0);
q <= sub_wire1;
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "TFF",
lpm_type => "LPM_FF",
lpm_width => 1
)
PORT MAP (
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "TFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2240.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02240ent IS
END c07s02b06x00p01n01i02240ent;
ARCHITECTURE c07s02b06x00p01n01i02240arch OF c07s02b06x00p01n01i02240ent IS
BEGIN
TESTING: PROCESS
variable STRINGV : STRING( 1 to 32 );
variable k : integer;
BEGIN
k := STRINGV mod "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02240 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02240arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2240.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02240ent IS
END c07s02b06x00p01n01i02240ent;
ARCHITECTURE c07s02b06x00p01n01i02240arch OF c07s02b06x00p01n01i02240ent IS
BEGIN
TESTING: PROCESS
variable STRINGV : STRING( 1 to 32 );
variable k : integer;
BEGIN
k := STRINGV mod "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02240 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02240arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2240.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02240ent IS
END c07s02b06x00p01n01i02240ent;
ARCHITECTURE c07s02b06x00p01n01i02240arch OF c07s02b06x00p01n01i02240ent IS
BEGIN
TESTING: PROCESS
variable STRINGV : STRING( 1 to 32 );
variable k : integer;
BEGIN
k := STRINGV mod "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02240 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02240arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0_9;
USE dist_mem_gen_v8_0_9.dist_mem_gen_v8_0_9;
ENTITY Stack IS
PORT (
a : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END Stack;
ARCHITECTURE Stack_arch OF Stack IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Stack_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0_9 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0_9;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Stack_arch: ARCHITECTURE IS "dist_mem_gen_v8_0_9,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Stack_arch : ARCHITECTURE IS "Stack,dist_mem_gen_v8_0_9,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Stack_arch: ARCHITECTURE IS "Stack,dist_mem_gen_v8_0_9,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_ADDR_WIDTH=10,C_DEFAULT_DATA=0,C_DEPTH=1024,C_HAS_CLK=1,C_HAS_D=1,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=1,C_MEM_INIT_FILE=no_coe_file_loaded,C_ELABORATION_DIR=./,C_MEM_TYPE=1,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=0,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=16,C_PARSER_TYPE=1}";
BEGIN
U0 : dist_mem_gen_v8_0_9
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 10,
C_DEFAULT_DATA => "0",
C_DEPTH => 1024,
C_HAS_CLK => 1,
C_HAS_D => 1,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 1,
C_MEM_INIT_FILE => "no_coe_file_loaded",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 1,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 0,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 16,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => d,
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
clk => clk,
we => we,
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END Stack_arch;
|
entity textio2 is
end entity;
use std.textio.all;
architecture test of textio2 is
begin
process is
file tmp : text;
variable l : line;
variable str : string(1 to 5);
variable good : boolean;
variable ch : character;
begin
file_open(tmp, "tmp.txt", WRITE_MODE);
write(l, string'("hello, world"));
writeline(tmp, l);
write(l, string'("second"));
writeline(tmp, l);
deallocate(l);
file_close(tmp);
file_open(tmp, "tmp.txt", READ_MODE);
readline(tmp, l);
read(l, str);
assert str = "hello";
read(l, str);
assert str = ", wor";
read(l, str, good);
assert not good; -- Fewer than 5 chars
deallocate(l);
readline(tmp, l);
read(l, str);
assert str = "secon";
read(l, ch);
assert ch = 'd';
read(l, ch, good);
assert not good;
deallocate(l);
file_close(tmp);
wait;
end process;
end architecture;
|
--
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 17:04:14 05/14/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decimalTo7SEG is
port (
clk: in std_logic;
bcd: in std_logic_vector(3 downto 0);
segmented: out std_logic_vector(6 downto 0);
);
end decimalTo7SEG;
architecture Behavioral of decimalTo7SEG is
begin
if(clk'event AND clk = '1') then
case bcd is
segmented <= "0000001" when "0000", -- '0'
"1001111" when "0001", -- '1'
"0010010" when "0010", -- '2'
"0000110" when "0011", -- '3'
"1001100" when "0100", -- '4'
"0100100" when "0101", -- '5'
"0100000" when "0110", -- '6'
"0001111" when "0111", -- '7'
"0000000" when "1000", -- '8'
"0000100" when "1001", -- '9'
"0001000" when "1010", -- 'A'
"1100000" when "1011", -- 'B'
"0110001" when "1100", -- 'C'
"1000010" when "1101", -- 'D'
"0110000" when "1110", -- 'E'
"0111000" when "1111", -- 'F'
"1111111" when others;
end case;
end if;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity control is
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_reset: in std_logic;
I_busy: in boolean;
I_interrupt: in std_logic; -- from outside world
I_opcode: in std_logic_vector(4 downto 0);
I_funct3: in std_logic_vector(2 downto 0);
I_funct7: in std_logic_vector(6 downto 0);
I_lt: in boolean := false;
I_ltu: in boolean := false;
I_eq: in boolean := false;
-- enable signals for components
O_aluen: out std_logic;
O_busen: out std_logic;
O_decen: out std_logic;
O_pcuen: out std_logic;
O_regen: out std_logic;
-- op selection for devices
O_aluop: out aluops_t;
O_busop: out busops_t;
O_pcuop: out pcuops_t;
O_regop: out regops_t;
-- muxer selection signals
O_mux_alu_dat1_sel: out integer range 0 to MUX_ALU_DAT1_PORTS-1;
O_mux_alu_dat2_sel: out integer range 0 to MUX_ALU_DAT2_PORTS-1;
O_mux_bus_addr_sel: out integer range 0 to MUX_BUS_ADDR_PORTS-1;
O_mux_reg_data_sel: out integer range 0 to MUX_REG_DATA_PORTS-1
);
end control;
architecture Behavioral of control is
type states_t is (RESET, FETCH, DECODE, REGREAD, CUSTOM0, JAL, JAL2, JALR, JALR2, LUI, AUIPC, OP, OPIMM, STORE, STORE2, LOAD, LOAD2, BRANCH, BRANCH2, TRAP, TRAP2, REGWRITEBUS, REGWRITEALU, PCNEXT, PCREGIMM, PCIMM, PCUPDATE_FETCH);
begin
process(I_clk, I_en, I_reset, I_busy, I_interrupt, I_opcode, I_funct3, I_funct7, I_lt, I_ltu, I_eq)
variable nextstate,state: states_t := RESET;
variable interrupt_enabled, in_interrupt, in_trap: boolean := false;
begin
-- run on falling edge to ensure that all control signals arrive in time
-- for the controlled units, which run on the rising edge
if falling_edge(I_clk) and I_en = '1' then
O_aluen <= '0';
O_busen <= '0';
O_decen <= '0';
O_pcuen <= '0';
O_regen <= '0';
O_aluop <= ALU_ADD;
O_busop <= BUS_READB;
O_pcuop <= PCU_SETPC;
O_regop <= REGOP_READ;
O_mux_alu_dat1_sel <= MUX_ALU_DAT1_PORT_S1;
O_mux_alu_dat2_sel <= MUX_ALU_DAT2_PORT_S2;
O_mux_bus_addr_sel <= MUX_BUS_ADDR_PORT_ALU; -- address by default from ALU
O_mux_reg_data_sel <= MUX_REG_DATA_PORT_ALU; -- data by default from ALU
-- only forward state machine if every component is finished
if not I_busy then
state := nextstate;
end if;
case state is
when RESET =>
nextstate := FETCH;
when FETCH =>
-- fetch next instruction, use the address the program counter unit (PCU) emits
O_busen <= '1';
O_busop <= BUS_READW;
O_mux_bus_addr_sel <= MUX_BUS_ADDR_PORT_PC;
nextstate := DECODE;
when DECODE =>
-- why check for interrupt here? It turns out that changing PC during bus cycles is a *bad*
-- idea. In this state we're sure no bus cycles are in progress.
if I_interrupt = '1' and interrupt_enabled and not in_interrupt and not in_trap then
O_pcuen <= '1';
O_pcuop <= PCU_ENTERINT;
in_interrupt := true;
nextstate := FETCH;
else
O_decen <= '1';
nextstate := REGREAD;
end if;
when REGREAD =>
O_regen <= '1';
O_regop <= REGOP_READ;
case I_opcode is
when OP_OP => nextstate := OP;
when OP_OPIMM => nextstate := OPIMM;
when OP_LOAD => nextstate := LOAD;
when OP_STORE => nextstate := STORE;
when OP_JAL => nextstate := JAL;
when OP_JALR => nextstate := JALR;
when OP_BRANCH => nextstate := BRANCH;
when OP_LUI => nextstate := LUI;
when OP_AUIPC => nextstate := AUIPC;
when OP_CUSTOM0 => nextstate := CUSTOM0;
when OP_MISCMEM => nextstate := PCNEXT; -- NOP, fetch next instruction
when others => nextstate := TRAP; -- trap OP_SYSTEM or unknown opcodes
end case;
when OP =>
O_aluen <= '1';
O_mux_alu_dat1_sel <= MUX_ALU_DAT1_PORT_S1;
O_mux_alu_dat2_sel <= MUX_ALU_DAT2_PORT_S2;
case I_funct3 is
when FUNC_ADD_SUB =>
if I_funct7(5) = '0' then
O_aluop <= ALU_ADD;
else
O_aluop <= ALU_SUB;
end if;
when FUNC_SLL => O_aluop <= ALU_SLL;
when FUNC_SLT => O_aluop <= ALU_SLT;
when FUNC_SLTU => O_aluop <= ALU_SLTU;
when FUNC_XOR => O_aluop <= ALU_XOR;
when FUNC_SRL_SRA =>
if I_funct7(5) = '0' then
O_aluop <= ALU_SRL;
else
O_aluop <= ALU_SRA;
end if;
when FUNC_OR => O_aluop <= ALU_OR;
when FUNC_AND => O_aluop <= ALU_AND;
when others => null;
end case;
nextstate := REGWRITEALU;
when OPIMM =>
O_aluen <= '1';
O_mux_alu_dat1_sel <= MUX_ALU_DAT1_PORT_S1;
O_mux_alu_dat2_sel <= MUX_ALU_DAT2_PORT_IMM;
case I_funct3 is
when FUNC_ADDI => O_aluop <= ALU_ADD;
when FUNC_SLLI => O_aluop <= ALU_SLL;
when FUNC_SLTI => O_aluop <= ALU_SLT;
when FUNC_SLTIU => O_aluop <= ALU_SLTU;
when FUNC_XORI => O_aluop <= ALU_XOR;
when FUNC_SRLI_SRAI =>
if I_funct7(5) = '0' then
O_aluop <= ALU_SRL;
else
O_aluop <= ALU_SRA;
end if;
when FUNC_ORI => O_aluop <= ALU_OR;
when FUNC_ANDI => O_aluop <= ALU_AND;
when others => null;
end case;
nextstate := REGWRITEALU;
when LOAD =>
-- compute load address on ALU
O_aluen <= '1';
O_aluop <= ALU_ADD;
O_mux_alu_dat1_sel <= MUX_ALU_DAT1_PORT_S1;
O_mux_alu_dat2_sel <= MUX_ALU_DAT2_PORT_IMM;
nextstate := LOAD2;
when LOAD2 =>
O_busen <= '1';
O_mux_bus_addr_sel <= MUX_BUS_ADDR_PORT_ALU;
case I_funct3 is
when FUNC_LB => O_busop <= BUS_READB;
when FUNC_LH => O_busop <= BUS_READH;
when FUNC_LW => O_busop <= BUS_READW;
when FUNC_LBU => O_busop <= BUS_READBU;
when FUNC_LHU => O_busop <= BUS_READHU;
when others => null;
end case;
nextstate := REGWRITEBUS;
when STORE =>
-- compute store address on ALU
O_aluen <= '1';
O_aluop <= ALU_ADD;
O_mux_alu_dat1_sel <= MUX_ALU_DAT1_PORT_S1;
O_mux_alu_dat2_sel <= MUX_ALU_DAT2_PORT_IMM;
nextstate := STORE2;
when STORE2 =>
O_busen <= '1';
O_mux_bus_addr_sel <= MUX_BUS_ADDR_PORT_ALU;
case I_funct3 is
when FUNC_SB => O_busop <= BUS_WRITEB;
when FUNC_SH => O_busop <= BUS_WRITEH;
when FUNC_SW => O_busop <= BUS_WRITEW;
when others => null;
end case;
nextstate := PCNEXT;
when JAL =>
-- compute return address on ALU
O_aluen <= '1';
O_aluop <= ALU_ADD;
O_mux_alu_dat1_sel <= MUX_ALU_DAT1_PORT_PC;
O_mux_alu_dat2_sel <= MUX_ALU_DAT2_PORT_INSTLEN;
nextstate := JAL2;
when JAL2 =>
-- write computed return address to register file
O_regen <= '1';
O_regop <= REGOP_WRITE;
O_mux_reg_data_sel <= MUX_REG_DATA_PORT_ALU;
nextstate := PCIMM;
when JALR =>
-- compute return address on ALU
O_aluen <= '1';
O_aluop <= ALU_ADD;
O_mux_alu_dat1_sel <= MUX_ALU_DAT1_PORT_PC;
O_mux_alu_dat2_sel <= MUX_ALU_DAT2_PORT_INSTLEN;
nextstate := JALR2;
when JALR2 =>
-- write computed return address to register file
O_regen <= '1';
O_regop <= REGOP_WRITE;
O_mux_reg_data_sel <= MUX_REG_DATA_PORT_ALU;
nextstate := PCREGIMM;
when BRANCH =>
-- use ALU to compute flags
O_aluen <= '1';
O_aluop <= ALU_ADD; -- doesn't really matter for flag computation
O_mux_alu_dat1_sel <= MUX_ALU_DAT1_PORT_S1;
O_mux_alu_dat2_sel <= MUX_ALU_DAT2_PORT_S2;
nextstate := BRANCH2;
when BRANCH2 =>
-- make branch decision by looking at flags
nextstate := PCNEXT; -- by default, don't branch
case I_funct3 is
when FUNC_BEQ =>
if I_eq then
nextstate := PCIMM;
end if;
when FUNC_BNE =>
if not I_eq then
nextstate := PCIMM;
end if;
when FUNC_BLT =>
if I_lt then
nextstate := PCIMM;
end if;
when FUNC_BGE =>
if not I_lt then
nextstate := PCIMM;
end if;
when FUNC_BLTU =>
if I_ltu then
nextstate := PCIMM;
end if;
when FUNC_BGEU =>
if not I_ltu then
nextstate := PCIMM;
end if;
when others => null;
end case;
when LUI =>
O_regen <= '1';
O_regop <= REGOP_WRITE;
O_mux_reg_data_sel <= MUX_REG_DATA_PORT_IMM;
nextstate := PCNEXT;
when AUIPC =>
-- compute PC + IMM on ALU
O_aluen <= '1';
O_aluop <= ALU_ADD;
O_mux_alu_dat1_sel <= MUX_ALU_DAT1_PORT_PC;
O_mux_alu_dat2_sel <= MUX_ALU_DAT2_PORT_IMM;
nextstate := REGWRITEALU;
when CUSTOM0 =>
case I_funct7 is
when "0000000" => -- return from interrupt
O_pcuen <= '1';
O_pcuop <= PCU_RETINT;
in_interrupt := false;
nextstate := FETCH;
when "0000001" => -- enable interrupts
interrupt_enabled := true;
nextstate := PCNEXT;
when "0000010" => -- disable interrupts
interrupt_enabled := false;
nextstate := PCNEXT;
when "0001000" => -- return from trap
O_pcuen <= '1';
O_pcuop <= PCU_RETTRAP;
in_trap := false;
nextstate := FETCH;
when "0001001" => -- get trap return address
O_regen <= '1';
O_regop <= REGOP_WRITE;
O_mux_reg_data_sel <= MUX_REG_DATA_PORT_TRAPRET;
nextstate := PCNEXT;
when others => null;
end case;
when TRAP =>
-- compute trap return address
O_aluen <= '1';
O_aluop <= ALU_ADD;
O_mux_alu_dat1_sel <= MUX_ALU_DAT1_PORT_PC;
O_mux_alu_dat2_sel <= MUX_ALU_DAT2_PORT_INSTLEN;
in_trap := true;
nextstate := TRAP2;
when TRAP2 =>
-- save trap return address and emit trap vector
O_pcuen <= '1';
O_pcuop <= PCU_ENTERTRAP;
nextstate := FETCH;
when REGWRITEBUS =>
O_regen <= '1';
O_regop <= REGOP_WRITE;
O_mux_reg_data_sel <= MUX_REG_DATA_PORT_BUS;
nextstate := PCNEXT;
when REGWRITEALU =>
O_regen <= '1';
O_regop <= REGOP_WRITE;
O_mux_reg_data_sel <= MUX_REG_DATA_PORT_ALU;
nextstate := PCNEXT;
when PCNEXT =>
-- compute new value for PC: PC + INST_LEN
O_aluen <= '1';
O_aluop <= ALU_ADD;
O_mux_alu_dat1_sel <= MUX_ALU_DAT1_PORT_PC;
O_mux_alu_dat2_sel <= MUX_ALU_DAT2_PORT_INSTLEN;
nextstate := PCUPDATE_FETCH;
when PCREGIMM =>
-- compute new value for PC: S1 + IMM;
O_aluen <= '1';
O_aluop <= ALU_ADD;
O_mux_alu_dat1_sel <= MUX_ALU_DAT1_PORT_S1;
O_mux_alu_dat2_sel <= MUX_ALU_DAT2_PORT_IMM;
nextstate := PCUPDATE_FETCH;
when PCIMM =>
-- compute new value for PC: PC + IMM;
O_aluen <= '1';
O_aluop <= ALU_ADD;
O_mux_alu_dat1_sel <= MUX_ALU_DAT1_PORT_PC;
O_mux_alu_dat2_sel <= MUX_ALU_DAT2_PORT_IMM;
nextstate := PCUPDATE_FETCH;
when PCUPDATE_FETCH =>
-- load new PC value into program counter unit
O_pcuen <= '1';
O_pcuop <= PCU_SETPC;
-- given that right now the ALU outputs the address for the next
-- instruction, we can also start instruction fetch
O_busen <= '1';
O_busop <= BUS_READW;
O_mux_bus_addr_sel <= MUX_BUS_ADDR_PORT_ALU;
nextstate := DECODE;
end case;
if I_reset = '1' then
state := RESET;
nextstate := RESET;
interrupt_enabled := false;
in_interrupt := false;
in_trap := false;
end if;
end if;
end process;
end Behavioral; |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: bv_images_body.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
--------------------------------------------------------------------------
--
-- bv_images package body.
--
-- Functions that return the string image of values.
-- Each image is a correctly formed literal according to the
-- rules of VHDL-93.
--
--------------------------------------------------------------------------
package body bv_images is
-- Image of bit vector as binary bit string literal
-- (in the format B"...")
-- Length of result is bv'length + 3
function image (bv : in bit_vector) return string is
alias bv_norm : bit_vector(1 to bv'length) is bv;
variable result : string(1 to bv'length + 3);
begin
result(1) := 'B';
result(2) := '"';
for index in bv_norm'range loop
if bv_norm(index) = '0' then
result(index + 2) := '0';
else
result(index + 2) := '1';
end if;
end loop;
result(bv'length + 3) := '"';
return result;
end image;
----------------------------------------------------------------
-- Image of bit vector as octal bit string literal
-- (in the format O"...")
-- Length of result is (bv'length+2)/3 + 3
function image_octal (bv : in bit_vector) return string is
constant nr_digits : natural := (bv'length + 2) / 3;
variable result : string(1 to nr_digits + 3);
variable bits : bit_vector(0 to 3*nr_digits - 1) := (others => '0');
variable three_bits : bit_vector(0 to 2);
variable digit : character;
begin
result(1) := 'O';
result(2) := '"';
bits(bits'right - bv'length + 1 to bits'right) := bv;
for index in 0 to nr_digits - 1 loop
three_bits := bits(3*index to 3*index + 2);
case three_bits is
when b"000" =>
digit := '0';
when b"001" =>
digit := '1';
when b"010" =>
digit := '2';
when b"011" =>
digit := '3';
when b"100" =>
digit := '4';
when b"101" =>
digit := '5';
when b"110" =>
digit := '6';
when b"111" =>
digit := '7';
end case;
result(index + 3) := digit;
end loop;
result(nr_digits + 3) := '"';
return result;
end image_octal;
----------------------------------------------------------------
-- Image of bit vector as hex bit string literal
-- (in the format X"...")
-- Length of result is (bv'length+3)/4 + 3
function image_hex (bv : in bit_vector) return string is
constant nr_digits : natural := (bv'length + 3) / 4;
variable result : string(1 to nr_digits + 3);
variable bits : bit_vector(0 to 4*nr_digits - 1) := (others => '0');
variable four_bits : bit_vector(0 to 3);
variable digit : character;
begin
result(1) := 'X';
result(2) := '"';
bits(bits'right - bv'length + 1 to bits'right) := bv;
for index in 0 to nr_digits - 1 loop
four_bits := bits(4*index to 4*index + 3);
case four_bits is
when b"0000" =>
digit := '0';
when b"0001" =>
digit := '1';
when b"0010" =>
digit := '2';
when b"0011" =>
digit := '3';
when b"0100" =>
digit := '4';
when b"0101" =>
digit := '5';
when b"0110" =>
digit := '6';
when b"0111" =>
digit := '7';
when b"1000" =>
digit := '8';
when b"1001" =>
digit := '9';
when b"1010" =>
digit := 'A';
when b"1011" =>
digit := 'B';
when b"1100" =>
digit := 'C';
when b"1101" =>
digit := 'D';
when b"1110" =>
digit := 'E';
when b"1111" =>
digit := 'F';
end case;
result(index + 3) := digit;
end loop;
result(nr_digits + 3) := '"';
return result;
end image_hex;
end bv_images;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: bv_images_body.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
--------------------------------------------------------------------------
--
-- bv_images package body.
--
-- Functions that return the string image of values.
-- Each image is a correctly formed literal according to the
-- rules of VHDL-93.
--
--------------------------------------------------------------------------
package body bv_images is
-- Image of bit vector as binary bit string literal
-- (in the format B"...")
-- Length of result is bv'length + 3
function image (bv : in bit_vector) return string is
alias bv_norm : bit_vector(1 to bv'length) is bv;
variable result : string(1 to bv'length + 3);
begin
result(1) := 'B';
result(2) := '"';
for index in bv_norm'range loop
if bv_norm(index) = '0' then
result(index + 2) := '0';
else
result(index + 2) := '1';
end if;
end loop;
result(bv'length + 3) := '"';
return result;
end image;
----------------------------------------------------------------
-- Image of bit vector as octal bit string literal
-- (in the format O"...")
-- Length of result is (bv'length+2)/3 + 3
function image_octal (bv : in bit_vector) return string is
constant nr_digits : natural := (bv'length + 2) / 3;
variable result : string(1 to nr_digits + 3);
variable bits : bit_vector(0 to 3*nr_digits - 1) := (others => '0');
variable three_bits : bit_vector(0 to 2);
variable digit : character;
begin
result(1) := 'O';
result(2) := '"';
bits(bits'right - bv'length + 1 to bits'right) := bv;
for index in 0 to nr_digits - 1 loop
three_bits := bits(3*index to 3*index + 2);
case three_bits is
when b"000" =>
digit := '0';
when b"001" =>
digit := '1';
when b"010" =>
digit := '2';
when b"011" =>
digit := '3';
when b"100" =>
digit := '4';
when b"101" =>
digit := '5';
when b"110" =>
digit := '6';
when b"111" =>
digit := '7';
end case;
result(index + 3) := digit;
end loop;
result(nr_digits + 3) := '"';
return result;
end image_octal;
----------------------------------------------------------------
-- Image of bit vector as hex bit string literal
-- (in the format X"...")
-- Length of result is (bv'length+3)/4 + 3
function image_hex (bv : in bit_vector) return string is
constant nr_digits : natural := (bv'length + 3) / 4;
variable result : string(1 to nr_digits + 3);
variable bits : bit_vector(0 to 4*nr_digits - 1) := (others => '0');
variable four_bits : bit_vector(0 to 3);
variable digit : character;
begin
result(1) := 'X';
result(2) := '"';
bits(bits'right - bv'length + 1 to bits'right) := bv;
for index in 0 to nr_digits - 1 loop
four_bits := bits(4*index to 4*index + 3);
case four_bits is
when b"0000" =>
digit := '0';
when b"0001" =>
digit := '1';
when b"0010" =>
digit := '2';
when b"0011" =>
digit := '3';
when b"0100" =>
digit := '4';
when b"0101" =>
digit := '5';
when b"0110" =>
digit := '6';
when b"0111" =>
digit := '7';
when b"1000" =>
digit := '8';
when b"1001" =>
digit := '9';
when b"1010" =>
digit := 'A';
when b"1011" =>
digit := 'B';
when b"1100" =>
digit := 'C';
when b"1101" =>
digit := 'D';
when b"1110" =>
digit := 'E';
when b"1111" =>
digit := 'F';
end case;
result(index + 3) := digit;
end loop;
result(nr_digits + 3) := '"';
return result;
end image_hex;
end bv_images;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: bv_images_body.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
--------------------------------------------------------------------------
--
-- bv_images package body.
--
-- Functions that return the string image of values.
-- Each image is a correctly formed literal according to the
-- rules of VHDL-93.
--
--------------------------------------------------------------------------
package body bv_images is
-- Image of bit vector as binary bit string literal
-- (in the format B"...")
-- Length of result is bv'length + 3
function image (bv : in bit_vector) return string is
alias bv_norm : bit_vector(1 to bv'length) is bv;
variable result : string(1 to bv'length + 3);
begin
result(1) := 'B';
result(2) := '"';
for index in bv_norm'range loop
if bv_norm(index) = '0' then
result(index + 2) := '0';
else
result(index + 2) := '1';
end if;
end loop;
result(bv'length + 3) := '"';
return result;
end image;
----------------------------------------------------------------
-- Image of bit vector as octal bit string literal
-- (in the format O"...")
-- Length of result is (bv'length+2)/3 + 3
function image_octal (bv : in bit_vector) return string is
constant nr_digits : natural := (bv'length + 2) / 3;
variable result : string(1 to nr_digits + 3);
variable bits : bit_vector(0 to 3*nr_digits - 1) := (others => '0');
variable three_bits : bit_vector(0 to 2);
variable digit : character;
begin
result(1) := 'O';
result(2) := '"';
bits(bits'right - bv'length + 1 to bits'right) := bv;
for index in 0 to nr_digits - 1 loop
three_bits := bits(3*index to 3*index + 2);
case three_bits is
when b"000" =>
digit := '0';
when b"001" =>
digit := '1';
when b"010" =>
digit := '2';
when b"011" =>
digit := '3';
when b"100" =>
digit := '4';
when b"101" =>
digit := '5';
when b"110" =>
digit := '6';
when b"111" =>
digit := '7';
end case;
result(index + 3) := digit;
end loop;
result(nr_digits + 3) := '"';
return result;
end image_octal;
----------------------------------------------------------------
-- Image of bit vector as hex bit string literal
-- (in the format X"...")
-- Length of result is (bv'length+3)/4 + 3
function image_hex (bv : in bit_vector) return string is
constant nr_digits : natural := (bv'length + 3) / 4;
variable result : string(1 to nr_digits + 3);
variable bits : bit_vector(0 to 4*nr_digits - 1) := (others => '0');
variable four_bits : bit_vector(0 to 3);
variable digit : character;
begin
result(1) := 'X';
result(2) := '"';
bits(bits'right - bv'length + 1 to bits'right) := bv;
for index in 0 to nr_digits - 1 loop
four_bits := bits(4*index to 4*index + 3);
case four_bits is
when b"0000" =>
digit := '0';
when b"0001" =>
digit := '1';
when b"0010" =>
digit := '2';
when b"0011" =>
digit := '3';
when b"0100" =>
digit := '4';
when b"0101" =>
digit := '5';
when b"0110" =>
digit := '6';
when b"0111" =>
digit := '7';
when b"1000" =>
digit := '8';
when b"1001" =>
digit := '9';
when b"1010" =>
digit := 'A';
when b"1011" =>
digit := 'B';
when b"1100" =>
digit := 'C';
when b"1101" =>
digit := 'D';
when b"1110" =>
digit := 'E';
when b"1111" =>
digit := 'F';
end case;
result(index + 3) := digit;
end loop;
result(nr_digits + 3) := '"';
return result;
end image_hex;
end bv_images;
|
-------------------------------------------------------------------------------
-- system_sram_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_mch_emc_v3_01_a;
use xps_mch_emc_v3_01_a.all;
entity system_sram_wrapper is
port (
MCH_SPLB_Clk : in std_logic;
RdClk : in std_logic;
MCH_SPLB_Rst : in std_logic;
MCH0_Access_Control : in std_logic;
MCH0_Access_Data : in std_logic_vector(0 to 31);
MCH0_Access_Write : in std_logic;
MCH0_Access_Full : out std_logic;
MCH0_ReadData_Control : out std_logic;
MCH0_ReadData_Data : out std_logic_vector(0 to 31);
MCH0_ReadData_Read : in std_logic;
MCH0_ReadData_Exists : out std_logic;
MCH1_Access_Control : in std_logic;
MCH1_Access_Data : in std_logic_vector(0 to 31);
MCH1_Access_Write : in std_logic;
MCH1_Access_Full : out std_logic;
MCH1_ReadData_Control : out std_logic;
MCH1_ReadData_Data : out std_logic_vector(0 to 31);
MCH1_ReadData_Read : in std_logic;
MCH1_ReadData_Exists : out std_logic;
MCH2_Access_Control : in std_logic;
MCH2_Access_Data : in std_logic_vector(0 to 31);
MCH2_Access_Write : in std_logic;
MCH2_Access_Full : out std_logic;
MCH2_ReadData_Control : out std_logic;
MCH2_ReadData_Data : out std_logic_vector(0 to 31);
MCH2_ReadData_Read : in std_logic;
MCH2_ReadData_Exists : out std_logic;
MCH3_Access_Control : in std_logic;
MCH3_Access_Data : in std_logic_vector(0 to 31);
MCH3_Access_Write : in std_logic;
MCH3_Access_Full : out std_logic;
MCH3_ReadData_Control : out std_logic;
MCH3_ReadData_Data : out std_logic_vector(0 to 31);
MCH3_ReadData_Read : in std_logic;
MCH3_ReadData_Exists : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
Mem_DQ_I : in std_logic_vector(0 to 31);
Mem_DQ_O : out std_logic_vector(0 to 31);
Mem_DQ_T : out std_logic_vector(0 to 31);
Mem_A : out std_logic_vector(0 to 31);
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to 0);
Mem_OEN : out std_logic_vector(0 to 0);
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to 3);
Mem_BEN : out std_logic_vector(0 to 3);
Mem_CE : out std_logic_vector(0 to 0);
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_sram_wrapper : entity is "xps_mch_emc_v3_01_a";
end system_sram_wrapper;
architecture STRUCTURE of system_sram_wrapper is
component xps_mch_emc is
generic (
C_FAMILY : STRING;
C_NUM_BANKS_MEM : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_PRIORITY_MODE : INTEGER;
C_INCLUDE_PLB_IPIF : INTEGER;
C_INCLUDE_WRBUF : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_MCH_SPLB_AWIDTH : INTEGER;
C_SPLB_SMALLEST_MASTER : INTEGER;
C_MCH_NATIVE_DWIDTH : INTEGER;
C_MCH_SPLB_CLK_PERIOD_PS : INTEGER;
C_MEM0_BASEADDR : std_logic_vector;
C_MEM0_HIGHADDR : std_logic_vector;
C_MEM1_BASEADDR : std_logic_vector;
C_MEM1_HIGHADDR : std_logic_vector;
C_MEM2_BASEADDR : std_logic_vector;
C_MEM2_HIGHADDR : std_logic_vector;
C_MEM3_BASEADDR : std_logic_vector;
C_MEM3_HIGHADDR : std_logic_vector;
C_PAGEMODE_FLASH_0 : INTEGER;
C_PAGEMODE_FLASH_1 : INTEGER;
C_PAGEMODE_FLASH_2 : INTEGER;
C_PAGEMODE_FLASH_3 : INTEGER;
C_INCLUDE_NEGEDGE_IOREGS : INTEGER;
C_MEM0_WIDTH : INTEGER;
C_MEM1_WIDTH : INTEGER;
C_MEM2_WIDTH : INTEGER;
C_MEM3_WIDTH : INTEGER;
C_MAX_MEM_WIDTH : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_0 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_1 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_2 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_3 : INTEGER;
C_SYNCH_MEM_0 : INTEGER;
C_SYNCH_PIPEDELAY_0 : INTEGER;
C_TCEDV_PS_MEM_0 : INTEGER;
C_TAVDV_PS_MEM_0 : INTEGER;
C_TPACC_PS_FLASH_0 : INTEGER;
C_THZCE_PS_MEM_0 : INTEGER;
C_THZOE_PS_MEM_0 : INTEGER;
C_TWC_PS_MEM_0 : INTEGER;
C_TWP_PS_MEM_0 : INTEGER;
C_TLZWE_PS_MEM_0 : INTEGER;
C_SYNCH_MEM_1 : INTEGER;
C_SYNCH_PIPEDELAY_1 : INTEGER;
C_TCEDV_PS_MEM_1 : INTEGER;
C_TAVDV_PS_MEM_1 : INTEGER;
C_TPACC_PS_FLASH_1 : INTEGER;
C_THZCE_PS_MEM_1 : INTEGER;
C_THZOE_PS_MEM_1 : INTEGER;
C_TWC_PS_MEM_1 : INTEGER;
C_TWP_PS_MEM_1 : INTEGER;
C_TLZWE_PS_MEM_1 : INTEGER;
C_SYNCH_MEM_2 : INTEGER;
C_SYNCH_PIPEDELAY_2 : INTEGER;
C_TCEDV_PS_MEM_2 : INTEGER;
C_TAVDV_PS_MEM_2 : INTEGER;
C_TPACC_PS_FLASH_2 : INTEGER;
C_THZCE_PS_MEM_2 : INTEGER;
C_THZOE_PS_MEM_2 : INTEGER;
C_TWC_PS_MEM_2 : INTEGER;
C_TWP_PS_MEM_2 : INTEGER;
C_TLZWE_PS_MEM_2 : INTEGER;
C_SYNCH_MEM_3 : INTEGER;
C_SYNCH_PIPEDELAY_3 : INTEGER;
C_TCEDV_PS_MEM_3 : INTEGER;
C_TAVDV_PS_MEM_3 : INTEGER;
C_TPACC_PS_FLASH_3 : INTEGER;
C_THZCE_PS_MEM_3 : INTEGER;
C_THZOE_PS_MEM_3 : INTEGER;
C_TWC_PS_MEM_3 : INTEGER;
C_TWP_PS_MEM_3 : INTEGER;
C_TLZWE_PS_MEM_3 : INTEGER;
C_MCH0_PROTOCOL : INTEGER;
C_MCH0_ACCESSBUF_DEPTH : INTEGER;
C_MCH0_RDDATABUF_DEPTH : INTEGER;
C_MCH1_PROTOCOL : INTEGER;
C_MCH1_ACCESSBUF_DEPTH : INTEGER;
C_MCH1_RDDATABUF_DEPTH : INTEGER;
C_MCH2_PROTOCOL : INTEGER;
C_MCH2_ACCESSBUF_DEPTH : INTEGER;
C_MCH2_RDDATABUF_DEPTH : INTEGER;
C_MCH3_PROTOCOL : INTEGER;
C_MCH3_ACCESSBUF_DEPTH : INTEGER;
C_MCH3_RDDATABUF_DEPTH : INTEGER;
C_XCL0_LINESIZE : INTEGER;
C_XCL0_WRITEXFER : INTEGER;
C_XCL1_LINESIZE : INTEGER;
C_XCL1_WRITEXFER : INTEGER;
C_XCL2_LINESIZE : INTEGER;
C_XCL2_WRITEXFER : INTEGER;
C_XCL3_LINESIZE : INTEGER;
C_XCL3_WRITEXFER : INTEGER
);
port (
MCH_SPLB_Clk : in std_logic;
RdClk : in std_logic;
MCH_SPLB_Rst : in std_logic;
MCH0_Access_Control : in std_logic;
MCH0_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH0_Access_Write : in std_logic;
MCH0_Access_Full : out std_logic;
MCH0_ReadData_Control : out std_logic;
MCH0_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH0_ReadData_Read : in std_logic;
MCH0_ReadData_Exists : out std_logic;
MCH1_Access_Control : in std_logic;
MCH1_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH1_Access_Write : in std_logic;
MCH1_Access_Full : out std_logic;
MCH1_ReadData_Control : out std_logic;
MCH1_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH1_ReadData_Read : in std_logic;
MCH1_ReadData_Exists : out std_logic;
MCH2_Access_Control : in std_logic;
MCH2_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH2_Access_Write : in std_logic;
MCH2_Access_Full : out std_logic;
MCH2_ReadData_Control : out std_logic;
MCH2_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH2_ReadData_Read : in std_logic;
MCH2_ReadData_Exists : out std_logic;
MCH3_Access_Control : in std_logic;
MCH3_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH3_Access_Write : in std_logic;
MCH3_Access_Full : out std_logic;
MCH3_ReadData_Control : out std_logic;
MCH3_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1));
MCH3_ReadData_Read : in std_logic;
MCH3_ReadData_Exists : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Mem_DQ_I : in std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_DQ_O : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_DQ_T : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
Mem_A : out std_logic_vector(0 to (C_MCH_SPLB_AWIDTH-1));
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_OEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1));
Mem_BEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1));
Mem_CE : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic
);
end component;
begin
SRAM : xps_mch_emc
generic map (
C_FAMILY => "virtex5",
C_NUM_BANKS_MEM => 1,
C_NUM_CHANNELS => 0,
C_PRIORITY_MODE => 0,
C_INCLUDE_PLB_IPIF => 1,
C_INCLUDE_WRBUF => 1,
C_SPLB_MID_WIDTH => 3,
C_SPLB_NUM_MASTERS => 6,
C_SPLB_P2P => 0,
C_SPLB_DWIDTH => 64,
C_MCH_SPLB_AWIDTH => 32,
C_SPLB_SMALLEST_MASTER => 32,
C_MCH_NATIVE_DWIDTH => 32,
C_MCH_SPLB_CLK_PERIOD_PS => 8000,
C_MEM0_BASEADDR => X"9af00000",
C_MEM0_HIGHADDR => X"9affffff",
C_MEM1_BASEADDR => X"ffffffff",
C_MEM1_HIGHADDR => X"00000000",
C_MEM2_BASEADDR => X"ffffffff",
C_MEM2_HIGHADDR => X"00000000",
C_MEM3_BASEADDR => X"ffffffff",
C_MEM3_HIGHADDR => X"00000000",
C_PAGEMODE_FLASH_0 => 0,
C_PAGEMODE_FLASH_1 => 0,
C_PAGEMODE_FLASH_2 => 0,
C_PAGEMODE_FLASH_3 => 0,
C_INCLUDE_NEGEDGE_IOREGS => 0,
C_MEM0_WIDTH => 32,
C_MEM1_WIDTH => 32,
C_MEM2_WIDTH => 32,
C_MEM3_WIDTH => 32,
C_MAX_MEM_WIDTH => 32,
C_INCLUDE_DATAWIDTH_MATCHING_0 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_1 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_2 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_3 => 0,
C_SYNCH_MEM_0 => 1,
C_SYNCH_PIPEDELAY_0 => 2,
C_TCEDV_PS_MEM_0 => 0,
C_TAVDV_PS_MEM_0 => 0,
C_TPACC_PS_FLASH_0 => 25000,
C_THZCE_PS_MEM_0 => 0,
C_THZOE_PS_MEM_0 => 0,
C_TWC_PS_MEM_0 => 0,
C_TWP_PS_MEM_0 => 0,
C_TLZWE_PS_MEM_0 => 0,
C_SYNCH_MEM_1 => 0,
C_SYNCH_PIPEDELAY_1 => 2,
C_TCEDV_PS_MEM_1 => 15000,
C_TAVDV_PS_MEM_1 => 15000,
C_TPACC_PS_FLASH_1 => 25000,
C_THZCE_PS_MEM_1 => 7000,
C_THZOE_PS_MEM_1 => 7000,
C_TWC_PS_MEM_1 => 15000,
C_TWP_PS_MEM_1 => 12000,
C_TLZWE_PS_MEM_1 => 0,
C_SYNCH_MEM_2 => 0,
C_SYNCH_PIPEDELAY_2 => 2,
C_TCEDV_PS_MEM_2 => 15000,
C_TAVDV_PS_MEM_2 => 15000,
C_TPACC_PS_FLASH_2 => 25000,
C_THZCE_PS_MEM_2 => 7000,
C_THZOE_PS_MEM_2 => 7000,
C_TWC_PS_MEM_2 => 15000,
C_TWP_PS_MEM_2 => 12000,
C_TLZWE_PS_MEM_2 => 0,
C_SYNCH_MEM_3 => 0,
C_SYNCH_PIPEDELAY_3 => 2,
C_TCEDV_PS_MEM_3 => 15000,
C_TAVDV_PS_MEM_3 => 15000,
C_TPACC_PS_FLASH_3 => 25000,
C_THZCE_PS_MEM_3 => 7000,
C_THZOE_PS_MEM_3 => 7000,
C_TWC_PS_MEM_3 => 15000,
C_TWP_PS_MEM_3 => 12000,
C_TLZWE_PS_MEM_3 => 0,
C_MCH0_PROTOCOL => 0,
C_MCH0_ACCESSBUF_DEPTH => 16,
C_MCH0_RDDATABUF_DEPTH => 16,
C_MCH1_PROTOCOL => 0,
C_MCH1_ACCESSBUF_DEPTH => 16,
C_MCH1_RDDATABUF_DEPTH => 16,
C_MCH2_PROTOCOL => 0,
C_MCH2_ACCESSBUF_DEPTH => 16,
C_MCH2_RDDATABUF_DEPTH => 16,
C_MCH3_PROTOCOL => 0,
C_MCH3_ACCESSBUF_DEPTH => 16,
C_MCH3_RDDATABUF_DEPTH => 16,
C_XCL0_LINESIZE => 4,
C_XCL0_WRITEXFER => 1,
C_XCL1_LINESIZE => 4,
C_XCL1_WRITEXFER => 1,
C_XCL2_LINESIZE => 4,
C_XCL2_WRITEXFER => 1,
C_XCL3_LINESIZE => 4,
C_XCL3_WRITEXFER => 1
)
port map (
MCH_SPLB_Clk => MCH_SPLB_Clk,
RdClk => RdClk,
MCH_SPLB_Rst => MCH_SPLB_Rst,
MCH0_Access_Control => MCH0_Access_Control,
MCH0_Access_Data => MCH0_Access_Data,
MCH0_Access_Write => MCH0_Access_Write,
MCH0_Access_Full => MCH0_Access_Full,
MCH0_ReadData_Control => MCH0_ReadData_Control,
MCH0_ReadData_Data => MCH0_ReadData_Data,
MCH0_ReadData_Read => MCH0_ReadData_Read,
MCH0_ReadData_Exists => MCH0_ReadData_Exists,
MCH1_Access_Control => MCH1_Access_Control,
MCH1_Access_Data => MCH1_Access_Data,
MCH1_Access_Write => MCH1_Access_Write,
MCH1_Access_Full => MCH1_Access_Full,
MCH1_ReadData_Control => MCH1_ReadData_Control,
MCH1_ReadData_Data => MCH1_ReadData_Data,
MCH1_ReadData_Read => MCH1_ReadData_Read,
MCH1_ReadData_Exists => MCH1_ReadData_Exists,
MCH2_Access_Control => MCH2_Access_Control,
MCH2_Access_Data => MCH2_Access_Data,
MCH2_Access_Write => MCH2_Access_Write,
MCH2_Access_Full => MCH2_Access_Full,
MCH2_ReadData_Control => MCH2_ReadData_Control,
MCH2_ReadData_Data => MCH2_ReadData_Data,
MCH2_ReadData_Read => MCH2_ReadData_Read,
MCH2_ReadData_Exists => MCH2_ReadData_Exists,
MCH3_Access_Control => MCH3_Access_Control,
MCH3_Access_Data => MCH3_Access_Data,
MCH3_Access_Write => MCH3_Access_Write,
MCH3_Access_Full => MCH3_Access_Full,
MCH3_ReadData_Control => MCH3_ReadData_Control,
MCH3_ReadData_Data => MCH3_ReadData_Data,
MCH3_ReadData_Read => MCH3_ReadData_Read,
MCH3_ReadData_Exists => MCH3_ReadData_Exists,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Mem_DQ_I => Mem_DQ_I,
Mem_DQ_O => Mem_DQ_O,
Mem_DQ_T => Mem_DQ_T,
Mem_A => Mem_A,
Mem_RPN => Mem_RPN,
Mem_CEN => Mem_CEN,
Mem_OEN => Mem_OEN,
Mem_WEN => Mem_WEN,
Mem_QWEN => Mem_QWEN,
Mem_BEN => Mem_BEN,
Mem_CE => Mem_CE,
Mem_ADV_LDN => Mem_ADV_LDN,
Mem_LBON => Mem_LBON,
Mem_CKEN => Mem_CKEN,
Mem_RNW => Mem_RNW
);
end architecture STRUCTURE;
|
------------------------------------------------------------------------------
-- Copyright (c) 2019 by Paul Scherrer Institute, Switzerland
-- All rights reserved.
-- Authors: Oliver Bruendler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Libraries
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
use work.psi_tb_txt_util.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_math_pkg.all;
------------------------------------------------------------------------------
-- Package Header
------------------------------------------------------------------------------
package psi_tb_i2c_pkg is
-- -----------------------------------------------------------------------
-- Constants
-- -----------------------------------------------------------------------
constant I2c_ACK : std_logic := '0';
constant I2c_NACK : std_logic := '1';
type I2c_Transaction_t is (I2c_READ, I2c_WRITE);
-- -----------------------------------------------------------------------
-- Functions
-- -----------------------------------------------------------------------
function I2cGetAddr( Addr : in integer;
Trans : in I2c_Transaction_t) return integer;
-- -----------------------------------------------------------------------
-- Initialization
-- -----------------------------------------------------------------------
procedure I2cPullup(signal scl : inout std_logic;
signal sda : inout std_logic);
procedure I2cBusFree( signal scl : inout std_logic;
signal sda : inout std_logic);
procedure I2cSetFrequency( frequencyHz : in real);
-- -----------------------------------------------------------------------
-- Master Side Transactions
-- -----------------------------------------------------------------------
procedure I2cMasterSendStart( signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
Prefix : in string := "###ERROR###: ");
procedure I2cMasterSendRepeatedStart( signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
Prefix : in string := "###ERROR###: ");
procedure I2cMasterSendStop( signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
Prefix : in string := "###ERROR###: ");
procedure I2cMasterSendAddr( Address : in integer;
IsRead : in boolean;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
AddrBits : in integer := 7; -- 7 or 10
ExpectedAck : in std_logic := '0'; -- '0' for ack, '1' for nack, anything else for "don't check"
Prefix : in string := "###ERROR###: ");
procedure I2cMasterSendByte( Data : in integer range -128 to 255;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
ExpectedAck : in std_logic := '0'; -- '0' for ack, '1' for nack, anything else for "don't check"
Prefix : in string := "###ERROR###: ");
procedure I2cMasterExpectByte( ExpData : in integer range -128 to 255;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
AckOutput : in std_logic := '0'; -- '0' for ack, '1' for nack
Prefix : in string := "###ERROR###: ");
-- -----------------------------------------------------------------------
-- Slave Side Transactions
-- -----------------------------------------------------------------------
procedure I2cSlaveWaitStart( signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
Timeout : in time := 1 ms;
Prefix : in string := "###ERROR###: ");
procedure I2cSlaveWaitRepeatedStart( signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
Timeout : in time := 1 ms;
ClkStretch : in time := 0 ns; -- hold clock-low for at least this time
Prefix : in string := "###ERROR###: ");
procedure I2cSlaveWaitStop( signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
Timeout : in time := 1 ms;
ClkStretch : in time := 0 ns; -- hold clock-low for at least this time
Prefix : in string := "###ERROR###: ");
procedure I2cSlaveExpectAddr( Address : in integer;
IsRead : in boolean;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
AddrBits : in integer := 7; -- 7 or 10
AckOutput : in std_logic := '0'; -- '0' for ack, '1' for nack
Timeout : in time := 1 ms;
ClkStretch : in time := 0 ns; -- hold clock-low for at least this time
Prefix : in string := "###ERROR###: ");
procedure I2cSlaveExpectByte( ExpData : in integer range -128 to 255;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
AckOutput : in std_logic := '0'; -- '0' for ack, '1' for nack
Timeout : in time := 1 ms;
ClkStretch : in time := 0 ns; -- hold clock-low for at least this time
Prefix : in string := "###ERROR###: ");
procedure I2cSlaveSendByte( Data : in integer range -128 to 255;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
ExpectedAck : in std_logic := '0'; -- '0' for ack, '1' for nack, anything else for "don't check"
Timeout : in time := 1 ms;
ClkStretch : in time := 0 ns; -- hold clock-low for at least this time
Prefix : in string := "###ERROR###: ");
end psi_tb_i2c_pkg;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body psi_tb_i2c_pkg is
-- -----------------------------------------------------------------------
-- Local Types
-- -----------------------------------------------------------------------
type MsgInfo_r is record
Prefix : string;
Func : string;
User : string;
end record;
-- -----------------------------------------------------------------------
-- Local Variables
-- -----------------------------------------------------------------------
shared variable FreqClk_v : real := 100.0e3;
-- -----------------------------------------------------------------------
-- Private Procedures
-- -----------------------------------------------------------------------
-- *** Message Handling ***
function GenMessage( Prefix : in string;
Func : in string;
General : in string;
User : in string)
return string is
begin
return Prefix & "- " & Func & " - " & General & " - " & User;
end function;
function GenMessageNoPrefix( Func : in string;
General : in string;
User : in string)
return string is
begin
return Func & " - " & General & " - " & User;
end function;
-- *** Level Check ***
procedure LevelCheck( Expected : in std_logic;
signal Sig : in std_logic;
Msg : in MsgInfo_r;
GeneralMsg : in string) is
begin
-- Do not check for other inputs than 1 or 0
if (Expected = '0') or (Expected = '1') then
assert ((Expected = '0') and (Sig = '0')) or ((Expected = '1') and ((Sig = '1') or (Sig = 'H')))
report GenMessage(Msg.Prefix, Msg.Func, GeneralMsg, Msg.User)
severity error;
end if;
end procedure;
procedure LevelWait( Expected : in std_logic;
signal Sig : in std_logic;
Timeout : in time;
Msg : in MsgInfo_r;
GeneralMsg : in string) is
variable Correct_v : boolean;
begin
if Sig /= Expected then
if Expected = '0' then
wait until Sig = '0' for Timeout;
Correct_v := (Sig = '0');
else
wait until (Sig = '1') or (Sig = 'H') for Timeout;
Correct_v := ((Sig = '1') or (Sig = 'H'));
end if;
assert Correct_v
report GenMessage(Msg.Prefix, Msg.Func, GeneralMsg, Msg.User)
severity error;
end if;
end procedure;
-- *** Time Calculations ***
impure function ClkPeriod return time is
begin
return (1 sec) / FreqClk_v;
end function;
impure function ClkHalfPeriod return time is
begin
return (0.5 sec) / FreqClk_v;
end function;
impure function ClkQuartPeriod return time is
begin
return (0.25 sec) / FreqClk_v;
end function;
-- *** Bit Transfers ***
procedure SendBitInclClock( Data : in std_logic;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
BitInfo : in string;
Msg : in MsgInfo_r) is
begin
-- Initial Check
LevelCheck('0', Scl, Msg, "SCL must be 0 before SendBitInclClock is called [" & BitInfo & "]");
-- Assert Data
if Data = '0' then
Sda <= '0';
else
Sda <= 'Z';
end if;
wait for ClkQuartPeriod;
-- Send Clk Pulse
Scl <= 'Z';
LevelWait('1', Scl, 1 ms, Msg, "SCL held low by other device");
wait for ClkHalfPeriod;
CheckLastActivity(Scl, ClkHalfPeriod*0.9, -1, GenMessageNoPrefix(Msg.Func, "SCL high period too short [" & BitInfo & "]", Msg.User), Msg.Prefix);
LevelCheck(Data, Sda, Msg, "SDA readback does not match SDA transmit value during SCL pulse [" & BitInfo & "]");
CheckLastActivity(Sda, ClkHalfPeriod, -1, GenMessageNoPrefix(Msg.Func, "SDA not stable during SCL pulse [" & BitInfo & "]", Msg.User), Msg.Prefix);
Scl <= '0';
wait for ClkQuartPeriod;
end procedure;
procedure CheckBitInclClock( Data : in std_logic;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
BitInfo : in string;
Msg : in MsgInfo_r) is
begin
-- Initial Check
LevelCheck('0', Scl, Msg, "SCL must be 0 before CheckBitInclClock is called");
-- Wait for assertion
wait for ClkQuartPeriod;
-- Send Clk Pulse
Scl <= 'Z';
LevelWait('1', Scl, 1 ms, Msg, "SCL held low by other device");
wait for ClkHalfPeriod;
CheckLastActivity(Scl, ClkHalfPeriod*0.9, -1, GenMessageNoPrefix(Msg.Func, "SCL high period too short [" & BitInfo & "]", Msg.User), Msg.Prefix);
LevelCheck(Data, Sda, Msg, "Received wrong data [" & BitInfo & "]");
CheckLastActivity(Sda, ClkHalfPeriod, -1, GenMessageNoPrefix(Msg.Func, "SDA not stable during SCL pulse [" & BitInfo & "]", Msg.User), Msg.Prefix);
Scl <= '0';
wait for ClkQuartPeriod;
end procedure;
procedure SendBitExclClock( Data : in std_logic;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Timeout : in time;
BitInfo : in string;
Msg : in MsgInfo_r;
ClockStretch : in time) is
variable Stretched_v : boolean := false;
begin
-- Initial Check
LevelCheck('0', Scl, Msg, "SCL must be 0 before SendBitExclClock is called");
-- Clock stretching
if ClockStretch > 0 ns then
Scl <= '0';
wait for ClockStretch;
Stretched_v := true;
end if;
-- Assert Data
if Data = '0' then
Sda <= '0';
else
Sda <= 'Z';
end if;
if Stretched_v then
wait for ClkQuartPeriod;
Scl <= 'Z';
end if;
-- Wait clock rising edge
LevelWait('1', Scl, Timeout, Msg, "SCL did not go high");
-- wait clock falling edge
LevelWait('0', Scl, Timeout, Msg, "SCL did not go low");
LevelCheck(Data, Sda, Msg, "Received wrong data [" & BitInfo & "]");
CheckLastActivity(Sda, ClkHalfPeriod, -1, GenMessageNoPrefix(Msg.Func, "SDA not stable during SCL pulse [" & BitInfo & "]", Msg.User), Msg.Prefix);
-- wait until center of low
wait for ClkQuartPeriod;
end procedure;
procedure CheckBitExclClock( Data : in std_logic;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Timeout : in time;
BitInfo : in string;
Msg : in MsgInfo_r;
ClockStretch : in time) is
begin
-- Initial Check
LevelCheck('0', Scl, Msg, "SCL must be 0 before CheckBitExclClock is called");
-- Wait clock rising edge
if ClockStretch > 0 ns then
Scl <= '0';
wait for ClockStretch;
Scl <= 'Z';
end if;
LevelWait('1', Scl, Timeout, Msg, "SCL did not go high");
-- wait clock falling edge
LevelWait('0', Scl, Timeout, Msg, "SCL did not go low");
LevelCheck(Data, Sda, Msg, "Received wrong data [" & BitInfo & "]");
CheckLastActivity(Sda, ClkHalfPeriod, -1, GenMessageNoPrefix(Msg.Func, "SDA not stable during SCL pulse [" & BitInfo & "]", Msg.User), Msg.Prefix);
-- wait until center of low
wait for ClkQuartPeriod;
end procedure;
-- *** Byte Transfers ***
procedure SendByteInclClock( Data : in std_logic_vector(7 downto 0);
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in MsgInfo_r) is
begin
-- Do bits
for i in 7 downto 0 loop
SendBitInclClock(Data(i), Scl, Sda, to_string(i), Msg);
end loop;
end procedure;
procedure ExpectByteExclClock( ExpData : in std_logic_vector(7 downto 0);
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in MsgInfo_r;
Timeout : in time;
ClkStretch : in time) is
begin
-- Do bits
for i in 7 downto 0 loop
CheckBitExclClock(ExpData(i), Scl, Sda, Timeout, to_string(i), Msg, ClkStretch);
end loop;
end procedure;
-- -----------------------------------------------------------------------
-- Functions
-- -----------------------------------------------------------------------
function I2cGetAddr( Addr : in integer;
Trans : in I2c_Transaction_t) return integer is
begin
return Addr*2+choose(Trans=I2c_READ, 1, 0);
end function;
-- -----------------------------------------------------------------------
-- Master Side Transactions
-- -----------------------------------------------------------------------
procedure I2cPullup(signal Scl : inout std_logic;
signal Sda : inout std_logic) is
begin
Scl <= 'H';
Sda <= 'H';
end procedure;
procedure I2cBusFree( signal Scl : inout std_logic;
signal Sda : inout std_logic) is
begin
Scl <= 'Z';
Sda <= 'Z';
end procedure;
procedure I2cSetFrequency( FrequencyHz : in real) is
begin
FreqClk_v := FrequencyHz;
end procedure;
procedure I2cMasterSendStart( signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
Prefix : in string := "###ERROR###: ") is
constant MsgInfo : MsgInfo_r := (Prefix, "I2cMasterSendStart", Msg);
begin
-- Initial check
LevelCheck('1', Scl, MsgInfo, "SCL must be 1 before procedure is called");
LevelCheck('1', Sda, MsgInfo, "SDA must be 1 before procedure is called");
-- Do start condition
wait for ClkQuartPeriod;
Sda <= '0';
LevelCheck('1', Scl, MsgInfo, "SCL must be 1 during SDA falling edge");
wait for ClkQuartPeriod;
-- Go to center of clk low period
Scl <= '0';
wait for ClkQuartPeriod;
end procedure;
procedure I2cMasterSendRepeatedStart( signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
Prefix : in string := "###ERROR###: ") is
constant MsgInfo : MsgInfo_r := (Prefix, "I2cMasterSendRepeatedStart", Msg);
begin
-- Initial check
if to01X(Scl) = '1' then
LevelCheck('1', Sda, MsgInfo, "SDA must be 1 before procedure is called if SCL = 1");
end if;
-- Do repeated start
if Scl = '0' then
Sda <= 'Z';
wait for ClkQuartPeriod;
LevelCheck('1', Sda, MsgInfo, "SDA held low by other device");
Scl <= 'Z';
wait for ClkQuartPeriod;
LevelCheck('1', Scl, MsgInfo, "SCL held low by other device");
end if;
wait for ClkQuartPeriod;
Sda <= '0';
LevelCheck('1', Scl, MsgInfo, "SCL must be 1 during SDA falling edge");
wait for ClkQuartPeriod;
-- Go to center of clk low period
Scl <= '0';
wait for ClkQuartPeriod;
end procedure;
procedure I2cMasterSendStop( signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
Prefix : in string := "###ERROR###: ") is
constant MsgInfo : MsgInfo_r := (Prefix, "I2cMasterSendStop", Msg);
begin
-- Initial check
if to01X(Scl) = '1' then
LevelCheck('0', Sda, MsgInfo, "SDA must be 0 before procedure is called if SCL = 1");
end if;
-- Do stop
if Scl = '0' then
Sda <= '0';
wait for ClkQuartPeriod;
Scl <= 'Z';
wait for ClkQuartPeriod;
LevelCheck('1', Scl, MsgInfo, "SCL held low by other device");
else
wait for ClkQuartPeriod;
end if;
Sda <= 'Z';
LevelCheck('1', Scl, MsgInfo, "SCL must be 1 during SDA rising edge");
-- Go to center of clk high period
wait for ClkQuartPeriod;
end procedure;
procedure I2cMasterSendAddr( Address : in integer;
IsRead : in boolean;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
AddrBits : in integer := 7; -- 7 or 10
ExpectedAck : in std_logic := '0'; -- '0' for ack, '1' for nack, anything else for "don't check"
Prefix : in string := "###ERROR###: ") is
constant AddrSlv_c : std_logic_vector(9 downto 0) := std_logic_vector(to_unsigned(Address, 10));
constant Rw_c : std_logic := choose(IsRead, '1', '0');
begin
-- 7 Bit addressing
if AddrBits = 7 then
SendByteInclClock(AddrSlv_c(6 downto 0) & Rw_c, Scl, Sda, (Prefix, "I2cMasterSendAddr 7b", Msg));
Sda <= 'Z';
CheckBitInclClock(ExpectedAck, Scl, Sda, "ACK", (Prefix, "I2cMasterSendAddr 7b", Msg));
-- 10 Bit addressing
elsif AddrBits = 10 then
SendByteInclClock("11110" & AddrSlv_c(9 downto 8) & Rw_c, Scl, Sda, (Prefix, "I2cMasterSendAddr 10b 9:8", Msg));
Sda <= 'Z';
CheckBitInclClock(ExpectedAck, Scl, Sda, "ACK", (Prefix, "I2cMasterSendAddr 10b 9:8", Msg));
SendByteInclClock(AddrSlv_c(7 downto 0), Scl, Sda, (Prefix, "I2cMasterSendAddr 10b 7:0", Msg));
Sda <= 'Z';
CheckBitInclClock(ExpectedAck, Scl, Sda, "ACK", (Prefix, "I2cMasterSendAddr 10b 7:0", Msg));
else
report Prefix & "I2cMasterSendAddr - Illegal addrBits (must be 7 or 10) - " & Msg severity error;
end if;
end procedure;
procedure I2cMasterSendByte( Data : in integer range -128 to 255;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
ExpectedAck : in std_logic := '0'; -- '0' for ack, '1' for nack, anything else for "don't check"
Prefix : in string := "###ERROR###: ") is
variable DataSlv_v : std_logic_vector(7 downto 0);
begin
-- Do data
if Data < 0 then
DataSlv_v := std_logic_vector(to_signed(Data, 8));
else
DataSlv_v := std_logic_vector(to_unsigned(Data, 8));
end if;
SendByteInclClock(DataSlv_v, Scl, Sda, (Prefix, "I2cMasterSendByte", Msg));
Sda <= 'Z';
CheckBitInclClock(ExpectedAck, Scl, Sda, "ACK", (Prefix, "I2cMasterSendByte", Msg));
end procedure;
procedure I2cMasterExpectByte( ExpData : in integer range -128 to 255;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
AckOutput : in std_logic := '0'; -- '0' for ack, '1' for nack
Prefix : in string := "###ERROR###: ") is
variable Data_v : std_logic_vector(7 downto 0);
begin
-- Convert data
if ExpData < 0 then
Data_v := std_logic_vector(to_signed(ExpData, 8));
else
Data_v := std_logic_vector(to_unsigned(ExpData, 8));
end if;
-- do bits
Sda <= 'Z';
for i in 7 downto 0 loop
CheckBitInclClock(Data_v(i), Scl, Sda, to_string(i), (Prefix, "I2cMasterExpectByte", Msg));
end loop;
SendBitInclClock(AckOutput, Scl, Sda, "ACK", (Prefix, "I2cMasterExpectByte", Msg));
end procedure;
-- -----------------------------------------------------------------------
-- Slave Side Transactions
-- -----------------------------------------------------------------------
procedure I2cSlaveWaitStart( signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
Timeout : in time := 1 ms;
Prefix : in string := "###ERROR###: ") is
constant MsgInfo : MsgInfo_r := (Prefix, "I2cSlaveWaitStart", Msg);
begin
-- Initial check
LevelCheck('1', Scl, MsgInfo, "SCL must be 1 before procedure is called");
LevelCheck('1', Sda, MsgInfo, "SDA must be 1 before procedure is called");
-- Do start checking
LevelWait('0', Sda, Timeout, MsgInfo, "SDA did not go low");
LevelCheck('1', Scl, MsgInfo, "SCL must be 1 during SDA falling edge");
LevelWait('0', Scl, Timeout, MsgInfo, "SCL did not go low");
LevelCheck('0', Sda, MsgInfo, "SDA must be 0 during SCL falling edge");
-- Wait for center of SCL low
wait for ClkQuartPeriod;
end procedure;
procedure I2cSlaveWaitRepeatedStart( signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
Timeout : in time := 1 ms;
ClkStretch : in time := 0 ns; -- hold clock-low for at least this time
Prefix : in string := "###ERROR###: ") is
constant MsgInfo : MsgInfo_r := (Prefix, "I2cSlaveWaitRepeatedStart", Msg);
begin
-- Initial Check
if to01X(Scl) = '1' then
LevelCheck('1', Sda, MsgInfo, "SDA must be 1 before procedure is called if SCL = 1");
end if;
-- Do Check
if to01X(Scl) = '0' then
-- Clock stretching
if ClkStretch > 0 ns then
Scl <= '0';
wait for ClkStretch;
Scl <= 'Z';
end if;
LevelWait('1', Scl, Timeout, MsgInfo, "SCL did not go high");
LevelCheck('1', Sda, MsgInfo, "SDA must be 1 before SCL goes high");
end if;
LevelWait('0', Sda, Timeout, MsgInfo, "SDA did not go low");
LevelCheck('1', Scl, MsgInfo, "SCL must be 1 during SDA falling edge");
LevelWait('0', Scl, Timeout, MsgInfo, "SCL did not go low");
LevelCheck('0', Sda, MsgInfo, "SDA must be 0 during SCL falling edge");
-- Wait for center of SCL low
wait for ClkQuartPeriod;
end procedure;
procedure I2cSlaveWaitStop( signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
Timeout : in time := 1 ms;
ClkStretch : in time := 0 ns; -- hold clock-low for at least this time
Prefix : in string := "###ERROR###: ") is
constant MsgInfo : MsgInfo_r := (Prefix, "I2cSlaveWaitStop", Msg);
begin
-- Initial check
if to01X(Scl) = '1' then
LevelCheck('0', Sda, MsgInfo, "SDA must be 0 before procedure is called if SCL = 1");
end if;
-- Do Check
if Scl = '0' then
-- Clock stretching
if ClkStretch > 0 ns then
Scl <= '0';
wait for ClkStretch;
Scl <= 'Z';
end if;
LevelWait('1', Scl, Timeout, MsgInfo, "SCL did not go high");
LevelCheck('0', Sda, MsgInfo, "SDA must be 0 before SCL goes high");
end if;
LevelWait('1', Sda, Timeout, MsgInfo, "SDA did not go high");
LevelCheck('1', Scl, MsgInfo, "SCL must be 1 during SDA rising edge");
-- Wait for center of SCL low
wait for ClkQuartPeriod;
end procedure;
procedure I2cSlaveExpectAddr( Address : in integer;
IsRead : in boolean;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
AddrBits : in integer := 7; -- 7 or 10
AckOutput : in std_logic := '0'; -- '0' for ack, '1' for nack
Timeout : in time := 1 ms;
ClkStretch : in time := 0 ns; -- hold clock-low for at least this time
Prefix : in string := "###ERROR###: ") is
constant AddrSlv_c : std_logic_vector(9 downto 0) := std_logic_vector(to_unsigned(Address, 10));
constant Rw_c : std_logic := choose(IsRead, '1', '0');
begin
-- 7 Bit addressing
if AddrBits = 7 then
ExpectByteExclClock(AddrSlv_c(6 downto 0) & Rw_c, Scl, Sda, (Prefix, "I2cSlaveExpectAddr 7b", Msg), Timeout, ClkStretch);
SendBitExclClock(AckOutput, Scl, Sda, Timeout, "ACK", (Prefix, "I2cSlaveExpectAddr 7b ack", Msg), ClkStretch);
I2cBusFree(Scl, Sda);
-- 10 Bit addressing
elsif AddrBits = 10 then
ExpectByteExclClock("11110" & AddrSlv_c(9 downto 8) & Rw_c, Scl, Sda, (Prefix, "I2cSlaveExpectAddr 10b 9:8" , Msg), Timeout, ClkStretch);
SendBitExclClock(AckOutput, Scl, Sda, Timeout, "ACK", (Prefix, "I2cSlaveExpectAddr 10b 9:8 ack", Msg), ClkStretch);
I2cBusFree(Scl, Sda);
ExpectByteExclClock(AddrSlv_c(7 downto 0), Scl, Sda, (Prefix, "I2cSlaveExpectAddr 10b 7:0", Msg), Timeout, ClkStretch);
SendBitExclClock(AckOutput, Scl, Sda, Timeout, "ACK", (Prefix, "I2cSlaveExpectAddr 10b 7:0 ack", Msg), ClkStretch);
I2cBusFree(Scl, Sda);
else
report Prefix & "I2cSlaveExpectAddr - Illegal addrBits (must be 7 or 10) - " & Msg severity error;
end if;
end procedure;
procedure I2cSlaveExpectByte( ExpData : in integer range -128 to 255;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
AckOutput : in std_logic := '0'; -- '0' for ack, '1' for nack
Timeout : in time := 1 ms;
ClkStretch : in time := 0 ns; -- hold clock-low for at least this time
Prefix : in string := "###ERROR###: ") is
variable Data_v : std_logic_vector(7 downto 0);
begin
if ExpData < 0 then
Data_v := std_logic_vector(to_signed(ExpData, 8));
else
Data_v := std_logic_vector(to_unsigned(ExpData, 8));
end if;
ExpectByteExclClock(Data_v, Scl, Sda, (Prefix, "I2cSlaveExpectByte", Msg), Timeout, ClkStretch);
SendBitExclClock(AckOutput, Scl, Sda, Timeout, "ACK", (Prefix, "I2cSlaveExpectByte ack", Msg), ClkStretch);
I2cBusFree(Scl, Sda);
end procedure;
procedure I2cSlaveSendByte( Data : in integer range -128 to 255;
signal Scl : inout std_logic;
signal Sda : inout std_logic;
Msg : in string := "No Msg";
ExpectedAck : in std_logic := '0'; -- '0' for ack, '1' for nack, anything else for "don't check"
Timeout : in time := 1 ms;
ClkStretch : in time := 0 ns; -- hold clock-low for at least this time
Prefix : in string := "###ERROR###: ") is
variable Data_v : std_logic_vector(7 downto 0);
begin
-- Convert Data
if Data < 0 then
Data_v := std_logic_vector(to_signed(Data, 8));
else
Data_v := std_logic_vector(to_unsigned(Data, 8));
end if;
-- Send data
for i in 7 downto 0 loop
SendBitExclClock(Data_v(i), Scl, Sda, Timeout, to_string(i), (Prefix, "I2cSlaveSendByte", Msg), ClkStretch);
end loop;
-- Check ack
I2cBusFree(Scl, Sda);
CheckBitExclClock(ExpectedAck, Scl, Sda, Timeout, "ACK", (Prefix, "I2cSlaveSendByte", Msg), ClkStretch);
end procedure;
end psi_tb_i2c_pkg;
|
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nbit_multiplier is
generic(n: integer:=4);
port(
mulA,mulB: in std_logic_vector(n-1 downto 0);
prod: out std_logic_vector(2*n-1 downto 0)
);
end nbit_multiplier;
architecture primary of nbit_multiplier is
begin
prod <= std_logic_vector(to_unsigned(to_integer(unsigned(mulA)) * to_integer(unsigned(mulB)),2*n));
end primary; |
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nbit_multiplier is
generic(n: integer:=4);
port(
mulA,mulB: in std_logic_vector(n-1 downto 0);
prod: out std_logic_vector(2*n-1 downto 0)
);
end nbit_multiplier;
architecture primary of nbit_multiplier is
begin
prod <= std_logic_vector(to_unsigned(to_integer(unsigned(mulA)) * to_integer(unsigned(mulB)),2*n));
end primary; |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package hexutil is
function to_1(c : character) return std_logic;
function to_2(c : character) return std_logic_vector;
function to_3(c : character) return std_logic_vector;
function to_4(c : character) return std_logic_vector;
end package;
package body hexutil is
-- Return the bits of the supplied hex nibble
function to_4(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
case c is
when '0' =>
nibble := "0000";
when '1' =>
nibble := "0001";
when '2' =>
nibble := "0010";
when '3' =>
nibble := "0011";
when '4' =>
nibble := "0100";
when '5' =>
nibble := "0101";
when '6' =>
nibble := "0110";
when '7' =>
nibble := "0111";
when '8' =>
nibble := "1000";
when '9' =>
nibble := "1001";
when 'a' =>
nibble := "1010";
when 'A' =>
nibble := "1010";
when 'b' =>
nibble := "1011";
when 'B' =>
nibble := "1011";
when 'c' =>
nibble := "1100";
when 'C' =>
nibble := "1100";
when 'd' =>
nibble := "1101";
when 'D' =>
nibble := "1101";
when 'e' =>
nibble := "1110";
when 'E' =>
nibble := "1110";
when 'f' =>
nibble := "1111";
when 'F' =>
nibble := "1111";
when 'X' =>
nibble := "XXXX";
when 'x' =>
nibble := "XXXX";
when 'Z' =>
nibble := "ZZZZ";
when 'z' =>
nibble := "ZZZZ";
when others =>
nibble := "UUUU";
end case;
return nibble;
end function;
-- Return the least-significant bit of the supplied hex nibble
function to_1(c : character) return std_logic is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(0);
end function;
-- Return two least-significant bits of the supplied hex nibble
function to_2(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(1 downto 0);
end function;
-- Return three least-significant bits of the supplied hex nibble
function to_3(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(2 downto 0);
end function;
end package body;
|
-------------------------------------------------------------------------------
--
-- Distributed Memory Generator - VHDL Behavioral Model
--
-------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Filename : dist_mem_gen_v8_0.vhd
--
-- Author : Xilinx
--
-- Description : Distributed Memory Simulation Model
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity dist_mem_gen_v8_0 is
generic (
C_FAMILY : STRING := "VIRTEX5";
C_ADDR_WIDTH : INTEGER := 6;
C_DEFAULT_DATA : STRING := "0";
C_ELABORATION_DIR : STRING := "0";
C_DEPTH : INTEGER := 64;
C_HAS_CLK : INTEGER := 1;
C_HAS_D : INTEGER := 1;
C_HAS_DPO : INTEGER := 0;
C_HAS_DPRA : INTEGER := 0;
C_HAS_I_CE : INTEGER := 0;
C_HAS_QDPO : INTEGER := 0;
C_HAS_QDPO_CE : INTEGER := 0;
C_HAS_QDPO_CLK : INTEGER := 0;
C_HAS_QDPO_RST : INTEGER := 0;
C_HAS_QDPO_SRST : INTEGER := 0;
C_HAS_QSPO : INTEGER := 0;
C_HAS_QSPO_CE : INTEGER := 0;
C_HAS_QSPO_RST : INTEGER := 0;
C_HAS_QSPO_SRST : INTEGER := 0;
C_HAS_SPO : INTEGER := 1;
C_HAS_WE : INTEGER := 1;
C_MEM_INIT_FILE : STRING := "NULL.MIF";
C_MEM_TYPE : INTEGER := 1;
C_PIPELINE_STAGES : INTEGER := 0;
C_QCE_JOINED : INTEGER := 0;
C_QUALIFY_WE : INTEGER := 0;
C_READ_MIF : INTEGER := 0;
C_REG_A_D_INPUTS : INTEGER := 0;
C_REG_DPRA_INPUT : INTEGER := 0;
C_SYNC_ENABLE : INTEGER := 0;
C_WIDTH : INTEGER := 16;
C_PARSER_TYPE : INTEGER := 1);
port (
a : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
clk : in std_logic := '0';
we : in std_logic := '0';
i_ce : in std_logic := '1';
qspo_ce : in std_logic := '1';
qdpo_ce : in std_logic := '1';
qdpo_clk : in std_logic := '0';
qspo_rst : in std_logic := '0';
qdpo_rst : in std_logic := '0';
qspo_srst : in std_logic := '0';
qdpo_srst : in std_logic := '0';
spo : out std_logic_vector(c_width-1 downto 0);
dpo : out std_logic_vector(c_width-1 downto 0);
qspo : out std_logic_vector(c_width-1 downto 0);
qdpo : out std_logic_vector(c_width-1 downto 0));
end dist_mem_gen_v8_0;
architecture behavioral of dist_mem_gen_v8_0 is
-- Register delay
CONSTANT C_TCQ : time := 100 ps;
constant max_address : std_logic_vector(c_addr_width-1 downto 0) :=
std_logic_vector(to_unsigned(c_depth-1, c_addr_width));
constant c_rom : integer := 0;
constant c_sp_ram : integer := 1;
constant c_dp_ram : integer := 2;
constant c_sdp_ram : integer := 4;
type mem_type is array ((2**c_addr_width)-1 downto 0) of std_logic_vector(c_width-1 downto 0);
---------------------------------------------------------------------
-- Convert character to type std_logic.
---------------------------------------------------------------------
impure function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
---------------------------------------------------------------------
impure function read_mif (
filename : in string;
def_data : in std_logic_vector;
depth : in integer;
width : in integer)
return mem_type is
file meminitfile : text;
variable mif_status : file_open_status;
variable bitline : line;
variable bitsgood : boolean := true;
variable bitchar : character;
variable lines : integer := 0;
variable memory_content : mem_type;
begin
for i in 0 to depth-1 loop
memory_content(i) := def_data;
end loop; -- i
file_open(mif_status, meminitfile, filename, read_mode);
if mif_status /= open_ok then
assert false
report "Error: read_mem_init_file: could not open MIF."
severity failure;
end if;
lines := 0;
for i in 0 to depth-1 loop
if not(endfile(meminitfile)) and i < depth then
memory_content(i) := (others => '0');
readline(meminitfile, bitline);
for j in 0 to width-1 loop
read(bitline, bitchar, bitsgood);
if ((bitsgood = false) or
((bitchar /= ' ') and (bitchar /= cr) and
(bitchar /= ht) and (bitchar /= lf) and
(bitchar /= '0') and (bitchar /= '1') and
(bitchar /= 'x') and (bitchar /= 'z'))) then
assert false
report
"Warning: dist_mem_utils: unknown or illegal " &
"character encountered while reading mif - " &
"finishing file read." & cr &
"This could be due to an undersized mif file"
severity warning;
exit; -- abort the file read
end if;
memory_content(i)(width-1-j) := char_to_std_logic(bitchar);
end loop; -- j
else
exit;
end if;
lines := i + 1;
end loop;
file_close(meminitfile);
assert not(lines > depth)
report "MIF file contains more addresses than the memory."
severity failure;
assert lines = depth
report
"MIF file size does not match memory size." & cr &
"Remaining addresses in memory are padded with default data."
severity warning;
return memory_content;
end read_mif;
---------------------------------------------------------------------
impure function string_to_std_logic_vector (
the_string : string;
size : integer)
return std_logic_vector is
variable slv_tmp : std_logic_vector(1 to size) := (others => '0');
variable slv : std_logic_vector(size-1 downto 0) := (others => '0');
variable index : integer := 0;
begin
slv_tmp := (others => '0');
index := size;
if the_string'length > size then
for i in the_string'length downto the_string'length-size+1 loop
slv_tmp(index) := char_to_std_logic(the_string(i));
index := index - 1;
end loop; -- i
else
for i in the_string'length downto 1 loop
slv_tmp(index) := char_to_std_logic(the_string(i));
index := index - 1;
end loop; -- i
end if;
for i in 1 to size loop
slv(size-i) := slv_tmp(i);
end loop; -- i
return slv;
end string_to_std_logic_vector;
---------------------------------------------------------------------
-- Convert the content of a file and return an array of
-- std_logic_vectors.
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Function which initialises the memory from the c_default_data
-- string or the c_mem_init_file MIF file.
---------------------------------------------------------------------
impure function init_mem (
memory_type : in integer;
read_mif_file : in integer;
filename : in string;
default_data : in string;
depth : in integer;
width : in integer)
return mem_type is
variable memory_content : mem_type := (others => (others => '0'));
variable def_data : std_logic_vector(width-1 downto 0) := (others => '0');
constant all_zeros : std_logic_vector(width-1 downto 0) := (others => '0');
begin
def_data := string_to_std_logic_vector(default_data, width);
if read_mif_file = 0 then
-- If the memory is not initialised from a MIF file then fill the memory array with
-- default data.
for i in 0 to depth-1 loop
memory_content(i) := def_data;
end loop; -- i
else
--Initialise the memory from the MIF file.
memory_content := read_mif(filename, def_data, depth, width);
end if;
return memory_content;
end init_mem;
------------------------------------------------------------------
signal memory : mem_type :=
init_mem(
c_mem_type,
c_read_mif,
c_mem_init_file,
c_default_data,
c_depth,
c_width);
-- address signal connected to memory
signal a_int : std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- address signal connected to memory, which has been registered.
signal a_reg : std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
signal a_over : std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- dual port read address signal connected to dual port memory
signal dpra_int : std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- dual port read address signal connected to dual port memory, which
-- has been registered.
signal dpra_reg : std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
signal dpra_over : std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- input data signal connected to RAM
signal d_int : std_logic_vector(c_width-1 downto 0) := (others => '0');
-- input data signal connected to RAM, which has been registered.
signal d_reg : std_logic_vector(c_width-1 downto 0) := (others => '0');
-- Write Enable signal connected to memory
signal we_int : std_logic := '0';
-- Write Enable signal connected to memory, which has been registered.
signal we_reg : std_logic := '0';
-- Internal Clock Enable for optional qspo output
signal qspo_ce_int : std_logic := '0';
-- Internal Clock Enable for optional qspo output, which has been
-- registered
signal qspo_ce_reg : std_logic := '0';
-- Internal Clock Enable for optional qdpo output
signal qdpo_ce_int : std_logic := '0';
-- Internal Clock Enable for optional qspo output, which has been
-- registered
signal qdpo_ce_reg : std_logic := '0';
-- Internal version of the spo output
signal spo_int : std_logic_vector(c_width-1 downto 0) := (others => '0');
-- Pipeline for the qspo output
signal qspo_pipe : std_logic_vector(c_width-1 downto 0) := (others => '0');
-- Internal version of the qspo output
signal qspo_int : std_logic_vector(c_width-1 downto 0) :=
string_to_std_logic_vector(c_default_data, c_width);
-- Internal version of the dpo output
signal dpo_int : std_logic_vector(c_width-1 downto 0) := (others => '0');
-- Pipeline for the qdpo output
signal qdpo_pipe : std_logic_vector(c_width-1 downto 0) := (others => '0');
-- Internal version of the qdpo output
signal qdpo_int : std_logic_vector(c_width-1 downto 0) :=
string_to_std_logic_vector(c_default_data, c_width);
-- Content of spo_int from address a
signal data_sp : std_logic_vector(c_width-1 downto 0);
-- Content of Dual Port Output at address dpra
signal data_dp : std_logic_vector(c_width-1 downto 0);
-- Content of spo_int from address a
signal data_sp_over : std_logic_vector(c_width-1 downto 0);
-- Content of Dual Port Output at address dpra
signal data_dp_over : std_logic_vector(c_width-1 downto 0);
signal a_is_over : std_logic;
signal dpra_is_over : std_logic;
begin
p_warn_behavioural : process
begin
assert false report "This core is supplied with a behavioral model. To model cycle-accurate behavior you must run timing simulation." severity warning;
wait;
end process p_warn_behavioural;
---------------------------------------------------------------------
-- Infer any optional input registers, in the clk clock domain.
---------------------------------------------------------------------
p_optional_input_registers : process
begin
wait until c_reg_a_d_inputs = 1 and clk'event and clk = '1';
if c_mem_type = c_rom then
if (c_has_qspo_ce = 1) then
if (qspo_ce = '1') then
a_reg <= a after C_TCQ;
end if;
else
a_reg <= a after C_TCQ;
end if;
elsif c_has_i_ce = 0 then
we_reg <= we after C_TCQ;
a_reg <= a after C_TCQ;
d_reg <= d after C_TCQ;
elsif c_qualify_we = 0 then
we_reg <= we after C_TCQ;
if i_ce = '1' then
a_reg <= a after C_TCQ;
d_reg <= d after C_TCQ;
end if;
elsif c_qualify_we = 1 and i_ce = '1' then
we_reg <= we after C_TCQ;
a_reg <= a after C_TCQ;
d_reg <= d after C_TCQ;
end if;
qspo_ce_reg <= qspo_ce after C_TCQ;
end process p_optional_input_registers;
---------------------------------------------------------------------
-- If the inputs are registered, propogate those signals to the
-- internal versions that will be used by the memory construct.
---------------------------------------------------------------------
g_optional_input_regs : if c_reg_a_d_inputs = 1 generate
we_int <= we_reg;
d_int <= d_reg;
a_int <= a_reg;
qspo_ce_int <= qspo_ce_reg;
end generate g_optional_input_regs;
---------------------------------------------------------------------
-- Otherwise, just pass the ports directly to the internal signals
-- used by the memory construct.
---------------------------------------------------------------------
g_no_optional_input_regs : if c_reg_a_d_inputs = 0 generate
we_int <= we;
d_int <= d;
a_int <= a;
qspo_ce_int <= qspo_ce;
end generate g_no_optional_input_regs;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- In addition, there are inputs that can be registered, that can
-- have their own clock domain. This is best handled in a seperate
-- process for readability.
---------------------------------------------------------------------
p_optional_dual_port_regs : process
begin
if c_reg_dpra_input = 0 then
wait;
elsif c_has_qdpo_clk = 0 then
wait until clk'event and clk = '1';
else
wait until qdpo_clk'event and qdpo_clk = '1';
end if;
if c_qce_joined = 1 then
if c_has_qspo_ce = 0 or (c_has_qspo_ce = 1 and qspo_ce = '1') then
dpra_reg <= dpra after C_TCQ;
end if;
elsif c_has_qdpo_ce = 0 or (c_has_qdpo_ce = 1 and qdpo_ce = '1') then
dpra_reg <= dpra after C_TCQ;
end if;
qdpo_ce_reg <= qdpo_ce after C_TCQ;
end process p_optional_dual_port_regs;
---------------------------------------------------------------------
-- If the inputs are registered, propogate those signals to the
-- internal versions that will be used by the memory construct.
---------------------------------------------------------------------
g_optional_dual_port_regs : if c_reg_dpra_input = 1 generate
dpra_int <= dpra_reg;
qdpo_ce_int <= qdpo_ce_reg;
end generate g_optional_dual_port_regs;
---------------------------------------------------------------------
-- Otherwise, just pass the ports directly to the internal signals
-- used by the memory construct.
---------------------------------------------------------------------
g_no_optional_dual_port_regs : if c_reg_dpra_input = 0 generate
dpra_int <= dpra;
qdpo_ce_int <= qdpo_ce;
end generate g_no_optional_dual_port_regs;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- For the Single Port RAM and Dual Port RAM memory types, define how
-- the RAM is written to.
---------------------------------------------------------------------
p_write_to_spram_dpram : process
begin -- process p_write_to_spram_dpram
wait until clk'event and clk = '1' and we_int = '1'
and c_mem_type /= c_rom;
if a_is_over = '1' then
assert false
report "Writing to out of range address." & cr &
"Max address is " & integer'image(c_depth-1) & "." &
cr & "Write ignored."
severity warning;
else
memory(to_integer(unsigned(a_int))) <= d_int after C_TCQ;
end if;
end process p_write_to_spram_dpram;
---------------------------------------------------------------------
-- Form the spo_int signal and the optional spo output. spo_int will
-- be used in assigning the optional qspo output.
---------------------------------------------------------------------
spo_int <= data_sp_over when a_is_over = '1' else data_sp;
a_is_over <= '1' when a_int > max_address else '0';
dpra_is_over <= '1' when dpra_int > max_address else '0';
g_dpra_over: for i in 0 to c_addr_width-1 generate
dpra_over(i) <= dpra_int(i) and max_address(i);
end generate g_dpra_over;
data_sp <= memory(to_integer(unsigned(a_int)));
data_sp_over <= (others => 'X');
data_dp <= memory(to_integer(unsigned(dpra_int)));
data_dp_over <= (others => 'X');
g_has_spo : if c_has_spo = 1 generate
spo <= spo_int;
end generate g_has_spo;
g_has_no_spo : if c_has_spo = 0 generate
spo <= (others => 'X');
end generate g_has_no_spo;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Form the dpo_int signal and the optional dpo output. dpo_int will
-- be used in assigning the optional qdpo output.
---------------------------------------------------------------------
g_dpram: if (c_mem_type = c_dp_ram or c_mem_type = c_sdp_ram) generate
dpo_int <= data_dp_over when dpra_is_over = '1' else data_dp;
end generate g_dpram;
g_not_dpram: if (c_mem_type /= c_dp_ram and c_mem_type /= c_sdp_ram) generate
dpo_int <= (others => 'X');
end generate g_not_dpram;
assert not((c_mem_type = c_dp_ram or c_mem_type = c_sdp_ram) and dpra_is_over = '1')
report "DPRA trying to read from out of range address." & cr &
"Max address is " & integer'image(c_depth-1)
severity warning;
g_has_dpo : if c_has_dpo = 1 generate
dpo <= dpo_int;
end generate g_has_dpo;
g_has_no_dpo : if c_has_dpo = 0 generate
dpo <= (others => 'X');
end generate g_has_no_dpo;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Form the QSPO output depending on the following:
---------------------------------------------------------------------
-- Generics
-- c_has_qspo
-- c_has_qspo_rst
-- c_sync_enable
-- c_has_qspo_ce
---------------------------------------------------------------------
-- Signals
-- clk
-- qspo_rst
-- qspo_srst
-- qspo_ce
-- spo_int
---------------------------------------------------------------------
p_has_qspo : process
begin
if c_has_qspo /= 1 then
qspo_int <= (others => 'X');
qspo_pipe <= (others => 'X');
wait;
end if;
wait until (clk'event and clk = '1') or (qspo_rst = '1' and c_has_qspo_rst = 1);
---------------------------------------------------------------------
if c_has_qspo_rst = 1 and qspo_rst = '1' then
qspo_pipe <= (others => '0');
qspo_int <= (others => '0');
elsif c_has_qspo_srst = 1 and qspo_srst = '1' then
if c_sync_enable = 0 then
qspo_pipe <= (others => '0') after C_TCQ;
qspo_int <= (others => '0') after C_TCQ;
elsif c_has_qspo_ce = 0 or (c_has_qspo_ce = 1 and qspo_ce_int = '1') then
qspo_pipe <= (others => '0') after C_TCQ;
qspo_int <= (others => '0') after C_TCQ;
end if;
elsif c_has_qspo_ce = 0 or qspo_ce_int = '1' then
qspo_pipe <= spo_int after C_TCQ;
if c_pipeline_stages = 1 then
qspo_int <= qspo_pipe after C_TCQ;
else
qspo_int <= spo_int after C_TCQ;
end if;
end if;
end process p_has_qspo;
---------------------------------------------------------------------
qspo <= qspo_int;
---------------------------------------------------------------------
-- Form the QDPO output depending on the following:
---------------------------------------------------------------------
-- Generics
-- c_has_qdpo
-- c_qce_joined
-- c_has_qdpo_clk
-- c_has_qdpo_rst
-- c_has_qdpo_srst
-- c_has_qdpo_ce
-- c_has_qspo_ce
-- c_sync_enable
---------------------------------------------------------------------
-- Signals
-- clk
-- qdpo_clk
-- qdpo_rst
-- qdpo_srst
-- qdpo_ce
-- qspo_ce
-- dpo_int
---------------------------------------------------------------------
p_has_qdpo : process
begin
if c_has_qdpo /= 1 then
qdpo_pipe <= (others => 'X');
qdpo_int <= (others => 'X');
wait;
end if;
if c_has_qdpo_clk = 0 then
--Common clock enables used for qspo and qdpo outputs.
--Therefore we have one clock domain to worry about.
wait until (clk'event and clk = '1')
or (c_has_qdpo_rst = 1 and qdpo_rst = '1');
else
--The qdpo output is in a seperate clock domain from the rest
--of the dual port RAM.
wait until
(qdpo_clk'event and qdpo_clk = '1') or
(c_has_qdpo_rst = 1 and qdpo_rst = '1');
end if;
if c_has_qdpo_rst = 1 and qdpo_rst = '1' then
-- Async reset asserted.
qdpo_pipe <= (others => '0');
qdpo_int <= (others => '0');
elsif c_has_qdpo_srst = 1 and qdpo_srst = '1' then
if c_sync_enable = 0 then
--Synchronous reset asserted. Sync reset overrides the
--clock enable
qdpo_pipe <= (others => '0') after C_TCQ;
qdpo_int <= (others => '0') after C_TCQ;
elsif c_qce_joined = 0 then
-- Seperate qdpo_clk domain
if c_has_qdpo_ce = 0 or (c_has_qdpo_ce = 1 and qdpo_ce_int = '1') then
-- Either the qdpo does not have a clock enable, or it
-- does, and it has been asserted permitting the sync
-- reset to act.
qdpo_pipe <= (others => '0') after C_TCQ;
qdpo_int <= (others => '0') after C_TCQ;
end if;
elsif c_has_qspo_ce = 0 or (c_has_qspo_ce = 1 and qspo_ce_int = '1') then
-- Common clock domain so we monitor the common clock
-- enable to see if the a sync reset is permitted, or there
-- are no clock enables to block the sync reset.
qdpo_pipe <= (others => '0') after C_TCQ;
qdpo_int <= (others => '0') after C_TCQ;
end if;
elsif c_qce_joined = 0 then
-- qdpo is a seperate clock domain, so check to see if there
-- is a qdpo_ce clock enable, if it is there, assign qdpo when
-- qdpo_ce is active - if there is no clock enable just assign
-- it.
if c_has_qdpo_ce = 0 or (c_has_qdpo_ce = 1 and qdpo_ce_int = '1') then
qdpo_pipe <= dpo_int after C_TCQ;
if c_pipeline_stages = 1 then
qdpo_int <= qdpo_pipe after C_TCQ;
else
qdpo_int <= dpo_int after C_TCQ;
end if;
end if;
elsif c_has_qspo_ce = 0 or (c_has_qspo_ce = 1 and qspo_ce_int = '1') then
-- Common clock domain, check to see if there is a qspo_ce to
-- concern us.
qdpo_pipe <= dpo_int after C_TCQ;
if c_pipeline_stages = 1 then
qdpo_int <= qdpo_pipe after C_TCQ;
else
qdpo_int <= dpo_int after C_TCQ;
end if;
end if;
end process p_has_qdpo;
---------------------------------------------------------------------
qdpo <= qdpo_int;
end behavioral;
|
entity tb_sram02 is
end tb_sram02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_sram02 is
signal addr : std_logic_vector(3 downto 0);
signal rdat : std_logic_vector(7 downto 0);
signal wdat : std_logic_vector(7 downto 0);
signal wen : std_logic;
signal clk : std_logic;
begin
dut: entity work.sram02
port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat,
wen_i => wen);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
addr <= "0000";
wdat <= x"02";
wen <= '1';
pulse;
assert rdat = x"02" severity failure;
addr <= "0100";
wdat <= x"03";
wait for 1 ns;
assert rdat = x"02" severity failure;
pulse;
assert rdat = x"03" severity failure;
addr <= "0000";
wen <= '0';
pulse;
assert rdat = x"02" severity failure;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
--use work.GENERIC_WHEN.all;
entity TEST2 is
begin
end entity TEST2;
architecture BEHAVIOUR of TEST2 is
component GENERIC_WHEN is
generic( FOO : std_logic_vector(1 downto 0) );
port( IN1 : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(1 downto 0) );
end component GENERIC_WHEN;
signal S1 : std_logic_vector(1 downto 0);
signal S2 : std_logic_vector(1 downto 0);
begin
GENERIC_WHEN_INST : GENERIC_WHEN
generic map ( FOO => "0" & "0")
port map ( IN1 => S1,
OUT1 => S2 );
process
variable l : line;
begin
S1 <= "01";
writeline(output, l);
wait;
end process;
end architecture BEHAVIOUR;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
--use work.GENERIC_WHEN.all;
entity TEST2 is
begin
end entity TEST2;
architecture BEHAVIOUR of TEST2 is
component GENERIC_WHEN is
generic( FOO : std_logic_vector(1 downto 0) );
port( IN1 : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(1 downto 0) );
end component GENERIC_WHEN;
signal S1 : std_logic_vector(1 downto 0);
signal S2 : std_logic_vector(1 downto 0);
begin
GENERIC_WHEN_INST : GENERIC_WHEN
generic map ( FOO => "0" & "0")
port map ( IN1 => S1,
OUT1 => S2 );
process
variable l : line;
begin
S1 <= "01";
writeline(output, l);
wait;
end process;
end architecture BEHAVIOUR;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
--use work.GENERIC_WHEN.all;
entity TEST2 is
begin
end entity TEST2;
architecture BEHAVIOUR of TEST2 is
component GENERIC_WHEN is
generic( FOO : std_logic_vector(1 downto 0) );
port( IN1 : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(1 downto 0) );
end component GENERIC_WHEN;
signal S1 : std_logic_vector(1 downto 0);
signal S2 : std_logic_vector(1 downto 0);
begin
GENERIC_WHEN_INST : GENERIC_WHEN
generic map ( FOO => "0" & "0")
port map ( IN1 => S1,
OUT1 => S2 );
process
variable l : line;
begin
S1 <= "01";
writeline(output, l);
wait;
end process;
end architecture BEHAVIOUR;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: BLINKER
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Simulate a BLINKER by inverting the
-- font for 1/2 second.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BLINKER is
Port ( CLK : in STD_LOGIC;
ADDR_B : in STD_LOGIC_VECTOR (11 downto 0);
CURSOR_ADR : in STD_LOGIC_VECTOR (11 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (7 downto 0);
FONT_ROM : in STD_LOGIC_VECTOR (7 downto 0));
end BLINKER;
architecture Behavioral of BLINKER is
signal sel : std_logic;
signal out1 : std_logic_vector(7 downto 0):="11111111";
begin
with sel select
OUTPUT<=out1 when '1',
FONT_ROM when others;
sel<='1' when ADDR_B=CURSOR_ADR else '0';
process(CLK)
variable count : integer;
begin
if CLK'event and CLK='1' then
count:=count+1;
if count=12500000 then
out1<=FONT_ROM;
elsif count=25000000 then
out1<="11111111";
count:=0;
end if;
end if;
end process;
end Behavioral;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: BLINKER
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Simulate a BLINKER by inverting the
-- font for 1/2 second.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BLINKER is
Port ( CLK : in STD_LOGIC;
ADDR_B : in STD_LOGIC_VECTOR (11 downto 0);
CURSOR_ADR : in STD_LOGIC_VECTOR (11 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (7 downto 0);
FONT_ROM : in STD_LOGIC_VECTOR (7 downto 0));
end BLINKER;
architecture Behavioral of BLINKER is
signal sel : std_logic;
signal out1 : std_logic_vector(7 downto 0):="11111111";
begin
with sel select
OUTPUT<=out1 when '1',
FONT_ROM when others;
sel<='1' when ADDR_B=CURSOR_ADR else '0';
process(CLK)
variable count : integer;
begin
if CLK'event and CLK='1' then
count:=count+1;
if count=12500000 then
out1<=FONT_ROM;
elsif count=25000000 then
out1<="11111111";
count:=0;
end if;
end if;
end process;
end Behavioral;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: BLINKER
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Simulate a BLINKER by inverting the
-- font for 1/2 second.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BLINKER is
Port ( CLK : in STD_LOGIC;
ADDR_B : in STD_LOGIC_VECTOR (11 downto 0);
CURSOR_ADR : in STD_LOGIC_VECTOR (11 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (7 downto 0);
FONT_ROM : in STD_LOGIC_VECTOR (7 downto 0));
end BLINKER;
architecture Behavioral of BLINKER is
signal sel : std_logic;
signal out1 : std_logic_vector(7 downto 0):="11111111";
begin
with sel select
OUTPUT<=out1 when '1',
FONT_ROM when others;
sel<='1' when ADDR_B=CURSOR_ADR else '0';
process(CLK)
variable count : integer;
begin
if CLK'event and CLK='1' then
count:=count+1;
if count=12500000 then
out1<=FONT_ROM;
elsif count=25000000 then
out1<="11111111";
count:=0;
end if;
end if;
end process;
end Behavioral;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: BLINKER
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Simulate a BLINKER by inverting the
-- font for 1/2 second.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BLINKER is
Port ( CLK : in STD_LOGIC;
ADDR_B : in STD_LOGIC_VECTOR (11 downto 0);
CURSOR_ADR : in STD_LOGIC_VECTOR (11 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (7 downto 0);
FONT_ROM : in STD_LOGIC_VECTOR (7 downto 0));
end BLINKER;
architecture Behavioral of BLINKER is
signal sel : std_logic;
signal out1 : std_logic_vector(7 downto 0):="11111111";
begin
with sel select
OUTPUT<=out1 when '1',
FONT_ROM when others;
sel<='1' when ADDR_B=CURSOR_ADR else '0';
process(CLK)
variable count : integer;
begin
if CLK'event and CLK='1' then
count:=count+1;
if count=12500000 then
out1<=FONT_ROM;
elsif count=25000000 then
out1<="11111111";
count:=0;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Multiplexer 2:1
-- Implements a 2-to-1 multiplexer of a given width.
library ieee;
use ieee.std_logic_1164.all;
entity mux_2x1 is
generic (
WIDTH : positive := 1
);
port (
output : out std_logic_vector(WIDTH-1 downto 0);
sel : in std_logic;
in0 : in std_logic_vector(WIDTH-1 downto 0);
in1 : in std_logic_vector(WIDTH-1 downto 0)
);
end mux_2x1;
architecture BHV of mux_2x1 is
begin
output <=
in0 when sel = '0' else
in1 when sel = '1' else
(others => '0');
end BHV;
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.2 use cram_*delay functions to determine delays
-- 2012-12-20 614 1.1.4 use 85 MHz (max after rlv4 update)
-- 2010-11-27 341 1.1.3 add sys_conf_clksys_mhz (clksys in MHz)
-- 2010-11-26 340 1.1.2 default now clksys=60 MHz
-- 2010-11-22 339 1.1.1 add memctl related constants
-- 2010-11-13 338 1.1 add dcm related constants
-- 2010-05-23 294 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 10;
constant sys_conf_clkfx_multiply : positive := 17;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := altera;
constant CFG_CLKMUL : integer := (7);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 16;
constant CFG_DTLBNUM : integer := 16;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1 + 64*0;
constant CFG_ATBSZ : integer := 1;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- HPS
constant CFG_HPS2FPGA : integer := 1;
constant CFG_FPGA2HPS : integer := 1;
constant CFG_HPS_RESET : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity ci_bridge_tb is
end;
architecture sym of ci_bridge_tb is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal address : std_logic_vector(14 downto 0) := (others => '0');
signal byteenable : std_logic_vector(7 downto 0) := (others => '0');
signal writedata : std_logic_vector(63 downto 0) := (others => '0');
signal write : std_logic := '0';
signal readdata : std_logic_vector(63 downto 0);
signal read : std_logic := '0';
signal waitrequest : std_logic;
signal cam_address : std_logic_vector(17 downto 0);
signal cam_writedata : std_logic_vector(7 downto 0);
signal cam_write : std_logic;
signal cam_readdata : std_logic_vector(7 downto 0);
signal cam_read : std_logic;
signal cam_waitreq : std_logic;
signal cia_ce_n : std_logic;
signal cib_ce_n : std_logic;
signal ci_reg_n : std_logic;
signal ci_a : std_logic_vector(14 downto 0);
signal ci_d_out : std_logic_vector(7 downto 0);
signal ci_d_out_en : std_logic;
signal ci_we_n : std_logic;
signal ci_oe_n : std_logic;
signal ci_iowr_n : std_logic;
signal ci_iord_n : std_logic;
signal cia_wait_n : std_logic := '1';
signal cib_wait_n : std_logic := '1';
signal cia_data_buf_oe_n : std_logic;
signal cib_data_buf_oe_n : std_logic;
signal ci_bus_dir : std_logic;
signal cia_data : std_logic_vector(7 downto 0) := (others => 'Z');
signal cib_data : std_logic_vector(7 downto 0) := (others => 'Z');
signal ci_data : std_logic_vector(7 downto 0) := (others => 'Z');
begin
cia_data <= (others => 'L') when cia_data_buf_oe_n or ci_bus_dir else ci_data;
cib_data <= (others => 'H') when cib_data_buf_oe_n or ci_bus_dir else ci_data;
ci_data <= ci_d_out when ci_d_out_en else
cia_data when not cia_data_buf_oe_n and ci_bus_dir else
cib_data when not cib_data_buf_oe_n and ci_bus_dir else
(others => 'Z');
ADAPTER_0 : entity work.avalon64_to_avalon8
generic map(
OUT_ADDR_WIDTH => 18
)
port map (
rst => rst,
clk => clk,
address => address,
byteenable => byteenable,
writedata => writedata,
write => write,
readdata => readdata,
read => read,
waitrequest => waitrequest,
out_address => cam_address,
out_writedata => cam_writedata,
out_write => cam_write,
out_readdata => cam_readdata,
out_read => cam_read,
out_waitrequest => cam_waitreq
);
BRIDGE_0 : entity work.ci_bridge
port map (
clk => clk,
rst => rst,
address => (others => '0'),
byteenable => (others => '0'),
writedata => (others => '0'),
write => '0',
readdata => open,
interrupt => open,
cam_address => cam_address,
cam_writedata => cam_writedata,
cam_write => cam_write,
cam_readdata => cam_readdata,
cam_read => cam_read,
cam_waitreq => cam_waitreq,
cam_interrupts => open,
cia_reset => open,
cib_reset => open,
cia_ce_n => cia_ce_n,
cib_ce_n => cib_ce_n,
ci_reg_n => ci_reg_n,
ci_a => ci_a,
ci_d_in => ci_data,
ci_d_out => ci_d_out,
ci_d_en => ci_d_out_en,
ci_we_n => ci_we_n,
ci_oe_n => ci_oe_n,
ci_iowr_n => ci_iowr_n,
ci_iord_n => ci_iord_n,
cia_wait_n => cia_wait_n,
cib_wait_n => cib_wait_n,
cia_ireq_n => '1',
cib_ireq_n => '1',
cia_cd_n => "00",
cib_cd_n => "00",
cia_overcurrent_n => '1',
cib_overcurrent_n => '1',
cia_reset_buf_oe_n => open,
cib_reset_buf_oe_n => open,
cia_data_buf_oe_n => cia_data_buf_oe_n,
cib_data_buf_oe_n => cib_data_buf_oe_n,
ci_bus_dir => ci_bus_dir
);
process
begin
wait for 8 ns;
clk <= not clk;
end process;
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
--
wait until rising_edge(clk);
address <= std_logic_vector(to_unsigned(0, 15));
byteenable <= "11111111";
read <= '1';
wait until rising_edge(clk) and waitrequest = '0';
--
address <= std_logic_vector(to_unsigned(2, 15));
byteenable <= "00110000";
read <= '1';
wait until rising_edge(clk) and waitrequest = '0';
read <= '0';
--
wait until rising_edge(clk);
--
wait;
end process;
end;
|
-------------------------------------------------------------------------------
--
-- Title : OpenMAC_phyAct
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : OpenMAC_phyAct.vhd
-- Generated : Wed Jul 27 12:01:32 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-27 V0.01 zelenkaj First version
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {OpenMAC_phyAct} architecture {rtl}}
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity OpenMAC_phyAct is
generic(
iBlinkFreq_g : integer := 6 -- [Hz]
);
port(
clk : in std_logic;
rst : in std_logic;
tx_en : in std_logic;
rx_dv : in std_logic;
act_led : out std_logic
);
end OpenMAC_phyAct;
--}} End of automatically maintained section
architecture rtl of OpenMAC_phyAct is
constant iMaxCnt : integer := 50e6 / iBlinkFreq_g;
constant iLog2MaxCnt : integer := integer(ceil(log2(real(iMaxCnt))));
signal cnt : std_logic_vector(iLog2MaxCnt-1 downto 0);
signal cnt_tc : std_logic;
signal actTrig : std_logic;
signal actEnable : std_logic;
begin
act_led <= cnt(cnt'high) when actEnable = '1' else '0';
ledCntr : process(clk, rst)
begin
if rst = '1' then
actTrig <= '0';
actEnable <= '0';
elsif clk = '1' and clk'event then
--monoflop, of course no default value!
if actTrig = '1' and cnt_tc = '1' then
--counter overflow and activity within last cycle
actEnable <= '1';
elsif cnt_tc = '1' then
--counter overflow but no activity
actEnable <= '0';
end if;
--monoflop, of course no default value!
if cnt_tc = '1' then
--count cycle over, reset trigger
actTrig <= '0';
elsif tx_en = '1' or rx_dv = '1' then
--activity within cycle
actTrig <= '1';
end if;
end if;
end process;
theFreeRunCnt : process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
elsif clk = '1' and clk'event then
--nice, it may count for ever!
cnt <= cnt - 1;
end if;
end process;
cnt_tc <= '1' when cnt = 0 else '0'; --"counter overflow"
end rtl;
|
-------------------------------------------------------------------------------
--
-- Title : OpenMAC_phyAct
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : OpenMAC_phyAct.vhd
-- Generated : Wed Jul 27 12:01:32 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-27 V0.01 zelenkaj First version
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {OpenMAC_phyAct} architecture {rtl}}
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity OpenMAC_phyAct is
generic(
iBlinkFreq_g : integer := 6 -- [Hz]
);
port(
clk : in std_logic;
rst : in std_logic;
tx_en : in std_logic;
rx_dv : in std_logic;
act_led : out std_logic
);
end OpenMAC_phyAct;
--}} End of automatically maintained section
architecture rtl of OpenMAC_phyAct is
constant iMaxCnt : integer := 50e6 / iBlinkFreq_g;
constant iLog2MaxCnt : integer := integer(ceil(log2(real(iMaxCnt))));
signal cnt : std_logic_vector(iLog2MaxCnt-1 downto 0);
signal cnt_tc : std_logic;
signal actTrig : std_logic;
signal actEnable : std_logic;
begin
act_led <= cnt(cnt'high) when actEnable = '1' else '0';
ledCntr : process(clk, rst)
begin
if rst = '1' then
actTrig <= '0';
actEnable <= '0';
elsif clk = '1' and clk'event then
--monoflop, of course no default value!
if actTrig = '1' and cnt_tc = '1' then
--counter overflow and activity within last cycle
actEnable <= '1';
elsif cnt_tc = '1' then
--counter overflow but no activity
actEnable <= '0';
end if;
--monoflop, of course no default value!
if cnt_tc = '1' then
--count cycle over, reset trigger
actTrig <= '0';
elsif tx_en = '1' or rx_dv = '1' then
--activity within cycle
actTrig <= '1';
end if;
end if;
end process;
theFreeRunCnt : process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
elsif clk = '1' and clk'event then
--nice, it may count for ever!
cnt <= cnt - 1;
end if;
end process;
cnt_tc <= '1' when cnt = 0 else '0'; --"counter overflow"
end rtl;
|
-------------------------------------------------------------------------------
--
-- Title : OpenMAC_phyAct
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : OpenMAC_phyAct.vhd
-- Generated : Wed Jul 27 12:01:32 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-27 V0.01 zelenkaj First version
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {OpenMAC_phyAct} architecture {rtl}}
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity OpenMAC_phyAct is
generic(
iBlinkFreq_g : integer := 6 -- [Hz]
);
port(
clk : in std_logic;
rst : in std_logic;
tx_en : in std_logic;
rx_dv : in std_logic;
act_led : out std_logic
);
end OpenMAC_phyAct;
--}} End of automatically maintained section
architecture rtl of OpenMAC_phyAct is
constant iMaxCnt : integer := 50e6 / iBlinkFreq_g;
constant iLog2MaxCnt : integer := integer(ceil(log2(real(iMaxCnt))));
signal cnt : std_logic_vector(iLog2MaxCnt-1 downto 0);
signal cnt_tc : std_logic;
signal actTrig : std_logic;
signal actEnable : std_logic;
begin
act_led <= cnt(cnt'high) when actEnable = '1' else '0';
ledCntr : process(clk, rst)
begin
if rst = '1' then
actTrig <= '0';
actEnable <= '0';
elsif clk = '1' and clk'event then
--monoflop, of course no default value!
if actTrig = '1' and cnt_tc = '1' then
--counter overflow and activity within last cycle
actEnable <= '1';
elsif cnt_tc = '1' then
--counter overflow but no activity
actEnable <= '0';
end if;
--monoflop, of course no default value!
if cnt_tc = '1' then
--count cycle over, reset trigger
actTrig <= '0';
elsif tx_en = '1' or rx_dv = '1' then
--activity within cycle
actTrig <= '1';
end if;
end if;
end process;
theFreeRunCnt : process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
elsif clk = '1' and clk'event then
--nice, it may count for ever!
cnt <= cnt - 1;
end if;
end process;
cnt_tc <= '1' when cnt = 0 else '0'; --"counter overflow"
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity plong_graphics is
port(
clk, not_reset: in std_logic;
nes1_up, nes1_down: in std_logic;
nes2_up, nes2_down: in std_logic;
nes1_start, nes2_start: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
video_on: in std_logic;
rgb_stream: out std_logic_vector(2 downto 0);
ball_bounced: out std_logic;
ball_missed: out std_logic
);
end plong_graphics;
architecture dispatcher of plong_graphics is
constant SCREEN_WIDTH: integer := 640;
constant SCREEN_HEIGHT: integer := 480;
type game_states is (start, waiting, playing, game_over);
signal state, state_next: game_states;
type counter_storage is array(0 to 3) of std_logic_vector(17 downto 0);
constant COUNTER_VALUES: counter_storage :=
(
"110010110111001101", -- 208333
"101000101100001011", -- 166667
"100001111010001001", -- 138889
"011101000100001000" -- 119048
);
-- counters to determine ball control frequency
signal ball_control_counter,
ball_control_counter_next: std_logic_vector(17 downto 0);
signal ball_control_value: integer;
-- counts how many times the ball hits the bar
-- used to determine ball speed
signal bounce_counter, bounce_counter_next: std_logic_vector(7 downto 0);
constant MIDDLE_LINE_POS: integer := SCREEN_WIDTH / 2;
signal middle_line_on: std_logic;
signal middle_line_rgb: std_logic_vector(2 downto 0);
signal score_1, score_1_next: std_logic_vector(5 downto 0);
signal score_2, score_2_next: std_logic_vector(5 downto 0);
signal score_on: std_logic;
signal current_score: std_logic_vector(5 downto 0);
signal score_font_addr: std_logic_vector(8 downto 0);
-- message format is "PLAYER p WINS!"
-- where p is replaced by player_id
signal message_on, player_id_on: std_logic;
signal message_font_addr, player_id_font_addr: std_logic_vector(8 downto 0);
signal font_addr: std_logic_vector(8 downto 0);
signal font_data: std_logic_vector(0 to 7);
signal font_pixel: std_logic;
signal font_rgb: std_logic_vector(2 downto 0);
constant BALL_SIZE: integer := 16; -- ball is square
signal ball_enable: std_logic;
signal ball_addr: std_logic_vector(3 downto 0);
signal ball_px_addr: std_logic_vector(3 downto 0);
signal ball_data: std_logic_vector(0 to BALL_SIZE - 1);
signal ball_pixel: std_logic;
signal ball_rgb: std_logic_vector(2 downto 0);
signal ball_x, ball_x_next: std_logic_vector(9 downto 0);
signal ball_y, ball_y_next: std_logic_vector(9 downto 0);
signal ball_h_dir, ball_h_dir_next, ball_v_dir, ball_v_dir_next: std_logic;
signal ball_bounce, ball_miss: std_logic;
constant BAR_1_POS: integer := 20;
constant BAR_2_POS: integer := 600;
constant BAR_WIDTH: integer := 20;
constant BAR_HEIGHT: integer := 64;
signal bar_pos: integer;
signal bar_addr: std_logic_vector(5 downto 0);
signal bar_data: std_logic_vector(0 to BAR_WIDTH - 1);
signal bar_pixel: std_logic;
signal bar_rgb: std_logic_vector(2 downto 0);
signal bar_1_y, bar_1_y_next,
bar_2_y, bar_2_y_next: std_logic_vector(9 downto 0);
signal ball_on, bar_on: std_logic;
signal nes_start: std_logic;
begin
process(state, ball_x, nes_start, score_1, score_2)
begin
state_next <= state;
ball_enable <= '0';
ball_miss <= '0';
score_1_next <= score_1;
score_2_next <= score_2;
case state is
when start =>
score_1_next <= (others => '0');
score_2_next <= (others => '0');
state_next <= waiting;
when waiting =>
ball_enable <= '0';
if score_1 = 7 or score_2 = 7 then
state_next <= game_over;
elsif nes_start = '1' then
state_next <= playing;
end if;
when playing =>
ball_enable <= '1';
if ball_x = 0 then
-- player 2 wins
score_2_next <= score_2 + 1;
state_next <= waiting;
ball_miss <= '1';
elsif ball_x = SCREEN_WIDTH - BALL_SIZE then
-- player 1 wins
score_1_next <= score_1 + 1;
state_next <= waiting;
ball_miss <= '1';
end if;
when game_over =>
if nes_start = '1' then
state_next <= start;
end if;
end case;
end process;
process(clk, not_reset)
begin
if not_reset = '0' then
state <= start;
ball_x <= (others => '0');
ball_y <= (others => '0');
bar_1_y <= conv_std_logic_vector(SCREEN_HEIGHT / 2 - BAR_HEIGHT / 2, 10);
bar_2_y <= conv_std_logic_vector(SCREEN_HEIGHT / 2 - BAR_HEIGHT / 2, 10);
ball_h_dir <= '0';
ball_v_dir <= '0';
bounce_counter <= (others => '0');
ball_control_counter <= (others => '0');
score_1 <= (others => '0');
score_2 <= (others => '0');
elsif clk'event and clk = '0' then
state <= state_next;
ball_x <= ball_x_next;
ball_y <= ball_y_next;
bar_1_y <= bar_1_y_next;
bar_2_y <= bar_2_y_next;
ball_h_dir <= ball_h_dir_next;
ball_v_dir <= ball_v_dir_next;
bounce_counter <= bounce_counter_next;
ball_control_counter <= ball_control_counter_next;
score_1 <= score_1_next;
score_2 <= score_2_next;
end if;
end process;
nes_start <= (nes1_start or nes2_start);
score_on <= '1' when px_y(9 downto 3) = 1 and
(px_x(9 downto 3) = 42 or px_x(9 downto 3) = 37) else
'0';
current_score <= score_1 when px_x < 320 else score_2;
-- numbers start at memory location 128
-- '1' starts at 136, '2' at 144 and so on
score_font_addr <= conv_std_logic_vector(128, 9) +
(current_score(2 downto 0) & current_score(5 downto 3));
player_id_on <= '1' when state = game_over and px_y(9 downto 3) = 29 and
(px_x(9 downto 3) = 19 or px_x(9 downto 3) = 59) else
'0';
-- player_id will display either 1 or 2
player_id_font_addr <= "010001000" when px_x < 320 else "010010000";
message_on <= '1' when state = game_over and
-- message on player_1's side
((score_1 > score_2 and
px_x(9 downto 3) >= 12 and
px_x(9 downto 3) < 26 and
px_y(9 downto 3) = 29) or
-- message on player_2's side
(score_2 > score_1 and
px_x(9 downto 3) >= 52 and
px_x(9 downto 3) < 66 and
px_y(9 downto 3) = 29)) else
'0';
with px_x(9 downto 3) select
message_font_addr <= "110000000" when "0110100"|"0001100", -- P
"101100000" when "0110101"|"0001101", -- L
"100001000" when "0110110"|"0001110", -- A
"111001000" when "0110111"|"0001111", -- Y
"100101000" when "0111000"|"0010000", -- E
"110010000" when "0111001"|"0010001", -- R
"111100000" when "0111011"|"0010011", -- not visible
"110111000" when "0111101"|"0010101", -- W
"101111000" when "0111110"|"0010110", -- O
"101110000" when "0111111"|"0010111", -- N
"000001000" when "1000000"|"0011000", -- !
"000000000" when others;
-- font address mutltiplexer
font_addr <= px_y(2 downto 0) + score_font_addr when score_on = '1' else
px_y(2 downto 0) + player_id_font_addr when player_id_on = '1' else
px_y(2 downto 0) + message_font_addr when message_on = '1' else
(others => '0');
font_pixel <= font_data(conv_integer(px_x(2 downto 0)));
font_rgb <= "000" when font_pixel = '1' else "111";
direction_control: process(
ball_control_counter,
ball_x, ball_y,
ball_h_dir, ball_v_dir,
ball_h_dir_next, ball_v_dir_next,
bar_1_y, bar_2_y
)
begin
ball_h_dir_next <= ball_h_dir;
ball_v_dir_next <= ball_v_dir;
ball_bounce <= '0';
--
-- BEWARE! Looks like ball_bounce signal is generated twice
-- due to slower clock! Too lazy to fix now :D
--
if ball_control_counter = 0 then
if ball_x = bar_1_pos + BAR_WIDTH and
ball_y + BALL_SIZE > bar_1_y and
ball_y < bar_1_y + BAR_HEIGHT then
ball_h_dir_next <= '1';
ball_bounce <= '1';
elsif ball_x + BALL_SIZE = bar_2_pos and
ball_y + BALL_SIZE > bar_2_y and
ball_y < bar_2_y + BAR_HEIGHT then
ball_h_dir_next <= '0';
ball_bounce <= '1';
elsif ball_x < bar_1_pos + BAR_WIDTH and
ball_x + BALL_SIZE > bar_1_pos then
if ball_y + BALL_SIZE = bar_1_y then
ball_v_dir_next <= '0';
elsif ball_y = bar_1_y + BAR_HEIGHT then
ball_v_dir_next <= '1';
end if;
elsif ball_x + BALL_SIZE > bar_2_pos and
ball_x < bar_2_pos + BAR_WIDTH then
if ball_y + BALL_SIZE = bar_2_y then
ball_v_dir_next <= '0';
elsif ball_y = bar_2_y + BAR_HEIGHT then
ball_v_dir_next <= '1';
end if;
end if;
if ball_y = 0 then
ball_v_dir_next <= '1';
elsif ball_y = SCREEN_HEIGHT - BALL_SIZE then
ball_v_dir_next <= '0';
end if;
end if;
end process;
bounce_counter_next <= bounce_counter + 1 when ball_bounce = '1' else
(others => '0') when ball_miss = '1' else
bounce_counter;
ball_control_value <= 0 when bounce_counter < 4 else
1 when bounce_counter < 15 else
2 when bounce_counter < 25 else
3;
ball_control_counter_next <= ball_control_counter + 1 when ball_control_counter < COUNTER_VALUES(ball_control_value) else
(others => '0');
ball_control: process(
ball_control_counter,
ball_x, ball_y,
ball_x_next, ball_y_next,
ball_h_dir, ball_v_dir,
ball_enable
)
begin
ball_x_next <= ball_x;
ball_y_next <= ball_y;
if ball_enable = '1' then
if ball_control_counter = 0 then
if ball_h_dir = '1' then
ball_x_next <= ball_x + 1;
else
ball_x_next <= ball_x - 1;
end if;
if ball_v_dir = '1' then
ball_y_next <= ball_y + 1;
else
ball_y_next <= ball_y - 1;
end if;
end if;
else
ball_x_next <= conv_std_logic_vector(SCREEN_WIDTH / 2 - BALL_SIZE / 2, 10);
ball_y_next <= conv_std_logic_vector(SCREEN_HEIGHT / 2 - BALL_SIZE / 2, 10);
end if;
end process;
bar_control: process(
bar_1_y, bar_2_y,
nes1_up, nes1_down,
nes2_up, nes2_down
)
begin
bar_1_y_next <= bar_1_y;
bar_2_y_next <= bar_2_y;
if nes1_up = '1' then
if bar_1_y > 0 then
bar_1_y_next <= bar_1_y - 1;
end if;
elsif nes1_down = '1' then
if bar_1_y < SCREEN_HEIGHT - BAR_HEIGHT - 1 then
bar_1_y_next <= bar_1_y + 1;
end if;
end if;
if nes2_up = '1' then
if bar_2_y > 0 then
bar_2_y_next <= bar_2_y - 1;
end if;
elsif nes2_down = '1' then
if bar_2_y < SCREEN_HEIGHT - BAR_HEIGHT - 1 then
bar_2_y_next <= bar_2_y + 1;
end if;
end if;
end process;
middle_line_on <= '1' when px_x = MIDDLE_LINE_POS else '0';
middle_line_rgb <= "000" when px_y(0) = '1' else "111";
ball_on <= '1' when px_x >= ball_x and
px_x < (ball_x + BALL_SIZE) and
px_y >= ball_y and
px_y < (ball_y + BALL_SIZE) else
'0';
-- whether bar_1 or bar_2 is on
bar_on <= '1' when (px_x >= BAR_1_POS and
px_x < BAR_1_POS + BAR_WIDTH and
px_y >= bar_1_y and
px_y < bar_1_y + BAR_HEIGHT) or
(px_x >= BAR_2_POS and
px_x < BAR_2_POS + BAR_WIDTH and
px_y >= bar_2_y and
px_y < bar_2_y + BAR_HEIGHT) else
'0';
ball_addr <= px_y(3 downto 0) - ball_y(3 downto 0);
ball_px_addr <= px_x(3 downto 0) - ball_x(3 downto 0);
ball_pixel <= ball_data(conv_integer(ball_px_addr));
ball_rgb <= "000" when ball_pixel = '1' else "111";
bar_addr <= (px_y(5 downto 0) - bar_1_y(5 downto 0)) when px_x < 320 else
(px_y(5 downto 0) - bar_2_y(5 downto 0));
bar_pos <= BAR_1_POS when px_x < 320 else BAR_2_POS;
bar_pixel <= bar_data(conv_integer(px_x - bar_pos));
bar_rgb <= "000" when bar_pixel = '1' else "111";
process(
ball_on, bar_on,
ball_rgb, bar_rgb,
score_on, message_on, font_rgb,
middle_line_on, middle_line_rgb,
video_on
)
begin
if video_on = '1' then
if bar_on = '1' then
rgb_stream <= bar_rgb;
elsif ball_on = '1' then
rgb_stream <= ball_rgb;
elsif middle_line_on = '1' then
rgb_stream <= middle_line_rgb;
-- scores and messages share rgb stream
elsif score_on = '1' or message_on = '1' then
rgb_stream <= font_rgb;
else
-- background is white
rgb_stream <= "111";
end if;
else
-- blank screen
rgb_stream <= "000";
end if;
end process;
ball_unit:
entity work.ball_rom(content)
port map(addr => ball_addr, data => ball_data);
bar_unit:
entity work.bar_rom(content)
port map(clk => clk, addr => bar_addr, data => bar_data);
font_unit:
entity work.codepage_rom(content)
port map(addr => font_addr, data => font_data);
ball_bounced <= ball_bounce;
ball_missed <= ball_miss;
end dispatcher;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
entity harness_dm_cache is
end harness_dm_cache;
architecture harness of harness_dm_cache is
signal clock : std_logic := '0';
signal clock_shifted : std_logic;
signal reset : std_logic;
signal client_req : t_mem_req := c_mem_req_init;
signal client_resp : t_mem_resp := c_mem_resp_init;
signal mem_req : t_mem_burst_req := c_mem_burst_req_init;
signal mem_resp : t_mem_burst_resp := c_mem_burst_resp_init;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(14 downto 0) := (others => 'H');
signal hit_count : unsigned(31 downto 0);
signal miss_count : unsigned(31 downto 0);
signal hit_ratio : real := 0.0;
begin
clock <= not clock after 10 ns;
clock_shifted <= transport clock after 7.5 ns;
reset <= '1', '0' after 100 ns;
i_cache: entity work.dm_cache
port map (
clock => clock,
reset => reset,
client_req => client_req,
client_resp => client_resp,
mem_req => mem_req,
mem_resp => mem_resp,
hit_count => hit_count,
miss_count => miss_count );
hit_ratio <= real(to_integer(hit_count)) / real(to_integer(miss_count) + to_integer(hit_count) + 1);
i_mem_master_bfm: entity work.mem_bus_master_bfm
generic map (
g_name => "mem_master" )
port map (
clock => clock,
req => client_req,
resp => client_resp );
i_mem_ctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => clock,
clk_shifted => clock_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
MEM_A => logic_A,
MEM_D => SDRAM_D );
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
SDRAM_A <= transport logic_A after 6 ns;
i_dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 1,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A(12 downto 0),
BA => SDRAM_A(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_D);
end harness;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
entity harness_dm_cache is
end harness_dm_cache;
architecture harness of harness_dm_cache is
signal clock : std_logic := '0';
signal clock_shifted : std_logic;
signal reset : std_logic;
signal client_req : t_mem_req := c_mem_req_init;
signal client_resp : t_mem_resp := c_mem_resp_init;
signal mem_req : t_mem_burst_req := c_mem_burst_req_init;
signal mem_resp : t_mem_burst_resp := c_mem_burst_resp_init;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(14 downto 0) := (others => 'H');
signal hit_count : unsigned(31 downto 0);
signal miss_count : unsigned(31 downto 0);
signal hit_ratio : real := 0.0;
begin
clock <= not clock after 10 ns;
clock_shifted <= transport clock after 7.5 ns;
reset <= '1', '0' after 100 ns;
i_cache: entity work.dm_cache
port map (
clock => clock,
reset => reset,
client_req => client_req,
client_resp => client_resp,
mem_req => mem_req,
mem_resp => mem_resp,
hit_count => hit_count,
miss_count => miss_count );
hit_ratio <= real(to_integer(hit_count)) / real(to_integer(miss_count) + to_integer(hit_count) + 1);
i_mem_master_bfm: entity work.mem_bus_master_bfm
generic map (
g_name => "mem_master" )
port map (
clock => clock,
req => client_req,
resp => client_resp );
i_mem_ctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => clock,
clk_shifted => clock_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
MEM_A => logic_A,
MEM_D => SDRAM_D );
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
SDRAM_A <= transport logic_A after 6 ns;
i_dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 1,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A(12 downto 0),
BA => SDRAM_A(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_D);
end harness;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
entity harness_dm_cache is
end harness_dm_cache;
architecture harness of harness_dm_cache is
signal clock : std_logic := '0';
signal clock_shifted : std_logic;
signal reset : std_logic;
signal client_req : t_mem_req := c_mem_req_init;
signal client_resp : t_mem_resp := c_mem_resp_init;
signal mem_req : t_mem_burst_req := c_mem_burst_req_init;
signal mem_resp : t_mem_burst_resp := c_mem_burst_resp_init;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(14 downto 0) := (others => 'H');
signal hit_count : unsigned(31 downto 0);
signal miss_count : unsigned(31 downto 0);
signal hit_ratio : real := 0.0;
begin
clock <= not clock after 10 ns;
clock_shifted <= transport clock after 7.5 ns;
reset <= '1', '0' after 100 ns;
i_cache: entity work.dm_cache
port map (
clock => clock,
reset => reset,
client_req => client_req,
client_resp => client_resp,
mem_req => mem_req,
mem_resp => mem_resp,
hit_count => hit_count,
miss_count => miss_count );
hit_ratio <= real(to_integer(hit_count)) / real(to_integer(miss_count) + to_integer(hit_count) + 1);
i_mem_master_bfm: entity work.mem_bus_master_bfm
generic map (
g_name => "mem_master" )
port map (
clock => clock,
req => client_req,
resp => client_resp );
i_mem_ctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => clock,
clk_shifted => clock_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
MEM_A => logic_A,
MEM_D => SDRAM_D );
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
SDRAM_A <= transport logic_A after 6 ns;
i_dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 1,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A(12 downto 0),
BA => SDRAM_A(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_D);
end harness;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
entity harness_dm_cache is
end harness_dm_cache;
architecture harness of harness_dm_cache is
signal clock : std_logic := '0';
signal clock_shifted : std_logic;
signal reset : std_logic;
signal client_req : t_mem_req := c_mem_req_init;
signal client_resp : t_mem_resp := c_mem_resp_init;
signal mem_req : t_mem_burst_req := c_mem_burst_req_init;
signal mem_resp : t_mem_burst_resp := c_mem_burst_resp_init;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(14 downto 0) := (others => 'H');
signal hit_count : unsigned(31 downto 0);
signal miss_count : unsigned(31 downto 0);
signal hit_ratio : real := 0.0;
begin
clock <= not clock after 10 ns;
clock_shifted <= transport clock after 7.5 ns;
reset <= '1', '0' after 100 ns;
i_cache: entity work.dm_cache
port map (
clock => clock,
reset => reset,
client_req => client_req,
client_resp => client_resp,
mem_req => mem_req,
mem_resp => mem_resp,
hit_count => hit_count,
miss_count => miss_count );
hit_ratio <= real(to_integer(hit_count)) / real(to_integer(miss_count) + to_integer(hit_count) + 1);
i_mem_master_bfm: entity work.mem_bus_master_bfm
generic map (
g_name => "mem_master" )
port map (
clock => clock,
req => client_req,
resp => client_resp );
i_mem_ctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => clock,
clk_shifted => clock_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
MEM_A => logic_A,
MEM_D => SDRAM_D );
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
SDRAM_A <= transport logic_A after 6 ns;
i_dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 1,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A(12 downto 0),
BA => SDRAM_A(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_D);
end harness;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.mem_bus_master_bfm_pkg.all;
entity harness_dm_cache is
end harness_dm_cache;
architecture harness of harness_dm_cache is
signal clock : std_logic := '0';
signal clock_shifted : std_logic;
signal reset : std_logic;
signal client_req : t_mem_req := c_mem_req_init;
signal client_resp : t_mem_resp := c_mem_resp_init;
signal mem_req : t_mem_burst_req := c_mem_burst_req_init;
signal mem_resp : t_mem_burst_resp := c_mem_burst_resp_init;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(14 downto 0) := (others => 'H');
signal hit_count : unsigned(31 downto 0);
signal miss_count : unsigned(31 downto 0);
signal hit_ratio : real := 0.0;
begin
clock <= not clock after 10 ns;
clock_shifted <= transport clock after 7.5 ns;
reset <= '1', '0' after 100 ns;
i_cache: entity work.dm_cache
port map (
clock => clock,
reset => reset,
client_req => client_req,
client_resp => client_resp,
mem_req => mem_req,
mem_resp => mem_resp,
hit_count => hit_count,
miss_count => miss_count );
hit_ratio <= real(to_integer(hit_count)) / real(to_integer(miss_count) + to_integer(hit_count) + 1);
i_mem_master_bfm: entity work.mem_bus_master_bfm
generic map (
g_name => "mem_master" )
port map (
clock => clock,
req => client_req,
resp => client_resp );
i_mem_ctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => clock,
clk_shifted => clock_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
MEM_A => logic_A,
MEM_D => SDRAM_D );
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
SDRAM_A <= transport logic_A after 6 ns;
i_dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 1,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A(12 downto 0),
BA => SDRAM_A(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_D);
end harness;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:43:50 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_stub.vhdl
-- Design : system_clock_splitter_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_clock_splitter_0_0 is
Port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end system_clock_splitter_0_0;
architecture stub of system_clock_splitter_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_in,latch_edge,clk_out";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "clock_splitter,Vivado 2016.4";
begin
end;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library proc_common_v4_0;
use proc_common_v4_0.sync_fifo_fg;
use proc_common_v4_0.srl_fifo_f;
use proc_common_v4_0.proc_common_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_MM2S : integer range 0 to 1 := 0;
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s_axis_updt_aclk : in std_logic ; --
--
--********************************-- --
--** Control and Status **-- --
--********************************-- --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--********************************-- --
--** Update Interfaces In **-- --
--********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--********************************-- --
--** Update Interfaces Out **-- --
--********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Number of words deep fifo needs to be. Depth required to store 2 word
-- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2
--constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2);
constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2));
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1);
-- Select between BRAM or LOGIC memory type
constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16);
-- Number of words deep fifo needs to be. Depth required to store all update
-- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE
constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG_WORDS_TO_UPDATE));
constant UPDATE_STS2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG2_WORDS_TO_UPDATE));
-- Select between BRAM or LOGIC memory type
constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16);
-- Select between BRAM or LOGIC memory type
constant STS2_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS2_QUEUE_DEPTH > 16);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_lsb_sm : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal write_curdesc_lsb1 : std_logic := '0';
signal write_curdesc_msb1 : std_logic := '0';
signal rden_del : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_d2 : std_logic := '0';
signal updt_active_re1 : std_logic := '0';
signal updt_active_re2 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
-- State Machine Signal
signal writing_status : std_logic := '0';
signal dataq_rden : std_logic := '0';
signal stsq_rden : std_logic := '0';
-- Pointer Queue FIFO Signals
signal ptr_queue_rden : std_logic := '0';
signal ptr_queue_wren : std_logic := '0';
signal ptr_queue_empty : std_logic := '0';
signal ptr_queue_full : std_logic := '0';
signal ptr_queue_din : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout_int : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts_queue_wren : std_logic := '0';
signal sts_queue_rden : std_logic := '0';
signal sts_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout_int : std_logic_vector (3 downto 0) := (others => '0');
signal sts_queue_full : std_logic := '0';
signal sts_queue_empty : std_logic := '0';
signal ptr2_queue_rden : std_logic := '0';
signal ptr2_queue_wren : std_logic := '0';
signal ptr2_queue_empty : std_logic := '0';
signal ptr2_queue_full : std_logic := '0';
signal ptr2_queue_din : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr2_queue_dout : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts2_queue_wren : std_logic := '0';
signal sts2_queue_rden : std_logic := '0';
signal sts2_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts2_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts2_queue_full : std_logic := '0';
signal sts2_queue_empty : std_logic := '0';
signal sts2_queue_empty_del : std_logic := '0';
signal sts2_dout_valid : std_logic := '0';
signal sts_dout_valid : std_logic := '0';
signal sts2_dout_valid_del : std_logic := '0';
signal valid_new : std_logic := '0';
signal valid_latch : std_logic := '0';
signal valid1_new : std_logic := '0';
signal valid1_latch : std_logic := '0';
signal empty_low : std_logic := '0';
-- Misc Support Signals
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal sinit : std_logic := '0';
signal updt_tvalid : std_logic := '0';
signal updt_tlast : std_logic := '0';
signal updt2_tvalid : std_logic := '0';
signal updt2_tlast : std_logic := '0';
attribute mark_debug of updt_tvalid : signal is "true";
attribute mark_debug of updt2_tvalid : signal is "true";
attribute mark_debug of updt_tlast : signal is "true";
attribute mark_debug of updt2_tlast : signal is "true";
signal status_d1, status_d2 : std_logic := '0';
signal updt_tvalid_int : std_logic := '0';
signal updt_tlast_int : std_logic := '0';
signal ptr_queue_empty_int : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal follower_reg_mm2s : std_logic_vector (33 downto 0) := (others => '0');
attribute mark_debug of follower_reg_mm2s : signal is "true";
signal follower_full_mm2s :std_logic := '0';
signal follower_empty_mm2s : std_logic := '0';
signal follower_reg_s2mm : std_logic_vector (33 downto 0) := (others => '0');
attribute mark_debug of follower_reg_s2mm : signal is "true";
signal follower_full_s2mm :std_logic := '0';
signal follower_empty_s2mm : std_logic := '0';
signal follower_reg, m_axis_updt_tdata_tmp : std_logic_vector (33 downto 0);
signal follower_full :std_logic := '0';
signal follower_empty : std_logic := '0';
signal sts_rden : std_logic := '0';
signal sts2_rden : std_logic := '0';
signal follower_tlast : std_logic := '0';
signal follower_reg_image : std_logic := '0';
signal m_axis_updt_tready_mm2s, m_axis_updt_tready_s2mm : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= follower_reg_mm2s (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) when updt_active = '1'
else follower_reg_s2mm (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) ;
m_axis_updt_tvalid <= updt_tvalid when updt_active = '1'
else updt2_tvalid;
m_axis_updt_tlast <= updt_tlast when updt_active = '1'
else updt2_tlast;
m_axis_updt_tready_mm2s <= m_axis_updt_tready when updt_active = '1' else '0';
m_axis_updt_tready_s2mm <= m_axis_updt_tready when updt2_active = '1' else '0';
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- channel 1
updt_active_re <= updt_active_re1 or updt_active_re2;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_re,
ptr_queue_empty_int,
m_axis_updt_tready,
updt_tvalid_int,
updt_tlast_int)
begin
write_curdesc_lsb_sm <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
dataq_rden <= '0';
stsq_rden <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(updt_active_re = '1')then
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor pointer
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_LSB =>
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(ptr_queue_empty_int = '0')then
write_curdesc_lsb_sm <= '1';
dataq_rden <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS; --READ_CURDESC_MSB;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
---------------------------------------------------------------
-- Get upper current descriptor
-- Reads one word from data queue fifo
---------------------------------------------------------------
-- when READ_CURDESC_MSB =>
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
-- if(ptr_queue_empty_int = '0')then
-- dataq_rden <= '1';
-- write_curdesc_msb <= '1';
-- pntr_ns <= WRITE_STATUS;
-- else
-- -- coverage off
-- pntr_ns <= READ_CURDESC_MSB;
-- -- coverage on
-- end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
-- De-MUX appropriage tvalid/tlast signals
writing_status <= '1';
-- Enable reading of Status Queue if datamover can
-- accept data
stsq_rden <= m_axis_updt_tready;
-- Hold in the status state until tlast is pulled
-- from status fifo
if(updt_tvalid_int = '1' and m_axis_updt_tready = '1'
and updt_tlast_int = '1')then
-- if(follower_full = '1' and m_axis_updt_tready = '1'
-- and follower_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
updt_tvalid_int <= updt_tvalid or updt2_tvalid;
updt_tlast_int <= updt_tlast or updt2_tlast;
ptr_queue_empty_int <= ptr_queue_empty when updt_active = '1' else
ptr2_queue_empty when updt2_active = '1' else
'1';
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate
begin
MM2S_CHANNEL : if C_INCLUDE_MM2S = 1 generate
updt_tvalid <= follower_full_mm2s and updt_active;
updt_tlast <= follower_reg_mm2s(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt_active;
sts_rden <= follower_empty_mm2s and (not sts_queue_empty); -- and updt_active;
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_mm2s = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (sts_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (sts_rden = '1') then
follower_reg_mm2s <= sts_queue_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re1 <= updt_active and not updt_active_d1;
-- I_UPDT_DATA_FIFO : entity proc_common_v4_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 32 ,
-- C_DEPTH => 8 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => ptr_queue_wren ,
-- Data_In => ptr_queue_din ,
-- FIFO_Read => ptr_queue_rden ,
-- Data_Out => ptr_queue_dout ,
-- FIFO_Empty => ptr_queue_empty ,
-- FIFO_Full => ptr_queue_full,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
ptr_queue_dout <= (others => '0');
elsif (ptr_queue_wren = '1') then
ptr_queue_dout <= ptr_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or ptr_queue_rden = '1') then
ptr_queue_empty <= '1';
ptr_queue_full <= '0';
elsif (ptr_queue_wren = '1') then
ptr_queue_empty <= '0';
ptr_queue_full <= '1';
end if;
end if;
end process;
-- Channel Pointer Queue (Generate Synchronous FIFO)
-- I_UPDT_STS_FIFO : entity proc_common_v4_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 34 ,
-- C_DEPTH => 4 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => sts_queue_wren ,
-- Data_In => sts_queue_din ,
-- FIFO_Read => sts_rden, --sts_queue_rden ,
-- Data_Out => sts_queue_dout ,
-- FIFO_Empty => sts_queue_empty ,
-- FIFO_Full => sts_queue_full ,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
sts_queue_dout <= (others => '0');
elsif (sts_queue_wren = '1') then
sts_queue_dout <= sts_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or sts_rden = '1') then
sts_queue_empty <= '1';
sts_queue_full <= '0';
elsif (sts_queue_wren = '1') then
sts_queue_empty <= '0';
sts_queue_full <= '1';
end if;
end if;
end process;
-- Channel Status Queue (Generate Synchronous FIFO)
--*****************************************
--** Channel Data Port Side of Queues
--*****************************************
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA
C_S_AXIS_UPDPTR_TDATA_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid
and not ptr_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis_updtptr_tready <= not ptr_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts_queue_wren <= s_axis_updtsts_tvalid
and not sts_queue_full;
-- Drive channel port with ready if room in status queue
s_axis_updtsts_tready <= not sts_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
-- updt_queue_empty <= ptr_queue_empty
-- or (sts_queue_empty and follower_empty and updt_active);
updt_queue_empty <= ptr_queue_empty
or follower_empty_mm2s; -- and updt_active);
-- Data queue read enable
ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr_queue_empty = '0' -- Data Queue NOT empty
and updt_active = '1'
else '0';
-- Status queue read enable
sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts_queue_empty = '0' -- Status fifo NOT empty
and updt_active = '1'
else '0';
-----------------------------------------------------------------------
-- TVALID - status queue not empty and writing status
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- TLAST - status queue not empty, writing status, and last asserted
-----------------------------------------------------------------------
-- Drive last as long as tvalid is asserted and last from fifo
-- is asserted
end generate MM2S_CHANNEL;
NO_MM2S_CHANNEL : if C_INCLUDE_MM2S = 0 generate
begin
updt_active_re1 <= '0';
updt_queue_empty <= '0';
s_axis_updtptr_tready <= '0';
s_axis_updtsts_tready <= '0';
sts_queue_dout <= (others => '0');
sts_queue_full <= '0';
sts_queue_empty <= '0';
ptr_queue_dout <= (others => '0');
ptr_queue_empty <= '0';
ptr_queue_full <= '0';
end generate NO_MM2S_CHANNEL;
S2MM_CHANNEL : if C_INCLUDE_S2MM = 1 generate
begin
updt2_tvalid <= follower_full_s2mm and updt2_active;
updt2_tlast <= follower_reg_s2mm(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt2_active;
sts2_rden <= follower_empty_s2mm and (not sts2_queue_empty); -- and updt2_active;
VALID_REG_S2MM_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_s2mm = '1' and follower_full_s2mm = '1'))then
-- follower_reg_s2mm <= (others => '0');
follower_full_s2mm <= '0';
follower_empty_s2mm <= '1';
else
if (sts2_rden = '1') then
-- follower_reg_s2mm <= sts2_queue_dout;
follower_full_s2mm <= '1';
follower_empty_s2mm <= '0';
end if;
end if;
end if;
end process VALID_REG_S2MM_ACTIVE;
VALID_REG_S2MM_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_s2mm <= (others => '0');
else
if (sts2_rden = '1') then
follower_reg_s2mm <= sts2_queue_dout;
end if;
end if;
end if;
end process VALID_REG_S2MM_ACTIVE1;
REG2_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d2 <= '0';
else
updt_active_d2 <= updt2_active;
end if;
end if;
end process REG2_ACTIVE;
updt_active_re2 <= updt2_active and not updt_active_d2;
-- I_UPDT2_DATA_FIFO : entity proc_common_v4_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 32 ,
-- C_DEPTH => 8 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => ptr2_queue_wren ,
-- Data_In => ptr2_queue_din ,
-- FIFO_Read => ptr2_queue_rden ,
-- Data_Out => ptr2_queue_dout ,
-- FIFO_Empty => ptr2_queue_empty ,
-- FIFO_Full => ptr2_queue_full,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
ptr2_queue_dout <= (others => '0');
elsif (ptr2_queue_wren = '1') then
ptr2_queue_dout <= ptr2_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or ptr2_queue_rden = '1') then
ptr2_queue_empty <= '1';
ptr2_queue_full <= '0';
elsif (ptr2_queue_wren = '1') then
ptr2_queue_empty <= '0';
ptr2_queue_full <= '1';
end if;
end if;
end process;
APP_UPDATE: if C_SG2_WORDS_TO_UPDATE /= 1 generate
begin
I_UPDT2_STS_FIFO : entity proc_common_v4_0.srl_fifo_f
generic map (
C_DWIDTH => 34 ,
C_DEPTH => 12 ,
C_FAMILY => C_FAMILY
)
port map (
Clk => m_axi_sg_aclk ,
Reset => sinit ,
FIFO_Write => sts2_queue_wren ,
Data_In => sts2_queue_din ,
FIFO_Read => sts2_rden,
Data_Out => sts2_queue_dout ,
FIFO_Empty => sts2_queue_empty ,
FIFO_Full => sts2_queue_full ,
Addr => open
);
end generate APP_UPDATE;
NO_APP_UPDATE: if C_SG2_WORDS_TO_UPDATE = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
sts2_queue_dout <= (others => '0');
elsif (sts2_queue_wren = '1') then
sts2_queue_dout <= sts2_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or sts2_rden = '1') then
sts2_queue_empty <= '1';
sts2_queue_full <= '0';
elsif (sts2_queue_wren = '1') then
sts2_queue_empty <= '0';
sts2_queue_full <= '1';
end if;
end if;
end process;
end generate NO_APP_UPDATE;
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr2_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis2_updtptr_tdata( -- DESC DATA
C_S_AXIS_UPDPTR_TDATA_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr2_queue_wren <= s_axis2_updtptr_tvalid -- TValid
and not ptr2_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis2_updtptr_tready <= not ptr2_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis2_updtsts_tlast; -- Store with tlast
sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis2_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts2_queue_wren <= s_axis2_updtsts_tvalid
and not sts2_queue_full;
-- Drive channel port with ready if room in status queue
s_axis2_updtsts_tready <= not sts2_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
updt2_queue_empty <= ptr2_queue_empty
or follower_empty_s2mm; --or (sts2_queue_empty and follower_empty and updt2_active);
-- Data queue read enable
ptr2_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr2_queue_empty = '0' -- Data Queue NOT empty
and updt2_active = '1'
else '0';
-- Status queue read enable
sts2_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts2_queue_empty = '0' -- Status fifo NOT empty
and updt2_active = '1'
else '0';
end generate S2MM_CHANNEL;
NO_S2MM_CHANNEL : if C_INCLUDE_S2MM = 0 generate
begin
updt_active_re2 <= '0';
updt2_queue_empty <= '0';
s_axis2_updtptr_tready <= '0';
s_axis2_updtsts_tready <= '0';
sts2_queue_dout <= (others => '0');
sts2_queue_full <= '0';
sts2_queue_empty <= '0';
ptr2_queue_dout <= (others => '0');
ptr2_queue_empty <= '0';
ptr2_queue_full <= '0';
end generate NO_S2MM_CHANNEL;
end generate GEN_Q_FOR_SYNC;
-- FIFO Reset is active high
sinit <= not m_axi_sg_aresetn;
-- LSB_PROC : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' )then
-- write_curdesc_lsb <= '0';
-- -- Capture lower pointer from FIFO or channel port
-- else -- if(write_curdesc_lsb = '1' and updt_active_int = '1')then
write_curdesc_lsb <= write_curdesc_lsb_sm;
-- end if;
-- end if;
-- end process LSB_PROC;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
ptr_queue_dout_int <= ptr2_queue_dout when (updt2_active = '1') else
ptr_queue_dout;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
updt_active_int <= updt_active or updt2_active;
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
updt_curdesc(31 downto 0) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1' and updt_active_int = '1')then
updt_curdesc(63 downto 32) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
--elsif(write_curdesc_msb = '1' and updt_active_int = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
-- updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT) and updt_active;
updt_ioc <= follower_reg_mm2s(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
--dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT) and updt_active;
dma_interr <= follower_reg_mm2s(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
-- dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT) and updt_active;
dma_slverr <= follower_reg_mm2s(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
-- dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT) and updt_active;
dma_decerr <= follower_reg_mm2s(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC2_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
-- updt2_ioc <= sts2_queue_dout(DESC_IOC_TAG_BIT) and updt2_active;
updt2_ioc <= follower_reg_s2mm(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC2_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_interr <= sts2_queue_dout(DESC_STS_INTERR_BIT) and updt2_active;
dma2_interr <= follower_reg_s2mm (DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT2_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_slverr <= sts2_queue_dout(DESC_STS_SLVERR_BIT) and updt2_active;
dma2_slverr <= follower_reg_s2mm(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV2_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_decerr <= sts2_queue_dout(DESC_STS_DECERR_BIT) and updt2_active;
dma2_decerr <= follower_reg_s2mm(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC2_ERROR;
end implementation;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ad
--
-- Generated
-- by: wig
-- on: Wed Nov 30 10:05:42 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ad-e.vhd,v 1.5 2005/11/30 14:04:18 wig Exp $
-- $Date: 2005/11/30 14:04:18 $
-- $Log: ent_ad-e.vhd,v $
-- Revision 1.5 2005/11/30 14:04:18 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_ad
--
entity ent_ad is
-- Generics:
-- No Generated Generics for Entity ent_ad
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_ad
port_ad_2 : out std_ulogic -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end ent_ad;
--
-- End of Generated Entity ent_ad
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
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