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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21696)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21696)
`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1681.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p09n01i01681ent IS
END c09s01b00x00p09n01i01681ent;
ARCHITECTURE c09s01b00x00p09n01i01681arch OF c09s01b00x00p09n01i01681ent IS
BEGIN
lab : block
begin
end block lab; -- labels match
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s01b00x00p09n01i01681"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s01b00x00p09n01i01681arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1681.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p09n01i01681ent IS
END c09s01b00x00p09n01i01681ent;
ARCHITECTURE c09s01b00x00p09n01i01681arch OF c09s01b00x00p09n01i01681ent IS
BEGIN
lab : block
begin
end block lab; -- labels match
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s01b00x00p09n01i01681"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s01b00x00p09n01i01681arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1681.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p09n01i01681ent IS
END c09s01b00x00p09n01i01681ent;
ARCHITECTURE c09s01b00x00p09n01i01681arch OF c09s01b00x00p09n01i01681ent IS
BEGIN
lab : block
begin
end block lab; -- labels match
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s01b00x00p09n01i01681"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s01b00x00p09n01i01681arch;
|
-------------------------------------------------------------------------------
--
-- T420/421 ROM.
--
-- $Id: t420_rom-e.vhd,v 1.1 2006-05-14 22:29:01 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t420_rom is
port (
ck_i : in std_logic;
addr_i : in std_logic_vector(9 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end t420_rom;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
--*****************************************************************************
-- @Copyright 2013 by SIAT_HFUS_TEAM, All rights reserved.
-- Module name : HUCB2P0_TOP
-- Call by :
-- Description : this module is the top module of HUCB2P0.
-- IC : 5CGXFC7D7F31C8N
-- Version : A
-- Note: :
-- Author : Peitian Mu
-- Date : 2013.09.12
-- Update :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
entity HUCB2P0_TOP is
port
(
I_reset : in std_logic; -- 复位，低有效--
I_ref_clk : in std_logic; -- 20M时钟
DDR3_A0 : out std_logic; -- not used
DDR3_A1 : out std_logic; -- not used
DDR3_A2 : out std_logic; -- not used
DDR3_A3 : out std_logic; -- not used
DDR3_A4 : out std_logic; -- not used
DDR3_A5 : out std_logic; -- not used
DDR3_A6 : out std_logic; -- not used
DDR3_A7 : out std_logic; -- not used
DDR3_A8 : out std_logic; -- not used
DDR3_A9 : out std_logic; -- not used
DDR3_A10 : out std_logic; -- not used
DDR3_A11 : out std_logic; -- not used
DDR3_A12 : out std_logic; -- not used
DDR3_A13 : out std_logic; -- not used
DDR3_D0 : inout std_logic; -- not used
DDR3_D1 : inout std_logic; -- not used
DDR3_D2 : inout std_logic; -- not used
DDR3_D3 : inout std_logic; -- not used
DDR3_D4 : inout std_logic; -- not used
DDR3_D5 : inout std_logic; -- not used
DDR3_D6 : inout std_logic; -- not used
DDR3_D7 : inout std_logic; -- not used
DDR3_D8 : inout std_logic; -- not used
DDR3_D9 : inout std_logic; -- not used
DDR3_D10 : inout std_logic; -- not used
DDR3_D11 : inout std_logic; -- not used
DDR3_D12 : inout std_logic; -- not used
DDR3_D13 : inout std_logic; -- not used
DDR3_D14 : inout std_logic; -- not used
DDR3_D15 : inout std_logic; -- not used
DDR3_BA0 : out std_logic; -- not used
DDR3_BA1 : out std_logic; -- not used
DDR3_BA2 : out std_logic; -- not used
DDR3_CAS : out std_logic_vector(0 downto 0); -- not used
DDR3_RAS : out std_logic_vector(0 downto 0); -- not used
DDR3_WE : out std_logic_vector(0 downto 0); -- not used
DDR3_CLK : out std_logic_vector(0 downto 0); -- not used
DDR3_CLK_n : out std_logic_vector(0 downto 0); -- not used
DDR3_DQS0 : inout std_logic; --not used
DDR3_DQS0_n : inout std_logic; --not used
DDR3_DQS1 : inout std_logic; --not used
DDR3_DQS1_n : inout std_logic; --not used
DDR3_ODT : out std_logic_vector(0 downto 0); --not used
DDR3_DML : out std_logic; --not used
DDR3_CKE : out std_logic_vector(0 downto 0); --not used
DDR3_DMU : out std_logic; --not used
DDR3_CS : out std_logic_vector(0 downto 0); --not used
DDR3_RST : out std_logic; --not used
--ADC ADS58C48
O_adca_sen : out std_logic; -- 此ADC未使用
I_adca_sd : in std_logic;
O_adca_sdata : out std_logic;
O_adca_sclk : out std_logic;
O_adca_rst : out std_logic;
O_adca_pdn : out std_logic;
O_adca_snrb0 : out std_logic;
O_adca_snrb1 : out std_logic;
I_adca_oclk : in std_logic;
I_adca_d : in std_logic_vector(5 downto 0);
I_adcb_d : in std_logic_vector(5 downto 0);
I_adcc_d : in std_logic_vector(5 downto 0);
I_adcd_d : in std_logic_vector(5 downto 0);
--ADC AD9634
I_adce_clk : in std_logic; -- 此ADC未使用
I_adce_d : in std_logic_vector(5 downto 0);
I_adce_or : in std_logic;
O_adce_csb : out std_logic;
O_adce_sdio : out std_logic;
O_adce_sclk : out std_logic;
--ADC AD9230
I_adcf_clk : in std_logic; -- 此ADC用于本项目数据采集 --240M
I_adcf_d : in std_logic_vector(11 downto 0);
I_adcf_or : in std_logic;
O_adcf_pwdn : out std_logic;
O_adcf_csb : out std_logic;
O_adcf_sclk : out std_logic;
O_adcf_sdio : out std_logic;
O_adcf_reset : out std_logic;
--ADC AD9235
I_m_adc_d : in std_logic_vector(11 downto 0); -- 此ADC未使用
O_m_adc_clk : out std_logic;
I_m_adc_otr : in std_logic;
O_m_adc_pdwn : out std_logic;
O_pulse : out std_logic_vector(3 downto 0); -- 未使用
O_pulse_0pd : out std_logic; -- 未使用
O_pulse_1pd : out std_logic; -- 未使用
O_pulse_2pd : out std_logic; -- 未使用
O_pulse_3pd : out std_logic; -- 未使用
O_8220pulse : out std_logic_vector(3 downto 0); -- 发射通道
O_8020islpulse : out std_logic_vector(3 downto 0); -- 未使用
O_8020mdpulse : out std_logic_vector(7 downto 0); -- 未使用
----------pll configuration
O_pll_rst : out std_logic; -- 此PLL用于ADC时钟配置，使用方法可参考AD9518的datasheet。
O_pll_sync : out std_logic;
O_pll_sdio : out std_logic;
O_pll_pd : out std_logic;
O_pll_cs : out std_logic;
O_pll_sclk : out std_logic;
I_pll_refmon : in std_logic; --not used
I_pll_ld : in std_logic; --not used
I_pll_status : in std_logic; --not used
I_pll_sdo : in std_logic; --not used
I_iotrig : in std_logic; -- X10 I/O -- not used
I_ioenable : in std_logic; -- X2 I/O -- not used
BEEP : in std_logic; -- 蜂鸣器未使用 -- not used
DA_SYNC : out std_logic; -- AD5300，是ADI公司的DAC，用于输出sine给功放驱动电磁铁。
DA_SCLK : out std_logic; -- AD5300
DA_DIN : out std_logic; -- AD5300
FPGA_IO0 : in std_logic; -- 未使用 --not used
FPGA_IO1 : in std_logic; -- 未使用 --not used
SRAM_WE : in std_logic; -- 未使用 --not used
SRAM_OE : in std_logic; --not used
SRAM_CLK : in std_logic; --not used
SRAM_ADV : in std_logic; --not used
SRAM_CRE : in std_logic; --not used
SRAM_LB : in std_logic; --not used
SRAM_UB : in std_logic; --not used
O_swi_dir : out std_logic; -- 电压转换芯片74LVC4245APW
O_swi_oe : out std_logic; -- 电压转换芯片74LVC4245APW
I_swi0 : in std_logic; --not used
I_swi1 : in std_logic; --not used
I_swi2 : in std_logic; --not used
I_swi3 : in std_logic; --not used
I_swi4 : in std_logic; --not used
PCIE_SMCLK : in std_logic; --not used
PCIE_SMDAT : in std_logic; --not used
PCIE_WAKE : in std_logic; --not used
PCIE_PERST : in std_logic; --not used
DAC_SLEEP : in std_logic; --not used
DAC_GD0 : in std_logic; --not used
DAC_GD1 : in std_logic; --not used
DAC_GD2 : in std_logic; --not used
DAC_GD3 : in std_logic; --not used
DAC_GD4 : in std_logic; --not used
DAC_GD5 : in std_logic; --not used
DAC_GD6 : in std_logic; --not used
DAC_GD7 : in std_logic; --not used
SRAM_D0 : in std_logic; --not used
SRAM_D1 : in std_logic; --not used
SRAM_D2 : in std_logic; --not used
SRAM_D3 : in std_logic; --not used
SRAM_D4 : in std_logic; --not used
SRAM_D5 : in std_logic; --not used
SRAM_D6 : in std_logic; --not used
SRAM_D7 : in std_logic; --not used
SRAM_D8 : in std_logic; --not used
SRAM_D9 : in std_logic; --not used
SRAM_D10 : in std_logic; --not used
SRAM_D11 : in std_logic; --not used
SRAM_D12 : in std_logic; --not used
SRAM_D13 : in std_logic; --not used
SRAM_D14 : in std_logic; --not used
SRAM_D15 : in std_logic; --not used
SRAM_A0 : in std_logic; --not used
SRAM_A1 : in std_logic; --not used
SRAM_A2 : in std_logic; --not used
SRAM_A3 : in std_logic; --not used
SRAM_A4 : in std_logic; --not used
SRAM_A5 : in std_logic; --not used
SRAM_A6 : in std_logic; --not used
SRAM_A7 : in std_logic; --not used
SRAM_A8 : in std_logic; --not used
SRAM_A9 : in std_logic; --not used
SRAM_A10 : in std_logic; --not used
SRAM_A11 : in std_logic; --not used
SRAM_A12 : in std_logic; --not used
SRAM_A13 : in std_logic; --not used
SRAM_A14 : in std_logic; --not used
SRAM_A15 : in std_logic; --not used
SRAM_A16 : in std_logic; --not used
SRAM_A17 : in std_logic; --not used
SRAM_A18 : in std_logic; --not used
SRAM_A19 : in std_logic; --not used
SRAM_A20 : in std_logic; --not used
SRAM_A21 : in std_logic; --not used
SRAM_WAIT : in std_logic; --not used
SRAM_CE : in std_logic; --not used
----------USB
O_usb_pclk : out std_logic; --CTL[0] SLCS#
--CTL[1] SLWR#
I_usb_flga : in std_logic := '0'; --CTL[2] SLOE#
I_usb_flgb : in std_logic := '0'; --CTL[3] SLRD#
--CTL[4] FLAGA
O_usb_cs : out std_logic; --CTL[5] FLAGB
O_usb_wr : out std_logic; --CTL[7] PKTEND#
O_usb_rd : out std_logic; --CTL[11] A1
O_usb_oe : out std_logic; --CTL[12] A0
O_usb_a0 : out std_logic;
O_usb_a1 : out std_logic;
O_usb_pkt : out std_logic;
O_usb_int : out std_logic;
O_usb_reset : out std_logic;
IO_usb_dq : inout std_logic_vector(31 downto 0);
O_usb_uart_rxd : out std_logic;
I_usb_uart_rts : in std_logic; --not used
I_usb_uart_txd : in std_logic;
O_usb_uart_cts : out std_logic; --not used
----------USB unused
USB_CTL6 : in std_logic; --not used
USB_CTL8 : in std_logic; --not used
USB_CTL9 : in std_logic; --not used
USB_CTL10 : in std_logic; --not used
O_usb_clk : out std_logic;
O_usb_i2s : out std_logic_vector(3 downto 0); --not used
O_usb_gpio : out std_logic_vector(5 downto 0); --not used
-- PCIE_RX_0 : in std_logic;
-- PCIE_RX_1 : in std_logic;
-- PCIE_RX_2 : in std_logic;
-- PCIE_RX_3 : in std_logic;
-- PCIE_TX_0 : out std_logic;
-- PCIE_TX_1 : out std_logic;
-- PCIE_TX_2 : out std_logic;
-- PCIE_TX_3 : out std_logic;
-- PCIE_RCLK : in std_logic;
USB_CLKIN : in std_logic; --not used
-- FPGA_CLK : in std_logic;--LVDS
DAC_GCLK : in std_logic; -- 未使用 --not used
KEYIN0 : in std_logic; -- button
O_led : out std_logic_vector(3 downto 0) -- LED
);
end HUCB2P0_TOP;
architecture arc_HUCB2P0_TOP of HUCB2P0_TOP is
component pll_conf -- PLL AD9518
port
(
I_clk : in std_logic;
I_reset_n : in std_logic;
O_ADC_ready : out std_logic;
O_FPGA_ADC_d : out std_logic;
O_FPGA_ADC_clk : out std_logic;
O_FPGA_ADC_en : out std_logic;
O_FPGA_ADC_reset : out std_logic
);
end component;
component LED_HANDLE -- 未使用
port
(
I_26M_clk : in std_logic;
I_reset_n : in std_logic;
I_led_dis : in std_logic_vector(3 downto 0);
I_adc_dis : in std_logic;
I_fifo_full : in std_logic;
O_fpga_led0 : out std_logic;
O_fpga_led1 : out std_logic;
O_fpga_led2 : out std_logic;
O_fpga_led3 : out std_logic
);
end component;
component frontend -- 重要，数据采集时序。
port
(
I_reset_n : in std_logic;
I_sys_clk : in std_logic;
I_scan_trig : in std_logic; --scan triger
I_reg_csr : in std_logic_vector(31 downto 0);
--ADC
I_adc_d : in std_logic_vector(11 downto 0);
I_adc_or : in std_logic;
I_f2pc_full : in std_logic;
O_pixel_symbol : out std_logic;
O_pixel_en : out std_logic;
O_pixel_data : out std_logic_vector(15 downto 0);
O_pulse_trig : out std_logic;
O_shake_start : out std_logic
);
end component;
component Interface -- 采集时序和USB3.0时序之间的连接
port
(
I_reset_n : in std_logic;
I_sys_clk : in std_logic;
--work control
O_register : out std_logic_vector(31 downto 0);
--image data output
I_data_en : in std_logic;
I_data_symbol : in std_logic;
I_data : in std_logic_vector(15 downto 0);
---usb FIFO
O_wfifo_reset : out std_logic;
O_usb_wrreq : out std_logic;
O_usb_din : out std_logic_vector(15 downto 0);
O_usb_rdreq : out std_logic;
I_usb_dout : in std_logic_vector(31 downto 0);
I_usb_rdempty : in std_logic
);
end component;
component usb_121pll -- USB逻辑时钟倍频 20->60
port
(
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic; -- outclk0.clk
outclk_1 : out std_logic; -- outclk0.clk
locked : out std_logic -- locked.export
);
end component;
component adc_pll -- ADC时钟分频，240->60
port
(
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic; -- outclk0.clk
outclk_1 : out std_logic -- locked.export
);
end component;
component pulse -- 超声发射
port
(
I_clk : in std_logic;
I_reset_n : in std_logic;
I_pulse_trig : in std_logic;
O_pulse : out std_logic_vector(3 downto 0)
);
end component;
component AD9634 -- 未使用
port
(
I_adce_clk : in std_logic;
I_adce_d : in std_logic_vector(5 downto 0);
I_adce_or : in std_logic;--LVDS
O_adce_csb : out std_logic;
O_adce_sdio : out std_logic;
O_adce_sclk : out std_logic;
O_adce_data : out std_logic_vector(11 downto 0)
);
end component;
component AD9235 -- 未使用
port
(
I_m_adc_d : in std_logic_vector(11 downto 0);
O_m_adc_clk : out std_logic;
I_m_adc_otr : in std_logic;
O_m_adc_pdwn : out std_logic
);
end component;
component ADS58C48 -- 未使用
port
(
O_adca_sen : out std_logic;
I_adca_sd : in std_logic;
O_adca_sdata : out std_logic;
O_adca_sclk : out std_logic;
O_adca_rst : out std_logic;
O_adca_pdn : out std_logic;
O_adca_snrb0 : out std_logic;
O_adca_snrb1 : out std_logic;
I_adca_oclk : in std_logic;
I_adca_d : in std_logic_vector(5 downto 0);
I_adcb_d : in std_logic_vector(5 downto 0);
I_adcc_d : in std_logic_vector(5 downto 0);
I_adcd_d : in std_logic_vector(5 downto 0);
O_adca_data : out std_logic_vector(11 downto 0);
O_adcb_data : out std_logic_vector(11 downto 0);
O_adcc_data : out std_logic_vector(11 downto 0);
O_adcd_data : out std_logic_vector(11 downto 0)
);
end component;
component p2s_dac -- AD5300，DAC时序，串行控制。
port(
a,clk,clr : in std_logic;
datain1 : in std_logic_vector(15 downto 0);
ld,s_data : out std_logic);
end component;
component sine_rom -- 正弦波查找表
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END component;
COMPONENT usb_top -- 新版本USB3.0时序，对用户来说就是操作FIFO。
PORT
(
I_sys_clk : IN STD_LOGIC := '1';
I_usb_clk : IN STD_LOGIC;
I_sys_rst : IN STD_LOGIC ;
I_usb_rst : IN STD_LOGIC;
I_usb_wfifo_aclr : IN STD_LOGIC;
I_usb_wrreq : IN STD_LOGIC;
I_usb_din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
O_usb_wrfull : OUT STD_LOGIC;
O_usb_wruesdw : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
I_usb_rdreq : IN STD_LOGIC;
O_usb_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
O_usb_rdempty : OUT STD_LOGIC;
I_usb_uart_tx_req : IN STD_LOGIC;
I_usb_uart_tx_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
O_usb_uart_tx_full : OUT STD_LOGIC;
I_usb_uart_rx_req : IN STD_LOGIC;
O_usb_uart_rx_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
O_usb_uart_rx_empty : OUT STD_LOGIC;
O_usb_pclk : OUT STD_LOGIC;
O_usb_clk : OUT STD_LOGIC;
I_usb_flga : IN STD_LOGIC;
I_usb_flgb : IN STD_LOGIC;
O_usb_cs : OUT STD_LOGIC;
O_usb_wr : OUT STD_LOGIC;
O_usb_rd : OUT STD_LOGIC;
O_usb_oe : OUT STD_LOGIC;
O_usb_a0 : OUT STD_LOGIC;
O_usb_a1 : OUT STD_LOGIC;
O_usb_pkt : OUT STD_LOGIC;
O_usb_reset : OUT STD_LOGIC;
IO_usb_dq : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
O_usb_uart_txd : OUT STD_LOGIC;
I_usb_uart_rxd : IN STD_LOGIC;
I_usb_dir : IN STD_LOGIC
);
END COMPONENT;
COMPONENT register_ctrl_top -- USB桥接芯片的串口通信部分，主要功能是接收上位机控制命令。
PORT
(
I_sys_clk : IN STD_LOGIC := '1';
I_sys_rst : IN STD_LOGIC := '1';
O_usb_uart_tx_req : OUT STD_LOGIC;
O_usb_uart_tx_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
I_usb_uart_tx_full : IN STD_LOGIC := '0';
O_usb_uart_rx_req : OUT STD_LOGIC;
I_usb_uart_rx_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
I_usb_uart_rx_empty : IN STD_LOGIC := '0';
O_usb_dir : OUT STD_LOGIC;
O_motor_start : OUT STD_LOGIC;
tp : OUT STD_LOGIC;
I_key_start : IN STD_LOGIC := '1'
);
END COMPONENT;
signal S_usb_wrfull : std_logic:= '0';
signal S_pulse : std_logic_vector (3 downto 0);
signal s_trig_pulse : std_logic;
constant c_speed_test : integer := 40000;
signal s_reset : std_logic := '0';
signal s_scan_trig : std_logic;
signal s_scan_trig_buf : std_logic;
signal s_pll_reset : std_logic;
signal S_pll_ready : std_logic;
signal S_usb_wrreq : std_logic;
signal S_usb_din : std_logic_vector(15 downto 0);
signal S_usb_wrusedw : std_logic_vector(15 downto 0):="0000000000000000";
signal S_usb_rdreq : std_logic;
signal S_usb_dout : std_logic_vector(31 downto 0);
signal S_usb_rdempty : std_logic;
signal S_usb_rdusedw : std_logic_vector(4 downto 0);
------------usb write state-------------
signal S_usb_wr_state : std_logic_vector(1 downto 0);
signal S_usb_wr_cnt : std_logic_vector(9 downto 0);
------------usb read state--------------
signal S_usb_pulse_state: std_logic_vector(1 downto 0);
signal s_usb_clk : std_logic;
signal s_pll_locked : std_logic;
-------constant for reset and logic judgement------------------
constant C_RST_ON : std_logic := '0'; --reset signal the system is low reset
constant C_ACT_ON : std_logic := '1'; --logic judgement signal
constant C_ACT_OFF : std_logic := '0';
signal S_case_test : std_logic_vector(1 downto 0);
signal S_case_work : std_logic_vector(1 downto 0);
signal S_ad_buf : std_logic_vector(11 downto 0);
signal S_ad_1buf : std_logic_vector(15 downto 0);
signal S_register : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal s_test_cn : std_logic_vector(19 downto 0);
signal s_work_cn : std_logic_vector(19 downto 0);
signal s_line_no : std_logic_vector(15 downto 0);
signal s_line_comb : std_logic_vector(15 downto 0);
signal s_pixel_data : std_logic_vector(15 downto 0);
signal S_pixel_symbol : std_logic;
signal S_pixel_en : std_logic;
signal s_sys_clk : std_logic;
signal s_sys_reset : std_logic;
signal s_pll_lock : std_logic;
signal S_pulse_trig : std_logic;
signal S_swi4 : std_logic;
signal S_key_start_dcnt : std_logic_vector (15 downto 0):="0000000000000000";
signal S_key_start_dclk : std_logic;
signal S_adce_data : std_logic_vector(11 downto 0);
signal S_adca_data : std_logic_vector(11 downto 0);
signal S_adcb_data : std_logic_vector(11 downto 0);
signal S_adcc_data : std_logic_vector(11 downto 0);
signal S_adcd_data : std_logic_vector(11 downto 0);
signal s_clk_60m : std_logic;
signal s_clk_60m_st : std_logic;
signal S_DA_SYNC : std_logic;
signal S_DA_cnt : std_logic_vector(4 downto 0):="00000";
signal S_DA_a : std_logic;
signal S_DA_addr : std_logic_vector(7 downto 0);
signal S_DA_rom_q : std_logic_vector(7 downto 0);
signal S_KEYIN0 : std_logic;
signal S_clk_4883_cnt : std_logic_vector(7 downto 0);
signal S_clk_4883 : std_logic:='0';
signal S_key0_cnt : std_logic_vector(24 downto 0);
signal S_key0_dclk : std_logic;
signal S_usb_uart_tx_req : std_logic;
signal S_usb_uart_tx_data : std_logic_vector(7 downto 0);
signal S_usb_uart_tx_full : std_logic;
signal S_usb_uart_rx_req : std_logic;
signal S_usb_uart_rx_data : std_logic_vector(7 downto 0);
signal S_usb_uart_rx_empty : std_logic;
signal S_usb_dir : std_logic;
signal S_motor_start : std_logic;
signal s_usb_clk_180 : std_logic;
signal S_motor_start_delay : std_logic;
signal S_shake_start : std_logic:='0';
signal S_key_start_temp1 : std_logic;
signal S_key_start_temp2 : std_logic;
signal S_key_start : std_logic;
begin
--s_sys_clk <= I_adcf_clk;
O_pll_pd <= '1'; --Chip Power Down, Active Low
O_pll_sync <= '1'; --Manual Synchronizations and Manual Holdover, Active Low
O_pll_rst <= not s_pll_reset;
O_adcf_pwdn <= '0';
O_adcf_csb <= '1';
O_adcf_sclk <= '1';
O_adcf_sdio <= '1';
O_adcf_reset <= '1';
--------------------------------
--pulse
--------------------------------
--O_pulse_0pd <= '0'; --1 power down
--O_pulse_1pd <= '0';
--O_pulse_2pd <= '0';
--O_pulse_3pd <= '0';
--O_pulse <= S_pulse;
--O_8020islpulse <= S_pulse;
--O_8020mdpulse(7 downto 6) <= S_pulse(1 downto 0);
O_8220pulse(3 downto 0) <= S_pulse(3 downto 0);
U0 : pll_conf -- 用于片外PLL配置ADC时钟，也可以不看。
port map
(
I_clk => I_ref_clk, --20M
I_reset_n => s_pll_lock ,
O_ADC_ready => S_pll_ready,
O_FPGA_ADC_d => O_pll_sdio,
O_FPGA_ADC_clk => O_pll_sclk,
O_FPGA_ADC_en => O_pll_cs,
O_FPGA_ADC_reset => s_pll_reset
);
U1_LED_HANDLE : LED_HANDLE
port map
(
I_26M_clk => I_ref_clk ,
I_reset_n => s_pll_lock ,
I_led_dis => "0100" ,
I_adc_dis => '0' ,
I_fifo_full => S_usb_wrfull ,
O_fpga_led0 => open,--O_led(0) ,
O_fpga_led1 => open,--O_led(1) ,
O_fpga_led2 => open,--O_led(2) ,
O_fpga_led3 => open--O_led(3)
);
U0_pulse : pulse -- 5M发射，60M时钟，类似于分频实现，可参考TC8220的发射时序。
port map
(
I_clk => s_clk_60m,--s_sys_clk,
I_reset_n => s_pll_lock,
I_pulse_trig => S_pulse_trig,--s_trig_pulse,
O_pulse => S_pulse
);
--------------------------------
--pulse
--------------------------------
O_pulse_0pd <= '0'; --1 power down
O_pulse_1pd <= '0';
O_pulse_2pd <= '1';
O_pulse_3pd <= '1';
s_sys_reset <= not I_reset;
U4_usb_pll : usb_121pll -- USB逻辑时钟
port map
(
refclk => I_ref_clk, --20M--
rst => s_sys_reset,
outclk_0 => s_usb_clk, --60M--
outclk_1 => s_usb_clk_180, --60M--
locked => s_pll_lock ----
);
U5_adc_pll : adc_pll -- ADC随路时钟分频得到的60M，用于数据采集。
port map
(
refclk => I_adcf_clk, --240M
rst => s_sys_reset,
outclk_0 => s_clk_60m,
outclk_1 => s_clk_60m_st
);
U0_frontend : frontend -- 重要，数据采集时序。
port map
(
I_reset_n => s_pll_lock ,
I_sys_clk => s_clk_60m ,
I_scan_trig => S_motor_start_delay, --motor start--
I_reg_csr => s_register, -- not used --
--ADC
I_adc_d => I_adcf_d,
I_adc_or => I_adcf_or ,
I_f2pc_full => S_usb_wrfull , --not used--
O_pixel_symbol => S_pixel_symbol, --receive valid--
O_pixel_en => S_pixel_en, --18000 period valid --
O_pixel_data => S_pixel_data, --receive data --
O_pulse_trig => S_pulse_trig, --trans valid --
O_shake_start => S_shake_start -- shake valid --
);
U4_interface : Interface -- 采集时序和USB3.0时序之间的连接
port map
(
I_reset_n => s_pll_lock,
I_sys_clk => s_clk_60m,
--work control
O_register => s_register, -- output not used--
--image data output
I_data_en => S_pixel_en, --18000 period valid--
I_data_symbol => S_pixel_symbol, --receive valid--
I_data => S_pixel_data, --receive data --
---usb FIFO
O_wfifo_reset => s_reset, --output for usb_top--
O_usb_wrreq => S_usb_wrreq, --output for usb_top--
O_usb_din => S_usb_din, --output for usb_top--
O_usb_rdreq => S_usb_rdreq, --output for usb_top--
I_usb_dout => S_usb_dout, --input from usb_top--
I_usb_rdempty => S_usb_rdempty --input from usb_top--
);
U33_usbcore : usb_top -- USB3.0
port map
(
I_sys_clk => s_clk_60m, --60M--
I_usb_clk => s_usb_clk, --60M--
I_sys_rst => not s_pll_lock,
I_usb_rst => not s_pll_lock,
I_usb_wfifo_aclr => s_reset, --input
I_usb_wrreq => S_usb_wrreq, --input
I_usb_din => S_usb_din, --input
O_usb_wrfull => S_usb_wrfull, --output-- not used--
O_usb_wruesdw => S_usb_wrusedw, --output-- not used--
I_usb_rdreq => S_usb_rdreq, --input--
O_usb_dout => S_usb_dout, --output--
O_usb_rdempty => S_usb_rdempty, --output--
I_usb_uart_tx_req => S_usb_uart_tx_req, --input--
I_usb_uart_tx_data => S_usb_uart_tx_data,--input--
O_usb_uart_tx_full => S_usb_uart_tx_full,--output--
I_usb_uart_rx_req => S_usb_uart_rx_req, --input--
O_usb_uart_rx_data => S_usb_uart_rx_data,--output--
O_usb_uart_rx_empty => S_usb_uart_rx_empty,--output--
O_usb_pclk => open, --O_usb_pclk,
O_usb_clk => open,
I_usb_flga => I_usb_flga, --input--
I_usb_flgb => I_usb_flgb, --input--
O_usb_cs => O_usb_cs, --output--
O_usb_wr => O_usb_wr, --output--
O_usb_rd => O_usb_rd, --output--
O_usb_oe => O_usb_oe, --output--
O_usb_a0 => O_usb_a0, --output--
O_usb_a1 => O_usb_a1, --output--
O_usb_pkt => O_usb_pkt, --output-- not used --
O_usb_reset => O_usb_reset, --output-- not used--
IO_usb_dq => IO_usb_dq, --inout--
O_usb_uart_txd => O_usb_uart_rxd, --output--
I_usb_uart_rxd => I_usb_uart_txd, --input--
I_usb_dir => S_usb_dir --input--
);
O_usb_pclk <= s_usb_clk_180;
U44_register_ctrl_top : register_ctrl_top
port map
(
I_sys_clk => s_clk_60m,
I_sys_rst => not s_pll_lock,
O_usb_uart_tx_req => S_usb_uart_tx_req,
O_usb_uart_tx_data => S_usb_uart_tx_data,
I_usb_uart_tx_full => S_usb_uart_tx_full,
O_usb_uart_rx_req => S_usb_uart_rx_req,
I_usb_uart_rx_data => S_usb_uart_rx_data,
I_usb_uart_rx_empty => S_usb_uart_rx_empty,
O_usb_dir => S_usb_dir,
O_motor_start => S_motor_start,
tp => open,
I_key_start => S_key_start
);
U5_AD9634 : AD9634 -- 未使用
port map
(
I_adce_clk => I_adce_clk,
I_adce_d => I_adce_d,
I_adce_or => I_adce_or,
O_adce_csb => O_adce_csb,
O_adce_sdio => O_adce_sdio,
O_adce_sclk => O_adce_sclk,
O_adce_data => S_adce_data
);
U6_AD9235 : AD9235 -- 未使用
port map
(
I_m_adc_d => I_m_adc_d,
O_m_adc_clk => O_m_adc_clk,
I_m_adc_otr => I_m_adc_otr,
O_m_adc_pdwn => O_m_adc_pdwn
);
U7_ADS58C48 : ADS58C48 -- 未使用
port map
(
O_adca_sen => O_adca_sen,
I_adca_sd => I_adca_sd,
O_adca_sdata => O_adca_sdata,
O_adca_sclk => O_adca_sclk,
O_adca_rst => O_adca_rst,
O_adca_pdn => O_adca_pdn,
O_adca_snrb0 => O_adca_snrb0,
O_adca_snrb1 => O_adca_snrb1,
I_adca_oclk => I_adca_oclk,
I_adca_d => I_adca_d,
I_adcb_d => I_adcb_d,
I_adcc_d => I_adcc_d,
I_adcd_d => I_adcd_d,
O_adca_data => S_adca_data,
O_adcb_data => S_adcb_data,
O_adcc_data => S_adcc_data,
O_adcd_data => S_adcd_data
);
U8_p2s_dac : p2s_dac -- AD5300，DAC时序，串行控制。
port map(
a => S_DA_a,
clk => S_clk_4883,
clr => not s_pll_lock,
datain1 => "0000000" & S_DA_rom_q(7 downto 3) & "0000",
ld => S_DA_SYNC,
s_data => DA_DIN);
DA_SYNC <= not S_DA_SYNC;
DA_SCLK <= not S_clk_4883;
process(I_ref_clk, s_pll_lock) -- 20M时钟分频，最终实现100Hz正弦，20M/128（查找表）/32（串行数据长度）/100（设计频率）=48
begin
if s_pll_lock = '0' then
S_clk_4883_cnt <= (others=>'0');
S_clk_4883 <= '0';
elsif rising_edge(I_ref_clk) then
if (S_clk_4883_cnt /= 24)then -- 24翻转一次电平，实现48分频。
S_clk_4883_cnt <= S_clk_4883_cnt + 1;
else
S_clk_4883 <= not S_clk_4883;
S_clk_4883_cnt <= (others=>'0');
end if;
end if;
end process;
process(S_clk_4883)
begin
if rising_edge(S_clk_4883) then -- 分频后的时钟用作串行时钟，此处生成16个高电平用于串行DAC时序。
S_DA_cnt <= S_DA_cnt + 1;
if S_DA_cnt >= "00001" and S_DA_cnt <= "10001" then
S_DA_a <= '1'; --valid--
else
S_DA_a <= '0';
end if;
end if;
end process;
O_led(0) <= S_motor_start_delay; -- 软件界面点开始之后，灯会灭一下，其他时间常亮，用于工作指示
O_led(1) <= S_motor_start_delay;
O_led(2) <= S_motor_start_delay;
O_led(3) <= S_motor_start_delay;
process(s_clk_60m_st, s_pll_lock,S_motor_start) -- 将上位机通过USB串口发送的开始信号的边沿转变成持续一段时间的电平，作为采集时序的开始使能。
begin
if s_pll_lock = '0' then
S_key0_cnt <= (others=>'0');
elsif rising_edge(s_clk_60m_st) then
if(S_motor_start='1') then
S_motor_start_delay <= '1';
S_key0_cnt <= "0000000000000000000000001";
elsif((S_key0_cnt>"0000000000000000000000000") and (S_key0_cnt<"1000000000000000000000000")) then
S_key0_cnt <= S_key0_cnt + 1;
else
S_motor_start_delay <= '0';
S_key0_cnt <= "0000000000000000000000000"; -- dian deng !--
end if;
end if;
end process;
process(S_DA_a,S_shake_start)--,s_register)--S_KEYIN0)
begin
-- if s_register(0) = '1' then
if S_shake_start = '0' then
S_DA_addr <= "00000000";
elsif rising_edge(S_DA_a) then -- 每发射一组串行数据，地址+1，直到128完成一次正弦波查找表。
S_DA_addr <= S_DA_addr + 1;
if S_DA_addr > "01111111" then
S_DA_addr <= "10000000";
end if;
end if;
-- else
-- S_DA_addr <= "00000000";
-- end if;
end process;
U9_sine_rom : sine_rom -- 正弦波查找表
PORT map
(
address => S_DA_addr(6 downto 0),
clock => S_DA_a,
q => S_DA_rom_q
);
O_swi_dir <= '1'; -- 电压转换芯片的方向
O_swi_oe <= '0'; -- 电压转换芯片的使能
process(I_ref_clk, s_pll_lock)
begin
if s_pll_lock = '0' then
S_key_start_dcnt <= (others=>'0');
S_key_start_dclk <= '0';
elsif rising_edge(I_ref_clk) then
S_key_start_dcnt <= S_key_start_dcnt + 1;
if (S_key_start_dcnt = 0)then
S_key_start_dclk <= not S_key_start_dclk; -- 20*10^6/2^16/2 clk period --
end if;
end if;
end process;
process(S_key_start_dclk)
begin
if rising_edge(S_key_start_dclk) then
S_key_start_temp1 <= KEYIN0;
end if;
end process;
process(s_clk_60m,S_key_start_temp1)
begin
if rising_edge(s_clk_60m) then
S_key_start_temp2 <= S_key_start_temp1;
if S_key_start_temp2 = '0' and S_key_start_temp1 = '1' then --rise--
S_key_start <= '1';
else
S_key_start <= '0';
end if;
end if;
end process;
end arc_HUCB2P0_TOP;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\Program_Counter.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Program_Counter
-- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit/Program Counter
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Program_Counter IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
func : IN std_logic_vector(1 DOWNTO 0); -- ufix2
addr_in : IN std_logic_vector(7 DOWNTO 0); -- uint8
addr_out : OUT std_logic_vector(7 DOWNTO 0) -- uint8
);
END Program_Counter;
ARCHITECTURE rtl OF Program_Counter IS
-- Signals
SIGNAL func_unsigned : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL addr_in_unsigned : unsigned(7 DOWNTO 0); -- uint8
SIGNAL addr_out_tmp : unsigned(7 DOWNTO 0); -- uint8
SIGNAL PC_value : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL PC_value_next : unsigned(7 DOWNTO 0); -- ufix8
BEGIN
func_unsigned <= unsigned(func);
addr_in_unsigned <= unsigned(addr_in);
Program_Counter_1_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
PC_value <= to_unsigned(2#00000000#, 8);
ELSIF enb = '1' THEN
PC_value <= PC_value_next;
END IF;
END IF;
END PROCESS Program_Counter_1_process;
Program_Counter_1_output : PROCESS (func_unsigned, addr_in_unsigned, PC_value)
BEGIN
PC_value_next <= PC_value;
--MATLAB Function 'CPU_Subsystem_8_bit/Program Counter': '<S10>:1'
-- Program Counter
-- func = 0 => reset PC
-- func = 1 => load PC
-- func = 2 => increment PC
-- HDL specific fimath
--'<S10>:1:20'
addr_out_tmp <= PC_value;
CASE func_unsigned IS
WHEN "00" =>
-- reset
--'<S10>:1:25'
PC_value_next <= to_unsigned(2#00000000#, 8);
WHEN "01" =>
-- store into PC
--'<S10>:1:28'
PC_value_next <= addr_in_unsigned;
WHEN "10" =>
-- increment PC
--'<S10>:1:31'
PC_value_next <= PC_value + 1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS Program_Counter_1_output;
addr_out <= std_logic_vector(addr_out_tmp);
END rtl;
|
-- #################################################################################################
-- # << NEO430 - Watchdog Timer >> #
-- # ********************************************************************************************* #
-- # The internal counter is 16 bit wide and triggers a HW reset when overflowing. The clock is #
-- # selected via the clk_sel bits of the control register. The WDT can only operate when the #
-- # enable bit is set. A write access to the WDT can only be performed, if the higher byte of the #
-- # written data contains the specific WDT password (0x47). I a write access occurs with a wrong #
-- # password, a HW reset is triggered, but only if the WDT is enabled. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_wdt is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- external reset, low-active, use as async
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- system reset --
rst_o : out std_ulogic -- timeout reset, low_active, use it as async!
);
end neo430_wdt;
architecture neo430_wdt_rtl of neo430_wdt is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(wdt_size_c); -- low address boundary bit
-- Watchdog access password - do not change! --
constant wdt_password_c : std_ulogic_vector(07 downto 0) := x"47";
-- Control register bits --
constant ctrl_clksel0_c : natural := 0; -- r/w: prescaler select bit 0
constant ctrl_clksel1_c : natural := 1; -- r/w: prescaler select bit 1
constant ctrl_clksel2_c : natural := 2; -- r/w: prescaler select bit 2
constant ctrl_enable_c : natural := 3; -- r/w: WDT enable
constant ctrl_rcause_c : natural := 4; -- r/-: reset cause (0: external, 1: watchdog timeout)
constant ctrl_rpwfail_c : natural := 5; -- r/-: watchdog reset caused by wrong password access when '1'
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal pwd_ok : std_ulogic; -- password correct
signal fail, fail_ff : std_ulogic; -- unauthorized access
signal wren : std_ulogic;
-- accessible regs --
signal rst_source : std_ulogic; -- source of the system reset: '0' = external, '1' = watchdog timeout
signal pw_fail : std_ulogic; -- watchdog reset caused by wrong password access
signal enable : std_ulogic;
signal clk_sel : std_ulogic_vector(02 downto 0);
-- reset counter --
signal cnt : std_ulogic_vector(16 downto 0);
signal rst_gen : std_ulogic_vector(03 downto 0);
signal rst_sync : std_ulogic_vector(01 downto 0);
-- prescaler clock generator --
signal prsc_tick : std_ulogic;
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wdt_base_c(hi_abb_c downto lo_abb_c)) else '0';
pwd_ok <= '1' when (data_i(15 downto 8) = wdt_password_c) else '0'; -- password check
wren <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '1')) else '0'; -- write access ok
fail <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '0')) else '0'; -- write access fail!
-- Write Access, Reset Generator --------------------------------------------
-- -----------------------------------------------------------------------------
wdt_core: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '0') or (rst_sync(1) = '0') then -- external or internal reset
enable <= '0'; -- disable WDT
clk_sel <= (others => '1'); -- slowest clock rst_source
rst_gen <= (others => '1'); -- do NOT fire on reset!
else
-- control register write access --
if (wren = '1') then -- allow write if password is correct
enable <= data_i(ctrl_enable_c);
clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
end if;
-- reset generator - enabled and (overflow or unauthorized access)? --
if (enable = '1') and ((cnt(cnt'left) = '1') or (fail_ff = '1')) then
rst_gen <= (others => '0');
else
rst_gen <= rst_gen(rst_gen'left-1 downto 0) & '1';
end if;
end if;
end if;
end process wdt_core;
-- enable external clock generator --
clkgen_en_o <= enable;
-- Counter Update -----------------------------------------------------------
-- -----------------------------------------------------------------------------
cnt_sync: process(clk_i)
begin
if rising_edge(clk_i) then
-- clock_en buffer --
prsc_tick <= clkgen_i(to_integer(unsigned(clk_sel)));
-- unauthorized access buffer --
fail_ff <= fail;
-- reset synchronizer --
rst_sync <= rst_sync(0) & rst_gen(rst_gen'left);
-- counter update --
if (wren = '1') then -- clear counter on write access (manual watchdog reset)
cnt <= (others => '0');
elsif (enable = '1') and (prsc_tick = '1') then
cnt <= std_ulogic_vector(unsigned('0' & cnt(cnt'left-1 downto 0)) + 1);
end if;
end if;
end process cnt_sync;
-- system reset --
rst_o <= rst_sync(1);
-- Reset Cause Indicator ----------------------------------------------------
-- -----------------------------------------------------------------------------
rst_cause: process(rst_i, clk_i)
begin
if (rst_i = '0') then
rst_source <= '0';
pw_fail <= '0';
elsif rising_edge(clk_i) then
rst_source <= rst_source or (cnt(cnt'left) and enable) or (fail_ff and enable); -- set on WDT timeout or access error
pw_fail <= (pw_fail or (fail_ff and enable)) and (not (cnt(cnt'left) and enable)); -- set on failed access, clear on WDT timeout
--pw_fail <= (pw_fail and (not (cnt(cnt'left) and enable))) or (fail_ff and enable); -- clear on WDT timeout, set on failed access
end if;
end process rst_cause;
-- Read Access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
read_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (acc_en = '1') and (rden_i = '1') then
data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= clk_sel;
data_o(ctrl_enable_c) <= enable;
data_o(ctrl_rcause_c) <= rst_source;
data_o(ctrl_rpwfail_c) <= pw_fail;
end if;
end if;
end process read_access;
end neo430_wdt_rtl;
|
------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- for arch1
-- use ieee.std_logic_arith.all; -- for arch2, arch3
-- best to use arch2 using numeric_std
------------------------------
entity signed_multiplier is
--generic declarations
port (
a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0);
prod: out std_vector_vector(7 downto 0);
);
end entity;
------------------------------
architecture arch1 of signed_multiplier is
signal a_sig: signed(3 downto 0);
signal a_sig: signed(3 downto 0);
begin
a_sig <= signed(a);
b_sig <= signed(b);
prod <= std_logic_vector(a_sig * b_sig);
end architecture;
------------------------------
architecture arch2 of signed_multiplier is
signal a_sig: signed(3 downto 0);
signal b_sig: signed(3 downto 0);
signal prod: signed(7 downto 0);
begin
a_sig <= signed(a);
b_sig <= signed(b);
prod_sig <= a_sig * b_sig;
prod <= std_logic_vector(prod_sig);
end architecture;
------------------------------
architecture arch2 of signed_multiplier is
signal a_sig: signed(3 downto 0);
signal b_sig: signed(3 downto 0);
begin
a_sig <= signed(a);
b_sig <= signed(b);
prod <= std_logic_vector(signed(a_sig * b_sig));
end architecture;
------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc220.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p06n03i00220ent IS
type e is (EMIN,ETYP,EMAX);
END c03s01b01x00p06n03i00220ent;
ARCHITECTURE c03s01b01x00p06n03i00220arch OF c03s01b01x00p06n03i00220ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(e'pos(ETYP) < e'pos(EMAX))
report "***PASSED TEST: c03s01b01x00p06n03i00220"
severity NOTE;
assert (e'pos(ETYP) < e'pos(EMAX))
report "***FAILED TEST: c03s01b01x00p06n03i00220 - The position number of the value of each additional enumeration literal is one more than that of its predecessor in the list."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p06n03i00220arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc220.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p06n03i00220ent IS
type e is (EMIN,ETYP,EMAX);
END c03s01b01x00p06n03i00220ent;
ARCHITECTURE c03s01b01x00p06n03i00220arch OF c03s01b01x00p06n03i00220ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(e'pos(ETYP) < e'pos(EMAX))
report "***PASSED TEST: c03s01b01x00p06n03i00220"
severity NOTE;
assert (e'pos(ETYP) < e'pos(EMAX))
report "***FAILED TEST: c03s01b01x00p06n03i00220 - The position number of the value of each additional enumeration literal is one more than that of its predecessor in the list."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p06n03i00220arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc220.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p06n03i00220ent IS
type e is (EMIN,ETYP,EMAX);
END c03s01b01x00p06n03i00220ent;
ARCHITECTURE c03s01b01x00p06n03i00220arch OF c03s01b01x00p06n03i00220ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(e'pos(ETYP) < e'pos(EMAX))
report "***PASSED TEST: c03s01b01x00p06n03i00220"
severity NOTE;
assert (e'pos(ETYP) < e'pos(EMAX))
report "***FAILED TEST: c03s01b01x00p06n03i00220 - The position number of the value of each additional enumeration literal is one more than that of its predecessor in the list."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p06n03i00220arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:06:44 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0/system_ov7670_vga_1_0_sim_netlist.vhdl
-- Design : system_ov7670_vga_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_1_0_ov7670_vga is
port (
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 );
active : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_vga_1_0_ov7670_vga : entity is "ov7670_vga";
end system_ov7670_vga_1_0_ov7670_vga;
architecture STRUCTURE of system_ov7670_vga_1_0_ov7670_vga is
signal cycle : STD_LOGIC;
signal \data_pair[15]_i_1_n_0\ : STD_LOGIC;
signal \data_pair[7]_i_1_n_0\ : STD_LOGIC;
signal \data_pair_reg_n_0_[0]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[10]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[11]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[12]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[13]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[14]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[15]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[1]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[2]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[3]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[4]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[5]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[6]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[7]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[8]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[9]\ : STD_LOGIC;
signal rgb_regn_0_0 : STD_LOGIC;
begin
cycle_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => \data_pair[7]_i_1_n_0\,
Q => cycle,
R => '0'
);
\data_pair[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => cycle,
I1 => active,
O => \data_pair[15]_i_1_n_0\
);
\data_pair[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => active,
I1 => cycle,
O => \data_pair[7]_i_1_n_0\
);
\data_pair_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(0),
Q => \data_pair_reg_n_0_[0]\,
R => '0'
);
\data_pair_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(2),
Q => \data_pair_reg_n_0_[10]\,
R => '0'
);
\data_pair_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(3),
Q => \data_pair_reg_n_0_[11]\,
R => '0'
);
\data_pair_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(4),
Q => \data_pair_reg_n_0_[12]\,
R => '0'
);
\data_pair_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(5),
Q => \data_pair_reg_n_0_[13]\,
R => '0'
);
\data_pair_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(6),
Q => \data_pair_reg_n_0_[14]\,
R => '0'
);
\data_pair_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(7),
Q => \data_pair_reg_n_0_[15]\,
R => '0'
);
\data_pair_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(1),
Q => \data_pair_reg_n_0_[1]\,
R => '0'
);
\data_pair_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(2),
Q => \data_pair_reg_n_0_[2]\,
R => '0'
);
\data_pair_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(3),
Q => \data_pair_reg_n_0_[3]\,
R => '0'
);
\data_pair_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(4),
Q => \data_pair_reg_n_0_[4]\,
R => '0'
);
\data_pair_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(5),
Q => \data_pair_reg_n_0_[5]\,
R => '0'
);
\data_pair_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(6),
Q => \data_pair_reg_n_0_[6]\,
R => '0'
);
\data_pair_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(7),
Q => \data_pair_reg_n_0_[7]\,
R => '0'
);
\data_pair_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(0),
Q => \data_pair_reg_n_0_[8]\,
R => '0'
);
\data_pair_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(1),
Q => \data_pair_reg_n_0_[9]\,
R => '0'
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[0]\,
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[10]\,
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[11]\,
Q => rgb(11),
R => '0'
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[12]\,
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[13]\,
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[14]\,
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[15]\,
Q => rgb(15),
R => '0'
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[1]\,
Q => rgb(1),
R => '0'
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[2]\,
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[3]\,
Q => rgb(3),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[4]\,
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[5]\,
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[6]\,
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[7]\,
Q => rgb(7),
R => '0'
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[8]\,
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[9]\,
Q => rgb(9),
R => '0'
);
rgb_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk_x2,
O => rgb_regn_0_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_1_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_vga_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_vga_1_0 : entity is "system_ov7670_vga_1_0,ov7670_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_vga_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_vga_1_0 : entity is "ov7670_vga,Vivado 2016.4";
end system_ov7670_vga_1_0;
architecture STRUCTURE of system_ov7670_vga_1_0 is
begin
U0: entity work.system_ov7670_vga_1_0_ov7670_vga
port map (
active => active,
clk_x2 => clk_x2,
data(7 downto 0) => data(7 downto 0),
rgb(15 downto 0) => rgb(15 downto 0)
);
end STRUCTURE;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: bscanregs
-- File: bscanregs.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: JTAG boundary scan registers, single-ended IO
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity bscanregs is
generic (
tech: integer := 0;
nsigs: integer range 1 to 30 := 8;
dirmask: integer := 2#00000000#;
enable: integer range 0 to 1 := 1
);
port (
sigi: in std_logic_vector(nsigs-1 downto 0);
sigo: out std_logic_vector(nsigs-1 downto 0);
tck: in std_ulogic;
tckn:in std_ulogic;
tdi: in std_ulogic;
tdo: out std_ulogic;
bsshft: in std_ulogic;
bscapt: in std_ulogic;
bsupdi: in std_ulogic;
bsupdo: in std_ulogic;
bsdrive: in std_ulogic;
bshighz: in std_ulogic
);
end;
architecture hier of bscanregs is
signal itdi: std_logic_vector(nsigs downto 0);
begin
disgen: if enable=0 generate
sigo <= sigi;
itdi <= (others => '0');
tdo <= '0';
end generate;
engen: if enable /= 0 generate
g0: for x in 0 to nsigs-1 generate
irgen: if ((dirmask / (2**x)) mod 2)=0 generate
ireg: scanregi
generic map (tech)
port map (sigi(x),sigo(x),tck,tckn,itdi(x),itdi(x+1),bsshft,bscapt,bsupdi,bsdrive,bshighz);
end generate;
orgen: if ((dirmask / (2**x)) mod 2)/=0 generate
oreg: scanrego
generic map (tech)
port map (sigo(x),sigi(x),sigi(x),tck,tckn,itdi(x),itdi(x+1),bsshft,bscapt,bsupdo,bsdrive);
end generate;
end generate;
itdi(0) <= tdi;
tdo <= itdi(nsigs);
end generate;
end;
|
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`protect end_protected
|
entity implicit is
end entity;
architecture test of implicit is
signal x : integer;
begin
process is
begin
assert x'delayed = 4; -- OK
assert x'delayed(1 ns) = 5; -- OK
assert x'delayed(5) = 1; -- Error
assert x'stable; -- OK
assert x'stable(1 ns); -- OK
assert x'delayed'stable(2 ns); -- OK
assert x'transaction = '1'; -- OK
assert x'quiet; -- OK
assert x'quiet(5 ns); -- OK
end process;
end architecture;
|
----------------------------------------
-- Main Processor : IITB-RISC
-- Author : Titto Thomas, Sainath, Anakha
-- Date : 9/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pipeline_RISC is
port (
clock, reset : in std_logic; -- clock and reset signals
InstrData, InstrAddress, DataData, DataAddress : in std_logic_vector(15 downto 0); -- External data and address for programing
mode, InstrWrite, DataWrite : in std_logic -- Program / Execution mode
);
end pipeline_RISC;
architecture behave of pipeline_RISC is
component Datapath is
port (
clock, reset : in std_logic; -- clock and reset signals
ExDData, ExDAddress : in std_logic_vector(15 downto 0); -- External data and address for programing
mode, ExDWrite : in std_logic; -- Program / Execution mode
RF_Write : in std_logic; -- Reg File write enable
MemRead, MemWrite : in std_logic; -- Read / Write from / to the data memory
OpSel, ALUc, ALUz, Cen, Zen,ALUOp : in std_logic; -- ALU & Flag block signals
M1_Sel, M2_Sel, M5_Sel, M3_Sel : in std_logic; -- Mux select lines
M4_Sel, M6_Sel, M7_Sel, M8_Sel, M9_Sel : in std_logic_vector(1 downto 0); -- Mux select lines
Instruction : out std_logic_vector(15 downto 0); -- Instruction to the CP
ExIWrite : in std_logic; -- Write to Instruction Mem
ExIData, ExIAddress : in std_logic_vector(15 downto 0) -- External instruction and address for programing
);
end component;
component ControlPath is
port (
clock, reset : in std_logic; -- clock and reset signals
RF_Write : out std_logic; -- Reg File write enable
MemRead, MemWrite : out std_logic; -- Read / Write from / to the data memory
OpSel, ALUc, ALUz, Cen, Zen, ALUop : out std_logic; -- ALU & Flag block signals
M1_Sel, M2_Sel, M5_Sel, M3_Sel : out std_logic; -- Mux select lines
M4_Sel, M6_Sel, M7_Sel, M8_Sel, M9_Sel : out std_logic_vector(1 downto 0); -- Mux select lines
Instruction : in std_logic_vector(15 downto 0) -- Instruction to the CP
);
end component;
signal RF_Write, MemRead, MemWrite, OpSel, ALUc, ALUz, Cen, Zen,ALUOp, M1_Sel, M2_Sel, M5_Sel, M3_Sel : std_logic;
signal M4_Sel, M6_Sel, M7_Sel, M8_Sel, M9_Sel : std_logic_vector(1 downto 0);
signal Instruction : std_logic_vector(15 downto 0);
begin -- behave
DP : Datapath port map (clock, reset, DataData, DataAddress, mode, DataWrite, RF_Write, MemRead, MemWrite, OpSel, ALUc, ALUz, Cen, Zen, ALUOp, M1_Sel, M2_Sel, M5_Sel, M3_Sel, M4_Sel, M6_Sel, M7_Sel, M8_Sel, M9_Sel, Instruction, InstrWrite, InstrData, InstrAddress);
CP : ControlPath port map (clock, reset, RF_Write, MemRead, MemWrite, OpSel, ALUc, ALUz, Cen, Zen, ALUop, M1_Sel, M2_Sel, M5_Sel, M3_Sel, M4_Sel, M6_Sel, M7_Sel, M8_Sel, M9_Sel, Instruction);
end behave;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divider is
GENERIC (
N: positive := 60
);
Port ( clk : in STD_LOGIC;
tc : out STD_LOGIC);
end divider;
architecture divider_architecture of divider is
signal cpt : STD_LOGIC_VECTOR (3 downto 0);
begin
count: process(clk)
begin
if rising_edge(clk) then
if cpt < N -1 then
cpt <= cpt + 1;
else
cpt <= (others => '0');
end if;
end if;
end process count;
remainder: process(cpt)
begin
if cpt = N-1 then
tc <= '1';
else
tc <= '0';
end if;
end process remainder;
end divider_architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2433.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02433ent IS
END c07s03b02x02p01n01i02433ent;
ARCHITECTURE c07s03b02x02p01n01i02433arch OF c07s03b02x02p01n01i02433ent IS
subtype BV1 is BIT_VECTOR (2 downto 1);
constant C18 : BV1 := (3 => '1', others => '0');
-- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02433 - Expression of each element association must be of the element type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02433arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2433.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02433ent IS
END c07s03b02x02p01n01i02433ent;
ARCHITECTURE c07s03b02x02p01n01i02433arch OF c07s03b02x02p01n01i02433ent IS
subtype BV1 is BIT_VECTOR (2 downto 1);
constant C18 : BV1 := (3 => '1', others => '0');
-- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02433 - Expression of each element association must be of the element type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02433arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2433.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02433ent IS
END c07s03b02x02p01n01i02433ent;
ARCHITECTURE c07s03b02x02p01n01i02433arch OF c07s03b02x02p01n01i02433ent IS
subtype BV1 is BIT_VECTOR (2 downto 1);
constant C18 : BV1 := (3 => '1', others => '0');
-- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02433 - Expression of each element association must be of the element type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02433arch;
|
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: GPU.vhd
-- // Date: 12/9/2004
-- // Description: Main GPU Module
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity GPU is
port(
iClk25MHZ : in std_logic;
iPaused : in std_logic;
iScore : std_logic_vector(15 downto 0);
oBlockAddr : out std_logic_vector(4 downto 0); --Holds static blocks
iBlockData : in std_logic_vector(15 downto 0); --Holds each row
iBlockY : in std_logic_vector(4 downto 0); --top edge of moving block
iBlockX : in std_logic_vector(3 downto 0); --left edge of moving block
iBlockReg : in std_logic_vector(15 downto 0); --encoded dynamic block memory
iClr : in std_logic;
iDiag : in std_logic;
oRGB : out std_logic_vector(2 downto 0);
oVSync : out std_logic;
oHSync : out std_logic);
end GPU;
architecture Behavioral of GPU is
Signal tRGB : std_logic_vector(2 downto 0);
component RGB_Controller is
Port ( oRGB : out std_logic_vector(2 downto 0);
iClk : in std_logic;
iClr : in std_logic;
iPaused : in std_logic;
iBlock: in std_logic_vector(15 downto 0); --Block rows fom Block RAM
oBlockAddr : out std_logic_vector(4 downto 0); --address for block ram
iBlockY : in std_logic_vector(4 downto 0); --encoded Y
iBlockX : in std_logic_vector(3 downto 0); --encoded X
iBlockReg : in std_logic_vector(15 downto 0));
end component;
component VGA is
Port ( oRGB : out std_logic_vector(2 downto 0);
oVSync : out std_logic;
oHSync : out std_logic;
iClk : in std_logic;
iDiag : in std_logic;
iClr : in std_logic;
iRGB : in std_logic_vector(2 downto 0));
end component;
begin
RGB00 : RGB_controller port map(
oRGB => tRGB,
iClk => iClk25Mhz,
iClr => iClr,
iPaused => iPaused,
iBlock => iBlockData,
oBlockAddr => oBlockAddr,
iBlockX => iBlockX,
iBlockY => iBlockY,
iBlockReg => iBlockReg);
VGA00 : VGA port map(
oRGB => oRGB,
iRGB => tRGB,
iDiag => iDiag,
oVSync => oVSync,
oHSync => oHSync,
iClk => iClk25Mhz,
iClr => iClr);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 20:59:47 06/19/2008
-- Design Name:
-- Module Name: idea_com_inner - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 1.00 - File Created
-- Revision 2.00 (nnc) - Key can be programmed
-- Revision 2.01 (nnc) - Add loopback mode for cable testing
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity idea_com_inner is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
RxD : in STD_LOGIC;
TxD : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR (7 downto 0));
end idea_com_inner;
architecture Behavioral of idea_com_inner is
-- The UART for the communication with the PC:
component uart
port ( mclkx16 : in STD_LOGIC;
reset : in STD_LOGIC;
read : in STD_LOGIC;
write : in STD_LOGIC;
--data : inout STD_LOGIC_VECTOR (7 downto 0);
rxdata : out STD_LOGIC_VECTOR (7 downto 0);
txdata : in STD_LOGIC_VECTOR (7 downto 0);
sin : in STD_LOGIC;
sout : out STD_LOGIC;
rxrdy : out STD_LOGIC;
txrdy : out STD_LOGIC;
parity_error : out STD_LOGIC;
framing_error : out STD_LOGIC;
overrun : out STD_LOGIC );
end component;
--component idea_hw
-- Port ( CLK : in STD_LOGIC;
-- START : in STD_LOGIC;
-- READY : out STD_LOGIC;
-- KEY : in STD_LOGIC_VECTOR (127 downto 0);
-- X1 : in STD_LOGIC_VECTOR (15 downto 0);
-- X2 : in STD_LOGIC_VECTOR (15 downto 0);
-- X3 : in STD_LOGIC_VECTOR (15 downto 0);
-- X4 : in STD_LOGIC_VECTOR (15 downto 0);
-- Y1 : out STD_LOGIC_VECTOR (15 downto 0);
-- Y2 : out STD_LOGIC_VECTOR (15 downto 0);
-- Y3 : out STD_LOGIC_VECTOR (15 downto 0);
-- Y4 : out STD_LOGIC_VECTOR (15 downto 0));
--end component;
COMPONENT idea_single
PORT(
KEY : IN std_logic_vector(127 downto 0);
clk_in : IN std_logic;
ready_out : OUT std_logic;
start_in : IN std_logic;
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT multiplexer
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0);
s : IN std_logic
);
END COMPONENT;
-- All used signals for the top level are defined here:
signal read : STD_LOGIC := '1';
signal write : STD_LOGIC := '1';
signal rxrdy, txrdy : STD_LOGIC := '1';
signal parity_error, framing_error, overrun : STD_LOGIC := '0';
signal data : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
signal txdata : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
signal start_idea, ready_idea : STD_LOGIC := '0';
signal x1, x2, x3, x4 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal y1, y2, y3, y4 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal key : STD_logic_vector (127 downto 0) := x"00000000000000000000000000000000";
type STATE_TYPE is ( IDLE, WAIT_FOR_DATA, RECEIVED_BYTE, READ_BYTE,
WAIT_FOR_RXRDY_0, WAIT_FOR_IDEA_TO_DEACTIVATE_READY,
WAIT_FOR_IDEA_TO_COMPLETE,
WRITE_BYTE, WRITE_BYTE_NOW, WRITE_BYTE_ACK,
WAIT_FOR_TXRDY_1, LOOPBACK_MODE );
signal state : STATE_TYPE := IDLE;
signal byte_cntr : std_logic_vector(4 downto 0) := "00000";
signal loopback_select : std_logic := '0';
signal z1, z2, z3, z4 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal led_count_sig : std_logic_vector(7 downto 0) := "00000000";
signal counter_sig : std_logic_vector(18 downto 0) := (others => '0');
begin
-- The UART module
uart1: uart port map( Clk, Reset,
read, write, data, txdata,
RxD, TxD,
rxrdy, txrdy,
parity_error, framing_error, overrun );
-- The encryption algorithm
-- idea1: idea_hw port map( clk, start_idea, ready_idea, key, x1, x2, x3, x4, y1, y2, y3, y4);
uut: idea_single PORT MAP (
KEY => key,
clk_in => Clk,
ready_out => ready_idea,
start_in => start_idea,
X1 => x1,
X2 => x2,
X3 => x3,
X4 => x4,
Y1 => y1,
Y2 => y2,
Y3 => y3,
Y4 => y4
);
-- mux for loopback mode
mux1 : multiplexer port map(
A => y1,
B => x1,
S => loopback_select,
O => z1);
mux2 : multiplexer port map(
A => y2,
B => x2,
S => loopback_select,
O => z2);
mux3 : multiplexer port map(
A => y3,
B => X3,
S => loopback_select,
O => z3);
mux4 : multiplexer port map(
A => y4,
B => X4,
S => loopback_select,
O => z4);
-- The state machine for the communication:
process ( Clk )
begin
if ( Clk'event and Clk='1' ) then
if ( Reset = '1' ) then
state <= IDLE;
byte_cntr <= "00000";
read <= '1';
write <= '1';
--LEDs <= "00000000";
else
if ( state = IDLE ) then
-- Initial state
state <= WAIT_FOR_DATA;
byte_cntr <= "00000";
elsif ( state = WAIT_FOR_DATA ) then
write <= '1';
-- Waiting for incoming data.
if ( rxrdy = '1' ) then
-- There is a byte at the receiver!
state <= RECEIVED_BYTE;
end if;
elsif ( state = RECEIVED_BYTE ) then
-- The UART signalizes, that there
-- is a new byte to be read!
read <= '0';
--LEDs(3) <= '0';
state <= READ_BYTE;
elsif ( state = READ_BYTE ) then
-- Read the byte and set the
-- right input registers of the
-- IDEA block.
--LEDs(0) <= framing_error;
--LEDs(1) <= parity_error;
--LEDs(2) <= overrun;
byte_cntr <= byte_cntr+"00001";
if ( byte_cntr = "00000" ) then
x1(7 downto 0) <= data;
elsif ( byte_cntr = "00001" ) then
x1(15 downto 8) <= data;
elsif ( byte_cntr = "00010" ) then
x2(7 downto 0) <= data;
elsif ( byte_cntr = "00011" ) then
x2(15 downto 8) <= data;
elsif ( byte_cntr = "00100" ) then
x3(7 downto 0) <= data;
elsif ( byte_cntr = "00101" ) then
x3(15 downto 8) <= data;
elsif ( byte_cntr = "00110" ) then
x4(7 downto 0) <= data;
elsif ( byte_cntr = "00111" ) then
x4(15 downto 8) <= data;
elsif ( byte_cntr = "01000" ) then
key(7 downto 0) <= data;
elsif ( byte_cntr = "01001" ) then
key(15 downto 8) <= data;
elsif ( byte_cntr = "01010" ) then
key(23 downto 16) <= data;
elsif ( byte_cntr = "01011" ) then
key(31 downto 24) <= data;
elsif ( byte_cntr = "01100" ) then
key(39 downto 32) <= data;
elsif ( byte_cntr = "01101" ) then
key(47 downto 40) <= data;
elsif ( byte_cntr = "01110" ) then
key(55 downto 48) <= data;
elsif ( byte_cntr = "01111" ) then
key(63 downto 56) <= data;
elsif ( byte_cntr = "10000" ) then
key(71 downto 64) <= data;
elsif ( byte_cntr = "10001" ) then
key(79 downto 72) <= data;
elsif ( byte_cntr = "10010" ) then
key(87 downto 80) <= data;
elsif ( byte_cntr = "10011" ) then
key(95 downto 88) <= data;
elsif ( byte_cntr = "10100" ) then
key(103 downto 96) <= data;
elsif ( byte_cntr = "10101" ) then
key(111 downto 104) <= data;
elsif ( byte_cntr = "10110" ) then
key(119 downto 112) <= data;
elsif ( byte_cntr = "10111" ) then
key(127 downto 120) <= data;
end if;
read <= '1';
state <= WAIT_FOR_RXRDY_0;
elsif ( state = WAIT_FOR_RXRDY_0 ) then
-- Wait until the UART has acknowledged
-- that the data has been read.
if ( rxrdy = '0' ) then
if ( byte_cntr = "11000" ) then
-- add loopback mode
if (key = X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF") then
state <= LOOPBACK_MODE;
loopback_select <= '1';
else
start_idea <= '1';
state <= WAIT_FOR_IDEA_TO_DEACTIVATE_READY;
loopback_select <= '0';
end if;
-- added newly: 20130405
-- read <= '1';
else
state <= WAIT_FOR_DATA;
end if;
end if;
elsif(state=LOOPBACK_MODE) then
byte_cntr <= "00000";
state <= WRITE_BYTE;
elsif ( state = WAIT_FOR_IDEA_TO_DEACTIVATE_READY ) then
if ( ready_idea = '0' ) then
state <= WAIT_FOR_IDEA_TO_COMPLETE;
end if;
elsif ( state = WAIT_FOR_IDEA_TO_COMPLETE ) then
-- The IDEA algorithm has computed its results now.
byte_cntr <= "00000";
start_idea <= '0';
if ( ready_idea = '1' ) then
state <= WRITE_BYTE;
end if;
elsif ( state = WRITE_BYTE ) then
-- Write back the computed data set
byte_cntr <= byte_cntr + "00001";
if ( byte_cntr = "00000" ) then
txdata <= z1(7 downto 0);
elsif ( byte_cntr = 1 ) then
txdata <= z1(15 downto 8);
elsif ( byte_cntr = 2 ) then
txdata <= z2(7 downto 0);
elsif ( byte_cntr = 3 ) then
txdata <= z2(15 downto 8);
elsif ( byte_cntr = 4 ) then
txdata <= z3(7 downto 0);
elsif ( byte_cntr = 5 ) then
txdata <= z3(15 downto 8);
elsif ( byte_cntr = 6 ) then
txdata <= z4(7 downto 0);
elsif ( byte_cntr = 7 ) then
txdata <= z4(15 downto 8);
end if;
state <= WRITE_BYTE_NOW;
elsif ( state = WRITE_BYTE_NOW ) then
write <= '0';
state <= WRITE_BYTE_ACK;
elsif ( state = WRITE_BYTE_ACK ) then
write <= '1';
if ( txrdy = '0' ) then
state <= WAIT_FOR_TXRDY_1;
end if;
elsif ( state = WAIT_FOR_TXRDY_1 ) then
if ( txrdy = '1' ) then
txdata <= "00000000";
if ( byte_cntr = "01000" ) then
state <= WAIT_FOR_DATA;
byte_cntr <= "00000";
else
state <= WRITE_BYTE;
end if;
end if;
end if;
end if;
end if;
end process;
LEDs_proc : process ( Clk )
begin
if ( Clk'event and Clk='1' ) then
if(counter_sig = "1001011000000000000") then
counter_sig <= "0000000000000000000";
if(led_count_sig = "11111111") then
led_count_sig <= "00000000";
else
LEDs <= led_count_sig;
led_count_sig <= led_count_sig +1;
end if;
else
counter_sig <= counter_sig +1;
end if;
end if;
end process LEDs_proc;
end Behavioral;
|
----- Libraries -----
library ieee;
use ieee.std_logic_1164.all;
entity Tester is
port( LEDR : out std_logic_vector(1 downto 0);
KEY : in std_logic_vector(1 downto 0);
SW : in std_logic_vector(1 downto 0)
);
end Tester;
architecture State of Tester is
begin
sm1 : entity work.Mee_Moo port map(moo_out => LEDR(0), mea_out => LEDR(1), clk => KEY(0), reset => KEY(1), inp => SW);
end State; |
library verilog;
use verilog.vl_types.all;
entity four_bit_adder_vlg_sample_tst is
port(
A : in vl_logic_vector(3 downto 0);
B : in vl_logic_vector(3 downto 0);
cin : in vl_logic;
sampler_tx : out vl_logic
);
end four_bit_adder_vlg_sample_tst;
|
----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY action_axi_slave IS
GENERIC (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
PORT (
reg_0x10_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x14_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x20_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x30_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x34_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x38_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x3c_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x40_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x44_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x48_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x4c_req_error_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
reg_0x4c_nvme_error_i : IN STD_LOGIC_VECTOR( 2 DOWNTO 0);
reg_0x4c_completion_i : IN STD_LOGIC_VECTOR( 4 DOWNTO 0);
reg_0x4c_rd_strobe_o : OUT STD_LOGIC;
reg_0x50_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x54_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
int_enable_o : OUT STD_LOGIC;
app_start_o : OUT STD_LOGIC;
app_done_i : IN STD_LOGIC;
app_ready_i : IN STD_LOGIC;
app_idle_i : IN STD_LOGIC;
-- AXI Slave interface
-- Global Clock Signal
S_AXI_ACLK : IN STD_LOGIC;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : IN STD_LOGIC;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : IN STD_LOGIC;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : OUT STD_LOGIC;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : IN STD_LOGIC_VECTOR((C_S_AXI_DATA_WIDTH/8)-1 DOWNTO 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : IN STD_LOGIC;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : OUT STD_LOGIC;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : OUT STD_LOGIC;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : IN STD_LOGIC;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : IN STD_LOGIC;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : OUT STD_LOGIC;
-- Read data (issued by slave)
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : OUT STD_LOGIC;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : IN STD_LOGIC
);
END action_axi_slave;
ARCHITECTURE action_axi_slave OF action_axi_slave IS
-- AXI4LITE signals
SIGNAL axi_awaddr : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL axi_awready : STD_LOGIC;
SIGNAL axi_wready : STD_LOGIC;
SIGNAL axi_bresp : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL axi_bvalid : STD_LOGIC;
SIGNAL axi_araddr : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL axi_arready : STD_LOGIC;
SIGNAL axi_rdata : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL axi_rresp : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL axi_rvalid : STD_LOGIC;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
CONSTANT ADDR_LSB : INTEGER := (C_S_AXI_DATA_WIDTH/32)+ 1;
CONSTANT OPT_MEM_ADDR_BITS : INTEGER := 6;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 16
SIGNAL slv_reg0 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg0_new : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg1 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg2 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg3 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg8 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg12 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg13 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg14 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg15 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg16 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg17 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg18 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg19 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg_rden : STD_LOGIC;
SIGNAL slv_reg_wren : STD_LOGIC;
SIGNAL reg_data_out : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL byte_index : INTEGER;
SIGNAL idle_q : STD_LOGIC;
SIGNAL app_start_q : STD_LOGIC;
SIGNAL app_done_q : STD_LOGIC;
BEGIN
-- I/O Connections assignments
int_enable_o <= slv_reg1(0);
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
IF (axi_awready = '0' AND S_AXI_AWVALID = '1' AND S_AXI_WVALID = '1') THEN
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
ELSE
axi_awready <= '0';
END IF;
IF S_AXI_ARESETN = '0' THEN
axi_awready <= '0';
END IF;
END IF;
END PROCESS;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
IF (axi_awready = '0' AND S_AXI_AWVALID = '1' AND S_AXI_WVALID = '1') THEN
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
END IF;
IF S_AXI_ARESETN = '0' THEN
axi_awaddr <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
IF (axi_wready = '0' AND S_AXI_WVALID = '1' AND S_AXI_AWVALID = '1') THEN
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
ELSE
axi_wready <= '0';
END IF;
IF S_AXI_ARESETN = '0' THEN
axi_wready <= '0';
END IF;
END IF;
END PROCESS;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready AND S_AXI_WVALID AND axi_awready AND S_AXI_AWVALID ;
PROCESS (S_AXI_ACLK)
VARIABLE loc_addr : std_logic_vector(OPT_MEM_ADDR_BITS-1 DOWNTO 0);
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 DOWNTO ADDR_LSB);
IF (slv_reg_wren = '1') THEN
CASE loc_addr IS
WHEN b"000000" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 0
slv_reg0(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"000001" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 1
slv_reg1(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"000010" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 2
slv_reg2(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"000011" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 3
slv_reg3(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"001000" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 8
slv_reg8(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"001100" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 12
slv_reg12(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"001101" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 13
slv_reg13(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"001110" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 14
slv_reg14(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"001111" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 15
slv_reg15(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"010000" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 16
slv_reg16(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"010001" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 17
slv_reg17(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"010010" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 18
slv_reg18(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"010011" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 19
slv_reg19(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN OTHERS =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg8 <= slv_reg8;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
END CASE;
END IF;
IF app_start_q = '1' THEN
slv_reg0(0) <= '0';
END IF;
IF S_AXI_ARESETN = '0' THEN
slv_reg0 <= (OTHERS => '0');
slv_reg1 <= (OTHERS => '0');
slv_reg2 <= (OTHERS => '0');
slv_reg3 <= (OTHERS => '0');
slv_reg8 <= (OTHERS => '0');
slv_reg12 <= (OTHERS => '0');
slv_reg13 <= (OTHERS => '0');
slv_reg14 <= (OTHERS => '0');
slv_reg15 <= (OTHERS => '0');
slv_reg16 <= (OTHERS => '0');
slv_reg17 <= (OTHERS => '0');
slv_reg18 <= (OTHERS => '0');
slv_reg19 <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
IF (axi_awready = '1' AND S_AXI_AWVALID = '1' AND axi_wready = '1' AND S_AXI_WVALID = '1' AND axi_bvalid = '0' ) THEN
axi_bvalid <= '1';
axi_bresp <= "00";
ELSIF (S_AXI_BREADY = '1' AND axi_bvalid = '1') THEN --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
END IF;
IF S_AXI_ARESETN = '0' THEN
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
END IF;
END IF;
END PROCESS;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
IF (axi_arready = '0' AND S_AXI_ARVALID = '1') THEN
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
ELSE
axi_arready <= '0';
END IF;
IF S_AXI_ARESETN = '0' THEN
axi_arready <= '0';
axi_araddr <= (OTHERS => '1');
END IF;
END IF;
END PROCESS;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
IF (axi_arready = '1' AND S_AXI_ARVALID = '1' AND axi_rvalid = '0') THEN
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
ELSIF (axi_rvalid = '1' AND S_AXI_RREADY = '1') THEN
-- Read data is accepted by the master
axi_rvalid <= '0';
END IF;
IF S_AXI_ARESETN = '0' THEN
axi_rvalid <= '0';
axi_rresp <= "00";
END IF;
END IF;
END PROCESS;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready AND S_AXI_ARVALID AND (NOT axi_rvalid) ;
PROCESS (slv_reg0_new, slv_reg1, slv_reg2, slv_reg3, reg_0x10_i, reg_0x14_i, slv_reg8, slv_reg12,
slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, reg_0x48_i, slv_reg19, axi_araddr,
reg_0x4c_completion_i, reg_0x4c_req_error_i, reg_0x4c_nvme_error_i,
reg_0x50_i, reg_0x54_i)
VARIABLE loc_addr : std_logic_vector(OPT_MEM_ADDR_BITS-1 DOWNTO 0);
VARIABLE loc_idx : integer RANGE 0 TO 511;
BEGIN
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 DOWNTO ADDR_LSB);
loc_idx := to_integer(unsigned(axi_araddr(5 DOWNTO 2))) * 32;
CASE loc_addr IS
WHEN b"000000" =>
reg_data_out <= slv_reg0_new; -- 0x00
WHEN b"000001" =>
reg_data_out <= slv_reg1; -- 0x04
WHEN b"000010" =>
reg_data_out <= slv_reg2; -- 0x08
WHEN b"000011" =>
reg_data_out <= slv_reg3; -- 0x0c
WHEN b"000100" =>
reg_data_out <= reg_0x10_i; -- 0x10
WHEN b"000101" =>
reg_data_out <= reg_0x14_i; -- 0x14
WHEN b"001000" =>
reg_data_out <= slv_reg8; -- 0x20
WHEN b"001100" =>
reg_data_out <= slv_reg12; -- 0x30
WHEN b"001101" =>
reg_data_out <= slv_reg13; -- 0x34
WHEN b"001110" =>
reg_data_out <= slv_reg14; -- 0x38
WHEN b"001111" =>
reg_data_out <= slv_reg15; -- 0x3c
WHEN b"010000" =>
reg_data_out <= slv_reg16; -- 0x40
WHEN b"010001" =>
reg_data_out <= slv_reg17; -- 0x44
WHEN b"010010" =>
reg_data_out <= reg_0x48_i; -- 0x48 : Tracking slots with NVMe read error (bits 31:16) / NVMe write error (bits 15:0)
WHEN b"010011" =>
reg_data_out <= reg_0x4c_req_error_i & slv_reg19(15 DOWNTO 11) & reg_0x4c_nvme_error_i & slv_reg19(7 DOWNTO 5) & reg_0x4c_completion_i; -- 0x4c
WHEN b"010100" =>
reg_data_out <= reg_0x50_i; -- 0x50 : Request tracking register
-- for slot in {0,...,15}:
-- bit slot+32 = '1' means: request from application for slot got initiated
-- bit is reset when the applications request is completed
-- bit slot = '1' means: request is an NVMe read request (NVMe writer request, otherwise)
WHEN b"010101" =>
reg_data_out <= reg_0x54_i; -- 0x54 : NVMe request / response register
-- for slot in {0,...,15}:
-- bit slot+32 = '1' means: request to Nvme host controller for slot initiated
-- bit is reset when the applications request is completed
-- bit slot = '1' means: response from Nvme host controler for slot arrived
-- bit is reset when the applications request is completed
-- WHEN b"010111" =>
-- reg_data_out <= reg_0x5c_i; -- 0x5c : NVMe host controller debug register 0x4c (snd tracking info)
-- -- for slot in {0,...,15}:
-- -- bit slot+32 = '1' means: request to Nvme drive for slot initiated (=>WRITE_SQ)
-- -- bit is reset when the drive signals receive of request
-- -- bit slot = '1' means: request to Nvme drive for slot completed (=>WRITE_SQ_DOORBELL)
-- -- bit is reset when the drive signals receive of request
WHEN OTHERS =>
reg_data_out <= (OTHERS => '0');
END CASE;
END PROCESS;
reg_0x4c_rd_strobe_o <= '1' WHEN slv_reg_rden = '1' AND axi_araddr(7 DOWNTO 0) = x"4c" ELSE '0';
-- Output register or memory read data
PROCESS( S_AXI_ACLK ) IS
BEGIN
IF (rising_edge (S_AXI_ACLK)) THEN
IF (slv_reg_rden = '1') THEN
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
END IF;
IF ( S_AXI_ARESETN = '0' ) THEN
axi_rdata <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
app_start_o <= app_start_q;
reg_0x20_o <= slv_reg8;
reg_0x30_o <= slv_reg12;
reg_0x34_o <= slv_reg13;
reg_0x38_o <= slv_reg14;
reg_0x3c_o <= slv_reg15;
reg_0x40_o <= slv_reg16;
reg_0x44_o <= slv_reg17;
PROCESS( S_AXI_ACLK ) IS
VARIABLE app_done_i_q : std_logic;
VARIABLE loc_addr : std_logic_vector(OPT_MEM_ADDR_BITS-1 DOWNTO 0);
BEGIN
IF (rising_edge (S_AXI_ACLK)) THEN
app_start_q <= app_start_q;
idle_q <= app_idle_i;
app_done_i_q := app_done_i;
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 DOWNTO ADDR_LSB);
-- clear app_done bit when register is read
IF slv_reg_rden = '1' AND loc_addr = "00000" THEN
app_done_q <= '0';
END IF;
IF (app_done_i_q = '0' AND app_done_i = '1') THEN
app_done_q <= '1';
END IF;
IF slv_reg0(0) = '1' THEN
app_start_q <= '1';
END IF;
IF idle_q = '1' AND app_idle_i = '0' THEN
app_start_q <= '0';
END IF;
IF ( S_AXI_ARESETN = '0' ) THEN
app_start_q <= '0';
app_done_q <= '0';
app_done_i_q := '0';
idle_q <= '0';
END IF;
END IF;
END PROCESS;
slv_reg0_new <= slv_reg0 (31 DOWNTO 4) & app_ready_i & idle_q & app_done_q & app_start_q ;
END action_axi_slave;
|
-------------------------------------------------------------------------------
-- Title : ALU log_or
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : ALU_Log_Or.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-06
-- Last update: 2016-12-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-06 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity ALU_Log_Or is
generic (
DATA_WIDTH : integer
);
port (
i_ra : in unsigned(DATA_WIDTH - 1 downto 0);
i_rb : in unsigned(DATA_WIDTH - 1 downto 0);
o_q : out unsigned(DATA_WIDTH * 2 - 1 downto 0)
);
end entity ALU_Log_Or;
-------------------------------------------------------------------------------
architecture rtl of ALU_Log_Or is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal result : unsigned(DATA_WIDTH - 1 downto 0);
constant upper : unsigned(DATA_WIDTH - 1 downto 0) := (others => '0');
begin -- architecture rtl
o_q <= upper & result;
result <= i_ra or i_rb;
end architecture rtl;
-------------------------------------------------------------------------------
|
-- Testebench gerado via script.
-- Data: Sáb,31/12/2011-01:39:29
-- Autor: rogerio
-- Comentario: Teste da entidade unidadeLogica.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity unidadeLogica_tb is
end unidadeLogica_tb;
architecture estrutural of unidadeLogica_tb is
-- Declaração do componente.
component unidadeLogica
port (A, B, OpAND, OpOR, OpNAND, OpNOR, OpXOR, OpXNOR, OpNOT: in <<type>>; S: out <<type>>);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for unidadeLogica_0: unidadeLogica use entity work.unidadeLogica;
signal s_t_A, s_t_B, s_t_OpAND, s_t_OpOR, s_t_OpNAND, s_t_OpNOR, s_t_OpXOR, s_t_OpXNOR, s_t_OpNOT, s_t_S: <<type>>;
begin
-- Instanciação do Componente.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
unidadeLogica_0: unidadeLogica port map ( A=>s_t_A, B=>s_t_B, OpAND=>s_t_OpAND, OpOR=>s_t_OpOR, OpNAND=>s_t_OpNAND, OpNOR=>s_t_OpNOR, OpXOR=>s_t_OpXOR, OpXNOR=>s_t_OpXNOR, OpNOT=>s_t_OpNOT, S=>s_t_S);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- entradas.
vi_A, vi_B, vi_OpAND, vi_OpOR, vi_OpNAND, vi_OpNOR, vi_OpXOR, vi_OpXNOR, vi_OpNOT: <<type>>;
-- saídas.
vo_S: <<type>>;
end record;
-- Os padrões de entrada que são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
-- Casos de teste.
constant patterns : pattern_array :=
(
(casos de testes com 10 colunas, '0'...),
(...)
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
s_t_A <= patterns(i).vi_A;
s_t_B <= patterns(i).vi_B;
s_t_OpAND <= patterns(i).vi_OpAND;
s_t_OpOR <= patterns(i).vi_OpOR;
s_t_OpNAND <= patterns(i).vi_OpNAND;
s_t_OpNOR <= patterns(i).vi_OpNOR;
s_t_OpXOR <= patterns(i).vi_OpXOR;
s_t_OpXNOR <= patterns(i).vi_OpXNOR;
s_t_OpNOT <= patterns(i).vi_OpNOT;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert s_t_S = patterns(i).vo_S report "Valor de s_t_S não confere com o resultado esperado." severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end estrutural;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2015, Przemyslaw Wegrzyn <[email protected]>
-- This file is distributed under the Modified BSD License.
--
-- Testbench for teh HD44780 LCD interface.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t_hd44780_iface is
end t_hd44780_iface;
architecture behavior of t_hd44780_iface is
component hd44780_iface
generic (time_base_period : integer);
port(clk : in std_logic;
time_base : in std_logic;
db : in std_logic_vector(7 downto 0);
rs : in std_logic;
strb : in std_logic;
rdy : out std_logic;
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_d : out std_logic_vector(7 downto 4)
);
end component;
signal clk : std_logic := '0';
signal time_base : std_logic := '0';
signal db : std_logic_vector(7 downto 0) := (others => '0');
signal rs : std_logic := '0';
signal strb : std_logic := '0';
signal ready : std_logic;
signal lcd_e : std_logic;
signal lcd_rs : std_logic;
signal lcd_rw : std_logic;
signal lcd_d : std_logic_vector(7 downto 4);
-- 50MHz main clock, 1kHz time base
constant clk_period : time := 20 ns;
constant time_base_ratio : integer := 5_000;
constant time_base_period : integer := 100; -- microseconds
-- E pulse timing paramters, from the Hitachi HD44780U datahseet,
-- worst case (VCC 2.7..4.5V)
constant min_power_up_delay : time := 40 ms;
constant min_addr_setup_time : time := 60 ns;
constant min_addr_hold_time : time := 20 ns;
constant min_data_setup_time : time := 195 ns;
constant min_data_hold_time : time := 10 ns;
constant min_e_pulse_width : time := 450 ns;
-- minimum time between E rising edges
constant min_e_cycle_time : time := 1000 ns;
-- datasheet says 37us (+ 4us for RAM access), let's add some margin
constant normal_cmd_delay : time := 50 us;
-- can't find it stated explicitely anywhere - assuming same
-- as command delay (probably much longer than needed)
constant high_nibble_delay : time := normal_cmd_delay;
-- Clear Display and Return Home need more time (1.6 ms + margin)
constant long_cmd_delay : time := 2 ms;
-- init sequence
type t_init_sequence_entry is record
data : std_logic_vector(7 downto 4);
delay : time;
end record;
type t_init_sequence is array (0 to 3) of t_init_sequence_entry;
signal init_sequence : t_init_sequence := (
(X"3", 4.1 ms),
(X"3", 100 us),
(X"3", 100 us),
(X"2", 100 us));
-- user commands
type t_user_command is record
rs : std_logic;
data: std_logic_vector(7 downto 0);
end record;
type t_user_commands is array (0 to 3) of t_user_command;
signal user_commands : t_user_commands := (
('0', X"01"), -- Display Clear command
('0', X"02"), -- Return Home command
('1', X"41"),
('1', X"5A"));
begin
-- TODO: check ready signal handling
uut: hd44780_iface
generic map (time_base_period => time_base_period)
port map (
clk => clk,
time_base => time_base,
db => db,
rs => rs,
strb => strb,
rdy => ready,
lcd_e => lcd_e,
lcd_rs => lcd_rs,
lcd_rw => lcd_rw,
lcd_d => lcd_d);
-- Clock process definitions
clk_process : process
variable i : integer;
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
time_base_process : process
begin
time_base <= '0';
wait for clk_period * (time_base_ratio - 1);
time_base <= '1';
wait for clk_period;
end process;
user_process : process
variable minimum_delay: time;
begin
-- note: we can't progress on the same edge when ready goes '1'
wait until ready = '1' and falling_edge(clk);
for i in user_commands'low to user_commands'high loop
rs <= user_commands(i).rs;
db <= user_commands(i).data;
strb <= '1';
wait for clk_period;
strb <= '0';
-- after one clk period 'ready' should be low
assert ready = '0' report "ready not low after submitting a byte" severity error;
wait until ready = '1';
-- ensure enough time was given for the command to execute
if user_commands(i).data = B"00000001" or user_commands(i).data(7 downto 1) = B"0000001" then
-- Clear Display or Return Home
minimum_delay := long_cmd_delay;
else
minimum_delay := normal_cmd_delay;
end if;
assert lcd_e = '0' and lcd_e'last_event > minimum_delay
report "command execution time not respected" severity error;
wait until falling_edge(clk);
end loop;
-- TODO: stop clocks to terminate simulation
wait until False;
end process;
t_lcd_timing : process
variable e_prev : time;
variable e_start : time := 0 ns;
begin
-- wait for E raising edge
wait until lcd_e = '1';
e_prev := e_start;
e_start := now;
assert e_start > min_power_up_delay report "initial power-up delay time violated" severity error;
-- check minimum cycle time
if e_prev /= 0 ns then
assert e_start - e_prev > min_e_cycle_time report "lcd_e minimum cycle time violated" severity error;
end if;
-- check setup time
assert lcd_rs'stable(min_addr_setup_time) report "lcd_rs setup time violated" severity error;
assert lcd_d'stable(min_data_setup_time) report "lcd_d setup time violated" severity error;
-- wait for E falling edge, check pulse width
wait until lcd_e = '0';
assert now - e_start > min_e_pulse_width report "lcd_e minimum pulse width violated" severity error;
-- check hold time
assert lcd_rs'stable(min_addr_hold_time) report "lcd_rs hold time violated" severity error;
assert lcd_d'stable(min_data_hold_time) report "lcd_d hold time violated" severity error;
end process;
t_lcd_init : process
variable cmd_start : time;
begin
wait until lcd_e = '1';
assert now > min_power_up_delay report "initial power-up delay time violated" severity error;
for i in init_sequence'low to init_sequence'high loop
wait until lcd_e = '0';
cmd_start := now;
assert lcd_d = init_sequence(i).data report "invalid init sequence" severity error;
-- check enough time is given for each command to execute
wait until lcd_e = '1';
assert now - cmd_start >= init_sequence(i).delay report "init sequence delay violation" severity error;
end loop;
-- when we get here, lcd_e is '1' - first user command was just submitted (high nibble)
wait until False;
end process;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:23:47 10/31/2013
-- Design Name:
-- Module Name: if_id_reg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------library IEEE;
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity IF_ID_REG is
port(
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
ID_STALL: in std_logic;
IF_ID_FLUSH: in std_logic;
PC_ADDR_IN: in STD_LOGIC_VECTOR(31 downto 0);
INST_REG_IN : in STD_LOGIC_VECTOR(31 downto 0);
PC_ADDR_OUT : out STD_LOGIC_VECTOR(31 downto 0);
INST_REG_OUT : out STD_LOGIC_VECTOR(31 downto 0)
);
end IF_ID_REG;
architecture IF_ID_REG_ARC of IF_ID_REG is
begin
process(Clk,Reset)
begin
if RESET = '1' then
INST_REG_OUT <= (others => '0');
PC_ADDR_OUT <= (others => '0');
elsif (Clk'event and Clk ='1') then
if IF_ID_FLUSH = '1' then
INST_REG_OUT <= (others =>'0');
PC_ADDR_OUT <= (others =>'0');
else
PC_ADDR_OUT <= PC_ADDR_IN;
INST_REG_OUT <= INST_REG_IN;
end if;
end if;
end process;
end IF_ID_REG_ARC; |
architecture RTL of FIFO is
begin
-- These are passing
a <= '0' when c = '0' else
'1';
a <= '0' when c = '0' else-- Comment
'1' when c = '1' else -- comment
'0' when d = '1' else
'1';
-- Violations below
a <= '0' when c = '0' else
'1' when c = '1' else
'0' when d = '1' else
'1';
a <= '0' when c = '0' else
'1' when c = '1' else
'0' when d =
'1' else
'1';
a <= '0' when c = '0' else
'1' when c =
'1' else
'0' when d = '1' else
'1';
end architecture RTL;
|
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-07B2.vhd
-- Creation Date: 01/11/09
-- Description:
-- S Register
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Change GT_CS_OPT to level-triggered latch
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
-- use work.all;
ENTITY SReg IS
port
(
SA : IN STD_LOGIC; -- 01C
CS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
CD : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
N_Z_BUS : IN STD_LOGIC_VECTOR(0 to 7);
Z_BUS0, CARRY_0, Z_BUS_HI_0, Z_BUS_LO_0 : IN STD_LOGIC; -- 06B
GT_CARRY_TO_S3 : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(0 to 7);
GT_Z_BUS_TO_S : OUT STD_LOGIC;
S_REG_RST : OUT STD_LOGIC;
CTRL_REG_RST : IN STD_LOGIC; -- 01C
MAN_STOR_PWR : IN STD_LOGIC; -- 03D
STORE_S_REG_RST : IN STD_LOGIC; -- 03D
E_SW_SEL_S : IN STD_LOGIC; -- 04C
MACH_RST_2C : IN STD_LOGIC; -- 06B
T_REQUEST : IN STD_LOGIC; -- 10BC6
FB_K_T2_PULSE : OUT STD_LOGIC;
CS_DECODE_X001 : OUT STD_LOGIC; -- 03C
BASIC_CS_0 : OUT STD_LOGIC; -- 03C
P1, T1, T2, T3, T4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END SReg;
ARCHITECTURE FMD OF SReg IS
signal SETS, RESETS : STD_LOGIC_VECTOR(0 to 7);
signal CS_X000,CS_X001,CS_X010,CS_X011,CS_X100,CS_X101,CS_X110,CS_X111,CS_X01X,CS_X0X1,CS_0XXX,CS_1XXX : STD_LOGIC;
signal CD_0110 : STD_LOGIC;
signal GT_CS_OPT_DECODER, GT_CS_BASIC_DECODER : STD_LOGIC;
signal BASIC_NOT_CS_0, sBASIC_CS_0 : STD_LOGIC;
signal sGT_Z_BUS_TO_S : STD_LOGIC;
signal sS_REG_RST : STD_LOGIC;
signal GT_CS_OPT_Set,GT_CS_OPT_Reset : STD_LOGIC;
signal S_REG_Set,S_REG_Reset : STD_LOGIC_VECTOR(0 to 7);
BEGIN
-- Fig 5-07B
CS_X000 <= '1' when CS(1 to 3)="000" else '0';
CS_X001 <= '1' when CS(1 to 3)="001" else '0';
CS_DECODE_X001 <= CS_X001;
CS_X010 <= '1' when CS(1 to 3)="010" else '0';
CS_X011 <= '1' when CS(1 to 3)="011" else '0';
CS_X100 <= '1' when CS(1 to 3)="100" else '0';
CS_X101 <= '1' when CS(1 to 3)="101" else '0';
CS_X110 <= '1' when CS(1 to 3)="110" else '0';
CS_X111 <= '1' when CS(1 to 3)="111" else '0';
CS_X01X <= '1' when CS(1 to 2)="01" else '0';
CS_X0X1 <= '1' when CS(1)='0' and CS(3)='1' else '0';
CS_0XXX <= '1' when CS(0)='0' else '0';
CS_1XXX <= '1' when CS(0)='1' else '0';
GT_CS_OPT_Set <= SA and P1;
GT_CS_OPT_Reset <= CTRL_REG_RST or T1;
-- GT_CS_OPT: FLE port map(GT_CS_OPT_Set, GT_CS_OPT_Reset, clk, GT_CS_OPT_DECODER); -- AB3E5
GT_CS_OPT: entity work.FLL port map(S=>GT_CS_OPT_Set, R=>GT_CS_OPT_Reset, Q=>GT_CS_OPT_DECODER); -- AB3E5
GT_CS_BASIC_DECODER <= not GT_CS_OPT_DECODER; -- AB3E5
BASIC_NOT_CS_0 <= GT_CS_BASIC_DECODER and CS_0XXX; -- AA3L5 Could be" GT_CS_BASIC_DECODER and not CS(0)"
sBASIC_CS_0 <= GT_CS_BASIC_DECODER and CS_1XXX; -- AA3L5 Could be "GT_CS_BASIC_DECODER and CS(0)"
BASIC_CS_0 <= sBASIC_CS_0;
FB_K_T2_PULSE <= sBASIC_CS_0 and T2 and CS_X110; -- AA3F7, AA3E3
CD_0110 <= '1' when CD="0110" else '0'; -- AA3B7, AA3J6
sGT_Z_BUS_TO_S <= (CD_0110 and T4) or (MAN_STOR_PWR and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
GT_Z_BUS_TO_S <= sGT_Z_BUS_TO_S;
sS_REG_RST <= (CD_0110 and T3) or (STORE_S_REG_RST and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
S_REG_RST <= sS_REG_RST;
SETS(0) <= CS_X111 and BASIC_NOT_CS_0; -- AA3G7
SETS(1) <= T_REQUEST and CS_X101 and BASIC_NOT_CS_0; -- AA3G7
SETS(2) <= CS_X001 and not Z_BUS0 and sBASIC_CS_0; -- AA3H7
SETS(3) <= GT_CARRY_TO_S3 and CARRY_0; -- AA3H7
SETS(4) <= BASIC_NOT_CS_0 and CS_X01X and Z_BUS_HI_0; -- AA3J7
SETS(5) <= BASIC_NOT_CS_0 and CS_X0X1 and Z_BUS_LO_0; -- AA3J7
SETS(6) <= CS_X011 and sBASIC_CS_0; -- AA3K7
SETS(7) <= CS_X101 and sBASIC_CS_0; -- AA3K7
RESETS(0) <= CS_X110 and BASIC_NOT_CS_0; -- AA3G7
RESETS(1) <= CS_X101 and not T_REQUEST and BASIC_NOT_CS_0; -- AA3G7
RESETS(2) <= CS_X000 and sBASIC_CS_0; -- AA3H7
RESETS(3) <= not CARRY_0 and GT_CARRY_TO_S3; -- AA3H7
RESETS(4) <= (BASIC_NOT_CS_0 and not Z_BUS_HI_0 and CS_X01X) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
RESETS(5) <= (BASIC_NOT_CS_0 and not Z_BUS_LO_0 and CS_X0X1) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
RESETS(6) <= sBASIC_CS_0 and CS_X010; -- AA3K7
RESETS(7) <= sBASIC_CS_0 and CS_X100; -- AA3K7
S_REG_Set <= mux(sGT_Z_BUS_TO_S,not N_Z_BUS) or mux(T4,SETS); -- ?? "T4 and not T1" to prevent erroneous S4 value
S_REG_Reset <= (S'range=>sS_REG_RST) or mux(T4,RESETS); -- ?? "T4 and not T1" to prevent erroneous S4 value
S_REG: FLVL port map(S_REG_Set, S_REG_Reset, S); -- AA3G7, AA3H7, AA3J7, AA3K7
END FMD;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Author: Richard Pender, Pender Electronic Design
-- Description: Clock generators for Virtex and Virtex-2 fpgas
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.CLKDLL;
use unisim.BUFGDLL;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture rtl of clkgen_virtex is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component CLKDLL
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic;
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, dll0rst, dll0lock, dll1lock : std_logic;
signal dll1rst : std_logic_vector(0 to 3);
signal clk0B, clkint, CLK2XL, CLKDV, CLK180, pciclkint : std_logic;
begin
gnd <= '0'; clk <= clk_i; clkn <= not clk_i;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0rst <= not cgi.pllrst;
dll0 : CLKDLL
port map (CLKIN => clkint, CLKFB => clk_k, CLK0 => clk_j, CLK180 => CLK180,
CLK2X => CLK2XL, CLKDV => CLKDV, LOCKED => dll0lock, RST => dll0rst);
clk0B <= CLK2XL when clk_mul/clk_div = 2
else CLKDV when clk_div/clk_mul = 2 else clk_j;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB = 0) generate
cgo.clklock <= dll1lock;
dll1 : CLKDLL
port map (CLKIN => clk_i, CLKFB => cgi.pllref, RST => dll1rst(0), CLK0 => sdclk,
CLK2X => clk2x, LOCKED => dll1lock);
rstdel : process (clk_i)
begin
if dll0lock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_i) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if not ((SDRAMEN /= 0) and (NOCLKFB = 0)) generate
sdclk <= clk_i; cgo.clklock <= dll0lock;
end generate;
cgo.pcilock <= '1';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.IBUFG;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex2 clock generator ---------------------------------------
------------------------------------------------------------------
entity clkgen_virtex2 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex2 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IBUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint, pciclkl, pciclkfb, pciclk0 : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
p2 : if (PCIDLL /= 0) and ( PCIDLL /= 1) generate
x1 : IBUFG port map (I => pciclkint, O => pciclkl);
dll0 : DCM
generic map (CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => PCIDLL)
port map ( CLKIN => pciclkint, CLKFB => pciclkfb,
DSSEN => gnd, PSCLK => gnd,
RST => gnd, PSEN => gnd, PSINCDEC => gnd, CLK0 => pciclk0);
x2 : BUFG port map (I => pciclk0, O => pciclkfb);
pciclk <= pciclkfb;
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
bufg3 : BUFG port map (I => clk_x, O => clk_i2);
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex2" & ": virtex-2 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex2" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkmul_virtex2 is
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end;
architecture struct of clkmul_virtex2 is
-- attribute CLKFX_MULTIPLY : string;
-- attribute CLKFX_DIVIDE : string;
-- attribute CLKIN_PERIOD : string;
--
-- attribute CLKFX_MULTIPLY of dll0: label is "5";
-- attribute CLKFX_DIVIDE of dll0: label is "4";
-- attribute CLKIN_PERIOD of dll0: label is "20";
--
-- attribute CLKFX_MULTIPLY of dll1: label is "4";
-- attribute CLKFX_DIVIDE of dll1: label is "4";
-- attribute CLKIN_PERIOD of dll1: label is "25";
--
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, clk_l : std_logic;
signal clk0B, clk_FB, dll0rst, lock : std_logic;
begin
gnd <= '0'; clk <= clk_i;
dll0rst <= not resetin;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkin, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
LOCKED => resetout, CLKFX => clk0B );
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_spartan3 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 50000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_spartan3 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= not clk_i when (CLK2XEN = 0) else not clk_p;
clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_j;
clk2xu <= clk_k;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_x, O => clk_k);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLK_FEEDBACK => "2X")
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_k;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_spartan3e" & ": spartan3/e sdram/pci clock generator, version " & tost(VERSION),
"clkgen_spartan3e" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
|
entity repro is
end repro;
architecture behav of repro is
signal clk : bit;
signal cyc: bit;
signal wen : bit;
signal lw : bit;
begin
-- psl default clock is clk;
-- psl c1: assert always lw -> cyc and (next not(wen))
-- report "error";
end;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLROM_3_14.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_14
-- Source Path: hdl_ofdm_tx/ifft/TWDLROM_3_14
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY TWDLROM_3_14 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_vld : OUT std_logic
);
END TWDLROM_3_14;
ARCHITECTURE rtl OF TWDLROM_3_14 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#4000#, 16), to_signed(16#3B21#, 16)); -- sfix16 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#0000#, 16), to_signed(-16#187E#, 16)); -- sfix16 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_14_re_tmp : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_14_im_tmp : signed(15 DOWNTO 0); -- sfix16_En14
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#1#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE addr_cast : unsigned(3 DOWNTO 0);
VARIABLE c : unsigned(1 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt;
Radix22TwdlMapping_phase_next <= Radix22TwdlMapping_phase;
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
c := unsigned'(Radix22TwdlMapping_cnt(0) & Radix22TwdlMapping_cnt(1));
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(c, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(c, 4) sll 1;
ELSE
addr_cast := resize(c, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (addr_cast sll 1) + addr_cast;
END IF;
IF dout_2_vld = '1' THEN
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000004#, 2);
END IF;
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(15 DOWNTO 0);
VARIABLE twdlIn_im : signed(15 DOWNTO 0);
VARIABLE cast : signed(16 DOWNTO 0);
VARIABLE cast_0 : signed(16 DOWNTO 0);
VARIABLE cast_1 : signed(16 DOWNTO 0);
VARIABLE cast_2 : signed(16 DOWNTO 0);
VARIABLE cast_3 : signed(16 DOWNTO 0);
VARIABLE cast_4 : signed(16 DOWNTO 0);
VARIABLE cast_5 : signed(16 DOWNTO 0);
VARIABLE cast_6 : signed(16 DOWNTO 0);
VARIABLE cast_7 : signed(16 DOWNTO 0);
VARIABLE cast_8 : signed(16 DOWNTO 0);
VARIABLE cast_9 : signed(16 DOWNTO 0);
VARIABLE cast_10 : signed(16 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "010" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "100" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(16#2D41#, 16);
WHEN OTHERS =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 17);
cast_0 := - (cast);
twdlIn_re := cast_0(15 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 17);
cast_6 := - (cast_5);
twdlIn_im := cast_6(15 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 17);
cast_8 := - (cast_7);
twdlIn_im := cast_8(15 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 17);
cast_2 := - (cast_1);
twdlIn_re := cast_2(15 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 17);
cast_4 := - (cast_3);
twdlIn_re := cast_4(15 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 17);
cast_10 := - (cast_9);
twdlIn_im := cast_10(15 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_14_re_tmp <= twdlIn_re;
twdl_3_14_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_14_re <= std_logic_vector(twdl_3_14_re_tmp);
twdl_3_14_im <= std_logic_vector(twdl_3_14_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_14_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl_3_14_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
--
-- \file conv_filter3x3.vhd
--
-- Implements a configurable 3x3 convolution kernel
--
-- \author Andreas Agne <[email protected]>
-- \date 21.11.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity conv_filter3x3 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ien : in STD_LOGIC;
shift_in : in STD_LOGIC_VECTOR (23 downto 0);
shift_out : out STD_LOGIC_VECTOR (7 downto 0);
kernel : in STD_LOGIC_VECTOR (80 downto 0) -- 9x9
);
end conv_filter3x3;
architecture Behavioral of conv_filter3x3 is
type t_state is ( STATE_ADD,
STATE_SHIFT_OUT);
signal state : t_state;
signal row_a : std_logic_vector(23 downto 0);
signal row_b : std_logic_vector(23 downto 0);
signal row_c : std_logic_vector(23 downto 0);
signal pixels : std_logic_vector(71 downto 0); -- 9 pixels x 8 bit
signal p0,p1,p2,p3,p4,p5,p6,p7,p8 : std_logic_vector(7 downto 0);
signal k0,k1,k2,k3,k4,k5,k6,k7,k8 : std_logic_vector(8 downto 0);
signal m0,m1,m2,m3,m4,m5,m6,m7,m8 : std_logic_vector(15 downto 0);
function my_sum(sign : std_logic_vector(8 downto 0);
m0 : std_logic_vector(15 downto 0);
m1 : std_logic_vector(15 downto 0);
m2 : std_logic_vector(15 downto 0);
m3 : std_logic_vector(15 downto 0);
m4 : std_logic_vector(15 downto 0);
m5 : std_logic_vector(15 downto 0);
m6 : std_logic_vector(15 downto 0);
m7 : std_logic_vector(15 downto 0);
m8 : std_logic_vector(15 downto 0)) return std_logic_vector is
variable s : std_logic_vector(19 downto 0);
variable s0 : std_logic_vector(19 downto 0);
variable s1 : std_logic_vector(19 downto 0);
variable s2 : std_logic_vector(19 downto 0);
variable s3 : std_logic_vector(19 downto 0);
variable s4 : std_logic_vector(19 downto 0);
variable s5 : std_logic_vector(19 downto 0);
variable result : std_logic_vector(7 downto 0);
begin
s0 := X"20000";
s1 := X"20000";
s2 := X"20000";
s3 := X"20000";
if sign(0) = '0' then s0 := s0 + m0(15 downto 4);
else s0 := s0 - m0(15 downto 4); end if;
if sign(1) = '0' then s0 := s0 + m1(15 downto 4);
else s0 := s0 - m1(15 downto 4); end if;
if sign(2) = '0' then s1 := s1 + m2(15 downto 4);
else s1 := s1 - m2(15 downto 4); end if;
if sign(3) = '0' then s1 := s1 + m3(15 downto 4);
else s1 := s1 - m3(15 downto 4); end if;
if sign(4) = '0' then s2 := s2 + m4(15 downto 4);
else s2 := s2 - m4(15 downto 4); end if;
if sign(5) = '0' then s2 := s2 + m5(15 downto 4);
else s2 := s2 - m5(15 downto 4); end if;
if sign(6) = '0' then s3 := s3 + m6(15 downto 4);
else s3 := s3 - m6(15 downto 4); end if;
if sign(7) = '0' then s3 := s3 + m7(15 downto 4);
else s3 := s3 - m7(15 downto 4); end if;
if sign(8) = '0' then s3 := s3 + m8(15 downto 4);
else s3 := s3 - m8(15 downto 4); end if;
s4 := s0 + s1;
s5 := s2 + s3;
s := s4 + s5;
if s > X"800FF" then
result := X"FF";
elsif s < X"80000" then
result := X"00";
else
result := s(7 downto 0);
end if;
return result;
end function;
begin
pixels <= row_a & row_b & row_c;
p0 <= pixels(1*8-1 downto 0*8);
p1 <= pixels(2*8-1 downto 1*8);
p2 <= pixels(3*8-1 downto 2*8);
p3 <= pixels(4*8-1 downto 3*8);
p4 <= pixels(5*8-1 downto 4*8);
p5 <= pixels(6*8-1 downto 5*8);
p6 <= pixels(7*8-1 downto 6*8);
p7 <= pixels(8*8-1 downto 7*8);
p8 <= pixels(9*8-1 downto 8*8);
k0 <= kernel(1*9-1 downto 0*9);
k1 <= kernel(2*9-1 downto 1*9);
k2 <= kernel(3*9-1 downto 2*9);
k3 <= kernel(4*9-1 downto 3*9);
k4 <= kernel(5*9-1 downto 4*9);
k5 <= kernel(6*9-1 downto 5*9);
k6 <= kernel(7*9-1 downto 6*9);
k7 <= kernel(8*9-1 downto 7*9);
k8 <= kernel(9*9-1 downto 8*9);
shift : process(clk, rst)
variable sum : std_logic_vector(15 downto 0);
begin
if rising_edge(clk) then
if ien = '1' then
row_a <= shift_in;
row_b <= row_a;
row_c <= row_b;
end if;
m0 <= p0*k0(7 downto 0);
m1 <= p1*k1(7 downto 0);
m2 <= p2*k2(7 downto 0);
m3 <= p3*k3(7 downto 0);
m4 <= p4*k4(7 downto 0);
m5 <= p5*k5(7 downto 0);
m6 <= p6*k6(7 downto 0);
m7 <= p7*k7(7 downto 0);
m8 <= p8*k8(7 downto 0);
shift_out <= my_sum(k0(8)&k1(8)&k2(8)&k3(8)&k4(8)&k5(8)&k6(8)&k7(8)&k8(8),
m0 ,m1 ,m2 ,m3 ,m4 ,m5 ,m6 ,m7 ,m8);
end if;
end process;
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_RS232 IS
END TB_RS232;
ARCHITECTURE behavior OF TB_RS232 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RS232
PORT(
clk : IN std_logic;
Entrada_8bits : IN std_logic_vector(7 downto 0);
Activador_Envio_Mensaje : IN std_logic;
Salida_1bit : OUT std_logic;
Entrada_1bit : IN std_logic;
Mensaje_8bits : OUT std_logic_vector(7 downto 0);
Activador_Entrega_Mensaje : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal Entrada_8bits : std_logic_vector(7 downto 0) := (others => '0');
signal Activador_Envio_Mensaje : std_logic := '0';
signal Entrada_1bit : std_logic := '0';
--Outputs
signal Salida_1bit : std_logic;
signal Mensaje_8bits : std_logic_vector(7 downto 0);
signal Div_Frec_AUX : STD_LOGIC;
signal Activador_Entrega_Mensaje : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RS232 PORT MAP (
clk => clk,
Entrada_8bits => Entrada_8bits,
Activador_Envio_Mensaje => Activador_Envio_Mensaje,
Salida_1bit => Salida_1bit,
Entrada_1bit => Entrada_1bit,
Mensaje_8bits => Mensaje_8bits,
Activador_Entrega_Mensaje => Activador_Entrega_Mensaje
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
Entrada_8bits <= "00110011";
Activador_Envio_Mensaje <= '0';
Entrada_1bit <= '1';
wait for 0.2 ms;
Activador_Envio_Mensaje <= '1';
wait for 0.10416 ms;
Activador_Envio_Mensaje <= '0';
-- IDLE --
Entrada_1bit <= '1';
wait for 0.10416 ms;
Entrada_1bit <= '1';
wait for 0.10416 ms;
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Entrada_1bit <= '0';
wait for 0.10416 ms;
-- BIT Numero 1 --
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 2
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 3
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 4
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 5
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 6
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 7
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 8
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Entrada_1bit <= '0';
wait for 0.10416 ms;
-- BIT DE FINALIZACION --
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- BIT DE FINALIZACION --
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- IDLE --
Entrada_1bit <= '1';
wait for 0.10416 ms;
Entrada_1bit <= '1';
wait for 0.10416 ms;
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Entrada_1bit <= '0';
wait for 0.10416 ms;
-- BIT Numero 1 --
Entrada_1bit <= '0';
wait for 0.10416 ms;
-- 2
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 3
Entrada_1bit <= '0';
wait for 0.10416 ms;
-- 4
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 5
Entrada_1bit <= '0';
wait for 0.10416 ms;
-- 6
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 7
Entrada_1bit <= '0';
wait for 0.10416 ms;
-- 8
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Entrada_1bit <= '0';
wait for 0.10416 ms;
-- BIT DE FINALIZACION --
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- BIT DE FINALIZACION --
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- IDLE --
Entrada_1bit <= '1';
wait for 0.10416 ms;
Entrada_1bit <= '1';
wait for 0.10416 ms;
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Entrada_1bit <= '0';
wait for 0.10416 ms;
-- BIT Numero 1 --
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 2
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 3
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 4
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 5
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 6
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 7
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- 8
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Entrada_1bit <= '0';
wait for 0.10416 ms;
-- BIT DE FINALIZACION --
Entrada_1bit <= '1';
wait for 0.10416 ms;
-- BIT DE FINALIZACION --
Entrada_1bit <= '1';
wait for 0.10416 ms;
Entrada_1bit <= '1';
wait for 10 ms;
Entrada_1bit <= '0';
wait for 2 ms;
Entrada_1bit <= '1';
wait;
end process;
END;
|
architecture RTL of FIFO is
begin
-- Test generate_statement_body
LABEL_1 : for i in 0 to 7 generate
signal blah : std_logic;
begin
a <= blah;
end;
end generate LABEL3;
-- Test generate_statement_body
LABEL_2 : for i in 0 to 7 generate
begin
a <= blah;
end;
end generate LABEL3;
-- Test generate_statement_body
LABEL_3 : for i in 0 to 7 generate
begin
a <= blah;
end generate LABEL3;
end architecture RTL;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.methods_pkg.all;
use work.string_methods_pkg.all;
use work.data_queue_pkg.all;
package data_stack_pkg is
shared variable shared_data_stack : t_data_queue;
------------------------------------------
-- uvvm_stack_init
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the stack.
--
-- - Parameters:
-- - buffer_size_in_bits (natural) - The size of the stack
--
-- - Returns: The index of the initiated stack (natural).
-- Returns 0 on error.
--
impure function uvvm_stack_init(
buffer_size_in_bits : natural
) return natural;
------------------------------------------
-- uvvm_stack_init
------------------------------------------
-- This procedure allocates space in the buffer at the given buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be initialized.
-- - buffer_size_in_bits (natural) - The size of the stack
--
procedure uvvm_stack_init(
buffer_index : natural;
buffer_size_in_bits : natural
);
------------------------------------------
-- uvvm_stack_push
------------------------------------------
-- This procedure puts data into a stack with index buffer_idx.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the stack size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure uvvm_stack_push(
buffer_index : natural;
data : std_logic_vector
);
------------------------------------------
-- uvvm_stack_pop
------------------------------------------
-- This function returns the data from the stack
-- and removes the returned data from the stack.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the stack (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty stack is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the stack size is allowed
-- but triggers a TB_WARNING.
--
--
impure function uvvm_stack_pop(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_stack_flush
------------------------------------------
-- This procedure empties the stack given
-- by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be flushed.
--
procedure uvvm_stack_flush(
buffer_index : natural
);
------------------------------------------
-- uvvm_stack_peek
------------------------------------------
-- This function returns the data from the stack
-- without removing it.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the stack. The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty stack is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the stack size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function uvvm_stack_peek(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_stack_get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the stack given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
--
-- - Returns: The number of elements occupying the stack (natural).
--
--
impure function uvvm_stack_get_count(
buffer_idx : natural
) return natural;
------------------------------------------
-- uvvm_stack_get_max_count
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the stack given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the stack (natural).
--
--
impure function uvvm_stack_get_max_count(
buffer_index : natural
) return natural;
end package data_stack_pkg;
package body data_stack_pkg is
impure function uvvm_stack_init(
buffer_size_in_bits : natural
) return natural is
begin
return shared_data_stack.init_queue(buffer_size_in_bits, "UVVM_STACK");
end function;
procedure uvvm_stack_init(
buffer_index : natural;
buffer_size_in_bits : natural
) is
begin
shared_data_stack.init_queue(buffer_index, buffer_size_in_bits, "UVVM_STACK");
end procedure;
procedure uvvm_stack_push(
buffer_index : natural;
data : std_logic_vector
) is
begin
shared_data_stack.push_back(buffer_index,data);
end procedure;
impure function uvvm_stack_pop(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_stack.pop_back(buffer_index, entry_size_in_bits);
end function;
procedure uvvm_stack_flush(
buffer_index : natural
) is
begin
shared_data_stack.flush(buffer_index);
end procedure;
impure function uvvm_stack_peek(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_stack.peek_back(buffer_index, entry_size_in_bits);
end function;
impure function uvvm_stack_get_count(
buffer_idx : natural
) return natural is
begin
return shared_data_stack.get_count(buffer_idx);
end function;
impure function uvvm_stack_get_max_count(
buffer_index : natural
) return natural is
begin
return shared_data_stack.get_queue_count_max(buffer_index);
end function;
end package body data_stack_pkg;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- Architecture level constants
library ieee;
use ieee.std_logic_1164.all;
library isa;
use isa.or1k_pkg.all;
package cpu_arch_pkg is
constant cpu_context_bits : natural := or1k_cid_bits;
constant cpu_vaddr_bits : natural := or1k_vaddr_bits;
constant cpu_paddr_bits : natural := or1k_paddr_bits;
constant cpu_log2_word_bytes : natural := or1k_log2_word_bytes;
constant cpu_word_bytes : natural := or1k_word_bytes;
constant cpu_log2_inst_bytes : natural := or1k_log2_inst_bytes;
constant cpu_inst_bytes : natural := or1k_inst_bytes;
constant cpu_rfaddr_bits : natural := or1k_rfaddr_bits;
constant cpu_wmask_bits : natural := or1k_wmask_bits;
constant cpu_log2_data_size_bits : natural := or1k_log2_data_size_bits;
constant cpu_word_bits : natural := or1k_word_bits;
constant cpu_inst_bits : natural := or1k_inst_bits;
constant cpu_wvaddr_bits : natural := or1k_wvaddr_bits;
constant cpu_ivaddr_bits : natural := or1k_ivaddr_bits;
constant cpu_wpaddr_bits : natural := or1k_wpaddr_bits;
constant cpu_ipaddr_bits : natural := or1k_ipaddr_bits;
constant cpu_shift_bits : natural := or1k_shift_bits;
subtype cpu_vaddr_type is or1k_vaddr_type;
subtype cpu_paddr_type is or1k_paddr_type;
subtype cpu_wvaddr_type is or1k_wvaddr_type;
subtype cpu_ivaddr_type is or1k_ivaddr_type;
subtype cpu_wpaddr_type is or1k_wpaddr_type;
subtype cpu_ipaddr_type is or1k_ipaddr_type;
subtype cpu_word_bytes_type is or1k_word_bytes_type;
subtype cpu_word_type is or1k_word_type;
subtype cpu_dword_type is or1k_dword_type;
subtype cpu_inst_bytes_type is or1k_inst_bytes_type;
subtype cpu_inst_type is or1k_inst_type;
subtype cpu_rfaddr_type is or1k_rfaddr_type;
subtype cpu_shift_type is or1k_shift_type;
subtype cpu_wmask_type is or1k_wmask_type;
subtype cpu_log2_data_size_type is or1k_log2_data_size_type;
end package;
|
entity TESTCASE is
end entity TESTCASE;
architecture PROBLEM of TESTCASE is
type ENUMERATION_TYPE is (VALUE1, VALUE2);
constant SOME_VAR : integer := ENUMERATION_TYPE'length;
begin
end architecture PROBLEM;
|
entity TESTCASE is
end entity TESTCASE;
architecture PROBLEM of TESTCASE is
type ENUMERATION_TYPE is (VALUE1, VALUE2);
constant SOME_VAR : integer := ENUMERATION_TYPE'length;
begin
end architecture PROBLEM;
|
entity TESTCASE is
end entity TESTCASE;
architecture PROBLEM of TESTCASE is
type ENUMERATION_TYPE is (VALUE1, VALUE2);
constant SOME_VAR : integer := ENUMERATION_TYPE'length;
begin
end architecture PROBLEM;
|
library ieee;
use ieee.std_logic_1164.all;
entity and6 is
port (i0, i1, i2, i3, i4, i5 : std_logic;
o : out std_logic);
end and6;
architecture behav of and6 is
signal t1, t2 : std_logic;
begin
a1: entity work.and3
port map (i0, i1, i2, t1);
a2: entity work.and3
port map (i3, i4, i5, t2);
o <= t1 and t2;
end behav;
|
------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
------------------------------------------------------------------------------
--
-- $Id: clk_lcd_cyc_cntr.vhd,v 1.1 2008-11-07 00:48:12 jwdonal Exp $
--
-- Description:
-- Counts the number of CLK_LCD cycles that have occured after C_VSYNC_TVS
-- lines have passed. The output vector is then used by ENAB and the IMAGE
-- generator for pulse and data timing. This method allows for a single
-- common counter for both the ENAB and image controller blocks. THe less
-- efficient way would be to have two counters - one for each block.
--
-- Structure:
-- - xupv2p.ucf
-- - components.vhd
-- - lq057q3dc02_tb.vhd
-- - lq057q3dc02.vhd
-- - dcm_sys_to_lcd.xaw
-- - video_controller.vhd
-- - enab_control.vhd
-- - hsyncx_control.vhd
-- - vsyncx_control.vhd
-- - clk_lcd_cyc_cntr.vhd
-- - image_gen_bram.vhd
-- - image_gen_bram_red.xco
-- - image_gen_bram_green.xco
-- - image_gen_bram_blue.xco
--
------------------------------------------------------------------------------
--
-- Naming Conventions:
-- active low signals "*x"
-- clock signal "CLK_*"
-- reset signal "RST"
-- generic/constant "C_*"
-- user defined type "TYPE_*"
-- state machine next state "*_ns"
-- state machine current state "*_cs""
-- pipelined signals "*_d#"
-- register delay signals "*_p#"
-- signal "*_sig"
-- variable "*_var"
-- storage register "*_reg"
-- clock enable signals "*_ce"
-- internal version of output port used as connecting wire "*_wire"
-- input/output port "ALL_CAPS"
-- process "*_PROC"
--
------------------------------------------------------------------------------
--////////////////////--
-- LIBRARY INCLUSIONS --
--////////////////////--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--////////////////////--
-- ENTITY DECLARATION --
--////////////////////--
ENTITY clk_lcd_cyc_cntr IS
generic (
C_VSYNC_TVS,
C_LINE_NUM_WIDTH,
C_CLK_LCD_CYC_NUM_WIDTH,
C_ENAB_TEP,
C_ENAB_THE : POSITIVE
);
port (
RSTx,
CLK_LCD,
HSYNCx,
VSYNCx : IN std_logic;
LINE_NUM : IN std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0);
CLK_LCD_CYC_NUM : OUT std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0)
);
END ENTITY clk_lcd_cyc_cntr;
--////////////////////////--
-- ARCHITECTURE OF ENTITY --
--////////////////////////--
ARCHITECTURE clk_lcd_cyc_cntr_arch OF clk_lcd_cyc_cntr IS
constant C_NUM_LCD_LINES : positive := 240; -- number of drawable lines in the LCD
constant C_NUM_LCD_PIXELS : positive := 320; -- number of drawable pixels per line in the LCD
--Enables/disables counter for pixel/enab counter process
signal clk_cyc_cnt_en_sig : std_logic := '0';
--Stores the number of CLK_LCD cycles that have occurred
signal clk_cyc_num_reg : std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0) := (others => '0');
---------------------------------------------------------------
-- States for CLK_Cntr_cntrl_*_PROC
---------------------------------------------------------------
--INACTIVE_WAIT_1 => wait here until new screen or new line starts
--INACTIVE_WAIT_2 => wait for HSYNCx pulse to deactivate b/c THE is measured from rising edge of HSYNCx pulse
--INACTIVE_WAIT_TVS => wait for TVS timespec to pass
--INACTIVE_WAIT_THE => wait THE timespec to pass
--ACTIVE => enable clock cycle counter
type TYPE_CLK_Cntr_sts is ( INACTIVE_WAIT_1, INACTIVE_WAIT_2,
INACTIVE_WAIT_TVS, INACTIVE_WAIT_THE,
ACTIVE );
signal CLK_Cntr_cs : TYPE_CLK_Cntr_sts;
signal CLK_Cntr_ns : TYPE_CLK_Cntr_sts;
begin
--///////////////////////--
-- CONCURRENT STATEMENTS --
--///////////////////////--
CLK_LCD_CYC_NUM <= clk_cyc_num_reg;
------------------------------------------------------------------
-- Process Description:
-- This is finite state machine process 1 of 3 for counting the
-- number of CLK_LCD cycles that have passed which controls
-- the pixel and ENAB count value (clk_cyc_num_reg). This process
-- only controls the reset of the state and the "current state to
-- next state" assignment.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- CLK_Cntr_cs
--
-- Notes:
-- N/A
------------------------------------------------------------------
CLK_Cntr_cntrl_1_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
CLK_Cntr_cs <= INACTIVE_WAIT_1;
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
CLK_Cntr_cs <= CLK_Cntr_ns;
end if;
end process CLK_Cntr_cntrl_1_PROC;
------------------------------------------------------------------
-- Process Description:
-- This is finite state machine process 2 of 3 for counting the
-- number of CLK_LCD cycles that have passed which controls
-- the pixel and ENAB count value (clk_cyc_num_reg). This process
-- controls all of the state changes.
--
-- Inputs:
-- CLK_Cntr_cs
-- HSYNCx
-- VSYNCx
-- LINE_NUM
-- clk_cyc_num_reg
--
-- Outputs:
-- CLK_Cntr_ns
--
-- Notes:
-- N/A
------------------------------------------------------------------
CLK_Cntr_cntrl_2_PROC : process( CLK_Cntr_cs, HSYNCx, VSYNCx, LINE_NUM, clk_cyc_num_reg )
begin
case CLK_Cntr_cs is
when INACTIVE_WAIT_1 => -- once we are in WAIT_1 we are either going to (A) be completely finished drawing the screen or (B) go to the next line.
if( HSYNCx = '0' and VSYNCx = '0' ) then -- if new frame has begun
CLK_Cntr_ns <= INACTIVE_WAIT_TVS; -- go to next state (the reason we do not have to wait for HSYNCx to go high (i.e. go to state INACTIVE_WAIT_2) is b/c LINE_NUM will not change until HSYNCx has already gone high - therefore we do not need to enter WAIT_2 state waiting for HSYNCx to go high. We can just skip that state! :-))
elsif( HSYNCx = '0' and LINE_NUM < (C_VSYNC_TVS + 1) + (C_NUM_LCD_LINES - 1) ) then --if only a new line has begun, not a whole new frame. And only if we have not drawn all the lines already (there is a delay between the last line drawn to the screen and the next VSYNCx pulse!)
CLK_Cntr_ns <= INACTIVE_WAIT_2; -- Once HSYNCx is activated we need to wait for it to deactivate before couting 'THE' CLK_LCD cycles b/c THE timespec is measured from the rising edge of the HSYNCx pulse!!!
else
CLK_Cntr_ns <= INACTIVE_WAIT_1; -- we haven't drawn a full screen yet! Get ready to send another line of data when HSYNCx activates!
end if;
when INACTIVE_WAIT_2 => -- wait for HSYNCx pulse to be deactivated (rise)
if( HSYNCx = '1' ) then
CLK_Cntr_ns <= INACTIVE_WAIT_THE; -- Once HSYNCx is deactivated we need to wait THE CLK_LCD cycles before activating again
else
CLK_Cntr_ns <= INACTIVE_WAIT_2; -- keep waiting for HSYNCx pulse to disable
end if;
when INACTIVE_WAIT_TVS =>
if( LINE_NUM = C_VSYNC_TVS + 1 ) then -- if enough lines (HSYNCx pulses) have passed after the *falling* edge of VSYNCx pulse (timespec TVS). We need to start sending exactly on the 8th line (i.e. TVS + 1)!! If we start sending even one line before or even one line after the entire screen will not be drawn!
CLK_Cntr_ns <= INACTIVE_WAIT_THE; -- go to next state
else
CLK_Cntr_ns <= INACTIVE_WAIT_TVS; -- still inactive until _after_ 7 lines (HSYNCx pulses) have passed!
end if;
when INACTIVE_WAIT_THE =>
if( clk_cyc_num_reg = C_ENAB_THE - 1 ) then -- 0 to (THE - 1) = THE clocks!
CLK_Cntr_ns <= ACTIVE; -- go to next state (PHEW! We can finally start sending data!)
else
CLK_Cntr_ns <= INACTIVE_WAIT_THE; -- still inactive until after timespec THE has passed
end if;
when ACTIVE => -- Now that ENAB is active we want it to stay active for TEP CLK_LCD cycles
if( clk_cyc_num_reg = C_ENAB_THE + C_NUM_LCD_PIXELS - 1 ) then -- C_ENAB_THE to C_ENAB_THE + (320 - 1) = C_ENAB_TEP clocks!
CLK_Cntr_ns <= INACTIVE_WAIT_1; -- once TEP clocks have passed we disable ENAB!
else
CLK_Cntr_ns <= ACTIVE; --enable counter (whose value is used by ENAB controller and image generator)
end if;
when others => --UH OH! How did we get here???
CLK_Cntr_ns <= INACTIVE_WAIT_1;
end case;
end process CLK_Cntr_cntrl_2_PROC;
------------------------------------------------------------------
-- Process Description:
-- This is finite state machine process 3 of 3 for counting the
-- number of CLK_LCD cycles that have passed which controls
-- the pixel and ENAB count value (clk_cyc_num_reg). This process
-- only controls the change of output values based on the current
-- state.
--
-- Inputs:
-- CLK_Cntr_cs
--
-- Outputs:
-- clk_cyc_cnt_en_sig
--
-- Notes:
-- N/A
------------------------------------------------------------------
CLK_Cntr_cntrl_3_PROC : process( CLK_Cntr_cs )
begin
case CLK_Cntr_cs is
when INACTIVE_WAIT_1 => --reset counter when not sending data (will go to either TVS-wait if a new frame is starting or INACTIVE_WAIT_2 if just a new line is starting)
clk_cyc_cnt_en_sig <= '0';
when INACTIVE_WAIT_2 => --reset counter when not sending data (not a new frame, but we still need to wait for HSYNCx to go high, then go to THE)
clk_cyc_cnt_en_sig <= '0';
when INACTIVE_WAIT_TVS => --reset counter when waiting for 7 lines (TVS) to pass
clk_cyc_cnt_en_sig <= '0';
when INACTIVE_WAIT_THE => --count THE clock wait for ENAB
clk_cyc_cnt_en_sig <= '1';
when ACTIVE => --count number of pixels to send (320 pixels across)
clk_cyc_cnt_en_sig <= '1';
when others => --UH OH! How did we get here???
clk_cyc_cnt_en_sig <= '0';
end case;
end process CLK_Cntr_cntrl_3_PROC;
------------------------------------------------------------------
-- Process Description:
-- This process enables/disables the pixel/enab counter dependent
-- upon the value of clk_cyc_cnt_en_sig.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- clk_cyc_num_reg
--
-- Notes:
-- N/A
------------------------------------------------------------------
CLK_Cycle_Cntr_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
clk_cyc_num_reg <= (others => '0');
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
if( clk_cyc_cnt_en_sig = '1' ) then
clk_cyc_num_reg <= clk_cyc_num_reg + 1;
else
clk_cyc_num_reg <= (others => '0');
end if;
end if;
end process CLK_Cycle_Cntr_PROC;
END ARCHITECTURE clk_lcd_cyc_cntr_arch;
|
-------------------------------------------------------------------------------
-- Title : Input Conditioner
-- Project :
-------------------------------------------------------------------------------
-- File : input_conditioner.vhd
-- Author : Gustavo BM Bruno
-- Company :
-- Created : 2014-01-30
-- Last update: 2014-02-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Define the timing for the switch at the RFFE board and apply a
-- proper window at the switch to avoid the switching noise.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-01-30 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.genram_pkg.all;
entity input_conditioner is
generic (
--g_clk_freq : real := 120.0e6; -- System clock frequency
--g_sw_freq : real := 100.0e3; -- Desired switching frequency
g_sw_interval : natural := 1000;
g_input_width : natural := 16;
g_output_width : natural := 24;
g_window_width : natural := 24;
g_input_delay : natural := 2;
g_window_coef_file : string);
port (
reset_n_i : in std_logic; -- Reset data
clk_i : in std_logic; -- Main clock
adc_a_i : in std_logic_vector(g_input_width-1 downto 0);
adc_b_i : in std_logic_vector(g_input_width-1 downto 0);
adc_c_i : in std_logic_vector(g_input_width-1 downto 0);
adc_d_i : in std_logic_vector(g_input_width-1 downto 0);
switch_o : out std_logic; -- Switch position output
switch_en_i : in std_logic;
switch_delay_i : in std_logic_vector(15 downto 0);
a_o : out std_logic_vector(g_output_width-1 downto 0);
b_o : out std_logic_vector(g_output_width-1 downto 0);
c_o : out std_logic_vector(g_output_width-1 downto 0);
d_o : out std_logic_vector(g_output_width-1 downto 0);
dbg_cur_address_o : out std_logic_vector(31 downto 0));
end entity input_conditioner;
architecture structural of input_conditioner is
--constant c_mem_size : natural := natural(g_clk_freq/(g_sw_freq*2.0)) + 1;
constant c_mem_size : natural := g_sw_interval/2 + 1;
constant c_bus_size : natural := f_log2_size(c_mem_size);
signal cur_address : std_logic_vector(c_bus_size-1 downto 0) := (others => '0'); -- Current index for lookup table
signal window_factor : std_logic_vector(g_window_width-1 downto 0); -- Current value of the window
-- factor, signed int
component counter is
generic (
g_mem_size : natural;
g_bus_size : natural;
g_switch_delay : natural);
port (
clk_i : in std_logic;
index_o : out std_logic_vector(c_bus_size-1 downto 0);
ce_i : in std_logic;
switch_o : out std_logic;
switch_en_i : in std_logic;
switch_delay_i : in std_logic_vector(15 downto 0);
reset_n_i : in std_logic);
end component counter;
component generic_multiplier is
generic (
g_a_width : natural;
g_b_width : natural;
g_signed : boolean;
g_p_width : natural);
port (
a_i : in std_logic_vector(g_a_width-1 downto 0);
b_i : in std_logic_vector(g_b_width-1 downto 0);
p_o : out std_logic_vector(g_p_width-1 downto 0);
clk_i : in std_logic;
reset_n_i : in std_logic);
end component generic_multiplier;
begin
cmp_lut : generic_simple_dpram
generic map (
g_data_width => g_window_width,
g_size => c_mem_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
--g_init_file => "./window.nif",
g_init_file => g_window_coef_file,
g_dual_clock => false
)
port map (
rst_n_i => reset_n_i,
clka_i => clk_i,
bwea_i => (others => '0'),
wea_i => '0',
aa_i => cur_address,
da_i => (others => '0'),
clkb_i => clk_i,
ab_i => cur_address,
qb_o => window_factor
);
cmp_index : counter
generic map (
g_mem_size => c_mem_size,
g_bus_size => c_bus_size,
g_switch_delay => g_input_delay
)
port map (
clk_i => clk_i,
index_o => cur_address,
ce_i => '1',
reset_n_i => reset_n_i,
switch_delay_i => switch_delay_i,
switch_o => switch_o,
switch_en_i => switch_en_i
);
dbg_cur_address_o(dbg_cur_address_o'left downto cur_address'left+1)
<= (others =>'0');
dbg_cur_address_o(cur_address'left downto 0) <= cur_address;
cmp_multiplier_a : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_a_i,
b_i => window_factor,
p_o => a_o,
clk_i => clk_i,
reset_n_i => reset_n_i);
cmp_multiplier_b : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_b_i,
b_i => window_factor,
p_o => b_o,
clk_i => clk_i,
reset_n_i => reset_n_i);
cmp_multiplier_c : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_c_i,
b_i => window_factor,
p_o => c_o,
clk_i => clk_i,
reset_n_i => reset_n_i);
cmp_multiplier_d : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_d_i,
b_i => window_factor,
p_o => d_o,
clk_i => clk_i,
reset_n_i => reset_n_i);
end structural;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fcmp_0_no_dsp_32 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ANN_ap_fcmp_0_no_dsp_32;
ARCHITECTURE ANN_ap_fcmp_0_no_dsp_32_arch OF ANN_ap_fcmp_0_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fcmp_0_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fcmp_0_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fcmp_0_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=1,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=1,C_RESULT_FRACTION_WIDTH=0,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=1,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=8,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 1,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 1,
C_RESULT_FRACTION_WIDTH => 0,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 1,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 8,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => s_axis_operation_tvalid,
s_axis_operation_tdata => s_axis_operation_tdata,
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fcmp_0_no_dsp_32_arch;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_3.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_3
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLROM_3_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.fft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_3_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_3_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_3_vld : OUT std_logic
);
END TWDLROM_3_3;
ARCHITECTURE rtl OF TWDLROM_3_3 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_3_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_3_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#2#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#0#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#0#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_3_re_tmp <= twdlIn_re;
twdl_3_3_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_3_re <= std_logic_vector(twdl_3_3_re_tmp);
twdl_3_3_im <= std_logic_vector(twdl_3_3_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_3_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_3_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY v_ram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END v_ram;
ARCHITECTURE v_ram_arch OF v_ram IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF v_ram_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "v_ram.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 76800,
C_READ_DEPTH_A => 76800,
C_ADDRA_WIDTH => 17,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 76800,
C_READ_DEPTH_B => 76800,
C_ADDRB_WIDTH => 17,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "26",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 16.2184 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END v_ram_arch;
|
`protect begin_protected
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`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 414048)
`protect data_block
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`protect end_protected
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_0_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_0_0;
ARCHITECTURE system_vga_buffer_0_0_arch OF system_vga_buffer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 10
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_0_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_0_0;
ARCHITECTURE system_vga_buffer_0_0_arch OF system_vga_buffer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 10
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_0_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_0_0;
ARCHITECTURE system_vga_buffer_0_0_arch OF system_vga_buffer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 10
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_0_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_0_0;
ARCHITECTURE system_vga_buffer_0_0_arch OF system_vga_buffer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 10
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_0_0_arch;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_fg_01_11.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture struct of reg4 is
signal int_clk : bit;
begin
bit0 : entity work.d_latch(basic)
port map (d0, int_clk, q0);
bit1 : entity work.d_latch(basic)
port map (d1, int_clk, q1);
bit2 : entity work.d_latch(basic)
port map (d2, int_clk, q2);
bit3 : entity work.d_latch(basic)
port map (d3, int_clk, q3);
gate : entity work.and2(basic)
port map (en, clk, int_clk);
end architecture struct;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_fg_01_11.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture struct of reg4 is
signal int_clk : bit;
begin
bit0 : entity work.d_latch(basic)
port map (d0, int_clk, q0);
bit1 : entity work.d_latch(basic)
port map (d1, int_clk, q1);
bit2 : entity work.d_latch(basic)
port map (d2, int_clk, q2);
bit3 : entity work.d_latch(basic)
port map (d3, int_clk, q3);
gate : entity work.and2(basic)
port map (en, clk, int_clk);
end architecture struct;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_fg_01_11.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture struct of reg4 is
signal int_clk : bit;
begin
bit0 : entity work.d_latch(basic)
port map (d0, int_clk, q0);
bit1 : entity work.d_latch(basic)
port map (d1, int_clk, q1);
bit2 : entity work.d_latch(basic)
port map (d2, int_clk, q2);
bit3 : entity work.d_latch(basic)
port map (d3, int_clk, q3);
gate : entity work.and2(basic)
port map (en, clk, int_clk);
end architecture struct;
|
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Blink is
port( enable : in std_logic;
numberIn : in std_logic_vector(3 downto 0);
numberOut: out std_logic_vector(3 downto 0);
clock : in std_logic;
load : in std_logic);
end Blink;
-- Entidade que faz piscar a uma certa frequência o valor de entrada caso o enable estiver ligado('1').
architecture Behavioral of Blink is
signal checkblink : std_logic;
signal s_nin : std_logic_vector(3 downto 0);
begin
process(clock, enable, load)
begin
if(enable = '1') then
if(rising_edge(clock))then
if(checkblink = '1') then
numberOut <= s_nin;
checkblink<= '0';
else
checkblink<= '1';
numberOut <= "1111";
end if;
end if;
else
checkblink<= '0';
numberOut <= s_nin;
end if;
if(load = '1') then
s_nin <= numberIn;
end if;
end process;
end Behavioral; |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/IFFT_HDL_Optimized.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: IFFT_HDL_Optimized
-- Source Path: OFDM_transmitter/IFFT HDL Optimized
-- Hierarchy Level: 1
--
-- FFT HDL Optimized
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.OFDM_transmitter_pkg.ALL;
ENTITY IFFT_HDL_Optimized IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dataIn_re : IN vector_of_std_logic_vector16(0 TO 15); -- sfix16_En13 [16]
dataIn_im : IN vector_of_std_logic_vector16(0 TO 15); -- sfix16_En13 [16]
validIn : IN std_logic;
dataOut_re : OUT vector_of_std_logic_vector16(0 TO 15); -- sfix16_En13 [16]
dataOut_im : OUT vector_of_std_logic_vector16(0 TO 15); -- sfix16_En13 [16]
validOut : OUT std_logic
);
END IFFT_HDL_Optimized;
ARCHITECTURE rtl OF IFFT_HDL_Optimized IS
-- Component Declarations
COMPONENT RADIX22FFT_SDNF1_1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_1_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_1 : IN std_logic; -- ufix1
dout_1_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_3 : IN std_logic; -- ufix1
dout_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_1_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_1_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_1_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_2_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_1_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block5
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_5 : IN std_logic; -- ufix1
dout_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_7 : IN std_logic; -- ufix1
dout_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_3_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_3_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_3_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_4_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_3_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_3_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_3_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_1_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_1 : IN std_logic; -- ufix1
dout_1_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_3 : IN std_logic; -- ufix1
dout_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_6_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_5_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_5_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_6_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_6_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_5_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_7
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_7_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_8
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_8_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_8_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_8_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_8_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_8_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_8_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_7_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_5 : IN std_logic; -- ufix1
dout_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_7 : IN std_logic; -- ufix1
dout_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_9 : IN std_logic; -- ufix1
dout_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_11 : IN std_logic; -- ufix1
dout_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_10
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_9_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block5
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_13 : IN std_logic; -- ufix1
dout_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_15 : IN std_logic; -- ufix1
dout_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_11
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_11_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_12
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_12_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_9 : IN std_logic; -- ufix1
dout_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_11 : IN std_logic; -- ufix1
dout_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_14
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block5
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_13_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_13_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_13_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_15
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_16
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_16_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_16_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_16_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_16_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block5
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block5
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_13 : IN std_logic; -- ufix1
dout_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_15 : IN std_logic; -- ufix1
dout_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : RADIX22FFT_SDNF1_1
USE ENTITY work.RADIX22FFT_SDNF1_1(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block3
USE ENTITY work.RADIX22FFT_SDNF1_1_block3(rtl);
FOR ALL : RADIX22FFT_SDNF2_2
USE ENTITY work.RADIX22FFT_SDNF2_2(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block
USE ENTITY work.RADIX22FFT_SDNF1_1_block(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block4
USE ENTITY work.RADIX22FFT_SDNF1_1_block4(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block
USE ENTITY work.RADIX22FFT_SDNF2_2_block(rtl);
FOR ALL : TWDLROM_3_2
USE ENTITY work.TWDLROM_3_2(rtl);
FOR ALL : TWDLMULT_SDNF1_3
USE ENTITY work.TWDLMULT_SDNF1_3(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block1
USE ENTITY work.RADIX22FFT_SDNF1_1_block1(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block5
USE ENTITY work.RADIX22FFT_SDNF1_1_block5(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block1
USE ENTITY work.RADIX22FFT_SDNF2_2_block1(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block2
USE ENTITY work.RADIX22FFT_SDNF1_1_block2(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block6
USE ENTITY work.RADIX22FFT_SDNF1_1_block6(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block2
USE ENTITY work.RADIX22FFT_SDNF2_2_block2(rtl);
FOR ALL : TWDLROM_3_3
USE ENTITY work.TWDLROM_3_3(rtl);
FOR ALL : TWDLROM_3_4
USE ENTITY work.TWDLROM_3_4(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block
USE ENTITY work.TWDLMULT_SDNF1_3_block(rtl);
FOR ALL : RADIX22FFT_SDNF1_3
USE ENTITY work.RADIX22FFT_SDNF1_3(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block
USE ENTITY work.RADIX22FFT_SDNF1_3_block(rtl);
FOR ALL : RADIX22FFT_SDNF2_4
USE ENTITY work.RADIX22FFT_SDNF2_4(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block
USE ENTITY work.RADIX22FFT_SDNF2_4_block(rtl);
FOR ALL : TWDLROM_3_6
USE ENTITY work.TWDLROM_3_6(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block1
USE ENTITY work.TWDLMULT_SDNF1_3_block1(rtl);
FOR ALL : TWDLROM_3_7
USE ENTITY work.TWDLROM_3_7(rtl);
FOR ALL : TWDLROM_3_8
USE ENTITY work.TWDLROM_3_8(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block2
USE ENTITY work.TWDLMULT_SDNF1_3_block2(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block1
USE ENTITY work.RADIX22FFT_SDNF1_3_block1(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block2
USE ENTITY work.RADIX22FFT_SDNF1_3_block2(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block1
USE ENTITY work.RADIX22FFT_SDNF2_4_block1(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block2
USE ENTITY work.RADIX22FFT_SDNF2_4_block2(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block3
USE ENTITY work.RADIX22FFT_SDNF2_2_block3(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block4
USE ENTITY work.RADIX22FFT_SDNF2_2_block4(rtl);
FOR ALL : TWDLROM_3_10
USE ENTITY work.TWDLROM_3_10(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block3
USE ENTITY work.TWDLMULT_SDNF1_3_block3(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block5
USE ENTITY work.RADIX22FFT_SDNF2_2_block5(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block6
USE ENTITY work.RADIX22FFT_SDNF2_2_block6(rtl);
FOR ALL : TWDLROM_3_11
USE ENTITY work.TWDLROM_3_11(rtl);
FOR ALL : TWDLROM_3_12
USE ENTITY work.TWDLROM_3_12(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block4
USE ENTITY work.TWDLMULT_SDNF1_3_block4(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block3
USE ENTITY work.RADIX22FFT_SDNF1_3_block3(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block4
USE ENTITY work.RADIX22FFT_SDNF1_3_block4(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block3
USE ENTITY work.RADIX22FFT_SDNF2_4_block3(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block4
USE ENTITY work.RADIX22FFT_SDNF2_4_block4(rtl);
FOR ALL : TWDLROM_3_14
USE ENTITY work.TWDLROM_3_14(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block5
USE ENTITY work.TWDLMULT_SDNF1_3_block5(rtl);
FOR ALL : TWDLROM_3_15
USE ENTITY work.TWDLROM_3_15(rtl);
FOR ALL : TWDLROM_3_16
USE ENTITY work.TWDLROM_3_16(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block6
USE ENTITY work.TWDLMULT_SDNF1_3_block6(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block5
USE ENTITY work.RADIX22FFT_SDNF1_3_block5(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block6
USE ENTITY work.RADIX22FFT_SDNF1_3_block6(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block5
USE ENTITY work.RADIX22FFT_SDNF2_4_block5(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block6
USE ENTITY work.RADIX22FFT_SDNF2_4_block6(rtl);
-- Signals
SIGNAL rotate_1 : std_logic; -- ufix1
SIGNAL rotate_1_1 : std_logic; -- ufix1
SIGNAL twdlXdin_1_vld : std_logic;
SIGNAL softReset : std_logic;
SIGNAL dout_1_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_1_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_1_vld : std_logic;
SIGNAL dout_9_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_9_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_10_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_10_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_9_vld : std_logic;
SIGNAL dout_1_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_1_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld : std_logic;
SIGNAL rotate_3 : std_logic; -- ufix1
SIGNAL dout_3_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_3_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_4_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_4_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_3_vld : std_logic;
SIGNAL dout_11_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_11_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_12_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_12_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_11_vld : std_logic;
SIGNAL dout_3_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_3_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_4_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_4_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_1 : std_logic;
SIGNAL twdl_3_1_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_1_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_2_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_2_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_2_vld : std_logic;
SIGNAL twdlXdin_1_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_1_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_2_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_2_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_1_vld_1 : std_logic;
SIGNAL rotate_5 : std_logic; -- ufix1
SIGNAL dout_5_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_5_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_6_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_6_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_5_vld : std_logic;
SIGNAL dout_13_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_13_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_14_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_14_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_13_vld : std_logic;
SIGNAL dout_5_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_5_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_6_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_6_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_2 : std_logic;
SIGNAL rotate_7 : std_logic; -- ufix1
SIGNAL dout_7_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_7_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_8_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_8_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_7_vld : std_logic;
SIGNAL dout_15_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_15_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_16_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_16_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_15_vld : std_logic;
SIGNAL dout_7_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_7_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_8_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_8_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_3 : std_logic;
SIGNAL twdl_3_3_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_3_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_3_vld : std_logic;
SIGNAL twdl_3_4_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_4_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_4_vld : std_logic;
SIGNAL twdlXdin_3_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_3_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_4_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_4_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_3_vld : std_logic;
SIGNAL dout_1_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_1_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_1_vld_1 : std_logic;
SIGNAL dout_3_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_3_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_4_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_4_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_3_vld_1 : std_logic;
SIGNAL dout_4_vld : std_logic;
SIGNAL rotate_3_1 : std_logic; -- ufix1
SIGNAL dout_4_vld_1 : std_logic;
SIGNAL rotate_5_1 : std_logic; -- ufix1
SIGNAL twdl_3_5_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_5_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_6_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_6_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_6_vld : std_logic;
SIGNAL twdlXdin_5_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_5_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_6_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_6_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_5_vld : std_logic;
SIGNAL twdl_3_7_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_7_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_7_vld : std_logic;
SIGNAL twdl_3_8_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_8_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_8_vld : std_logic;
SIGNAL twdlXdin_7_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_7_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_8_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_8_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_7_vld : std_logic;
SIGNAL dout_5_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_5_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_6_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_6_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_5_vld_1 : std_logic;
SIGNAL dout_7_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_7_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_8_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_8_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_7_vld_1 : std_logic;
SIGNAL dout_4_vld_2 : std_logic;
SIGNAL rotate_7_1 : std_logic; -- ufix1
SIGNAL dout_4_vld_3 : std_logic;
SIGNAL rotate_9 : std_logic; -- ufix1
SIGNAL rotate_9_1 : std_logic; -- ufix1
SIGNAL dout_9_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_9_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_10_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_10_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_4 : std_logic;
SIGNAL rotate_11 : std_logic; -- ufix1
SIGNAL dout_11_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_11_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_12_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_12_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_5 : std_logic;
SIGNAL twdl_3_9_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_9_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_10_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_10_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_10_vld : std_logic;
SIGNAL twdlXdin_9_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_9_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_10_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_10_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_9_vld : std_logic;
SIGNAL rotate_13 : std_logic; -- ufix1
SIGNAL dout_13_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_13_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_14_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_14_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_6 : std_logic;
SIGNAL rotate_15 : std_logic; -- ufix1
SIGNAL dout_15_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_15_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_16_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_16_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_7 : std_logic;
SIGNAL twdl_3_11_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_11_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_11_vld : std_logic;
SIGNAL twdl_3_12_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_12_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_12_vld : std_logic;
SIGNAL twdlXdin_11_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_11_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_12_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_12_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_11_vld : std_logic;
SIGNAL dout_9_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_9_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_10_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_10_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_9_vld_1 : std_logic;
SIGNAL dout_11_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_11_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_12_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_12_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_11_vld_1 : std_logic;
SIGNAL dout_4_vld_4 : std_logic;
SIGNAL rotate_11_1 : std_logic; -- ufix1
SIGNAL dout_4_vld_5 : std_logic;
SIGNAL rotate_13_1 : std_logic; -- ufix1
SIGNAL twdl_3_13_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_13_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_14_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_14_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_14_vld : std_logic;
SIGNAL twdlXdin_13_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_13_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_14_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_14_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_13_vld : std_logic;
SIGNAL twdl_3_15_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_15_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_15_vld : std_logic;
SIGNAL twdl_3_16_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_16_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_16_vld : std_logic;
SIGNAL twdlXdin_15_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_15_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_16_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_16_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_15_vld : std_logic;
SIGNAL dout_13_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_13_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_14_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_14_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_13_vld_1 : std_logic;
SIGNAL dout_15_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_15_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_16_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_16_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_15_vld_1 : std_logic;
SIGNAL dout_4_vld_6 : std_logic;
SIGNAL rotate_15_1 : std_logic; -- ufix1
SIGNAL dout_4_vld_7 : std_logic;
SIGNAL dataOut_re_tmp : vector_of_std_logic_vector16(0 TO 15); -- ufix16 [16]
SIGNAL dataOut_im_tmp : vector_of_std_logic_vector16(0 TO 15); -- ufix16 [16]
BEGIN
u_SDNF1_1_1 : RADIX22FFT_SDNF1_1
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_1_re => dataIn_im(0), -- sfix16_En13
twdlXdin_1_im => dataIn_re(0), -- sfix16_En13
twdlXdin_9_re => dataIn_im(8), -- sfix16_En13
twdlXdin_9_im => dataIn_re(8), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_1_re => dout_1_re, -- sfix16_En13
dout_1_im => dout_1_im, -- sfix16_En13
dout_2_re => dout_2_re, -- sfix16_En13
dout_2_im => dout_2_im, -- sfix16_En13
dout_1_vld => dout_1_vld
);
u_SDNF1_1_9 : RADIX22FFT_SDNF1_1_block3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_5_re => dataIn_im(4), -- sfix16_En13
twdlXdin_5_im => dataIn_re(4), -- sfix16_En13
twdlXdin_13_re => dataIn_im(12), -- sfix16_En13
twdlXdin_13_im => dataIn_re(12), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_9_re => dout_9_re, -- sfix16_En13
dout_9_im => dout_9_im, -- sfix16_En13
dout_10_re => dout_10_re, -- sfix16_En13
dout_10_im => dout_10_im, -- sfix16_En13
dout_9_vld => dout_9_vld
);
u_SDNF2_2_1 : RADIX22FFT_SDNF2_2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_1 => rotate_1_1, -- ufix1
dout_1_re => dout_1_re, -- sfix16_En13
dout_1_im => dout_1_im, -- sfix16_En13
dout_9_re => dout_9_re, -- sfix16_En13
dout_9_im => dout_9_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_1_re_1 => dout_1_re_1, -- sfix16_En13
dout_1_im_1 => dout_1_im_1, -- sfix16_En13
dout_2_re => dout_2_re_1, -- sfix16_En13
dout_2_im => dout_2_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld
);
u_SDNF1_1_3 : RADIX22FFT_SDNF1_1_block
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_2_re => dataIn_im(1), -- sfix16_En13
twdlXdin_2_im => dataIn_re(1), -- sfix16_En13
twdlXdin_10_re => dataIn_im(9), -- sfix16_En13
twdlXdin_10_im => dataIn_re(9), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_3_re => dout_3_re, -- sfix16_En13
dout_3_im => dout_3_im, -- sfix16_En13
dout_4_re => dout_4_re, -- sfix16_En13
dout_4_im => dout_4_im, -- sfix16_En13
dout_3_vld => dout_3_vld
);
u_SDNF1_1_11 : RADIX22FFT_SDNF1_1_block4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_6_re => dataIn_im(5), -- sfix16_En13
twdlXdin_6_im => dataIn_re(5), -- sfix16_En13
twdlXdin_14_re => dataIn_im(13), -- sfix16_En13
twdlXdin_14_im => dataIn_re(13), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_11_re => dout_11_re, -- sfix16_En13
dout_11_im => dout_11_im, -- sfix16_En13
dout_12_re => dout_12_re, -- sfix16_En13
dout_12_im => dout_12_im, -- sfix16_En13
dout_11_vld => dout_11_vld
);
u_SDNF2_2_3 : RADIX22FFT_SDNF2_2_block
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_3 => rotate_3, -- ufix1
dout_3_re => dout_3_re, -- sfix16_En13
dout_3_im => dout_3_im, -- sfix16_En13
dout_11_re => dout_11_re, -- sfix16_En13
dout_11_im => dout_11_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_3_re_1 => dout_3_re_1, -- sfix16_En13
dout_3_im_1 => dout_3_im_1, -- sfix16_En13
dout_4_re => dout_4_re_1, -- sfix16_En13
dout_4_im => dout_4_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_1
);
u_twdlROM_3_2 : TWDLROM_3_2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_2_re => twdl_3_2_re, -- sfix16_En14
twdl_3_2_im => twdl_3_2_im, -- sfix16_En14
twdl_3_2_vld => twdl_3_2_vld
);
u_TWDLMULT_SDNF1_3_1 : TWDLMULT_SDNF1_3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_1_re => dout_1_re_1, -- sfix16_En13
dout_1_im => dout_1_im_1, -- sfix16_En13
dout_3_re => dout_3_re_1, -- sfix16_En13
dout_3_im => dout_3_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_1_re => std_logic_vector(twdl_3_1_re), -- sfix16_En14
twdl_3_1_im => std_logic_vector(twdl_3_1_im), -- sfix16_En14
twdl_3_2_re => twdl_3_2_re, -- sfix16_En14
twdl_3_2_im => twdl_3_2_im, -- sfix16_En14
twdl_3_2_vld => twdl_3_2_vld,
softReset => softReset,
twdlXdin_1_re => twdlXdin_1_re, -- sfix16_En13
twdlXdin_1_im => twdlXdin_1_im, -- sfix16_En13
twdlXdin_2_re => twdlXdin_2_re, -- sfix16_En13
twdlXdin_2_im => twdlXdin_2_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1
);
u_SDNF1_1_5 : RADIX22FFT_SDNF1_1_block1
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_3_re => dataIn_im(2), -- sfix16_En13
twdlXdin_3_im => dataIn_re(2), -- sfix16_En13
twdlXdin_11_re => dataIn_im(10), -- sfix16_En13
twdlXdin_11_im => dataIn_re(10), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_5_re => dout_5_re, -- sfix16_En13
dout_5_im => dout_5_im, -- sfix16_En13
dout_6_re => dout_6_re, -- sfix16_En13
dout_6_im => dout_6_im, -- sfix16_En13
dout_5_vld => dout_5_vld
);
u_SDNF1_1_13 : RADIX22FFT_SDNF1_1_block5
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_7_re => dataIn_im(6), -- sfix16_En13
twdlXdin_7_im => dataIn_re(6), -- sfix16_En13
twdlXdin_15_re => dataIn_im(14), -- sfix16_En13
twdlXdin_15_im => dataIn_re(14), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_13_re => dout_13_re, -- sfix16_En13
dout_13_im => dout_13_im, -- sfix16_En13
dout_14_re => dout_14_re, -- sfix16_En13
dout_14_im => dout_14_im, -- sfix16_En13
dout_13_vld => dout_13_vld
);
u_SDNF2_2_5 : RADIX22FFT_SDNF2_2_block1
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_5 => rotate_5, -- ufix1
dout_5_re => dout_5_re, -- sfix16_En13
dout_5_im => dout_5_im, -- sfix16_En13
dout_13_re => dout_13_re, -- sfix16_En13
dout_13_im => dout_13_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_5_re_1 => dout_5_re_1, -- sfix16_En13
dout_5_im_1 => dout_5_im_1, -- sfix16_En13
dout_6_re => dout_6_re_1, -- sfix16_En13
dout_6_im => dout_6_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_2
);
u_SDNF1_1_7 : RADIX22FFT_SDNF1_1_block2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_4_re => dataIn_im(3), -- sfix16_En13
twdlXdin_4_im => dataIn_re(3), -- sfix16_En13
twdlXdin_12_re => dataIn_im(11), -- sfix16_En13
twdlXdin_12_im => dataIn_re(11), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_7_re => dout_7_re, -- sfix16_En13
dout_7_im => dout_7_im, -- sfix16_En13
dout_8_re => dout_8_re, -- sfix16_En13
dout_8_im => dout_8_im, -- sfix16_En13
dout_7_vld => dout_7_vld
);
u_SDNF1_1_15 : RADIX22FFT_SDNF1_1_block6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_8_re => dataIn_im(7), -- sfix16_En13
twdlXdin_8_im => dataIn_re(7), -- sfix16_En13
twdlXdin_16_re => dataIn_im(15), -- sfix16_En13
twdlXdin_16_im => dataIn_re(15), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_15_re => dout_15_re, -- sfix16_En13
dout_15_im => dout_15_im, -- sfix16_En13
dout_16_re => dout_16_re, -- sfix16_En13
dout_16_im => dout_16_im, -- sfix16_En13
dout_15_vld => dout_15_vld
);
u_SDNF2_2_7 : RADIX22FFT_SDNF2_2_block2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_7 => rotate_7, -- ufix1
dout_7_re => dout_7_re, -- sfix16_En13
dout_7_im => dout_7_im, -- sfix16_En13
dout_15_re => dout_15_re, -- sfix16_En13
dout_15_im => dout_15_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_7_re_1 => dout_7_re_1, -- sfix16_En13
dout_7_im_1 => dout_7_im_1, -- sfix16_En13
dout_8_re => dout_8_re_1, -- sfix16_En13
dout_8_im => dout_8_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_3
);
u_twdlROM_3_3 : TWDLROM_3_3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_3_re => twdl_3_3_re, -- sfix16_En14
twdl_3_3_im => twdl_3_3_im, -- sfix16_En14
twdl_3_3_vld => twdl_3_3_vld
);
u_twdlROM_3_4 : TWDLROM_3_4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_4_re => twdl_3_4_re, -- sfix16_En14
twdl_3_4_im => twdl_3_4_im, -- sfix16_En14
twdl_3_4_vld => twdl_3_4_vld
);
u_TWDLMULT_SDNF1_3_3 : TWDLMULT_SDNF1_3_block
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_5_re => dout_5_re_1, -- sfix16_En13
dout_5_im => dout_5_im_1, -- sfix16_En13
dout_7_re => dout_7_re_1, -- sfix16_En13
dout_7_im => dout_7_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_3_re => twdl_3_3_re, -- sfix16_En14
twdl_3_3_im => twdl_3_3_im, -- sfix16_En14
twdl_3_4_re => twdl_3_4_re, -- sfix16_En14
twdl_3_4_im => twdl_3_4_im, -- sfix16_En14
twdl_3_4_vld => twdl_3_4_vld,
softReset => softReset,
twdlXdin_3_re => twdlXdin_3_re, -- sfix16_En13
twdlXdin_3_im => twdlXdin_3_im, -- sfix16_En13
twdlXdin_4_re => twdlXdin_4_re, -- sfix16_En13
twdlXdin_4_im => twdlXdin_4_im, -- sfix16_En13
twdlXdin_3_vld => twdlXdin_3_vld
);
u_SDNF1_3_1 : RADIX22FFT_SDNF1_3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_1_re => twdlXdin_1_re, -- sfix16_En13
twdlXdin_1_im => twdlXdin_1_im, -- sfix16_En13
twdlXdin_3_re => twdlXdin_3_re, -- sfix16_En13
twdlXdin_3_im => twdlXdin_3_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_1_re => dout_1_re_2, -- sfix16_En13
dout_1_im => dout_1_im_2, -- sfix16_En13
dout_2_re => dout_2_re_2, -- sfix16_En13
dout_2_im => dout_2_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1
);
u_SDNF1_3_3 : RADIX22FFT_SDNF1_3_block
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_2_re => twdlXdin_2_re, -- sfix16_En13
twdlXdin_2_im => twdlXdin_2_im, -- sfix16_En13
twdlXdin_4_re => twdlXdin_4_re, -- sfix16_En13
twdlXdin_4_im => twdlXdin_4_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_3_re => dout_3_re_2, -- sfix16_En13
dout_3_im => dout_3_im_2, -- sfix16_En13
dout_4_re => dout_4_re_2, -- sfix16_En13
dout_4_im => dout_4_im_2, -- sfix16_En13
dout_3_vld => dout_3_vld_1
);
u_SDNF2_4_1 : RADIX22FFT_SDNF2_4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_1 => rotate_1, -- ufix1
dout_1_re => dout_1_re_2, -- sfix16_En13
dout_1_im => dout_1_im_2, -- sfix16_En13
dout_3_re => dout_3_re_2, -- sfix16_En13
dout_3_im => dout_3_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_1_re_1 => dataOut_im_tmp(0), -- sfix16_En13
dout_1_im_1 => dataOut_re_tmp(0), -- sfix16_En13
dout_2_re => dataOut_im_tmp(1), -- sfix16_En13
dout_2_im => dataOut_re_tmp(1), -- sfix16_En13
dout_4_vld => dout_4_vld
);
u_SDNF2_4_3 : RADIX22FFT_SDNF2_4_block
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_3 => rotate_3_1, -- ufix1
dout_2_re => dout_2_re_2, -- sfix16_En13
dout_2_im => dout_2_im_2, -- sfix16_En13
dout_4_re => dout_4_re_2, -- sfix16_En13
dout_4_im => dout_4_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_3_re => dataOut_im_tmp(2), -- sfix16_En13
dout_3_im => dataOut_re_tmp(2), -- sfix16_En13
dout_4_re_1 => dataOut_im_tmp(3), -- sfix16_En13
dout_4_im_1 => dataOut_re_tmp(3), -- sfix16_En13
dout_4_vld => dout_4_vld_1
);
u_twdlROM_3_6 : TWDLROM_3_6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_6_re => twdl_3_6_re, -- sfix16_En14
twdl_3_6_im => twdl_3_6_im, -- sfix16_En14
twdl_3_6_vld => twdl_3_6_vld
);
u_TWDLMULT_SDNF1_3_5 : TWDLMULT_SDNF1_3_block1
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_re => dout_2_re_1, -- sfix16_En13
dout_2_im => dout_2_im_1, -- sfix16_En13
dout_4_re => dout_4_re_1, -- sfix16_En13
dout_4_im => dout_4_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_5_re => std_logic_vector(twdl_3_5_re), -- sfix16_En14
twdl_3_5_im => std_logic_vector(twdl_3_5_im), -- sfix16_En14
twdl_3_6_re => twdl_3_6_re, -- sfix16_En14
twdl_3_6_im => twdl_3_6_im, -- sfix16_En14
twdl_3_6_vld => twdl_3_6_vld,
softReset => softReset,
twdlXdin_5_re => twdlXdin_5_re, -- sfix16_En13
twdlXdin_5_im => twdlXdin_5_im, -- sfix16_En13
twdlXdin_6_re => twdlXdin_6_re, -- sfix16_En13
twdlXdin_6_im => twdlXdin_6_im, -- sfix16_En13
twdlXdin_5_vld => twdlXdin_5_vld
);
u_twdlROM_3_7 : TWDLROM_3_7
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_7_re => twdl_3_7_re, -- sfix16_En14
twdl_3_7_im => twdl_3_7_im, -- sfix16_En14
twdl_3_7_vld => twdl_3_7_vld
);
u_twdlROM_3_8 : TWDLROM_3_8
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_8_re => twdl_3_8_re, -- sfix16_En14
twdl_3_8_im => twdl_3_8_im, -- sfix16_En14
twdl_3_8_vld => twdl_3_8_vld
);
u_TWDLMULT_SDNF1_3_7 : TWDLMULT_SDNF1_3_block2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_6_re => dout_6_re_1, -- sfix16_En13
dout_6_im => dout_6_im_1, -- sfix16_En13
dout_8_re => dout_8_re_1, -- sfix16_En13
dout_8_im => dout_8_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_7_re => twdl_3_7_re, -- sfix16_En14
twdl_3_7_im => twdl_3_7_im, -- sfix16_En14
twdl_3_8_re => twdl_3_8_re, -- sfix16_En14
twdl_3_8_im => twdl_3_8_im, -- sfix16_En14
twdl_3_8_vld => twdl_3_8_vld,
softReset => softReset,
twdlXdin_7_re => twdlXdin_7_re, -- sfix16_En13
twdlXdin_7_im => twdlXdin_7_im, -- sfix16_En13
twdlXdin_8_re => twdlXdin_8_re, -- sfix16_En13
twdlXdin_8_im => twdlXdin_8_im, -- sfix16_En13
twdlXdin_7_vld => twdlXdin_7_vld
);
u_SDNF1_3_5 : RADIX22FFT_SDNF1_3_block1
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_5_re => twdlXdin_5_re, -- sfix16_En13
twdlXdin_5_im => twdlXdin_5_im, -- sfix16_En13
twdlXdin_7_re => twdlXdin_7_re, -- sfix16_En13
twdlXdin_7_im => twdlXdin_7_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_5_re => dout_5_re_2, -- sfix16_En13
dout_5_im => dout_5_im_2, -- sfix16_En13
dout_6_re => dout_6_re_2, -- sfix16_En13
dout_6_im => dout_6_im_2, -- sfix16_En13
dout_5_vld => dout_5_vld_1
);
u_SDNF1_3_7 : RADIX22FFT_SDNF1_3_block2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_6_re => twdlXdin_6_re, -- sfix16_En13
twdlXdin_6_im => twdlXdin_6_im, -- sfix16_En13
twdlXdin_8_re => twdlXdin_8_re, -- sfix16_En13
twdlXdin_8_im => twdlXdin_8_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_7_re => dout_7_re_2, -- sfix16_En13
dout_7_im => dout_7_im_2, -- sfix16_En13
dout_8_re => dout_8_re_2, -- sfix16_En13
dout_8_im => dout_8_im_2, -- sfix16_En13
dout_7_vld => dout_7_vld_1
);
u_SDNF2_4_5 : RADIX22FFT_SDNF2_4_block1
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_5 => rotate_5_1, -- ufix1
dout_5_re => dout_5_re_2, -- sfix16_En13
dout_5_im => dout_5_im_2, -- sfix16_En13
dout_7_re => dout_7_re_2, -- sfix16_En13
dout_7_im => dout_7_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_5_re_1 => dataOut_im_tmp(4), -- sfix16_En13
dout_5_im_1 => dataOut_re_tmp(4), -- sfix16_En13
dout_6_re => dataOut_im_tmp(5), -- sfix16_En13
dout_6_im => dataOut_re_tmp(5), -- sfix16_En13
dout_4_vld => dout_4_vld_2
);
u_SDNF2_4_7 : RADIX22FFT_SDNF2_4_block2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_7 => rotate_7_1, -- ufix1
dout_6_re => dout_6_re_2, -- sfix16_En13
dout_6_im => dout_6_im_2, -- sfix16_En13
dout_8_re => dout_8_re_2, -- sfix16_En13
dout_8_im => dout_8_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_7_re => dataOut_im_tmp(6), -- sfix16_En13
dout_7_im => dataOut_re_tmp(6), -- sfix16_En13
dout_8_re_1 => dataOut_im_tmp(7), -- sfix16_En13
dout_8_im_1 => dataOut_re_tmp(7), -- sfix16_En13
dout_4_vld => dout_4_vld_3
);
u_SDNF2_2_9 : RADIX22FFT_SDNF2_2_block3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_9 => rotate_9_1, -- ufix1
dout_2_re => dout_2_re, -- sfix16_En13
dout_2_im => dout_2_im, -- sfix16_En13
dout_10_re => dout_10_re, -- sfix16_En13
dout_10_im => dout_10_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_9_re => dout_9_re_1, -- sfix16_En13
dout_9_im => dout_9_im_1, -- sfix16_En13
dout_10_re_1 => dout_10_re_1, -- sfix16_En13
dout_10_im_1 => dout_10_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_4
);
u_SDNF2_2_11 : RADIX22FFT_SDNF2_2_block4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_11 => rotate_11, -- ufix1
dout_4_re => dout_4_re, -- sfix16_En13
dout_4_im => dout_4_im, -- sfix16_En13
dout_12_re => dout_12_re, -- sfix16_En13
dout_12_im => dout_12_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_11_re => dout_11_re_1, -- sfix16_En13
dout_11_im => dout_11_im_1, -- sfix16_En13
dout_12_re_1 => dout_12_re_1, -- sfix16_En13
dout_12_im_1 => dout_12_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_5
);
u_twdlROM_3_10 : TWDLROM_3_10
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_10_re => twdl_3_10_re, -- sfix16_En14
twdl_3_10_im => twdl_3_10_im, -- sfix16_En14
twdl_3_10_vld => twdl_3_10_vld
);
u_TWDLMULT_SDNF1_3_9 : TWDLMULT_SDNF1_3_block3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_9_re => dout_9_re_1, -- sfix16_En13
dout_9_im => dout_9_im_1, -- sfix16_En13
dout_11_re => dout_11_re_1, -- sfix16_En13
dout_11_im => dout_11_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_9_re => std_logic_vector(twdl_3_9_re), -- sfix16_En14
twdl_3_9_im => std_logic_vector(twdl_3_9_im), -- sfix16_En14
twdl_3_10_re => twdl_3_10_re, -- sfix16_En14
twdl_3_10_im => twdl_3_10_im, -- sfix16_En14
twdl_3_10_vld => twdl_3_10_vld,
softReset => softReset,
twdlXdin_9_re => twdlXdin_9_re, -- sfix16_En13
twdlXdin_9_im => twdlXdin_9_im, -- sfix16_En13
twdlXdin_10_re => twdlXdin_10_re, -- sfix16_En13
twdlXdin_10_im => twdlXdin_10_im, -- sfix16_En13
twdlXdin_9_vld => twdlXdin_9_vld
);
u_SDNF2_2_13 : RADIX22FFT_SDNF2_2_block5
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_13 => rotate_13, -- ufix1
dout_6_re => dout_6_re, -- sfix16_En13
dout_6_im => dout_6_im, -- sfix16_En13
dout_14_re => dout_14_re, -- sfix16_En13
dout_14_im => dout_14_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_13_re => dout_13_re_1, -- sfix16_En13
dout_13_im => dout_13_im_1, -- sfix16_En13
dout_14_re_1 => dout_14_re_1, -- sfix16_En13
dout_14_im_1 => dout_14_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_6
);
u_SDNF2_2_15 : RADIX22FFT_SDNF2_2_block6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_15 => rotate_15, -- ufix1
dout_8_re => dout_8_re, -- sfix16_En13
dout_8_im => dout_8_im, -- sfix16_En13
dout_16_re => dout_16_re, -- sfix16_En13
dout_16_im => dout_16_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_15_re => dout_15_re_1, -- sfix16_En13
dout_15_im => dout_15_im_1, -- sfix16_En13
dout_16_re_1 => dout_16_re_1, -- sfix16_En13
dout_16_im_1 => dout_16_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_7
);
u_twdlROM_3_11 : TWDLROM_3_11
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_11_re => twdl_3_11_re, -- sfix16_En14
twdl_3_11_im => twdl_3_11_im, -- sfix16_En14
twdl_3_11_vld => twdl_3_11_vld
);
u_twdlROM_3_12 : TWDLROM_3_12
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_12_re => twdl_3_12_re, -- sfix16_En14
twdl_3_12_im => twdl_3_12_im, -- sfix16_En14
twdl_3_12_vld => twdl_3_12_vld
);
u_TWDLMULT_SDNF1_3_11 : TWDLMULT_SDNF1_3_block4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_13_re => dout_13_re_1, -- sfix16_En13
dout_13_im => dout_13_im_1, -- sfix16_En13
dout_15_re => dout_15_re_1, -- sfix16_En13
dout_15_im => dout_15_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_11_re => twdl_3_11_re, -- sfix16_En14
twdl_3_11_im => twdl_3_11_im, -- sfix16_En14
twdl_3_12_re => twdl_3_12_re, -- sfix16_En14
twdl_3_12_im => twdl_3_12_im, -- sfix16_En14
twdl_3_12_vld => twdl_3_12_vld,
softReset => softReset,
twdlXdin_11_re => twdlXdin_11_re, -- sfix16_En13
twdlXdin_11_im => twdlXdin_11_im, -- sfix16_En13
twdlXdin_12_re => twdlXdin_12_re, -- sfix16_En13
twdlXdin_12_im => twdlXdin_12_im, -- sfix16_En13
twdlXdin_11_vld => twdlXdin_11_vld
);
u_SDNF1_3_9 : RADIX22FFT_SDNF1_3_block3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_9_re => twdlXdin_9_re, -- sfix16_En13
twdlXdin_9_im => twdlXdin_9_im, -- sfix16_En13
twdlXdin_11_re => twdlXdin_11_re, -- sfix16_En13
twdlXdin_11_im => twdlXdin_11_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_9_re => dout_9_re_2, -- sfix16_En13
dout_9_im => dout_9_im_2, -- sfix16_En13
dout_10_re => dout_10_re_2, -- sfix16_En13
dout_10_im => dout_10_im_2, -- sfix16_En13
dout_9_vld => dout_9_vld_1
);
u_SDNF1_3_11 : RADIX22FFT_SDNF1_3_block4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_10_re => twdlXdin_10_re, -- sfix16_En13
twdlXdin_10_im => twdlXdin_10_im, -- sfix16_En13
twdlXdin_12_re => twdlXdin_12_re, -- sfix16_En13
twdlXdin_12_im => twdlXdin_12_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_11_re => dout_11_re_2, -- sfix16_En13
dout_11_im => dout_11_im_2, -- sfix16_En13
dout_12_re => dout_12_re_2, -- sfix16_En13
dout_12_im => dout_12_im_2, -- sfix16_En13
dout_11_vld => dout_11_vld_1
);
u_SDNF2_4_9 : RADIX22FFT_SDNF2_4_block3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_9 => rotate_9, -- ufix1
dout_9_re => dout_9_re_2, -- sfix16_En13
dout_9_im => dout_9_im_2, -- sfix16_En13
dout_11_re => dout_11_re_2, -- sfix16_En13
dout_11_im => dout_11_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_9_re_1 => dataOut_im_tmp(8), -- sfix16_En13
dout_9_im_1 => dataOut_re_tmp(8), -- sfix16_En13
dout_10_re => dataOut_im_tmp(9), -- sfix16_En13
dout_10_im => dataOut_re_tmp(9), -- sfix16_En13
dout_4_vld => dout_4_vld_4
);
u_SDNF2_4_11 : RADIX22FFT_SDNF2_4_block4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_11 => rotate_11_1, -- ufix1
dout_10_re => dout_10_re_2, -- sfix16_En13
dout_10_im => dout_10_im_2, -- sfix16_En13
dout_12_re => dout_12_re_2, -- sfix16_En13
dout_12_im => dout_12_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_11_re => dataOut_im_tmp(10), -- sfix16_En13
dout_11_im => dataOut_re_tmp(10), -- sfix16_En13
dout_12_re_1 => dataOut_im_tmp(11), -- sfix16_En13
dout_12_im_1 => dataOut_re_tmp(11), -- sfix16_En13
dout_4_vld => dout_4_vld_5
);
u_twdlROM_3_14 : TWDLROM_3_14
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_14_re => twdl_3_14_re, -- sfix16_En14
twdl_3_14_im => twdl_3_14_im, -- sfix16_En14
twdl_3_14_vld => twdl_3_14_vld
);
u_TWDLMULT_SDNF1_3_13 : TWDLMULT_SDNF1_3_block5
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_10_re => dout_10_re_1, -- sfix16_En13
dout_10_im => dout_10_im_1, -- sfix16_En13
dout_12_re => dout_12_re_1, -- sfix16_En13
dout_12_im => dout_12_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_13_re => std_logic_vector(twdl_3_13_re), -- sfix16_En14
twdl_3_13_im => std_logic_vector(twdl_3_13_im), -- sfix16_En14
twdl_3_14_re => twdl_3_14_re, -- sfix16_En14
twdl_3_14_im => twdl_3_14_im, -- sfix16_En14
twdl_3_14_vld => twdl_3_14_vld,
softReset => softReset,
twdlXdin_13_re => twdlXdin_13_re, -- sfix16_En13
twdlXdin_13_im => twdlXdin_13_im, -- sfix16_En13
twdlXdin_14_re => twdlXdin_14_re, -- sfix16_En13
twdlXdin_14_im => twdlXdin_14_im, -- sfix16_En13
twdlXdin_13_vld => twdlXdin_13_vld
);
u_twdlROM_3_15 : TWDLROM_3_15
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_15_re => twdl_3_15_re, -- sfix16_En14
twdl_3_15_im => twdl_3_15_im, -- sfix16_En14
twdl_3_15_vld => twdl_3_15_vld
);
u_twdlROM_3_16 : TWDLROM_3_16
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_16_re => twdl_3_16_re, -- sfix16_En14
twdl_3_16_im => twdl_3_16_im, -- sfix16_En14
twdl_3_16_vld => twdl_3_16_vld
);
u_TWDLMULT_SDNF1_3_15 : TWDLMULT_SDNF1_3_block6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_14_re => dout_14_re_1, -- sfix16_En13
dout_14_im => dout_14_im_1, -- sfix16_En13
dout_16_re => dout_16_re_1, -- sfix16_En13
dout_16_im => dout_16_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_15_re => twdl_3_15_re, -- sfix16_En14
twdl_3_15_im => twdl_3_15_im, -- sfix16_En14
twdl_3_16_re => twdl_3_16_re, -- sfix16_En14
twdl_3_16_im => twdl_3_16_im, -- sfix16_En14
twdl_3_16_vld => twdl_3_16_vld,
softReset => softReset,
twdlXdin_15_re => twdlXdin_15_re, -- sfix16_En13
twdlXdin_15_im => twdlXdin_15_im, -- sfix16_En13
twdlXdin_16_re => twdlXdin_16_re, -- sfix16_En13
twdlXdin_16_im => twdlXdin_16_im, -- sfix16_En13
twdlXdin_15_vld => twdlXdin_15_vld
);
u_SDNF1_3_13 : RADIX22FFT_SDNF1_3_block5
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_13_re => twdlXdin_13_re, -- sfix16_En13
twdlXdin_13_im => twdlXdin_13_im, -- sfix16_En13
twdlXdin_15_re => twdlXdin_15_re, -- sfix16_En13
twdlXdin_15_im => twdlXdin_15_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_13_re => dout_13_re_2, -- sfix16_En13
dout_13_im => dout_13_im_2, -- sfix16_En13
dout_14_re => dout_14_re_2, -- sfix16_En13
dout_14_im => dout_14_im_2, -- sfix16_En13
dout_13_vld => dout_13_vld_1
);
u_SDNF1_3_15 : RADIX22FFT_SDNF1_3_block6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_14_re => twdlXdin_14_re, -- sfix16_En13
twdlXdin_14_im => twdlXdin_14_im, -- sfix16_En13
twdlXdin_16_re => twdlXdin_16_re, -- sfix16_En13
twdlXdin_16_im => twdlXdin_16_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_15_re => dout_15_re_2, -- sfix16_En13
dout_15_im => dout_15_im_2, -- sfix16_En13
dout_16_re => dout_16_re_2, -- sfix16_En13
dout_16_im => dout_16_im_2, -- sfix16_En13
dout_15_vld => dout_15_vld_1
);
u_SDNF2_4_13 : RADIX22FFT_SDNF2_4_block5
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_13 => rotate_13_1, -- ufix1
dout_13_re => dout_13_re_2, -- sfix16_En13
dout_13_im => dout_13_im_2, -- sfix16_En13
dout_15_re => dout_15_re_2, -- sfix16_En13
dout_15_im => dout_15_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_13_re_1 => dataOut_im_tmp(12), -- sfix16_En13
dout_13_im_1 => dataOut_re_tmp(12), -- sfix16_En13
dout_14_re => dataOut_im_tmp(13), -- sfix16_En13
dout_14_im => dataOut_re_tmp(13), -- sfix16_En13
dout_4_vld => dout_4_vld_6
);
u_SDNF2_4_15 : RADIX22FFT_SDNF2_4_block6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_15 => rotate_15_1, -- ufix1
dout_14_re => dout_14_re_2, -- sfix16_En13
dout_14_im => dout_14_im_2, -- sfix16_En13
dout_16_re => dout_16_re_2, -- sfix16_En13
dout_16_im => dout_16_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_15_re => dataOut_im_tmp(14), -- sfix16_En13
dout_15_im => dataOut_re_tmp(14), -- sfix16_En13
dout_16_re_1 => dataOut_im_tmp(15), -- sfix16_En13
dout_16_im_1 => dataOut_re_tmp(15), -- sfix16_En13
dout_4_vld => dout_4_vld_7
);
rotate_1 <= '0';
rotate_1_1 <= '0';
twdlXdin_1_vld <= '1' WHEN validIn /= '0' ELSE
'0';
softReset <= '0';
rotate_3 <= '0';
twdl_3_1_re <= to_signed(16#4000#, 16);
twdl_3_1_im <= to_signed(16#0000#, 16);
rotate_5 <= '0';
rotate_7 <= '0';
rotate_3_1 <= '1';
rotate_5_1 <= '0';
twdl_3_5_re <= to_signed(16#4000#, 16);
twdl_3_5_im <= to_signed(16#0000#, 16);
rotate_7_1 <= '1';
rotate_9 <= '0';
rotate_9_1 <= '1';
rotate_11 <= '1';
twdl_3_9_re <= to_signed(16#4000#, 16);
twdl_3_9_im <= to_signed(16#0000#, 16);
rotate_13 <= '1';
rotate_15 <= '1';
rotate_11_1 <= '1';
rotate_13_1 <= '0';
twdl_3_13_re <= to_signed(16#4000#, 16);
twdl_3_13_im <= to_signed(16#0000#, 16);
rotate_15_1 <= '1';
dataOut_re <= dataOut_re_tmp;
dataOut_im <= dataOut_im_tmp;
validOut <= dout_4_vld;
END rtl;
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.depp_pkg.all;
entity depp_slave_controller is
port (
clk : in std_logic;
rst : in std_logic;
-- Bus connection
slv2mst : in bus_slv2mst_type;
mst2slv : out bus_mst2slv_type;
-- Physical USB/DEPP connection
USB_DB : inout STD_LOGIC_VECTOR(7 DOWNTO 0);
USB_WRITE : in STD_LOGIC;
USB_ASTB : in STD_LOGIC;
USB_DSTB : in STD_LOGIC;
USB_WAIT : out STD_LOGIC
);
end depp_slave_controller;
architecture behaviourial of depp_slave_controller is
signal usb_astb_delayed : std_logic;
signal usb_dstb_delayed : std_logic;
signal mst2slv_out : bus_mst2slv_type := BUS_MST2SLV_IDLE;
begin
sequential : process(clk)
variable wait_dstb_finish : boolean := false;
variable address : natural range 0 to 2**8 - 1;
variable address_tmp : natural range 0 to 2**8 - 1;
variable read_latch : depp_data_type := (others => '0');
variable bus_active : boolean := false;
variable reread : boolean := false;
variable write_mask_reg : std_logic_vector(depp2bus_write_mask_length_ceil*8 - 1 downto 0) := (others => '0');
variable slv2mst_cpy : bus_slv2mst_type := BUS_SLV2MST_IDLE;
variable depp_mode : depp_data_type := (others => '0');
variable next_bus_address : bus_address_type := (others => '0');
begin
if rising_edge(clk) then
-- We are crossing clock domains. Therefore, if either of these is high, other signals might still be settling.
-- Therefore, delay these by one cycle so that by the time interpretation starts, everything has settled.
usb_astb_delayed <= USB_ASTB;
usb_dstb_delayed <= USB_DSTB;
USB_WAIT <= '0';
USB_DB <= (others => 'Z');
if rst = '1' then
USB_WAIT <= '1';
wait_dstb_finish := false;
mst2slv_out <= BUS_MST2SLV_IDLE;
slv2mst_cpy := BUS_SLV2MST_IDLE;
write_mask_reg := (others => '0');
bus_active := false;
address := 0;
else
if bus_active then
if bus_slave_finished(slv2mst) = '1' then
bus_active := false;
mst2slv_out.writeEnable <= '0';
mst2slv_out.readEnable <= '0';
mst2slv_out.address <= next_bus_address;
wait_dstb_finish := true;
slv2mst_cpy := slv2mst;
if reread then
read_latch := slv2mst_cpy.readData(7 downto 0);
reread := false;
end if;
end if;
elsif usb_astb_delayed = '0' then
USB_WAIT <= '1';
if USB_WRITE = '0' then
address := to_integer(unsigned(USB_DB));
elsif USB_WRITE = '1' then
USB_DB <= std_logic_vector(to_unsigned(address, usb_db'length));
end if;
elsif usb_dstb_delayed = '0' and wait_dstb_finish = false then
wait_dstb_finish := true;
if USB_WRITE = '0' then
if address >= depp2bus_addr_reg_start and address <= depp2bus_addr_reg_end then
address_tmp := address - depp2bus_addr_reg_start;
mst2slv_out.address(8*(address_tmp + 1) - 1 downto 8*address_tmp) <= usb_db;
elsif address >= depp2bus_writeData_reg_start and address <= depp2bus_writeData_reg_end then
address_tmp := address - depp2bus_writeData_reg_start;
mst2slv_out.writeData(8*(address_tmp + 1) - 1 downto 8*address_tmp) <= usb_db;
if depp_mode_fast_write_active(depp_mode) then
address := address + 1;
if address > depp2bus_writeData_reg_end then
next_bus_address := std_logic_vector(to_unsigned(
to_integer(unsigned(mst2slv_out.address)) + depp2bus_addr_reg_len,
next_bus_address'length));
address := depp2bus_writeData_reg_start;
mst2slv_out.writeEnable <= '1';
bus_active := true;
wait_dstb_finish := false;
end if;
end if;
elsif address >= depp2bus_write_mask_reg_start and address <= depp2bus_write_mask_reg_end then
address_tmp := address - depp2bus_write_mask_reg_start;
write_mask_reg(8*(address_tmp + 1) - 1 downto 8*address_tmp) := usb_db;
mst2slv_out.writeMask <= write_mask_reg(mst2slv_out.writeMask'range);
elsif address >= depp2bus_mode_register_start and address <= depp2bus_mode_register_end then
depp_mode := usb_db;
elsif address >= depp2bus_activation_register_start and address <= depp2bus_activation_register_end then
next_bus_address := mst2slv_out.address;
mst2slv_out.writeEnable <= '1';
for i in 0 to usb_db'high loop
if usb_db(i) = '1' then
mst2slv_out.writeEnable <= '0';
mst2slv_out.readEnable <= '1';
end if;
end loop;
bus_active := true;
wait_dstb_finish := false;
end if;
elsif USB_WRITE = '1' then
read_latch := (others => '0');
if address >= depp2bus_addr_reg_start and address <= depp2bus_addr_reg_end then
address_tmp := address - depp2bus_addr_reg_start;
read_latch := mst2slv_out.address(8*address_tmp + 7 downto 8*address_tmp);
elsif address >= depp2bus_writeData_reg_start and address <= depp2bus_writeData_reg_end then
address_tmp := address - depp2bus_writeData_reg_start;
read_latch := mst2slv_out.writeData(8*address_tmp + 7 downto 8*address_tmp);
elsif address >= depp2bus_readData_reg_start and address <= depp2bus_readData_reg_end then
address_tmp := address - depp2bus_readData_reg_start;
if depp_mode_fast_read_active(depp_mode) then
if address = depp2bus_readData_reg_start then
next_bus_address := std_logic_vector(to_unsigned(
to_integer(unsigned(mst2slv_out.address)) + depp2bus_addr_reg_len,
next_bus_address'length));
mst2slv_out.readEnable <= '1';
bus_active := true;
wait_dstb_finish := false;
reread := true;
end if;
address := address + 1;
if address > depp2bus_readData_reg_end then
address := depp2bus_readData_reg_start;
end if;
end if;
read_latch := slv2mst_cpy.readData(8*address_tmp + 7 downto 8*address_tmp);
elsif address >= depp2bus_write_mask_reg_start and address <= depp2bus_write_mask_reg_end then
address_tmp := address - depp2bus_write_mask_reg_start;
read_latch := write_mask_reg(8*(address_tmp + 1) - 1 downto 8*address_tmp);
elsif address >= depp2bus_mode_register_start and address <= depp2bus_mode_register_end then
read_latch := depp_mode;
elsif address >= depp2bus_fault_register_start and address <= depp2bus_fault_register_end then
read_latch := (others => '0');
read_latch(0) := slv2mst_cpy.fault;
end if;
end if;
end if;
if usb_dstb_delayed = '0' and usb_write = '1' then
usb_db <= read_latch;
end if;
if wait_dstb_finish then
if usb_dstb_delayed = '1' then
wait_dstb_finish := false;
else
USB_WAIT <= '1';
end if;
end if;
end if;
end if;
end process;
concurrent : process(mst2slv_out)
begin
mst2slv <= mst2slv_out;
end process;
end behaviourial;
|
architecture RTL of ENTITY_NAME is
begin
process
begin
LABEL : assert TRUE
report "This is a string"
severity WARNING;
assert TRUE
report "This is a string"
severity WARNING;
LABEL : assert TRUE
report "This is a string";
LABEL : assert TRUE
severity WARNING;
LABEL : assert TRUE;
end process;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity cpu is
port(
clk : in vl_logic;
reset : in vl_logic;
e1 : in vl_logic_vector(7 downto 0);
e2 : in vl_logic_vector(7 downto 0);
e3 : in vl_logic_vector(7 downto 0);
e4 : in vl_logic_vector(7 downto 0);
s1 : out vl_logic_vector(7 downto 0);
s2 : out vl_logic_vector(7 downto 0);
s3 : out vl_logic_vector(7 downto 0);
s4 : out vl_logic_vector(7 downto 0);
opcode : out vl_logic_vector(5 downto 0);
operacion : out vl_logic_vector(2 downto 0);
z : out vl_logic
);
end cpu;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll0 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altpll0;
ARCHITECTURE SYN OF altpll0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=altpll0",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll0 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altpll0;
ARCHITECTURE SYN OF altpll0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=altpll0",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll0 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altpll0;
ARCHITECTURE SYN OF altpll0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=altpll0",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll0 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altpll0;
ARCHITECTURE SYN OF altpll0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=altpll0",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll0 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altpll0;
ARCHITECTURE SYN OF altpll0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=altpll0",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll0 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altpll0;
ARCHITECTURE SYN OF altpll0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=altpll0",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 18:24:55 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top mig_wrap_proc_sys_reset_1_0 -prefix
-- mig_wrap_proc_sys_reset_1_0_ mig_wrap_proc_sys_reset_0_0_sim_netlist.vhdl
-- Design : mig_wrap_proc_sys_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7vx485tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0_cdc_sync is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
slowest_sync_clk : in STD_LOGIC
);
end mig_wrap_proc_sys_reset_1_0_cdc_sync;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0_cdc_sync is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ext_reset_in,
I1 => mb_debug_sys_rst,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0_cdc_sync_0 is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_1_0_cdc_sync_0 : entity is "cdc_sync";
end mig_wrap_proc_sys_reset_1_0_cdc_sync_0;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0_cdc_sync_0 is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end mig_wrap_proc_sys_reset_1_0_upcnt_n;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
end mig_wrap_proc_sys_reset_1_0_lpf;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0_lpf is
signal \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_SRL_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_HIGH_EXT.ACT_HI_EXT\: entity work.mig_wrap_proc_sys_reset_1_0_cdc_sync
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.mig_wrap_proc_sys_reset_1_0_cdc_sync_0
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => dcm_locked,
I1 => Q,
I2 => lpf_exr,
I3 => lpf_asr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end mig_wrap_proc_sys_reset_1_0_sequence_psr;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.mig_wrap_proc_sys_reset_1_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is "virtex7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
end mig_wrap_proc_sys_reset_1_0_proc_sys_reset;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.mig_wrap_proc_sys_reset_1_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.mig_wrap_proc_sys_reset_1_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mig_wrap_proc_sys_reset_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mig_wrap_proc_sys_reset_1_0 : entity is "mig_wrap_proc_sys_reset_0_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mig_wrap_proc_sys_reset_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mig_wrap_proc_sys_reset_1_0 : entity is "proc_sys_reset,Vivado 2016.4";
end mig_wrap_proc_sys_reset_1_0;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "virtex7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.mig_wrap_proc_sys_reset_1_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
-------------------------------------------------------------------------------
--
-- File: ResetBridge.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a reset-bridge. It takes a reset signal asynchronous to the
-- target clock domain (OutClk) and provides a safe asynchronous or synchronous
-- reset for the OutClk domain (aoRst). The signal aoRst is asserted immediately
-- as aRst arrives, but is de-asserted synchronously with the OutClk rising
-- edge. This means it can be used to safely reset any FF in the OutClk domain,
-- respecting recovery time specs for FFs.
-- The additional output register does not have placement and overly
-- restrictive delay constraints, so that the tools can freely replicate it,
-- if needed.
-- Constraints:
-- # Replace <InstResetBridge> with path to ResetBridge instance, keep rest unchanged
-- # Begin scope to ResetBridge instance
-- current_instance [get_cells <InstResetBridge>]
-- # Reset input to the synchronizer must be ignored for timing analysis
-- set_false_path -through [get_ports -scoped_to_current_instance aRst]
-- # Constrain internal synchronizer paths to half-period, which is expected to be easily met with ASYNC_REG=true
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_ports -scoped_to_current_instance OutClk]]]
-- set_max_delay -from [get_cells OutputFF*.SyncAsyncx/oSyncStages_reg[*]] -to [get_cells OutputFF*.SyncAsyncx/oSyncStages_reg[*]] [expr $ClkPeriod/2]
-- current_instance -quiet
-- # End scope to ResetBridge instance
--
-- Changelog:
-- 2020-Dec-14: Changed file name to ResetBridge
-- 2022-Oct-05: Replaced KEEP with keep_hierarchy. Added the possibility to
-- specify the number of output synchronization stages. Added the
-- possibility to specify an output FF, for replication purposes.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ResetBridge is
Generic (
kPolarity : std_logic := '1';
kStages : natural := 2;
kOutputFF : boolean := false); -- additional output FF for replication
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
aoRst : out STD_LOGIC);
attribute keep_hierarchy : string;
attribute keep_hierarchy of ResetBridge : entity is "yes";
end ResetBridge;
architecture Behavioral of ResetBridge is
signal aRst_int, aoRst_int : std_logic;
begin
aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset
OutputFF_Yes: if kOutputFF generate
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => kStages) --use double FF synchronizer
port map (
aoReset => aRst_int,
aIn => '0',
OutClk => OutClk,
oOut => aoRst_int);
-- Output FF that can be replicated by the tools, if needed
OutputFF: process (OutClk, aoRst_int)
begin
if (aoRst_int = '1') then
aoRst <= kPolarity;
elsif Rising_Edge(OutClk) then
aoRst <= not kPolarity;
end if;
end process;
end generate OutputFF_Yes;
OutputFF_No: if not kOutputFF generate
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kPolarity,
kStages => kStages) --use double FF synchronizer
port map (
aoReset => aRst_int,
aIn => not kPolarity,
OutClk => OutClk,
oOut => aoRst);
end generate OutputFF_No;
end Behavioral; |
-------------------------------------------------------------------------------
--
-- File: ResetBridge.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a reset-bridge. It takes a reset signal asynchronous to the
-- target clock domain (OutClk) and provides a safe asynchronous or synchronous
-- reset for the OutClk domain (aoRst). The signal aoRst is asserted immediately
-- as aRst arrives, but is de-asserted synchronously with the OutClk rising
-- edge. This means it can be used to safely reset any FF in the OutClk domain,
-- respecting recovery time specs for FFs.
-- The additional output register does not have placement and overly
-- restrictive delay constraints, so that the tools can freely replicate it,
-- if needed.
-- Constraints:
-- # Replace <InstResetBridge> with path to ResetBridge instance, keep rest unchanged
-- # Begin scope to ResetBridge instance
-- current_instance [get_cells <InstResetBridge>]
-- # Reset input to the synchronizer must be ignored for timing analysis
-- set_false_path -through [get_ports -scoped_to_current_instance aRst]
-- # Constrain internal synchronizer paths to half-period, which is expected to be easily met with ASYNC_REG=true
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_ports -scoped_to_current_instance OutClk]]]
-- set_max_delay -from [get_cells OutputFF*.SyncAsyncx/oSyncStages_reg[*]] -to [get_cells OutputFF*.SyncAsyncx/oSyncStages_reg[*]] [expr $ClkPeriod/2]
-- current_instance -quiet
-- # End scope to ResetBridge instance
--
-- Changelog:
-- 2020-Dec-14: Changed file name to ResetBridge
-- 2022-Oct-05: Replaced KEEP with keep_hierarchy. Added the possibility to
-- specify the number of output synchronization stages. Added the
-- possibility to specify an output FF, for replication purposes.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ResetBridge is
Generic (
kPolarity : std_logic := '1';
kStages : natural := 2;
kOutputFF : boolean := false); -- additional output FF for replication
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
aoRst : out STD_LOGIC);
attribute keep_hierarchy : string;
attribute keep_hierarchy of ResetBridge : entity is "yes";
end ResetBridge;
architecture Behavioral of ResetBridge is
signal aRst_int, aoRst_int : std_logic;
begin
aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset
OutputFF_Yes: if kOutputFF generate
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => kStages) --use double FF synchronizer
port map (
aoReset => aRst_int,
aIn => '0',
OutClk => OutClk,
oOut => aoRst_int);
-- Output FF that can be replicated by the tools, if needed
OutputFF: process (OutClk, aoRst_int)
begin
if (aoRst_int = '1') then
aoRst <= kPolarity;
elsif Rising_Edge(OutClk) then
aoRst <= not kPolarity;
end if;
end process;
end generate OutputFF_Yes;
OutputFF_No: if not kOutputFF generate
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kPolarity,
kStages => kStages) --use double FF synchronizer
port map (
aoReset => aRst_int,
aIn => not kPolarity,
OutClk => OutClk,
oOut => aoRst);
end generate OutputFF_No;
end Behavioral; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_4_0;
USE blk_mem_gen_v8_4_0.blk_mem_gen_v8_4_0;
ENTITY design_1_blk_mem_gen_0_3 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_blk_mem_gen_0_3;
ARCHITECTURE design_1_blk_mem_gen_0_3_arch OF design_1_blk_mem_gen_0_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_blk_mem_gen_0_3_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_4_0 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_4_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_blk_mem_gen_0_3_arch: ARCHITECTURE IS "blk_mem_gen_v8_4_0,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_blk_mem_gen_0_3_arch : ARCHITECTURE IS "design_1_blk_mem_gen_0_3,blk_mem_gen_v8_4_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_blk_mem_gen_0_3_arch: ARCHITECTURE IS "design_1_blk_mem_gen_0_3,blk_mem_gen_v8_4_0,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.4,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAM" &
"E=no_coe_file_loaded,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_" &
"WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C" &
"_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 10.7492 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF clkb: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 108, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF clka: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE";
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
BEGIN
U0 : blk_mem_gen_v8_4_0
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 10.7492 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END design_1_blk_mem_gen_0_3_arch;
|
context c1;
context c2;
context my_lib.c1;
context my_lib.c2;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := kintex7;
constant CFG_MEMTECH : integer := kintex7;
constant CFG_PADTECH : integer := kintex7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := kintex7;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (8);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 1 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 16;
constant CFG_DTLBNUM : integer := 16;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 1 + 0;
constant CFG_PCLOW : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 0;
constant CFG_MIG_RANKS : integer := 1;
constant CFG_MIG_COLBITS : integer := 10;
constant CFG_MIG_ROWBITS : integer := 13;
constant CFG_MIG_BANKBITS: integer := 2;
constant CFG_MIG_HMASK : integer := 16#F00#;
-- Xilinx MIG Series 7
constant CFG_MIG_SERIES7 : integer := 1;
constant CFG_MIG_SERIES7_MODEL : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 32;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (7);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
entity FIFO is
end entity fifo;
entity FIFO is
end entity fifo;
entity FIFO is
end entity fifo;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
carryIn : in std_logic;
carryOut : out std_logic;
fnord : out std_logic;
baz : out std_logic_vector(7 downto 0);
clock : in std_logic;
sum : out std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return std_logic;
begin
process(A) is
begin
baz <= "00101100";
case "100" is
when "000" =>
if rising_edge(clock) then
A <= '0';
end if;
when "001" => A <= '1';
when "010" => A <= '1';
when "011" => B <= '1';
when "100" => A <= '0';
when "101" => A <= '1';
when "110" => A <= '1';
when "111" => A <= '1';
end case;
end process;
end behv;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1383.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01383ent IS
END c08s05b00x00p03n01i01383ent;
ARCHITECTURE c08s05b00x00p03n01i01383arch OF c08s05b00x00p03n01i01383ent IS
BEGIN
TESTING: PROCESS
variable v1 : integer := 0;
BEGIN
ch0805_p00301_29_arch := v1; -- illegal name target
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01383 - Target of a variable assignment can not be the name of an architecture body."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01383arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1383.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01383ent IS
END c08s05b00x00p03n01i01383ent;
ARCHITECTURE c08s05b00x00p03n01i01383arch OF c08s05b00x00p03n01i01383ent IS
BEGIN
TESTING: PROCESS
variable v1 : integer := 0;
BEGIN
ch0805_p00301_29_arch := v1; -- illegal name target
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01383 - Target of a variable assignment can not be the name of an architecture body."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01383arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1383.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01383ent IS
END c08s05b00x00p03n01i01383ent;
ARCHITECTURE c08s05b00x00p03n01i01383arch OF c08s05b00x00p03n01i01383ent IS
BEGIN
TESTING: PROCESS
variable v1 : integer := 0;
BEGIN
ch0805_p00301_29_arch := v1; -- illegal name target
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01383 - Target of a variable assignment can not be the name of an architecture body."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01383arch;
|
-- highpass_filter_tb.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity highpass_filter_tb is
end entity;
architecture testbench of highpass_filter_tb is
signal clk : std_logic;
signal rst : std_logic;
signal win_r : std_logic_vector(71 downto 0);
signal win_g : std_logic_vector(71 downto 0);
signal win_b : std_logic_vector(71 downto 0);
signal win_de : std_logic_vector(8 downto 0);
signal win_hs : std_logic_vector(8 downto 0);
signal win_vs : std_logic_vector(8 downto 0);
signal out_r : std_logic_vector(7 downto 0);
signal out_g : std_logic_vector(7 downto 0);
signal out_b : std_logic_vector(7 downto 0);
signal out_de : std_logic;
signal out_hs : std_logic;
signal out_vs : std_logic;
begin
clkgen_i : entity work.clkgen
port map (
CLK => clk,
RST => rst
);
gen_i : entity work.vga_matrix_gen
port map (
CLK => clk,
RST => rst,
R => win_r,
G => win_g,
B => win_b,
HS => win_hs,
VS => win_vs,
DE => win_de
);
dut_i : entity work.highpass_filter
port map (
CLK => clk,
CE => '1',
WIN_R => win_r,
WIN_G => win_g,
WIN_B => win_b,
WIN_DE => win_de,
WIN_HS => win_hs,
WIN_VS => win_vs,
OUT_R => out_r,
OUT_G => out_g,
OUT_B => out_b,
OUT_DE => out_de,
OUT_HS => out_hs,
OUT_VS => out_vs
);
rgb_mon_i : entity work.file_pixel_mon
port map (
CLK => clk,
RST => rst,
R => out_r,
G => out_g,
B => out_b,
DE => out_de,
HS => out_hs,
VS => out_vs
);
end architecture;
|
component Avalon_Test_Streaming is
end component Avalon_Test_Streaming;
u0 : component Avalon_Test_Streaming
port map (
);
|
entity test2 is
begin
end entity;
architecture arch of test2 is
begin
process(all)
begin
loop
exit;
end loop;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_562 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_562;
architecture augh of sub_562 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_562 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_562;
architecture augh of sub_562 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : vhdl_version_layer_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.standard_textio_additions.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.string_methods_pkg.all;
package vhdl_version_layer_pkg is
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural;
procedure increment_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
);
procedure report_alert_counters(
order : t_order
);
end package vhdl_version_layer_pkg;
--=============================================================================
--=============================================================================
package body vhdl_version_layer_pkg is
-- Shared variable for all the alert counters for different attention
shared variable shared_alert_attention_counters : t_alert_attention_counters;
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural is
begin
return shared_alert_attention_counters(alert_level)(attention);
end;
procedure increment_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
) is
begin
shared_alert_attention_counters(alert_level)(attention) :=
shared_alert_attention_counters(alert_level)(attention) + number;
end;
procedure report_alert_counters(
order : t_order
) is
begin
to_string(shared_alert_attention_counters, order);
end;
end package body vhdl_version_layer_pkg;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : vhdl_version_layer_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.standard_textio_additions.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.string_methods_pkg.all;
package vhdl_version_layer_pkg is
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural;
procedure increment_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
);
procedure report_alert_counters(
order : t_order
);
end package vhdl_version_layer_pkg;
--=============================================================================
--=============================================================================
package body vhdl_version_layer_pkg is
-- Shared variable for all the alert counters for different attention
shared variable shared_alert_attention_counters : t_alert_attention_counters;
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural is
begin
return shared_alert_attention_counters(alert_level)(attention);
end;
procedure increment_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
) is
begin
shared_alert_attention_counters(alert_level)(attention) :=
shared_alert_attention_counters(alert_level)(attention) + number;
end;
procedure report_alert_counters(
order : t_order
) is
begin
to_string(shared_alert_attention_counters, order);
end;
end package body vhdl_version_layer_pkg;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : vhdl_version_layer_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.standard_textio_additions.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.string_methods_pkg.all;
package vhdl_version_layer_pkg is
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural;
procedure increment_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
);
procedure report_alert_counters(
order : t_order
);
end package vhdl_version_layer_pkg;
--=============================================================================
--=============================================================================
package body vhdl_version_layer_pkg is
-- Shared variable for all the alert counters for different attention
shared variable shared_alert_attention_counters : t_alert_attention_counters;
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural is
begin
return shared_alert_attention_counters(alert_level)(attention);
end;
procedure increment_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
) is
begin
shared_alert_attention_counters(alert_level)(attention) :=
shared_alert_attention_counters(alert_level)(attention) + number;
end;
procedure report_alert_counters(
order : t_order
) is
begin
to_string(shared_alert_attention_counters, order);
end;
end package body vhdl_version_layer_pkg;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: testlib
-- file: testlib.vhd
-- author: Marko Isomaki - Aeroflex Gaisler
-- description: package for common vhdl functions for testbenches
------------------------------------------------------------------------------
-- pragma translate_off
library std;
use std.standard.all;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library grlib;
use grlib.stdio.all;
use grlib.stdlib.tost;
-- pragma translate_on
package testlib is
-- pragma translate_off
type octet_vector is array (natural range <>) of std_logic_vector(7 downto 0);
subtype data_vector8 is octet_vector;
type data_vector16 is array (natural range <>) of std_logic_vector(15 downto 0);
type data_vector32 is array (natural range <>) of std_logic_vector(31 downto 0);
type data_vector64 is array (natural range <>) of std_logic_vector(63 downto 0);
type data_vector128 is array (natural range <>) of std_logic_vector(127 downto 0);
type data_vector256 is array (natural range <>) of std_logic_vector(255 downto 0);
type nibble_vector is array (natural range <>) of std_logic_vector(3 downto 0);
subtype data_vector is data_vector32;
-----------------------------------------------------------------------------
-- compare function handling '-'. c is the expected data parameter. If it is
--'-' or 'U' then this bit is not compared. Returns true if the vectors match
-----------------------------------------------------------------------------
function compare(o, c: in std_logic_vector) return boolean;
-----------------------------------------------------------------------------
-- compare function handling '-'
-----------------------------------------------------------------------------
function compare(o, c: in std_ulogic_vector) return boolean;
-----------------------------------------------------------------------------
-- this procedure prints a message to standard output. Also includes the time
-- at which it occurs.
-----------------------------------------------------------------------------
procedure print(
constant comment: in string := "-";
constant severe: in severity_level := note;
constant screen: in boolean := true);
-----------------------------------------------------------------------------
-- synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure synchronise(
signal clock: in std_ulogic;
constant offset: in time := 5 ns;
constant enable: in boolean := true);
-----------------------------------------------------------------------------
-- this procedure initialises the test error counters. Used in testbenches
-- with a test variable to check if a subtest has failed and at the end how
-- many subtests have failed. This procedure is called before the first
-- subtest
-----------------------------------------------------------------------------
procedure tinitialise(
variable test: inout boolean;
variable testcount: inout integer);
-----------------------------------------------------------------------------
-- this procedure completes the sub-test. Called at the end of each subtest
-----------------------------------------------------------------------------
procedure tintermediate(
variable test: inout boolean;
variable testcount: inout integer);
-----------------------------------------------------------------------------
-- this procedure completes the test. Called at the end of the complete test
-----------------------------------------------------------------------------
procedure tterminate(
variable test: inout boolean;
variable testcount: inout integer);
-----------------------------------------------------------------------------
-- check std_logic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic_vector;
constant expected: in std_logic_vector;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check std_logic
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic;
constant expected: in std_logic;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check std_ulogic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_ulogic_vector;
constant expected: in std_ulogic_vector;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check natural
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in natural;
constant expected: in natural;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check time
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in time;
constant expected: in time;
constant spread: in time;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check boolean
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in boolean;
constant expected: in boolean;
constant message: in string := "");
-----------------------------------------------------------------------------
-- Convert Data_Vector to Octet_Vector
-----------------------------------------------------------------------------
function conv_octet_vector(
constant d: in data_vector)
return octet_vector;
-----------------------------------------------------------------------------
-- Convert Octet_Vector to Data_Vector, with padding
-----------------------------------------------------------------------------
function conv_data_vector(
constant o: in octet_vector)
return data_vector;
procedure compare(
constant data: in octet_vector;
constant cxdata: in octet_vector;
variable tP: inout boolean);
----------------------------------------------------------------------------
-- Read file contents to octet vector
----------------------------------------------------------------------------
--Expects data only in hex with four bytes on each line.
procedure readfile(
constant filename: in string := "";
constant filetype: in integer := 0;
constant size: in integer := 0;
variable dataout: out octet_vector);
--Reads bytes from a file with the format packets are output from ethereal
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out octet_vector);
----------------------------------------------------------------------------
-- Read file contents to data_vector
----------------------------------------------------------------------------
--Expects data only in hex with four bytes on each line.
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out data_vector);
--generates an random integer from 0 to the maximum value specified with max
procedure gen_rand_int(
constant max : in real;
variable seed1 : inout positive;
variable seed2 : inout positive;
variable rand : out integer);
--reverses std_logic_vector
function reverse(din : std_logic_vector) return std_logic_vector;
-- Returns offset to start of valid data for an access of size 'size' in
-- AMBA data vector
function ahb_doff (
constant dw : integer;
constant size : integer; -- access size
constant addr : std_logic_vector(4 downto 0))
return integer;
-- pragma translate_on
end package testlib;
-- pragma translate_off
--============================================================================--
package body testlib is
-----------------------------------------------------------------------------
-- compare function handling '-'
-----------------------------------------------------------------------------
function compare(o, c: in std_logic_vector) return boolean is
variable t: std_logic_vector(o'range) := c;
variable result: boolean;
begin
result := true;
for i in o'range loop
if not (o(i)=t(i) or t(i)='-' or t(i)='U') then
result := false;
end if;
end loop;
return result;
end function compare;
-----------------------------------------------------------------------------
-- compare function handling '-'
-----------------------------------------------------------------------------
function compare(o, c: in std_ulogic_vector) return boolean is
variable t: std_ulogic_vector(o'range) := c;
variable result: boolean;
begin
result := true;
for i in o'range loop
if not (o(i)=t(i) or t(i)='-' or t(i)='U') then
result := false;
end if;
end loop;
return result;
end function compare;
-----------------------------------------------------------------------------
-- this procedure prints a message to standard output
-----------------------------------------------------------------------------
procedure print(
constant comment: in string := "-";
constant severe: in severity_level := note;
constant screen: in boolean := true) is
variable l: line;
begin
if screen then
write(l, now, right, 15);
write(l, " : " & comment);
if severe = warning then
write(l, string'(" # warning, "));
elsif severe = error then
write(l, string'(" # error, "));
elsif severe = failure then
write(l, string'(" # failure, "));
end if;
writeline(output, l);
end if;
end procedure print;
-----------------------------------------------------------------------------
-- synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure synchronise(
signal clock: in std_ulogic;
constant offset: in time := 5 ns;
constant enable: in boolean := true) is
begin
if enable then
wait until clock = '1'; -- synchronise
wait for offset; -- output offset delay
end if;
end procedure synchronise;
-----------------------------------------------------------------------------
-- this procedure initialises the test error counters
-----------------------------------------------------------------------------
procedure tinitialise(
variable test: inout boolean;
variable testcount: inout integer) is
begin
--------------------------------------------------------------------------
-- initialise test status
--------------------------------------------------------------------------
test := true; -- reset any errors
testcount := 0;
print("--=========================================================--");
print("*** test initialised ¨ ***");
print("--=========================================================--");
end procedure tinitialise;
-----------------------------------------------------------------------------
-- this procedure completes the sub-test
-----------------------------------------------------------------------------
procedure tintermediate(
variable test: inout boolean;
variable testcount: inout integer) is
variable l: line;
begin
--------------------------------------------------------------------------
-- report test status
--------------------------------------------------------------------------
wait for 10 us;
print("--=========================================================--");
if test then
print("*** sub-test completed successfully ***");
if testcount > 0 then
write(l, now, right, 15);
write(l, string'(" : "));
write(l, testcount);
write(l, string'(" sub-test(s) ended with one or more errors."));
writeline(output, l);
end if;
else
print("*** sub-test completed with errors -- # error # -- ***");
testcount := testcount + 1;
test := true;
if testcount > 0 then
write(l, now, right, 15);
write(l, string'(" : "));
write(l, testcount);
write(l, string'(" sub-test(s) ended with one or more errors."));
writeline(output, l);
end if;
end if;
print("--=========================================================--");
end procedure tintermediate;
-----------------------------------------------------------------------------
-- this procedure completes the test
-----------------------------------------------------------------------------
procedure tterminate(
variable test: inout boolean;
variable testcount: inout integer) is
variable l: line;
begin
--------------------------------------------------------------------------
-- end of test
--------------------------------------------------------------------------
wait for 1 ms;
print("--=========================================================--");
if testcount = 0 then
print("*** test completed successfully ***");
else
print("*** test completed with errors -- # error # -- ***");
write(l, now, right, 15);
write(l, string'(" : "));
write(l, testcount);
write(l, string'(" sub-test(s) ended with one or more errors."));
writeline(output, l);
end if;
print("--=========================================================--");
report "---- end of test ----"
severity failure;
wait;
end procedure tterminate;
-----------------------------------------------------------------------------
-- check std_logic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic_vector;
constant expected: in std_logic_vector;
constant message: in string := "") is
variable l: line;
constant padding: std_logic_vector(1 to
(4-(received'length mod 4))) :=
(others => '0');
begin
if not compare(received, expected) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, padding & std_logic_vector(received));
else
hwrite(l, std_logic_vector(received));
end if;
write(l, string'(" expected: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, padding & std_logic_vector(expected));
else
hwrite(l, std_logic_vector(expected));
end if;
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check std_logic
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic;
constant expected: in std_logic;
constant message: in string := "") is
variable l: line;
begin
if not (to_x01z(received)=to_x01z(expected)) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check std_ulogic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_ulogic_vector;
constant expected: in std_ulogic_vector;
constant message: in string := "") is
variable l: line;
constant padding: std_ulogic_vector(1 to
(4-(received'length mod 4))) :=
(others => '0');
begin
if not compare(received, expected) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, std_logic_vector(padding) & std_logic_vector(received));
else
hwrite(l, std_logic_vector(received));
end if;
write(l, string'(" expected: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, std_logic_vector(padding) & std_logic_vector(expected));
else
hwrite(l, std_logic_vector(expected));
end if;
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check natural
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in natural;
constant expected: in natural;
constant message: in string := "") is
variable l: line;
begin
if received /= expected then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check time
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in time;
constant expected: in time;
constant spread: in time;
constant message: in string := "") is
variable l: line;
begin
if (received > expected+spread) or
(received < expected-spread) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check boolean
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in boolean;
constant expected: in boolean;
constant message: in string := "") is
variable l: line;
begin
if received /= expected then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- Convert Data_Vector to Octet_Vector
-----------------------------------------------------------------------------
function conv_octet_vector(
constant d: in data_vector)
return octet_vector is
variable o: octet_vector(0 to d'Length*4-1);
begin
for i in o'range loop
o(i) := d(i/4)((3-(i mod 4))*8+7 downto (3-(i mod 4))*8);
end loop;
return o;
end function conv_octet_vector;
-----------------------------------------------------------------------------
-- Convert Octet_Vector to Data_Vector, with padding
-----------------------------------------------------------------------------
function conv_data_vector(
constant o: in octet_vector)
return data_vector is
variable d: data_vector(0 to (1+(o'Length-1)/4)-1);
begin
for i in o'Range loop
d(i/4)((3-(i mod 4))*8+7 downto (3-(i mod 4))*8) := o(i);
end loop;
return d;
end function conv_data_vector;
procedure compare(
constant data: in octet_vector;
constant cxdata: in octet_vector;
variable tp: inout boolean) is
begin
if (data'length /= cxdata'length) then
tp := false;
print("compare error: lengths do not match");
else
for i in data'low to data'low+data'length-1 loop
if not compare(data(i), cxdata(i)) then
tp := false;
print("compare error. index: " & tost(i) & " data: " & tost(data(i)) & " expected: " & tost(cxdata(i)));
end if;
end loop;
end if;
end compare;
function FromChar(C: Character) return Std_Logic_Vector is
variable R: Std_Logic_Vector(0 to 3);
begin
case C is
when '0' => R := "0000";
when '1' => R := "0001";
when '2' => R := "0010";
when '3' => R := "0011";
when '4' => R := "0100";
when '5' => R := "0101";
when '6' => R := "0110";
when '7' => R := "0111";
when '8' => R := "1000";
when '9' => R := "1001";
when 'A' => R := "1010";
when 'B' => R := "1011";
when 'C' => R := "1100";
when 'D' => R := "1101";
when 'E' => R := "1110";
when 'F' => R := "1111";
when 'a' => R := "1010";
when 'b' => R := "1011";
when 'c' => R := "1100";
when 'd' => R := "1101";
when 'e' => R := "1110";
when 'f' => R := "1111";
when others => R := "XXXX";
end case;
return R;
end FromChar;
procedure readfile(
constant filename: in string := "";
constant filetype: in integer := 0;
constant size: in integer := 0;
variable dataout: out octet_vector) is
file readfile: text;
variable l: line;
variable test: boolean := true;
variable count: integer := 0;
variable dtmp: std_logic_vector(31 downto 0);
variable data: octet_vector(0 to size-1);
variable i: integer := 0;
variable good: boolean := true;
variable c: character;
begin
if size /= 0 then
if filename = "" then
print("no file given");
else
if filetype = 0 then
file_open(readfile, filename, read_mode);
while not endfile(readfile) loop
readline(readfile, l);
hread(l, dtmp, test);
if (not test) then
print("illegal data in file");
exit;
end if;
for i in 0 to 3 loop
data(count) := dtmp(31-i*8 downto 24-i*8);
count := count + 1;
if count >= size then
exit;
end if;
end loop;
if count >= size then
exit;
end if;
end loop;
if count < size then
print("not enough data in file");
else
for i in 0 to size-1 loop
dataout(dataout'low+i) := data(i);
end loop;
end if;
else
file_open(readfile, filename, read_mode);
while not endfile(readfile) loop
readline(readfile, L);
while (i < 4) loop
Read(L, C, good);
if not good then
Print("Error in read data");
exit;
end if;
if (C = character'val(32)) or (C = character'val(160)) or (C = HT) then
next;
else
i := i + 1;
end if;
end loop;
i := 0;
while (i < 32) loop
Read(L, C, good);
if not good then
Print("Error in read data");
exit;
end if;
if (C = character'val(32)) or (C = character'val(160)) or (C = HT) then
next;
else
if (i mod 2) = 0 then
data(count)(7 downto 4) := fromchar(C);
else
data(count)(3 downto 0) := fromchar(C);
-- Print(tost(data(count)));
count := count + 1;
if count >= size then
exit;
end if;
end if;
i := i + 1;
end if;
end loop;
i := 0;
end loop;
if count < size then
Print("Not enough data in file");
else
dataout := data;
end if;
end if;
end if;
else
print("size is zero. no data read");
end if;
end procedure;
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out octet_vector) is
begin
readfile(filename, 0, size, dataout);
end procedure;
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out data_vector) is
file readfile: text;
variable l: line;
variable test: boolean := true;
variable count: integer := 0;
variable data: data_vector(0 to size/4);
begin
if size /= 0 then
if filename = "" then
print("no file given");
else
file_open(readfile, filename, read_mode);
while not endfile(readfile) loop
readline(readfile, l);
hread(l, data(count/4), test);
if (not test) then
print("illegal data in file");
exit;
end if;
count := count + 4;
if count >= size then
exit;
end if;
end loop;
if count < size then
print("not enough data in file");
else
if (size mod 4) = 0 then
dataout(dataout'low to dataout'low+data'high-1) :=
data(0 to data'high-1);
else
dataout(dataout'low to dataout'low+data'high) := data(0 to data'high);
end if;
end if;
end if;
else
print("size is zero. no data read");
end if;
end procedure;
procedure gen_rand_int(
constant max : in real;
variable seed1 : inout positive;
variable seed2 : inout positive;
variable rand : out integer) is
variable rand_tmp : real;
begin
uniform(seed1, seed2, rand_tmp);
rand := integer(floor(rand_tmp*max));
end procedure;
function reverse(din : std_logic_vector)
return std_logic_vector is
variable dout: std_logic_vector(din'REVERSE_RANGE);
begin
for i in din'RANGE loop dout(i) := din(i); end loop;
return dout;
end function reverse;
function ahb_doff (
constant dw : integer;
constant size : integer;
constant addr : std_logic_vector(4 downto 0))
return integer is
variable off : integer;
begin -- ahb_doff
if size < 256 and dw = 256 and addr(4) = '0' then off := 128; else off := 0; end if;
if size < 128 and dw >= 128 and addr(3) = '0' then off := off + 64; end if;
if size < 64 and dw >= 64 and addr(2) = '0' then off := off + 32; end if;
if size < 32 and addr(1) = '0' then off := off + 16; end if;
if size < 16 and addr(0) = '0' then off := off + 8; end if;
return off;
end ahb_doff;
end package body ; --=======================================--
-- pragma translate_on
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= hex_to_std_logic_vector("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"instructionROM.mif",
DEFAULT_DATA,
32,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
-- SIMON 64/128
-- feistel round function operation gamma
-- gamma(x,y) = (x xor y)
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- x_in: half block 1
-- y_in: half block 2
-- x_out: xor of both inputs
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gamma is
port(x_in : in std_logic_vector(31 downto 0);
y_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0)
);
end gamma;
architecture Behavioral of gamma is
begin
x_out <= x_in xor y_in;
end Behavioral; |
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