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-- SIMON 64/128
-- feistel round function operation gamma
-- gamma(x,y) = (x xor y)
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- x_in: half block 1
-- y_in: half block 2
-- x_out: xor of both inputs
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gamma is
port(x_in : in std_logic_vector(31 downto 0);
y_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0)
);
end gamma;
architecture Behavioral of gamma is
begin
x_out <= x_in xor y_in;
end Behavioral; |
-- SIMON 64/128
-- feistel round function operation gamma
-- gamma(x,y) = (x xor y)
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- x_in: half block 1
-- y_in: half block 2
-- x_out: xor of both inputs
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gamma is
port(x_in : in std_logic_vector(31 downto 0);
y_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0)
);
end gamma;
architecture Behavioral of gamma is
begin
x_out <= x_in xor y_in;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:55:53 06/12/2014
-- Design Name:
-- Module Name: RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAM is
PORT(
clk: IN std_logic;
address: IN std_logic_vector(31 downto 0);
read_en: IN std_logic;
data_out: OUT std_logic_vector(7 downto 0)
);
end RAM;
architecture Behavioral of RAM is
begin
process(clk)
begin
if rising_edge(clk)then
if read_en = '1' then
data_out <= (others => '1');
end if;
end if;
end process;
end Behavioral;
|
-- 8 bit up counter with parallel load
-- (c) Cliff Chapman 2013
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY up_counter IS
PORT (
-- Load. When run is low used for parallel load
load : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- Clock Input
clk : IN STD_LOGIC;
-- Run/Set. High to run, low to set from load input
run : IN STD_LOGIC;
-- Async reset.
rst : IN STD_LOGIC := '0';
-- Output value
v : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END up_counter;
ARCHITECTURE counter OF up_counter IS
SIGNAL reg_count : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
-- Count up on rising clock while running
counter : PROCESS (clk, run, load, rst, reg_count) BEGIN
IF (rst = '1') THEN
reg_count <= "00000000";
ELSIF (run = '0') THEN
reg_count <= load;
ELSIF (rising_edge(clk)) THEN
IF (run = '1') THEN
-- Regular run
reg_count <= reg_count + 1;
END IF;
ELSE
reg_count <= reg_count;
END IF;
END PROCESS counter;
v <= reg_count;
END ARCHITECTURE; |
architecture RTL of FIFO is
begin
-- These are passing
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
a <= b;
a <= when c = '0' else '1';
-- Failing variations
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
a<= b;
a <= when c = '0' else '1';
-- Testing generate breaks
a <= b;
gen : if '1' = '1' generate
anExtraLoooooooooooooooooooongName <= c;
end generate gen;
aSlighltyLongerName <= d;
b <= c;
a <= b;
gen : for i in 0 to 7 generate
anExtraLoooooooooooooooooooongName <= c;
end generate gen;
aSlighltyLongerName <= d;
b <= c;
a <= b;
aSlightlyLooongerName <= c;
LABEL0 : case a & b & c generate
when "000" =>
anExtraLoooooooooooooooooooongName <= c;
anExtraLoooooooooooongName <= c;
when "001" =>
anExtraLoooooooooooooooongName <= c;
anExtraLooooooooooooooooooooooooongName <= c;
end generate LABEL0;
aSlighltyLongerName <= d;
b <= c;
end architecture RTL;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00578
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.4 (2)
-- 11.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00578
-- PKG00578/BODY
-- ENT00578(ARCH00578)
-- ENT00578_Test_Bench(ARCH00578_Test_Bench)
-- CONF00578
--
-- REVISION HISTORY:
--
-- 20-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
package PKG00578 is
function F return TIME ; -- predefined physical type TIME
end PKG00578 ;
package body PKG00578 is
function F return TIME is
begin
return NOW ; -- predefined function NOW
end F;
end PKG00578 ;
use WORK.PKG00578.all ;
entity ENT00578 is
generic (G : NATURAL := 0); -- predefined numeric subtype NATURAL
port (P : BIT := '1') ; -- predefined enumeration type BIT
begin
assert G < NATURAL'HIGH -- predefined attribute HIGH
report "Assert in Entity should never occur -- test failed" ;
end ENT00578 ;
use WORK.STANDARD_TYPES.all;
architecture ARCH00578 of ENT00578 is begin
L_X_1 : block
subtype ST is BIT_VECTOR (1 to 1) ; -- predefined array type
signal S : ST := b"1" ;
begin
process
begin
test_report ( "ARCH00578" ,
"Standard is implicitly use'd" ,
(G = 1) and
(P = '1') and
(S = "1") and
(F = 0 ns) ) ;
wait ;
end process;
end block;
end;
entity ENT00578_Test_Bench is
end ENT00578_Test_Bench ;
architecture ARCH00578_Test_Bench of ENT00578_Test_Bench is
begin
L1:
block
component UUT
end component ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00578_Test_Bench ;
configuration CONF00578 of WORK.ENT00578_Test_Bench is
for ARCH00578_Test_Bench
for L1
for CIS1 : UUT
use entity WORK.ENT00578 ( ARCH00578 )
generic map ( 1 )
port map ( open ) ;
end for ;
end for ;
end for ;
end CONF00578 ;
|
-- Copyright (c) 2006 Rice University
-- All Rights Reserved
-- This code is covered by the Rice-WARP license
-- See http://warp.rice.edu/license/ for details
------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library opb_ipif_v3_01_c;
use opb_ipif_v3_01_c.all;
library radio_controller_v1_10_a;
use radio_controller_v1_10_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_OPB_AWIDTH -- OPB address bus width
-- C_OPB_DWIDTH -- OPB data bus width
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- OPB_Clk -- OPB Clock
-- OPB_Rst -- OPB Reset
-- Sl_DBus -- Slave data bus
-- Sl_errAck -- Slave error acknowledge
-- Sl_retry -- Slave retry
-- Sl_toutSup -- Slave timeout suppress
-- Sl_xferAck -- Slave transfer acknowledge
-- OPB_ABus -- OPB address bus
-- OPB_BE -- OPB byte enable
-- OPB_DBus -- OPB data bus
-- OPB_RNW -- OPB read/not write
-- OPB_select -- OPB select
-- OPB_seqAddr -- OPB sequential address
------------------------------------------------------------------------------
entity radio_controller is
generic
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"0000FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
spi_clk : out std_logic;
data_out : out std_logic;
radio1_cs : out std_logic;
radio2_cs : out std_logic;
radio3_cs : out std_logic;
radio4_cs : out std_logic;
dac1_cs : out std_logic;
dac2_cs : out std_logic;
dac3_cs : out std_logic;
dac4_cs : out std_logic;
radio1_SHDN : out std_logic;
radio1_TxEn : out std_logic;
radio1_RxEn : out std_logic;
radio1_RxHP : out std_logic;
radio1_LD : in std_logic;
radio1_24PA : out std_logic;
radio1_5PA : out std_logic;
radio1_ANTSW : out std_logic_vector(0 to 1);
radio1_LED : out std_logic_vector(0 to 2);
radio1_ADC_RX_DCS : out std_logic;
radio1_ADC_RX_DFS : out std_logic;
radio1_ADC_RX_OTRA : in std_logic;
radio1_ADC_RX_OTRB : in std_logic;
radio1_ADC_RX_PWDNA : out std_logic;
radio1_ADC_RX_PWDNB : out std_logic;
radio1_DIPSW : in std_logic_vector(0 to 3);
radio1_RSSI_ADC_CLAMP : out std_logic;
radio1_RSSI_ADC_HIZ : out std_logic;
radio1_RSSI_ADC_OTR : in std_logic;
radio1_RSSI_ADC_SLEEP : out std_logic;
radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio1_TX_DAC_PLL_LOCK : in std_logic;
radio1_TX_DAC_RESET : out std_logic;
radio1_SHDN_external : in std_logic;
radio1_TxEn_external : in std_logic;
radio1_RxEn_external : in std_logic;
radio1_RxHP_external : in std_logic;
radio1_TxGain : out std_logic_vector(0 to 5);
radio1_TxStart : out std_logic;
radio2_SHDN : out std_logic;
radio2_TxEn : out std_logic;
radio2_RxEn : out std_logic;
radio2_RxHP : out std_logic;
radio2_LD : in std_logic;
radio2_24PA : out std_logic;
radio2_5PA : out std_logic;
radio2_ANTSW : out std_logic_vector(0 to 1);
radio2_LED : out std_logic_vector(0 to 2);
radio2_ADC_RX_DCS : out std_logic;
radio2_ADC_RX_DFS : out std_logic;
radio2_ADC_RX_OTRA : in std_logic;
radio2_ADC_RX_OTRB : in std_logic;
radio2_ADC_RX_PWDNA : out std_logic;
radio2_ADC_RX_PWDNB : out std_logic;
radio2_DIPSW : in std_logic_vector(0 to 3);
radio2_RSSI_ADC_CLAMP : out std_logic;
radio2_RSSI_ADC_HIZ : out std_logic;
radio2_RSSI_ADC_OTR : in std_logic;
radio2_RSSI_ADC_SLEEP : out std_logic;
radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio2_TX_DAC_PLL_LOCK : in std_logic;
radio2_TX_DAC_RESET : out std_logic;
radio2_SHDN_external : in std_logic;
radio2_TxEn_external : in std_logic;
radio2_RxEn_external : in std_logic;
radio2_RxHP_external : in std_logic;
radio2_TxGain : out std_logic_vector(0 to 5);
radio2_TxStart : out std_logic;
radio3_SHDN : out std_logic;
radio3_TxEn : out std_logic;
radio3_RxEn : out std_logic;
radio3_RxHP : out std_logic;
radio3_LD : in std_logic;
radio3_24PA : out std_logic;
radio3_5PA : out std_logic;
radio3_ANTSW : out std_logic_vector(0 to 1);
radio3_LED : out std_logic_vector(0 to 2);
radio3_ADC_RX_DCS : out std_logic;
radio3_ADC_RX_DFS : out std_logic;
radio3_ADC_RX_OTRA : in std_logic;
radio3_ADC_RX_OTRB : in std_logic;
radio3_ADC_RX_PWDNA : out std_logic;
radio3_ADC_RX_PWDNB : out std_logic;
radio3_DIPSW : in std_logic_vector(0 to 3);
radio3_RSSI_ADC_CLAMP : out std_logic;
radio3_RSSI_ADC_HIZ : out std_logic;
radio3_RSSI_ADC_OTR : in std_logic;
radio3_RSSI_ADC_SLEEP : out std_logic;
radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio3_TX_DAC_PLL_LOCK : in std_logic;
radio3_TX_DAC_RESET : out std_logic;
radio3_SHDN_external : in std_logic;
radio3_TxEn_external : in std_logic;
radio3_RxEn_external : in std_logic;
radio3_RxHP_external : in std_logic;
radio3_TxGain : out std_logic_vector(0 to 5);
radio3_TxStart : out std_logic;
radio4_SHDN : out std_logic;
radio4_TxEn : out std_logic;
radio4_RxEn : out std_logic;
radio4_RxHP : out std_logic;
radio4_LD : in std_logic;
radio4_24PA : out std_logic;
radio4_5PA : out std_logic;
radio4_ANTSW : out std_logic_vector(0 to 1);
radio4_LED : out std_logic_vector(0 to 2);
radio4_ADC_RX_DCS : out std_logic;
radio4_ADC_RX_DFS : out std_logic;
radio4_ADC_RX_OTRA : in std_logic;
radio4_ADC_RX_OTRB : in std_logic;
radio4_ADC_RX_PWDNA : out std_logic;
radio4_ADC_RX_PWDNB : out std_logic;
radio4_DIPSW : in std_logic_vector(0 to 3);
radio4_RSSI_ADC_CLAMP : out std_logic;
radio4_RSSI_ADC_HIZ : out std_logic;
radio4_RSSI_ADC_OTR : in std_logic;
radio4_RSSI_ADC_SLEEP : out std_logic;
radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio4_TX_DAC_PLL_LOCK : in std_logic;
radio4_TX_DAC_RESET : out std_logic;
radio4_SHDN_external : in std_logic;
radio4_TxEn_external : in std_logic;
radio4_RxEn_external : in std_logic;
radio4_RxHP_external : in std_logic;
radio4_TxGain : out std_logic_vector(0 to 5);
radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity radio_controller;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of radio_controller is
------------------------------------------
-- Constant: array of address range identifiers
------------------------------------------
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_00 -- user logic S/W register address space
);
------------------------------------------
-- Constant: array of address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
constant USER_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address
);
------------------------------------------
-- Constant: array of data widths for each target address range
------------------------------------------
constant USER_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH -- user logic data width
);
------------------------------------------
-- Constant: array of desired number of chip enables for each address range
------------------------------------------
constant USER_NUM_CE : integer := 17;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_CE) -- user logic number of CEs
);
------------------------------------------
-- Constant: array of unique properties for each address range
------------------------------------------
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0) -- user logic slave space dependent properties (none defined)
);
------------------------------------------
-- Constant: pipeline mode
-- 1 = include OPB-In pipeline registers
-- 2 = include IP pipeline registers
-- 3 = include OPB-In and IP pipeline registers
-- 4 = include OPB-Out pipeline registers
-- 5 = include OPB-In and OPB-Out pipeline registers
-- 6 = include IP and OPB-Out pipeline registers
-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
-- Note:
-- only mode 4, 5, 7 are supported for this release
------------------------------------------
constant PIPELINE_MODEL : integer := 5;
------------------------------------------
-- Constant: user core ID code
------------------------------------------
constant DEV_BLK_ID : integer := 0;
------------------------------------------
-- Constant: enable MIR/Reset register
------------------------------------------
constant DEV_MIR_ENABLE : integer := 0;
------------------------------------------
-- Constant: array of IP interrupt mode
-- 1 = Active-high interrupt condition
-- 2 = Active-low interrupt condition
-- 3 = Active-high pulse interrupt event
-- 4 = Active-low pulse interrupt event
-- 5 = Positive-edge interrupt event
-- 6 = Negative-edge interrupt event
------------------------------------------
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
------------------------------------------
-- Constant: enable device burst
------------------------------------------
constant DEV_BURST_ENABLE : integer := 0;
------------------------------------------
-- Constant: include address counter for burst transfers
------------------------------------------
constant INCLUDE_ADDR_CNTR : integer := 0;
------------------------------------------
-- Constant: include write buffer that decouples OPB and IPIC write transactions
------------------------------------------
constant INCLUDE_WR_BUF : integer := 0;
------------------------------------------
-- Constant: index for CS/CE
------------------------------------------
constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
signal iIP2Bus_Ack : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal ENABLE_POSTED_WRITE : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- enable posted write behavior
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 17
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
spi_clk : out std_logic;
data_out : out std_logic;
Radio1_cs : out std_logic;
Radio2_cs : out std_logic;
Radio3_cs : out std_logic;
Radio4_cs : out std_logic;
Dac1_cs : out std_logic;
Dac2_cs : out std_logic;
Dac3_cs : out std_logic;
Dac4_cs : out std_logic;
Radio1_SHDN : out std_logic;
Radio1_TxEn : out std_logic;
Radio1_RxEn : out std_logic;
Radio1_RxHP : out std_logic;
Radio1_LD : in std_logic;
Radio1_24PA : out std_logic;
Radio1_5PA : out std_logic;
Radio1_ANTSW : out std_logic_vector(0 to 1);
Radio1_LED : out std_logic_vector(0 to 2);
Radio1_ADC_RX_DCS : out std_logic;
Radio1_ADC_RX_DFS : out std_logic;
Radio1_ADC_RX_OTRA : in std_logic;
Radio1_ADC_RX_OTRB : in std_logic;
Radio1_ADC_RX_PWDNA : out std_logic;
Radio1_ADC_RX_PWDNB : out std_logic;
Radio1_DIPSW : in std_logic_vector(0 to 3);
Radio1_RSSI_ADC_CLAMP : out std_logic;
Radio1_RSSI_ADC_HIZ : out std_logic;
Radio1_RSSI_ADC_OTR : in std_logic;
Radio1_RSSI_ADC_SLEEP : out std_logic;
Radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio1_TX_DAC_PLL_LOCK : in std_logic;
Radio1_TX_DAC_RESET : out std_logic;
Radio1_SHDN_external : in std_logic;
Radio1_TxEn_external : in std_logic;
Radio1_RxEn_external : in std_logic;
Radio1_RxHP_external : in std_logic;
Radio1_TxGain : out std_logic_vector(0 to 5);
Radio1_TxStart : out std_logic;
Radio2_SHDN : out std_logic;
Radio2_TxEn : out std_logic;
Radio2_RxEn : out std_logic;
Radio2_RxHP : out std_logic;
Radio2_LD : in std_logic;
Radio2_24PA : out std_logic;
Radio2_5PA : out std_logic;
Radio2_ANTSW : out std_logic_vector(0 to 1);
Radio2_LED : out std_logic_vector(0 to 2);
Radio2_ADC_RX_DCS : out std_logic;
Radio2_ADC_RX_DFS : out std_logic;
Radio2_ADC_RX_OTRA : in std_logic;
Radio2_ADC_RX_OTRB : in std_logic;
Radio2_ADC_RX_PWDNA : out std_logic;
Radio2_ADC_RX_PWDNB : out std_logic;
Radio2_DIPSW : in std_logic_vector(0 to 3);
Radio2_RSSI_ADC_CLAMP : out std_logic;
Radio2_RSSI_ADC_HIZ : out std_logic;
Radio2_RSSI_ADC_OTR : in std_logic;
Radio2_RSSI_ADC_SLEEP : out std_logic;
Radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio2_TX_DAC_PLL_LOCK : in std_logic;
Radio2_TX_DAC_RESET : out std_logic;
Radio2_SHDN_external : in std_logic;
Radio2_TxEn_external : in std_logic;
Radio2_RxEn_external : in std_logic;
Radio2_RxHP_external : in std_logic;
Radio2_TxGain : out std_logic_vector(0 to 5);
Radio2_TxStart : out std_logic;
Radio3_SHDN : out std_logic;
Radio3_TxEn : out std_logic;
Radio3_RxEn : out std_logic;
Radio3_RxHP : out std_logic;
Radio3_LD : in std_logic;
Radio3_24PA : out std_logic;
Radio3_5PA : out std_logic;
Radio3_ANTSW : out std_logic_vector(0 to 1);
Radio3_LED : out std_logic_vector(0 to 2);
Radio3_ADC_RX_DCS : out std_logic;
Radio3_ADC_RX_DFS : out std_logic;
Radio3_ADC_RX_OTRA : in std_logic;
Radio3_ADC_RX_OTRB : in std_logic;
Radio3_ADC_RX_PWDNA : out std_logic;
Radio3_ADC_RX_PWDNB : out std_logic;
Radio3_DIPSW : in std_logic_vector(0 to 3);
Radio3_RSSI_ADC_CLAMP : out std_logic;
Radio3_RSSI_ADC_HIZ : out std_logic;
Radio3_RSSI_ADC_OTR : in std_logic;
Radio3_RSSI_ADC_SLEEP : out std_logic;
Radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio3_TX_DAC_PLL_LOCK : in std_logic;
Radio3_TX_DAC_RESET : out std_logic;
Radio3_SHDN_external : in std_logic;
Radio3_TxEn_external : in std_logic;
Radio3_RxEn_external : in std_logic;
Radio3_RxHP_external : in std_logic;
Radio3_TxGain : out std_logic_vector(0 to 5);
Radio3_TxStart : out std_logic;
Radio4_SHDN : out std_logic;
Radio4_TxEn : out std_logic;
Radio4_RxEn : out std_logic;
Radio4_RxHP : out std_logic;
Radio4_LD : in std_logic;
Radio4_24PA : out std_logic;
Radio4_5PA : out std_logic;
Radio4_ANTSW : out std_logic_vector(0 to 1);
Radio4_LED : out std_logic_vector(0 to 2);
Radio4_ADC_RX_DCS : out std_logic;
Radio4_ADC_RX_DFS : out std_logic;
Radio4_ADC_RX_OTRA : in std_logic;
Radio4_ADC_RX_OTRB : in std_logic;
Radio4_ADC_RX_PWDNA : out std_logic;
Radio4_ADC_RX_PWDNB : out std_logic;
Radio4_DIPSW : in std_logic_vector(0 to 3);
Radio4_RSSI_ADC_CLAMP : out std_logic;
Radio4_RSSI_ADC_HIZ : out std_logic;
Radio4_RSSI_ADC_OTR : in std_logic;
Radio4_RSSI_ADC_SLEEP : out std_logic;
Radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio4_TX_DAC_PLL_LOCK : in std_logic;
Radio4_TX_DAC_RESET : out std_logic;
Radio4_SHDN_external : in std_logic;
Radio4_TxEn_external : in std_logic;
Radio4_RxEn_external : in std_logic;
Radio4_RxHP_external : in std_logic;
Radio4_TxGain : out std_logic_vector(0 to 5);
Radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
OPB_IPIF_I : entity opb_ipif_v3_01_c.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => PIPELINE_MODEL,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sl_DBus,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_retry => Sl_retry,
Sln_toutSup => Sl_toutSup,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_Addr => open,
Bus2IP_AddrValid => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_RNW => open,
Bus2IP_Burst => open,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_AddrAck => '0',
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => ENABLE_POSTED_WRITE,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => ZERO_WFIFO2IP_Data,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
Freeze => '0',
Bus2IP_Freeze => open,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => iBus2IP_Clk,
IP2Bus_Clk => '0',
Reset => OPB_Rst,
Bus2IP_Reset => iBus2IP_Reset
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
C_DWIDTH => USER_DWIDTH,
C_NUM_CE => USER_NUM_CE
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
spi_clk => spi_clk,
data_out => data_out,
Radio1_cs => radio1_cs,
Radio2_cs => radio2_cs,
Radio3_cs => radio3_cs,
Radio4_cs => radio4_cs,
Dac1_cs => dac1_cs,
Dac2_cs => dac2_cs,
Dac3_cs => dac3_cs,
Dac4_cs => dac4_cs,
Radio1_SHDN => radio1_SHDN,
Radio1_TxEn => radio1_TxEn,
Radio1_RxEn => radio1_RxEn,
Radio1_RxHP => radio1_RxHP,
Radio1_LD => radio1_LD,
Radio1_24PA => radio1_24PA,
Radio1_5PA => radio1_5PA,
Radio1_ANTSW => radio1_ANTSW,
Radio1_LED => radio1_LED,
Radio1_ADC_RX_DCS => radio1_ADC_RX_DCS,
Radio1_ADC_RX_DFS => radio1_ADC_RX_DFS,
Radio1_ADC_RX_OTRA => radio1_ADC_RX_OTRA,
Radio1_ADC_RX_OTRB => radio1_ADC_RX_OTRB,
Radio1_ADC_RX_PWDNA => radio1_ADC_RX_PWDNA,
Radio1_ADC_RX_PWDNB => radio1_ADC_RX_PWDNB,
Radio1_DIPSW => radio1_DIPSW,
Radio1_RSSI_ADC_CLAMP => radio1_RSSI_ADC_CLAMP,
Radio1_RSSI_ADC_HIZ => radio1_RSSI_ADC_HIZ,
Radio1_RSSI_ADC_OTR => radio1_RSSI_ADC_OTR,
Radio1_RSSI_ADC_SLEEP => radio1_RSSI_ADC_SLEEP,
Radio1_RSSI_ADC_D => radio1_RSSI_ADC_D,
Radio1_TX_DAC_PLL_LOCK => radio1_TX_DAC_PLL_LOCK,
Radio1_TX_DAC_RESET => radio1_TX_DAC_RESET,
Radio1_SHDN_external => radio1_SHDN_external,
Radio1_TxEn_external => radio1_TxEn_external,
Radio1_RxEn_external => radio1_RxEn_external,
Radio1_RxHP_external => radio1_RxHP_external,
Radio1_TxGain => radio1_TxGain,
Radio1_TxStart => radio1_TxStart,
Radio2_SHDN => radio2_SHDN,
Radio2_TxEn => radio2_TxEn,
Radio2_RxEn => radio2_RxEn,
Radio2_RxHP => radio2_RxHP,
Radio2_LD => radio2_LD,
Radio2_24PA => radio2_24PA,
Radio2_5PA => radio2_5PA,
Radio2_ANTSW => radio2_ANTSW,
Radio2_LED => radio2_LED,
Radio2_ADC_RX_DCS => radio2_ADC_RX_DCS,
Radio2_ADC_RX_DFS => radio2_ADC_RX_DFS,
Radio2_ADC_RX_OTRA => radio2_ADC_RX_OTRA,
Radio2_ADC_RX_OTRB => radio2_ADC_RX_OTRB,
Radio2_ADC_RX_PWDNA => radio2_ADC_RX_PWDNA,
Radio2_ADC_RX_PWDNB => radio2_ADC_RX_PWDNB,
Radio2_DIPSW => radio2_DIPSW,
Radio2_RSSI_ADC_CLAMP => radio2_RSSI_ADC_CLAMP,
Radio2_RSSI_ADC_HIZ => radio2_RSSI_ADC_HIZ,
Radio2_RSSI_ADC_OTR => radio2_RSSI_ADC_OTR,
Radio2_RSSI_ADC_SLEEP => radio2_RSSI_ADC_SLEEP,
Radio2_RSSI_ADC_D => radio2_RSSI_ADC_D,
Radio2_TX_DAC_PLL_LOCK => radio2_TX_DAC_PLL_LOCK,
Radio2_TX_DAC_RESET => radio2_TX_DAC_RESET,
Radio2_SHDN_external => radio2_SHDN_external,
Radio2_TxEn_external => radio2_TxEn_external,
Radio2_RxEn_external => radio2_RxEn_external,
Radio2_RxHP_external => radio2_RxHP_external,
Radio2_TxGain => radio2_TxGain,
Radio2_TxStart => radio2_TxStart,
Radio3_SHDN => radio3_SHDN,
Radio3_TxEn => radio3_TxEn,
Radio3_RxEn => radio3_RxEn,
Radio3_RxHP => radio3_RxHP,
Radio3_LD => radio3_LD,
Radio3_24PA => radio3_24PA,
Radio3_5PA => radio3_5PA,
Radio3_ANTSW => radio3_ANTSW,
Radio3_LED => radio3_LED,
Radio3_ADC_RX_DCS => radio3_ADC_RX_DCS,
Radio3_ADC_RX_DFS => radio3_ADC_RX_DFS,
Radio3_ADC_RX_OTRA => radio3_ADC_RX_OTRA,
Radio3_ADC_RX_OTRB => radio3_ADC_RX_OTRB,
Radio3_ADC_RX_PWDNA => radio3_ADC_RX_PWDNA,
Radio3_ADC_RX_PWDNB => radio3_ADC_RX_PWDNB,
Radio3_DIPSW => radio3_DIPSW,
Radio3_RSSI_ADC_CLAMP => radio3_RSSI_ADC_CLAMP,
Radio3_RSSI_ADC_HIZ => radio3_RSSI_ADC_HIZ,
Radio3_RSSI_ADC_OTR => radio3_RSSI_ADC_OTR,
Radio3_RSSI_ADC_SLEEP => radio3_RSSI_ADC_SLEEP,
Radio3_RSSI_ADC_D => radio3_RSSI_ADC_D,
Radio3_TX_DAC_PLL_LOCK => radio3_TX_DAC_PLL_LOCK,
Radio3_TX_DAC_RESET => radio3_TX_DAC_RESET,
Radio3_SHDN_external => radio3_SHDN_external,
Radio3_TxEn_external => radio3_TxEn_external,
Radio3_RxEn_external => radio3_RxEn_external,
Radio3_RxHP_external => radio3_RxHP_external,
Radio3_TxGain => radio3_TxGain,
Radio3_TxStart => radio3_TxStart,
Radio4_SHDN => radio4_SHDN,
Radio4_TxEn => radio4_TxEn,
Radio4_RxEn => radio4_RxEn,
Radio4_RxHP => radio4_RxHP,
Radio4_LD => radio4_LD,
Radio4_24PA => radio4_24PA,
Radio4_5PA => radio4_5PA,
Radio4_ANTSW => radio4_ANTSW,
Radio4_LED => radio4_LED,
Radio4_ADC_RX_DCS => radio4_ADC_RX_DCS,
Radio4_ADC_RX_DFS => radio4_ADC_RX_DFS,
Radio4_ADC_RX_OTRA => radio4_ADC_RX_OTRA,
Radio4_ADC_RX_OTRB => radio4_ADC_RX_OTRB,
Radio4_ADC_RX_PWDNA => radio4_ADC_RX_PWDNA,
Radio4_ADC_RX_PWDNB => radio4_ADC_RX_PWDNB,
Radio4_DIPSW => radio4_DIPSW,
Radio4_RSSI_ADC_CLAMP => radio4_RSSI_ADC_CLAMP,
Radio4_RSSI_ADC_HIZ => radio4_RSSI_ADC_HIZ,
Radio4_RSSI_ADC_OTR => radio4_RSSI_ADC_OTR,
Radio4_RSSI_ADC_SLEEP => radio4_RSSI_ADC_SLEEP,
Radio4_RSSI_ADC_D => radio4_RSSI_ADC_D,
Radio4_TX_DAC_PLL_LOCK => radio4_TX_DAC_PLL_LOCK,
Radio4_TX_DAC_RESET => radio4_TX_DAC_RESET,
Radio4_SHDN_external => radio4_SHDN_external,
Radio4_TxEn_external => radio4_TxEn_external,
Radio4_RxEn_external => radio4_RxEn_external,
Radio4_RxHP_external => radio4_RxHP_external,
Radio4_TxGain => radio4_TxGain,
Radio4_TxStart => radio4_TxStart,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup
);
------------------------------------------
-- hooking up signal slicing
------------------------------------------
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end IMP;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fpext_32ns_64_1 is
generic (
ID : integer := 4;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
dout_WIDTH : integer := 64
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fpext_32ns_64_1 is
--------------------- Component ---------------------
component ANN_ap_fpext_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fpext_0_no_dsp_32_u : component ANN_ap_fpext_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
dout <= r_tdata;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Channel Mux
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : Unit Mux left and right channel
-------------------------------------------------------------------------------
architecture Rtl of ChannelMux is
---------------------------------------------------------------------------
-- Types and constants
---------------------------------------------------------------------------
subtype aMuxSel is std_logic_vector (3 downto 0);
signal MuxSel : aMuxSel;
constant cSilence : std_logic_vector(gDataWidth-1 downto 0) := (others => '0');
begin
-- combinatoric output logic
out_mux : process(MuxSel, asi_left_data, asi_left_valid, asi_right_data, asi_right_valid) is
variable L, R : std_logic_vector(gDataWidth-1 downto 0);
begin -- process out_mux
-- mute left channel
case MuxSel(3) is
when '0' => L := asi_left_data;
when '1' => L := cSilence;
when others => L := (others => 'X');
end case;
-- mute right channel
case MuxSel(2) is
when '0' => R := asi_right_data;
when '1' => R := cSilence;
when others => R := (others => 'X');
end case;
-- function cross or skip
case MuxSel(1) is
-- cross channels
when '0' =>
-- cross or straight
case MuxSel(0) is
when '0' => -- straight
aso_left_data <= L;
aso_left_valid <= asi_left_valid;
aso_right_data <= R;
aso_right_valid <= asi_right_valid;
when '1' => -- cross
aso_left_data <= R;
aso_left_valid <= asi_right_valid;
aso_right_data <= L;
aso_right_valid <= asi_left_valid;
when others =>
aso_left_data <= (others => 'X');
aso_left_valid <= 'X';
aso_right_data <= (others => 'X');
aso_right_valid <= 'X';
end case;
-- skip channel
when '1' =>
-- both L or R
case MuxSel(0) is
when '0' => -- both left
aso_left_data <= L;
aso_left_valid <= asi_left_valid;
aso_right_data <= L;
aso_right_valid <= asi_left_valid;
when '1' => -- both right
aso_left_data <= R;
aso_left_valid <= asi_right_valid;
aso_right_data <= R;
aso_right_valid <= asi_right_valid;
when others =>
aso_left_data <= (others => 'X');
aso_left_valid <= 'X';
aso_right_data <= (others => 'X');
aso_right_valid <= 'X';
end case;
when others =>
aso_left_data <= (others => 'X');
aso_left_valid <= 'X';
aso_right_data <= (others => 'X');
aso_right_valid <= 'X';
end case;
end process out_mux;
-- MM INTERFACE for configuration
SetConfigReg : process (csi_clk, rsi_reset_n) is
begin
if rsi_reset_n = not('1') then -- low active reset
MuxSel <= (others => '0');
elsif rising_edge(csi_clk) then -- rising
if avs_s0_write = '1' then
MuxSel <= avs_s0_writedata(MuxSel'range);
end if;
end if;
end process;
end architecture Rtl;
|
-------------------------------------------------------------------------------
-- Title : Vivado DDS cos lut for SIRIUS 250M
-- Project :
-------------------------------------------------------------------------------
-- File : dds_cos_lut.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-04-15
-- Last update: 2016-04-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Temporary cosine lut for SIRIUS machine with 250M ADC generated
-- through Vivado.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-04 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
entity dds_cos_lut is
port (
clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end entity dds_cos_lut;
architecture str of dds_cos_lut is
component generic_rom
generic (
g_data_width : natural := 32;
g_size : natural := 16384;
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end component;
begin
cmp_cos_lut_sirius_50_191_1 : generic_rom
generic map (
g_data_width => 16,
g_size => 191,
g_init_file => "cos_lut_sirius_50_191.mif",
g_fail_if_file_not_found => true
)
port map (
rst_n_i => '1',
clk_i => clka,
a_i => addra,
q_o => douta
);
end architecture str;
|
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of mem_ctrl is
type StateType is (
-- Initialisation states
S_INIT_WAIT,
S_INIT_PRE,
S_INIT_REF1,
S_INIT_REF1_WAIT,
S_INIT_REF2,
S_INIT_REF2_WAIT,
S_INIT_LMR,
S_INIT_LMR_WAIT,
-- Execute a write
S_WRITE1,
S_WRITE2,
S_WRITE3,
-- Execute a read
S_READ1,
S_READ2,
S_READ3,
-- Do a refresh operation
S_REFRESH,
-- Execute an interruptable refresh
S_IDLE
);
constant RAM_NOP : std_logic_vector(2 downto 0) := "111";
constant RAM_ACT : std_logic_vector(2 downto 0) := "011";
constant RAM_READ : std_logic_vector(2 downto 0) := "101";
constant RAM_WRITE : std_logic_vector(2 downto 0) := "100";
constant RAM_PRE : std_logic_vector(2 downto 0) := "010";
constant RAM_REF : std_logic_vector(2 downto 0) := "001";
constant RAM_LMR : std_logic_vector(2 downto 0) := "000";
-- Reserved
-- / Write Burst Mode (0=Burst, 1=Single)
-- / / Reserved
-- / / / Latency Mode (CL=2)
-- / / / / Burst Type (0=Sequential, 1=Interleaved)
-- / / / / / Burst Length (1,2,4,8,X,X,X,Full)
-- / / / / / /
-- / / / / / /
constant LMR_VALUE : std_logic_vector(11 downto 0) := "00" & "1" & "00" & "010" & "0" & "000";
signal state : StateType := S_INIT_WAIT;
signal state_next : StateType;
signal count : unsigned(12 downto 0) := INIT_COUNT;
signal count_next : unsigned(12 downto 0);
signal rowAddr : std_logic_vector(8 downto 0) := (others => '0');
signal rowAddr_next : std_logic_vector(8 downto 0);
signal bankAddr : std_logic_vector(1 downto 0) := (others => '0');
signal bankAddr_next : std_logic_vector(1 downto 0);
signal wrData : std_logic_vector(15 downto 0) := (others => '0');
signal wrData_next : std_logic_vector(15 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_INIT_WAIT;
count <= INIT_COUNT;
rowAddr <= (others => '0');
bankAddr <= (others => '0');
wrData <= (others => '0');
else
state <= state_next;
count <= count_next;
rowAddr <= rowAddr_next;
bankAddr <= bankAddr_next;
wrData <= wrData_next;
end if;
end if;
end process;
-- Next state logic
process(
state, count, mcAutoMode_in, mcCmd_in, mcAddr_in, mcData_in, rowAddr, bankAddr, wrData,
ramData_io)
begin
-- Internal signal defaults
state_next <= state;
rowAddr_next <= rowAddr;
bankAddr_next <= bankAddr;
wrData_next <= wrData;
if ( count = 0 ) then
count_next <= count;
else
count_next <= count - 1;
end if;
-- Client interface defaults
mcReady_out <= '0';
mcRDV_out <= '0';
mcData_out <= (others => 'X');
-- SDRAM interface defaults
ramCmd_out <= RAM_NOP;
ramBank_out <= (others => 'X');
ramAddr_out <= (others => 'X');
ramData_io <= (others => 'Z');
case state is
----------------------------------------------------------------------------------------
-- The init sequence: 4800 NOPs, PRE all, 2xREF, & LMR
----------------------------------------------------------------------------------------
-- Issue NOPs until the count hits the threshold
when S_INIT_WAIT =>
if ( count = 0 ) then
state_next <= S_INIT_PRE;
end if;
-- Issue a PRECHARGE command to all banks
when S_INIT_PRE =>
state_next <= S_INIT_REF1;
ramCmd_out <= RAM_PRE;
ramAddr_out(10) <= '1'; -- A10=1: Precharge all banks
-- Issue a refresh command. Must wait 63ns (four clocks, conservatively)
when S_INIT_REF1 =>
state_next <= S_INIT_REF1_WAIT;
ramCmd_out <= RAM_REF;
count_next <= REFRESH_LENGTH;
when S_INIT_REF1_WAIT => -- Three NOPs
if ( count = 0 ) then
state_next <= S_INIT_REF2;
end if;
-- Issue a refresh command. Must wait 63ns (four clocks, conservatively)
when S_INIT_REF2 =>
state_next <= S_INIT_REF2_WAIT;
ramCmd_out <= RAM_REF;
count_next <= REFRESH_LENGTH;
when S_INIT_REF2_WAIT => -- Three NOPs
if ( count = 0 ) then
state_next <= S_INIT_LMR;
end if;
-- Issue a Load Mode Register command. Must wait tMRD (two clocks).
when S_INIT_LMR =>
state_next <= S_INIT_LMR_WAIT;
ramCmd_out <= RAM_LMR;
ramAddr_out <= LMR_VALUE;
when S_INIT_LMR_WAIT =>
count_next <= REFRESH_DELAY;
state_next <= S_IDLE;
-------------------------------------------------------------------------------------------
-- Do a write
-------------------------------------------------------------------------------------------
when S_WRITE1 =>
state_next <= S_WRITE2;
ramCmd_out <= RAM_WRITE;
ramData_io <= wrData;
ramBank_out <= bankAddr;
ramAddr_out <= "000" & rowAddr;
when S_WRITE2 =>
state_next <= S_WRITE3;
when S_WRITE3 =>
ramCmd_out <= RAM_PRE;
ramAddr_out(10) <= '1'; -- A10=1: Precharge all banks
state_next <= S_IDLE;
-------------------------------------------------------------------------------------------
-- Do a read
-------------------------------------------------------------------------------------------
when S_READ1 =>
state_next <= S_READ2;
ramCmd_out <= RAM_READ;
ramBank_out <= bankAddr;
ramAddr_out <= "000" & rowAddr; -- no auto precharge
when S_READ2 =>
state_next <= S_READ3;
when S_READ3 =>
ramCmd_out <= RAM_PRE;
ramAddr_out(10) <= '1'; -- A10=1: Precharge all banks
mcData_out <= ramData_io;
mcRDV_out <= '1';
state_next <= S_IDLE;
-------------------------------------------------------------------------------------------
-- Refresh
-------------------------------------------------------------------------------------------
when S_REFRESH =>
if ( count = 0 ) then
state_next <= S_IDLE;
count_next <= REFRESH_DELAY;
end if;
-------------------------------------------------------------------------------------------
-- S_IDLE, etc
-------------------------------------------------------------------------------------------
when others =>
if ( count = 0 and mcAutoMode_in = '1' ) then
state_next <= S_REFRESH;
ramCmd_out <= RAM_REF;
count_next <= REFRESH_LENGTH;
else
mcReady_out <= '1';
case mcCmd_in is
when MC_REF =>
state_next <= S_REFRESH;
ramCmd_out <= RAM_REF;
count_next <= REFRESH_LENGTH;
when MC_RD =>
state_next <= S_READ1;
ramCmd_out <= RAM_ACT;
ramAddr_out <= mcAddr_in(21 downto 10);
ramBank_out <= mcAddr_in(9 downto 8);
rowAddr_next <= mcAddr_in(22) & mcAddr_in(7 downto 0);
bankAddr_next <= mcAddr_in(9 downto 8);
when MC_WR =>
state_next <= S_WRITE1;
ramCmd_out <= RAM_ACT;
ramAddr_out <= mcAddr_in(21 downto 10);
ramBank_out <= mcAddr_in(9 downto 8);
rowAddr_next <= mcAddr_in(22) & mcAddr_in(7 downto 0);
bankAddr_next <= mcAddr_in(9 downto 8);
wrData_next <= mcData_in;
when others =>
null;
end case;
end if;
end case;
end process;
-- Don't mask anything
ramLDQM_out <= '0';
ramUDQM_out <= '0';
end architecture;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal plb_error : std_logic;
signal opb_error : std_logic;
signal flash_a23 : std_ulogic;
signal sram_flash_addr : std_logic_vector(20 downto 0);
signal sram_flash_data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_flash_oe_n : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_ce : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal sram_zz : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (3 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (3 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (31 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(13 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal tft_lcd_clk : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 3);
signal vid_g : std_logic_vector(7 downto 3);
signal vid_b : std_logic_vector(7 downto 3);
signal usb_csn : std_logic;
signal flash_cex : std_logic;
signal iic_scl : std_logic;
signal iic_sda : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxsp : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txdp : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txsp : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal datazz : std_logic_vector(0 to 3);
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
rxd1 <= 'H';
sram_clk_fb <= sram_clk; ddr_clk_fb <= ddr_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl <= 'H'; iic_sda <= 'H';
flash_cex <= not flash_ce;
gpio <= (others => 'L');
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, plb_error, opb_error, sram_flash_addr,
sram_flash_data, sram_cen, sram_bw, sram_flash_oe_n, sram_flash_we_n,
flash_ce, sram_clk, sram_clk_fb, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, ps2_keyb_clk,
ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data, tft_lcd_clk,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b,
usb_csn,
iic_scl, iic_sda
);
datazz <= "HHHH";
u0 : cy7c1354 generic map (fname => sramfile, tWEH => 0.0 ns, tAH => 0.0 ns)
port map(
Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data,
Addr => sram_flash_addr(17 downto 0), Mode => sram_mode,
Clk => sram_clk, CEN_n => gnd, AdvLd_n => sram_adv_ld_n,
Bwa_n => sram_bw(3), Bwb_n => sram_bw(2),
Bwc_n => sram_bw(1), Bwd_n => sram_bw(0),
Rw_n => sram_flash_we_n, Oe_n => sram_flash_oe_n,
Ce1_n => sram_cen,
Ce2 => vcc,
Ce3_n => gnd,
Zz => sram_zz);
sram_zz <= '0';
-- u1 : mt46v16m16
-- generic map (index => 1, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
-- u2 : mt46v16m16
-- generic map (index => 0, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(3 downto 2));
ddr0 : ddrram
generic map(width => 32, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 2)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(31-i*8 downto 24-i*8),
flash_cex, sram_bw(i), sram_flash_oe_n);
end generate;
phy_mii_data <= 'H';
p0: phy
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv,
phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_gtx_clk);
i0: i2c_slave_model
port map (iic_scl, iic_sda);
plb_error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(plb_error) = '1' then wait on plb_error; end if;
assert (to_x01(plb_error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, plb_error, sram_flash_addr(19 downto 0), sram_flash_data,
iosn, sram_flash_oe_n, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
|
-------------------------------------------------------------------------------
-- Title : Top module that instantiates ascon
-- Project :
-------------------------------------------------------------------------------
-- File : top.vhdl
-- Author : Erich Wenger <[email protected]>
-- Company : Graz University of Technology
-- Created : 2014-03-24
-- Last update: 2014-03-24
-- Platform : ASIC design
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-24 1.0 erichwenger Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top is
generic (
DATA_BUS_WIDTH : integer := 32;
ADDR_BUS_WIDTH : integer := 8);
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
CSxSI : in std_logic;
WExSI : in std_logic;
AddressxDI : in std_logic_vector(ADDR_BUS_WIDTH-1 downto 0);
DataWritexDI : in std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
DataReadxDO : out std_logic_vector(DATA_BUS_WIDTH-1 downto 0));
end entity top;
architecture structural of top is
begin -- architecture structural
ascon_1: entity work.ascon
generic map (
DATA_BUS_WIDTH => DATA_BUS_WIDTH,
ADDR_BUS_WIDTH => ADDR_BUS_WIDTH)
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
CSxSI => CSxSI,
WExSI => WExSI,
AddressxDI => AddressxDI,
DataWritexDI => DataWritexDI,
DataReadxDO => DataReadxDO);
end architecture structural;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- Modified by Joris van Rantwijk to support Digilent Atlys board.
-- Modified by Aeroflex Gaisler
--
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
library hynix;
use hynix.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal rst : std_logic := '0'; -- Reset
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_cke : std_logic;
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
signal ddr_csb : std_ulogic := '0';
signal txd1, rxd1 : std_logic;
signal genio : std_logic_vector(7 downto 0) := (others => '0');
signal switch : std_logic_vector(7 downto 0) := (others => '0');
signal led : std_logic_vector(7 downto 0);
signal button : std_logic_vector(4 downto 0) := (others => '0');
-- Ethernet
signal erx_clk : std_ulogic;
signal erxd : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etx_clk : std_ulogic;
signal etxd : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal egtxclk : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
signal emdint : std_ulogic;
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
-- SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_logic;
signal spi_miso : std_logic;
signal errorn : std_logic;
begin
-- system clock
clk <= (not clk) after clkperiod * 0.5 ns;
-- reset
rst <= '0', '1' after 2500 ns;
rxd1 <= 'H';
ps2clk <= "HH"; ps2data <= "HH";
-- enable DSU
switch(7) <= '1';
switch(6) <= '0';
cpu : entity work.leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow )
port map (
resetn => rst,
clk => clk,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_odt => ddr_odt,
ddr_we => ddr_we,
ddr_ras => ddr_ras,
ddr_cas => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr_ad,
ddr_dq => ddr_dq,
ddr_rzq => ddr_rzq,
ddr_zio => ddr_zio,
txd1 => txd1,
rxd1 => rxd1,
pmoda => genio,
switch => switch,
led => led,
button => button,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etx_clk => etx_clk,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
erst => open,
egtxclk => egtxclk,
emdc => emdc,
emdio => emdio,
emdint => emdint,
kbd_clk => ps2clk(0),
kbd_data => ps2data(0),
mou_clk => ps2clk(1),
mou_data => ps2data(1),
spi_sel_n => spi_sel_n,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
tmdstx_clk_p => open,
tmdstx_clk_n => open,
tmdstx_dat_p => open,
tmdstx_dat_n => open );
prom0 : spi_flash
generic map (
ftype => 4,
debug => 0,
fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => 16#200000# )
port map (
sck => spi_clk,
di => spi_mosi,
do => spi_miso,
csn => spi_sel_n );
-- NOTE: LEON3 expects DDR2 memory chip with eight banks, but simulation
-- model has only four banks. Therefore 2nd block of 64 MByte will alias
-- to first block.
ddr2mem0 : for i in 0 to 0 generate
u1 : HY5PS121621F
generic map (TimingCheckFlag => false, PUSCheckFlag => false,
index => i, bbits => 16, fname => sdramfile, fdelay => 340)
port map (DQ => ddr_dq(i*16+15 downto i*16),
LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2),
UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1),
LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas,
RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba(1 downto 0),
ADDR => ddr_ad(12 downto 0), CKE => ddr_cke,
CLK => ddr_clk, CLKB => ddr_clkb, UDM => ddr_dm(i*2+1));
end generate;
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (base1000_t_fd => 0, base1000_t_hd => 0, address => 7)
port map (rst, emdio, etx_clk, erx_clk, erxd, erx_dv,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, egtxclk);
end generate;
-- Monitor error indication.
errorn <= not led(7);
iuerr: process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
-- Write serial port output to stdout.
--uart0: process
-- constant bit_interval : time := 1 sec / 38400.0;
-- variable d : std_logic_vector(7 downto 0);
-- variable c : character;
-- variable lin : line;
--begin
-- rxc(txd1, d, bit_interval);
-- c := character'val(conv_integer(d));
-- if c = LF then
-- std.textio.writeline(output, lin);
-- elsif c /= CR then
-- std.textio.write(lin, c);
-- end if;
--end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2427.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n03i02427ent IS
END c07s03b02x01p01n03i02427ent;
ARCHITECTURE c07s03b02x01p01n03i02427arch OF c07s03b02x01p01n03i02427ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : integer;
ele_2 : real;
ele_3 : boolean;
end record;
constant p :rec := (ele_1 | ele_2 | ele_3 => 4.5); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x01p01n03i02427 - Element association with others choice should be used to represent elements of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n03i02427arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2427.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n03i02427ent IS
END c07s03b02x01p01n03i02427ent;
ARCHITECTURE c07s03b02x01p01n03i02427arch OF c07s03b02x01p01n03i02427ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : integer;
ele_2 : real;
ele_3 : boolean;
end record;
constant p :rec := (ele_1 | ele_2 | ele_3 => 4.5); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x01p01n03i02427 - Element association with others choice should be used to represent elements of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n03i02427arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2427.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n03i02427ent IS
END c07s03b02x01p01n03i02427ent;
ARCHITECTURE c07s03b02x01p01n03i02427arch OF c07s03b02x01p01n03i02427ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : integer;
ele_2 : real;
ele_3 : boolean;
end record;
constant p :rec := (ele_1 | ele_2 | ele_3 => 4.5); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x01p01n03i02427 - Element association with others choice should be used to represent elements of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n03i02427arch;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:59:49 11/19/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282_19.11.2013/My_16bit4x1Mux_tb_948282.vhd
-- Project Name: Mips32_948282_19.11.2013
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: My_16bit4x1Mux_948282
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY My_16bit4x1Mux_tb_948282 IS
END My_16bit4x1Mux_tb_948282;
ARCHITECTURE behavior OF My_16bit4x1Mux_tb_948282 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT My_16bit4x1Mux_948282
PORT(
S_1 : IN std_logic;
S_2 : IN std_logic;
A_mux : IN std_logic_vector(15 downto 0);
B_mux : IN std_logic_vector(15 downto 0);
C_mux : IN std_logic_vector(15 downto 0);
D_mux : IN std_logic_vector(15 downto 0);
Result : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal S_1 : std_logic := '0';
signal S_2 : std_logic := '0';
signal A_mux : std_logic_vector(15 downto 0) := (others => '0');
signal B_mux : std_logic_vector(15 downto 0) := (others => '0');
signal C_mux : std_logic_vector(15 downto 0) := (others => '0');
signal D_mux : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal Result : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: My_16bit4x1Mux_948282 PORT MAP (
S_1 => S_1,
S_2 => S_2,
A_mux => A_mux,
B_mux => B_mux,
C_mux => C_mux,
D_mux => D_mux,
Result => Result
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
S_1<='1';
S_2<='0';
A_mux<="0001110011111101";
B_mux<="0111000000000000";
C_mux<="1111111111111111";
D_mux<="0000000011111111";
wait;
end process;
END;
|
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test2 is
port(
A,B,C : in bit_vector(7 downto 0);
D0 : out bit_vector(7 downto 0);
D1 : out bit_vector(7 downto 0);
D2 : out bit_vector(7 downto 0);
D3 : out bit_vector(7 downto 0);
D4 : out bit_vector(7 downto 0);
D5 : out bit_vector(7 downto 0);
D6 : out bit_vector(7 downto 0);
D7 : out bit_vector(7 downto 0)
);
end test2;
architecture rtl of test2 is
type T_IN_DSP_PC_ARR is array(0 to 7,0 to 7) of bit;
signal s_pout : T_IN_DSP_PC_ARR;
begin
D0 <= s_pout(0,7)&s_pout(0,6)&s_pout(0,5)&s_pout(0,4)&s_pout(0,3)&s_pout(0,2)&s_pout(0,1)&s_pout(0,0);
D1 <= s_pout(1,7)&s_pout(1,6)&s_pout(1,5)&s_pout(1,4)&s_pout(1,3)&s_pout(1,2)&s_pout(1,1)&s_pout(1,0);
D2 <= s_pout(2,7)&s_pout(2,6)&s_pout(2,5)&s_pout(2,4)&s_pout(2,3)&s_pout(2,2)&s_pout(2,1)&s_pout(2,0);
D3 <= s_pout(3,7)&s_pout(3,6)&s_pout(3,5)&s_pout(3,4)&s_pout(3,3)&s_pout(3,2)&s_pout(3,1)&s_pout(3,0);
D4 <= s_pout(4,7)&s_pout(4,6)&s_pout(4,5)&s_pout(4,4)&s_pout(4,3)&s_pout(4,2)&s_pout(4,1)&s_pout(4,0);
D5 <= s_pout(5,7)&s_pout(5,6)&s_pout(5,5)&s_pout(5,4)&s_pout(5,3)&s_pout(5,2)&s_pout(5,1)&s_pout(5,0);
D6 <= s_pout(6,7)&s_pout(6,6)&s_pout(6,5)&s_pout(6,4)&s_pout(6,3)&s_pout(6,2)&s_pout(6,1)&s_pout(6,0);
D7 <= s_pout(7,7)&s_pout(7,6)&s_pout(7,5)&s_pout(7,4)&s_pout(7,3)&s_pout(7,2)&s_pout(7,1)&s_pout(7,0);
VGEN: for V in 0 to 7 generate
UGEN: for I in 0 to 7 generate
signal C_C :bit;
begin
C_C <= '0' when I=0 else C(I-1);
UX: entity work.t1
port map(A(I),B(I),C_C,s_pout(V,I));
end generate UGEN;
end generate VGEN;
end rtl;
entity issue112 is
end entity;
architecture test of issue112 is
signal A, B, C : bit_vector(7 downto 0);
signal D0 : bit_vector(7 downto 0);
signal D1 : bit_vector(7 downto 0);
signal D2 : bit_vector(7 downto 0);
signal D3 : bit_vector(7 downto 0);
signal D4 : bit_vector(7 downto 0);
signal D5 : bit_vector(7 downto 0);
signal D6 : bit_vector(7 downto 0);
signal D7 : bit_vector(7 downto 0);
begin
test2_1: entity work.test2
port map (
A => A,
B => B,
C => C,
D0 => D0,
D1 => D1,
D2 => D2,
D3 => D3,
D4 => D4,
D5 => D5,
D6 => D6,
D7 => D7);
process is
begin
wait for 1 ns;
assert D0 = X"00";
A <= X"0f";
B <= X"03";
C <= X"01";
wait for 1 ns;
assert D0 = X"02";
wait;
end process;
end architecture;
|
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test2 is
port(
A,B,C : in bit_vector(7 downto 0);
D0 : out bit_vector(7 downto 0);
D1 : out bit_vector(7 downto 0);
D2 : out bit_vector(7 downto 0);
D3 : out bit_vector(7 downto 0);
D4 : out bit_vector(7 downto 0);
D5 : out bit_vector(7 downto 0);
D6 : out bit_vector(7 downto 0);
D7 : out bit_vector(7 downto 0)
);
end test2;
architecture rtl of test2 is
type T_IN_DSP_PC_ARR is array(0 to 7,0 to 7) of bit;
signal s_pout : T_IN_DSP_PC_ARR;
begin
D0 <= s_pout(0,7)&s_pout(0,6)&s_pout(0,5)&s_pout(0,4)&s_pout(0,3)&s_pout(0,2)&s_pout(0,1)&s_pout(0,0);
D1 <= s_pout(1,7)&s_pout(1,6)&s_pout(1,5)&s_pout(1,4)&s_pout(1,3)&s_pout(1,2)&s_pout(1,1)&s_pout(1,0);
D2 <= s_pout(2,7)&s_pout(2,6)&s_pout(2,5)&s_pout(2,4)&s_pout(2,3)&s_pout(2,2)&s_pout(2,1)&s_pout(2,0);
D3 <= s_pout(3,7)&s_pout(3,6)&s_pout(3,5)&s_pout(3,4)&s_pout(3,3)&s_pout(3,2)&s_pout(3,1)&s_pout(3,0);
D4 <= s_pout(4,7)&s_pout(4,6)&s_pout(4,5)&s_pout(4,4)&s_pout(4,3)&s_pout(4,2)&s_pout(4,1)&s_pout(4,0);
D5 <= s_pout(5,7)&s_pout(5,6)&s_pout(5,5)&s_pout(5,4)&s_pout(5,3)&s_pout(5,2)&s_pout(5,1)&s_pout(5,0);
D6 <= s_pout(6,7)&s_pout(6,6)&s_pout(6,5)&s_pout(6,4)&s_pout(6,3)&s_pout(6,2)&s_pout(6,1)&s_pout(6,0);
D7 <= s_pout(7,7)&s_pout(7,6)&s_pout(7,5)&s_pout(7,4)&s_pout(7,3)&s_pout(7,2)&s_pout(7,1)&s_pout(7,0);
VGEN: for V in 0 to 7 generate
UGEN: for I in 0 to 7 generate
signal C_C :bit;
begin
C_C <= '0' when I=0 else C(I-1);
UX: entity work.t1
port map(A(I),B(I),C_C,s_pout(V,I));
end generate UGEN;
end generate VGEN;
end rtl;
entity issue112 is
end entity;
architecture test of issue112 is
signal A, B, C : bit_vector(7 downto 0);
signal D0 : bit_vector(7 downto 0);
signal D1 : bit_vector(7 downto 0);
signal D2 : bit_vector(7 downto 0);
signal D3 : bit_vector(7 downto 0);
signal D4 : bit_vector(7 downto 0);
signal D5 : bit_vector(7 downto 0);
signal D6 : bit_vector(7 downto 0);
signal D7 : bit_vector(7 downto 0);
begin
test2_1: entity work.test2
port map (
A => A,
B => B,
C => C,
D0 => D0,
D1 => D1,
D2 => D2,
D3 => D3,
D4 => D4,
D5 => D5,
D6 => D6,
D7 => D7);
process is
begin
wait for 1 ns;
assert D0 = X"00";
A <= X"0f";
B <= X"03";
C <= X"01";
wait for 1 ns;
assert D0 = X"02";
wait;
end process;
end architecture;
|
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test2 is
port(
A,B,C : in bit_vector(7 downto 0);
D0 : out bit_vector(7 downto 0);
D1 : out bit_vector(7 downto 0);
D2 : out bit_vector(7 downto 0);
D3 : out bit_vector(7 downto 0);
D4 : out bit_vector(7 downto 0);
D5 : out bit_vector(7 downto 0);
D6 : out bit_vector(7 downto 0);
D7 : out bit_vector(7 downto 0)
);
end test2;
architecture rtl of test2 is
type T_IN_DSP_PC_ARR is array(0 to 7,0 to 7) of bit;
signal s_pout : T_IN_DSP_PC_ARR;
begin
D0 <= s_pout(0,7)&s_pout(0,6)&s_pout(0,5)&s_pout(0,4)&s_pout(0,3)&s_pout(0,2)&s_pout(0,1)&s_pout(0,0);
D1 <= s_pout(1,7)&s_pout(1,6)&s_pout(1,5)&s_pout(1,4)&s_pout(1,3)&s_pout(1,2)&s_pout(1,1)&s_pout(1,0);
D2 <= s_pout(2,7)&s_pout(2,6)&s_pout(2,5)&s_pout(2,4)&s_pout(2,3)&s_pout(2,2)&s_pout(2,1)&s_pout(2,0);
D3 <= s_pout(3,7)&s_pout(3,6)&s_pout(3,5)&s_pout(3,4)&s_pout(3,3)&s_pout(3,2)&s_pout(3,1)&s_pout(3,0);
D4 <= s_pout(4,7)&s_pout(4,6)&s_pout(4,5)&s_pout(4,4)&s_pout(4,3)&s_pout(4,2)&s_pout(4,1)&s_pout(4,0);
D5 <= s_pout(5,7)&s_pout(5,6)&s_pout(5,5)&s_pout(5,4)&s_pout(5,3)&s_pout(5,2)&s_pout(5,1)&s_pout(5,0);
D6 <= s_pout(6,7)&s_pout(6,6)&s_pout(6,5)&s_pout(6,4)&s_pout(6,3)&s_pout(6,2)&s_pout(6,1)&s_pout(6,0);
D7 <= s_pout(7,7)&s_pout(7,6)&s_pout(7,5)&s_pout(7,4)&s_pout(7,3)&s_pout(7,2)&s_pout(7,1)&s_pout(7,0);
VGEN: for V in 0 to 7 generate
UGEN: for I in 0 to 7 generate
signal C_C :bit;
begin
C_C <= '0' when I=0 else C(I-1);
UX: entity work.t1
port map(A(I),B(I),C_C,s_pout(V,I));
end generate UGEN;
end generate VGEN;
end rtl;
entity issue112 is
end entity;
architecture test of issue112 is
signal A, B, C : bit_vector(7 downto 0);
signal D0 : bit_vector(7 downto 0);
signal D1 : bit_vector(7 downto 0);
signal D2 : bit_vector(7 downto 0);
signal D3 : bit_vector(7 downto 0);
signal D4 : bit_vector(7 downto 0);
signal D5 : bit_vector(7 downto 0);
signal D6 : bit_vector(7 downto 0);
signal D7 : bit_vector(7 downto 0);
begin
test2_1: entity work.test2
port map (
A => A,
B => B,
C => C,
D0 => D0,
D1 => D1,
D2 => D2,
D3 => D3,
D4 => D4,
D5 => D5,
D6 => D6,
D7 => D7);
process is
begin
wait for 1 ns;
assert D0 = X"00";
A <= X"0f";
B <= X"03";
C <= X"01";
wait for 1 ns;
assert D0 = X"02";
wait;
end process;
end architecture;
|
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test2 is
port(
A,B,C : in bit_vector(7 downto 0);
D0 : out bit_vector(7 downto 0);
D1 : out bit_vector(7 downto 0);
D2 : out bit_vector(7 downto 0);
D3 : out bit_vector(7 downto 0);
D4 : out bit_vector(7 downto 0);
D5 : out bit_vector(7 downto 0);
D6 : out bit_vector(7 downto 0);
D7 : out bit_vector(7 downto 0)
);
end test2;
architecture rtl of test2 is
type T_IN_DSP_PC_ARR is array(0 to 7,0 to 7) of bit;
signal s_pout : T_IN_DSP_PC_ARR;
begin
D0 <= s_pout(0,7)&s_pout(0,6)&s_pout(0,5)&s_pout(0,4)&s_pout(0,3)&s_pout(0,2)&s_pout(0,1)&s_pout(0,0);
D1 <= s_pout(1,7)&s_pout(1,6)&s_pout(1,5)&s_pout(1,4)&s_pout(1,3)&s_pout(1,2)&s_pout(1,1)&s_pout(1,0);
D2 <= s_pout(2,7)&s_pout(2,6)&s_pout(2,5)&s_pout(2,4)&s_pout(2,3)&s_pout(2,2)&s_pout(2,1)&s_pout(2,0);
D3 <= s_pout(3,7)&s_pout(3,6)&s_pout(3,5)&s_pout(3,4)&s_pout(3,3)&s_pout(3,2)&s_pout(3,1)&s_pout(3,0);
D4 <= s_pout(4,7)&s_pout(4,6)&s_pout(4,5)&s_pout(4,4)&s_pout(4,3)&s_pout(4,2)&s_pout(4,1)&s_pout(4,0);
D5 <= s_pout(5,7)&s_pout(5,6)&s_pout(5,5)&s_pout(5,4)&s_pout(5,3)&s_pout(5,2)&s_pout(5,1)&s_pout(5,0);
D6 <= s_pout(6,7)&s_pout(6,6)&s_pout(6,5)&s_pout(6,4)&s_pout(6,3)&s_pout(6,2)&s_pout(6,1)&s_pout(6,0);
D7 <= s_pout(7,7)&s_pout(7,6)&s_pout(7,5)&s_pout(7,4)&s_pout(7,3)&s_pout(7,2)&s_pout(7,1)&s_pout(7,0);
VGEN: for V in 0 to 7 generate
UGEN: for I in 0 to 7 generate
signal C_C :bit;
begin
C_C <= '0' when I=0 else C(I-1);
UX: entity work.t1
port map(A(I),B(I),C_C,s_pout(V,I));
end generate UGEN;
end generate VGEN;
end rtl;
entity issue112 is
end entity;
architecture test of issue112 is
signal A, B, C : bit_vector(7 downto 0);
signal D0 : bit_vector(7 downto 0);
signal D1 : bit_vector(7 downto 0);
signal D2 : bit_vector(7 downto 0);
signal D3 : bit_vector(7 downto 0);
signal D4 : bit_vector(7 downto 0);
signal D5 : bit_vector(7 downto 0);
signal D6 : bit_vector(7 downto 0);
signal D7 : bit_vector(7 downto 0);
begin
test2_1: entity work.test2
port map (
A => A,
B => B,
C => C,
D0 => D0,
D1 => D1,
D2 => D2,
D3 => D3,
D4 => D4,
D5 => D5,
D6 => D6,
D7 => D7);
process is
begin
wait for 1 ns;
assert D0 = X"00";
A <= X"0f";
B <= X"03";
C <= X"01";
wait for 1 ns;
assert D0 = X"02";
wait;
end process;
end architecture;
|
entity bounds2 is
end entity;
architecture test of bounds2 is
type int_vec is array (natural range <>) of integer;
begin
process is
variable v : int_vec(1 to 10) := (others => 0);
variable k : integer := 51761;
begin
v(k) := 2;
wait;
end process;
end architecture;
|
entity bounds2 is
end entity;
architecture test of bounds2 is
type int_vec is array (natural range <>) of integer;
begin
process is
variable v : int_vec(1 to 10) := (others => 0);
variable k : integer := 51761;
begin
v(k) := 2;
wait;
end process;
end architecture;
|
entity bounds2 is
end entity;
architecture test of bounds2 is
type int_vec is array (natural range <>) of integer;
begin
process is
variable v : int_vec(1 to 10) := (others => 0);
variable k : integer := 51761;
begin
v(k) := 2;
wait;
end process;
end architecture;
|
entity bounds2 is
end entity;
architecture test of bounds2 is
type int_vec is array (natural range <>) of integer;
begin
process is
variable v : int_vec(1 to 10) := (others => 0);
variable k : integer := 51761;
begin
v(k) := 2;
wait;
end process;
end architecture;
|
entity bounds2 is
end entity;
architecture test of bounds2 is
type int_vec is array (natural range <>) of integer;
begin
process is
variable v : int_vec(1 to 10) := (others => 0);
variable k : integer := 51761;
begin
v(k) := 2;
wait;
end process;
end architecture;
|
entity tb is
end tb;
|
entity tb is
end tb;
|
entity tb is
end tb;
|
entity tb is
end tb;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll1.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll1 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC
);
END altpll1;
ARCHITECTURE SYN OF altpll1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c0 <= sub_wire2;
c2 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
clk2_divide_by => 1,
clk2_duty_cycle => 50,
clk2_multiply_by => 1,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=altpll1",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Detect edges on input signal.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity edge_detector is
generic (
-- Initial value of observed signal
init_value_g : std_ulogic := '0';
-- Edge type: 0 = Rising, 1 = Falling, 2 = Both
edge_type_g : natural range 0 to 2 := 0;
-- Hold flag until it is acknowledged
hold_flag_g : boolean := false);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Enable
en_i : in std_ulogic;
-- Acknowledge detected edges
ack_i : in std_ulogic;
-- Monitored signal
sig_i : in std_ulogic;
-- Detection flag
edge_o : out std_ulogic);
end entity edge_detector;
architecture rtl of edge_detector is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal sig : std_ulogic := init_value_g;
signal edge : std_ulogic := '0';
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal detected : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
edge_o <= edge;
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
-- Detect rising edge
rising_gen : if edge_type_g = 0 generate
detected <= (sig_i and not sig) and en_i;
end generate rising_gen;
-- Detect falling edge
falling_gen : if edge_type_g = 1 generate
detected <= (not sig_i and sig) and en_i;
end generate falling_gen;
-- Detect both edges
both_gen : if edge_type_g = 2 generate
detected <= (sig_i xor sig) and en_i;
end generate both_gen;
-- Directly report a detected edge
direct_gen : if hold_flag_g = false generate
edge <= detected;
end generate direct_gen;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
sig <= init_value_g;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
-- Save last state of observed signal
sig <= sig_i;
end if;
end if;
end process regs;
-- Hold flag which reports a detected edge
hold_gen : if hold_flag_g = true generate
hold : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
edge <= '0';
end procedure reset;
begin -- process hold
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
if ack_i = '1' then
-- The acknowledge input resets the flag
edge <= '0';
elsif detected = '1' then
-- Set flag when an edge is detected
edge <= '1';
end if;
end if;
end if;
end process hold;
end generate hold_gen;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_ac_xhuff_tbl_huffval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_ac_xhuff_tbl_huffval;
architecture augh of p_jinfo_ac_xhuff_tbl_huffval is
-- Embedded RAM
type ram_type is array (0 to 1023) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_ac_xhuff_tbl_huffval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_ac_xhuff_tbl_huffval;
architecture augh of p_jinfo_ac_xhuff_tbl_huffval is
-- Embedded RAM
type ram_type is array (0 to 1023) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 03:32:36 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_gcd_0_1_sim_netlist.vhdl
-- Design : gcd_block_design_gcd_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi is
port (
\out\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_gcd_bus_RVALID : out STD_LOGIC_VECTOR ( 1 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
interrupt : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\b_read_reg_102_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
\a_read_reg_107_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
ap_clk : in STD_LOGIC;
s_axi_gcd_bus_ARVALID : in STD_LOGIC;
s_axi_gcd_bus_RREADY : in STD_LOGIC;
s_axi_gcd_bus_AWVALID : in STD_LOGIC;
s_axi_gcd_bus_WVALID : in STD_LOGIC;
s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_gcd_bus_BREADY : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\result_reg_56_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
\p_s_reg_45_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
ap_rst_n : in STD_LOGIC;
s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi is
signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \FSM_onehot_rstate[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_rstate[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_rstate_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_rstate_reg_n_0_[0]\ : signal is "yes";
signal \FSM_onehot_wstate[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_wstate_reg_n_0_[0]\ : signal is "yes";
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^a_read_reg_107_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ar_hs : STD_LOGIC;
signal \^b_read_reg_102_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal int_a0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \int_a[15]_i_1_n_0\ : STD_LOGIC;
signal \int_a[15]_i_3_n_0\ : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_done1 : STD_LOGIC;
signal int_ap_done_i_1_n_0 : STD_LOGIC;
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_start3_out : STD_LOGIC;
signal int_ap_start_i_10_n_0 : STD_LOGIC;
signal int_ap_start_i_1_n_0 : STD_LOGIC;
signal int_ap_start_i_5_n_0 : STD_LOGIC;
signal int_ap_start_i_6_n_0 : STD_LOGIC;
signal int_ap_start_i_7_n_0 : STD_LOGIC;
signal int_ap_start_i_8_n_0 : STD_LOGIC;
signal int_ap_start_i_9_n_0 : STD_LOGIC;
signal int_ap_start_reg_i_2_n_3 : STD_LOGIC;
signal int_ap_start_reg_i_4_n_0 : STD_LOGIC;
signal int_ap_start_reg_i_4_n_1 : STD_LOGIC;
signal int_ap_start_reg_i_4_n_2 : STD_LOGIC;
signal int_ap_start_reg_i_4_n_3 : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_auto_restart_i_1_n_0 : STD_LOGIC;
signal int_b0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \int_b[15]_i_1_n_0\ : STD_LOGIC;
signal int_gie_i_1_n_0 : STD_LOGIC;
signal int_gie_reg_n_0 : STD_LOGIC;
signal \int_ier[0]_i_1_n_0\ : STD_LOGIC;
signal \int_ier[1]_i_1_n_0\ : STD_LOGIC;
signal \int_ier[1]_i_2_n_0\ : STD_LOGIC;
signal \int_ier_reg_n_0_[0]\ : STD_LOGIC;
signal \int_ier_reg_n_0_[1]\ : STD_LOGIC;
signal int_isr6_out : STD_LOGIC;
signal \int_isr[0]_i_1_n_0\ : STD_LOGIC;
signal \int_isr[1]_i_1_n_0\ : STD_LOGIC;
signal \int_isr_reg_n_0_[0]\ : STD_LOGIC;
signal int_pResult : STD_LOGIC_VECTOR ( 15 downto 0 );
signal int_pResult_ap_vld : STD_LOGIC;
signal int_pResult_ap_vld1 : STD_LOGIC;
signal int_pResult_ap_vld_i_1_n_0 : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP of \^out\ : signal is "yes";
signal p_1_in : STD_LOGIC;
signal \rdata[0]_i_1_n_0\ : STD_LOGIC;
signal \rdata[0]_i_2_n_0\ : STD_LOGIC;
signal \rdata[0]_i_3_n_0\ : STD_LOGIC;
signal \rdata[0]_i_4_n_0\ : STD_LOGIC;
signal \rdata[10]_i_1_n_0\ : STD_LOGIC;
signal \rdata[11]_i_1_n_0\ : STD_LOGIC;
signal \rdata[12]_i_1_n_0\ : STD_LOGIC;
signal \rdata[13]_i_1_n_0\ : STD_LOGIC;
signal \rdata[14]_i_1_n_0\ : STD_LOGIC;
signal \rdata[15]_i_1_n_0\ : STD_LOGIC;
signal \rdata[15]_i_3_n_0\ : STD_LOGIC;
signal \rdata[1]_i_1_n_0\ : STD_LOGIC;
signal \rdata[1]_i_2_n_0\ : STD_LOGIC;
signal \rdata[1]_i_3_n_0\ : STD_LOGIC;
signal \rdata[1]_i_4_n_0\ : STD_LOGIC;
signal \rdata[1]_i_5_n_0\ : STD_LOGIC;
signal \rdata[2]_i_1_n_0\ : STD_LOGIC;
signal \rdata[2]_i_2_n_0\ : STD_LOGIC;
signal \rdata[3]_i_1_n_0\ : STD_LOGIC;
signal \rdata[3]_i_2_n_0\ : STD_LOGIC;
signal \rdata[4]_i_1_n_0\ : STD_LOGIC;
signal \rdata[5]_i_1_n_0\ : STD_LOGIC;
signal \rdata[6]_i_1_n_0\ : STD_LOGIC;
signal \rdata[7]_i_1_n_0\ : STD_LOGIC;
signal \rdata[7]_i_2_n_0\ : STD_LOGIC;
signal \rdata[8]_i_1_n_0\ : STD_LOGIC;
signal \rdata[9]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_gcd_bus_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^s_axi_gcd_bus_rvalid\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \^s_axi_gcd_bus_rvalid\ : signal is "yes";
signal waddr : STD_LOGIC;
signal \waddr_reg_n_0_[0]\ : STD_LOGIC;
signal \waddr_reg_n_0_[1]\ : STD_LOGIC;
signal \waddr_reg_n_0_[2]\ : STD_LOGIC;
signal \waddr_reg_n_0_[3]\ : STD_LOGIC;
signal \waddr_reg_n_0_[4]\ : STD_LOGIC;
signal \waddr_reg_n_0_[5]\ : STD_LOGIC;
signal NLW_int_ap_start_reg_i_2_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_int_ap_start_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_int_ap_start_reg_i_4_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[0]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_rstate_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[1]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP of \FSM_onehot_rstate_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[2]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP of \FSM_onehot_rstate_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[0]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[1]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[2]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[3]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[3]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ap_CS_fsm[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \int_a[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \int_a[10]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \int_a[11]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \int_a[12]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_a[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_a[14]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_a[15]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_a[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \int_a[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \int_a[3]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_a[4]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_a[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \int_a[6]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \int_a[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \int_a[8]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \int_a[9]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of int_ap_idle_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of int_ap_start_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \int_b[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \int_b[10]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_b[11]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_b[12]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_b[13]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_b[14]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_b[15]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_b[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \int_b[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_b[3]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_b[4]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \int_b[5]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \int_b[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \int_b[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \int_b[8]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \int_b[9]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \int_isr[0]_i_2\ : label is "soft_lutpair0";
begin
CO(0) <= \^co\(0);
SR(0) <= \^sr\(0);
\a_read_reg_107_reg[15]\(15 downto 0) <= \^a_read_reg_107_reg[15]\(15 downto 0);
\b_read_reg_102_reg[15]\(15 downto 0) <= \^b_read_reg_102_reg[15]\(15 downto 0);
\out\(2 downto 0) <= \^out\(2 downto 0);
s_axi_gcd_bus_RDATA(15 downto 0) <= \^s_axi_gcd_bus_rdata\(15 downto 0);
s_axi_gcd_bus_RVALID(1 downto 0) <= \^s_axi_gcd_bus_rvalid\(1 downto 0);
\FSM_onehot_rstate[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F747"
)
port map (
I0 => s_axi_gcd_bus_ARVALID,
I1 => \^s_axi_gcd_bus_rvalid\(0),
I2 => \^s_axi_gcd_bus_rvalid\(1),
I3 => s_axi_gcd_bus_RREADY,
O => \FSM_onehot_rstate[1]_i_1_n_0\
);
\FSM_onehot_rstate[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88F8"
)
port map (
I0 => s_axi_gcd_bus_ARVALID,
I1 => \^s_axi_gcd_bus_rvalid\(0),
I2 => \^s_axi_gcd_bus_rvalid\(1),
I3 => s_axi_gcd_bus_RREADY,
O => \FSM_onehot_rstate[2]_i_1_n_0\
);
\FSM_onehot_rstate_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => '0',
Q => \FSM_onehot_rstate_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_rstate_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_rstate[1]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rvalid\(0),
R => \^sr\(0)
);
\FSM_onehot_rstate_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_rstate[2]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rvalid\(1),
R => \^sr\(0)
);
\FSM_onehot_wstate[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888BFF8B"
)
port map (
I0 => s_axi_gcd_bus_BREADY,
I1 => \^out\(2),
I2 => \^out\(1),
I3 => \^out\(0),
I4 => s_axi_gcd_bus_AWVALID,
O => \FSM_onehot_wstate[1]_i_1_n_0\
);
\FSM_onehot_wstate[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_gcd_bus_AWVALID,
I1 => \^out\(0),
I2 => s_axi_gcd_bus_WVALID,
I3 => \^out\(1),
O => \FSM_onehot_wstate[2]_i_1_n_0\
);
\FSM_onehot_wstate[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ap_rst_n,
O => \^sr\(0)
);
\FSM_onehot_wstate[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_gcd_bus_WVALID,
I1 => \^out\(1),
I2 => s_axi_gcd_bus_BREADY,
I3 => \^out\(2),
O => \FSM_onehot_wstate[3]_i_2_n_0\
);
\FSM_onehot_wstate_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => '0',
Q => \FSM_onehot_wstate_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_wstate_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[1]_i_1_n_0\,
Q => \^out\(0),
R => \^sr\(0)
);
\FSM_onehot_wstate_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[2]_i_1_n_0\,
Q => \^out\(1),
R => \^sr\(0)
);
\FSM_onehot_wstate_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[3]_i_2_n_0\,
Q => \^out\(2),
R => \^sr\(0)
);
\ap_CS_fsm[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FA30"
)
port map (
I0 => \^co\(0),
I1 => ap_start,
I2 => Q(0),
I3 => Q(2),
O => D(0)
);
\ap_CS_fsm[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00001000"
)
port map (
I0 => Q(1),
I1 => Q(3),
I2 => Q(0),
I3 => ap_start,
I4 => Q(2),
O => D(1)
);
\b_read_reg_102[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Q(0),
I1 => ap_start,
O => E(0)
);
\int_a[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(0),
O => int_a0(0)
);
\int_a[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(10),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(10),
O => int_a0(10)
);
\int_a[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(11),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(11),
O => int_a0(11)
);
\int_a[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(12),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(12),
O => int_a0(12)
);
\int_a[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(13),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(13),
O => int_a0(13)
);
\int_a[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(14),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(14),
O => int_a0(14)
);
\int_a[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => \waddr_reg_n_0_[4]\,
I1 => \int_a[15]_i_3_n_0\,
I2 => \waddr_reg_n_0_[2]\,
I3 => \waddr_reg_n_0_[3]\,
O => \int_a[15]_i_1_n_0\
);
\int_a[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(15),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(15),
O => int_a0(15)
);
\int_a[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00001000"
)
port map (
I0 => \waddr_reg_n_0_[0]\,
I1 => \waddr_reg_n_0_[5]\,
I2 => \^out\(1),
I3 => s_axi_gcd_bus_WVALID,
I4 => \waddr_reg_n_0_[1]\,
O => \int_a[15]_i_3_n_0\
);
\int_a[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(1),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(1),
O => int_a0(1)
);
\int_a[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(2),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(2),
O => int_a0(2)
);
\int_a[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(3),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(3),
O => int_a0(3)
);
\int_a[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(4),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(4),
O => int_a0(4)
);
\int_a[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(5),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(5),
O => int_a0(5)
);
\int_a[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(6),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(6),
O => int_a0(6)
);
\int_a[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(7),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^a_read_reg_107_reg[15]\(7),
O => int_a0(7)
);
\int_a[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(8),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(8),
O => int_a0(8)
);
\int_a[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(9),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^a_read_reg_107_reg[15]\(9),
O => int_a0(9)
);
\int_a_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(0),
Q => \^a_read_reg_107_reg[15]\(0),
R => \^sr\(0)
);
\int_a_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(10),
Q => \^a_read_reg_107_reg[15]\(10),
R => \^sr\(0)
);
\int_a_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(11),
Q => \^a_read_reg_107_reg[15]\(11),
R => \^sr\(0)
);
\int_a_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(12),
Q => \^a_read_reg_107_reg[15]\(12),
R => \^sr\(0)
);
\int_a_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(13),
Q => \^a_read_reg_107_reg[15]\(13),
R => \^sr\(0)
);
\int_a_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(14),
Q => \^a_read_reg_107_reg[15]\(14),
R => \^sr\(0)
);
\int_a_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(15),
Q => \^a_read_reg_107_reg[15]\(15),
R => \^sr\(0)
);
\int_a_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(1),
Q => \^a_read_reg_107_reg[15]\(1),
R => \^sr\(0)
);
\int_a_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(2),
Q => \^a_read_reg_107_reg[15]\(2),
R => \^sr\(0)
);
\int_a_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(3),
Q => \^a_read_reg_107_reg[15]\(3),
R => \^sr\(0)
);
\int_a_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(4),
Q => \^a_read_reg_107_reg[15]\(4),
R => \^sr\(0)
);
\int_a_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(5),
Q => \^a_read_reg_107_reg[15]\(5),
R => \^sr\(0)
);
\int_a_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(6),
Q => \^a_read_reg_107_reg[15]\(6),
R => \^sr\(0)
);
\int_a_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(7),
Q => \^a_read_reg_107_reg[15]\(7),
R => \^sr\(0)
);
\int_a_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(8),
Q => \^a_read_reg_107_reg[15]\(8),
R => \^sr\(0)
);
\int_a_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_a[15]_i_1_n_0\,
D => int_a0(9),
Q => \^a_read_reg_107_reg[15]\(9),
R => \^sr\(0)
);
int_ap_done_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8FFFFFFF88888888"
)
port map (
I0 => Q(2),
I1 => \^co\(0),
I2 => \^s_axi_gcd_bus_rvalid\(0),
I3 => s_axi_gcd_bus_ARVALID,
I4 => int_ap_done1,
I5 => int_ap_done,
O => int_ap_done_i_1_n_0
);
int_ap_done_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(5),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => s_axi_gcd_bus_ARADDR(1),
I3 => s_axi_gcd_bus_ARADDR(0),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => s_axi_gcd_bus_ARADDR(2),
O => int_ap_done1
);
int_ap_done_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_ap_done_i_1_n_0,
Q => int_ap_done,
R => \^sr\(0)
);
int_ap_idle_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Q(0),
I1 => ap_start,
O => ap_idle
);
int_ap_idle_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => ap_idle,
Q => int_ap_idle,
R => \^sr\(0)
);
int_ap_ready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^co\(0),
I1 => Q(2),
O => ap_done
);
int_ap_ready_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => ap_done,
Q => int_ap_ready,
R => \^sr\(0)
);
int_ap_start_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFBFFF80"
)
port map (
I0 => int_auto_restart,
I1 => Q(2),
I2 => \^co\(0),
I3 => int_ap_start3_out,
I4 => ap_start,
O => int_ap_start_i_1_n_0
);
int_ap_start_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(0),
I1 => \p_s_reg_45_reg[15]\(0),
I2 => \p_s_reg_45_reg[15]\(2),
I3 => \result_reg_56_reg[15]\(2),
I4 => \p_s_reg_45_reg[15]\(1),
I5 => \result_reg_56_reg[15]\(1),
O => int_ap_start_i_10_n_0
);
int_ap_start_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \waddr_reg_n_0_[2]\,
I3 => \int_ier[1]_i_2_n_0\,
I4 => \waddr_reg_n_0_[3]\,
O => int_ap_start3_out
);
int_ap_start_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \p_s_reg_45_reg[15]\(15),
I1 => \result_reg_56_reg[15]\(15),
O => int_ap_start_i_5_n_0
);
int_ap_start_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(12),
I1 => \p_s_reg_45_reg[15]\(12),
I2 => \p_s_reg_45_reg[15]\(14),
I3 => \result_reg_56_reg[15]\(14),
I4 => \p_s_reg_45_reg[15]\(13),
I5 => \result_reg_56_reg[15]\(13),
O => int_ap_start_i_6_n_0
);
int_ap_start_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(9),
I1 => \p_s_reg_45_reg[15]\(9),
I2 => \p_s_reg_45_reg[15]\(11),
I3 => \result_reg_56_reg[15]\(11),
I4 => \p_s_reg_45_reg[15]\(10),
I5 => \result_reg_56_reg[15]\(10),
O => int_ap_start_i_7_n_0
);
int_ap_start_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(6),
I1 => \p_s_reg_45_reg[15]\(6),
I2 => \p_s_reg_45_reg[15]\(8),
I3 => \result_reg_56_reg[15]\(8),
I4 => \p_s_reg_45_reg[15]\(7),
I5 => \result_reg_56_reg[15]\(7),
O => int_ap_start_i_8_n_0
);
int_ap_start_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \result_reg_56_reg[15]\(3),
I1 => \p_s_reg_45_reg[15]\(3),
I2 => \p_s_reg_45_reg[15]\(5),
I3 => \result_reg_56_reg[15]\(5),
I4 => \p_s_reg_45_reg[15]\(4),
I5 => \result_reg_56_reg[15]\(4),
O => int_ap_start_i_9_n_0
);
int_ap_start_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_ap_start_i_1_n_0,
Q => ap_start,
R => \^sr\(0)
);
int_ap_start_reg_i_2: unisim.vcomponents.CARRY4
port map (
CI => int_ap_start_reg_i_4_n_0,
CO(3 downto 2) => NLW_int_ap_start_reg_i_2_CO_UNCONNECTED(3 downto 2),
CO(1) => \^co\(0),
CO(0) => int_ap_start_reg_i_2_n_3,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_int_ap_start_reg_i_2_O_UNCONNECTED(3 downto 0),
S(3 downto 2) => B"00",
S(1) => int_ap_start_i_5_n_0,
S(0) => int_ap_start_i_6_n_0
);
int_ap_start_reg_i_4: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => int_ap_start_reg_i_4_n_0,
CO(2) => int_ap_start_reg_i_4_n_1,
CO(1) => int_ap_start_reg_i_4_n_2,
CO(0) => int_ap_start_reg_i_4_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_int_ap_start_reg_i_4_O_UNCONNECTED(3 downto 0),
S(3) => int_ap_start_i_7_n_0,
S(2) => int_ap_start_i_8_n_0,
S(1) => int_ap_start_i_9_n_0,
S(0) => int_ap_start_i_10_n_0
);
int_auto_restart_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => s_axi_gcd_bus_WDATA(7),
I1 => \waddr_reg_n_0_[3]\,
I2 => \int_ier[1]_i_2_n_0\,
I3 => \waddr_reg_n_0_[2]\,
I4 => s_axi_gcd_bus_WSTRB(0),
I5 => int_auto_restart,
O => int_auto_restart_i_1_n_0
);
int_auto_restart_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_auto_restart_i_1_n_0,
Q => int_auto_restart,
R => \^sr\(0)
);
\int_b[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(0),
O => int_b0(0)
);
\int_b[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(10),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(10),
O => int_b0(10)
);
\int_b[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(11),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(11),
O => int_b0(11)
);
\int_b[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(12),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(12),
O => int_b0(12)
);
\int_b[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(13),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(13),
O => int_b0(13)
);
\int_b[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(14),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(14),
O => int_b0(14)
);
\int_b[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \waddr_reg_n_0_[3]\,
I1 => \waddr_reg_n_0_[4]\,
I2 => \int_a[15]_i_3_n_0\,
I3 => \waddr_reg_n_0_[2]\,
O => \int_b[15]_i_1_n_0\
);
\int_b[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(15),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(15),
O => int_b0(15)
);
\int_b[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(1),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(1),
O => int_b0(1)
);
\int_b[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(2),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(2),
O => int_b0(2)
);
\int_b[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(3),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(3),
O => int_b0(3)
);
\int_b[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(4),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(4),
O => int_b0(4)
);
\int_b[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(5),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(5),
O => int_b0(5)
);
\int_b[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(6),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(6),
O => int_b0(6)
);
\int_b[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(7),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \^b_read_reg_102_reg[15]\(7),
O => int_b0(7)
);
\int_b[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(8),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(8),
O => int_b0(8)
);
\int_b[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_gcd_bus_WDATA(9),
I1 => s_axi_gcd_bus_WSTRB(1),
I2 => \^b_read_reg_102_reg[15]\(9),
O => int_b0(9)
);
\int_b_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(0),
Q => \^b_read_reg_102_reg[15]\(0),
R => \^sr\(0)
);
\int_b_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(10),
Q => \^b_read_reg_102_reg[15]\(10),
R => \^sr\(0)
);
\int_b_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(11),
Q => \^b_read_reg_102_reg[15]\(11),
R => \^sr\(0)
);
\int_b_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(12),
Q => \^b_read_reg_102_reg[15]\(12),
R => \^sr\(0)
);
\int_b_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(13),
Q => \^b_read_reg_102_reg[15]\(13),
R => \^sr\(0)
);
\int_b_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(14),
Q => \^b_read_reg_102_reg[15]\(14),
R => \^sr\(0)
);
\int_b_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(15),
Q => \^b_read_reg_102_reg[15]\(15),
R => \^sr\(0)
);
\int_b_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(1),
Q => \^b_read_reg_102_reg[15]\(1),
R => \^sr\(0)
);
\int_b_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(2),
Q => \^b_read_reg_102_reg[15]\(2),
R => \^sr\(0)
);
\int_b_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(3),
Q => \^b_read_reg_102_reg[15]\(3),
R => \^sr\(0)
);
\int_b_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(4),
Q => \^b_read_reg_102_reg[15]\(4),
R => \^sr\(0)
);
\int_b_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(5),
Q => \^b_read_reg_102_reg[15]\(5),
R => \^sr\(0)
);
\int_b_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(6),
Q => \^b_read_reg_102_reg[15]\(6),
R => \^sr\(0)
);
\int_b_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(7),
Q => \^b_read_reg_102_reg[15]\(7),
R => \^sr\(0)
);
\int_b_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(8),
Q => \^b_read_reg_102_reg[15]\(8),
R => \^sr\(0)
);
\int_b_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \int_b[15]_i_1_n_0\,
D => int_b0(9),
Q => \^b_read_reg_102_reg[15]\(9),
R => \^sr\(0)
);
int_gie_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \waddr_reg_n_0_[3]\,
I3 => \waddr_reg_n_0_[2]\,
I4 => \int_ier[1]_i_2_n_0\,
I5 => int_gie_reg_n_0,
O => int_gie_i_1_n_0
);
int_gie_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => int_gie_i_1_n_0,
Q => int_gie_reg_n_0,
R => \^sr\(0)
);
\int_ier[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFFFFF00800000"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \int_ier[1]_i_2_n_0\,
I3 => \waddr_reg_n_0_[2]\,
I4 => \waddr_reg_n_0_[3]\,
I5 => \int_ier_reg_n_0_[0]\,
O => \int_ier[0]_i_1_n_0\
);
\int_ier[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFFFFF00800000"
)
port map (
I0 => s_axi_gcd_bus_WDATA(1),
I1 => s_axi_gcd_bus_WSTRB(0),
I2 => \int_ier[1]_i_2_n_0\,
I3 => \waddr_reg_n_0_[2]\,
I4 => \waddr_reg_n_0_[3]\,
I5 => \int_ier_reg_n_0_[1]\,
O => \int_ier[1]_i_1_n_0\
);
\int_ier[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => \waddr_reg_n_0_[1]\,
I1 => s_axi_gcd_bus_WVALID,
I2 => \^out\(1),
I3 => \waddr_reg_n_0_[5]\,
I4 => \waddr_reg_n_0_[0]\,
I5 => \waddr_reg_n_0_[4]\,
O => \int_ier[1]_i_2_n_0\
);
\int_ier_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_ier[0]_i_1_n_0\,
Q => \int_ier_reg_n_0_[0]\,
R => \^sr\(0)
);
\int_ier_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_ier[1]_i_1_n_0\,
Q => \int_ier_reg_n_0_[1]\,
R => \^sr\(0)
);
\int_isr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7777777F8888888"
)
port map (
I0 => s_axi_gcd_bus_WDATA(0),
I1 => int_isr6_out,
I2 => \int_ier_reg_n_0_[0]\,
I3 => \^co\(0),
I4 => Q(2),
I5 => \int_isr_reg_n_0_[0]\,
O => \int_isr[0]_i_1_n_0\
);
\int_isr[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => s_axi_gcd_bus_WSTRB(0),
I1 => \waddr_reg_n_0_[2]\,
I2 => \int_ier[1]_i_2_n_0\,
I3 => \waddr_reg_n_0_[3]\,
O => int_isr6_out
);
\int_isr[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7777777F8888888"
)
port map (
I0 => s_axi_gcd_bus_WDATA(1),
I1 => int_isr6_out,
I2 => \int_ier_reg_n_0_[1]\,
I3 => \^co\(0),
I4 => Q(2),
I5 => p_1_in,
O => \int_isr[1]_i_1_n_0\
);
\int_isr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_isr[0]_i_1_n_0\,
Q => \int_isr_reg_n_0_[0]\,
R => \^sr\(0)
);
\int_isr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \int_isr[1]_i_1_n_0\,
Q => p_1_in,
R => \^sr\(0)
);
int_pResult_ap_vld_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8FFFFFFF88888888"
)
port map (
I0 => Q(2),
I1 => \^co\(0),
I2 => \^s_axi_gcd_bus_rvalid\(0),
I3 => s_axi_gcd_bus_ARVALID,
I4 => int_pResult_ap_vld1,
I5 => int_pResult_ap_vld,
O => int_pResult_ap_vld_i_1_n_0
);
int_pResult_ap_vld_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(1),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => s_axi_gcd_bus_ARADDR(5),
I3 => s_axi_gcd_bus_ARADDR(2),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => s_axi_gcd_bus_ARADDR(0),
O => int_pResult_ap_vld1
);
int_pResult_ap_vld_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => int_pResult_ap_vld_i_1_n_0,
Q => int_pResult_ap_vld,
R => \^sr\(0)
);
\int_pResult_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(0),
Q => int_pResult(0),
R => \^sr\(0)
);
\int_pResult_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(10),
Q => int_pResult(10),
R => \^sr\(0)
);
\int_pResult_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(11),
Q => int_pResult(11),
R => \^sr\(0)
);
\int_pResult_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(12),
Q => int_pResult(12),
R => \^sr\(0)
);
\int_pResult_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(13),
Q => int_pResult(13),
R => \^sr\(0)
);
\int_pResult_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(14),
Q => int_pResult(14),
R => \^sr\(0)
);
\int_pResult_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(15),
Q => int_pResult(15),
R => \^sr\(0)
);
\int_pResult_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(1),
Q => int_pResult(1),
R => \^sr\(0)
);
\int_pResult_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(2),
Q => int_pResult(2),
R => \^sr\(0)
);
\int_pResult_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(3),
Q => int_pResult(3),
R => \^sr\(0)
);
\int_pResult_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(4),
Q => int_pResult(4),
R => \^sr\(0)
);
\int_pResult_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(5),
Q => int_pResult(5),
R => \^sr\(0)
);
\int_pResult_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(6),
Q => int_pResult(6),
R => \^sr\(0)
);
\int_pResult_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(7),
Q => int_pResult(7),
R => \^sr\(0)
);
\int_pResult_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(8),
Q => int_pResult(8),
R => \^sr\(0)
);
\int_pResult_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_done,
D => \p_s_reg_45_reg[15]\(9),
Q => int_pResult(9),
R => \^sr\(0)
);
interrupt_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"E0"
)
port map (
I0 => p_1_in,
I1 => \int_isr_reg_n_0_[0]\,
I2 => int_gie_reg_n_0,
O => interrupt
);
\rdata[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => \rdata[0]_i_2_n_0\,
I1 => s_axi_gcd_bus_ARADDR(2),
I2 => \rdata[0]_i_3_n_0\,
I3 => \rdata[1]_i_4_n_0\,
I4 => ar_hs,
I5 => \^s_axi_gcd_bus_rdata\(0),
O => \rdata[0]_i_1_n_0\
);
\rdata[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => \int_ier_reg_n_0_[0]\,
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(0),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => \rdata[0]_i_4_n_0\,
O => \rdata[0]_i_2_n_0\
);
\rdata[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033223000002230"
)
port map (
I0 => int_pResult_ap_vld,
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_gie_reg_n_0,
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => \int_isr_reg_n_0_[0]\,
O => \rdata[0]_i_3_n_0\
);
\rdata[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(0),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(0),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => ap_start,
O => \rdata[0]_i_4_n_0\
);
\rdata[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(10),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(10),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(10),
O => \rdata[10]_i_1_n_0\
);
\rdata[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(11),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(11),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(11),
O => \rdata[11]_i_1_n_0\
);
\rdata[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(12),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(12),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(12),
O => \rdata[12]_i_1_n_0\
);
\rdata[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(13),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(13),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(13),
O => \rdata[13]_i_1_n_0\
);
\rdata[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(14),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(14),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(14),
O => \rdata[14]_i_1_n_0\
);
\rdata[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88888880"
)
port map (
I0 => s_axi_gcd_bus_ARVALID,
I1 => \^s_axi_gcd_bus_rvalid\(0),
I2 => s_axi_gcd_bus_ARADDR(1),
I3 => s_axi_gcd_bus_ARADDR(0),
I4 => s_axi_gcd_bus_ARADDR(2),
O => \rdata[15]_i_1_n_0\
);
\rdata[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_gcd_bus_rvalid\(0),
I1 => s_axi_gcd_bus_ARVALID,
O => ar_hs
);
\rdata[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(15),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(15),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(15),
O => \rdata[15]_i_3_n_0\
);
\rdata[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => \rdata[1]_i_2_n_0\,
I1 => s_axi_gcd_bus_ARADDR(2),
I2 => \rdata[1]_i_3_n_0\,
I3 => \rdata[1]_i_4_n_0\,
I4 => ar_hs,
I5 => \^s_axi_gcd_bus_rdata\(1),
O => \rdata[1]_i_1_n_0\
);
\rdata[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => \int_ier_reg_n_0_[1]\,
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(1),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => s_axi_gcd_bus_ARADDR(3),
I5 => \rdata[1]_i_5_n_0\,
O => \rdata[1]_i_2_n_0\
);
\rdata[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(4),
I1 => s_axi_gcd_bus_ARADDR(5),
I2 => s_axi_gcd_bus_ARADDR(3),
I3 => p_1_in,
O => \rdata[1]_i_3_n_0\
);
\rdata[1]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(1),
I1 => s_axi_gcd_bus_ARADDR(0),
O => \rdata[1]_i_4_n_0\
);
\rdata[1]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(1),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(1),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => int_ap_done,
O => \rdata[1]_i_5_n_0\
);
\rdata[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40FF4000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(5),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(2),
I3 => s_axi_gcd_bus_ARADDR(3),
I4 => \rdata[2]_i_2_n_0\,
O => \rdata[2]_i_1_n_0\
);
\rdata[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(2),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(2),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => int_ap_idle,
O => \rdata[2]_i_2_n_0\
);
\rdata[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40FF4000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(5),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(3),
I3 => s_axi_gcd_bus_ARADDR(3),
I4 => \rdata[3]_i_2_n_0\,
O => \rdata[3]_i_1_n_0\
);
\rdata[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(3),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(3),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => int_ap_ready,
O => \rdata[3]_i_2_n_0\
);
\rdata[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(4),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(4),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(4),
O => \rdata[4]_i_1_n_0\
);
\rdata[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(5),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(5),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(5),
O => \rdata[5]_i_1_n_0\
);
\rdata[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(6),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(6),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(6),
O => \rdata[6]_i_1_n_0\
);
\rdata[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40FF4000"
)
port map (
I0 => s_axi_gcd_bus_ARADDR(5),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => \^b_read_reg_102_reg[15]\(7),
I3 => s_axi_gcd_bus_ARADDR(3),
I4 => \rdata[7]_i_2_n_0\,
O => \rdata[7]_i_1_n_0\
);
\rdata[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^a_read_reg_107_reg[15]\(7),
I1 => s_axi_gcd_bus_ARADDR(4),
I2 => int_pResult(7),
I3 => s_axi_gcd_bus_ARADDR(5),
I4 => int_auto_restart,
O => \rdata[7]_i_2_n_0\
);
\rdata[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(8),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(8),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(8),
O => \rdata[8]_i_1_n_0\
);
\rdata[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0033B8000000B800"
)
port map (
I0 => \^b_read_reg_102_reg[15]\(9),
I1 => s_axi_gcd_bus_ARADDR(3),
I2 => \^a_read_reg_107_reg[15]\(9),
I3 => s_axi_gcd_bus_ARADDR(4),
I4 => s_axi_gcd_bus_ARADDR(5),
I5 => int_pResult(9),
O => \rdata[9]_i_1_n_0\
);
\rdata_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \rdata[0]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(0),
R => '0'
);
\rdata_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[10]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(10),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[11]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(11),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[12]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(12),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[13]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(13),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[14]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(14),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[15]_i_3_n_0\,
Q => \^s_axi_gcd_bus_rdata\(15),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \rdata[1]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(1),
R => '0'
);
\rdata_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[2]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(2),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[3]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(3),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[4]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(4),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[5]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(5),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[6]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(6),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[7]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(7),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[8]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(8),
R => \rdata[15]_i_1_n_0\
);
\rdata_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[9]_i_1_n_0\,
Q => \^s_axi_gcd_bus_rdata\(9),
R => \rdata[15]_i_1_n_0\
);
\waddr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^out\(0),
I1 => s_axi_gcd_bus_AWVALID,
O => waddr
);
\waddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(0),
Q => \waddr_reg_n_0_[0]\,
R => '0'
);
\waddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(1),
Q => \waddr_reg_n_0_[1]\,
R => '0'
);
\waddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(2),
Q => \waddr_reg_n_0_[2]\,
R => '0'
);
\waddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(3),
Q => \waddr_reg_n_0_[3]\,
R => '0'
);
\waddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(4),
Q => \waddr_reg_n_0_[4]\,
R => '0'
);
\waddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_gcd_bus_AWADDR(5),
Q => \waddr_reg_n_0_[5]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd is
port (
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
s_axi_gcd_bus_AWVALID : in STD_LOGIC;
s_axi_gcd_bus_AWREADY : out STD_LOGIC;
s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_gcd_bus_WVALID : in STD_LOGIC;
s_axi_gcd_bus_WREADY : out STD_LOGIC;
s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_gcd_bus_ARVALID : in STD_LOGIC;
s_axi_gcd_bus_ARREADY : out STD_LOGIC;
s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_gcd_bus_RVALID : out STD_LOGIC;
s_axi_gcd_bus_RREADY : in STD_LOGIC;
s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_gcd_bus_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_gcd_bus_BVALID : out STD_LOGIC;
s_axi_gcd_bus_BREADY : in STD_LOGIC;
s_axi_gcd_bus_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt : out STD_LOGIC
);
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 32;
attribute C_S_AXI_GCD_BUS_ADDR_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 6;
attribute C_S_AXI_GCD_BUS_DATA_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 32;
attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 4;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is 4;
attribute ap_ST_fsm_state1 : string;
attribute ap_ST_fsm_state1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b0001";
attribute ap_ST_fsm_state2 : string;
attribute ap_ST_fsm_state2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b0010";
attribute ap_ST_fsm_state3 : string;
attribute ap_ST_fsm_state3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b0100";
attribute ap_ST_fsm_state4 : string;
attribute ap_ST_fsm_state4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "4'b1000";
attribute hls_module : string;
attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd is
signal \<const0>\ : STD_LOGIC;
signal a : STD_LOGIC_VECTOR ( 15 downto 0 );
signal a_assign_fu_78_p21_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal a_assign_reg_121 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal a_assign_reg_1210 : STD_LOGIC;
signal \a_assign_reg_121[11]_i_2_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[11]_i_3_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[11]_i_4_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[11]_i_5_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[15]_i_2_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[15]_i_3_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[15]_i_4_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[15]_i_5_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[3]_i_2_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[3]_i_3_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[3]_i_4_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[3]_i_5_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[7]_i_2_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[7]_i_3_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[7]_i_4_n_0\ : STD_LOGIC;
signal \a_assign_reg_121[7]_i_5_n_0\ : STD_LOGIC;
signal \a_assign_reg_121_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \a_assign_reg_121_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \a_assign_reg_121_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \a_assign_reg_121_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \a_assign_reg_121_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \a_assign_reg_121_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \a_assign_reg_121_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \a_assign_reg_121_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \a_assign_reg_121_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \a_assign_reg_121_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \a_assign_reg_121_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \a_assign_reg_121_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \a_assign_reg_121_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \a_assign_reg_121_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \a_assign_reg_121_reg[7]_i_1_n_3\ : STD_LOGIC;
signal a_read_reg_107 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \ap_CS_fsm_reg_n_0_[0]\ : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
signal ap_CS_fsm_state3 : STD_LOGIC;
signal ap_CS_fsm_state4 : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ap_NS_fsm1 : STD_LOGIC;
signal ap_rst_n_inv : STD_LOGIC;
signal b : STD_LOGIC_VECTOR ( 15 downto 0 );
signal b_assign_fu_84_p20_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal b_assign_reg_126 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \b_assign_reg_126[11]_i_2_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[11]_i_3_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[11]_i_4_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[11]_i_5_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[15]_i_2_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[15]_i_3_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[15]_i_4_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[15]_i_5_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[3]_i_2_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[3]_i_3_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[3]_i_4_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[3]_i_5_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[7]_i_2_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[7]_i_3_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[7]_i_4_n_0\ : STD_LOGIC;
signal \b_assign_reg_126[7]_i_5_n_0\ : STD_LOGIC;
signal \b_assign_reg_126_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \b_assign_reg_126_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \b_assign_reg_126_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \b_assign_reg_126_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \b_assign_reg_126_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \b_assign_reg_126_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \b_assign_reg_126_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \b_assign_reg_126_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \b_assign_reg_126_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \b_assign_reg_126_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \b_assign_reg_126_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \b_assign_reg_126_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \b_assign_reg_126_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \b_assign_reg_126_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \b_assign_reg_126_reg[7]_i_1_n_3\ : STD_LOGIC;
signal b_read_reg_102 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 15 downto 0 );
signal p_s_reg_45 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \p_s_reg_45[0]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[10]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[11]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[12]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[13]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[14]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[15]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[15]_i_2_n_0\ : STD_LOGIC;
signal \p_s_reg_45[1]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[2]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[3]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[4]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[5]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[6]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[7]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[8]_i_1_n_0\ : STD_LOGIC;
signal \p_s_reg_45[9]_i_1_n_0\ : STD_LOGIC;
signal result_reg_56 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \result_reg_56[15]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_gcd_bus_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal tmp_2_fu_66_p2 : STD_LOGIC;
signal tmp_3_fu_72_p2 : STD_LOGIC;
signal tmp_3_reg_115 : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_10_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_11_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_12_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_13_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_14_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_15_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_16_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_17_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_18_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_3_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_4_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_5_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_6_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_7_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_8_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115[0]_i_9_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \tmp_3_reg_115_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \NLW_a_assign_reg_121_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_b_assign_reg_126_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_tmp_3_reg_115_reg[0]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_tmp_3_reg_115_reg[0]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of \ap_CS_fsm_reg[0]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[1]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[2]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[3]\ : label is "none";
begin
s_axi_gcd_bus_BRESP(1) <= \<const0>\;
s_axi_gcd_bus_BRESP(0) <= \<const0>\;
s_axi_gcd_bus_RDATA(31) <= \<const0>\;
s_axi_gcd_bus_RDATA(30) <= \<const0>\;
s_axi_gcd_bus_RDATA(29) <= \<const0>\;
s_axi_gcd_bus_RDATA(28) <= \<const0>\;
s_axi_gcd_bus_RDATA(27) <= \<const0>\;
s_axi_gcd_bus_RDATA(26) <= \<const0>\;
s_axi_gcd_bus_RDATA(25) <= \<const0>\;
s_axi_gcd_bus_RDATA(24) <= \<const0>\;
s_axi_gcd_bus_RDATA(23) <= \<const0>\;
s_axi_gcd_bus_RDATA(22) <= \<const0>\;
s_axi_gcd_bus_RDATA(21) <= \<const0>\;
s_axi_gcd_bus_RDATA(20) <= \<const0>\;
s_axi_gcd_bus_RDATA(19) <= \<const0>\;
s_axi_gcd_bus_RDATA(18) <= \<const0>\;
s_axi_gcd_bus_RDATA(17) <= \<const0>\;
s_axi_gcd_bus_RDATA(16) <= \<const0>\;
s_axi_gcd_bus_RDATA(15 downto 0) <= \^s_axi_gcd_bus_rdata\(15 downto 0);
s_axi_gcd_bus_RRESP(1) <= \<const0>\;
s_axi_gcd_bus_RRESP(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\a_assign_reg_121[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(11),
I1 => p_s_reg_45(11),
O => \a_assign_reg_121[11]_i_2_n_0\
);
\a_assign_reg_121[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(10),
I1 => p_s_reg_45(10),
O => \a_assign_reg_121[11]_i_3_n_0\
);
\a_assign_reg_121[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(9),
I1 => p_s_reg_45(9),
O => \a_assign_reg_121[11]_i_4_n_0\
);
\a_assign_reg_121[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(8),
I1 => p_s_reg_45(8),
O => \a_assign_reg_121[11]_i_5_n_0\
);
\a_assign_reg_121[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(15),
I1 => p_s_reg_45(15),
O => \a_assign_reg_121[15]_i_2_n_0\
);
\a_assign_reg_121[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(14),
I1 => p_s_reg_45(14),
O => \a_assign_reg_121[15]_i_3_n_0\
);
\a_assign_reg_121[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(13),
I1 => p_s_reg_45(13),
O => \a_assign_reg_121[15]_i_4_n_0\
);
\a_assign_reg_121[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(12),
I1 => p_s_reg_45(12),
O => \a_assign_reg_121[15]_i_5_n_0\
);
\a_assign_reg_121[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(3),
I1 => p_s_reg_45(3),
O => \a_assign_reg_121[3]_i_2_n_0\
);
\a_assign_reg_121[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(2),
I1 => p_s_reg_45(2),
O => \a_assign_reg_121[3]_i_3_n_0\
);
\a_assign_reg_121[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(1),
I1 => p_s_reg_45(1),
O => \a_assign_reg_121[3]_i_4_n_0\
);
\a_assign_reg_121[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(0),
I1 => p_s_reg_45(0),
O => \a_assign_reg_121[3]_i_5_n_0\
);
\a_assign_reg_121[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(7),
I1 => p_s_reg_45(7),
O => \a_assign_reg_121[7]_i_2_n_0\
);
\a_assign_reg_121[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(6),
I1 => p_s_reg_45(6),
O => \a_assign_reg_121[7]_i_3_n_0\
);
\a_assign_reg_121[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(5),
I1 => p_s_reg_45(5),
O => \a_assign_reg_121[7]_i_4_n_0\
);
\a_assign_reg_121[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => result_reg_56(4),
I1 => p_s_reg_45(4),
O => \a_assign_reg_121[7]_i_5_n_0\
);
\a_assign_reg_121_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(0),
Q => a_assign_reg_121(0),
R => '0'
);
\a_assign_reg_121_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(10),
Q => a_assign_reg_121(10),
R => '0'
);
\a_assign_reg_121_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(11),
Q => a_assign_reg_121(11),
R => '0'
);
\a_assign_reg_121_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \a_assign_reg_121_reg[7]_i_1_n_0\,
CO(3) => \a_assign_reg_121_reg[11]_i_1_n_0\,
CO(2) => \a_assign_reg_121_reg[11]_i_1_n_1\,
CO(1) => \a_assign_reg_121_reg[11]_i_1_n_2\,
CO(0) => \a_assign_reg_121_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => result_reg_56(11 downto 8),
O(3 downto 0) => a_assign_fu_78_p21_out(11 downto 8),
S(3) => \a_assign_reg_121[11]_i_2_n_0\,
S(2) => \a_assign_reg_121[11]_i_3_n_0\,
S(1) => \a_assign_reg_121[11]_i_4_n_0\,
S(0) => \a_assign_reg_121[11]_i_5_n_0\
);
\a_assign_reg_121_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(12),
Q => a_assign_reg_121(12),
R => '0'
);
\a_assign_reg_121_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(13),
Q => a_assign_reg_121(13),
R => '0'
);
\a_assign_reg_121_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(14),
Q => a_assign_reg_121(14),
R => '0'
);
\a_assign_reg_121_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(15),
Q => a_assign_reg_121(15),
R => '0'
);
\a_assign_reg_121_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \a_assign_reg_121_reg[11]_i_1_n_0\,
CO(3) => \NLW_a_assign_reg_121_reg[15]_i_1_CO_UNCONNECTED\(3),
CO(2) => \a_assign_reg_121_reg[15]_i_1_n_1\,
CO(1) => \a_assign_reg_121_reg[15]_i_1_n_2\,
CO(0) => \a_assign_reg_121_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => result_reg_56(14 downto 12),
O(3 downto 0) => a_assign_fu_78_p21_out(15 downto 12),
S(3) => \a_assign_reg_121[15]_i_2_n_0\,
S(2) => \a_assign_reg_121[15]_i_3_n_0\,
S(1) => \a_assign_reg_121[15]_i_4_n_0\,
S(0) => \a_assign_reg_121[15]_i_5_n_0\
);
\a_assign_reg_121_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(1),
Q => a_assign_reg_121(1),
R => '0'
);
\a_assign_reg_121_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(2),
Q => a_assign_reg_121(2),
R => '0'
);
\a_assign_reg_121_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(3),
Q => a_assign_reg_121(3),
R => '0'
);
\a_assign_reg_121_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \a_assign_reg_121_reg[3]_i_1_n_0\,
CO(2) => \a_assign_reg_121_reg[3]_i_1_n_1\,
CO(1) => \a_assign_reg_121_reg[3]_i_1_n_2\,
CO(0) => \a_assign_reg_121_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => result_reg_56(3 downto 0),
O(3 downto 0) => a_assign_fu_78_p21_out(3 downto 0),
S(3) => \a_assign_reg_121[3]_i_2_n_0\,
S(2) => \a_assign_reg_121[3]_i_3_n_0\,
S(1) => \a_assign_reg_121[3]_i_4_n_0\,
S(0) => \a_assign_reg_121[3]_i_5_n_0\
);
\a_assign_reg_121_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(4),
Q => a_assign_reg_121(4),
R => '0'
);
\a_assign_reg_121_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(5),
Q => a_assign_reg_121(5),
R => '0'
);
\a_assign_reg_121_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(6),
Q => a_assign_reg_121(6),
R => '0'
);
\a_assign_reg_121_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(7),
Q => a_assign_reg_121(7),
R => '0'
);
\a_assign_reg_121_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \a_assign_reg_121_reg[3]_i_1_n_0\,
CO(3) => \a_assign_reg_121_reg[7]_i_1_n_0\,
CO(2) => \a_assign_reg_121_reg[7]_i_1_n_1\,
CO(1) => \a_assign_reg_121_reg[7]_i_1_n_2\,
CO(0) => \a_assign_reg_121_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => result_reg_56(7 downto 4),
O(3 downto 0) => a_assign_fu_78_p21_out(7 downto 4),
S(3) => \a_assign_reg_121[7]_i_2_n_0\,
S(2) => \a_assign_reg_121[7]_i_3_n_0\,
S(1) => \a_assign_reg_121[7]_i_4_n_0\,
S(0) => \a_assign_reg_121[7]_i_5_n_0\
);
\a_assign_reg_121_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(8),
Q => a_assign_reg_121(8),
R => '0'
);
\a_assign_reg_121_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => a_assign_fu_78_p21_out(9),
Q => a_assign_reg_121(9),
R => '0'
);
\a_read_reg_107_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(0),
Q => a_read_reg_107(0),
R => '0'
);
\a_read_reg_107_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(10),
Q => a_read_reg_107(10),
R => '0'
);
\a_read_reg_107_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(11),
Q => a_read_reg_107(11),
R => '0'
);
\a_read_reg_107_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(12),
Q => a_read_reg_107(12),
R => '0'
);
\a_read_reg_107_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(13),
Q => a_read_reg_107(13),
R => '0'
);
\a_read_reg_107_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(14),
Q => a_read_reg_107(14),
R => '0'
);
\a_read_reg_107_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(15),
Q => a_read_reg_107(15),
R => '0'
);
\a_read_reg_107_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(1),
Q => a_read_reg_107(1),
R => '0'
);
\a_read_reg_107_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(2),
Q => a_read_reg_107(2),
R => '0'
);
\a_read_reg_107_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(3),
Q => a_read_reg_107(3),
R => '0'
);
\a_read_reg_107_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(4),
Q => a_read_reg_107(4),
R => '0'
);
\a_read_reg_107_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(5),
Q => a_read_reg_107(5),
R => '0'
);
\a_read_reg_107_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(6),
Q => a_read_reg_107(6),
R => '0'
);
\a_read_reg_107_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(7),
Q => a_read_reg_107(7),
R => '0'
);
\a_read_reg_107_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(8),
Q => a_read_reg_107(8),
R => '0'
);
\a_read_reg_107_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => a(9),
Q => a_read_reg_107(9),
R => '0'
);
\ap_CS_fsm[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ap_CS_fsm_state2,
I1 => ap_CS_fsm_state4,
O => ap_NS_fsm(2)
);
\ap_CS_fsm[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ap_CS_fsm_state3,
I1 => tmp_2_fu_66_p2,
O => a_assign_reg_1210
);
\ap_CS_fsm_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(0),
Q => \ap_CS_fsm_reg_n_0_[0]\,
S => ap_rst_n_inv
);
\ap_CS_fsm_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(1),
Q => ap_CS_fsm_state2,
R => ap_rst_n_inv
);
\ap_CS_fsm_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(2),
Q => ap_CS_fsm_state3,
R => ap_rst_n_inv
);
\ap_CS_fsm_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => a_assign_reg_1210,
Q => ap_CS_fsm_state4,
R => ap_rst_n_inv
);
\b_assign_reg_126[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(11),
I1 => result_reg_56(11),
O => \b_assign_reg_126[11]_i_2_n_0\
);
\b_assign_reg_126[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(10),
I1 => result_reg_56(10),
O => \b_assign_reg_126[11]_i_3_n_0\
);
\b_assign_reg_126[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(9),
I1 => result_reg_56(9),
O => \b_assign_reg_126[11]_i_4_n_0\
);
\b_assign_reg_126[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(8),
I1 => result_reg_56(8),
O => \b_assign_reg_126[11]_i_5_n_0\
);
\b_assign_reg_126[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(15),
I1 => result_reg_56(15),
O => \b_assign_reg_126[15]_i_2_n_0\
);
\b_assign_reg_126[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(14),
I1 => result_reg_56(14),
O => \b_assign_reg_126[15]_i_3_n_0\
);
\b_assign_reg_126[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(13),
I1 => result_reg_56(13),
O => \b_assign_reg_126[15]_i_4_n_0\
);
\b_assign_reg_126[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(12),
I1 => result_reg_56(12),
O => \b_assign_reg_126[15]_i_5_n_0\
);
\b_assign_reg_126[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(3),
I1 => result_reg_56(3),
O => \b_assign_reg_126[3]_i_2_n_0\
);
\b_assign_reg_126[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(2),
I1 => result_reg_56(2),
O => \b_assign_reg_126[3]_i_3_n_0\
);
\b_assign_reg_126[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(1),
I1 => result_reg_56(1),
O => \b_assign_reg_126[3]_i_4_n_0\
);
\b_assign_reg_126[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(0),
I1 => result_reg_56(0),
O => \b_assign_reg_126[3]_i_5_n_0\
);
\b_assign_reg_126[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(7),
I1 => result_reg_56(7),
O => \b_assign_reg_126[7]_i_2_n_0\
);
\b_assign_reg_126[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(6),
I1 => result_reg_56(6),
O => \b_assign_reg_126[7]_i_3_n_0\
);
\b_assign_reg_126[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(5),
I1 => result_reg_56(5),
O => \b_assign_reg_126[7]_i_4_n_0\
);
\b_assign_reg_126[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_s_reg_45(4),
I1 => result_reg_56(4),
O => \b_assign_reg_126[7]_i_5_n_0\
);
\b_assign_reg_126_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(0),
Q => b_assign_reg_126(0),
R => '0'
);
\b_assign_reg_126_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(10),
Q => b_assign_reg_126(10),
R => '0'
);
\b_assign_reg_126_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(11),
Q => b_assign_reg_126(11),
R => '0'
);
\b_assign_reg_126_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \b_assign_reg_126_reg[7]_i_1_n_0\,
CO(3) => \b_assign_reg_126_reg[11]_i_1_n_0\,
CO(2) => \b_assign_reg_126_reg[11]_i_1_n_1\,
CO(1) => \b_assign_reg_126_reg[11]_i_1_n_2\,
CO(0) => \b_assign_reg_126_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_s_reg_45(11 downto 8),
O(3 downto 0) => b_assign_fu_84_p20_out(11 downto 8),
S(3) => \b_assign_reg_126[11]_i_2_n_0\,
S(2) => \b_assign_reg_126[11]_i_3_n_0\,
S(1) => \b_assign_reg_126[11]_i_4_n_0\,
S(0) => \b_assign_reg_126[11]_i_5_n_0\
);
\b_assign_reg_126_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(12),
Q => b_assign_reg_126(12),
R => '0'
);
\b_assign_reg_126_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(13),
Q => b_assign_reg_126(13),
R => '0'
);
\b_assign_reg_126_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(14),
Q => b_assign_reg_126(14),
R => '0'
);
\b_assign_reg_126_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(15),
Q => b_assign_reg_126(15),
R => '0'
);
\b_assign_reg_126_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \b_assign_reg_126_reg[11]_i_1_n_0\,
CO(3) => \NLW_b_assign_reg_126_reg[15]_i_1_CO_UNCONNECTED\(3),
CO(2) => \b_assign_reg_126_reg[15]_i_1_n_1\,
CO(1) => \b_assign_reg_126_reg[15]_i_1_n_2\,
CO(0) => \b_assign_reg_126_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => p_s_reg_45(14 downto 12),
O(3 downto 0) => b_assign_fu_84_p20_out(15 downto 12),
S(3) => \b_assign_reg_126[15]_i_2_n_0\,
S(2) => \b_assign_reg_126[15]_i_3_n_0\,
S(1) => \b_assign_reg_126[15]_i_4_n_0\,
S(0) => \b_assign_reg_126[15]_i_5_n_0\
);
\b_assign_reg_126_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(1),
Q => b_assign_reg_126(1),
R => '0'
);
\b_assign_reg_126_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(2),
Q => b_assign_reg_126(2),
R => '0'
);
\b_assign_reg_126_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(3),
Q => b_assign_reg_126(3),
R => '0'
);
\b_assign_reg_126_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \b_assign_reg_126_reg[3]_i_1_n_0\,
CO(2) => \b_assign_reg_126_reg[3]_i_1_n_1\,
CO(1) => \b_assign_reg_126_reg[3]_i_1_n_2\,
CO(0) => \b_assign_reg_126_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => p_s_reg_45(3 downto 0),
O(3 downto 0) => b_assign_fu_84_p20_out(3 downto 0),
S(3) => \b_assign_reg_126[3]_i_2_n_0\,
S(2) => \b_assign_reg_126[3]_i_3_n_0\,
S(1) => \b_assign_reg_126[3]_i_4_n_0\,
S(0) => \b_assign_reg_126[3]_i_5_n_0\
);
\b_assign_reg_126_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(4),
Q => b_assign_reg_126(4),
R => '0'
);
\b_assign_reg_126_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(5),
Q => b_assign_reg_126(5),
R => '0'
);
\b_assign_reg_126_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(6),
Q => b_assign_reg_126(6),
R => '0'
);
\b_assign_reg_126_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(7),
Q => b_assign_reg_126(7),
R => '0'
);
\b_assign_reg_126_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \b_assign_reg_126_reg[3]_i_1_n_0\,
CO(3) => \b_assign_reg_126_reg[7]_i_1_n_0\,
CO(2) => \b_assign_reg_126_reg[7]_i_1_n_1\,
CO(1) => \b_assign_reg_126_reg[7]_i_1_n_2\,
CO(0) => \b_assign_reg_126_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_s_reg_45(7 downto 4),
O(3 downto 0) => b_assign_fu_84_p20_out(7 downto 4),
S(3) => \b_assign_reg_126[7]_i_2_n_0\,
S(2) => \b_assign_reg_126[7]_i_3_n_0\,
S(1) => \b_assign_reg_126[7]_i_4_n_0\,
S(0) => \b_assign_reg_126[7]_i_5_n_0\
);
\b_assign_reg_126_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(8),
Q => b_assign_reg_126(8),
R => '0'
);
\b_assign_reg_126_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => b_assign_fu_84_p20_out(9),
Q => b_assign_reg_126(9),
R => '0'
);
\b_read_reg_102_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(0),
Q => b_read_reg_102(0),
R => '0'
);
\b_read_reg_102_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(10),
Q => b_read_reg_102(10),
R => '0'
);
\b_read_reg_102_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(11),
Q => b_read_reg_102(11),
R => '0'
);
\b_read_reg_102_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(12),
Q => b_read_reg_102(12),
R => '0'
);
\b_read_reg_102_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(13),
Q => b_read_reg_102(13),
R => '0'
);
\b_read_reg_102_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(14),
Q => b_read_reg_102(14),
R => '0'
);
\b_read_reg_102_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(15),
Q => b_read_reg_102(15),
R => '0'
);
\b_read_reg_102_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(1),
Q => b_read_reg_102(1),
R => '0'
);
\b_read_reg_102_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(2),
Q => b_read_reg_102(2),
R => '0'
);
\b_read_reg_102_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(3),
Q => b_read_reg_102(3),
R => '0'
);
\b_read_reg_102_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(4),
Q => b_read_reg_102(4),
R => '0'
);
\b_read_reg_102_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(5),
Q => b_read_reg_102(5),
R => '0'
);
\b_read_reg_102_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(6),
Q => b_read_reg_102(6),
R => '0'
);
\b_read_reg_102_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(7),
Q => b_read_reg_102(7),
R => '0'
);
\b_read_reg_102_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(8),
Q => b_read_reg_102(8),
R => '0'
);
\b_read_reg_102_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => b(9),
Q => b_read_reg_102(9),
R => '0'
);
gcd_gcd_bus_s_axi_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd_gcd_bus_s_axi
port map (
CO(0) => tmp_2_fu_66_p2,
D(1 downto 0) => ap_NS_fsm(1 downto 0),
E(0) => ap_NS_fsm1,
Q(3) => ap_CS_fsm_state4,
Q(2) => ap_CS_fsm_state3,
Q(1) => ap_CS_fsm_state2,
Q(0) => \ap_CS_fsm_reg_n_0_[0]\,
SR(0) => ap_rst_n_inv,
\a_read_reg_107_reg[15]\(15 downto 0) => a(15 downto 0),
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
\b_read_reg_102_reg[15]\(15 downto 0) => b(15 downto 0),
interrupt => interrupt,
\out\(2) => s_axi_gcd_bus_BVALID,
\out\(1) => s_axi_gcd_bus_WREADY,
\out\(0) => s_axi_gcd_bus_AWREADY,
\p_s_reg_45_reg[15]\(15 downto 0) => p_s_reg_45(15 downto 0),
\result_reg_56_reg[15]\(15 downto 0) => result_reg_56(15 downto 0),
s_axi_gcd_bus_ARADDR(5 downto 0) => s_axi_gcd_bus_ARADDR(5 downto 0),
s_axi_gcd_bus_ARVALID => s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_AWADDR(5 downto 0) => s_axi_gcd_bus_AWADDR(5 downto 0),
s_axi_gcd_bus_AWVALID => s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_BREADY => s_axi_gcd_bus_BREADY,
s_axi_gcd_bus_RDATA(15 downto 0) => \^s_axi_gcd_bus_rdata\(15 downto 0),
s_axi_gcd_bus_RREADY => s_axi_gcd_bus_RREADY,
s_axi_gcd_bus_RVALID(1) => s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RVALID(0) => s_axi_gcd_bus_ARREADY,
s_axi_gcd_bus_WDATA(15 downto 0) => s_axi_gcd_bus_WDATA(15 downto 0),
s_axi_gcd_bus_WSTRB(1 downto 0) => s_axi_gcd_bus_WSTRB(1 downto 0),
s_axi_gcd_bus_WVALID => s_axi_gcd_bus_WVALID
);
\p_s_reg_45[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(0),
I1 => b_read_reg_102(0),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[0]_i_1_n_0\
);
\p_s_reg_45[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(10),
I1 => b_read_reg_102(10),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[10]_i_1_n_0\
);
\p_s_reg_45[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(11),
I1 => b_read_reg_102(11),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[11]_i_1_n_0\
);
\p_s_reg_45[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(12),
I1 => b_read_reg_102(12),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[12]_i_1_n_0\
);
\p_s_reg_45[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(13),
I1 => b_read_reg_102(13),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[13]_i_1_n_0\
);
\p_s_reg_45[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(14),
I1 => b_read_reg_102(14),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[14]_i_1_n_0\
);
\p_s_reg_45[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => tmp_3_reg_115,
I1 => ap_CS_fsm_state4,
I2 => ap_CS_fsm_state2,
O => \p_s_reg_45[15]_i_1_n_0\
);
\p_s_reg_45[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(15),
I1 => b_read_reg_102(15),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[15]_i_2_n_0\
);
\p_s_reg_45[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(1),
I1 => b_read_reg_102(1),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[1]_i_1_n_0\
);
\p_s_reg_45[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(2),
I1 => b_read_reg_102(2),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[2]_i_1_n_0\
);
\p_s_reg_45[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(3),
I1 => b_read_reg_102(3),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[3]_i_1_n_0\
);
\p_s_reg_45[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(4),
I1 => b_read_reg_102(4),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[4]_i_1_n_0\
);
\p_s_reg_45[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(5),
I1 => b_read_reg_102(5),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[5]_i_1_n_0\
);
\p_s_reg_45[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(6),
I1 => b_read_reg_102(6),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[6]_i_1_n_0\
);
\p_s_reg_45[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(7),
I1 => b_read_reg_102(7),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[7]_i_1_n_0\
);
\p_s_reg_45[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(8),
I1 => b_read_reg_102(8),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[8]_i_1_n_0\
);
\p_s_reg_45[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => b_assign_reg_126(9),
I1 => b_read_reg_102(9),
I2 => ap_CS_fsm_state4,
O => \p_s_reg_45[9]_i_1_n_0\
);
\p_s_reg_45_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[0]_i_1_n_0\,
Q => p_s_reg_45(0),
R => '0'
);
\p_s_reg_45_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[10]_i_1_n_0\,
Q => p_s_reg_45(10),
R => '0'
);
\p_s_reg_45_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[11]_i_1_n_0\,
Q => p_s_reg_45(11),
R => '0'
);
\p_s_reg_45_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[12]_i_1_n_0\,
Q => p_s_reg_45(12),
R => '0'
);
\p_s_reg_45_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[13]_i_1_n_0\,
Q => p_s_reg_45(13),
R => '0'
);
\p_s_reg_45_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[14]_i_1_n_0\,
Q => p_s_reg_45(14),
R => '0'
);
\p_s_reg_45_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[15]_i_2_n_0\,
Q => p_s_reg_45(15),
R => '0'
);
\p_s_reg_45_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[1]_i_1_n_0\,
Q => p_s_reg_45(1),
R => '0'
);
\p_s_reg_45_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[2]_i_1_n_0\,
Q => p_s_reg_45(2),
R => '0'
);
\p_s_reg_45_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[3]_i_1_n_0\,
Q => p_s_reg_45(3),
R => '0'
);
\p_s_reg_45_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[4]_i_1_n_0\,
Q => p_s_reg_45(4),
R => '0'
);
\p_s_reg_45_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[5]_i_1_n_0\,
Q => p_s_reg_45(5),
R => '0'
);
\p_s_reg_45_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[6]_i_1_n_0\,
Q => p_s_reg_45(6),
R => '0'
);
\p_s_reg_45_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[7]_i_1_n_0\,
Q => p_s_reg_45(7),
R => '0'
);
\p_s_reg_45_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[8]_i_1_n_0\,
Q => p_s_reg_45(8),
R => '0'
);
\p_s_reg_45_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \p_s_reg_45[15]_i_1_n_0\,
D => \p_s_reg_45[9]_i_1_n_0\,
Q => p_s_reg_45(9),
R => '0'
);
\result_reg_56[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(0),
I1 => a_read_reg_107(0),
I2 => ap_CS_fsm_state4,
O => p_1_in(0)
);
\result_reg_56[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(10),
I1 => a_read_reg_107(10),
I2 => ap_CS_fsm_state4,
O => p_1_in(10)
);
\result_reg_56[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(11),
I1 => a_read_reg_107(11),
I2 => ap_CS_fsm_state4,
O => p_1_in(11)
);
\result_reg_56[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(12),
I1 => a_read_reg_107(12),
I2 => ap_CS_fsm_state4,
O => p_1_in(12)
);
\result_reg_56[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(13),
I1 => a_read_reg_107(13),
I2 => ap_CS_fsm_state4,
O => p_1_in(13)
);
\result_reg_56[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(14),
I1 => a_read_reg_107(14),
I2 => ap_CS_fsm_state4,
O => p_1_in(14)
);
\result_reg_56[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => tmp_3_reg_115,
I1 => ap_CS_fsm_state4,
I2 => ap_CS_fsm_state2,
O => \result_reg_56[15]_i_1_n_0\
);
\result_reg_56[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(15),
I1 => a_read_reg_107(15),
I2 => ap_CS_fsm_state4,
O => p_1_in(15)
);
\result_reg_56[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(1),
I1 => a_read_reg_107(1),
I2 => ap_CS_fsm_state4,
O => p_1_in(1)
);
\result_reg_56[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(2),
I1 => a_read_reg_107(2),
I2 => ap_CS_fsm_state4,
O => p_1_in(2)
);
\result_reg_56[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(3),
I1 => a_read_reg_107(3),
I2 => ap_CS_fsm_state4,
O => p_1_in(3)
);
\result_reg_56[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(4),
I1 => a_read_reg_107(4),
I2 => ap_CS_fsm_state4,
O => p_1_in(4)
);
\result_reg_56[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(5),
I1 => a_read_reg_107(5),
I2 => ap_CS_fsm_state4,
O => p_1_in(5)
);
\result_reg_56[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(6),
I1 => a_read_reg_107(6),
I2 => ap_CS_fsm_state4,
O => p_1_in(6)
);
\result_reg_56[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(7),
I1 => a_read_reg_107(7),
I2 => ap_CS_fsm_state4,
O => p_1_in(7)
);
\result_reg_56[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(8),
I1 => a_read_reg_107(8),
I2 => ap_CS_fsm_state4,
O => p_1_in(8)
);
\result_reg_56[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => a_assign_reg_121(9),
I1 => a_read_reg_107(9),
I2 => ap_CS_fsm_state4,
O => p_1_in(9)
);
\result_reg_56_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(0),
Q => result_reg_56(0),
R => '0'
);
\result_reg_56_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(10),
Q => result_reg_56(10),
R => '0'
);
\result_reg_56_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(11),
Q => result_reg_56(11),
R => '0'
);
\result_reg_56_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(12),
Q => result_reg_56(12),
R => '0'
);
\result_reg_56_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(13),
Q => result_reg_56(13),
R => '0'
);
\result_reg_56_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(14),
Q => result_reg_56(14),
R => '0'
);
\result_reg_56_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(15),
Q => result_reg_56(15),
R => '0'
);
\result_reg_56_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(1),
Q => result_reg_56(1),
R => '0'
);
\result_reg_56_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(2),
Q => result_reg_56(2),
R => '0'
);
\result_reg_56_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(3),
Q => result_reg_56(3),
R => '0'
);
\result_reg_56_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(4),
Q => result_reg_56(4),
R => '0'
);
\result_reg_56_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(5),
Q => result_reg_56(5),
R => '0'
);
\result_reg_56_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(6),
Q => result_reg_56(6),
R => '0'
);
\result_reg_56_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(7),
Q => result_reg_56(7),
R => '0'
);
\result_reg_56_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(8),
Q => result_reg_56(8),
R => '0'
);
\result_reg_56_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => \result_reg_56[15]_i_1_n_0\,
D => p_1_in(9),
Q => result_reg_56(9),
R => '0'
);
\tmp_3_reg_115[0]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(8),
I1 => p_s_reg_45(8),
I2 => result_reg_56(9),
I3 => p_s_reg_45(9),
O => \tmp_3_reg_115[0]_i_10_n_0\
);
\tmp_3_reg_115[0]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(6),
I1 => p_s_reg_45(6),
I2 => p_s_reg_45(7),
I3 => result_reg_56(7),
O => \tmp_3_reg_115[0]_i_11_n_0\
);
\tmp_3_reg_115[0]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(4),
I1 => p_s_reg_45(4),
I2 => p_s_reg_45(5),
I3 => result_reg_56(5),
O => \tmp_3_reg_115[0]_i_12_n_0\
);
\tmp_3_reg_115[0]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(2),
I1 => p_s_reg_45(2),
I2 => p_s_reg_45(3),
I3 => result_reg_56(3),
O => \tmp_3_reg_115[0]_i_13_n_0\
);
\tmp_3_reg_115[0]_i_14\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(0),
I1 => p_s_reg_45(0),
I2 => p_s_reg_45(1),
I3 => result_reg_56(1),
O => \tmp_3_reg_115[0]_i_14_n_0\
);
\tmp_3_reg_115[0]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(6),
I1 => p_s_reg_45(6),
I2 => result_reg_56(7),
I3 => p_s_reg_45(7),
O => \tmp_3_reg_115[0]_i_15_n_0\
);
\tmp_3_reg_115[0]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(4),
I1 => p_s_reg_45(4),
I2 => result_reg_56(5),
I3 => p_s_reg_45(5),
O => \tmp_3_reg_115[0]_i_16_n_0\
);
\tmp_3_reg_115[0]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(2),
I1 => p_s_reg_45(2),
I2 => result_reg_56(3),
I3 => p_s_reg_45(3),
O => \tmp_3_reg_115[0]_i_17_n_0\
);
\tmp_3_reg_115[0]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(0),
I1 => p_s_reg_45(0),
I2 => result_reg_56(1),
I3 => p_s_reg_45(1),
O => \tmp_3_reg_115[0]_i_18_n_0\
);
\tmp_3_reg_115[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(14),
I1 => p_s_reg_45(14),
I2 => result_reg_56(15),
I3 => p_s_reg_45(15),
O => \tmp_3_reg_115[0]_i_3_n_0\
);
\tmp_3_reg_115[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(12),
I1 => p_s_reg_45(12),
I2 => p_s_reg_45(13),
I3 => result_reg_56(13),
O => \tmp_3_reg_115[0]_i_4_n_0\
);
\tmp_3_reg_115[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(10),
I1 => p_s_reg_45(10),
I2 => p_s_reg_45(11),
I3 => result_reg_56(11),
O => \tmp_3_reg_115[0]_i_5_n_0\
);
\tmp_3_reg_115[0]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => result_reg_56(8),
I1 => p_s_reg_45(8),
I2 => p_s_reg_45(9),
I3 => result_reg_56(9),
O => \tmp_3_reg_115[0]_i_6_n_0\
);
\tmp_3_reg_115[0]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(14),
I1 => p_s_reg_45(14),
I2 => p_s_reg_45(15),
I3 => result_reg_56(15),
O => \tmp_3_reg_115[0]_i_7_n_0\
);
\tmp_3_reg_115[0]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(12),
I1 => p_s_reg_45(12),
I2 => result_reg_56(13),
I3 => p_s_reg_45(13),
O => \tmp_3_reg_115[0]_i_8_n_0\
);
\tmp_3_reg_115[0]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => result_reg_56(10),
I1 => p_s_reg_45(10),
I2 => result_reg_56(11),
I3 => p_s_reg_45(11),
O => \tmp_3_reg_115[0]_i_9_n_0\
);
\tmp_3_reg_115_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => a_assign_reg_1210,
D => tmp_3_fu_72_p2,
Q => tmp_3_reg_115,
R => '0'
);
\tmp_3_reg_115_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \tmp_3_reg_115_reg[0]_i_2_n_0\,
CO(3) => tmp_3_fu_72_p2,
CO(2) => \tmp_3_reg_115_reg[0]_i_1_n_1\,
CO(1) => \tmp_3_reg_115_reg[0]_i_1_n_2\,
CO(0) => \tmp_3_reg_115_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \tmp_3_reg_115[0]_i_3_n_0\,
DI(2) => \tmp_3_reg_115[0]_i_4_n_0\,
DI(1) => \tmp_3_reg_115[0]_i_5_n_0\,
DI(0) => \tmp_3_reg_115[0]_i_6_n_0\,
O(3 downto 0) => \NLW_tmp_3_reg_115_reg[0]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \tmp_3_reg_115[0]_i_7_n_0\,
S(2) => \tmp_3_reg_115[0]_i_8_n_0\,
S(1) => \tmp_3_reg_115[0]_i_9_n_0\,
S(0) => \tmp_3_reg_115[0]_i_10_n_0\
);
\tmp_3_reg_115_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \tmp_3_reg_115_reg[0]_i_2_n_0\,
CO(2) => \tmp_3_reg_115_reg[0]_i_2_n_1\,
CO(1) => \tmp_3_reg_115_reg[0]_i_2_n_2\,
CO(0) => \tmp_3_reg_115_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \tmp_3_reg_115[0]_i_11_n_0\,
DI(2) => \tmp_3_reg_115[0]_i_12_n_0\,
DI(1) => \tmp_3_reg_115[0]_i_13_n_0\,
DI(0) => \tmp_3_reg_115[0]_i_14_n_0\,
O(3 downto 0) => \NLW_tmp_3_reg_115_reg[0]_i_2_O_UNCONNECTED\(3 downto 0),
S(3) => \tmp_3_reg_115[0]_i_15_n_0\,
S(2) => \tmp_3_reg_115[0]_i_16_n_0\,
S(1) => \tmp_3_reg_115[0]_i_17_n_0\,
S(0) => \tmp_3_reg_115[0]_i_18_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_gcd_bus_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_gcd_bus_AWVALID : in STD_LOGIC;
s_axi_gcd_bus_AWREADY : out STD_LOGIC;
s_axi_gcd_bus_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_gcd_bus_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_gcd_bus_WVALID : in STD_LOGIC;
s_axi_gcd_bus_WREADY : out STD_LOGIC;
s_axi_gcd_bus_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_gcd_bus_BVALID : out STD_LOGIC;
s_axi_gcd_bus_BREADY : in STD_LOGIC;
s_axi_gcd_bus_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_gcd_bus_ARVALID : in STD_LOGIC;
s_axi_gcd_bus_ARREADY : out STD_LOGIC;
s_axi_gcd_bus_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_gcd_bus_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_gcd_bus_RVALID : out STD_LOGIC;
s_axi_gcd_bus_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
interrupt : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd_block_design_gcd_0_1,gcd,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute IP_DEFINITION_SOURCE : string;
attribute IP_DEFINITION_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "HLS";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd,Vivado 2018.2";
attribute hls_module : string;
attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_GCD_BUS_ADDR_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_ADDR_WIDTH of inst : label is 6;
attribute C_S_AXI_GCD_BUS_DATA_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH : integer;
attribute C_S_AXI_GCD_BUS_WSTRB_WIDTH of inst : label is 4;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of inst : label is 4;
attribute ap_ST_fsm_state1 : string;
attribute ap_ST_fsm_state1 of inst : label is "4'b0001";
attribute ap_ST_fsm_state2 : string;
attribute ap_ST_fsm_state2 of inst : label is "4'b0010";
attribute ap_ST_fsm_state3 : string;
attribute ap_ST_fsm_state3 of inst : label is "4'b0100";
attribute ap_ST_fsm_state4 : string;
attribute ap_ST_fsm_state4 of inst : label is "4'b1000";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of ap_clk : signal is "xilinx.com:signal:clock:1.0 ap_clk CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of ap_clk : signal is "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_gcd_bus, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0";
attribute X_INTERFACE_INFO of ap_rst_n : signal is "xilinx.com:signal:reset:1.0 ap_rst_n RST";
attribute X_INTERFACE_PARAMETER of ap_rst_n : signal is "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}";
attribute X_INTERFACE_INFO of interrupt : signal is "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
attribute X_INTERFACE_PARAMETER of interrupt : signal is "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARREADY";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWREADY";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BREADY";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_gcd_bus_RREADY : signal is "XIL_INTERFACENAME s_axi_gcd_bus, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WREADY";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WVALID";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARADDR";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWADDR";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BRESP";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RDATA";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RRESP";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WDATA";
attribute X_INTERFACE_INFO of s_axi_gcd_bus_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WSTRB";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gcd
port map (
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
s_axi_gcd_bus_ARADDR(5 downto 0) => s_axi_gcd_bus_ARADDR(5 downto 0),
s_axi_gcd_bus_ARREADY => s_axi_gcd_bus_ARREADY,
s_axi_gcd_bus_ARVALID => s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_AWADDR(5 downto 0) => s_axi_gcd_bus_AWADDR(5 downto 0),
s_axi_gcd_bus_AWREADY => s_axi_gcd_bus_AWREADY,
s_axi_gcd_bus_AWVALID => s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_BREADY => s_axi_gcd_bus_BREADY,
s_axi_gcd_bus_BRESP(1 downto 0) => s_axi_gcd_bus_BRESP(1 downto 0),
s_axi_gcd_bus_BVALID => s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_RDATA(31 downto 0) => s_axi_gcd_bus_RDATA(31 downto 0),
s_axi_gcd_bus_RREADY => s_axi_gcd_bus_RREADY,
s_axi_gcd_bus_RRESP(1 downto 0) => s_axi_gcd_bus_RRESP(1 downto 0),
s_axi_gcd_bus_RVALID => s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_WDATA(31 downto 0) => s_axi_gcd_bus_WDATA(31 downto 0),
s_axi_gcd_bus_WREADY => s_axi_gcd_bus_WREADY,
s_axi_gcd_bus_WSTRB(3 downto 0) => s_axi_gcd_bus_WSTRB(3 downto 0),
s_axi_gcd_bus_WVALID => s_axi_gcd_bus_WVALID
);
end STRUCTURE;
|
-- $Id: bpgenlib.vhd 534 2013-09-22 21:37:24Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: bpgenlib
-- Description: Generic Board/Part components
--
-- Dependencies: -
-- Tool versions: 12.1, 13.3; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-09-21 534 1.1.1 add bp_rs232_4l4l_iob
-- 2013-01-26 476 1.1 moved rbus depended components to bpgenrbuslib
-- 2013-01-06 472 1.0.7 add sn_humanio_demu_rbus
-- 2011-11-16 426 1.0.6 now numeric_std clean
-- 2011-10-10 413 1.0.5 add sn_humanio_demu
-- 2011-08-07 404 1.0.4 add RELAY generic for bp_rs232_2l4l_iob
-- 2011-08-06 403 1.0.3 add RESET port for bp_rs232_2l4l_iob
-- 2011-07-09 391 1.0.2 move in bp_rs232_2l4l_iob from s3boardlib
-- 2011-07-08 390 1.0.1 move in sn_(4x7segctl|humanio*) from s3boardlib
-- 2011-07-01 386 1.0 Initial version (with rs232_iob's and bp_swibtnled)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
package bpgenlib is
component bp_rs232_2line_iob is -- iob's for 2 line rs232 (RXD,TXD)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit -- pad-o: transmit data (board view)
);
end component;
component bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit; -- pad-o: transmit data (board view)
I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
O_RTS_N : out slbit -- pad-o: request to send (act. low)
);
end component;
component bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end component;
component bp_rs232_4l4l_iob is -- iob's for dual 4l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_CTS0_N : in slbit; -- pad-i: p0: clear to send (act. low)
O_RTS0_N : out slbit; -- pad-o: p0: request to send (act. low)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end component;
component bp_swibtnled is -- generic SWI, BTN and LED handling
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end component;
component sn_4x7segctl is -- Quad 7 segment display controller
generic (
CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
port (
CLK : in slbit; -- clock
DIN : in slv16; -- data
DP : in slv4; -- decimal points
ANO_N : out slv4; -- anodes (act.low)
SEG_N : out slv8 -- segements (act.low)
);
end component;
component sn_humanio is -- human i/o handling: swi,btn,led,dsp
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end component;
component sn_humanio_demu is -- human i/o handling: swi,btn,led only
generic (
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end component;
end package bpgenlib;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @details Implementation of the axictrl device.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library ambalib;
use ambalib.types_amba4.all;
--! @brief AXI (NASTI) bus controller.
--! @details Simplified version with the hardcoded priorities to bus access.
--! Lower master index has a higher priority.
--! @todo Round-robin algorithm for the master selection.
entity axictrl is
generic (
rdslave_with_waitstate : boolean := false
);
port (
clk : in std_logic;
nrst : in std_logic;
slvoi : in nasti_slaves_out_vector;
mstoi : in nasti_master_out_vector;
slvio : out nasti_slave_in_type;
mstio : out nasti_master_in_type
);
end;
architecture arch_axictrl of axictrl is
constant MSTZERO : std_logic_vector(CFG_NASTI_MASTER_TOTAL-1 downto 0) := (others => '0');
type reg_type is record
mstidx : integer range 0 to CFG_NASTI_MASTER_TOTAL-1;
mstsel : std_logic_vector(CFG_NASTI_MASTER_TOTAL-1 downto 0);
cur_slave : nasti_slave_out_type; -- 1 clock wait state
end record;
signal rin, r : reg_type;
begin
comblogic : process(mstoi, slvoi, r)
variable v : reg_type;
variable busreq : std_logic;
variable mstsel : std_logic_vector(CFG_NASTI_MASTER_TOTAL-1 downto 0);
variable n, mstidx, mstidx_cur : integer range 0 to CFG_NASTI_MASTER_TOTAL-1;
variable cur_master : nasti_master_out_type;
variable cur_slave : nasti_slave_out_type;
variable busy : std_logic;
begin
v := r;
mstsel := r.mstsel;
busreq := '0';
mstidx := 0;
v.cur_slave := nasti_slave_out_none;
cur_master := nasti_master_out_none;
-- Select master bus:
for n in 0 to CFG_NASTI_MASTER_TOTAL-1 loop
if (mstoi(n).ar_valid or mstoi(n).aw_valid) = '1' then
mstidx := n;
busreq := '1';
end if;
cur_master.b_ready := cur_master.b_ready or mstoi(n).b_ready;
cur_master.r_ready := cur_master.r_ready or mstoi(n).r_ready;
end loop;
busy := mstoi(r.mstidx).w_valid or mstoi(r.mstidx).r_ready;
if (r.mstsel = MSTZERO) or ((busreq and not busy) = '1') then
mstsel(r.mstidx) := '0';
mstsel(mstidx) := busreq;
v.mstidx := mstidx;
mstidx_cur := mstidx;
else
mstidx_cur := r.mstidx;
end if;
if mstoi(mstidx_cur).aw_valid = '1' then
cur_master.aw_valid := mstoi(mstidx_cur).aw_valid;
cur_master.aw_bits := mstoi(mstidx_cur).aw_bits;
cur_master.aw_id := mstoi(mstidx_cur).aw_id;
cur_master.aw_user := mstoi(mstidx_cur).aw_user;
end if;
if mstoi(mstidx_cur).w_valid = '1' then
cur_master.w_valid := mstoi(mstidx_cur).w_valid;
cur_master.w_data := mstoi(mstidx_cur).w_data;
cur_master.w_last := mstoi(mstidx_cur).w_last;
cur_master.w_strb := mstoi(mstidx_cur).w_strb;
cur_master.w_user := mstoi(mstidx_cur).w_user;
end if;
if mstoi(mstidx_cur).ar_valid = '1' then
cur_master.ar_valid := mstoi(mstidx_cur).ar_valid;
cur_master.ar_bits := mstoi(mstidx_cur).ar_bits;
cur_master.ar_id := mstoi(mstidx_cur).ar_id;
cur_master.ar_user := mstoi(mstidx_cur).ar_user;
end if;
-- Select slave bus:
for n in 0 to CFG_NASTI_SLAVES_TOTAL-1 loop
v.cur_slave.ar_ready := v.cur_slave.ar_ready or slvoi(n).ar_ready;
v.cur_slave.aw_ready := v.cur_slave.aw_ready or slvoi(n).aw_ready;
v.cur_slave.w_ready := v.cur_slave.w_ready or slvoi(n).w_ready;
if v.cur_slave.b_valid = '0' and slvoi(n).b_valid = '1' then
v.cur_slave.b_valid := '1';
v.cur_slave.b_resp := slvoi(n).b_resp;
v.cur_slave.b_id := slvoi(n).b_id;
v.cur_slave.b_user := slvoi(n).b_user;
end if;
if v.cur_slave.r_valid = '0' and slvoi(n).r_valid = '1' then
v.cur_slave.r_valid := '1';
v.cur_slave.r_resp := slvoi(n).r_resp;
v.cur_slave.r_data := slvoi(n).r_data;
v.cur_slave.r_last := slvoi(n).r_last;
v.cur_slave.r_id := slvoi(n).r_id;
v.cur_slave.r_user := slvoi(n).r_user;
end if;
end loop;
v.mstsel := mstsel;
if rdslave_with_waitstate then
cur_slave := r.cur_slave;
else
cur_slave := v.cur_slave;
end if;
rin <= v;
mstio.grant <= mstsel;
mstio.aw_ready <= cur_slave.aw_ready;
mstio.w_ready <= cur_slave.w_ready;
mstio.b_valid <= cur_slave.b_valid;
mstio.b_resp <= cur_slave.b_resp;
mstio.b_id <= cur_slave.b_id;
mstio.b_user <= cur_slave.b_user;
mstio.ar_ready <= cur_slave.ar_ready;
mstio.r_valid <= cur_slave.r_valid;
mstio.r_resp <= cur_slave.r_resp;
mstio.r_data <= cur_slave.r_data;
mstio.r_last <= cur_slave.r_last;
mstio.r_id <= cur_slave.r_id;
mstio.r_user <= cur_slave.r_user;
slvio.aw_valid <= cur_master.aw_valid;
slvio.aw_bits <= cur_master.aw_bits;
slvio.aw_id <= cur_master.aw_id;
slvio.aw_user <= cur_master.aw_user;
slvio.w_valid <= cur_master.w_valid;
slvio.w_data <= cur_master.w_data;
slvio.w_last <= cur_master.w_last;
slvio.w_strb <= cur_master.w_strb;
slvio.w_user <= cur_master.w_user;
slvio.b_ready <= cur_master.b_ready;
slvio.ar_valid <= cur_master.ar_valid;
slvio.ar_bits <= cur_master.ar_bits;
slvio.ar_id <= cur_master.ar_id;
slvio.ar_user <= cur_master.ar_user;
slvio.r_ready <= cur_master.r_ready;
end process;
reg0 : process(clk, nrst) begin
if nrst = '0' then
r.mstidx <= 0;
r.mstsel <= (others =>'0');
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @details Implementation of the axictrl device.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library ambalib;
use ambalib.types_amba4.all;
--! @brief AXI (NASTI) bus controller.
--! @details Simplified version with the hardcoded priorities to bus access.
--! Lower master index has a higher priority.
--! @todo Round-robin algorithm for the master selection.
entity axictrl is
generic (
rdslave_with_waitstate : boolean := false
);
port (
clk : in std_logic;
nrst : in std_logic;
slvoi : in nasti_slaves_out_vector;
mstoi : in nasti_master_out_vector;
slvio : out nasti_slave_in_type;
mstio : out nasti_master_in_type
);
end;
architecture arch_axictrl of axictrl is
constant MSTZERO : std_logic_vector(CFG_NASTI_MASTER_TOTAL-1 downto 0) := (others => '0');
type reg_type is record
mstidx : integer range 0 to CFG_NASTI_MASTER_TOTAL-1;
mstsel : std_logic_vector(CFG_NASTI_MASTER_TOTAL-1 downto 0);
cur_slave : nasti_slave_out_type; -- 1 clock wait state
end record;
signal rin, r : reg_type;
begin
comblogic : process(mstoi, slvoi, r)
variable v : reg_type;
variable busreq : std_logic;
variable mstsel : std_logic_vector(CFG_NASTI_MASTER_TOTAL-1 downto 0);
variable n, mstidx, mstidx_cur : integer range 0 to CFG_NASTI_MASTER_TOTAL-1;
variable cur_master : nasti_master_out_type;
variable cur_slave : nasti_slave_out_type;
variable busy : std_logic;
begin
v := r;
mstsel := r.mstsel;
busreq := '0';
mstidx := 0;
v.cur_slave := nasti_slave_out_none;
cur_master := nasti_master_out_none;
-- Select master bus:
for n in 0 to CFG_NASTI_MASTER_TOTAL-1 loop
if (mstoi(n).ar_valid or mstoi(n).aw_valid) = '1' then
mstidx := n;
busreq := '1';
end if;
cur_master.b_ready := cur_master.b_ready or mstoi(n).b_ready;
cur_master.r_ready := cur_master.r_ready or mstoi(n).r_ready;
end loop;
busy := mstoi(r.mstidx).w_valid or mstoi(r.mstidx).r_ready;
if (r.mstsel = MSTZERO) or ((busreq and not busy) = '1') then
mstsel(r.mstidx) := '0';
mstsel(mstidx) := busreq;
v.mstidx := mstidx;
mstidx_cur := mstidx;
else
mstidx_cur := r.mstidx;
end if;
if mstoi(mstidx_cur).aw_valid = '1' then
cur_master.aw_valid := mstoi(mstidx_cur).aw_valid;
cur_master.aw_bits := mstoi(mstidx_cur).aw_bits;
cur_master.aw_id := mstoi(mstidx_cur).aw_id;
cur_master.aw_user := mstoi(mstidx_cur).aw_user;
end if;
if mstoi(mstidx_cur).w_valid = '1' then
cur_master.w_valid := mstoi(mstidx_cur).w_valid;
cur_master.w_data := mstoi(mstidx_cur).w_data;
cur_master.w_last := mstoi(mstidx_cur).w_last;
cur_master.w_strb := mstoi(mstidx_cur).w_strb;
cur_master.w_user := mstoi(mstidx_cur).w_user;
end if;
if mstoi(mstidx_cur).ar_valid = '1' then
cur_master.ar_valid := mstoi(mstidx_cur).ar_valid;
cur_master.ar_bits := mstoi(mstidx_cur).ar_bits;
cur_master.ar_id := mstoi(mstidx_cur).ar_id;
cur_master.ar_user := mstoi(mstidx_cur).ar_user;
end if;
-- Select slave bus:
for n in 0 to CFG_NASTI_SLAVES_TOTAL-1 loop
v.cur_slave.ar_ready := v.cur_slave.ar_ready or slvoi(n).ar_ready;
v.cur_slave.aw_ready := v.cur_slave.aw_ready or slvoi(n).aw_ready;
v.cur_slave.w_ready := v.cur_slave.w_ready or slvoi(n).w_ready;
if v.cur_slave.b_valid = '0' and slvoi(n).b_valid = '1' then
v.cur_slave.b_valid := '1';
v.cur_slave.b_resp := slvoi(n).b_resp;
v.cur_slave.b_id := slvoi(n).b_id;
v.cur_slave.b_user := slvoi(n).b_user;
end if;
if v.cur_slave.r_valid = '0' and slvoi(n).r_valid = '1' then
v.cur_slave.r_valid := '1';
v.cur_slave.r_resp := slvoi(n).r_resp;
v.cur_slave.r_data := slvoi(n).r_data;
v.cur_slave.r_last := slvoi(n).r_last;
v.cur_slave.r_id := slvoi(n).r_id;
v.cur_slave.r_user := slvoi(n).r_user;
end if;
end loop;
v.mstsel := mstsel;
if rdslave_with_waitstate then
cur_slave := r.cur_slave;
else
cur_slave := v.cur_slave;
end if;
rin <= v;
mstio.grant <= mstsel;
mstio.aw_ready <= cur_slave.aw_ready;
mstio.w_ready <= cur_slave.w_ready;
mstio.b_valid <= cur_slave.b_valid;
mstio.b_resp <= cur_slave.b_resp;
mstio.b_id <= cur_slave.b_id;
mstio.b_user <= cur_slave.b_user;
mstio.ar_ready <= cur_slave.ar_ready;
mstio.r_valid <= cur_slave.r_valid;
mstio.r_resp <= cur_slave.r_resp;
mstio.r_data <= cur_slave.r_data;
mstio.r_last <= cur_slave.r_last;
mstio.r_id <= cur_slave.r_id;
mstio.r_user <= cur_slave.r_user;
slvio.aw_valid <= cur_master.aw_valid;
slvio.aw_bits <= cur_master.aw_bits;
slvio.aw_id <= cur_master.aw_id;
slvio.aw_user <= cur_master.aw_user;
slvio.w_valid <= cur_master.w_valid;
slvio.w_data <= cur_master.w_data;
slvio.w_last <= cur_master.w_last;
slvio.w_strb <= cur_master.w_strb;
slvio.w_user <= cur_master.w_user;
slvio.b_ready <= cur_master.b_ready;
slvio.ar_valid <= cur_master.ar_valid;
slvio.ar_bits <= cur_master.ar_bits;
slvio.ar_id <= cur_master.ar_id;
slvio.ar_user <= cur_master.ar_user;
slvio.r_ready <= cur_master.r_ready;
end process;
reg0 : process(clk, nrst) begin
if nrst = '0' then
r.mstidx <= 0;
r.mstsel <= (others =>'0');
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2877.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p06n05i02877ent IS
-- Failure_here
function "an" & "d" return BOOLEAN;
END c02s01b00x00p06n05i02877ent;
ARCHITECTURE c02s01b00x00p06n05i02877arch OF c02s01b00x00p06n05i02877ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b00x00p06n05i02877 - Illegal function designator."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p06n05i02877arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2877.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p06n05i02877ent IS
-- Failure_here
function "an" & "d" return BOOLEAN;
END c02s01b00x00p06n05i02877ent;
ARCHITECTURE c02s01b00x00p06n05i02877arch OF c02s01b00x00p06n05i02877ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b00x00p06n05i02877 - Illegal function designator."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p06n05i02877arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2877.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p06n05i02877ent IS
-- Failure_here
function "an" & "d" return BOOLEAN;
END c02s01b00x00p06n05i02877ent;
ARCHITECTURE c02s01b00x00p06n05i02877arch OF c02s01b00x00p06n05i02877ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b00x00p06n05i02877 - Illegal function designator."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p06n05i02877arch;
|
--------------------------------------------------------------------------------
-- Testbench - gf2m multiplier
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 18.08.2017
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
use ieee.math_real.all; -- FOR UNIFORM, TRUNC
USE std.textio.ALL;
use work.tld_ecdsa_package.all;
ENTITY tb_gf2m_multiplier IS
END tb_gf2m_multiplier;
ARCHITECTURE behavior OF tb_gf2m_multiplier IS
-- Import entity e_gf2m_interleaved_multiplier
COMPONENT e_gf2m_interleaved_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0) := ONE(M-1 DOWNTO 0)
);
PORT (
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
a_i: IN std_logic_vector (M-1 DOWNTO 0);
b_i: IN std_logic_vector (M-1 DOWNTO 0);
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL a : std_logic_vector(m-1 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(m-1 downto 0) := (others=>'0');
SIGNAL clk, rst, enable: std_logic;
--Outputs
SIGNAL z : std_logic_vector(m-1 downto 0);
SIGNAL done: std_logic;
constant PERIOD : time := 200 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 0 ns;
BEGIN
-- Instantiate multiplier
uut: e_gf2m_interleaved_multiplier GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP(
clk_i => clk,
rst_i => rst,
enable_i => enable,
a_i => a,
b_i => b,
z_o => z,
ready_o => done
);
-- Clock process for clk
PROCESS
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD *(1.0 - DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
-- Start test cases
tb : PROCESS
-- Internal signals
VARIABLE TX_LOC : LINE;
VARIABLE TX_STR : String(1 TO 4096);
BEGIN
-- Disable computation and reset all entities
enable <= '0';
rst <= '1';
WAIT FOR PERIOD;
rst <= '0';
WAIT FOR PERIOD;
-- Test #1:
a <= "000000010";
b <= "000001111";
enable <= '1';
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL (done = '1');
IF ( z /= "000011110" ) THEN
write(TX_LOC,string'("TEST #1 ERROR!!! 000011110 != 000000010 * 000001111"));
write(TX_LOC, string'(" )"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
END IF;
WAIT FOR 2*PERIOD;
-- Test #2:
a <= "000000000";
b <= "101010101";
enable <= '1';
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL (done = '1');
IF ( z /= "000000000" ) THEN
write(TX_LOC,string'("TEST #2 ERROR!!! 000000000 != 000000000 * 101010101"));
write(TX_LOC, string'(" )"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
END IF;
WAIT FOR 2*PERIOD;
-- Test #3:
a <= "011011100";
b <= "000000000";
enable <= '1';
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL (done = '1');
IF ( z /= "000000000" ) THEN
write(TX_LOC,string'("TEST #3 ERROR!!! 000000000 != 011011100 * 000000000"));
write(TX_LOC, string'(" )"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
END IF;
WAIT FOR 2*PERIOD;
-- Test #4:
a <= "011011010";
b <= "000111010";
enable <= '1';
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL (done = '1');
IF ( z /= "110011100" ) THEN
write(TX_LOC,string'("TEST #4 ERROR!!! 110011100 != 011011010 * 000111010"));
write(TX_LOC, string'(" )"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
END IF;
WAIT FOR 2*PERIOD;
ASSERT (FALSE) REPORT
"Simulation successful!"
SEVERITY FAILURE;
END PROCESS;
END; |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_05.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture abstract of adder is
begin
add_a_b : process (a, b) is
begin
sum <= a + b;
end process add_a_b;
end architecture abstract;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_05.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture abstract of adder is
begin
add_a_b : process (a, b) is
begin
sum <= a + b;
end process add_a_b;
end architecture abstract;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_05.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture abstract of adder is
begin
add_a_b : process (a, b) is
begin
sum <= a + b;
end process add_a_b;
end architecture abstract;
|
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end CASE;
end process PROC_2;
PROC_3 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end Case;
end process PROC_3;
end architecture ARCH;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clockport is
Port( -- clockport signals
data : inout STD_LOGIC_VECTOR (7 downto 0); -- data pins
addressIn : in STD_LOGIC_VECTOR (3 downto 0); -- address pins
iord : in STD_LOGIC; -- active low when read from device to CPU
iowr : in STD_LOGIC; -- active low when write from CPU to device
cs : in STD_LOGIC;
-- debug signals
--addressOut : out STD_LOGIC_VECTOR (3 downto 0);
-- registers used to exchange data
btnReg : in STD_LOGIC_VECTOR (7 downto 0);
ledReg : out STD_LOGIC_VECTOR (3 downto 0);
testOut : out STD_LOGIC_VECTOR (7 downto 0);
commDataInReg : in STD_LOGIC_VECTOR (7 downto 0);
commDataOutReg : out STD_LOGIC_VECTOR (7 downto 0)
);
end clockport;
architecture Behavioral of clockport is
signal address : STD_LOGIC_VECTOR (3 downto 0);
-- signal lastID : STD_LOGIC_VECTOR (7 downto 0) := "11000000";
-- signal currID : STD_LOGIC_VECTOR (7 downto 0);
begin
address <= addressIn when cs = '0' and (iord = '0' or iowr = '0');
--addressOut <= address;
--data <= "ZZZZZZZZ";
-- data <= btnReg & "0000" when (iord = '0' and cs = '0') and address = "0001" else
-- "00000001" when (iord = '0' and cs = '0') and address = "1111" else
-- -- somereg when (iord = '0' and cs = '0') AND address = "xxxxxxxx" else
-- "ZZZZZZZZ";
process (iord, cs, address, data)
begin
if iord = '0' and cs = '0' and address = "0000" then -- reg 0, 0xD80001
data <= "11100111";
elsif iord = '0' and cs = '0' and address = "0001" then -- reg 1, 0xD80005
data <= commDataInReg;
elsif iord = '0' and cs = '0' and address = "0010" then -- reg 2, 0xD80009
data <= "00000010";
elsif iord = '0' and cs = '0' and address = "0100" then -- reg 4, 0xD80011
data <= "00000100";
elsif iord = '0' and cs = '0' and address = "1101" then
data <= btnReg;
else
data <= "ZZZZZZZZ";
end if;
end process;
process (iowr, cs, address, data)
begin
if iowr = '0' and cs = '0' and address = "0001" then
commDataOutReg <= data;
-- testOut <= data;
elsif iowr = '0' and cs = '0' and address = "1111" then
ledReg(0) <= data(0);
ledReg(1) <= data(1);
ledReg(2) <= data(2);
ledReg(3) <= data(3);
end if;
end process;
end Behavioral;
|
-- This filter produces a pole pair at +/-zp=sqrt(2^-shift_value) on the real axis
-- A shift register is used instead of a multiplier
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package real_pole_filter_shift_reg_pkg is
component real_pole_filter_shift_reg
generic(
data_width : integer;
internal_data_width : integer;
shift_value : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end real_pole_filter_shift_reg_pkg;
package body real_pole_filter_shift_reg_pkg is
end real_pole_filter_shift_reg_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.resize_tools_pkg.all;
entity real_pole_filter_shift_reg is
generic(
data_width : integer := 16;
internal_data_width : integer := 16;
shift_value : integer := 1
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end real_pole_filter_shift_reg;
architecture real_pole_filter_shift_reg_arch of real_pole_filter_shift_reg is
signal x_res : std_logic_vector(internal_data_width-1 downto 0);
signal xaydmb0 : std_logic_vector(internal_data_width-1 downto 0);
signal ydmb0 : std_logic_vector(internal_data_width-1 downto 0);
signal y : std_logic_vector (internal_data_width-1 downto 0);
signal yd : std_logic_vector (internal_data_width-1 downto 0);
begin
x_res <= resize_to_msb_round(data_i,internal_data_width);
xaydmb0 <= resize_to_msb_round(std_logic_vector(signed(x_res) + signed(ydmb0)),internal_data_width);
ydmb0 <= resize_to_msb_round(std_logic_vector(shift_right(signed(yd),shift_value)),internal_data_width);
process (clk_i, rst_i)
begin
if rst_i = '1' then
y <= (others => '0');
yd <= (others => '0');
data_str_o <= '0';
data_o <= (others => '0');
elsif clk_i'EVENT and clk_i = '1' then
data_str_o <= data_str_i;
data_o <= y;
if data_str_i='1' then
y <= xaydmb0;
yd <= y;
end if;
end if;
end process;
end real_pole_filter_shift_reg_arch;
|
-- predefined sequence
-- receiver
entity FRAME_CHECK is
port
(
-- User Interface
RX_DATA : in std_logic_vector(7 downto 0);
RX_CHAR_IS_K_IN : in std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
ERROR_COUNT : out std_logic_vector(7 downto 0)
);
--...
signal error : std_logic := '0';
signal STATE_i : std_logic_vector(3 downto 0);
attribute keep: string;
attribute keep of error : signal is "true";
attribute keep of rx_data_r : signal is "true";
--...
--We count the total number of errors we detect. By keeping a count we make it less likely that we will miss
--errors we did not directly observe. This counter must be reset when it reaches its max value
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(start_toggling_r = '0') then
error_count_r <= (others=>'0') after DLY;
elsif(error_detected_r='1') then
error_count_r <= error_count_r + 1 after DLY;
end if;
end if;
if (USER_CLK 'event and USER_CLK = '1') then
if (RX_CHAR_IS_K_IN = '0') then -- if it is not BC
if ((RX_DATA /= x"AA") and (RX_DATA /= x"55") and (RX_DATA /= x"0F") and (RX_DATA /= x"F0") and (RX_DATA /= x"CC") and (RX_DATA /= x"33") and (RX_DATA /= x"BC") and (RX_DATA /= x"F7")) then
error <= '1';
else
error <= '0';
end if;
end if;
end if;
end process;
-- transmitter
signal STATE_i : std_logic_vector(3 downto 0);
signal counter : std_logic_vector(31 downto 0);
--______________________________ Transmit Data __________________________________
--Assign TX_DATA to data register or align char based on the value
TX_DATA <= tx_d_r when (send_align_r='0') else
align_char_c;
TX_CHARISK <= tied_to_ground_i when (send_align_r='0') else
control_bits_c;
--Transmit data when send_align_r is de-asserted. Data is right shifted every cycle.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(RESET = '1') then
tx_d_r <= x"BC" after DLY;
counter <= x"00000000";
STATE_i <= x"0";
elsif (send_align_r = '0') then
if (STATE_i = x"0") then
STATE_i <= x"1";
tx_d_r <= x"F0";
else
case counter is
when x"00000000" => tx_d_r <= x"AA"; counter <= counter + x"00000001";
when x"00000001" => tx_d_r <= x"55"; counter <= counter + x"00000001";
when x"00000002" => tx_d_r <= x"0F"; counter <= counter + x"00000001";
when x"00000003" => tx_d_r <= x"CC"; counter <= counter + x"00000001";
when x"00000004" => tx_d_r <= x"F7"; counter <= counter + x"00000001";
when x"00000005" => tx_d_r <= x"F7"; counter <= counter + x"00000001";
when x"00000006" => tx_d_r <= x"33"; counter <= counter + x"00000001";
when x"00000007" => tx_d_r <= x"AA"; counter <= counter + x"00000001";
when x"00000008" => tx_d_r <= x"55"; counter <= counter + x"00000001";
when x"00000009" => tx_d_r <= x"0F"; counter <= counter + x"00000001";
when x"0000000A" => tx_d_r <= x"CC"; counter <= counter + x"00000001";
when x"0000000B" => tx_d_r <= x"F7"; counter <= counter + x"00000001";
when x"0000000C" => tx_d_r <= x"F7"; counter <= counter + x"00000001";
when x"0000000D" => tx_d_r <= x"33"; counter <= counter + x"00000001";
when others => tx_d_r <= x"F0"; counter <= x"00000000"; STATE_i <= x"0";
end case;
end if;
end if;
end if;
end process;
|
-------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_brams_s6.vhd
-- Description: BlockRAM module for Spartan-6 PCIe Block
--
-- Arranges and connects brams
-- Implements address decoding, datapath muxing and
-- pipeline stages
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pcie_brams_s6 is
generic (
-- the number of BRAMs to use
-- supported values are:
-- 1,2,4,9
NUM_BRAMS : integer := 0;
-- BRAM read address latency
--
-- value meaning
-- ====================================================
-- 0 BRAM read address port sample
-- 1 BRAM read address port sample and a pipeline stage on the address port
RAM_RADDR_LATENCY : integer := 1;
-- BRAM read data latency
--
-- value meaning
-- ====================================================
-- 1 no BRAM OREG
-- 2 use BRAM OREG
-- 3 use BRAM OREG and a pipeline stage on the data port
RAM_RDATA_LATENCY : integer := 1;
-- BRAM write latency
-- The BRAM write port is synchronous
--
-- value meaning
-- ====================================================
-- 0 BRAM write port sample
-- 1 BRAM write port sample plus pipeline stage
RAM_WRITE_LATENCY : integer := 1
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
wen : in std_logic;
waddr : in std_logic_vector(11 downto 0);
wdata : in std_logic_vector(35 downto 0);
ren : in std_logic;
rce : in std_logic;
raddr : in std_logic_vector(11 downto 0);
rdata : out std_logic_vector(35 downto 0)
);
end pcie_brams_s6;
architecture rtl of pcie_brams_s6 is
constant TCQ : time := 1 ns; -- Clock-to-out delay to be modeled
-- Turn on the bram output register
function CALC_DOB_REG(constant RAM_RDATA_LATENCY : in integer) return integer is
variable DOB_REG : integer;
begin
if (RAM_RDATA_LATENCY > 1) then DOB_REG := 1;
else DOB_REG := 0;
end if;
return DOB_REG;
end function CALC_DOB_REG;
-- Calculate the data width of the individual BRAMs
function CALC_WIDTH(constant NUM_BRAMS : in integer) return integer is
variable WIDTH : integer;
begin
if (NUM_BRAMS = 1) then WIDTH := 36;
elsif (NUM_BRAMS = 2) then WIDTH := 18;
elsif (NUM_BRAMS = 4) then WIDTH := 9;
else WIDTH := 4; -- NUM_BRAMS = 9
end if;
return WIDTH;
end function CALC_WIDTH;
component pcie_bram_s6 is
generic (
DOB_REG : integer;
WIDTH : integer
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
wen_i : in std_logic;
waddr_i : in std_logic_vector(11 downto 0);
wdata_i : in std_logic_vector(CALC_WIDTH(NUM_BRAMS)-1 downto 0);
ren_i : in std_logic;
rce_i : in std_logic;
raddr_i : in std_logic_vector(11 downto 0);
rdata_o : out std_logic_vector(CALC_WIDTH(NUM_BRAMS)-1 downto 0) -- read data
);
end component;
-- Model the delays for RAM write latency
signal wen_int : std_logic;
signal waddr_int : std_logic_vector(11 downto 0);
signal wdata_int : std_logic_vector(35 downto 0);
signal wen_dly : std_logic;
signal waddr_dly : std_logic_vector(11 downto 0);
signal wdata_dly : std_logic_vector(35 downto 0);
-- Model the delays for RAM read latency
signal ren_int : std_logic;
signal raddr_int : std_logic_vector(11 downto 0);
signal rdata_int : std_logic_vector(35 downto 0);
signal ren_dly : std_logic;
signal raddr_dly : std_logic_vector(11 downto 0);
signal rdata_dly : std_logic_vector(35 downto 0);
begin
--synthesis translate_off
process begin
case NUM_BRAMS is
when 1 | 2 | 4 | 9 =>
null;
when others =>
report "Error NUM_BRAMS size " & integer'image(NUM_BRAMS) & " is not supported." severity failure;
end case; -- case NUM_BRAMS
case RAM_RADDR_LATENCY is
when 0 | 1 =>
null;
when others =>
report "Error RAM_RADDR_LATENCY size " & integer'image(RAM_RADDR_LATENCY) & " is not supported." severity failure;
end case; -- case RAM_RADDR_LATENCY
case RAM_RDATA_LATENCY is
when 1 | 2 | 3 =>
null;
when others =>
report "Error RAM_RDATA_LATENCY size " & integer'image(RAM_RDATA_LATENCY) & " is not supported." severity failure;
end case; -- case RAM_RDATA_LATENCY
case RAM_WRITE_LATENCY is
when 0 | 1 =>
null;
when others =>
report "Error RAM_WRITE_LATENCY size " & integer'image(RAM_WRITE_LATENCY) & " is not supported." severity failure;
end case; -- case RAM_WRITE_LATENCY
wait;
end process;
--synthesis translate_on
-- 1 stage RAM write pipeline
wr_lat_1 : if(RAM_WRITE_LATENCY = 1) generate
process (user_clk_i) begin
if (user_clk_i'event and user_clk_i = '1') then
if (reset_i = '1') then
wen_dly <= '0' after TCQ;
waddr_dly <= (others => '0') after TCQ;
wdata_dly <= (others => '0') after TCQ;
else
wen_dly <= wen after TCQ;
waddr_dly <= waddr after TCQ;
wdata_dly <= wdata after TCQ;
end if;
end if;
end process;
wen_int <= wen_dly;
waddr_int <= waddr_dly;
wdata_int <= wdata_dly;
end generate wr_lat_1;
-- No RAM write pipeline
wr_lat_0 : if(RAM_WRITE_LATENCY /= 1) generate
wen_int <= wen;
waddr_int <= waddr;
wdata_int <= wdata;
end generate wr_lat_0;
-- 1 stage RAM read addr pipeline
raddr_lat_1 : if(RAM_RADDR_LATENCY = 1) generate
process (user_clk_i) begin
if (user_clk_i'event and user_clk_i = '1') then
if (reset_i = '1') then
ren_dly <= '0' after TCQ;
raddr_dly <= (others => '0') after TCQ;
else
ren_dly <= ren after TCQ;
raddr_dly <= raddr after TCQ;
end if;
end if;
end process;
ren_int <= ren_dly;
raddr_int <= raddr_dly;
end generate raddr_lat_1;
-- No RAM read addr pipeline
raddr_lat_0 : if(RAM_RADDR_LATENCY /= 1) generate
ren_int <= ren after TCQ;
raddr_int <= raddr after TCQ;
end generate raddr_lat_0;
-- 3 stages RAM read data pipeline (first is internal to BRAM)
rdata_lat_3 : if(RAM_RDATA_LATENCY = 3) generate
process (user_clk_i) begin
if (user_clk_i'event and user_clk_i = '1') then
if (reset_i = '1') then
rdata_dly <= (others => '0') after TCQ;
else
rdata_dly <= rdata_int after TCQ;
end if;
end if;
end process;
rdata <= rdata_dly;
end generate rdata_lat_3;
-- 1 or 2 stages RAM read data pipeline
rdata_lat_1_2 : if(RAM_RDATA_LATENCY /= 3) generate
rdata <= rdata_int;
end generate rdata_lat_1_2;
-- Instantiate BRAM(s)
brams : for i in 0 to (NUM_BRAMS - 1) generate
begin
ram : pcie_bram_s6
generic map (
DOB_REG => CALC_DOB_REG(RAM_RDATA_LATENCY),
WIDTH => CALC_WIDTH(NUM_BRAMS)
)
port map (
user_clk_i => user_clk_i,
reset_i => reset_i,
wen_i => wen_int,
waddr_i => waddr_int,
wdata_i => wdata_int((((i + 1) * CALC_WIDTH(NUM_BRAMS)) - 1) downto (i * CALC_WIDTH(NUM_BRAMS))),
ren_i => ren_int,
rce_i => rce,
raddr_i => raddr_int,
rdata_o => rdata_int((((i + 1) * CALC_WIDTH(NUM_BRAMS)) - 1) downto (i * CALC_WIDTH(NUM_BRAMS)))
);
end generate brams;
end rtl;
|
--This should pass
context c1 is
end context c1;
--This should fail
context c1 is
end context c1;
context c1 is
end context c1;
context c1 is
end context c1;
--This should pass
context c1 is
end context c1;
-- Split declaration across lines
context
c1
is
end
context
c1
;
|
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|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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ZaLu4ACIfgNcv80dwSFw+I1cMmecwe4FVUKMN4BHnyao52AUKlAD4yVsE/39M8qHUaU=
`protect end_protected
|
entity E is
end entity;
architecture A of E is
signal S1 : bit := '0';
signal S2_inertial : bit;
signal S2_transport : bit;
signal S2_delayed : bit;
constant LEVEL : severity_level := FAILURE;
begin
S1 <= '1' after 10 ns, '0' after 20 ns;
S2_inertial <= inertial S1 after 100 ns;
S2_transport <= transport S1 after 100 ns;
S2_delayed <= S1'delayed(100 ns);
CheckInertial: process
begin
wait until S2_inertial = '1' for 200 ns;
assert (S2_inertial = '0') report "Pulse was not rejected!" severity LEVEL;
wait;
end process;
CheckTransport: process
begin
wait until S2_transport = '1' for 115 ns;
assert (S2_transport = '1') report "Pulse was not transport delayed!" severity LEVEL;
assert (now = 110 ns) report "Transport delayed pulse was not received at 110 ns!" severity LEVEL;
wait;
end process;
CheckDelayed: process
begin
wait until S2_delayed = '1' for 115 ns;
assert (S2_delayed = '1') report "Pulse was not delayed!" severity LEVEL;
assert (now = 110 ns) report "Delayed pulse was not received at 110 ns!" severity LEVEL;
wait;
end process;
end architecture;
|
--********************************************************************************************************************--
--! @brief Testbench for decoder simulator
--********************************************************************************************************************--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use std.env.all;
use work.irqc_pif_pkg.all;
use work.ilos_sim_pkg.all;
--! Local libraries
library work;
--! Entity/Package Description
entity tb_irqc is
end entity tb_irqc;
architecture tb of tb_irqc is
-- Signal declarations
SIGNAL arst_sig: std_logic;
SIGNAL clk_sig: std_logic;
SIGNAL cs_sig: std_logic;
SIGNAL addr_sig: unsigned(2 DOWNTO 0);
SIGNAL wr_sig: std_logic;
SIGNAL rd_sig: std_logic;
SIGNAL din_sig: std_logic_vector(7 DOWNTO 0);
SIGNAL dout_sig: std_logic_vector(7 DOWNTO 0);
SIGNAL p2c_sig: t_p2c;
SIGNAL c2p_sig: t_c2p;
SIGNAL run_sig: std_logic;
signal sbi_if : t_sbi_if(addr(2 downto 0), wdata(7 downto 0), rdata(7 downto 0)) := init_sbi_if_signals(3, 8);
--! Component declaration for Behavioral Decoder
COMPONENT irqc_pif IS
PORT(
arst : in std_logic;
clk : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned;
wr : in std_logic;
rd : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0) := (others => '0');
--
p2c : out t_p2c;
c2p : in t_c2p
);
END COMPONENT irqc_pif;
BEGIN
IRQC: irqc_pif PORT MAP (
arst => arst_sig,
clk => clk_sig,
cs => cs_sig,
addr => addr_sig,
wr => wr_sig,
rd => rd_sig,
din => din_sig,
dout => dout_sig,
p2c => p2c_sig,
c2p => c2p_sig
);
-- Clock generation with concurrent procedure call
clk_gen(clk_sig, 50.0E6, 0 fs, run_sig); -- 50 MHz clock
-- Time resolution show
-- assert FALSE report "Time resolution: " & time'image(time'succ(0 fs)) severity NOTE;
tb: PROCESS
BEGIN
run_sig <= '1';
arst_sig <= '1';
cs_sig <= '0';
addr_sig <= to_unsigned(0, addr_sig'length);
wr_sig <= '0';
rd_sig <= '0';
din_sig <= (others => '0');
c2p_sig.aro_irr <= (others => '0');
c2p_sig.aro_ipr <= (others => '0');
c2p_sig.aro_irq2cpu_allowed <= '0';
wait for 200 ns;
arst_sig <= '0';
wait for 205 nS;
rd_sig <= '1';
cs_sig <= '1';
wait for 20 ns;
addr_sig <= to_unsigned(C_ADDR_IER, addr_sig'length);
wait for 20 nS;
addr_sig <= to_unsigned(C_ADDR_IPR, addr_sig'length);
wait for 20 nS;
addr_sig <= to_unsigned(C_ADDR_IRQ2CPU_ALLOWED, addr_sig'length);
wait for 20 nS;
addr_sig <= to_unsigned(C_ADDR_IER, addr_sig'length);
din_sig <= X"15";
wr_sig <= '1';
rd_sig <= '0';
wait for 20 ns;
cs_sig <= '0';
wr_sig <= '0';
rd_sig <= '1';
cs_sig <= '1';
wait for 80 ns;
cs_sig <= '0';
rd_sig <= '0';
wait for 200 nS;
-- End simulation
run_sig <= '0';
wait for 200 nS;
finish;
END PROCESS tb;
end architecture tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- Instruction memory for DLX
-- Memory filled by a process which reads from a file
-- file name is "test.asm.mem"
entity IRAM is
generic (
RAM_DEPTH : integer := 2048;
I_SIZE : integer := 32);
port (
Rst : in std_logic;
Addr : in std_logic_vector(I_SIZE - 1 downto 0);
Dout : out std_logic_vector(I_SIZE - 1 downto 0)
);
end IRAM;
architecture IRam_Bhe of IRAM is
type RAMtype is array (0 to RAM_DEPTH - 1) of integer;-- std_logic_vector(I_SIZE - 1 downto 0);
signal IRAM_mem : RAMtype;
begin -- IRam_Bhe
Dout <= conv_std_logic_vector(IRAM_mem(conv_integer(unsigned(Addr))/4),I_SIZE);
-- purpose: This process is in charge of filling the Instruction RAM with the firmware
-- type : combinational
-- inputs : Rst
-- outputs: IRAM_mem
FILL_MEM_P: process (Rst)
file mem_fp: text;
variable file_line : line;
variable index : integer := 0;
variable tmp_data_u : std_logic_vector(I_SIZE-1 downto 0);
begin -- process FILL_MEM_P
if (Rst = '1') then
file_open(mem_fp,"DLX_vhd/test_bench/test.asm.mem",READ_MODE);
while (not endfile(mem_fp)) loop
readline(mem_fp,file_line);
hread(file_line,tmp_data_u);
IRAM_mem(index) <= conv_integer(unsigned(tmp_data_u));
index := index + 1;
end loop;
end if;
end process FILL_MEM_P;
end IRam_Bhe;
|
-------------------------------------------------------------------------------------
-- FILE NAME : lfsr_internal.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- IEEE
--use ieee.numeric_std.all;
-- non-IEEE
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity lfsr_internal is
generic (
WIDTH : natural := 8
);
port (
clk_in : in std_logic;
rst_in : in std_logic;
reg_out : out std_logic_vector(WIDTH-1 downto 0)
);
end lfsr_internal;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of lfsr_internal is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant INIT_VALUE : std_logic_vector(WIDTH-1 downto 0) := (2 => '1', others => '0');
-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal shift_reg : std_logic_vector(WIDTH-1 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
process(clk_in, rst_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
shift_reg <= INIT_VALUE;
else
-- right shift the registers
--shift_reg(WIDTH-2 downto 0) <= shift_reg(WIDTH-1 downto 1);
-- xor bits to generate new value comming in from the msb
--shift_reg(WIDTH-1) <= shift_reg(2) xor (shift_reg(1) xor (shift_reg(0) xor shift_reg(0)));
shift_reg(0) <= shift_reg(2);
shift_reg(1) <= shift_reg(2) xor shift_reg(0);
shift_reg(2) <= shift_reg(1);
end if;
end if;
reg_out <= shift_reg;
end process;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1463.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p02n01i01463ent IS
END c08s08b00x00p02n01i01463ent;
ARCHITECTURE c08s08b00x00p02n01i01463arch OF c08s08b00x00p02n01i01463ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 1;
variable k : integer := 0;
BEGIN
case x is
when 1 => k := 5;
when 2 => NULL;
when 3 => NULL;
when others => NULL;
end case;
assert NOT( k=5 )
report "***PASSED TEST: c08s08b00x00p02n01i01463"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s08b00x00p02n01i01463 - missing reserved word 'when'"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p02n01i01463arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1463.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p02n01i01463ent IS
END c08s08b00x00p02n01i01463ent;
ARCHITECTURE c08s08b00x00p02n01i01463arch OF c08s08b00x00p02n01i01463ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 1;
variable k : integer := 0;
BEGIN
case x is
when 1 => k := 5;
when 2 => NULL;
when 3 => NULL;
when others => NULL;
end case;
assert NOT( k=5 )
report "***PASSED TEST: c08s08b00x00p02n01i01463"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s08b00x00p02n01i01463 - missing reserved word 'when'"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p02n01i01463arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1463.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p02n01i01463ent IS
END c08s08b00x00p02n01i01463ent;
ARCHITECTURE c08s08b00x00p02n01i01463arch OF c08s08b00x00p02n01i01463ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 1;
variable k : integer := 0;
BEGIN
case x is
when 1 => k := 5;
when 2 => NULL;
when 3 => NULL;
when others => NULL;
end case;
assert NOT( k=5 )
report "***PASSED TEST: c08s08b00x00p02n01i01463"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s08b00x00p02n01i01463 - missing reserved word 'when'"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p02n01i01463arch;
|
-----------------------------------------------------------------------------------------------------------
--
--
-- MILK COPROCESSOR
--
-- Created by Claudio Brunelli, 2004
--
-----------------------------------------------------------------------------------------------------------
--Copyright (c) 2004, Tampere University of Technology.
--All rights reserved.
--Redistribution and use in source and binary forms, with or without modification,
--are permitted provided that the following conditions are met:
--* Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--* Neither the name of Tampere University of Technology nor the names of its
-- contributors may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--THIS HARDWARE DESCRIPTION OR SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
--CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND NONINFRINGEMENT AND
--FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
--OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
--EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
--PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
--BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--ARISING IN ANY WAY OUT OF THE USE OF THIS HARDWARE DESCRIPTION OR SOFTWARE, EVEN
--IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use work.cop_definitions.all;
use work.cop_components.all;
use work.milk_regfile.all;
entity cop is
generic(COP_INDEX : integer range 0 to 3 := 1;
conv_flag : integer := conv_flag_value;
trunc_flag : integer := trunc_flag_value;
mul_flag : integer := mul_flag_value;
div_flag : integer := div_flag_value;
add_flag : integer := add_flag_value;
sqrt_flag : integer := sqrt_flag_value;
compare_flag : integer := compare_flag_value );
port( clk,reset,enable : in std_logic;
rd_cop, wr_cop : in std_logic;
c_index : in std_logic_vector(1 downto 0);
r_index : in std_logic_vector(3 downto 0);
cop_in : in std_logic_vector(word_width-1 downto 0);
cop_out : out std_logic_vector(word_width-1 downto 0);
read_hit : out std_logic;
write_hit : out std_logic;
cop_exc : out std_logic;
cop_stall : out std_logic);
end cop;
-----------------------------------------------------------------------------------
architecture milk of cop is
component ctrl_logic
port( clk,reset,enable,cr_we : in std_logic;
coffee_data : in std_logic_vector(word_width-1 downto 0);
lock_micro : in std_logic;
rs1,rs2,rd : out rf_addr;
opcd : out cop_opcode;
cvt_s_we,trunc_w_we,
mul_s_we,div_s_we,
add_s_we,sub_s_we,
sqrt_s_we,compare_s_we : out std_logic;
wb_reg_1 : out rf_addr;
wb_en_1 : out std_logic;
wb_reg_2 : out rf_addr;
wb_en_2 : out std_logic;
wb_reg_3 : out rf_addr;
wb_en_3 : out std_logic;
wb_reg_4 : out rf_addr;
wb_en_4 : out std_logic;
wb_reg_5 : out rf_addr;
wb_en_5 : out std_logic;
wb_reg_6 : out rf_addr;
wb_en_6 : out std_logic;
wb_reg_7 : out rf_addr;
wb_en_7 : out std_logic;
wb_reg_8 : out rf_addr;
wb_en_8 : out std_logic;
wb_reg_9 : out rf_addr;
wb_en_9 : out std_logic;
wb_en_10 : out std_logic;
exc_unknown_instruction : out std_logic );
end component;
component IO_logic
port( rd, enable, wr : in std_logic;
regtype_sel : in std_logic_vector(2 downto 0);
compare_out : in std_logic_vector(3 downto 0);
data_out : in std_logic_vector(word_width-1 downto 0);
sreg_out : in std_logic_vector(sreg_width-1 downto 0);
gated_write, gated_read,
creg_we, sreg_we : out std_logic;
data_in : out std_logic_vector(word_width-1 downto 0);
incoming_data : in std_logic_vector(word_width-1 downto 0);
outgoing_data : out std_logic_vector(word_width-1 downto 0));
end component;
component intr_sgls_generator
port( clk, reset : in std_logic;
exc_bus : in std_logic_vector(flags_amount-1 downto 0);
exception : out std_logic );
end component;
component sticky_status_logic
port( restore : in std_logic;
exc_in, status : in std_logic_vector(flags_amount-1 downto 0);
sticky_status : out std_logic_vector(flags_amount-1 downto 0) );
end component;
component int_to_single_conv
port( clk,reset,enable : in std_logic;
cvt_s_in : in std_logic_vector(word_width-1 downto 0);
cvt_s_out : out std_logic_vector(word_width-1 downto 0);
exc_inexact_conv : out std_logic );
end component;
component single_to_int_trunc
port( clk,reset,enable : in std_logic;
cvt_w_in : in std_logic_vector(word_width-1 downto 0);
cvt_w_out : out std_logic_vector(word_width-1 downto 0);
exc_inexact_trunc : out std_logic;
exc_overflow_trunc : out std_logic;
exc_invalid_operation_trunc : out std_logic );
end component;
component sp_fmultiplier
port( clk,reset,enable : in std_logic;
multiplicand,multiplicator : in std_logic_vector(word_width-1 downto 0);
mul_result : out std_logic_vector(word_width-1 downto 0);
exc_overflow_mul : out std_logic;
exc_underflow_mul : out std_logic;
exc_inexact_mul : out std_logic;
exc_invalid_operation_mul : out std_logic );
end component;
component sp_fdivider
port( clk,reset,enable : in std_logic;
dividend,divisor : in std_logic_vector(word_width-1 downto 0);
div_result : out std_logic_vector(word_width-1 downto 0);
exc_overflow_div : out std_logic;
exc_underflow_div : out std_logic;
exc_inexact_div : out std_logic;
exc_invalid_operation_div : out std_logic;
exc_division_by_zero : out std_logic );
end component;
component sp_fadder
port( clk,reset,enable : in std_logic;
sub_sel : in std_logic;
operand_a,operand_b : in std_logic_vector(word_width-1 downto 0);
add_result : out std_logic_vector(word_width-1 downto 0);
exc_overflow_add : out std_logic;
exc_underflow_add : out std_logic;
exc_inexact_add : out std_logic;
exc_invalid_operation_add : out std_logic );
end component;
component sp_fsqrt
port( clk,reset,enable : in std_logic;
radicand : in std_logic_vector(word_width-1 downto 0);
sqrt_result : out std_logic_vector(word_width-1 downto 0);
exc_inexact_sqrt : out std_logic;
exc_invalid_operation_sqrt : out std_logic );
end component;
component sp_fcomparator
port( clk,reset,enable : in std_logic;
unordered_query,equal_query,
less_query,invalid_enable : in std_logic;
opa,opb : in std_logic_vector(word_width-1 downto 0);
comparison_result : out std_logic_vector(word_width-1 downto 0);
exc_invalid_operation_compare : out std_logic );
end component;
component Register_locking is
port ( clk,reset : in Std_logic;
enable : in Std_logic;
cop_we : in Std_logic;
cop_rd_addr : in rf_addr;
cop_rd_enable : in Std_logic;
r_index : in Std_logic_vector(3 downto 0);
cop_rs1_addr : in rf_addr;
cop_rs2_addr : in rf_addr;
cop_wb_enable_1 : in Std_logic;
cop_wb_addr_1 : in rf_addr;
cop_wb_enable_2 : in Std_logic;
cop_wb_addr_2 : in rf_addr;
cop_wb_enable_3 : in Std_logic;
cop_wb_addr_3 : in rf_addr;
cop_wb_enable_4 : in Std_logic;
cop_wb_addr_4 : in rf_addr;
cop_wb_enable_5 : in Std_logic;
cop_wb_addr_5 : in rf_addr;
cop_wb_enable_6 : in Std_logic;
cop_wb_addr_6 : in rf_addr;
cop_wb_enable_7 : in Std_logic;
cop_wb_addr_7 : in rf_addr;
cop_wb_enable_8 : in Std_logic;
cop_wb_addr_8 : in rf_addr;
cop_wb_enable_9 : in Std_logic;
cop_wb_addr_9 : in rf_addr;
lock_micro : out Std_logic;
creg_rd : in rf_addr;
creg_opcode : in Std_logic_vector(cop_opcode_width-1 downto 0);
next_lock_vector_p : out Std_logic_vector(RF_width-1 downto 0) );
end component;
------------------------------------------------------------------------------
signal cs,write_hit_s,read_hit_s,
rcoffee_we,
coffee_sreg_write : std_logic;
signal cr_we, sr_we : std_logic;
signal high_value : std_logic;
signal regtype_sgl : std_logic_vector(2 downto 0);
------------------------------------------------------------------------------
-- DATA PATH SIGNALS
-- control
signal trunc_w_we,
cvt_s_we,
mul_s_we,
div_s_we,
add_s_we,
sub_s_we,
addsub_s_we,
sqrt_s_we,
compare_s_we : std_logic;
signal wb_en_1,wb_en_2,wb_en_3,
wb_en_4,wb_en_5,wb_en_6,
wb_en_7,wb_en_8,wb_en_9,
wb_en_10 : std_logic;
signal wb_reg_1,wb_reg_2,wb_reg_3,
wb_reg_4,wb_reg_5,wb_reg_6,
wb_reg_7, wb_reg_8, wb_reg_9 : rf_addr;
signal rs1,rs2 : rf_addr;
-- data
signal exception_bus : std_logic_vector(exceptions_amount-1 downto 0);
signal flags_in,flags_out,
sticky_status_input : std_logic_vector(flags_amount-1 downto 0);
signal coffee_data_in,ext_data_out,
op1,op2,cvt_s_out,
trunc_w_out,mul_out,div_out,
add_out,sqrt_out,compare_out,
mov_out,abs_out,
neg_out : std_logic_vector(word_width-1 downto 0);
signal status_reg_in, status_reg_out : std_logic_vector(sreg_width-1 downto 0);
signal exc_abs_invalid,
exc_neg_invalid : std_logic;
signal sticky_exc_bus : std_logic_vector(flags_amount-1 downto 0);
signal incoming_data,outgoing_data : std_logic_vector(word_width-1 downto 0);
signal lock_micro : Std_logic; -- active low
signal rd_addr,rs1_addr,rs2_addr : rf_addr;
signal compare_flag_in, compare_flag_out : std_logic_vector(3 downto 0);
signal creg_rd_s : rf_addr;
signal creg_opcode_s : cop_opcode;
signal next_lock_vector_s : Std_logic_vector(RF_width-1 downto 0);
-----------------------------------------------------------------------------------------------------------
begin
incoming_data <= cop_in;
cop_out <= outgoing_data;
rd_addr <= cop_in(8 downto 6);
rs1_addr <= cop_in(13 downto 11);
rs2_addr <= cop_in(18 downto 16);
cop_stall <= lock_micro;
high_value <= '1';
sr_we <= '1';
regtype_sgl <= ( r_index(3) & r_index(1) & r_index(0) );
addsub_s_we <= ( add_s_we or sub_s_we );
------------------------------------------------------------------------------
CS_VERIFICATION : process(c_index,rd_cop,wr_cop)
begin
if (c_index = std_logic_vector(to_unsigned(COP_INDEX,2)) and
(rd_cop = '1' or wr_cop = '1')) then
-- this coprocessor is indexed
cs <= '1';
else
-- not this coprocessor active
cs <= '0';
end if;
end process;
COFFEE_REG_WE:process(write_hit_s,r_index)
begin
if (write_hit_s='1' and r_index(3)='0') then
-- Coffee is writing on the Register file
rcoffee_we <= '1';
else
-- Coffee is writing (if gwrite='1') on a special purpose register
rcoffee_we <= '0';
end if;
end process;
------------------------------------------------------------------------------
-- Special Registers of the architecture
STATUS_REGISTER : WE_register
-- made up of 2 fields:
--
-- FLAGnS: 7 bits, each related to a whole set of exceptions (DOUBLEWRITE, OVERFLOW, UNDERFLOW,
-- INEXACT RESULT, INVALID OPERAND, DIVISION BY ZERO and UNKNOWN INSTRUCTION). They are
-- "sticky" meaning that once they are asserted, they can only be explicitly cleared by
-- the user.
-- They can only be read and written all at once.
--
-- CURRENT STATUS: this field also contains 7 bits having the same meaning as those in the flags
-- field, but they refer to the status of the last executed instruction.
generic map (reg_width => sreg_width)
port map (clk => clk, reset => reset, we => sr_we, data_in => status_reg_in,
data_out => status_reg_out);
------------------------------------------------------------------------------
-- main components instantiation
REG_FILE: Milk_RFile
port map ( clk => clk, reset => reset, enable => high_value,
exc_doublewrite => exception_bus(0),
rcoffee_we => rcoffee_we,
coffee_out => ext_data_out,
rs1 => rs1, rs1_out => op1,
rs2 => rs2, rs2_out => op2,
rcoffee_in => r_index(2 downto 0), coffee_in => coffee_data_in,
rd_we_1 => wb_en_1, rd_1 => wb_reg_1, d1_in => cvt_s_out,
rd_we_2 => wb_en_2, rd_2 => wb_reg_2, d2_in => trunc_w_out,
rd_we_3 => wb_en_3, rd_3 => wb_reg_3, d3_in => mul_out,
rd_we_4 => wb_en_4, rd_4 => wb_reg_4, d4_in => div_out,
rd_we_5 => wb_en_5, rd_5 => wb_reg_5, d5_in => add_out,
rd_we_6 => wb_en_6, rd_6 => wb_reg_6, d6_in => sqrt_out,
rd_we_7 => wb_en_7, rd_7 => wb_reg_7, d7_in => abs_out,
rd_we_8 => wb_en_8, rd_8 => wb_reg_8, d8_in => mov_out,
rd_we_9 => wb_en_9, rd_9 => wb_reg_9, d9_in => neg_out,
next_lock_vector => next_lock_vector_s);
REG_LOCK: Register_locking
port map (clk => clk, reset=> reset, enable => enable,
cop_we => wr_cop, cop_rd_addr => rd_addr, cop_rd_enable => rd_cop,
r_index => r_index, cop_rs1_addr => rs1_addr, cop_rs2_addr => rs2_addr,
cop_wb_enable_1 => wb_en_1, cop_wb_addr_1 => wb_reg_1,
cop_wb_enable_2 => wb_en_2, cop_wb_addr_2 => wb_reg_2,
cop_wb_enable_3 => wb_en_3, cop_wb_addr_3 => wb_reg_3,
cop_wb_enable_4 => wb_en_4, cop_wb_addr_4 => wb_reg_4,
cop_wb_enable_5 => wb_en_5, cop_wb_addr_5 => wb_reg_5,
cop_wb_enable_6 => wb_en_6, cop_wb_addr_6 => wb_reg_6,
cop_wb_enable_7 => wb_en_7, cop_wb_addr_7 => wb_reg_7,
cop_wb_enable_8 => wb_en_8, cop_wb_addr_8 => wb_reg_8,
cop_wb_enable_9 => wb_en_9, cop_wb_addr_9 => wb_reg_9,
lock_micro=> lock_micro, creg_rd => creg_rd_s, creg_opcode => creg_opcode_s,
next_lock_vector_p => next_lock_vector_s);
IO: IO_logic
port map (incoming_data => incoming_data,
outgoing_data => outgoing_data,
rd => rd_cop,
wr => wr_cop,
enable => cs,
gated_write => write_hit_s,
gated_read => read_hit_s,
data_in => coffee_data_in,
creg_we => cr_we,
sreg_we => coffee_sreg_write,
regtype_sel => regtype_sgl,
compare_out => compare_flag_in,
sreg_out => status_reg_out,
data_out => ext_data_out );
CTRL: ctrl_logic
port map (clk => clk,reset => reset,enable => enable,cr_we => cr_we,
coffee_data => coffee_data_in, lock_micro => lock_micro,
rs1 => rs1, rs2 => rs2, rd => creg_rd_s, opcd => creg_opcode_s,
cvt_s_we => cvt_s_we,trunc_w_we => trunc_w_we, mul_s_we => mul_s_we,
div_s_we => div_s_we, add_s_we => add_s_we, sub_s_we => sub_s_we,
sqrt_s_we => sqrt_s_we, compare_s_we => compare_s_we,
wb_reg_1 => wb_reg_1, wb_en_1 => wb_en_1,
wb_reg_2 => wb_reg_2, wb_en_2 => wb_en_2,
wb_reg_3 => wb_reg_3, wb_en_3 => wb_en_3,
wb_reg_4 => wb_reg_4, wb_en_4 => wb_en_4,
wb_reg_5 => wb_reg_5, wb_en_5 => wb_en_5,
wb_reg_6 => wb_reg_6, wb_en_6 => wb_en_6,
wb_reg_7 => wb_reg_7, wb_en_7 => wb_en_7,
wb_reg_8 => wb_reg_8, wb_en_8 => wb_en_8,
wb_reg_9 => wb_reg_9, wb_en_9 => wb_en_9,
wb_en_10 => wb_en_10,
exc_unknown_instruction => exception_bus(exceptions_amount-1));
INTR_SIGNALS_GEN: intr_sgls_generator
port map (clk => clk, reset => reset,
exc_bus => status_reg_in(flags_amount-1 downto 0),
exception => cop_exc );
STICKY_STATUS: sticky_status_logic
port map (restore => coffee_sreg_write,
exc_in => sticky_status_input,
status => flags_out,
sticky_status => flags_in );
------------------------------------------------------------------------------
-- FUNCTIONAL UNITS SUPPORTED BY THE COPROCESSOR
conv_generation: if conv_flag = 1 generate
CVT_S_LOGIC: int_to_single_conv
port map (clk => clk, reset => reset, enable => cvt_s_we,
cvt_s_in => op1, cvt_s_out => cvt_s_out, exc_inexact_conv => exception_bus(1) );
end generate conv_generation;
no_conv_generation: if conv_flag = 0 generate
cvt_s_out <= (others => '0');
exception_bus(1) <= '0';
end generate no_conv_generation;
-----------------------------------------------------
trunc_generation: if trunc_flag = 1 generate
TRUNC_W_LOGIC: single_to_int_trunc
port map (clk => clk, reset => reset, enable => trunc_w_we,
cvt_w_in => op1, cvt_w_out => trunc_w_out,
exc_overflow_trunc => exception_bus(2), exc_inexact_trunc => exception_bus(3),
exc_invalid_operation_trunc => exception_bus(4) );
end generate trunc_generation;
no_trunc_generation: if trunc_flag = 0 generate
trunc_w_out <= (others => '0');
exception_bus(2) <= '0';
exception_bus(3) <= '0';
exception_bus(4) <= '0';
end generate no_trunc_generation;
-----------------------------------------------------
mul_generation: if mul_flag = 1 generate
MUL_S_LOGIC: sp_fmultiplier
port map (clk => clk, reset => reset, enable => mul_s_we,
multiplicand => op1, multiplicator => op2,
exc_overflow_mul => exception_bus(5), exc_underflow_mul => exception_bus(6),
exc_inexact_mul => exception_bus(7), exc_invalid_operation_mul => exception_bus(8),
mul_result => mul_out );
end generate mul_generation;
no_mul_generation: if mul_flag = 0 generate
mul_out <= (others => '0');
exception_bus(5) <= '0';
exception_bus(6) <= '0';
exception_bus(7) <= '0';
exception_bus(8) <= '0';
end generate no_mul_generation;
-----------------------------------------------------
div_generation: if div_flag = 1 generate
DIV_S_LOGIC: sp_fdivider
port map (clk => clk, reset => reset ,enable => div_s_we,
dividend => op1, divisor => op2, exc_overflow_div => exception_bus(9),
exc_underflow_div => exception_bus(10), exc_inexact_div => exception_bus(11),
exc_invalid_operation_div => exception_bus(12), exc_division_by_zero => exception_bus(13),
div_result => div_out);
end generate div_generation;
no_div_generation: if div_flag = 0 generate
div_out <= (others => '0');
exception_bus(9) <= '0';
exception_bus(10) <= '0';
exception_bus(11) <= '0';
exception_bus(12) <= '0';
exception_bus(13) <= '0';
end generate no_div_generation;
-----------------------------------------------------
add_generation: if add_flag = 1 generate
ADD_S_LOGIC: sp_fadder
port map (clk => clk, reset => reset, enable => addsub_s_we,
operand_a => op1, operand_b => op2, sub_sel => sub_s_we, exc_overflow_add => exception_bus(14),
exc_underflow_add => exception_bus(15), exc_inexact_add => exception_bus(16),
exc_invalid_operation_add => exception_bus(17), add_result => add_out);
end generate add_generation;
no_add_generation: if add_flag = 0 generate
add_out <= (others => '0');
exception_bus(14) <= '0';
exception_bus(15) <= '0';
exception_bus(16) <= '0';
exception_bus(17) <= '0';
end generate no_add_generation;
-----------------------------------------------------
sqrt_generation: if sqrt_flag = 1 generate
SQRT_S_LOGIC: sp_fsqrt
port map (clk => clk, reset => reset, enable => sqrt_s_we, radicand => op1, sqrt_result => sqrt_out,
exc_inexact_sqrt => exception_bus(18), exc_invalid_operation_sqrt => exception_bus(19));
end generate sqrt_generation;
no_sqrt_generation: if sqrt_flag = 0 generate
sqrt_out <= (others => '0');
exception_bus(18) <= '0';
exception_bus(19) <= '0';
end generate no_sqrt_generation;
-----------------------------------------------------
comparator_generation: if compare_flag = 1 generate
COMP_S_LOGIC: sp_fcomparator
port map (clk => clk, reset => reset, enable => compare_s_we, opa => op1, opb => op2,
unordered_query => creg_opcode_s(0), equal_query => creg_opcode_s(1), less_query => creg_opcode_s(2),
invalid_enable => creg_opcode_s(3), exc_invalid_operation_compare => exception_bus(20),
comparison_result => compare_out);
end generate comparator_generation;
no_comparator_generation: if compare_flag = 0 generate
compare_out <= (others => '0');
exception_bus(20) <= '0';
end generate no_comparator_generation;
------------------------------------------------------------------
ABS_LOGIC : process(op1)
begin
--abs
if ( (op1(30 downto 23)="11111111") and (op1(22 downto 0) /= conv_std_logic_vector(0,23)) ) then
-- operand is a NaN
abs_out <= op1;
exc_abs_invalid <= '1';
elsif (op1(word_width-1)='1') then
abs_out <= ( not(op1(word_width-1)) & op1(word_width-2 downto 0) );
exc_abs_invalid <= '0';
else
abs_out <= op1;
exc_abs_invalid <= '0';
end if;
end process;
-----------------------------------------------------------------------
NEG_LOGIC : process(op1)
begin
if ( (op1(30 downto 23)="11111111") and (op1(22 downto 0)/=conv_std_logic_vector(0,23)) ) then
-- operand is a NaN
neg_out <= op1;
exc_neg_invalid <= '1';
else
neg_out <= ( not(op1(word_width-1)) & op1(word_width-2 downto 0) );
exc_neg_invalid <= '0';
end if;
end process;
mov_out <= op1;
-------------------------------------------------------------------------------
-- compare flag flip flop
COMPARE_FLAG_FF3: data_ff
port map (clk => clk, reset=>reset, d=>compare_flag_in(3), q=>compare_flag_out(3) );
COMPARE_FLAG_FF2: data_ff
port map (clk => clk, reset=>reset, d=>compare_flag_in(2), q=>compare_flag_out(2) );
COMPARE_FLAG_FF1: data_ff
port map (clk => clk, reset=>reset, d=>compare_flag_in(1), q=>compare_flag_out(1) );
COMPARE_FLAG_FF0: data_ff
port map (clk => clk, reset=>reset, d=>compare_flag_in(0), q=>compare_flag_out(0) );
-------------------------------------------------------------------------------
-- Compare flag selection logic
COMPARE_FLAG_SELECTION_LOGIC: process(compare_out,wb_en_10,compare_flag_out)
begin
if (wb_en_10 = '1') then
compare_flag_in <= compare_out(word_width-1 downto word_width-4);
else
compare_flag_in <= compare_flag_out;
end if;
end process;
-------------------------------------------------------------------------------
-- status register input specification; "flags field":
status_reg_in(sreg_width-1 downto flags_amount) <= flags_in;
----------------------------------------------------------
-- status register input specification; "current status" field:
flags_out <= status_reg_out(sreg_width-1 downto flags_amount);
-------------------------------------------------------------------------------
-- exceptions assignement
sticky_exc_bus(0) <= exception_bus(0);
sticky_exc_bus(1) <= (exception_bus(2) and wb_en_2) or (exception_bus(5) and wb_en_3) or (exception_bus(9) and wb_en_4) or (exception_bus(14) and wb_en_5);
sticky_exc_bus(2) <= (exception_bus(6) and wb_en_3) or (exception_bus(10) and wb_en_4) or (exception_bus(15) and wb_en_5);
sticky_exc_bus(3) <= (exception_bus(1) and wb_en_1) or (exception_bus(3) and wb_en_2) or (exception_bus(7) and wb_en_3) or (exception_bus(11) and wb_en_4) or (exception_bus(16) and wb_en_5) or (exception_bus(18) and wb_en_6);
sticky_exc_bus(4) <= (exception_bus(4) and wb_en_2) or (exception_bus(8) and wb_en_3) or (exception_bus(12) and wb_en_4) or (exception_bus(17) and wb_en_5) or (exc_abs_invalid and wb_en_7) or (exc_neg_invalid and wb_en_9) or (exception_bus(19) and wb_en_6);
sticky_exc_bus(5) <= (exception_bus(13) and wb_en_4);
sticky_exc_bus(6) <= exception_bus(21);
-------------------------------------------------------------------------------
status_reg_in(flags_amount-1 downto 0) <= sticky_exc_bus;
------------------------------------------------------------------------------
-- "sticky_status_logic" input assignement
process(coffee_sreg_write,sticky_exc_bus,coffee_data_in)
begin
if (coffee_sreg_write = '0') then
sticky_status_input <= sticky_exc_bus(flags_amount-1 downto 0);
else
sticky_status_input <= coffee_data_in(6 downto 0);
end if;
end process;
-----------------------------------------------------------------------------------------------------------
read_hit <= read_hit_s;
write_hit <= write_hit_s;
end milk;
|
package body
|
-- $Id: ibd_ibtst.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibd_ibtst - syn
-- Description: ibus dev(rem): ibus tester
--
-- Dependencies: memlib/fifo_simple_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2017.2; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-03-01 1116 1.0.1 rnam dly[rw]->bsy[rw]; datto for write; add datab
-- 2019-02-16 1112 1.0 Initial version
-- 2019-02-09 1110 0.1 First draft
------------------------------------------------------------------------------
--
-- ibus registers:
--
-- Addr Bits IB RB IR Name Function
-- 00 cntl Control register
-- 15 -- 0W 00 fclr fifo clear
-- 8 -- RW 00 datab ibus ack while busy for data nak
-- 7 -- RW 00 datto ibus timeout for data nak
-- 6 -- RW 00 nobyt disallow byte writes to data (loc+rem)
-- 5 -- RW 00 bsyw enable loc write busy for fifo/data
-- 4 -- RW 00 bsyr enable loc read busy for fifo/data
-- 3 -- RW 11 remw enable rem write for fifo/data
-- 2 -- RW 11 remr enable rem read for fifo/data
-- 1 -- RW 00 locw enable loc write for fifo/data
-- 0 -- RW 00 locr enable loc read for fifo/data
-- 01 -- R- stat Status register (moni last data/fifo)
-- 15:12 -- R- fsize fifo size
-- 6 -- R- racc remote access seen
-- 5 -- R- cacc console access seen
-- 4 -- R- be1 byte enable high seen
-- 3 -- R- be0 byte enable low seen
-- 2 -- R- rmw read-modify-write seen
-- 1 -- R- we write enable seen
-- 0 -- R- re read enable seen
-- 10 rw rw 00 data data register (byte/word writable)
-- 11 rw rw fifo fifo interface register
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibd_ibtst is -- ibus dev(rem): ibus tester
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#170000#,16))); -- base address
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end ibd_ibtst;
architecture syn of ibd_ibtst is
constant ibaddr_cntl : slv2 := "00"; -- cntl address offset
constant ibaddr_stat : slv2 := "01"; -- stat address offset
constant ibaddr_data : slv2 := "10"; -- bdat address offset
constant ibaddr_fifo : slv2 := "11"; -- wdat address offset
constant cntl_ibf_fclr : integer := 15;
constant cntl_ibf_datab : integer := 8;
constant cntl_ibf_datto : integer := 7;
constant cntl_ibf_nobyt : integer := 6;
constant cntl_ibf_bsyw : integer := 5;
constant cntl_ibf_bsyr : integer := 4;
constant cntl_ibf_remw : integer := 3;
constant cntl_ibf_remr : integer := 2;
constant cntl_ibf_locw : integer := 1;
constant cntl_ibf_locr : integer := 0;
subtype stat_ibf_fsize is integer range 15 downto 12;
constant stat_ibf_racc : integer := 6;
constant stat_ibf_cacc : integer := 5;
constant stat_ibf_be1 : integer := 4;
constant stat_ibf_be0 : integer := 3;
constant stat_ibf_rmw : integer := 2;
constant stat_ibf_we : integer := 1;
constant stat_ibf_re : integer := 0;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
datab : slbit; -- cntl: ibus busy for bad loc data
datto : slbit; -- cntl: ibus timeout for bad loc data
nobyt : slbit; -- cntl: disallow byte writes to data
bsyw : slbit; -- cntl: enable loc write busy
bsyr : slbit; -- cntl: enable loc read busy
remw : slbit; -- cntl: enable rem write
remr : slbit; -- cntl: enable rem read
locw : slbit; -- cntl: enable loc write
locr : slbit; -- cntl: enable loc read
racc : slbit; -- stat: racc seen
cacc : slbit; -- stat: cacc seen
be1 : slbit; -- stat: be1 seen
be0 : slbit; -- stat: be0 seen
rmw : slbit; -- stat: rmw seen
we : slbit; -- stat: we seen
re : slbit; -- stat: re seen
data : slv16; -- data register
dcnt : slv3; -- delay counter
req_1 : slbit; -- (re or we) of last cycle
rwm_1 : slbit; -- (re or we or rmw) of last cycle
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'0','0','0','0','0', -- datab,datto,nobyt,bsyw,bsyr
'1','1','0','0', -- remw,remr,locw,locr
'0','0','0','0', -- racc,cacc,be1,be0
'0','0','0', -- rmw,we,re
(others=>'0'), -- data
(others=>'0'), -- dcnt
'0','0' -- req_1,rwm_1
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal FIFO_CE : slbit := '0';
signal FIFO_WE : slbit := '0';
signal FIFO_RESET : slbit := '0';
signal FIFO_EMPTY : slbit := '0';
signal FIFO_FULL : slbit := '0';
signal FIFO_SIZE : slv4 := (others=>'0');
signal FIFO_DO : slv16 := (others=>'0');
begin
FIFO : fifo_simple_dram
generic map (
AWIDTH => 4,
DWIDTH => 16)
port map (
CLK => CLK,
RESET => FIFO_RESET,
CE => FIFO_CE,
WE => FIFO_WE,
DI => IB_MREQ.din,
DO => FIFO_DO,
EMPTY => FIFO_EMPTY,
FULL => FIFO_FULL,
SIZE => FIFO_SIZE
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, RESET, FIFO_DO, FIFO_EMPTY,
FIFO_FULL, FIFO_SIZE)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibreq : slbit := '0';
variable ibbusy : slbit := '0';
variable iback : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ififo_rst : slbit := '0';
variable ififo_ce : slbit := '0';
variable ififo_we : slbit := '0';
variable bsyok : slbit := '0'; -- fifo/data busy ok
variable dobsy : slbit := '0'; -- fifo/data do busy
variable wrok : slbit := '0'; -- fifo/data write ok
variable rdok : slbit := '0'; -- fifo/data read ok
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibbusy := '0';
iback := r.ibsel and ibreq;
ififo_rst := RESET;
ififo_ce := '0';
ififo_we := '0';
bsyok := '0';
if IB_MREQ.racc = '0' then -- loc
bsyok := (r.bsyr and IB_MREQ.re) or (r.bsyw and IB_MREQ.we);
end if;
dobsy := '0';
if IB_MREQ.racc = '1' then -- rem
wrok := r.remw;
rdok := r.remr;
else -- loc
wrok := r.locw;
rdok := r.locr;
end if;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
-- re,we,rmw edge detectors
n.req_1 := r.ibsel and (ibreq);
n.rwm_1 := r.ibsel and (ibreq or IB_MREQ.rmw);
-- ibus mreq monitor
if r.ibsel = '1' then
if (ibreq or IB_MREQ.rmw) = '1' and -- re or we or rmw
IB_MREQ.addr(2) = '1' then -- and addr = (data or fifo)
if r.rwm_1 = '0' then -- leading edge
n.racc := IB_MREQ.racc;
n.cacc := IB_MREQ.cacc;
n.be1 := IB_MREQ.be1;
n.be0 := IB_MREQ.be0;
n.rmw := IB_MREQ.rmw;
n.we := IB_MREQ.we;
n.re := IB_MREQ.re;
else -- later
n.we := r.we or IB_MREQ.we;
n.re := r.re or IB_MREQ.re;
end if;
end if;
end if;
-- delay counter
if r.ibsel='1' and ibreq='1' and bsyok='1' then -- selected,active,busy
if r.req_1 = '0' then -- leading edge
n.dcnt := "111";
dobsy := '1';
else -- later
if r.dcnt /= "000" then
n.dcnt := slv(unsigned(r.dcnt) - 1);
dobsy := '1';
end if;
end if;
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_cntl => -- CNTL
if IB_MREQ.racc = '1' then -- rem
if IB_MREQ.we = '1' then -- write
ififo_rst := IB_MREQ.din(cntl_ibf_fclr);
n.datab := IB_MREQ.din(cntl_ibf_datab);
n.datto := IB_MREQ.din(cntl_ibf_datto);
n.nobyt := IB_MREQ.din(cntl_ibf_nobyt);
n.bsyw := IB_MREQ.din(cntl_ibf_bsyw);
n.bsyr := IB_MREQ.din(cntl_ibf_bsyr);
n.remw := IB_MREQ.din(cntl_ibf_remw);
n.remr := IB_MREQ.din(cntl_ibf_remr);
n.locw := IB_MREQ.din(cntl_ibf_locw);
n.locr := IB_MREQ.din(cntl_ibf_locr);
end if;
else -- loc
iback := '0'; -- reject loc access to CNTL
end if;
when ibaddr_stat => -- STAT
if IB_MREQ.racc = '0' then -- loc
iback := '0'; -- reject loc access to STAT
end if;
when ibaddr_data => -- DATA
if IB_MREQ.we = '1' then -- write
if wrok = '1' then -- write enabled
if r.nobyt = '1' and -- byte write allowed check
(IB_MREQ.be1='0' or IB_MREQ.be0='0') then
iback := '0'; -- send nak
else -- byte check ok
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
else -- no busy active
if IB_MREQ.be1 = '1' then
n.data(ibf_byte1) := IB_MREQ.din(ibf_byte1);
end if;
if IB_MREQ.be0 = '1' then
n.data(ibf_byte0) := IB_MREQ.din(ibf_byte0);
end if;
end if; -- dobsy = '1'
end if; -- byte check
else -- write disabled
if dobsy = '1' then -- busy active
iback := r.datab; -- send ack when busy for nak
ibbusy := '1';
else -- no busy active
if r.datto = '1' then -- data time out enabled
iback := '0';
ibbusy := '1'; -- will cause timeout !
else
iback := '0'; -- send nak
end if;
end if; -- dobsy = '1'
end if; -- wrok = '1'
end if; -- IB_MREQ.we = '1'
if IB_MREQ.re = '1' then -- read
if rdok = '1' then -- read enabled
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
end if;
else -- read disabled
if dobsy = '1' then -- busy active
iback := r.datab; -- send ack when busy for nak
ibbusy := '1';
else -- no busy active
if r.datto = '1' then -- data time out enabled
iback := '0';
ibbusy := '1'; -- will cause timeout !
else
iback := '0'; -- send nak
end if;
end if; -- dobsy = '1'
end if; -- rdok = '0'
end if; -- IB_MREQ.re = '1'
when ibaddr_fifo => -- FIFO
if IB_MREQ.we = '1' then -- write
if wrok = '1' then -- write enabled
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
else -- busy not active
if FIFO_FULL = '0' then -- fifo not full
ififo_ce := '1';
ififo_we := '1';
else -- fifo full
iback := '0'; -- send nak
end if; -- FIFO_FULL = '0'
end if; -- dobsy = '1'
else -- write disabled
iback := '0'; -- send nak
end if; -- wrok = '1'
end if; -- IB_MREQ.we = '1'
if IB_MREQ.re = '1' then -- read
if rdok = '1' then -- read enabled
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
else -- busy not active
if FIFO_EMPTY = '0' then -- fifo not empty
ififo_ce := '1';
else -- fifo empty
iback := '0'; -- send nak
end if; -- FIFO_EMPTY = '0'
end if; -- dobsy = '1'
else -- read disabled
iback := '0'; -- send nak
end if; -- rdok = '1'
end if; -- IB_MREQ.re = '1'
when others => null;
end case; --
end if; --r.ibsel = '1'
-- ibus output driver
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_cntl => -- CNTL
idout(cntl_ibf_datab) := r.datab;
idout(cntl_ibf_datto) := r.datto;
idout(cntl_ibf_nobyt) := r.nobyt;
idout(cntl_ibf_bsyw) := r.bsyw;
idout(cntl_ibf_bsyr) := r.bsyr;
idout(cntl_ibf_remw) := r.remw;
idout(cntl_ibf_remr) := r.remr;
idout(cntl_ibf_locw) := r.locw;
idout(cntl_ibf_locr) := r.locr;
when ibaddr_stat => -- STAT
idout(stat_ibf_fsize) := FIFO_SIZE;
idout(stat_ibf_racc) := r.racc;
idout(stat_ibf_cacc) := r.cacc;
idout(stat_ibf_be1) := r.be1;
idout(stat_ibf_be0) := r.be0;
idout(stat_ibf_rmw) := r.rmw;
idout(stat_ibf_we) := r.we;
idout(stat_ibf_re) := r.re;
when ibaddr_data => -- DATA
idout := r.data;
when ibaddr_fifo => -- FIFO
idout := FIFO_DO;
when others => null;
end case;
end if;
N_REGS <= n;
FIFO_RESET <= ififo_rst;
FIFO_CE <= ififo_ce;
FIFO_WE <= ififo_we;
IB_SRES.dout <= idout;
IB_SRES.ack <= iback;
IB_SRES.busy <= ibbusy;
end process proc_next;
end syn;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3120.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p05n01i03120ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p05n01i03120ent_a;
ARCHITECTURE c05s02b01x01p05n01i03120arch_a OF c05s02b01x01p05n01i03120ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p05n01i03120arch_a;
configuration c05s02b01x01p05n01i03120cfg_a of c05s02b01x01p05n01i03120ent_a is
for c05s02b01x01p05n01i03120arch_a
end for;
end c05s02b01x01p05n01i03120cfg_a;
--
ENTITY c05s02b01x01p05n01i03120ent IS
END c05s02b01x01p05n01i03120ent;
ARCHITECTURE c05s02b01x01p05n01i03120arch OF c05s02b01x01p05n01i03120ent IS
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
for all : virtual use configuration work.c05s02b01x01p05n01i03120cfg_a;
BEGIN
u1 : virtual
generic map ( true )
port map (s1, s2);
u2 : virtual
generic map ( true )
port map (s2, s3);
u3 : virtual
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p05n01i03120"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p05n01i03120 - Use a configuration that is fully bound test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p05n01i03120arch;
configuration c05s02b01x01p05n01i03120cfg of c05s02b01x01p05n01i03120ent is
for c05s02b01x01p05n01i03120arch
end for;
end c05s02b01x01p05n01i03120cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3120.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p05n01i03120ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p05n01i03120ent_a;
ARCHITECTURE c05s02b01x01p05n01i03120arch_a OF c05s02b01x01p05n01i03120ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p05n01i03120arch_a;
configuration c05s02b01x01p05n01i03120cfg_a of c05s02b01x01p05n01i03120ent_a is
for c05s02b01x01p05n01i03120arch_a
end for;
end c05s02b01x01p05n01i03120cfg_a;
--
ENTITY c05s02b01x01p05n01i03120ent IS
END c05s02b01x01p05n01i03120ent;
ARCHITECTURE c05s02b01x01p05n01i03120arch OF c05s02b01x01p05n01i03120ent IS
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
for all : virtual use configuration work.c05s02b01x01p05n01i03120cfg_a;
BEGIN
u1 : virtual
generic map ( true )
port map (s1, s2);
u2 : virtual
generic map ( true )
port map (s2, s3);
u3 : virtual
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p05n01i03120"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p05n01i03120 - Use a configuration that is fully bound test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p05n01i03120arch;
configuration c05s02b01x01p05n01i03120cfg of c05s02b01x01p05n01i03120ent is
for c05s02b01x01p05n01i03120arch
end for;
end c05s02b01x01p05n01i03120cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3120.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p05n01i03120ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p05n01i03120ent_a;
ARCHITECTURE c05s02b01x01p05n01i03120arch_a OF c05s02b01x01p05n01i03120ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p05n01i03120arch_a;
configuration c05s02b01x01p05n01i03120cfg_a of c05s02b01x01p05n01i03120ent_a is
for c05s02b01x01p05n01i03120arch_a
end for;
end c05s02b01x01p05n01i03120cfg_a;
--
ENTITY c05s02b01x01p05n01i03120ent IS
END c05s02b01x01p05n01i03120ent;
ARCHITECTURE c05s02b01x01p05n01i03120arch OF c05s02b01x01p05n01i03120ent IS
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
for all : virtual use configuration work.c05s02b01x01p05n01i03120cfg_a;
BEGIN
u1 : virtual
generic map ( true )
port map (s1, s2);
u2 : virtual
generic map ( true )
port map (s2, s3);
u3 : virtual
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p05n01i03120"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p05n01i03120 - Use a configuration that is fully bound test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p05n01i03120arch;
configuration c05s02b01x01p05n01i03120cfg of c05s02b01x01p05n01i03120ent is
for c05s02b01x01p05n01i03120arch
end for;
end c05s02b01x01p05n01i03120cfg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rs232_in is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
input_i : in std_logic;
data_o : out std_logic_vector(7 downto 0);
receive_o : out std_logic
);
end rs232_in;
architecture behavioral of rs232_in is
-- input sync
signal input_sync : std_logic;
-- delay counter
signal delay_counter : std_logic_vector(8 downto 0);
signal delay_counter_reset : std_logic;
signal delay_counter_half : std_logic;
-- shift register
signal shift_register : std_logic_vector(7 downto 0);
signal shift_register_shift : std_logic;
-- FSM
type state_type is (READY, WAIT_HALF, RECV_START, RECV0, RECV1, RECV2, RECV3,
RECV4, RECV5, RECV6, RECV7, RECV_END);
signal state : state_type;
signal next_state : state_type;
begin
data_o <= shift_register;
-- input sync
input_sync_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
input_sync <= input_i;
end if;
end process;
-- delay counter (set for 115200 boud)
delay_counter_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1' or delay_counter_reset = '1') then
delay_counter <= (others => '0');
else
if (delay_counter = "110110010") then
delay_counter <= (others => '0');
else
delay_counter <= delay_counter + 1;
end if;
end if;
end if;
end process;
delay_counter_half_proc : process(delay_counter)
begin
if (delay_counter = "011011001") then
delay_counter_half <= '1';
else
delay_counter_half <= '0';
end if;
end process;
-- shift register
shift_register_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
shift_register <= (others => '0');
else
if (shift_register_shift = '1') then
shift_register <= input_sync & shift_register(7 downto 1);
else
shift_register <= shift_register;
end if;
end if;
end if;
end process;
-- FSM
sync_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
state <= READY;
else
state <= next_state;
end if;
end if;
end process;
state_proc : process(state, input_sync, delay_counter_half)
begin
next_state <= state;
case (state) is
when READY =>
if (input_sync = '0') then
next_state <= WAIT_HALF;
end if;
when WAIT_HALF =>
if (delay_counter_half = '1') then
next_state <= RECV_START;
end if;
when RECV_START =>
if (delay_counter_half = '1') then
next_state <= RECV0;
end if;
when RECV0 =>
if (delay_counter_half = '1') then
next_state <= RECV1;
end if;
when RECV1 =>
if (delay_counter_half = '1') then
next_state <= RECV2;
end if;
when RECV2 =>
if (delay_counter_half = '1') then
next_state <= RECV3;
end if;
when RECV3 =>
if (delay_counter_half = '1') then
next_state <= RECV4;
end if;
when RECV4 =>
if (delay_counter_half = '1') then
next_state <= RECV5;
end if;
when RECV5 =>
if (delay_counter_half = '1') then
next_state <= RECV6;
end if;
when RECV6 =>
if (delay_counter_half = '1') then
next_state <= RECV7;
end if;
when RECV7 =>
if (delay_counter_half = '1') then
next_state <= RECV_END;
end if;
when RECV_END =>
if (input_sync = '1') then
next_state <= READY;
end if;
when others =>
end case;
end process;
output_proc : process(state, input_sync, delay_counter_half)
begin
delay_counter_reset <= '0';
shift_register_shift <= '0';
receive_o <= '0';
case (state) is
when READY =>
if (input_sync = '0') then
delay_counter_reset <= '1';
end if;
when WAIT_HALF =>
when RECV_START | RECV0 | RECV1 | RECV2 | RECV3 | RECV4 | RECV5 | RECV6 =>
if (delay_counter_half = '1') then
shift_register_shift <= '1';
end if;
when RECV7 =>
if (delay_counter_half = '1') then
receive_o <= '1';
end if;
when RECV_END =>
when others =>
end case;
end process;
end behavioral;
|
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|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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|
`protect begin_protected
`protect version = 1
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`protect data_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_block
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`protect key_block
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`protect key_block
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|
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|
`protect begin_protected
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|
`protect begin_protected
`protect version = 1
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`protect key_block
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`protect end_protected
|
entity FIFO is
end entity FIFO;
entity FIFO is
end entity;
entity FIFO is
end;
entity FIFO is
end FIFO;
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- This design implements an FIR Moving Average filter
-- which averages L points
--
-- y[n] = ( x[n] + x[n-1] + .. + x[n-L-1] ) / L
-- = summation( x[n-k], k = 0 to L-1 ) / L
--
-- L= Number of points to be averaged or length of filter
-- N = L-1 = order of the filter
--
-- To design above FIR filer using R adders (resources),
-- we modify the difference equation in two ways below:
--
-- 1. y[n] = summation( summation( x[ n - r x M - s], s = 0 to M-1 ), r = 0 to R-1 ) / L
--
-- where,
-- M = L/R = Samples to be processed per resource (adder)
-- r = resource id = 0 to R-1
-- s = sample id = 0 to M-1
--
-- This allocates resource id
-- 0 with sub-sequence : x[n] x[n-1] ... x[n-M+1]
-- 1 with sub-sequence : x[n-M] x[n-M-1] ... x[n-2M+1]
-- 2 with sub-sequence : x[n-2M] x[n-2M-1] ... x[n-3M+1]
-- ...
-- R-1 with sub-sequence : x[n-(R-1)M] x[n-(R-1)M-1] ... x[n-RM+1] = x[n-L+1]
--
-- 2. y[n] = summation( summation( x[ n - R x s - r], s = 0 to M-1 ), r = 0 to R-1 ) / L
--
-- where,
-- M = L/R = Samples to be processed per resource (adder)
-- r = resource id = 0 to R-1
-- s = sample id = 0 to M-1
--
-- This allocates rth resource id with subsequence
-- m = 0 m = 1 m = M-1
-- r = 0 : x[n-1] x[n-1-R] ... x[n-1-RM+R]
-- r = 1 : x[n-2] x[n-2-R] ... x[n-2-RM+R]
-- r = 2 : x[n-3] x[n-3-R] ... x[n-3-RM+R]
-- ..
-- r = R-1 : x[n-R] x[n-R-R] ... x[n-R-RM+R] = x[n-RM]= x[n-L]
--
-- While we can implement any of above two equations,
-- in our design we implement the second of the above
-- two equations
entity fir is
generic( L : natural := 16; -- L = Filter length or number of points to be averaged
L_BW : natural := 4; -- L_BW = Ceil(Log2(L))
R : natural := 4; -- R = Number of resources (adders and multiplexers)
R_BW : natural := 2; -- R_BW = Ceil(Log2(R))
M : natural := 4; -- M = L/R = Samples to be processed per resource (adder)
M_BW : natural := 2; -- M_BW = Ceil(Log2(M)) = number of select bits for M samples
W : natural := 16 ); -- W = Bit width of input and output sample data (signed)
port (clk : in std_logic; -- clock
reset_n : in std_logic; -- active low asynchronous reset
fir_en : in std_logic; -- handshake signal
fir_in : in std_logic_vector( W-1 downto 0 ); -- sample inout x[n]
fir_out : out std_logic_vector( W-1 downto 0 ); -- sample output y[n]
fir_rdy : out std_logic -- handshake signal
);
end fir;
architecture rtl of fir is
type t_reg_x is array ( 0 to L-1 ) of signed( W-1 downto 0 );
signal reg_x : t_reg_x := ( others => ( others => '0' ) );
-- R outputs of R muxes (one mux output per resource)
type t_array_mux_out_x is array ( 0 to R-1 ) of signed( W-1 downto 0 );
signal sig_array_mux_out_x : t_array_mux_out_x := ( others => ( others => '0') );
-- Each of the R muxes has M data inputs requiring total of L=MR data inputs
--type t_array_mux_in_x is array ( 0 to L-1 ) of signed( W-1 downto 0 );
--signal sig_array_mux_in_x : t_array_mux_in_x := ( others => ( others => '0') );
type t_mux_in is array ( 0 to R-1, 0 to M-1 ) of signed( W-1 downto 0 );
signal sig_array_mux_in_x : t_mux_in := ( others => ( others => ( others => '0') ) );
-- M_BW-bit select signal for each mux where M_BW = Ceil(Log2(M)), M = L/R
signal sig_mux_sel_cnt : unsigned( M_BW-1 downto 0 ) := ( others => '0' );
signal sig_mux_sel_cnt_next : unsigned( M_BW-1 downto 0 ) := ( others => '0' );
-- R-1 signed adders to add R mux outputs.
-- i.e. 0, 1..., (R-2)th signed adders
-- Note that we set bit size of each adder output equal to the
-- maximum bit-size required to accumulate addition of R signed
-- numbers which is W+R_BW bits where R_BW = Ceil(Log2(R))
type t_array_signed_adders is array ( 0 to R-2 ) of signed( W+R_BW-1 downto 0 );
signal sig_array_signed_adders: t_array_signed_adders := ( others => ( others => '0' ) );
-- (R-1)th signed adder is used to accumulate result of
-- R-1 signed adders i.e output of the (R-2)th signed adder
signal sig_y_sum : signed( W+L_BW-1 downto 0 ) := ( others => '0' ); -- add/sub of L = MR signed numbers each of W bit-width
-- requires total W+L_BW bits where L_BW = Ceil(log2(L))
signal reg_y_sum : signed( W+L_BW-1 downto 0 ) := ( others => '0' );
signal sig_y_out : signed( W+L_BW-1 downto 0 ) := ( others => '0' );
begin
-- Generate x[n-1],x[n-2]...x[n-L+1], x[n-L]
process ( clk, reset_n )
begin
if ( reset_n = '0' ) then
for i in 0 to (L-1) loop
reg_x(i) <= ( others => '0');
end loop;
elsif ( rising_edge(clk) ) then
if( fir_en = '1' ) then
reg_x(0) <= signed(fir_in);
for i in 1 to (L-1) loop
reg_x(i) <= reg_x(i-1);
end loop;
end if;
end if;
end process;
-- Allocate following data lines as inputs to the rth multiplexer:
-- j = 0 j = 1 j = M-1
-- i = 0 : x[n-1] x[n-1-R] ... x[n-1-RM+R]
-- i = 1 : x[n-2] x[n-2-R] ... x[n-2-RM+R]
-- i = 2 : x[n-3] x[n-3-R] ... x[n-3-RM+R]
-- ..
-- i = R-1 : x[n-R] x[n-R-R] ... x[n-R-RM+R] = x[n-RM]= x[n-L]
process( reg_x )
begin
for i in 0 to R-1 loop
for j in 0 to M-1 loop
sig_array_mux_in_x( i, j ) <= reg_x( i + j*R );
end loop;
end loop;
end process;
-- Generate select signal for the muxes using a counter (mod M)
process ( clk, reset_n )
begin
if ( reset_n = '0' ) then
sig_mux_sel_cnt <= to_unsigned( M-1, sig_mux_sel_cnt'LENGTH );
elsif ( rising_edge( clk ) ) then
if ( fir_en = '1' ) then
sig_mux_sel_cnt <= sig_mux_sel_cnt_next;
end if;
end if;
end process;
sig_mux_sel_cnt_next <= ( others => '0' ) when sig_mux_sel_cnt = ( M-1 ) else
( sig_mux_sel_cnt + 1 );
-- Generate the R muxes
process ( sig_array_mux_in_x, sig_mux_sel_cnt )
begin
for i in 0 to R-1 loop
sig_array_mux_out_x( i ) <= sig_array_mux_in_x( i, to_integer( sig_mux_sel_cnt ) );
end loop;
end process;
-- Generate R-1 signed adders for R muxes.
-- i.e. 0, 1..., (R-2)th signed adders
-- A[0] = M[0]+M[1]
-- A[1] = A[0]+M[2]
-- A[2] = A[1]+M[3]
-- ....
-- A[R-2] = A[R-3]+M[R-1]
--
-- Note: The last signed adder to be used for
-- accumulation is generated separately
comb_adders : process ( sig_array_mux_out_x )
begin
sig_array_signed_adders(0) <= resize( sig_array_mux_out_x(0), sig_array_signed_adders(0)'LENGTH ) +
resize( sig_array_mux_out_x(1), sig_array_signed_adders(0)'LENGTH );
for i in 1 to R-2 loop
sig_array_signed_adders(i)<= resize( sig_array_signed_adders(i-1), sig_array_signed_adders(i)'LENGTH ) +
resize( sig_array_mux_out_x(i+1), sig_array_signed_adders(i)'LENGTH );
end loop;
end process comb_adders;
-- Generate Y[n] i.e. Rth signed adder which accumulates
-- result of R-1 signed adders i.e the output of
-- (R-1)th signed adder
-- A[R-1] = A[R-1] + A[R-2]
-- Y[n] = Y[n-1] + A[R-2];
sig_y_sum <= reg_y_sum + resize( sig_array_signed_adders( R-2 ), sig_y_sum'LENGTH ) ;
-- Generate Y[n-1]
process( clk, reset_n )
begin
if ( reset_n = '0' ) then
reg_y_sum <= ( others => '0');
elsif ( rising_edge(clk) ) then
if( fir_en = '1' ) then
reg_y_sum <= sig_y_sum;
end if;
end if;
end process;
-- y[n] = Y[n]/L = Y[n] >> L_BW, where L_BW=Ceil(log2(L))
sig_y_out <= sig_y_sum srl L_BW;
process ( clk, reset_n )
begin
if ( reset_n = '0' ) then
fir_out <= ( others => '0' );
elsif ( rising_edge( clk ) ) then
if( fir_en = '1' ) then
fir_out <= std_logic_vector( sig_y_out( W-1 downto 0 ) );
end if;
end if;
end process;
end rtl; |
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`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
------------
-- pcore top level wrapper
-- generated at 2008-02-12 16:14:05.727709 by 'mkhwtask.py hwt_mutex_unlock 1 ../src/hwt_mutex_unlock.vhd'
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hw_task is
generic (
C_BUS_BURST_AWIDTH : integer := 13; -- Note: This addresses bytes
C_BUS_BURST_DWIDTH : integer := 64;
C_TASK_BURST_AWIDTH : integer := 11; -- this addresses 32Bit words
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif_flat : in std_logic_vector;
o_osif_flat : out std_logic_vector;
-- burst mem interface
i_burstAddr : in std_logic_vector(0 to C_BUS_BURST_AWIDTH-1);
i_burstData : in std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
o_burstData : out std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
i_burstWE : in std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end hw_task;
architecture structural of hw_task is
component burst_ram
port (
addra: IN std_logic_VECTOR(10 downto 0);
addrb: IN std_logic_VECTOR(9 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
dinb: IN std_logic_VECTOR(63 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(63 downto 0);
wea: IN std_logic;
web: IN std_logic
);
end component;
signal o_osif_flat_i : std_logic_vector(0 to 41);
signal i_osif_flat_i : std_logic_vector(0 to 44);
signal o_osif : osif_task2os_t;
signal i_osif : osif_os2task_t;
signal task2burst_Addr : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
signal task2burst_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal burst2task_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal task2burst_WE : std_logic;
signal task2burst_Clk : std_logic;
attribute keep_hierarchy : string;
attribute keep_hierarchy of structural: architecture is "true";
begin
-- connect top level signals
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
-- (un)flatten osif records
o_osif_flat_i <= to_std_logic_vector(o_osif);
i_osif <= to_osif_os2task_t(i_osif_flat_i);
-- instantiate user task
hwt_mutex_i : entity hwt_mutex
port map (
clk => clk,
reset => reset,
i_osif => i_osif,
o_osif => o_osif,
o_RAMAddr => task2burst_Addr,
o_RAMData => task2burst_Data,
i_RAMData => burst2task_Data,
o_RAMWE => task2burst_WE,
o_RAMClk => task2burst_Clk,
i_timeBase => i_timeBase
);
burst_ram_i : burst_ram
port map (
addra => task2burst_Addr,
addrb => i_burstAddr(0 to C_BUS_BURST_AWIDTH-1 -3), -- RAM is addressing 64Bit values
clka => task2burst_Clk,
clkb => clk,
dina => task2burst_Data,
dinb => i_burstData,
douta => burst2task_Data,
doutb => o_burstData,
wea => task2burst_WE,
web => i_burstWE
);
end structural;
|
--==============================================================================
--! @file ddr3_ctrl_pkg.vhd
--==============================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--! Specific packages
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- DDR3 Controller Package
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--! @brief
--! DDR3 controller package
--------------------------------------------------------------------------------
--! @details
--! Contains DDR3 controller core top level component declaration.
--------------------------------------------------------------------------------
--! @version
--! 0.1 | mc | 12.08.2011 | File creation and Doxygen comments
--!
--! @author
--! mc : Matthieu Cattin, CERN (BE-CO-HT)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--==============================================================================
--! Entity declaration for ddr3_ctrl_pkg
--==============================================================================
package ddr3_ctrl_pkg is
--==============================================================================
--! Functions declaration
--==============================================================================
function f_qword_swap_256 (
constant enable : boolean;
signal din : std_logic_vector(255 downto 0);
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector;
function f_qword_swap_512 (
constant enable : boolean;
signal din : std_logic_vector(511 downto 0);
signal byte_swap : std_logic_vector(2 downto 0))
return std_logic_vector;
--==============================================================================
--! Components declaration
--==============================================================================
COMPONENT fifo_315x16
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(604 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(604 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_27x16
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(29-1 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(29-1 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_4x16
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(37-1 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(37-1 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_256x16
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
component qword_swap_512 is
Port ( qword_swap : in STD_LOGIC_VECTOR (2 downto 0);
din : in STD_LOGIC_VECTOR (511 downto 0);
dout : out STD_LOGIC_VECTOR (511 downto 0));
end component;
component byte_swap_64 is
Port ( qword_swap : in STD_LOGIC_VECTOR (2 downto 0);
din : in STD_LOGIC_VECTOR (63 downto 0);
dout : out STD_LOGIC_VECTOR (63 downto 0));
end component;
end ddr3_ctrl_pkg;
package body ddr3_ctrl_pkg is
-----------------------------------------------------------------------------
-- QWORD swap function
--
-- enable | byte_swap | din | dout
-- false | XX | ABCD | ABCD
-- true | 00 | ABCD | ABCD
-- true | 01 | ABCD | BADC
-- true | 10 | ABCD | CDAB
-- true | 11 | ABCD | DCBA
-----------------------------------------------------------------------------
function f_qword_swap_256 (
constant enable : boolean;
signal din : std_logic_vector(255 downto 0);
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector is
variable dout : std_logic_vector(255 downto 0);
begin
if (enable = true) then
case byte_swap is
when "00" =>
dout := din;
when "01" =>
dout := din(191 downto 128)
& din(255 downto 192)
& din(63 downto 0)
& din(127 downto 64);
when "10" =>
dout := din(127 downto 0)
& din(255 downto 128);
when "11" =>
dout := din(63 downto 0)
& din(127 downto 64)
& din(191 downto 128)
& din(255 downto 192);
when others =>
dout := din;
end case;
else
dout := din;
end if;
return dout;
end function f_qword_swap_256;
-----------------------------------------------------------------------------
-- QWORD swap function
--
-- enable | byte_swap | din | dout
-- false | XXX | ABCDEFGH | ABCDEFGH
-- true | 000 | ABCDEFGH | ABCDEFGH
-- true | 001 | ABCDEFGH | BADCFEHG
-- true | 010 | ABCDEFGH | CDABGHEF
-- true | 011 | ABCDEFGH | DCBAHGFE
-- true | 100 | ABCDEFGH | EFGHABCD
-- true | 101 | ABCDEFGH | FEHGBADC
-- true | 110 | ABCDEFGH | GHEFCDAB
-- true | 111 | ABCDEFGH | HGFEDCBA
-----------------------------------------------------------------------------
function f_qword_swap_512 (
constant enable : boolean;
signal din : std_logic_vector(511 downto 0);
signal byte_swap : std_logic_vector(2 downto 0))
return std_logic_vector is
variable dout : std_logic_vector(511 downto 0);
begin
if (enable = true) then
if byte_swap(2) = '0' then
dout := f_qword_swap_256(true, din(511 downto 256), byte_swap(1 downto 0)) & f_qword_swap_256(true, din(255 downto 0), byte_swap(1 downto 0));
else
dout := f_qword_swap_256(true, din(255 downto 0), byte_swap(1 downto 0)) & f_qword_swap_256(true, din(511 downto 256), byte_swap(1 downto 0));
end if;
else
dout := din;
end if;
return dout;
end function f_qword_swap_512;
end ddr3_ctrl_pkg;
|
architecture RTL of FIFO is
function func1 return integer is begin end function func1;
FUNCTION FUNC1 RETURN INTEGER is BEGIN END FUNCTION FUNC1;
procedure proc1 Is begin end procedure proc1;
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_119 is
port (
ne : out std_logic;
in0 : in std_logic_vector(15 downto 0);
in1 : in std_logic_vector(15 downto 0)
);
end cmp_119;
architecture augh of cmp_119 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_119 is
port (
ne : out std_logic;
in0 : in std_logic_vector(15 downto 0);
in1 : in std_logic_vector(15 downto 0)
);
end cmp_119;
architecture augh of cmp_119 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
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------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reg_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 1 ;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
m_axi_sg_hrdresetn : in std_logic ; --
--
s_axi_lite_aclk : in std_logic ; --
axi_lite_reset_n : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
--
-- MM2S Signals --
mm2s_stop : in std_logic ; --
mm2s_halted_clr : in std_logic ; --
mm2s_halted_set : in std_logic ; --
mm2s_idle_set : in std_logic ; --
mm2s_idle_clr : in std_logic ; --
mm2s_dma_interr_set : in std_logic ; --
mm2s_dma_slverr_set : in std_logic ; --
mm2s_dma_decerr_set : in std_logic ; --
mm2s_ioc_irq_set : in std_logic ; --
mm2s_dly_irq_set : in std_logic ; --
mm2s_irqdelay_status : in std_logic_vector(7 downto 0) ; --
mm2s_irqthresh_status : in std_logic_vector(7 downto 0) ; --
mm2s_ftch_interr_set : in std_logic ; --
mm2s_ftch_slverr_set : in std_logic ; --
mm2s_ftch_decerr_set : in std_logic ; --
mm2s_updt_interr_set : in std_logic ; --
mm2s_updt_slverr_set : in std_logic ; --
mm2s_updt_decerr_set : in std_logic ; --
mm2s_new_curdesc_wren : in std_logic ; --
mm2s_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_dlyirq_dsble : out std_logic ; -- CR605888 --
mm2s_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
mm2s_irqthresh_wren : out std_logic ; --
mm2s_irqdelay_wren : out std_logic ; --
mm2s_tailpntr_updated : out std_logic ; --
mm2s_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_sa : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_length_wren : out std_logic ; --
--
-- S2MM Signals --
tdest_in : in std_logic_vector (6 downto 0) ;
same_tdest_in : in std_logic;
sg_ctl : out std_logic_vector (7 downto 0) ;
s2mm_sof : in std_logic ;
s2mm_eof : in std_logic ;
s2mm_stop : in std_logic ; --
s2mm_halted_clr : in std_logic ; --
s2mm_halted_set : in std_logic ; --
s2mm_idle_set : in std_logic ; --
s2mm_idle_clr : in std_logic ; --
s2mm_dma_interr_set : in std_logic ; --
s2mm_dma_slverr_set : in std_logic ; --
s2mm_dma_decerr_set : in std_logic ; --
s2mm_ioc_irq_set : in std_logic ; --
s2mm_dly_irq_set : in std_logic ; --
s2mm_irqdelay_status : in std_logic_vector(7 downto 0) ; --
s2mm_irqthresh_status : in std_logic_vector(7 downto 0) ; --
s2mm_ftch_interr_set : in std_logic ; --
s2mm_ftch_slverr_set : in std_logic ; --
s2mm_ftch_decerr_set : in std_logic ; --
s2mm_updt_interr_set : in std_logic ; --
s2mm_updt_slverr_set : in std_logic ; --
s2mm_updt_decerr_set : in std_logic ; --
s2mm_new_curdesc_wren : in std_logic ; --
s2mm_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_tvalid : in std_logic;
s2mm_dlyirq_dsble : out std_logic ; -- CR605888 --
s2mm_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
s2mm_irqthresh_wren : out std_logic ; --
s2mm_irqdelay_wren : out std_logic ; --
s2mm_tailpntr_updated : out std_logic ; --
s2mm_tvalid_latch : out std_logic ;
s2mm_tvalid_latch_del : out std_logic ;
s2mm_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_da : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s2mm_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : out std_logic ; --
s2mm_bytes_rcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : in std_logic ; --
--
soft_reset : out std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- Fetch/Update error addresses --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
bd_eq : in std_logic
);
end axi_dma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant LENGTH_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH - C_SG_LENGTH_WIDTH;
constant LENGTH_PAD : std_logic_vector(LENGTH_PAD_WIDTH-1 downto 0) := (others => '0');
constant ZERO_BYTES : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
constant NUM_REG_PER_S2MM_INT : integer := NUM_REG_PER_CHANNEL + ((NUM_REG_PER_S2MM+1)*C_ENABLE_MULTI_CHANNEL);
-- Specifies to axi_dma_register which block belongs to S2MM channel
-- so simple dma s2mm_da register offset can be correctly assigned
-- CR603034
--constant NOT_S2MM_CHANNEL : integer := 0;
--constant IS_S2MM_CHANNEL : integer := 1;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi2ip_wrce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_rdce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_error_in : std_logic := '0';
signal mm2s_error_out : std_logic := '0';
signal s2mm_curdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_curdesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int3 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_error_in : std_logic := '0';
signal s2mm_error_out : std_logic := '0';
signal read_addr : std_logic_vector(9 downto 0) := (others => '0');
signal mm2s_introut_i_cdc_from : std_logic := '0';
signal mm2s_introut_d1_cdc_tig : std_logic := '0';
signal mm2s_introut_to : std_logic := '0';
signal s2mm_introut_i_cdc_from : std_logic := '0';
signal s2mm_introut_d1_cdc_tig : std_logic := '0';
signal s2mm_introut_to : std_logic := '0';
signal mm2s_sgctl : std_logic_vector (7 downto 0);
signal s2mm_sgctl : std_logic_vector (7 downto 0);
signal or_sgctl : std_logic_vector (7 downto 0);
signal open_window, wren : std_logic;
signal s2mm_tailpntr_updated_int : std_logic;
signal s2mm_tailpntr_updated_int1 : std_logic;
signal s2mm_tailpntr_updated_int2 : std_logic;
signal s2mm_tailpntr_updated_int3 : std_logic;
signal tvalid_int : std_logic;
signal tvalid_int1 : std_logic;
signal tvalid_int2 : std_logic;
signal new_tdest : std_logic;
signal tvalid_latch : std_logic;
signal tdest_changed : std_logic;
signal tdest_fix : std_logic_vector (4 downto 0);
signal same_tdest_int1 : std_logic;
signal same_tdest_int2 : std_logic;
signal same_tdest_int3 : std_logic;
signal same_tdest_arrived : std_logic;
signal s2mm_msb_sa : std_logic_vector (31 downto 0);
signal mm2s_msb_sa : std_logic_vector (31 downto 0);
--ATTRIBUTE async_reg OF mm2s_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_introut_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_to : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
or_sgctl <= mm2s_sgctl or s2mm_sgctl;
sg_ctl <= mm2s_sgctl or s2mm_sgctl;
mm2s_dmacr <= mm2s_dmacr_i; -- MM2S DMA Control Register
mm2s_dmasr <= mm2s_dmasr_i; -- MM2S DMA Status Register
mm2s_sa <= mm2s_sa_i; -- MM2S Source Address (Simple Only)
mm2s_length <= mm2s_length_i; -- MM2S Length (Simple Only)
s2mm_dmacr <= s2mm_dmacr_i; -- S2MM DMA Control Register
s2mm_dmasr <= s2mm_dmasr_i; -- S2MM DMA Status Register
s2mm_da <= s2mm_da_i; -- S2MM Destination Address (Simple Only)
s2mm_length <= s2mm_length_i; -- S2MM Length (Simple Only)
-- Soft reset set in mm2s DMACR or s2MM DMACR
soft_reset <= mm2s_dmacr_i(DMACR_RESET_BIT)
or s2mm_dmacr_i(DMACR_RESET_BIT);
-- CR572013 - added to match legacy SDMA operation
mm2s_irqthresh_rstdsbl <= not mm2s_dmacr_i(DMACR_DLY_IRQEN_BIT);
s2mm_irqthresh_rstdsbl <= not s2mm_dmacr_i(DMACR_DLY_IRQEN_BIT);
--GEN_S2MM_TDEST : if (C_NUM_S2MM_CHANNELS > 1) generate
GEN_S2MM_TDEST : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
PROC_WREN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_taildesc_int3 <= (others => '0');
s2mm_tailpntr_updated_int <= '0';
s2mm_tailpntr_updated_int2 <= '0';
s2mm_tailpntr_updated <= '0';
else -- (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- s2mm_tailpntr_updated_int <= new_tdest or same_tdest_arrived;
-- s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
-- s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
-- Commenting this code as it is causing SG to start early
s2mm_tailpntr_updated_int <= new_tdest or s2mm_tailpntr_updated_int1 or (same_tdest_arrived and (not bd_eq));
s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
end if;
end if;
end process PROC_WREN;
-- this is always '1' as MCH needs to have all desc reg programmed before hand
--s2mm_tailpntr_updated_int3_i <= s2mm_tailpntr_updated_int2_i and (not s2mm_tailpntr_updated_int_i); -- and tvalid_latch;
tdest_fix <= "11111";
new_tdest <= tvalid_int1 xor tvalid_int2;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
tvalid_int <= '0';
tvalid_int1 <= '0';
tvalid_int2 <= '0';
tvalid_latch <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
tvalid_int <= tdest_in (6); --s2mm_tvalid;
tvalid_int1 <= tvalid_int;
tvalid_int2 <= tvalid_int1;
s2mm_tvalid_latch_del <= tvalid_latch;
if (new_tdest = '1') then
tvalid_latch <= '0';
else
tvalid_latch <= '1';
end if;
end if;
end if;
end process;
-- will trigger tailptrupdtd and it will then get SG out of pause
same_tdest_arrived <= same_tdest_int2 xor same_tdest_int3;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
same_tdest_int1 <= '0';
same_tdest_int2 <= '0';
same_tdest_int3 <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
same_tdest_int1 <= same_tdest_in;
same_tdest_int2 <= same_tdest_int1;
same_tdest_int3 <= same_tdest_int2;
end if;
end if;
end process;
-- process (m_axi_sg_aclk)
-- begin
-- if (m_axi_sg_aresetn = '0') then
-- tvalid_int <= '0';
-- tvalid_int1 <= '0';
-- tvalid_latch <= '0';
-- tdest_in_int <= (others => '0');
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- tvalid_int <= s2mm_tvalid;
-- tvalid_int1 <= tvalid_int;
-- tdest_in_int <= tdest_in;
-- -- if (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- if (tvalid_int1 = '1' and tdest_in_int = "00000" and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- elsif (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- tvalid_latch <= '0';
-- elsif (tvalid_int1 = '1' and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- end if;
-- end if;
-- end process;
s2mm_tvalid_latch <= tvalid_latch;
PROC_TDEST_IN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_curdesc_int2 <= (others => '0');
s2mm_taildesc_int2 <= (others => '0');
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
s2mm_curdesc_int2 <= s2mm_curdesc_int;
s2mm_taildesc_int2 <= s2mm_taildesc_int;
end if;
end if;
end process PROC_TDEST_IN;
s2mm_curdesc <= s2mm_curdesc_int2;
s2mm_taildesc <= s2mm_taildesc_int2;
end generate GEN_S2MM_TDEST;
GEN_S2MM_NO_TDEST : if (C_ENABLE_MULTI_CHANNEL = 0) generate
--GEN_S2MM_NO_TDEST : if (C_NUM_S2MM_CHANNELS = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int1;
s2mm_curdesc <= s2mm_curdesc_int;
s2mm_taildesc <= s2mm_taildesc_int;
s2mm_tvalid_latch <= '1';
s2mm_tvalid_latch_del <= '1';
end generate GEN_S2MM_NO_TDEST;
-- For 32 bit address map only lsb registers out
GEN_DESC_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_curdesc <= mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL32;
-- For 64 bit address map lsb and msb registers out
GEN_DESC_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
mm2s_curdesc <= mm2s_curdesc_msb_i & mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_msb_i & mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_msb_muxed & s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_msb_muxed & s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL64;
-------------------------------------------------------------------------------
-- Generate AXI Lite Inteface
-------------------------------------------------------------------------------
GEN_AXI_LITE_IF : if C_INCLUDE_MM2S = 1 or C_INCLUDE_S2MM = 1 generate
begin
AXI_LITE_IF_I : entity axi_dma_v7_1_10.axi_dma_lite_if
generic map(
C_NUM_CE => 23+(121*C_ENABLE_MULTI_CHANNEL) ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
ip2axi_aclk => m_axi_sg_aclk ,
ip2axi_aresetn => m_axi_sg_hrdresetn ,
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_aresetn => axi_lite_reset_n ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
axi2ip_wrce => axi2ip_wrce ,
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_rdce => open ,
axi2ip_rdaddr => axi2ip_rdaddr ,
ip2axi_rddata => ip2axi_rddata
);
end generate GEN_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- No channels therefore do not generate an AXI Lite interface
-------------------------------------------------------------------------------
GEN_NO_AXI_LITE_IF : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
s_axi_lite_awready <= '0';
s_axi_lite_wready <= '0';
s_axi_lite_bresp <= (others => '0');
s_axi_lite_bvalid <= '0';
s_axi_lite_arready <= '0';
s_axi_lite_rvalid <= '0';
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rresp <= (others => '0');
end generate GEN_NO_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- Generate MM2S Registers if included
-------------------------------------------------------------------------------
GEN_MM2S_REGISTERS : if C_INCLUDE_MM2S = 1 generate
begin
I_MM2S_DMA_REGISTER : entity axi_dma_v7_1_10.axi_dma_register
generic map (
C_NUM_REGISTERS => NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
-- C_NUM_S2MM_CHANNELS => 1 --C_S2MM_NUM_CHANNELS
--C_CHANNEL_IS_S2MM => NOT_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
(RESERVED_2C_INDEX
downto MM2S_DMACR_INDEX),
--(MM2S_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => mm2s_stop ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
-- SG Error Control
ftch_interr_set => mm2s_ftch_interr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => mm2s_updt_interr_set ,
updt_slverr_set => mm2s_updt_slverr_set ,
updt_decerr_set => mm2s_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
dma_interr_set => mm2s_dma_interr_set ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
error_in => s2mm_error_out ,
error_out => mm2s_error_out ,
introut => mm2s_introut_i_cdc_from ,
soft_reset_in => s2mm_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => mm2s_tailpntr_updated ,
-- Channel Registers
sg_ctl => mm2s_sgctl ,
dmacr => mm2s_dmacr_i ,
dmasr => mm2s_dmasr_i ,
curdesc_lsb => mm2s_curdesc_lsb_i ,
curdesc_msb => mm2s_curdesc_msb_i ,
taildesc_lsb => mm2s_taildesc_lsb_i ,
taildesc_msb => mm2s_taildesc_msb_i ,
-- curdesc1_lsb => open ,
-- curdesc1_msb => open ,
-- taildesc1_lsb => open ,
-- taildesc1_msb => open ,
-- curdesc2_lsb => open ,
-- curdesc2_msb => open ,
-- taildesc2_lsb => open ,
-- taildesc2_msb => open ,
--
-- curdesc3_lsb => open ,
-- curdesc3_msb => open ,
-- taildesc3_lsb => open ,
-- taildesc3_msb => open ,
--
-- curdesc4_lsb => open ,
-- curdesc4_msb => open ,
-- taildesc4_lsb => open ,
-- taildesc4_msb => open ,
--
-- curdesc5_lsb => open ,
-- curdesc5_msb => open ,
-- taildesc5_lsb => open ,
-- taildesc5_msb => open ,
--
-- curdesc6_lsb => open ,
-- curdesc6_msb => open ,
-- taildesc6_lsb => open ,
-- taildesc6_msb => open ,
--
-- curdesc7_lsb => open ,
-- curdesc7_msb => open ,
-- taildesc7_lsb => open ,
-- taildesc7_msb => open ,
--
-- curdesc8_lsb => open ,
-- curdesc8_msb => open ,
-- taildesc8_lsb => open ,
-- taildesc8_msb => open ,
--
-- curdesc9_lsb => open ,
-- curdesc9_msb => open ,
-- taildesc9_lsb => open ,
-- taildesc9_msb => open ,
--
-- curdesc10_lsb => open ,
-- curdesc10_msb => open ,
-- taildesc10_lsb => open ,
-- taildesc10_msb => open ,
--
-- curdesc11_lsb => open ,
-- curdesc11_msb => open ,
-- taildesc11_lsb => open ,
-- taildesc11_msb => open ,
--
-- curdesc12_lsb => open ,
-- curdesc12_msb => open ,
-- taildesc12_lsb => open ,
-- taildesc12_msb => open ,
--
-- curdesc13_lsb => open ,
-- curdesc13_msb => open ,
-- taildesc13_lsb => open ,
-- taildesc13_msb => open ,
--
-- curdesc14_lsb => open ,
-- curdesc14_msb => open ,
-- taildesc14_lsb => open ,
-- taildesc14_msb => open ,
--
--
-- curdesc15_lsb => open ,
-- curdesc15_msb => open ,
-- taildesc15_lsb => open ,
-- taildesc15_msb => open ,
--
-- tdest_in => "00000" ,
buffer_address => mm2s_sa_i ,
buffer_length => mm2s_length_i ,
buffer_length_wren => mm2s_length_wren ,
bytes_received => ZERO_BYTES , -- Not used on transmit
bytes_received_wren => '0' -- Not used on transmit
);
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => mm2s_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- -- if(axi_lite_reset_n = '0')then
-- -- mm2s_introut_d1_cdc_tig <= '0';
-- -- mm2s_introut_to <= '0';
-- -- else
-- mm2s_introut_d1_cdc_tig <= mm2s_introut_i_cdc_from;
-- mm2s_introut_to <= mm2s_introut_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
mm2s_introut <= mm2s_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
mm2s_introut <= mm2s_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Tie MM2S Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_MM2S_REGISTERS : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_dmacr_i <= (others => '0');
mm2s_dmasr_i <= (others => '0');
mm2s_curdesc_lsb_i <= (others => '0');
mm2s_curdesc_msb_i <= (others => '0');
mm2s_taildesc_lsb_i <= (others => '0');
mm2s_taildesc_msb_i <= (others => '0');
mm2s_tailpntr_updated <= '0';
mm2s_sa_i <= (others => '0');
mm2s_length_i <= (others => '0');
mm2s_length_wren <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_introut <= '0';
mm2s_sgctl <= (others => '0');
mm2s_dlyirq_dsble <= '0';
end generate GEN_NO_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Generate S2MM Registers if included
-------------------------------------------------------------------------------
GEN_S2MM_REGISTERS : if C_INCLUDE_S2MM = 1 generate
begin
I_S2MM_DMA_REGISTER : entity axi_dma_v7_1_10.axi_dma_register_s2mm
generic map (
C_NUM_REGISTERS => NUM_REG_PER_S2MM_INT, --NUM_REG_TOTAL, --NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
--C_CHANNEL_IS_S2MM => IS_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
((23+(121*C_ENABLE_MULTI_CHANNEL)-1)
downto RESERVED_2C_INDEX) ,
-- downto S2MM_DMACR_INDEX),
--S2MM_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => s2mm_stop ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
-- SG Error Control
dma_interr_set => s2mm_dma_interr_set ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_interr_set => s2mm_ftch_interr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => s2mm_updt_interr_set ,
updt_slverr_set => s2mm_updt_slverr_set ,
updt_decerr_set => s2mm_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
error_in => mm2s_error_out ,
error_out => s2mm_error_out ,
introut => s2mm_introut_i_cdc_from ,
soft_reset_in => mm2s_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => s2mm_tailpntr_updated_int1 ,
-- Channel Registers
sg_ctl => s2mm_sgctl ,
dmacr => s2mm_dmacr_i ,
dmasr => s2mm_dmasr_i ,
curdesc_lsb => s2mm_curdesc_lsb_i ,
curdesc_msb => s2mm_curdesc_msb_i ,
taildesc_lsb => s2mm_taildesc_lsb_i ,
taildesc_msb => s2mm_taildesc_msb_i ,
curdesc1_lsb => s2mm_curdesc1_lsb_i ,
curdesc1_msb => s2mm_curdesc1_msb_i ,
taildesc1_lsb => s2mm_taildesc1_lsb_i ,
taildesc1_msb => s2mm_taildesc1_msb_i ,
curdesc2_lsb => s2mm_curdesc2_lsb_i ,
curdesc2_msb => s2mm_curdesc2_msb_i ,
taildesc2_lsb => s2mm_taildesc2_lsb_i ,
taildesc2_msb => s2mm_taildesc2_msb_i ,
curdesc3_lsb => s2mm_curdesc3_lsb_i ,
curdesc3_msb => s2mm_curdesc3_msb_i ,
taildesc3_lsb => s2mm_taildesc3_lsb_i ,
taildesc3_msb => s2mm_taildesc3_msb_i ,
curdesc4_lsb => s2mm_curdesc4_lsb_i ,
curdesc4_msb => s2mm_curdesc4_msb_i ,
taildesc4_lsb => s2mm_taildesc4_lsb_i ,
taildesc4_msb => s2mm_taildesc4_msb_i ,
curdesc5_lsb => s2mm_curdesc5_lsb_i ,
curdesc5_msb => s2mm_curdesc5_msb_i ,
taildesc5_lsb => s2mm_taildesc5_lsb_i ,
taildesc5_msb => s2mm_taildesc5_msb_i ,
curdesc6_lsb => s2mm_curdesc6_lsb_i ,
curdesc6_msb => s2mm_curdesc6_msb_i ,
taildesc6_lsb => s2mm_taildesc6_lsb_i ,
taildesc6_msb => s2mm_taildesc6_msb_i ,
curdesc7_lsb => s2mm_curdesc7_lsb_i ,
curdesc7_msb => s2mm_curdesc7_msb_i ,
taildesc7_lsb => s2mm_taildesc7_lsb_i ,
taildesc7_msb => s2mm_taildesc7_msb_i ,
curdesc8_lsb => s2mm_curdesc8_lsb_i ,
curdesc8_msb => s2mm_curdesc8_msb_i ,
taildesc8_lsb => s2mm_taildesc8_lsb_i ,
taildesc8_msb => s2mm_taildesc8_msb_i ,
curdesc9_lsb => s2mm_curdesc9_lsb_i ,
curdesc9_msb => s2mm_curdesc9_msb_i ,
taildesc9_lsb => s2mm_taildesc9_lsb_i ,
taildesc9_msb => s2mm_taildesc9_msb_i ,
curdesc10_lsb => s2mm_curdesc10_lsb_i ,
curdesc10_msb => s2mm_curdesc10_msb_i ,
taildesc10_lsb => s2mm_taildesc10_lsb_i ,
taildesc10_msb => s2mm_taildesc10_msb_i ,
curdesc11_lsb => s2mm_curdesc11_lsb_i ,
curdesc11_msb => s2mm_curdesc11_msb_i ,
taildesc11_lsb => s2mm_taildesc11_lsb_i ,
taildesc11_msb => s2mm_taildesc11_msb_i ,
curdesc12_lsb => s2mm_curdesc12_lsb_i ,
curdesc12_msb => s2mm_curdesc12_msb_i ,
taildesc12_lsb => s2mm_taildesc12_lsb_i ,
taildesc12_msb => s2mm_taildesc12_msb_i ,
curdesc13_lsb => s2mm_curdesc13_lsb_i ,
curdesc13_msb => s2mm_curdesc13_msb_i ,
taildesc13_lsb => s2mm_taildesc13_lsb_i ,
taildesc13_msb => s2mm_taildesc13_msb_i ,
curdesc14_lsb => s2mm_curdesc14_lsb_i ,
curdesc14_msb => s2mm_curdesc14_msb_i ,
taildesc14_lsb => s2mm_taildesc14_lsb_i ,
taildesc14_msb => s2mm_taildesc14_msb_i ,
curdesc15_lsb => s2mm_curdesc15_lsb_i ,
curdesc15_msb => s2mm_curdesc15_msb_i ,
taildesc15_lsb => s2mm_taildesc15_lsb_i ,
taildesc15_msb => s2mm_taildesc15_msb_i ,
tdest_in => tdest_in (5 downto 0) ,
buffer_address => s2mm_da_i ,
buffer_length => s2mm_length_i ,
buffer_length_wren => s2mm_length_wren ,
bytes_received => s2mm_bytes_rcvd ,
bytes_received_wren => s2mm_bytes_rcvd_wren
);
GEN_DESC_MUX_SINGLE_CH : if C_NUM_S2MM_CHANNELS = 1 generate
begin
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
end generate GEN_DESC_MUX_SINGLE_CH;
GEN_DESC_MUX : if C_NUM_S2MM_CHANNELS > 1 generate
begin
PROC_DESC_SEL : process (tdest_in, s2mm_curdesc_lsb_i,s2mm_curdesc_msb_i, s2mm_taildesc_lsb_i, s2mm_taildesc_msb_i,
s2mm_curdesc1_lsb_i,s2mm_curdesc1_msb_i, s2mm_taildesc1_lsb_i, s2mm_taildesc1_msb_i,
s2mm_curdesc2_lsb_i,s2mm_curdesc2_msb_i, s2mm_taildesc2_lsb_i, s2mm_taildesc2_msb_i,
s2mm_curdesc3_lsb_i,s2mm_curdesc3_msb_i, s2mm_taildesc3_lsb_i, s2mm_taildesc3_msb_i,
s2mm_curdesc4_lsb_i,s2mm_curdesc4_msb_i, s2mm_taildesc4_lsb_i, s2mm_taildesc4_msb_i,
s2mm_curdesc5_lsb_i,s2mm_curdesc5_msb_i, s2mm_taildesc5_lsb_i, s2mm_taildesc5_msb_i,
s2mm_curdesc6_lsb_i,s2mm_curdesc6_msb_i, s2mm_taildesc6_lsb_i, s2mm_taildesc6_msb_i,
s2mm_curdesc7_lsb_i,s2mm_curdesc7_msb_i, s2mm_taildesc7_lsb_i, s2mm_taildesc7_msb_i,
s2mm_curdesc8_lsb_i,s2mm_curdesc8_msb_i, s2mm_taildesc8_lsb_i, s2mm_taildesc8_msb_i,
s2mm_curdesc9_lsb_i,s2mm_curdesc9_msb_i, s2mm_taildesc9_lsb_i, s2mm_taildesc9_msb_i,
s2mm_curdesc10_lsb_i,s2mm_curdesc10_msb_i, s2mm_taildesc10_lsb_i, s2mm_taildesc10_msb_i,
s2mm_curdesc11_lsb_i,s2mm_curdesc11_msb_i, s2mm_taildesc11_lsb_i, s2mm_taildesc11_msb_i,
s2mm_curdesc12_lsb_i,s2mm_curdesc12_msb_i, s2mm_taildesc12_lsb_i, s2mm_taildesc12_msb_i,
s2mm_curdesc13_lsb_i,s2mm_curdesc13_msb_i, s2mm_taildesc13_lsb_i, s2mm_taildesc13_msb_i,
s2mm_curdesc14_lsb_i,s2mm_curdesc14_msb_i, s2mm_taildesc14_lsb_i, s2mm_taildesc14_msb_i,
s2mm_curdesc15_lsb_i,s2mm_curdesc15_msb_i, s2mm_taildesc15_lsb_i, s2mm_taildesc15_msb_i
)
begin
case tdest_in (3 downto 0) is
when "0000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
when "0001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc1_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc1_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc1_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc1_msb_i;
when "0010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc2_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc2_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc2_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc2_msb_i;
when "0011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc3_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc3_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc3_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc3_msb_i;
when "0100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc4_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc4_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc4_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc4_msb_i;
when "0101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc5_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc5_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc5_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc5_msb_i;
when "0110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc6_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc6_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc6_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc6_msb_i;
when "0111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc7_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc7_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc7_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc7_msb_i;
when "1000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc8_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc8_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc8_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc8_msb_i;
when "1001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc9_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc9_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc9_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc9_msb_i;
when "1010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc10_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc10_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc10_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc10_msb_i;
when "1011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc11_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc11_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc11_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc11_msb_i;
when "1100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc12_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc12_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc12_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc12_msb_i;
when "1101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc13_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc13_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc13_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc13_msb_i;
when "1110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc14_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc14_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc14_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc14_msb_i;
when "1111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc15_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc15_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc15_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc15_msb_i;
when others =>
s2mm_curdesc_lsb_muxed <= (others => '0');
s2mm_curdesc_msb_muxed <= (others => '0');
s2mm_taildesc_lsb_muxed <= (others => '0');
s2mm_taildesc_msb_muxed <= (others => '0');
end case;
end process PROC_DESC_SEL;
end generate GEN_DESC_MUX;
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
-- Cross interrupt out to AXI Lite clock domain
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s2mm_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(axi_lite_reset_n = '0')then
-- s2mm_introut_d1_cdc_tig <= '0';
-- s2mm_introut_to <= '0';
-- else
-- s2mm_introut_d1_cdc_tig <= s2mm_introut_i_cdc_from;
-- s2mm_introut_to <= s2mm_introut_d1_cdc_tig;
-- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
s2mm_introut <= s2mm_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
s2mm_introut <= s2mm_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- Tie S2MM Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_S2MM_REGISTERS : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_dmacr_i <= (others => '0');
s2mm_dmasr_i <= (others => '0');
s2mm_curdesc_lsb_i <= (others => '0');
s2mm_curdesc_msb_i <= (others => '0');
s2mm_taildesc_lsb_i <= (others => '0');
s2mm_taildesc_msb_i <= (others => '0');
s2mm_da_i <= (others => '0');
s2mm_length_i <= (others => '0');
s2mm_length_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_introut <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_tailpntr_updated_int1 <= '0';
s2mm_sgctl <= (others => '0');
end generate GEN_NO_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
read_addr <= axi2ip_rdaddr(9 downto 0);
-- Generate read mux for Scatter Gather Mode
GEN_READ_MUX_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_curdesc_lsb_i ,
mm2s_curdesc_msb_i ,
mm2s_taildesc_lsb_i ,
mm2s_taildesc_msb_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_curdesc_lsb_i ,
s2mm_curdesc_msb_i ,
s2mm_taildesc_lsb_i ,
s2mm_taildesc_msb_i ,
s2mm_curdesc1_lsb_i ,
s2mm_curdesc1_msb_i ,
s2mm_taildesc1_lsb_i ,
s2mm_taildesc1_msb_i ,
s2mm_curdesc2_lsb_i ,
s2mm_curdesc2_msb_i ,
s2mm_taildesc2_lsb_i ,
s2mm_taildesc2_msb_i ,
s2mm_curdesc3_lsb_i ,
s2mm_curdesc3_msb_i ,
s2mm_taildesc3_lsb_i ,
s2mm_taildesc3_msb_i ,
s2mm_curdesc4_lsb_i ,
s2mm_curdesc4_msb_i ,
s2mm_taildesc4_lsb_i ,
s2mm_taildesc4_msb_i ,
s2mm_curdesc5_lsb_i ,
s2mm_curdesc5_msb_i ,
s2mm_taildesc5_lsb_i ,
s2mm_taildesc5_msb_i ,
s2mm_curdesc6_lsb_i ,
s2mm_curdesc6_msb_i ,
s2mm_taildesc6_lsb_i ,
s2mm_taildesc6_msb_i ,
s2mm_curdesc7_lsb_i ,
s2mm_curdesc7_msb_i ,
s2mm_taildesc7_lsb_i ,
s2mm_taildesc7_msb_i ,
s2mm_curdesc8_lsb_i ,
s2mm_curdesc8_msb_i ,
s2mm_taildesc8_lsb_i ,
s2mm_taildesc8_msb_i ,
s2mm_curdesc9_lsb_i ,
s2mm_curdesc9_msb_i ,
s2mm_taildesc9_lsb_i ,
s2mm_taildesc9_msb_i ,
s2mm_curdesc10_lsb_i ,
s2mm_curdesc10_msb_i ,
s2mm_taildesc10_lsb_i ,
s2mm_taildesc10_msb_i ,
s2mm_curdesc11_lsb_i ,
s2mm_curdesc11_msb_i ,
s2mm_taildesc11_lsb_i ,
s2mm_taildesc11_msb_i ,
s2mm_curdesc12_lsb_i ,
s2mm_curdesc12_msb_i ,
s2mm_taildesc12_lsb_i ,
s2mm_taildesc12_msb_i ,
s2mm_curdesc13_lsb_i ,
s2mm_curdesc13_msb_i ,
s2mm_taildesc13_lsb_i ,
s2mm_taildesc13_msb_i ,
s2mm_curdesc14_lsb_i ,
s2mm_curdesc14_msb_i ,
s2mm_taildesc14_lsb_i ,
s2mm_taildesc14_msb_i ,
s2mm_curdesc15_lsb_i ,
s2mm_curdesc15_msb_i ,
s2mm_taildesc15_lsb_i ,
s2mm_taildesc15_msb_i ,
or_sgctl
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_lsb_i;
when MM2S_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_msb_i;
when MM2S_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_lsb_i;
when MM2S_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_msb_i;
when SGCTL_OFFSET =>
ip2axi_rddata <= x"00000" & or_sgctl (7 downto 4) & "0000" & or_sgctl (3 downto 0);
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_lsb_i;
when S2MM_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_msb_i;
when S2MM_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_lsb_i;
when S2MM_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_msb_i;
when S2MM_CURDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_lsb_i;
when S2MM_CURDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_msb_i;
when S2MM_TAILDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_lsb_i;
when S2MM_TAILDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_msb_i;
when S2MM_CURDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_lsb_i;
when S2MM_CURDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_msb_i;
when S2MM_TAILDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_lsb_i;
when S2MM_TAILDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_msb_i;
when S2MM_CURDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_lsb_i;
when S2MM_CURDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_msb_i;
when S2MM_TAILDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_lsb_i;
when S2MM_TAILDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_msb_i;
when S2MM_CURDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_lsb_i;
when S2MM_CURDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_msb_i;
when S2MM_TAILDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_lsb_i;
when S2MM_TAILDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_msb_i;
when S2MM_CURDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_lsb_i;
when S2MM_CURDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_msb_i;
when S2MM_TAILDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_lsb_i;
when S2MM_TAILDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_msb_i;
when S2MM_CURDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_lsb_i;
when S2MM_CURDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_msb_i;
when S2MM_TAILDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_lsb_i;
when S2MM_TAILDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_msb_i;
when S2MM_CURDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_lsb_i;
when S2MM_CURDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_msb_i;
when S2MM_TAILDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_lsb_i;
when S2MM_TAILDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_msb_i;
when S2MM_CURDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_lsb_i;
when S2MM_CURDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_msb_i;
when S2MM_TAILDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_lsb_i;
when S2MM_TAILDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_msb_i;
when S2MM_CURDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_lsb_i;
when S2MM_CURDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_msb_i;
when S2MM_TAILDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_lsb_i;
when S2MM_TAILDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_msb_i;
when S2MM_CURDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_lsb_i;
when S2MM_CURDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_msb_i;
when S2MM_TAILDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_lsb_i;
when S2MM_TAILDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_msb_i;
when S2MM_CURDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_lsb_i;
when S2MM_CURDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_msb_i;
when S2MM_TAILDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_lsb_i;
when S2MM_TAILDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_msb_i;
when S2MM_CURDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_lsb_i;
when S2MM_CURDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_msb_i;
when S2MM_TAILDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_lsb_i;
when S2MM_TAILDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_msb_i;
when S2MM_CURDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_lsb_i;
when S2MM_CURDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_msb_i;
when S2MM_TAILDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_lsb_i;
when S2MM_TAILDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_msb_i;
when S2MM_CURDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_lsb_i;
when S2MM_CURDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_msb_i;
when S2MM_TAILDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_lsb_i;
when S2MM_TAILDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_msb_i;
when S2MM_CURDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_lsb_i;
when S2MM_CURDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_msb_i;
when S2MM_TAILDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_lsb_i;
when S2MM_TAILDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_msb_i;
-- coverage off
when others =>
ip2axi_rddata <= (others => '0');
-- coverage on
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SG;
-- Generate read mux for Simple DMA Mode
GEN_READ_MUX_FOR_SMPL_DMA : if C_INCLUDE_SG = 0 generate
begin
ADDR32_MSB : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_msb_sa <= (others => '0');
s2mm_msb_sa <= (others => '0');
end generate ADDR32_MSB;
ADDR64_MSB : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_msb_sa <= mm2s_sa_i (63 downto 32);
s2mm_msb_sa <= s2mm_da_i (63 downto 32);
end generate ADDR64_MSB;
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_sa_i (31 downto 0) ,
mm2s_length_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_da_i (31 downto 0) ,
s2mm_length_i ,
mm2s_msb_sa ,
s2mm_msb_sa
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_SA_OFFSET =>
ip2axi_rddata <= mm2s_sa_i (31 downto 0);
when MM2S_SA2_OFFSET =>
ip2axi_rddata <= mm2s_msb_sa; --mm2s_sa_i (63 downto 32);
when MM2S_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & mm2s_length_i;
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_DA_OFFSET =>
ip2axi_rddata <= s2mm_da_i (31 downto 0);
when S2MM_DA2_OFFSET =>
ip2axi_rddata <= s2mm_msb_sa; --s2mm_da_i (63 downto 32);
when S2MM_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & s2mm_length_i;
when others =>
ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SMPL_DMA;
end implementation;
|
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Multiplexor Channel registers FO & FB
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Revise XH & XL BU latches amd MPX_INTRPT signal
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.PH;
use work.FLVL;
entity MpxFOFB is
Port ( MPX_ROS_LCH : in STD_LOGIC;
S_REG_0 : in STD_LOGIC;
SET_FW : in STD_LOGIC;
S_REG_1 : in STD_LOGIC;
S_REG_2 : in STD_LOGIC;
T3 : in STD_LOGIC;
CK_SALS : in STD_LOGIC_VECTOR (0 to 3);
PK_SALS : in STD_LOGIC;
FBK_T2 : in STD_LOGIC;
MACH_RST_SET_LCH : in STD_LOGIC;
SALS_CS : in STD_LOGIC_VECTOR (0 to 3);
SALS_SA : in STD_LOGIC;
CK_0_PWR : in STD_LOGIC;
R_REG : in STD_LOGIC_VECTOR (0 to 8);
T1,T2 : in STD_LOGIC;
XXH : out STD_LOGIC;
XH : out STD_LOGIC;
XL : out STD_LOGIC;
FT_7_BIT_MPX_CHNL_INTRP : out STD_LOGIC;
FT_2_BIT_MPX_OPN_LCH : out STD_LOGIC;
SUPPR_CTRL_LCH : out STD_LOGIC;
OP_OUT_SIG : out STD_LOGIC;
MPX_OPN_LT_GATE : out STD_LOGIC;
MACH_RST_MPX : out STD_LOGIC;
MPX_INTRPT : out STD_LOGIC;
SX1_MASK : out STD_LOGIC;
EXT_TRAP_MASK_ON : out STD_LOGIC;
SX2_MASK : out STD_LOGIC;
FAK : out STD_LOGIC;
SET_BUS_O_CTRL_LCH : out STD_LOGIC;
MPX_BUS_O_REG : out STD_LOGIC_VECTOR (0 to 8);
clk : in STD_LOGIC);
end MpxFOFB;
architecture FMD of MpxFOFB is
signal sXXH,sXH,sXL,T3SET,X_SET : STD_LOGIC;
signal XXH_IN,XH_IN,XL_IN : STD_LOGIC;
signal XXHBU,XHBU,XLBU : STD_LOGIC;
signal sMACH_RST_MPX : STD_LOGIC;
signal CK11XX, CKX11X,CKX1X1,CK1X1X,CKXX11 : STD_LOGIC;
signal CHNL_L,OPN_L,SUPPR_L,OUT_L : STD_LOGIC;
signal notOP_OUT_SIG,MpxMask : STD_LOGIC;
alias KP is PK_SALS;
signal sFAK,sSET_BUS_O_CTRL : STD_LOGIC;
signal BusO_Set,BusO_Reset : STD_LOGIC_VECTOR (0 to 8);
signal sFT_7_BIT_MPX_CHNL_INTRP,sFT_2_BIT_MPX_OPN_LCH,sSUPPR_CTRL_LCH : STD_LOGIC;
begin
-- XL, XH and XXL bits and backup
XXH_BU: entity PH port map (D=>sXXH, L=>SET_FW, Q=> XXHBU);
XXH_IN <= (XXHBU and MPX_ROS_LCH) or (S_REG_0 and not MPX_ROS_LCH);
X_SET <= T3SET or sMACH_RST_MPX;
XXH_PH: entity PH port map (D=>XXH_IN, L=>X_SET, Q=> sXXH);
XXH <= sXXH;
XH_BU: entity PH port map (D=>sXH, L=>SET_FW, Q=> XHBU);
-- XH_IN <= (XHBU and MPX_ROS_LCH) or (not S_REG_1 and not MPX_ROS_LCH);
XH_IN <= (XHBU and MPX_ROS_LCH) or (S_REG_1 and not MPX_ROS_LCH);
XH_PH: entity PH port map (D=>XH_IN, L=>X_SET, Q=>sXH);
XH <= sXH;
XL_BU: entity PH port map (D=>sXL, L=>SET_FW, Q=> XLBU);
-- XL_IN <= (XLBU and MPX_ROS_LCH) or (not S_REG_2 and not MPX_ROS_LCH);
XL_IN <= (XLBU and MPX_ROS_LCH) or (S_REG_2 and not MPX_ROS_LCH);
XL_PH: entity PH port map (D=>XL_IN, L=>X_SET, Q=>sXL);
XL <= sXL;
-- MPX Flags
T3SET <= (MPX_ROS_LCH and T3) or (FBK_T2 and CK_SALS(0) and CK_SALS(3));
sMACH_RST_MPX <= MACH_RST_SET_LCH;
MACH_RST_MPX <= sMACH_RST_MPX;
CK11XX <= CK_SALS(0) and CK_SALS(1) and FBK_T2;
CHNL_L <= sMACH_RST_MPX or CK11XX;
MPX_CHNL: entity PH port map (D=>KP,L=>CHNL_L,Q=>sFT_7_BIT_MPX_CHNL_INTRP);
FT_7_BIT_MPX_CHNL_INTRP <= sFT_7_BIT_MPX_CHNL_INTRP;
CKX11X <= CK_SALS(1) and CK_SALS(2) and FBK_T2;
OPN_L <= sMACH_RST_MPX or CKX11X;
MPX_OPN: entity PH port map (D=>KP,L=>OPN_L,Q=>sFT_2_BIT_MPX_OPN_LCH);
FT_2_BIT_MPX_OPN_LCH <= sFT_2_BIT_MPX_OPN_LCH;
CK1X1X <= CK_SALS(0) and CK_SALS(2) and FBK_T2;
SUPPR_L <= sMACH_RST_MPX or CK1X1X;
SUPPR_CTRL: entity PH port map (D=>KP,L=>SUPPR_L,Q=>sSUPPR_CTRL_LCH);
SUPPR_CTRL_LCH <= sSUPPR_CTRL_LCH;
CKX1X1 <= CK_SALS(1) and CK_SALS(3) and FBK_T2;
OUT_L <= sMACH_RST_MPX or CKX1X1;
OP_OUT_CTRL: entity PH port map (D=>KP,L=>OUT_L,Q=>notOP_OUT_SIG);
OP_OUT_SIG <= not notOP_OUT_SIG;
MPX_OPN_LT_GATE <= CKX11X;
-- External Interrupt Masks
-- ?? Should the R_REG bits be inverted before use?
CKXX11 <= CK_SALS(2) and CK_SALS(3) and FBK_T2;
MPX_MASK: entity PH port map (D=>R_REG(0),L=>CKXX11,Q=>MPXMask);
MPX_INTRPT <= sFT_7_BIT_MPX_CHNL_INTRP and MPXMask;
SX1MASK: entity PH port map (D=>R_REG(1),L=>CKXX11,Q=>SX1_MASK);
EXT_MASK: entity PH port map (D=>R_REG(7),L=>CKXX11,Q=>EXT_TRAP_MASK_ON);
SX2MASK: entity PH port map (D=>R_REG(2),L=>CKXX11,Q=>SX2_MASK);
-- MPX BUS OUT REGISTER
sFAK <= SALS_CS(0) and SALS_CS(1) and SALS_CS(2) and SALS_CS(3) and not SALS_SA;
FAK <= sFAK;
sSET_BUS_O_CTRL <= sFAK and CK_0_PWR;
SET_BUS_O_CTRL_LCH <= sSET_BUS_O_CTRL;
BusO_Set <= R_REG and (0 to 8=>(sSET_BUS_O_CTRL and T2)); -- ??? "and T2" added to prevent incorrect setting of BUS_O
BusO_Reset <= (0 to 8=>sSET_BUS_O_CTRL and T1);
MPX_BUSO: entity FLVL port map (S=>BusO_Set,R=>BusO_Reset,Q=>MPX_BUS_O_REG);
end FMD;
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: bv_test-bench.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 20:13:16 $
--
--------------------------------------------------------------------------
--
-- Architecture for test bench for bit vector arithmetic package.
--
use std.textio.all, work.bv_arithmetic.all;
architecture bench of bv_test is
begin
process
variable L : line;
variable byte : bit_vector(0 to 7);
variable word : bit_vector(1 to 32);
variable half_byte : bit_vector(1 to 4);
variable overflow, div_by_zero, result : boolean;
begin
WAIT for 1 ns;
----------------------------------------------------------------
----------------------------------------------------------------
-- test bit_vector to numeric conversions
----------------------------------------------------------------
----------------------------------------------------------------
write(L, string'("Testing bv_to_natural:"));
writeline(output, L);
write(L, string'(" bv_to_natural(X""02"") = "));
write(L, bv_to_natural(X"02"));
writeline(output, L);
assert bv_to_natural(X"02") = 2;
write(L, string'(" bv_to_natural(X""FE"") = "));
write(L, bv_to_natural(X"FE"));
writeline(output, L);
assert bv_to_natural(X"FE") = 254;
----------------------------------------------------------------
write(L, string'("Testing natural_to_bv:"));
writeline(output, L);
write(L, string'(" natural_to_bv(2) = "));
write(L, natural_to_bv(2, 8));
writeline(output, L);
assert natural_to_bv(2, 8) = X"02";
write(L, string'(" natural_to_bv(254) = "));
write(L, natural_to_bv(254, 8));
writeline(output, L);
assert natural_to_bv(254, 8) = X"FE";
----------------------------------------------------------------
write(L, string'("Testing bv_to_integer:"));
writeline(output, L);
write(L, string'(" bv_to_integer(X""02"") = "));
write(L, bv_to_integer(X"02"));
writeline(output, L);
assert bv_to_integer(X"02") = 2;
write(L, string'(" bv_to_integer(X""FE"") = "));
write(L, bv_to_integer(X"FE"));
writeline(output, L);
assert bv_to_integer(X"FE") = -2;
----------------------------------------------------------------
write(L, string'("Testing integer_to_bv:"));
writeline(output, L);
write(L, string'(" integer_to_bv(2) = "));
write(L, integer_to_bv(2, 8));
writeline(output, L);
assert integer_to_bv(2, 8) = X"02";
write(L, string'(" integer_to_bv(-2) = "));
write(L, integer_to_bv(-2, 8));
writeline(output, L);
assert integer_to_bv(-2, 8) = X"FE";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic operations
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_add: Signed addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_add with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_add(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 2+(-3) = "));
bv_add(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FF" and not overflow;
write(L, string'(" 64+64 = "));
bv_add(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64+(-64) = "));
bv_add(X"C0", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "+": Signed addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""+"" without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
byte := X"02" + X"02";
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 2+(-3) = "));
byte := X"02" + X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"FF";
write(L, string'(" 64+64 = "));
byte := X"40" + X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64+(-64) = "));
byte := X"C0" + X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_sub: Signed subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sub with overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
bv_sub(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 2-(-3) = "));
bv_sub(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"05" and not overflow;
write(L, string'(" 64-(-64) = "));
bv_sub(X"40", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64-64 = "));
bv_sub(X"C0", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "-": Signed subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
byte := X"02" - X"02";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 2-(-3) = "));
byte := X"02" - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"05";
write(L, string'(" 64-(-64) = "));
byte := X"40" - X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64-64 = "));
byte := X"C0" - X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_addu: Unsigned addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_addu(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 64+64 = "));
bv_addu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 128+128 = "));
bv_addu(X"80", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_addu: Unsigned addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_addu(X"02", X"02", byte);
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 64+64 = "));
bv_addu(X"40", X"40", byte);
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 128+128 = "));
bv_addu(X"80", X"80", byte);
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu with overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
bv_subu(X"03", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"01" and not overflow;
write(L, string'(" 64-64 = "));
bv_subu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 64-128 = "));
bv_subu(X"40", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"C0" and overflow;
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu without overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
bv_subu(X"03", X"02", byte);
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 64-64 = "));
bv_subu(X"40", X"40", byte);
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 64-128 = "));
bv_subu(X"40", X"80", byte);
write(L, byte);
writeline(output, L);
assert byte = X"C0";
----------------------------------------------------------------
-- bv_neg: Signed negation with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_neg with overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
bv_neg(X"03", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not overflow;
write(L, string'(" -(-3) = "));
bv_neg(X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not overflow;
write(L, string'(" -(127) = "));
bv_neg(X"7F", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"81" and not overflow;
write(L, string'(" -(-128) = "));
bv_neg(X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
----------------------------------------------------------------
-- "-": Signed negation without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
byte := - X"03";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -(-3) = "));
byte := - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -(127) = "));
byte := - X"7F";
write(L, byte);
writeline(output, L);
assert byte = X"81";
write(L, string'(" -(-128) = "));
byte := - X"80";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_mult: Signed multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_mult with overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
bv_mult(X"05", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"F1" and not overflow;
write(L, string'(" (-5)*(-3) = "));
bv_mult(X"FB", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"0F" and not overflow;
write(L, string'(" 16*8 = "));
bv_mult(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" 16*16 = "));
bv_mult(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
write(L, string'(" 16*(-8) = "));
bv_mult(X"10", X"F8", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*(-16) = "));
bv_mult(X"10", X"F0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- "*": Signed multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""*"" without overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
byte := X"05" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"F1";
write(L, string'(" (-5)*(-3) = "));
byte := X"FB" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"0F";
write(L, string'(" 16*8 = "));
byte := X"10" * X"08";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
byte := X"10" * X"10";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 16*(-8) = "));
byte := X"10" * X"F8";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*(-16) = "));
byte := X"10" * X"F0";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu with overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
bv_multu(X"05", X"07", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"23" and not overflow;
write(L, string'(" 16*8 = "));
bv_multu(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*16 = "));
bv_multu(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu without overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
bv_multu(X"05", X"07", byte);
write(L, byte);
writeline(output, L);
assert byte = X"23";
write(L, string'(" 16*8 = "));
bv_multu(X"10", X"08", byte);
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
bv_multu(X"10", X"10", byte);
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_div: Signed division with divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_div with flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_div(X"07", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -7/2 = "));
bv_div(X"F9", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" 7/-2 = "));
bv_div(X"07", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" -7/-2 = "));
bv_div(X"F9", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -128/1 = "));
bv_div(X"80", X"01", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and not overflow;
write(L, string'(" -128/-1 = "));
bv_div(X"80", X"FF", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and overflow;
write(L, string'(" -16/0 = "));
bv_div(X"F0", X"00", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and div_by_zero and not overflow;
----------------------------------------------------------------
-- "/": Signed division without divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""/"" without flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
byte := X"07" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -7/2 = "));
byte := X"F9" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" 7/-2 = "));
byte := X"07" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -7/-2 = "));
byte := X"F9" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -128/1 = "));
byte := X"80" / X"01";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -128/-1 = "));
byte := X"80" / X"FF";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -16/0 = "));
byte := X"F0" / X"00";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_divu: Unsigned division with divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu with flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_divu(X"07", X"02", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"03" and not div_by_zero;
write(L, string'(" 14/7 = "));
bv_divu(X"0E", X"07", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"02" and not div_by_zero;
write(L, string'(" 16/1 = "));
bv_divu(X"10", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and not div_by_zero;
write(L, string'(" 16/0 = "));
bv_divu(X"10", X"00", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and div_by_zero;
write(L, string'(" 16/16 = "));
bv_divu(X"10", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"01" and not div_by_zero;
write(L, string'(" 1/16 = "));
bv_divu(X"01", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"00" and not div_by_zero;
write(L, string'(" 255/1 = "));
bv_divu(X"FF", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"FF" and not div_by_zero;
----------------------------------------------------------------
-- bv_divu: Unsigned division without divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu without flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_divu(X"07", X"02", byte);
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" 14/7 = "));
bv_divu(X"0E", X"07", byte);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" 16/1 = "));
bv_divu(X"10", X"01", byte);
write(L, byte);
writeline(output, L);
assert byte = X"10";
write(L, string'(" 16/0 = "));
bv_divu(X"10", X"00", byte);
write(L, byte);
writeline(output, L);
assert byte = X"10";
write(L, string'(" 16/16 = "));
bv_divu(X"10", X"10", byte);
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 1/16 = "));
bv_divu(X"01", X"10", byte);
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 255/1 = "));
bv_divu(X"FF", X"01", byte);
write(L, byte);
writeline(output, L);
assert byte = X"FF";
----------------------------------------------------------------
----------------------------------------------------------------
-- Logical operators
-- (Provided for VHDL-87, built in for VHDL-93)
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_sll: Shift left logical (fill with '0' bits)
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sll:"));
writeline(output, L);
write(L, string'(" 10100101 sll 4 = "));
byte := bv_sll(B"10100101", 4);
write(L, byte);
writeline(output, L);
assert byte = B"01010000";
----------------------------------------------------------------
-- bv_srl: Shift right logical (fill with '0' bits)
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_srl:"));
writeline(output, L);
write(L, string'(" 10100101 srl 4 = "));
byte := bv_srl(B"10100101", 4);
write(L, byte);
writeline(output, L);
assert byte = B"00001010";
----------------------------------------------------------------
-- bv_sra: Shift right arithmetic (fill with copy of sign bit)
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sra:"));
writeline(output, L);
write(L, string'(" 01011010 sra 4 = "));
byte := bv_sra(B"01011010", 4);
write(L, byte);
writeline(output, L);
assert byte = B"00000101";
write(L, string'(" 10100101 sra 4 = "));
byte := bv_sra(B"10100101", 4);
write(L, byte);
writeline(output, L);
assert byte = B"11111010";
----------------------------------------------------------------
-- bv_rol: Rotate left
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_rol:"));
writeline(output, L);
write(L, string'(" 10100101 rol 3 = "));
byte := bv_rol(B"10100101", 3);
write(L, byte);
writeline(output, L);
assert byte = B"00101101";
----------------------------------------------------------------
-- bv_rol: Rotate right
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_ror:"));
writeline(output, L);
write(L, string'(" 10100101 ror 3 = "));
byte := bv_ror(B"10100101", 3);
write(L, byte);
writeline(output, L);
assert byte = B"10110100";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic comparison operators.
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_lt: Signed less than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_lt:"));
writeline(output, L);
write(L, string'(" 2 < 2 = "));
result := bv_lt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 2 < 3 = "));
result := bv_lt(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 < 2 = "));
result := bv_lt(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 < -3 = "));
result := bv_lt(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_le: Signed less than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_le:"));
writeline(output, L);
write(L, string'(" 2 <= 2 = "));
result := bv_le(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= 3 = "));
result := bv_le(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 <= 2 = "));
result := bv_le(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= -3 = "));
result := bv_le(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_gt: Signed greater than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_gt:"));
writeline(output, L);
write(L, string'(" 2 > 2 = "));
result := bv_gt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 3 > 2 = "));
result := bv_gt(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 > -2 = "));
result := bv_gt(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 > 2 = "));
result := bv_gt(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_ge: Signed greater than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_ge:"));
writeline(output, L);
write(L, string'(" 2 >= 2 = "));
result := bv_ge(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 3 >= 2 = "));
result := bv_ge(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 >= -2 = "));
result := bv_ge(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 >= 2 = "));
result := bv_ge(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
----------------------------------------------------------------
-- Extension operators - convert a bit vector to a longer one
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_sext: Sign extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sext:"));
writeline(output, L);
write(L, string'(" sext(X""02"", 32) = "));
word := bv_sext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" sext(X""FE"", 32) = "));
word := bv_sext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"FFFFFFFE";
write(L, string'(" sext(X""02"", 8) = "));
byte := bv_sext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" sext(X""FE"", 8) = "));
byte := bv_sext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" sext(X""02"", 4) = "));
half_byte := bv_sext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" sext(X""FE"", 4) = "));
half_byte := bv_sext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
----------------------------------------------------------------
-- bv_zext" Zero extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_zext:"));
writeline(output, L);
write(L, string'(" zext(X""02"", 32) = "));
word := bv_zext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" zext(X""FE"", 32) = "));
word := bv_zext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"000000FE";
write(L, string'(" zext(X""02"", 8) = "));
byte := bv_zext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" zext(X""FE"", 8) = "));
byte := bv_zext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" zext(X""02"", 4) = "));
half_byte := bv_zext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" zext(X""FE"", 4) = "));
half_byte := bv_zext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
wait;
end process;
end bench;
|
-- This VHDL was converted from Verilog using the
-- Icarus Verilog VHDL Code Generator 0.10.0 (devel) (s20090923-519-g6ce96cc)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity subtract is
port (
a : in unsigned(3 downto 0);
b : in unsigned(3 downto 0);
out_sig : out unsigned(3 downto 0)
);
end entity;
architecture test of subtract is
begin
out_sig <= (a + not b) + 1;
end architecture;
|
-- This VHDL was converted from Verilog using the
-- Icarus Verilog VHDL Code Generator 0.10.0 (devel) (s20090923-519-g6ce96cc)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity subtract is
port (
a : in unsigned(3 downto 0);
b : in unsigned(3 downto 0);
out_sig : out unsigned(3 downto 0)
);
end entity;
architecture test of subtract is
begin
out_sig <= (a + not b) + 1;
end architecture;
|
-- This VHDL was converted from Verilog using the
-- Icarus Verilog VHDL Code Generator 0.10.0 (devel) (s20090923-519-g6ce96cc)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity subtract is
port (
a : in unsigned(3 downto 0);
b : in unsigned(3 downto 0);
out_sig : out unsigned(3 downto 0)
);
end entity;
architecture test of subtract is
begin
out_sig <= (a + not b) + 1;
end architecture;
|
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