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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu_tb is
end entity;
architecture tb of nano_cpu_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ram_addr : std_logic_vector(9 downto 0);
signal ram_en : std_logic;
signal ram_we : std_logic;
signal ram_wdata : std_logic_vector(15 downto 0);
signal ram_rdata : std_logic_vector(15 downto 0);
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
type t_instructions is array(natural range <>) of std_logic_vector(15 downto 0);
-- constant c_load : std_logic_vector(15 downto 11) := X"0" & '1'; -- load
-- constant c_or : std_logic_vector(15 downto 11) := X"1" & '1'; -- or
-- constant c_and : std_logic_vector(15 downto 11) := X"2" & '1'; -- and
-- constant c_xor : std_logic_vector(15 downto 11) := X"3" & '1'; -- xor
-- constant c_add : std_logic_vector(15 downto 11) := X"4" & '1'; -- add
-- constant c_sub : std_logic_vector(15 downto 11) := X"5" & '1'; -- sub
-- constant c_compare : std_logic_vector(15 downto 11) := X"5" & '0'; -- sub
-- constant c_store : std_logic_vector(15 downto 11) := X"8" & '0'; -- xxx
-- constant c_load_ind : std_logic_vector(15 downto 11) := X"8" & '1'; -- load
-- constant c_store_ind: std_logic_vector(15 downto 11) := X"9" & '0'; -- xxx
-- constant c_out : std_logic_vector(15 downto 11) := X"A" & '0'; -- xxx
-- constant c_in : std_logic_vector(15 downto 11) := X"A" & '1'; -- load
--
-- -- Specials
-- constant c_return : std_logic_vector(15 downto 11) := X"B" & '1'; -- xxx
-- constant c_branch : std_logic_vector(15 downto 14) := "11";
--
-- -- Branches (bit 10..0) are address
-- constant c_br_eq : std_logic_vector(13 downto 11) := "000"; -- zero
-- constant c_br_neq : std_logic_vector(13 downto 11) := "001"; -- not zero
-- constant c_br_mi : std_logic_vector(13 downto 11) := "010"; -- negative
-- constant c_br_pl : std_logic_vector(13 downto 11) := "011"; -- not negative
-- constant c_br_always: std_logic_vector(13 downto 11) := "100"; -- always (jump)
-- constant c_br_call : std_logic_vector(13 downto 11) := "101"; -- always (call)
--
constant c_program : t_instructions := (
X"0840", -- 00 -- load $40
X"804E", -- 01 -- store $44
X"4841", -- 02 -- add $41
X"8045", -- 03 -- store $45
X"0840", -- 04 -- load $40
X"1841", -- 05 -- or $41
X"8046", -- 06 -- store $46
X"0840", -- 07 -- load $40
X"2841", -- 08 -- and $41
X"8047", -- 09 -- store $47
X"8842", -- 0a -- load ($42)
X"9043", -- 0b -- store ($43)
X"0840", -- 0c -- load $40
X"5041", -- 0d -- comp $41
X"C000", -- 0e -- equal? => 0
X"D800", -- 0f -- not negative? => 0
X"A055", -- 10 -- out to $55
X"6857", -- 11 -- in from $57
X"E818", -- 12 -- call $18
X"8048", -- 13 -- store $48
X"E01A", -- 14 -- jump $1a
X"0000", -- 15
X"0000", -- 16
X"0000", -- 17
X"0844", -- 18 -- load $44
X"B800", -- 19 -- return
X"6801", -- 1A -- in 1
X"804F", -- 1B -- store in $4f
X"A002", -- 1C -- out to $2
X"5842", -- 1D -- sub 1
X"C81C", -- 1E -- bne $1d
X"E01F" -- 1F -- jump self
);
constant c_data : t_instructions(64 to 68) := (
X"237A",
X"59B2",
X"0001",
X"0049",
X"FFFF" );
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano_cpu
port map (
clock => clock,
reset => reset,
-- instruction/data ram
ram_addr => ram_addr,
ram_en => ram_en,
ram_we => ram_we,
ram_wdata => ram_wdata,
ram_rdata => ram_rdata,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
p_ram: process
variable ram : t_instructions(0 to 1023) := (others => (others => '1'));
begin
ram(c_program'range) := c_program;
ram(c_data'range) := c_data;
while true loop
wait until clock='1';
if ram_en='1' then
ram_rdata <= ram(to_integer(unsigned(ram_addr)));
if ram_we='1' then
ram(to_integer(unsigned(ram_addr))) := ram_wdata;
end if;
end if;
end loop;
end process;
io_rdata <= X"0006";
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu_tb is
end entity;
architecture tb of nano_cpu_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ram_addr : std_logic_vector(9 downto 0);
signal ram_en : std_logic;
signal ram_we : std_logic;
signal ram_wdata : std_logic_vector(15 downto 0);
signal ram_rdata : std_logic_vector(15 downto 0);
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
type t_instructions is array(natural range <>) of std_logic_vector(15 downto 0);
-- constant c_load : std_logic_vector(15 downto 11) := X"0" & '1'; -- load
-- constant c_or : std_logic_vector(15 downto 11) := X"1" & '1'; -- or
-- constant c_and : std_logic_vector(15 downto 11) := X"2" & '1'; -- and
-- constant c_xor : std_logic_vector(15 downto 11) := X"3" & '1'; -- xor
-- constant c_add : std_logic_vector(15 downto 11) := X"4" & '1'; -- add
-- constant c_sub : std_logic_vector(15 downto 11) := X"5" & '1'; -- sub
-- constant c_compare : std_logic_vector(15 downto 11) := X"5" & '0'; -- sub
-- constant c_store : std_logic_vector(15 downto 11) := X"8" & '0'; -- xxx
-- constant c_load_ind : std_logic_vector(15 downto 11) := X"8" & '1'; -- load
-- constant c_store_ind: std_logic_vector(15 downto 11) := X"9" & '0'; -- xxx
-- constant c_out : std_logic_vector(15 downto 11) := X"A" & '0'; -- xxx
-- constant c_in : std_logic_vector(15 downto 11) := X"A" & '1'; -- load
--
-- -- Specials
-- constant c_return : std_logic_vector(15 downto 11) := X"B" & '1'; -- xxx
-- constant c_branch : std_logic_vector(15 downto 14) := "11";
--
-- -- Branches (bit 10..0) are address
-- constant c_br_eq : std_logic_vector(13 downto 11) := "000"; -- zero
-- constant c_br_neq : std_logic_vector(13 downto 11) := "001"; -- not zero
-- constant c_br_mi : std_logic_vector(13 downto 11) := "010"; -- negative
-- constant c_br_pl : std_logic_vector(13 downto 11) := "011"; -- not negative
-- constant c_br_always: std_logic_vector(13 downto 11) := "100"; -- always (jump)
-- constant c_br_call : std_logic_vector(13 downto 11) := "101"; -- always (call)
--
constant c_program : t_instructions := (
X"0840", -- 00 -- load $40
X"804E", -- 01 -- store $44
X"4841", -- 02 -- add $41
X"8045", -- 03 -- store $45
X"0840", -- 04 -- load $40
X"1841", -- 05 -- or $41
X"8046", -- 06 -- store $46
X"0840", -- 07 -- load $40
X"2841", -- 08 -- and $41
X"8047", -- 09 -- store $47
X"8842", -- 0a -- load ($42)
X"9043", -- 0b -- store ($43)
X"0840", -- 0c -- load $40
X"5041", -- 0d -- comp $41
X"C000", -- 0e -- equal? => 0
X"D800", -- 0f -- not negative? => 0
X"A055", -- 10 -- out to $55
X"6857", -- 11 -- in from $57
X"E818", -- 12 -- call $18
X"8048", -- 13 -- store $48
X"E01A", -- 14 -- jump $1a
X"0000", -- 15
X"0000", -- 16
X"0000", -- 17
X"0844", -- 18 -- load $44
X"B800", -- 19 -- return
X"6801", -- 1A -- in 1
X"804F", -- 1B -- store in $4f
X"A002", -- 1C -- out to $2
X"5842", -- 1D -- sub 1
X"C81C", -- 1E -- bne $1d
X"E01F" -- 1F -- jump self
);
constant c_data : t_instructions(64 to 68) := (
X"237A",
X"59B2",
X"0001",
X"0049",
X"FFFF" );
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano_cpu
port map (
clock => clock,
reset => reset,
-- instruction/data ram
ram_addr => ram_addr,
ram_en => ram_en,
ram_we => ram_we,
ram_wdata => ram_wdata,
ram_rdata => ram_rdata,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
p_ram: process
variable ram : t_instructions(0 to 1023) := (others => (others => '1'));
begin
ram(c_program'range) := c_program;
ram(c_data'range) := c_data;
while true loop
wait until clock='1';
if ram_en='1' then
ram_rdata <= ram(to_integer(unsigned(ram_addr)));
if ram_we='1' then
ram(to_integer(unsigned(ram_addr))) := ram_wdata;
end if;
end if;
end loop;
end process;
io_rdata <= X"0006";
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu_tb is
end entity;
architecture tb of nano_cpu_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ram_addr : std_logic_vector(9 downto 0);
signal ram_en : std_logic;
signal ram_we : std_logic;
signal ram_wdata : std_logic_vector(15 downto 0);
signal ram_rdata : std_logic_vector(15 downto 0);
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
type t_instructions is array(natural range <>) of std_logic_vector(15 downto 0);
-- constant c_load : std_logic_vector(15 downto 11) := X"0" & '1'; -- load
-- constant c_or : std_logic_vector(15 downto 11) := X"1" & '1'; -- or
-- constant c_and : std_logic_vector(15 downto 11) := X"2" & '1'; -- and
-- constant c_xor : std_logic_vector(15 downto 11) := X"3" & '1'; -- xor
-- constant c_add : std_logic_vector(15 downto 11) := X"4" & '1'; -- add
-- constant c_sub : std_logic_vector(15 downto 11) := X"5" & '1'; -- sub
-- constant c_compare : std_logic_vector(15 downto 11) := X"5" & '0'; -- sub
-- constant c_store : std_logic_vector(15 downto 11) := X"8" & '0'; -- xxx
-- constant c_load_ind : std_logic_vector(15 downto 11) := X"8" & '1'; -- load
-- constant c_store_ind: std_logic_vector(15 downto 11) := X"9" & '0'; -- xxx
-- constant c_out : std_logic_vector(15 downto 11) := X"A" & '0'; -- xxx
-- constant c_in : std_logic_vector(15 downto 11) := X"A" & '1'; -- load
--
-- -- Specials
-- constant c_return : std_logic_vector(15 downto 11) := X"B" & '1'; -- xxx
-- constant c_branch : std_logic_vector(15 downto 14) := "11";
--
-- -- Branches (bit 10..0) are address
-- constant c_br_eq : std_logic_vector(13 downto 11) := "000"; -- zero
-- constant c_br_neq : std_logic_vector(13 downto 11) := "001"; -- not zero
-- constant c_br_mi : std_logic_vector(13 downto 11) := "010"; -- negative
-- constant c_br_pl : std_logic_vector(13 downto 11) := "011"; -- not negative
-- constant c_br_always: std_logic_vector(13 downto 11) := "100"; -- always (jump)
-- constant c_br_call : std_logic_vector(13 downto 11) := "101"; -- always (call)
--
constant c_program : t_instructions := (
X"0840", -- 00 -- load $40
X"804E", -- 01 -- store $44
X"4841", -- 02 -- add $41
X"8045", -- 03 -- store $45
X"0840", -- 04 -- load $40
X"1841", -- 05 -- or $41
X"8046", -- 06 -- store $46
X"0840", -- 07 -- load $40
X"2841", -- 08 -- and $41
X"8047", -- 09 -- store $47
X"8842", -- 0a -- load ($42)
X"9043", -- 0b -- store ($43)
X"0840", -- 0c -- load $40
X"5041", -- 0d -- comp $41
X"C000", -- 0e -- equal? => 0
X"D800", -- 0f -- not negative? => 0
X"A055", -- 10 -- out to $55
X"6857", -- 11 -- in from $57
X"E818", -- 12 -- call $18
X"8048", -- 13 -- store $48
X"E01A", -- 14 -- jump $1a
X"0000", -- 15
X"0000", -- 16
X"0000", -- 17
X"0844", -- 18 -- load $44
X"B800", -- 19 -- return
X"6801", -- 1A -- in 1
X"804F", -- 1B -- store in $4f
X"A002", -- 1C -- out to $2
X"5842", -- 1D -- sub 1
X"C81C", -- 1E -- bne $1d
X"E01F" -- 1F -- jump self
);
constant c_data : t_instructions(64 to 68) := (
X"237A",
X"59B2",
X"0001",
X"0049",
X"FFFF" );
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano_cpu
port map (
clock => clock,
reset => reset,
-- instruction/data ram
ram_addr => ram_addr,
ram_en => ram_en,
ram_we => ram_we,
ram_wdata => ram_wdata,
ram_rdata => ram_rdata,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
p_ram: process
variable ram : t_instructions(0 to 1023) := (others => (others => '1'));
begin
ram(c_program'range) := c_program;
ram(c_data'range) := c_data;
while true loop
wait until clock='1';
if ram_en='1' then
ram_rdata <= ram(to_integer(unsigned(ram_addr)));
if ram_we='1' then
ram(to_integer(unsigned(ram_addr))) := ram_wdata;
end if;
end if;
end loop;
end process;
io_rdata <= X"0006";
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu_tb is
end entity;
architecture tb of nano_cpu_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ram_addr : std_logic_vector(9 downto 0);
signal ram_en : std_logic;
signal ram_we : std_logic;
signal ram_wdata : std_logic_vector(15 downto 0);
signal ram_rdata : std_logic_vector(15 downto 0);
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
type t_instructions is array(natural range <>) of std_logic_vector(15 downto 0);
-- constant c_load : std_logic_vector(15 downto 11) := X"0" & '1'; -- load
-- constant c_or : std_logic_vector(15 downto 11) := X"1" & '1'; -- or
-- constant c_and : std_logic_vector(15 downto 11) := X"2" & '1'; -- and
-- constant c_xor : std_logic_vector(15 downto 11) := X"3" & '1'; -- xor
-- constant c_add : std_logic_vector(15 downto 11) := X"4" & '1'; -- add
-- constant c_sub : std_logic_vector(15 downto 11) := X"5" & '1'; -- sub
-- constant c_compare : std_logic_vector(15 downto 11) := X"5" & '0'; -- sub
-- constant c_store : std_logic_vector(15 downto 11) := X"8" & '0'; -- xxx
-- constant c_load_ind : std_logic_vector(15 downto 11) := X"8" & '1'; -- load
-- constant c_store_ind: std_logic_vector(15 downto 11) := X"9" & '0'; -- xxx
-- constant c_out : std_logic_vector(15 downto 11) := X"A" & '0'; -- xxx
-- constant c_in : std_logic_vector(15 downto 11) := X"A" & '1'; -- load
--
-- -- Specials
-- constant c_return : std_logic_vector(15 downto 11) := X"B" & '1'; -- xxx
-- constant c_branch : std_logic_vector(15 downto 14) := "11";
--
-- -- Branches (bit 10..0) are address
-- constant c_br_eq : std_logic_vector(13 downto 11) := "000"; -- zero
-- constant c_br_neq : std_logic_vector(13 downto 11) := "001"; -- not zero
-- constant c_br_mi : std_logic_vector(13 downto 11) := "010"; -- negative
-- constant c_br_pl : std_logic_vector(13 downto 11) := "011"; -- not negative
-- constant c_br_always: std_logic_vector(13 downto 11) := "100"; -- always (jump)
-- constant c_br_call : std_logic_vector(13 downto 11) := "101"; -- always (call)
--
constant c_program : t_instructions := (
X"0840", -- 00 -- load $40
X"804E", -- 01 -- store $44
X"4841", -- 02 -- add $41
X"8045", -- 03 -- store $45
X"0840", -- 04 -- load $40
X"1841", -- 05 -- or $41
X"8046", -- 06 -- store $46
X"0840", -- 07 -- load $40
X"2841", -- 08 -- and $41
X"8047", -- 09 -- store $47
X"8842", -- 0a -- load ($42)
X"9043", -- 0b -- store ($43)
X"0840", -- 0c -- load $40
X"5041", -- 0d -- comp $41
X"C000", -- 0e -- equal? => 0
X"D800", -- 0f -- not negative? => 0
X"A055", -- 10 -- out to $55
X"6857", -- 11 -- in from $57
X"E818", -- 12 -- call $18
X"8048", -- 13 -- store $48
X"E01A", -- 14 -- jump $1a
X"0000", -- 15
X"0000", -- 16
X"0000", -- 17
X"0844", -- 18 -- load $44
X"B800", -- 19 -- return
X"6801", -- 1A -- in 1
X"804F", -- 1B -- store in $4f
X"A002", -- 1C -- out to $2
X"5842", -- 1D -- sub 1
X"C81C", -- 1E -- bne $1d
X"E01F" -- 1F -- jump self
);
constant c_data : t_instructions(64 to 68) := (
X"237A",
X"59B2",
X"0001",
X"0049",
X"FFFF" );
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano_cpu
port map (
clock => clock,
reset => reset,
-- instruction/data ram
ram_addr => ram_addr,
ram_en => ram_en,
ram_we => ram_we,
ram_wdata => ram_wdata,
ram_rdata => ram_rdata,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
p_ram: process
variable ram : t_instructions(0 to 1023) := (others => (others => '1'));
begin
ram(c_program'range) := c_program;
ram(c_data'range) := c_data;
while true loop
wait until clock='1';
if ram_en='1' then
ram_rdata <= ram(to_integer(unsigned(ram_addr)));
if ram_we='1' then
ram(to_integer(unsigned(ram_addr))) := ram_wdata;
end if;
end if;
end loop;
end process;
io_rdata <= X"0006";
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu_tb is
end entity;
architecture tb of nano_cpu_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ram_addr : std_logic_vector(9 downto 0);
signal ram_en : std_logic;
signal ram_we : std_logic;
signal ram_wdata : std_logic_vector(15 downto 0);
signal ram_rdata : std_logic_vector(15 downto 0);
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
type t_instructions is array(natural range <>) of std_logic_vector(15 downto 0);
-- constant c_load : std_logic_vector(15 downto 11) := X"0" & '1'; -- load
-- constant c_or : std_logic_vector(15 downto 11) := X"1" & '1'; -- or
-- constant c_and : std_logic_vector(15 downto 11) := X"2" & '1'; -- and
-- constant c_xor : std_logic_vector(15 downto 11) := X"3" & '1'; -- xor
-- constant c_add : std_logic_vector(15 downto 11) := X"4" & '1'; -- add
-- constant c_sub : std_logic_vector(15 downto 11) := X"5" & '1'; -- sub
-- constant c_compare : std_logic_vector(15 downto 11) := X"5" & '0'; -- sub
-- constant c_store : std_logic_vector(15 downto 11) := X"8" & '0'; -- xxx
-- constant c_load_ind : std_logic_vector(15 downto 11) := X"8" & '1'; -- load
-- constant c_store_ind: std_logic_vector(15 downto 11) := X"9" & '0'; -- xxx
-- constant c_out : std_logic_vector(15 downto 11) := X"A" & '0'; -- xxx
-- constant c_in : std_logic_vector(15 downto 11) := X"A" & '1'; -- load
--
-- -- Specials
-- constant c_return : std_logic_vector(15 downto 11) := X"B" & '1'; -- xxx
-- constant c_branch : std_logic_vector(15 downto 14) := "11";
--
-- -- Branches (bit 10..0) are address
-- constant c_br_eq : std_logic_vector(13 downto 11) := "000"; -- zero
-- constant c_br_neq : std_logic_vector(13 downto 11) := "001"; -- not zero
-- constant c_br_mi : std_logic_vector(13 downto 11) := "010"; -- negative
-- constant c_br_pl : std_logic_vector(13 downto 11) := "011"; -- not negative
-- constant c_br_always: std_logic_vector(13 downto 11) := "100"; -- always (jump)
-- constant c_br_call : std_logic_vector(13 downto 11) := "101"; -- always (call)
--
constant c_program : t_instructions := (
X"0840", -- 00 -- load $40
X"804E", -- 01 -- store $44
X"4841", -- 02 -- add $41
X"8045", -- 03 -- store $45
X"0840", -- 04 -- load $40
X"1841", -- 05 -- or $41
X"8046", -- 06 -- store $46
X"0840", -- 07 -- load $40
X"2841", -- 08 -- and $41
X"8047", -- 09 -- store $47
X"8842", -- 0a -- load ($42)
X"9043", -- 0b -- store ($43)
X"0840", -- 0c -- load $40
X"5041", -- 0d -- comp $41
X"C000", -- 0e -- equal? => 0
X"D800", -- 0f -- not negative? => 0
X"A055", -- 10 -- out to $55
X"6857", -- 11 -- in from $57
X"E818", -- 12 -- call $18
X"8048", -- 13 -- store $48
X"E01A", -- 14 -- jump $1a
X"0000", -- 15
X"0000", -- 16
X"0000", -- 17
X"0844", -- 18 -- load $44
X"B800", -- 19 -- return
X"6801", -- 1A -- in 1
X"804F", -- 1B -- store in $4f
X"A002", -- 1C -- out to $2
X"5842", -- 1D -- sub 1
X"C81C", -- 1E -- bne $1d
X"E01F" -- 1F -- jump self
);
constant c_data : t_instructions(64 to 68) := (
X"237A",
X"59B2",
X"0001",
X"0049",
X"FFFF" );
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano_cpu
port map (
clock => clock,
reset => reset,
-- instruction/data ram
ram_addr => ram_addr,
ram_en => ram_en,
ram_we => ram_we,
ram_wdata => ram_wdata,
ram_rdata => ram_rdata,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
p_ram: process
variable ram : t_instructions(0 to 1023) := (others => (others => '1'));
begin
ram(c_program'range) := c_program;
ram(c_data'range) := c_data;
while true loop
wait until clock='1';
if ram_en='1' then
ram_rdata <= ram(to_integer(unsigned(ram_addr)));
if ram_we='1' then
ram(to_integer(unsigned(ram_addr))) := ram_wdata;
end if;
end if;
end loop;
end process;
io_rdata <= X"0006";
end tb;
|
package range1 is
subtype preal is real range 1.0 to real'high;
function as_positive (x : integer) return positive;
function as_positive (x : real) return preal;
end package;
package body range1 is
function as_positive (x : integer) return positive is
variable p : positive;
begin
p := x;
return p;
end function;
function as_positive (x : real) return preal is
variable p : preal;
begin
p := x;
return p;
end function;
end package body;
|
--
-- OutputGenerator.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity OutputGenerator is
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in std_logic_vector( 4 downto 0 );
stage : in std_logic_vector( 1 downto 0 );
rhythm : in std_logic;
opout : in std_logic_vector( 13 downto 0 );
faddr : in integer range 0 to 9-1;
fdata : out SIGNED_LI_TYPE;
maddr : in std_logic_vector( 4 downto 0 );
mdata : out SIGNED_LI_TYPE
);
end entity;
architecture RTL of OutputGenerator is
function AVERAGE ( L : SIGNED_LI_TYPE ; R : SIGNED_LI_TYPE ) return SIGNED_LI_TYPE is
variable vL, vR : std_logic_vector(LI_TYPE'high + 2 downto 0);
begin
-- {âÎl ¨ QÌâ
if( L.sign = '0' )then
vL := "00" & L.value;
else
vL := not ( "00" & L.value ) + '1';
end if;
if( R.sign = '0' )then
vR := "00" & R.value;
else
vR := not ( "00" & R.value ) + '1';
end if;
vL := vL + vR;
-- QÌâ ¨ {âÎlA¢ÅÉ 1/2 {B±±ÅPrbgÁ¸B
if vL(vL'high) = '0' then -- positive
return ( sign => '0', value => vL(vL'high-1 downto 1) );
else -- negative
vL := not ( vL - '1' );
return ( sign => '1', value => vL(vL'high-1 downto 1) );
end if;
end;
signal fb_wr, mo_wr : std_logic;
signal fb_addr : integer range 0 to 9-1;
signal mo_addr : std_logic_vector( 4 downto 0 );
signal li_data, fb_wdata, mo_wdata, mo_rdata : SIGNED_LI_TYPE;
begin
Fmem : entity work.FeedbackMemory
port map(
clk => clk,
reset => reset,
wr => fb_wr,
waddr => fb_addr,
wdata => fb_wdata,
raddr => faddr,
rdata => fdata
);
Mmem : entity work.OutputMemory
port map(
clk => clk,
reset => reset,
wr => mo_wr,
addr => mo_addr,
wdata => mo_wdata,
rdata => mo_rdata,
addr2 => maddr,
rdata2 => mdata
);
Ltbl : entity work.LinearTable
port map (
clk => clk,
reset => reset,
addr => opout, -- 0`127 (opout Í FF Ìo;©ç_CNgÉüêÄàâèÈ¢j
data => li_data -- 0`511
);
process( reset, clk )
begin
if( reset = '1' )then
mo_wr <= '0';
fb_wr <= '0';
elsif( clk'event and clk = '1' )then
if( clkena = '1' )then
mo_addr <= slot;
if( stage = 0 )then
mo_wr <= '0';
fb_wr <= '0';
elsif( stage = 1 )then
-- opout É]ÌlªüÁÄéXe[W
elsif( stage = 2 )then
-- Ò¿
elsif( stage = 3 )then
-- LinerTable ©ç opout Åwè³ê½AhXÉηélªoÄéXe[W
if( slot(0) = '0' )then
-- tB[hobNÉÍW
[^ÌÆ«µ©«ÜÈ¢
fb_addr <= conv_integer(slot)/2;
fb_wdata<= AVERAGE(mo_rdata, li_data);
fb_wr <= '1';
end if;
-- Store raw output
mo_wdata<= li_data;
mo_wr <= '1';
end if;
end if;
end if;
end process;
end architecture;
|
entity test is
subtype t is ((bar baz, qux zzz)) foo;
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:03:52 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0_1/system_ov7670_controller_0_0_stub.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_controller_0_0 is
Port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end system_ov7670_controller_0_0;
architecture stub of system_ov7670_controller_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,resend,config_finished,sioc,siod,reset,pwdn,xclk";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_controller,Vivado 2016.4";
begin
end;
|
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 24/06/2015 - 20:23
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ULA_CTRL IS
PORT (
ALUOp : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
IN_A : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END ULA_CTRL;
ARCHITECTURE ARC_ULA_CTRL of ULA_CTRL IS
BEGIN
--Conforme Apndix D do livro texto
OUT_A(2) <= ALUOp(0) OR (ALUOp(1) AND IN_A(1));
OUT_A(1) <= (NOT ALUOp(1)) OR (NOT IN_A(2));
OUT_A(0) <= (ALUOp(1) AND IN_A(0)) OR (ALUOp(1) AND IN_A(3));
END ARC_ULA_CTRL;
|
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 24/06/2015 - 20:23
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ULA_CTRL IS
PORT (
ALUOp : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
IN_A : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END ULA_CTRL;
ARCHITECTURE ARC_ULA_CTRL of ULA_CTRL IS
BEGIN
--Conforme Apndix D do livro texto
OUT_A(2) <= ALUOp(0) OR (ALUOp(1) AND IN_A(1));
OUT_A(1) <= (NOT ALUOp(1)) OR (NOT IN_A(2));
OUT_A(0) <= (ALUOp(1) AND IN_A(0)) OR (ALUOp(1) AND IN_A(3));
END ARC_ULA_CTRL;
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean;
function is_illegal(inst: std_logic_vector(7 downto 0)) return boolean;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector;
constant c_stack_idx_brk : std_logic_vector(1 downto 0) := "00";
constant c_stack_idx_jsr : std_logic_vector(1 downto 0) := "01";
constant c_stack_idx_rti : std_logic_vector(1 downto 0) := "10";
constant c_stack_idx_rts : std_logic_vector(1 downto 0) := "11";
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean;
end;
package body pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X11X | 1101
if inst(3 downto 2)="11" then
return true;
elsif inst(4 downto 2)="110" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(7 downto 6)="01" and inst(3 downto 0)=X"C";
end function;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210 = 1XX000X0
if inst(7)='1' and inst(4 downto 2)="000" and inst(0)='0' then
return true;
-- 76543210 = XXX010X1
elsif inst(4 downto 2)="010" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X100
return inst(3 downto 2)="10" and inst(0)='0';
end function;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210
-- 0xx0x000
return inst(7)='0' and inst(4)='0' and inst(2 downto 0)="000";
end function;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- we already know it's a stack operation, so only the direction is important
return inst(5)='0';
end function;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(3 downto 2)="01" then
return true;
elsif inst(3 downto 2)="00" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(3 downto 2)="00" and inst(0)='1');
end function;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(4 downto 0)="10000");
end function;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(7 downto 5)="100");
end function;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7)='1' and inst(4 downto 2)="010" then
return false;
end if;
return (inst(1)='1');
end function;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7)='0' and inst(4 downto 1)="0101" then
return false;
end if;
return (inst(0)='1');
end function;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return not is_store(inst) and not is_rmw(inst);
end function;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(1)='1' and inst(7 downto 6)/="10";
end function;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return is_jump(inst) and inst(5)='0';
end function;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(4)='1';
end function;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
return inst(6 downto 5);
end function;
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(4)='1' and inst(2)='0' and inst(0)='1' then -- XXX1X0X1
return true;
elsif inst(7 downto 6)="10" and inst(2 downto 1)="11" then -- 10XXX11X
return true;
end if;
return false;
end function;
-- function flags_bit_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(2 downto 0)="100";
-- end function;
--
-- function flags_alu_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(1 downto 0)="01"; -- could also choose not to look at bit 1 (overlap)
-- end function;
--
-- function flags_shift_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(1 downto 0)="10"; -- could also choose not to look at bit 0 (overlap)
-- end function;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst = X"68");
end function;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 0XXXXXX1 or alu operations "lo"
-- 1X100001 or alu operations "hi" (except store and cmp)
-- 0XX01010 (implied)
return (inst(7)='0' and inst(4 downto 0)="01010") or
(inst(7)='0' and inst(0)='1') or
(inst(7)='1' and inst(0)='1' and inst(5)='1');
end function;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX1X or 1100101- (for SAX #)
if inst(7 downto 1)="1100101" then
return true;
end if;
return inst(7 downto 5)="101" and inst(1)='1' and not is_implied(inst);
end function;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX00
return inst(7 downto 5)="101" and inst(1 downto 0)="00" and not is_implied(inst);
end function;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
-- 00 = none, 01 = memory, 10 = A, 11 = A & M
if inst(4 downto 2)="010" and inst(7)='0' then
return inst(1 downto 0);
end if;
return "01";
end function;
-- function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
-- begin
-- -- 0=memory, 1=A
-- if inst(4 downto 1)="0101" and inst(7)='0' then
-- return "01";
-- end if;
-- return "10";
-- end function;
function is_illegal (inst: std_logic_vector(7 downto 0)) return boolean is
type t_my16bit_array is array(natural range <>) of std_logic_vector(15 downto 0);
constant c_illegal_map : t_my16bit_array(0 to 15) := (
X"989C", X"9C9C", X"888C", X"9C9C", X"889C", X"9C9C", X"889C", X"9C9C",
X"8A8D", X"D88C", X"8888", X"888C", X"888C", X"9C9C", X"888C", X"9C9C" );
variable row : std_logic_vector(15 downto 0);
begin
row := c_illegal_map(conv_integer(inst(7 downto 4)));
return (row(conv_integer(inst(3 downto 0))) = '1');
end function;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 1-00101- 8A,8B,CA,CB
return inst(5 downto 1)="00101" and inst(7)='1';
end function;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean;
function is_illegal(inst: std_logic_vector(7 downto 0)) return boolean;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector;
constant c_stack_idx_brk : std_logic_vector(1 downto 0) := "00";
constant c_stack_idx_jsr : std_logic_vector(1 downto 0) := "01";
constant c_stack_idx_rti : std_logic_vector(1 downto 0) := "10";
constant c_stack_idx_rts : std_logic_vector(1 downto 0) := "11";
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean;
end;
package body pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X11X | 1101
if inst(3 downto 2)="11" then
return true;
elsif inst(4 downto 2)="110" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(7 downto 6)="01" and inst(3 downto 0)=X"C";
end function;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210 = 1XX000X0
if inst(7)='1' and inst(4 downto 2)="000" and inst(0)='0' then
return true;
-- 76543210 = XXX010X1
elsif inst(4 downto 2)="010" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X100
return inst(3 downto 2)="10" and inst(0)='0';
end function;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210
-- 0xx0x000
return inst(7)='0' and inst(4)='0' and inst(2 downto 0)="000";
end function;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- we already know it's a stack operation, so only the direction is important
return inst(5)='0';
end function;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(3 downto 2)="01" then
return true;
elsif inst(3 downto 2)="00" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(3 downto 2)="00" and inst(0)='1');
end function;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(4 downto 0)="10000");
end function;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(7 downto 5)="100");
end function;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7)='1' and inst(4 downto 2)="010" then
return false;
end if;
return (inst(1)='1');
end function;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7)='0' and inst(4 downto 1)="0101" then
return false;
end if;
return (inst(0)='1');
end function;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return not is_store(inst) and not is_rmw(inst);
end function;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(1)='1' and inst(7 downto 6)/="10";
end function;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return is_jump(inst) and inst(5)='0';
end function;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(4)='1';
end function;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
return inst(6 downto 5);
end function;
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(4)='1' and inst(2)='0' and inst(0)='1' then -- XXX1X0X1
return true;
elsif inst(7 downto 6)="10" and inst(2 downto 1)="11" then -- 10XXX11X
return true;
end if;
return false;
end function;
-- function flags_bit_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(2 downto 0)="100";
-- end function;
--
-- function flags_alu_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(1 downto 0)="01"; -- could also choose not to look at bit 1 (overlap)
-- end function;
--
-- function flags_shift_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(1 downto 0)="10"; -- could also choose not to look at bit 0 (overlap)
-- end function;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst = X"68");
end function;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 0XXXXXX1 or alu operations "lo"
-- 1X100001 or alu operations "hi" (except store and cmp)
-- 0XX01010 (implied)
return (inst(7)='0' and inst(4 downto 0)="01010") or
(inst(7)='0' and inst(0)='1') or
(inst(7)='1' and inst(0)='1' and inst(5)='1');
end function;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX1X or 1100101- (for SAX #)
if inst(7 downto 1)="1100101" then
return true;
end if;
return inst(7 downto 5)="101" and inst(1)='1' and not is_implied(inst);
end function;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX00
return inst(7 downto 5)="101" and inst(1 downto 0)="00" and not is_implied(inst);
end function;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
-- 00 = none, 01 = memory, 10 = A, 11 = A & M
if inst(4 downto 2)="010" and inst(7)='0' then
return inst(1 downto 0);
end if;
return "01";
end function;
-- function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
-- begin
-- -- 0=memory, 1=A
-- if inst(4 downto 1)="0101" and inst(7)='0' then
-- return "01";
-- end if;
-- return "10";
-- end function;
function is_illegal (inst: std_logic_vector(7 downto 0)) return boolean is
type t_my16bit_array is array(natural range <>) of std_logic_vector(15 downto 0);
constant c_illegal_map : t_my16bit_array(0 to 15) := (
X"989C", X"9C9C", X"888C", X"9C9C", X"889C", X"9C9C", X"889C", X"9C9C",
X"8A8D", X"D88C", X"8888", X"888C", X"888C", X"9C9C", X"888C", X"9C9C" );
variable row : std_logic_vector(15 downto 0);
begin
row := c_illegal_map(conv_integer(inst(7 downto 4)));
return (row(conv_integer(inst(3 downto 0))) = '1');
end function;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 1-00101- 8A,8B,CA,CB
return inst(5 downto 1)="00101" and inst(7)='1';
end function;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean;
function is_illegal(inst: std_logic_vector(7 downto 0)) return boolean;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector;
constant c_stack_idx_brk : std_logic_vector(1 downto 0) := "00";
constant c_stack_idx_jsr : std_logic_vector(1 downto 0) := "01";
constant c_stack_idx_rti : std_logic_vector(1 downto 0) := "10";
constant c_stack_idx_rts : std_logic_vector(1 downto 0) := "11";
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean;
end;
package body pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X11X | 1101
if inst(3 downto 2)="11" then
return true;
elsif inst(4 downto 2)="110" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(7 downto 6)="01" and inst(3 downto 0)=X"C";
end function;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210 = 1XX000X0
if inst(7)='1' and inst(4 downto 2)="000" and inst(0)='0' then
return true;
-- 76543210 = XXX010X1
elsif inst(4 downto 2)="010" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X100
return inst(3 downto 2)="10" and inst(0)='0';
end function;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210
-- 0xx0x000
return inst(7)='0' and inst(4)='0' and inst(2 downto 0)="000";
end function;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- we already know it's a stack operation, so only the direction is important
return inst(5)='0';
end function;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(3 downto 2)="01" then
return true;
elsif inst(3 downto 2)="00" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(3 downto 2)="00" and inst(0)='1');
end function;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(4 downto 0)="10000");
end function;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(7 downto 5)="100");
end function;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7)='1' and inst(4 downto 2)="010" then
return false;
end if;
return (inst(1)='1');
end function;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7)='0' and inst(4 downto 1)="0101" then
return false;
end if;
return (inst(0)='1');
end function;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return not is_store(inst) and not is_rmw(inst);
end function;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(1)='1' and inst(7 downto 6)/="10";
end function;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return is_jump(inst) and inst(5)='0';
end function;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(4)='1';
end function;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
return inst(6 downto 5);
end function;
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(4)='1' and inst(2)='0' and inst(0)='1' then -- XXX1X0X1
return true;
elsif inst(7 downto 6)="10" and inst(2 downto 1)="11" then -- 10XXX11X
return true;
end if;
return false;
end function;
-- function flags_bit_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(2 downto 0)="100";
-- end function;
--
-- function flags_alu_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(1 downto 0)="01"; -- could also choose not to look at bit 1 (overlap)
-- end function;
--
-- function flags_shift_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(1 downto 0)="10"; -- could also choose not to look at bit 0 (overlap)
-- end function;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst = X"68");
end function;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 0XXXXXX1 or alu operations "lo"
-- 1X100001 or alu operations "hi" (except store and cmp)
-- 0XX01010 (implied)
return (inst(7)='0' and inst(4 downto 0)="01010") or
(inst(7)='0' and inst(0)='1') or
(inst(7)='1' and inst(0)='1' and inst(5)='1');
end function;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX1X or 1100101- (for SAX #)
if inst(7 downto 1)="1100101" then
return true;
end if;
return inst(7 downto 5)="101" and inst(1)='1' and not is_implied(inst);
end function;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX00
return inst(7 downto 5)="101" and inst(1 downto 0)="00" and not is_implied(inst);
end function;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
-- 00 = none, 01 = memory, 10 = A, 11 = A & M
if inst(4 downto 2)="010" and inst(7)='0' then
return inst(1 downto 0);
end if;
return "01";
end function;
-- function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
-- begin
-- -- 0=memory, 1=A
-- if inst(4 downto 1)="0101" and inst(7)='0' then
-- return "01";
-- end if;
-- return "10";
-- end function;
function is_illegal (inst: std_logic_vector(7 downto 0)) return boolean is
type t_my16bit_array is array(natural range <>) of std_logic_vector(15 downto 0);
constant c_illegal_map : t_my16bit_array(0 to 15) := (
X"989C", X"9C9C", X"888C", X"9C9C", X"889C", X"9C9C", X"889C", X"9C9C",
X"8A8D", X"D88C", X"8888", X"888C", X"888C", X"9C9C", X"888C", X"9C9C" );
variable row : std_logic_vector(15 downto 0);
begin
row := c_illegal_map(conv_integer(inst(7 downto 4)));
return (row(conv_integer(inst(3 downto 0))) = '1');
end function;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 1-00101- 8A,8B,CA,CB
return inst(5 downto 1)="00101" and inst(7)='1';
end function;
end;
|
-------------------------------------------------------------------------------
--
-- Title : absdb
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\absdb.vhd
-- Generated : Tue Dec 6 14:07:10 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {absdb} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity absdb is
port(
rs1: in std_logic_vector(63 downto 0);
rs2: in std_logic_vector(63 downto 0);
rd: out std_logic_vector (63 downto 0)
);
end absdb;
--}} End of automatically maintained section
architecture behavioral of absdb is
begin
process(rs1,rs2)
variable diff: unsigned(7 downto 0);
variable larger: unsigned(7 downto 0);
variable smaller: unsigned(7 downto 0);
begin
diff:=to_unsigned(0,8) ;
for j in 0 to 7 loop
if(rs1((j*8+7) downto j*8)>rs2((j*8+7) downto j*8)) then
larger:= unsigned(rs1((j*8+7) downto j*8));
smaller:=unsigned(rs2((j*8+7) downto j*8));
else
larger:= unsigned(rs2((j*8+7) downto j*8));
smaller:=unsigned(rs1((j*8+7) downto j*8));
end if;
diff:= larger-smaller;
rd(j*8+7 downto j*8)<=std_logic_vector(diff);
end loop;
end process;
end behavioral;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity div_pipe_inferred is
generic (
stages : positive := 3;
src1_bits : natural := 32;
src2_bits : natural := 32
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
unsgnd : in std_ulogic;
src1 : in std_ulogic_vector(src1_bits-1 downto 0);
src2 : in std_ulogic_vector(src2_bits-1 downto 0);
dbz : out std_ulogic;
result : out std_ulogic_vector(src1_bits-1 downto 0);
overflow : out std_ulogic
);
end;
|
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity PreScale is
generic (BIT_WIDTH : integer := 19);
Port(inclock: IN std_logic;
outclock: OUT std_logic);
End PreScale;
--generic map (BIT_WIDTH=>6) port map ()
Architecture structure of PreScale is
signal Q: unsigned (BIT_WIDTH-1 downto 0);
begin
outclock <= Q(BIT_WIDTH-1);
q <= Q + 1 when rising_edge(inclock);
end structure; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY SDPRAM_16A9024X32B4512 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END SDPRAM_16A9024X32B4512;
ARCHITECTURE SDPRAM_16A9024X32B4512_arch OF SDPRAM_16A9024X32B4512 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF SDPRAM_16A9024X32B4512_arch : ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=SDPRAM_16A9024X32B4512.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=9024,C_READ_DEPTH_A=9024,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=4512,C_READ_DEPTH_B=4512,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 8.994245 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "SDPRAM_16A9024X32B4512.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 9024,
C_READ_DEPTH_A => 9024,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 4512,
C_READ_DEPTH_B => 4512,
C_ADDRB_WIDTH => 13,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 8.994245 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END SDPRAM_16A9024X32B4512_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY SDPRAM_16A9024X32B4512 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END SDPRAM_16A9024X32B4512;
ARCHITECTURE SDPRAM_16A9024X32B4512_arch OF SDPRAM_16A9024X32B4512 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF SDPRAM_16A9024X32B4512_arch : ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF SDPRAM_16A9024X32B4512_arch: ARCHITECTURE IS "SDPRAM_16A9024X32B4512,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=SDPRAM_16A9024X32B4512.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=9024,C_READ_DEPTH_A=9024,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=4512,C_READ_DEPTH_B=4512,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 8.994245 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "SDPRAM_16A9024X32B4512.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 9024,
C_READ_DEPTH_A => 9024,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 4512,
C_READ_DEPTH_B => 4512,
C_ADDRB_WIDTH => 13,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 8.994245 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END SDPRAM_16A9024X32B4512_arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
package clock_power_pkg is
constant Tpw : delay_length := 4 ns;
signal clock_phase1, clock_phase2 : std_ulogic;
terminal analog_plus_supply, analog_ground : electrical;
end package clock_power_pkg;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
package clock_power_pkg is
constant Tpw : delay_length := 4 ns;
signal clock_phase1, clock_phase2 : std_ulogic;
terminal analog_plus_supply, analog_ground : electrical;
end package clock_power_pkg;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
package clock_power_pkg is
constant Tpw : delay_length := 4 ns;
signal clock_phase1, clock_phase2 : std_ulogic;
terminal analog_plus_supply, analog_ground : electrical;
end package clock_power_pkg;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(7 - 1 downto 0);
b: in std_logic_vector(31 - 1 downto 0);
p: out std_logic_vector(38 - 1 downto 0));
end entity;
architecture behav of feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
signal tmp_product : std_logic_vector(38 - 1 downto 0);
signal a_i : std_logic_vector(7 - 1 downto 0);
signal b_i : std_logic_vector(31 - 1 downto 0);
signal p_tmp : std_logic_vector(38 - 1 downto 0);
signal a_reg0 : std_logic_vector(7 - 1 downto 0);
signal b_reg0 : std_logic_vector(31 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(38 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 38));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_mul_7ns_31ns_38_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_mul_7ns_31ns_38_3 is
component feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_mul_7ns_31ns_38_3_Mul3S_0_U : component feedforward_mul_7ns_31ns_38_3_Mul3S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(7 - 1 downto 0);
b: in std_logic_vector(31 - 1 downto 0);
p: out std_logic_vector(38 - 1 downto 0));
end entity;
architecture behav of feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
signal tmp_product : std_logic_vector(38 - 1 downto 0);
signal a_i : std_logic_vector(7 - 1 downto 0);
signal b_i : std_logic_vector(31 - 1 downto 0);
signal p_tmp : std_logic_vector(38 - 1 downto 0);
signal a_reg0 : std_logic_vector(7 - 1 downto 0);
signal b_reg0 : std_logic_vector(31 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(38 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 38));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_mul_7ns_31ns_38_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_mul_7ns_31ns_38_3 is
component feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_mul_7ns_31ns_38_3_Mul3S_0_U : component feedforward_mul_7ns_31ns_38_3_Mul3S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(7 - 1 downto 0);
b: in std_logic_vector(31 - 1 downto 0);
p: out std_logic_vector(38 - 1 downto 0));
end entity;
architecture behav of feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
signal tmp_product : std_logic_vector(38 - 1 downto 0);
signal a_i : std_logic_vector(7 - 1 downto 0);
signal b_i : std_logic_vector(31 - 1 downto 0);
signal p_tmp : std_logic_vector(38 - 1 downto 0);
signal a_reg0 : std_logic_vector(7 - 1 downto 0);
signal b_reg0 : std_logic_vector(31 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(38 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 38));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_mul_7ns_31ns_38_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_mul_7ns_31ns_38_3 is
component feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_mul_7ns_31ns_38_3_Mul3S_0_U : component feedforward_mul_7ns_31ns_38_3_Mul3S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1653.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c09s00b00x00p02n01i01653ent_a is
port (signal ss : in integer);
end c09s00b00x00p02n01i01653ent_a;
architecture c09s00b00x00p02n01i01653arch_a of c09s00b00x00p02n01i01653ent_a is
begin
process
begin
wait;
end process;
end c09s00b00x00p02n01i01653arch_a;
ENTITY c09s00b00x00p02n01i01653ent IS
port ( Pt : in BOOLEAN;
PTO : out BIT) ;
END c09s00b00x00p02n01i01653ent;
ARCHITECTURE c09s00b00x00p02n01i01653arch OF c09s00b00x00p02n01i01653ent IS
component FO
port (signal ss : in INTEGER);
end component ;
for Ls : FO use entity work.c09s00b00x00p02n01i01653ent_a(c09s00b00x00p02n01i01653arch_a);
signal S1, S2 : Integer;
signal S : INTEGER;
BEGIN
-- concurrent signal statement
S <= transport 5;
-- concurrent assertion statement
assert ( not PT)
report " dead wire "
severity WARNING;
-- generate
L_G_1: for I in 1 to 1 generate
L_X_2: block
signal S3 : Bit;
begin
S2 <= transport 1;
end block;
end generate;
-- component instatiation
Ls : FO port map (S1);
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s00b00x00p02n01i01653"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s00b00x00p02n01i01653arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1653.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c09s00b00x00p02n01i01653ent_a is
port (signal ss : in integer);
end c09s00b00x00p02n01i01653ent_a;
architecture c09s00b00x00p02n01i01653arch_a of c09s00b00x00p02n01i01653ent_a is
begin
process
begin
wait;
end process;
end c09s00b00x00p02n01i01653arch_a;
ENTITY c09s00b00x00p02n01i01653ent IS
port ( Pt : in BOOLEAN;
PTO : out BIT) ;
END c09s00b00x00p02n01i01653ent;
ARCHITECTURE c09s00b00x00p02n01i01653arch OF c09s00b00x00p02n01i01653ent IS
component FO
port (signal ss : in INTEGER);
end component ;
for Ls : FO use entity work.c09s00b00x00p02n01i01653ent_a(c09s00b00x00p02n01i01653arch_a);
signal S1, S2 : Integer;
signal S : INTEGER;
BEGIN
-- concurrent signal statement
S <= transport 5;
-- concurrent assertion statement
assert ( not PT)
report " dead wire "
severity WARNING;
-- generate
L_G_1: for I in 1 to 1 generate
L_X_2: block
signal S3 : Bit;
begin
S2 <= transport 1;
end block;
end generate;
-- component instatiation
Ls : FO port map (S1);
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s00b00x00p02n01i01653"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s00b00x00p02n01i01653arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1653.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c09s00b00x00p02n01i01653ent_a is
port (signal ss : in integer);
end c09s00b00x00p02n01i01653ent_a;
architecture c09s00b00x00p02n01i01653arch_a of c09s00b00x00p02n01i01653ent_a is
begin
process
begin
wait;
end process;
end c09s00b00x00p02n01i01653arch_a;
ENTITY c09s00b00x00p02n01i01653ent IS
port ( Pt : in BOOLEAN;
PTO : out BIT) ;
END c09s00b00x00p02n01i01653ent;
ARCHITECTURE c09s00b00x00p02n01i01653arch OF c09s00b00x00p02n01i01653ent IS
component FO
port (signal ss : in INTEGER);
end component ;
for Ls : FO use entity work.c09s00b00x00p02n01i01653ent_a(c09s00b00x00p02n01i01653arch_a);
signal S1, S2 : Integer;
signal S : INTEGER;
BEGIN
-- concurrent signal statement
S <= transport 5;
-- concurrent assertion statement
assert ( not PT)
report " dead wire "
severity WARNING;
-- generate
L_G_1: for I in 1 to 1 generate
L_X_2: block
signal S3 : Bit;
begin
S2 <= transport 1;
end block;
end generate;
-- component instatiation
Ls : FO port map (S1);
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s00b00x00p02n01i01653"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s00b00x00p02n01i01653arch;
|
--*****************************************************************************
--*****************************************************************************
-- Model: testbench for a uniaxial MEMS accelerometer accelZa_02.vhd in hAMSter
--
--
-- Author: <[email protected]>
-- Date: 30.09.2021
-- Library dependencies:
-- accelZa_02.vhd - VHDL-AMS generated code from ANSYS for hAMSter
--
-- https://github.com/Kolchuzhin/LMGT_MEMS_component_library/tree/master/uniaxial_accelerometer
-------------------------------------------------------------------------------
-- parameters, uMKSV units
--
-- loading cases
-- 0. static mechanical test: az_input
-- 10. static mechanical test, constant modal forces
-- 11. mechanical test: ramp/sweep
-- 12. mechanical test: sin/chirp
-- 13. mechanical test: puls
-- 20. static electrical test: dc
-- 21. electrical test: ramp/sweep, pull-in
-- 22. electrical test: chirp
-- 23. electrical test: puls
--
--
--
-- Damping: modal quality factors qm_i in accelZa_02.vhd
--
-------------------------------------------------------------------------------
-- Euler solver: time=5m; step=200n *** 2021-07-27
-------------------------------------------------------------------------------
-- ID: testbench_02.vhd
-- ver. 0.22 02.08.2021 8 master nodes, az_input
-- ver. 0.30 29.09.2021 GitHuB realize
-- ver. 0.31 30.09.2021 more loading cases
--*****************************************************************************
--*****************************************************************************
use work.electromagnetic_system.all;
use work.all;
library ieee;
use ieee.math_real.all;
entity testbench is
end;
architecture behav of testbench is
terminal struc1_ext,struc2_ext: translational; -- modal dof
terminal lagrange1_ext,lagrange2_ext,lagrange3_ext,lagrange4_ext,lagrange5_ext,lagrange6_ext,lagrange7_ext,lagrange8_ext:translational; --
terminal master1_ext,master2_ext,master3_ext,master4_ext,master5_ext,master6_ext,master7_ext,master8_ext:translational; --
terminal elec1_ext,elec2_ext,elec3_ext: electrical; --
-- Modal displacement
quantity q_ext1 across fm_ext1 through struc1_ext; -- modal amplitude 1 (mode 1)
quantity q_ext2 across fm_ext2 through struc2_ext; -- modal amplitude 2 (mode 5)
-- Lagrangian multipler
quantity p_ext1 across r_ext1 through lagrange1_ext;
quantity p_ext2 across r_ext2 through lagrange2_ext;
quantity p_ext3 across r_ext3 through lagrange3_ext;
quantity p_ext4 across r_ext4 through lagrange4_ext;
quantity p_ext5 across r_ext5 through lagrange5_ext;
quantity p_ext6 across r_ext6 through lagrange6_ext;
quantity p_ext7 across r_ext7 through lagrange7_ext;
quantity p_ext8 across r_ext8 through lagrange8_ext;
-- Nodal displacement
quantity u_ext1 across f_ext1 through master1_ext; -- nodal amplitude 1
quantity u_ext2 across f_ext2 through master2_ext; -- nodal amplitude 2
quantity u_ext3 across f_ext3 through master3_ext; -- nodal amplitude 3
quantity u_ext4 across f_ext4 through master4_ext; -- nodal amplitude 4
quantity u_ext5 across f_ext5 through master5_ext; -- nodal amplitude 5
quantity u_ext6 across f_ext6 through master6_ext; -- nodal amplitude 6
quantity u_ext7 across f_ext7 through master7_ext; -- nodal amplitude 7
quantity u_ext8 across f_ext8 through master8_ext; -- nodal amplitude 8
-- Electrical ports
quantity v_ext1 across i_ext1 through elec1_ext; -- conductor 1
quantity v_ext2 across i_ext2 through elec2_ext; -- conductor 2
quantity v_ext3 across i_ext3 through elec3_ext; -- conductor 3
quantity az_input: real;
constant digital_delay:time:=200.0 ns; -- digital time step size for matrix update == analog time step
-- constant az_input:real:=1.0*10.0;
constant t_end:real:=5.0E-03;
constant dt:real:=2.0E-07; -- time step
constant ac_value:real:= 1.0;
constant dc_value:real:= 1.1; -- V23_pullin=1.085V (ANSYS) / gap=1.8
-- puls
constant t1:real:= 0.3E-03;
constant t2:real:= 1.0E-03; -- 5.0E-06
-- chirp
constant fm_1:real:= 1205.3; -- mode1 frequency
constant fm_2:real:= 15539.0; -- mode5 frequency
constant f_begin:real:= 1205.3*0.1; -- begin of frequency sweep
constant f_end:real:= 1205.3*7.0; -- end of frequency sweep
constant fm1_test:real:= 0.2716; -- f=k*u => u=f/k
constant fm2_test:real:= 76.516;
-- loading cases
-- constant key_load:integer:= 0; -- static mechanical test: az_input
-- constant key_load:integer:=10; -- static mechanical test: constant modal forces
-- constant key_load:integer:=11; -- mechanical test: ramp/sweep
-- constant key_load:integer:=12; -- mechanical test: sin/chirp
-- constant key_load:integer:=13; -- mechanical test: puls
-- constant key_load:integer:=20; -- static electrical test: dc
constant key_load:integer:=21; -- electrical test: ramp/sweep, pull-in
-- constant key_load:integer:=22; -- electrical test: chirp
-- constant key_load:integer:=23; -- electrical test: puls
begin
-- Loads
if key_load = 0 use -- static mechanical test: az_input
az_input == 2.0;
--az_input == 10.0/t_end*now;
v_ext1==0.0;
v_ext2==0.0;
fm_ext1==0.0; -- external modal force 1
fm_ext2==0.0; -- external modal force 2
-- ANSYS: az=2.0*g => Uzmax=0.117083um (mn4) Uzmin=-0.162066um (mn2)
--
-- mn3 o---------------o mn4
-- | |
-- | |
-- | |
-- | movable |
-- | electrode |
-- | |
-- | |
-- | cond3 |
-- mn1 o---------------o mn2
--(mn5) (mn6)
end use;
if key_load = 10 use -- static mechanical test: modal forces
az_input == 0.0;
v_ext1==0.0;
v_ext2==0.0;
fm_ext1==fm1_test; -- external modal force 1: fm_1=km_1 => q_1=1
fm_ext2==fm2_test; -- external modal force 2: fm_2=km_2 => q_2=1
end use;
if key_load = 11 use -- ramp/sweep
az_input == 0.0;
v_ext1==0.0;
v_ext2==0.0;
fm_ext1==fm1_test/t_end/1.0*now;
fm_ext2==fm2_test/t_end/1.0*now;
end use;
if key_load = 12 use -- sin/chirp
az_input == 0.0;
v_ext1==0.0;
v_ext2==0.0;
fm_ext1==0.0 + fm1_test*sin(2.0*3.14*(f_begin + (f_end-f_begin)/t_end*now) * now);
fm_ext2==0.0;
end use;
if key_load = 13 use -- puls
az_input == 0.0;
v_ext1==0.0;
v_ext2==0.0;
fm_ext2==0.0;
if now <= t1-dt use
fm_ext1 == 0.0;
end use;
if now > t1-dt and now <= t1 use
fm_ext1 == 0.0;
end use;
if now > t1 and now <= t2 use
fm_ext1 == fm1_test*0.2;
end use;
if now > t2 and now <= t2+dt use
fm_ext1 == 0.0;
end use;
if now > t2+dt use
fm_ext1 == 0.0;
end use;
end use;
if key_load = 20 use -- static electrical
az_input == 0.0;
v_ext1== 0.5;
v_ext2== 0.0; -- ground electrode
fm_ext1==0.0;
fm_ext2==0.0;
end use;
if key_load = 21 use -- ramp/sweep
az_input == 0.0;
v_ext2 == dc_value/t_end*now;
i_ext1== 0.0;
fm_ext1==0.0;
fm_ext2==0.0;
end use;
if key_load = 22 use -- chirp
az_input == 0.0;
v_ext1 == dc_value*0.1 + ac_value*sin(2.0*3.14*(f_begin + (f_end-f_begin)/t_end*now) * now);
v_ext2== 0.0;
fm_ext1==0.0;
fm_ext2==0.0;
end use;
if key_load = 23 use -- puls
az_input == 0.0;
if now <= t1-dt use
v_ext1 == 0.0;
end use;
if now > t1-dt and now <= t1 use
v_ext1 == 0.0;
end use;
if now > t1 and now <= t2 use
v_ext1 == dc_value*0.1;
end use;
if now > t2 and now <= t2+dt use
v_ext1 == 0.0;
end use;
if now > t2+dt use
v_ext1 == 0.0;
end use;
v_ext2== 0.0;
fm_ext1==0.0;
fm_ext2==0.0;
end use;
-- BCs:
--i_ext3==0.0; -- floating movable plate
v_ext3==0.0; -- grounded movable plate
--fm_ext1==0.0; -- external modal force 1
--fm_ext2==0.0; -- external modal force 2
-- Lagrangian ports: p/r
r_ext1==0.0; -- must be zero
r_ext2==0.0; -- must be zero
r_ext3==0.0; -- must be zero
r_ext4==0.0; -- must be zero
r_ext5==0.0; -- must be zero
r_ext6==0.0; -- must be zero
r_ext7==0.0; -- must be zero
r_ext8==0.0; -- must be zero
-- nodal ports: u/f
f_ext1==0.0; -- external nodal force on master node 1
f_ext2==0.0; -- external nodal force on master node 2
f_ext3==0.0; -- external nodal force on master node 3
f_ext4==0.0; -- external nodal force on master node 4
f_ext5==0.0; -- external nodal force on master node 5
f_ext6==0.0; -- external nodal force on master node 6
f_ext7==0.0; -- external nodal force on master node 7
f_ext8==0.0; -- external nodal force on master node 8
-------------------------------------------------------------------------------
--
-- Modal ports
--
-- q1 q2
-- o o
-- | |
-- Lagrangian ports o------o---------o------o Nodal ports: 5 master nodes
-- | |
-- r_ext1=0 ->>- p1 o---o o---o u1 -<<- f_ext1=0
-- | element: accelZa_02 |
-- p2 o---o o---o u2 -<<- f_ext2=0
-- | |
-- p3 o---o o---o u3 -<<- f_ext3=0
-- | |
-- p4 o---o o---o u4 -<<- f_ext4=0
-- | |
-- p5 o---o o---o u5 -<<- f_ext5=0
-- | |
-- p6 o---o o---o u6 -<<- f_ext6=0
-- | |
-- p7 o---o o---o u7 -<<- f_ext7=0
-- | |
-- p8 o---o o---o u8 -<<- f_ext8=0
-- | |
-- o------o----o----o------o
-- | | | \
-- o | o \
-- v1_ext | v2_ext=0 o az_input
-- |
-- o v3_ext=0 (plate)
--
-- Electrical ports
--
-- ASCII-Schematic of the ROM component for uniaxial MEMS accelerometer: accelZa_02
-------------------------------------------------------------------------------
ROM_element:
entity accelZa_02(ROM)
generic map (digital_delay)
port map (az_input,
struc1_ext,struc2_ext,
lagrange1_ext,lagrange2_ext,lagrange3_ext,lagrange4_ext,lagrange5_ext,lagrange6_ext,lagrange7_ext,lagrange8_ext,
master1_ext,master2_ext,master3_ext,master4_ext,master5_ext,master6_ext,master7_ext,master8_ext,
elec1_ext,elec2_ext,elec3_ext);
end;
-------------------------------------------------------------------------------
|
--!
--! Copyright 2020 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! @brief Group of "River" CPUs with L2-cache.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
--! River top level with AMBA interface module declaration
use riverlib.types_river.all;
entity river_workgroup is
generic (
cpunum : integer;
memtech : integer;
async_reset : boolean;
fpu_ena : boolean;
coherence_ena : boolean;
tracer_ena : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_msti : in axi4_master_in_type;
o_msto : out axi4_master_out_type;
o_mstcfg : out axi4_master_config_type;
i_dport : in dport_in_vector;
o_dport : out dport_out_vector;
i_ext_irq : in std_logic_vector(CFG_TOTAL_CPU_MAX-1 downto 0)
);
end;
architecture arch_river_workgroup of river_workgroup is
constant xconfig : axi4_master_config_type := (
descrsize => PNP_CFG_MASTER_DESCR_BYTES,
descrtype => PNP_CFG_TYPE_MASTER,
vid => VENDOR_GNSSSENSOR,
did => RISCV_RIVER_WORKGROUP
);
signal corei : axi4_l1_in_vector;
signal coreo : axi4_l1_out_vector;
signal l2i : axi4_l2_in_type;
signal l2o : axi4_l2_out_type;
begin
o_mstcfg <= xconfig;
--! @brief RISC-V Processor core River.
cpuslotx : for n in 0 to CFG_TOTAL_CPU_MAX-1 generate
cpux : if n < cpunum generate
river0 : river_amba generic map (
memtech => memtech,
hartid => n,
async_reset => async_reset,
fpu_ena => fpu_ena,
coherence_ena => coherence_ena,
tracer_ena => tracer_ena
) port map (
i_nrst => i_nrst,
i_clk => i_clk,
i_msti => corei(n),
o_msto => coreo(n),
i_dport => i_dport(n),
o_dport => o_dport(n),
i_ext_irq => i_ext_irq(n)
);
end generate;
emptyx : if n >= cpunum generate
cpudummy0 : river_dummycpu port map (
o_msto => coreo(n),
o_dport => o_dport(n),
o_flush_l2 => open
);
end generate;
end generate;
l2_ena : if coherence_ena generate
-- TODO: see Wasserfall implementation
end generate;
l2_dis : if not coherence_ena generate
l2dummy0 : RiverL2Dummy generic map (
async_reset => async_reset
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_l1o => coreo,
o_l1i => corei,
i_l2i => l2i,
o_l2o => l2o,
i_flush_valid => '0'
);
end generate;
l2serdes0 : river_l2serdes generic map (
async_reset => async_reset
) port map (
i_nrst => i_nrst,
i_clk => i_clk,
i_l2o => l2o,
o_l2i => l2i,
i_msti => i_msti,
o_msto => o_msto
);
end;
|
library verilog;
use verilog.vl_types.all;
entity control_vlg_check_tst is
port(
lose : in vl_logic;
roll : in vl_logic;
sp : in vl_logic;
win : in vl_logic;
sampler_rx : in vl_logic
);
end control_vlg_check_tst;
|
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant2.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant2 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_constant2;
ARCHITECTURE SYN OF lpm_constant2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(0 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I2",
lpm_type => "LPM_CONSTANT",
lpm_width => 1
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "I2"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I2"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]"
-- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @details PLL instance for the behaviour simulation
--!
--! "Output Output Phase Duty Pk-to-Pk Phase"
--! "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
--!
--! CLK_OUT1____70.000
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--library unisim;
--use unisim.vcomponents.all;
entity SysPLL_inferred is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end SysPLL_inferred;
architecture rtl of SysPLL_inferred is
begin
CLK_OUT1 <= CLK_IN;
LOCKED <= not RESET;
end rtl;
|
use Std.Textio.all;
library IEEE;
library worklib;
use ieee.std_logic_1164.ALL;
entity test_c_and
is end;
architecture test_c_and of test_c_and is
component c_and
generic (width : integer := 1);
port (input1 : std_logic_vector((width -1) downto 0);
input2 : std_logic_vector((width -1) downto 0);
output : out std_logic_vector((width -1) downto 0));
end component;
for all : c_and use entity worklib.c_and(behavior);
signal input1 : std_logic_vector(3 downto 0);
signal input2 : std_logic_vector(3 downto 0);
signal out1 : std_logic_vector(3 downto 0);
begin
and4 : c_and generic map(4)
port map( input1, input2, out1);
test_process : process
begin
input1 <= "0001" ;
input2 <= "0001" ;
wait for 10 ns;
input1 <= "1111" ;
input2 <= "0001" ;
wait for 10 ns;
input1 <= "1111" ;
input2 <= "0101" ;
wait for 10 ns;
wait;
end process test_process ;
end test_c_and;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 12bits
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
Control : in std_logic_vector(7 downto 0); -- control register
Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
Env : out std_logic_vector(7 downto 0); -- Voice envelope register
voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
);
end sid_voice;
architecture Behavioral of sid_voice is
-------------------------------------------------------------------------------
-- Altera multiplier
-- COMPONENT lpm_mult
-- GENERIC
-- (
-- lpm_hint : STRING;
-- lpm_representation : STRING;
-- lpm_type : STRING;
-- lpm_widtha : NATURAL;
-- lpm_widthb : NATURAL;
-- lpm_widthp : NATURAL;
-- lpm_widths : NATURAL
-- );
-- PORT
-- (
-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
signal accu_bit_prev : std_logic := '0';
signal PA_MSB_in_prev : std_logic := '0';
-- this type of signal has only two states 0 or 1 (so no more bits are required)
signal pulse : std_logic := '0';
signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
signal triangle : std_logic_vector(11 downto 0) := (others => '0');
signal noise : std_logic_vector(11 downto 0) := (others => '0');
signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
signal frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-- Envelope Generator
type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, release, release_lp);
signal cur_state, next_state : envelope_state_types;
signal divider_value : integer range 0 to 2**15 - 1 :=0;
signal divider_attack : integer range 0 to 2**15 - 1 :=0;
signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
signal divider_counter : integer range 0 to 2**18 - 1 :=0;
signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
signal exp_table_active : std_logic := '0';
signal divider_rst : std_logic := '0';
signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
signal Dec_rel_sel : std_logic := '0';
signal env_counter : std_logic_vector(7 downto 0) := (others => '0');
signal env_count_hold_A : std_logic := '0';
signal env_count_hold_B : std_logic := '0';
signal env_cnt_up : std_logic := '0';
signal env_cnt_clear : std_logic := '0';
signal signal_mux : std_logic_vector(11 downto 0) := (others => '0');
signal signal_vol : std_logic_vector(19 downto 0) := (others => '0');
-------------------------------------------------------------------------------------
-- stop the oscillator when test = '1'
alias test : std_logic is Control(3);
-- Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation.
alias ringmod : std_logic is Control(2);
-- Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator.
alias sync : std_logic is Control(1);
--
alias gate : std_logic is Control(0);
-------------------------------------------------------------------------------------
begin
-- output the Phase accumulator's MSB for sync and ringmod purposes
PA_MSB_out <= accumulator(23);
-- output the upper 8-bits of the waveform.
-- Useful for random numbers (noise must be selected)
Osc <= signal_mux(11 downto 4);
-- output the envelope register, for special sound effects when connecting this
-- signal to the input of other channels/voices
Env <= env_counter;
-- use the register value to fill the variable
frequency <= Freq_hi & Freq_lo;
-- use the register value to fill the variable
pulsewidth <= Pw_hi & Pw_lo;
--
voice <= signal_vol(19 downto 8);
-- Phase accumulator :
-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
-- the lower 16-bits are programmable for pitch control. The output of the
-- accumulator goes directly to a D/A converter through a waveform selector.
-- Normally, the output of a phase-accumulating oscillator would be used as an
-- address into memory which contained a wavetable, but SID had to be entirely
-- self-contained and there was no room at all for a wavetable on the chip."
-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
-- based on the accumulator MSB of the previous oscillator."
PhaseAcc:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
PA_MSB_in_prev <= PA_MSB_in;
-- the reset and test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
accumulator <= (others => '0');
else
-- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
accumulator <= accumulator + ("0" & frequency);
end if;
end if;
end process;
-- Sawtooth waveform :
-- "The Sawtooth waveform was created by sending the upper 12-bits of the
-- accumulator to the 12-bit Waveform D/A."
Snd_Sawtooth:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
sawtooth <= accumulator(23 downto 12);
end if;
end process;
--Pulse waveform :
-- "The Pulse waveform was created by sending the upper 12-bits of the
-- accumulator to a 12-bit digital comparator. The output of the comparator was
-- either a one or a zero. This single output was then sent to all 12 bits of
-- the Waveform D/A. "
Snd_pulse:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((accumulator(23 downto 12)) >= pulsewidth) then
pulse <= '1';
else
pulse <= '0';
end if;
end if;
end process;
--Triangle waveform :
-- "The Triangle waveform was created by using the MSB of the accumulator to
-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
-- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
-- but the amplitude and frequency were the same). "
-- "Ring Modulation was accomplished by substituting the accumulator MSB of an
-- oscillator in the EXOR function of the triangle waveform generator with the
-- accumulator MSB of the previous oscillator. That is why the triangle waveform
-- must be selected to use Ring Modulation."
Snd_triangle:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ringmod = '0' then
-- no ringmodulation
triangle(11)<= accumulator(23) xor accumulator(22);
triangle(10)<= accumulator(23) xor accumulator(21);
triangle(9) <= accumulator(23) xor accumulator(20);
triangle(8) <= accumulator(23) xor accumulator(19);
triangle(7) <= accumulator(23) xor accumulator(18);
triangle(6) <= accumulator(23) xor accumulator(17);
triangle(5) <= accumulator(23) xor accumulator(16);
triangle(4) <= accumulator(23) xor accumulator(15);
triangle(3) <= accumulator(23) xor accumulator(14);
triangle(2) <= accumulator(23) xor accumulator(13);
triangle(1) <= accumulator(23) xor accumulator(12);
triangle(0) <= accumulator(23) xor accumulator(11);
else
-- ringmodulation by the other voice (previous voice)
triangle(11)<= PA_MSB_in xor accumulator(22);
triangle(10)<= PA_MSB_in xor accumulator(21);
triangle(9) <= PA_MSB_in xor accumulator(20);
triangle(8) <= PA_MSB_in xor accumulator(19);
triangle(7) <= PA_MSB_in xor accumulator(18);
triangle(6) <= PA_MSB_in xor accumulator(17);
triangle(5) <= PA_MSB_in xor accumulator(16);
triangle(4) <= PA_MSB_in xor accumulator(15);
triangle(3) <= PA_MSB_in xor accumulator(14);
triangle(2) <= PA_MSB_in xor accumulator(13);
triangle(1) <= PA_MSB_in xor accumulator(12);
triangle(0) <= PA_MSB_in xor accumulator(11);
end if;
end if;
end process;
--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
-- "The Noise waveform was created using a 23-bit pseudo-random sequence
-- generator (i.e., a shift register with specific outputs fed back to the input
-- through combinatorial logic). The shift register was clocked by one of the
-- intermediate bits of the accumulator to keep the frequency content of the
-- noise waveform relatively the same as the pitched waveforms.
-- The upper 12-bits of the shift register were sent to the Waveform D/A."
noise <= LFSR(22 downto 11);
Snd_noise:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
-- the test signal can stop the oscillator,
-- stopping the oscillator is very useful when you want to play "samples"
if ((reset = '1') or (test = '1')) then
accu_bit_prev <= '0';
-- the "seed" value (the value that eventually determines the output
-- pattern) may never be '0' otherwise the generator "locks up"
LFSR <= "00000000000000000000001";
else
accu_bit_prev <= accumulator(19);
-- when not equal to ...
if (accu_bit_prev /= accumulator(19)) then
LFSR(22 downto 1) <= LFSR(21 downto 0);
LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
else
LFSR <= LFSR;
end if;
end if;
end if;
end process;
-- Waveform Output selector (MUX):
-- "Since all of the waveforms were just digital bits, the Waveform Selector
-- consisted of multiplexers that selected which waveform bits would be sent
-- to the Waveform D/A. The multiplexers were single transistors and did not
-- provide a "lock-out", allowing combinations of the waveforms to be selected.
-- The combination was actually a logical ANDing of the bits of each waveform,
-- which produced unpredictable results, so I didn't encourage this, especially
-- since it could lock up the pseudo-random sequence generator by filling it
-- with zeroes."
Snd_select:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
end if;
end process;
-- Waveform envelope (volume) control :
-- "The output of the Waveform D/A (which was an analog voltage at this point)
-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
-- (digitally-controlled-amplifier). The digital control word which modulated
-- the amplitude of the waveform came from the Envelope Generator."
-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
-- D/A converter to modulate the amplitude of the selected Oscillator Waveform
-- (to be technically accurate, actually the waveform was modulating the output
-- of the Envelope Generator, but the result is the same)."
Envelope_multiplier:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
--calculate the resulting volume (due to the envelope generator) of the
--voice, signal_mux(12bit) * env_counter(8bit), so the result will
--require 20 bits !!
signal_vol <= signal_mux * env_counter;
end if;
end process;
-- Envelope generator :
-- "The Envelope Generator was simply an 8-bit up/down counter which, when
-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
-- 255 down to the programmed Sustain value at the Decay rate, remained at the
-- Sustain value until the Gate bit was cleared then counted down from the
-- Sustain value to 0 at the Release rate."
--
-- /\
-- / \
-- / | \________
-- / | | \
-- / | | |\
-- / | | | \
-- attack|dec|sustain|rel
-- this process controls the state machine "current-state"-value
Envelope_SM_advance: process (reset, clk_1MHz)
begin
if (reset = '1') then
cur_state <= idle;
else
if (rising_edge(clk_1MHz)) then
cur_state <= next_state;
end if;
end if;
end process;
-- this process controls the envelope (in other words, the volume control)
Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
begin
if (reset = '1') then
next_state <= idle;
env_cnt_clear <='1';
env_cnt_up <='1';
env_count_hold_B <='1';
divider_rst <='1';
divider_value <= 0;
exp_table_active <='0';
Dec_rel_sel <='0'; -- select decay as input for decay/release table
else
env_cnt_clear <='0'; -- use this statement unless stated otherwise
env_cnt_up <='1'; -- use this statement unless stated otherwise
env_count_hold_B <='1'; -- use this statement unless stated otherwise
divider_rst <='0'; -- use this statement unless stated otherwise
divider_value <= 0; -- use this statement unless stated otherwise
exp_table_active <='0'; -- use this statement unless stated otherwise
case cur_state is
-- IDLE
when idle =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if gate = '1' then
next_state <= attack;
else
next_state <= idle;
end if;
when attack =>
env_cnt_clear <= '1'; -- clear envelope env_counter
divider_rst <= '1';
divider_value <= divider_attack;
next_state <= attack_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when attack_lp =>
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
divider_value <= divider_attack;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if env_counter = "11111111" then
next_state <= decay;
else
if gate = '0' then
next_state <= release;
else
next_state <= attack_lp;
end if;
end if;
when decay =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
next_state <= decay_lp;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
when decay_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
if gate = '0' then
next_state <= release;
else
next_state <= decay_lp;
end if;
end if;
-- "A digital comparator was used for the Sustain function. The upper
-- four bits of the Up/Down counter were compared to the programmed
-- Sustain value and would stop the clock to the Envelope Generator when
-- the counter counted down to the Sustain value. This created 16 linearly
-- spaced sustain levels without havingto go through a look-up table
-- translation between the 4-bit register value and the 8-bit Envelope
-- Generator output. It also meant that sustain levels were adjustable
-- in steps of 16. Again, more register bits would have provided higher
-- resolution."
-- "When the Gate bit was cleared, the clock would again be enabled,
-- allowing the counter to count down to zero. Like an analog envelope
-- generator, the SID Envelope Generator would track the Sustain level
-- if it was changed to a lower value during the Sustain portion of the
-- envelope, however, it would not count UP if the Sustain level were set
-- higher." Instead it would count down to '0'.
when sustain =>
divider_value <= 0;
Dec_rel_sel <='1'; -- select release as input for decay/release table
if gate = '0' then
next_state <= release;
else
if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
next_state <= sustain;
else
next_state <= decay;
end if;
end if;
when release =>
divider_rst <= '1';
exp_table_active <= '1'; -- activate exponential look-up table
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
next_state <= release_lp;
when release_lp =>
exp_table_active <= '1'; -- activate exponential look-up table
env_count_hold_B <= '0'; -- enable envelope env_counter
env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
divider_value <= divider_dec_rel;
Dec_rel_sel <= '1'; -- select release as input for decay/release table
if env_counter = "00000000" then
next_state <= idle;
else
if gate = '1' then
next_state <= idle;
else
next_state <= release_lp;
end if;
end if;
when others =>
divider_value <= 0;
Dec_rel_sel <= '0'; -- select decay as input for decay/release table
next_state <= idle;
end case;
end if;
end process;
-- 8 bit up/down env_counter
Envelope_counter:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (env_cnt_clear = '1')) then
env_counter <= (others => '0');
else
if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
env_counter <= env_counter;
else
if (env_cnt_up = '1') then
env_counter <= env_counter + 1;
else
env_counter <= env_counter - 1;
end if;
end if;
end if;
end if;
end process;
-- Divider :
-- "A programmable frequency divider was used to set the various rates
-- (unfortunately I don't remember how many bits the divider was, either 12
-- or 16 bits). A small look-up table translated the 16 register-programmable
-- values to the appropriate number to load into the frequency divider.
-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
-- appropriate register would be selected and that number would be translated
-- and loaded into the divider. Obviously it would have been better to have
-- individual bit control of the divider which would have provided great
-- resolution for each rate, however I did not have enough silicon area for a
-- lot of register bits. Using this approach, I was able to cram a wide range
-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
-- of eight. The actual numbers in the look-up table were arrived at
-- subjectively by setting up typical patches on a Sequential Circuits Pro-1
-- and measuring the envelope times by ear (which is why the available rates
-- seem strange)!"
prog_freq_div:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if ((reset = '1') or (divider_rst = '1')) then
env_count_hold_A <= '1';
divider_counter <= 0;
else
if (divider_counter = 0) then
env_count_hold_A <= '0';
if (exp_table_active = '1') then
divider_counter <= exp_table_value;
else
divider_counter <= divider_value;
end if;
else
env_count_hold_A <= '1';
divider_counter <= divider_counter - 1;
end if;
end if;
end if;
end process;
-- Piese-wise linear approximation of an exponential :
-- "In order to more closely model the exponential decay of sounds, another
-- look-up table on the output of the Envelope Generator would sequentially
-- divide the clock to the Envelope Generator by two at specific counts in the
-- Decay and Release cycles. This created a piece-wise linear approximation of
-- an exponential. I was particularly happy how well this worked considering
-- the simplicity of the circuitry. The Attack, however, was linear, but this
-- sounded fine."
-- The clock is divided by two at specific values of the envelope generator to
-- create an exponential.
Exponential_table:process(clk_1MHz)
BEGIN
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
exp_table_value <= 0;
else
case CONV_INTEGER(env_counter) is
when 0 to 51 => exp_table_value <= divider_value * 16;
when 52 to 101 => exp_table_value <= divider_value * 8;
when 102 to 152 => exp_table_value <= divider_value * 4;
when 153 to 203 => exp_table_value <= divider_value * 2;
when 204 to 255 => exp_table_value <= divider_value;
when others => exp_table_value <= divider_value;
end case;
end if;
end if;
end process;
-- Attack Lookup table :
-- It takes 255 clock cycles from zero to peak value. Therefore the divider
-- equals (attack rate / clockcycletime of 1MHz clock) / 254;
Attack_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if (reset = '1') then
divider_attack <= 0;
else
case Att_dec(7 downto 4) is
when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
when others => divider_attack <= 0; --
end case;
end if;
end if;
end process;
Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
begin
if (Dec_rel_sel = '0') then
Dec_rel <= Att_dec(3 downto 0);
else
Dec_rel <= Sus_rel(3 downto 0);
end if;
end process;
-- Decay Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-- Release Lookup table :
-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
Decay_Release_table:process(clk_1MHz)
begin
if (rising_edge(clk_1MHz)) then
if reset = '1' then
divider_dec_rel <= 0;
else
case Dec_rel is
when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
when others => divider_dec_rel <= 0; --
end case;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: LM.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.SimpleFIFO;
use work.DebugLib;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LM is
Generic(
kMaxLaneCount : natural := 4;
--PPI
kLaneCount : natural range 1 to 4 := 2 --[1,2,4]
);
Port (
RxByteClkHS : in STD_LOGIC;
RxDataHS : in STD_LOGIC_VECTOR (8 * kLaneCount - 1 downto 0);
RxSyncHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
RxValidHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
RxActiveHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
--Master AXI-Stream
rbMAxisTdata : out std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
rbMAxisTkeep : out std_logic_vector(kMaxLaneCount - 1 downto 0);
rbMAxisTvalid : out std_logic;
rbMAxisTready : in std_logic;
rbMAxisTlast : out std_logic;
rbErrSkew : out std_logic;
rbErrOvf : out std_logic;
rbEn : in std_logic;
rbRst : in std_logic;
dbgLMLane : out DebugLib.DebugLMLanes_t;
dbgLM : out DebugLib.DebugLM_t
);
end LM;
architecture Behavioral of LM is
type state_t is (stReset, stIdle, stWaitForReady, stWaitForValid, stReceive, stEndReceive, stError);
signal rbState, rbNstate : state_t;
signal rbByteCnt : natural range 0 to kMaxLaneCount - 1 := 0;
signal rbTvalidInt, rbMAxisTvalidInt, rbTlastInt, rbPartial : std_logic;
signal rbTdataInt : std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
signal rbTkeepInt : std_logic_vector(kMaxLaneCount - 1 downto 0);
constant kAllOnes : std_logic_vector(kMaxLaneCount - 1 downto 0) := (others => '1');
alias rbDataHSInt is RxDataHS;
alias rbSyncHSInt is RxSyncHS;
alias rbValidHSInt is RxValidHS;
alias rbActiveHSInt is RxActiveHS;
signal rbRdEn, rbWrEn, rbFull : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbEnInt : std_logic;
-- De-skewed PPI data lanes
signal rbDataHS : STD_LOGIC_VECTOR (8 * kLaneCount - 1 downto 0);
signal rbSyncHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbValidHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbActiveHS, rbActiveHS_q : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
-- VHDL-2008 back-port
function orv(vec : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in vec'range loop
result := result or vec(i);
end loop;
return result;
end orv;
-- VHDL-2008 back-port
function andv(vec : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in vec'range loop
result := result and vec(i);
end loop;
return result;
end andv;
begin
dbgLM.state <= std_logic_vector(to_unsigned(state_t'pos(rbState), 3));
dbgLM.rbByteCnt <= std_logic_vector(to_unsigned(rbByteCnt, 2));
-- Shallow, synchronous FIFOs for each data lane are used to delay data
-- on those that transmit earlier than the rest. Thus, data lanes
-- are de-skewed and their RxActiveHS edges aligned. This approach relies
-- on the timing of RxValidHS relative to the corresponding RxActiveHS to be
-- the same for all lanes.
DeskewFIFOs: for i in 0 to kLaneCount - 1 generate
dbgLMLane(i).rbSkwRdEn <= rbRdEn(i);
dbgLMLane(i).rbSkwWrEn <= rbEn;
dbgLMLane(i).rbSkwFull <= rbFull(i);
dbgLMLane(i).rbActiveHS <= rbActiveHS(i);
dbgLMLane(i).rbSyncHS <= rbSyncHS(i);
dbgLMLane(i).rbValidHS <= rbValidHS(i);
dbgLMLane(i).rbDataHS <= rbDataHS((i+1)*8-1 downto i*8);
DeskewFIFOx: entity work.SimpleFIFO
Generic map (kDataWidth => 11)
Port map (
InClk => RxByteClkHS,
iRst => rbRst,
iDataIn => rbActiveHSInt(i) & rbSyncHSInt(i) & rbValidHSInt(i) & rbDataHSInt((i+1)*8-1 downto i*8),
iWrEn => rbWrEn(i),
iRdEn => rbRdEn(i),
iFull => rbFull(i),
iEmpty => open,
iDataOut(10) => rbActiveHS(i),
iDataOut(9) => rbSyncHS(i),
iDataOut(8) => rbValidHS(i),
iDataOut(7 downto 0) => rbDataHS((i+1)*8-1 downto i*8)
);
rbWrEn(i) <= rbEnInt;
rbRdEn(i) <= '0' when (rbState = stReset) else
'0' when (rbActiveHS(i) = '1' and andv(rbActiveHS) = '0' and andv(rbActiveHS_q) = '0') else -- lane is active while others not, pause it
'0' when (andv(rbActiveHS) = '1' and rbState = stWaitForReady) else -- all lanes active, but we are held up by rbMAxisTready
'1';
process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbRdEn(i) = '1') then
rbActiveHS_q(i) <= rbActiveHS(i);
end if;
end if;
end process;
end generate DeskewFIFOs;
InternalEnable: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbState = stReset) then
rbEnInt <= '0';
else
rbEnInt <= rbEn;
end if;
end if;
end process;
-- The deskew error flag is set when one of the lanes was halted for so long awaiting valid data on the
-- other lanes that the FIFOs filled up. Possible causes:
-- not all lanes in the specified kLaneCount are receiving data, or
-- lane skew larger than 8 RxByteClkHS periods.
DeskewFullFlag: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbRst = '1') then
rbErrSkew <= '0';
elsif (rbEnInt = '1' and orv(rbFull) = '1') then
rbErrSkew <= '1';
end if;
end if;
end process;
-- The overflow error flag set whenever we provide valid data on the AXI-Stream
-- and the slave is not ready to receive. Buffering should be done downstream.
OverflowFlag: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbRst = '1') then
rbErrOvf <= '0';
elsif (rbMAxisTvalidInt = '1' and rbMAxisTready = '0') then
rbErrOvf <= '1';
end if;
end if;
end process;
SYNC_PROC: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbRst = '1') then
rbState <= stReset;
else
rbState <= rbNstate;
end if;
end if;
end process;
ByteRegisters: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbRst = '1') then
rbTdataInt <= (others => '0');
rbTkeepInt <= (others => '0');
else
if (rbState = stReceive or rbState = stWaitForValid) then
--Walk the valid signals, register valid bytes and set keep bits
--Order is important: last bytes are filled from low-order lanes to high-order ones
if (rbTvalidInt = '1') then
rbTkeepInt <= (others => '0');
end if;
for i in 0 to kLaneCount - 1 loop
if (rbValidHS(i) = '0') then
exit;
end if;
rbTdataInt((i+rbByteCnt+1)*8-1 downto (i+rbByteCnt)*8) <= rbDataHS((i+1)*8-1 downto i*8);
rbTkeepInt(i+rbByteCnt) <= '1';
end loop;
end if;
end if;
end if;
end process;
BufferCounter: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbState = stIdle) then
rbByteCnt <= 0;
else
if (rbState = stWaitForValid and orv(rbValidHS) = '1') or (rbState = stReceive) then
if (rbByteCnt = kMaxLaneCount - kLaneCount) then
rbByteCnt <= 0;
else
rbByteCnt <= rbByteCnt + kLaneCount;
end if;
end if;
end if;
end if;
end process;
rbTValidInt <= '1' when ((rbState = stReceive and (rbByteCnt = 0 or orv(rbValidHS) = '0')) -- buffer full, or no more bytes
or (rbState = stEndReceive)) -- flush partial packet
else '0';
rbTlastInt <= '1' when (rbState = stReceive and orv(rbValidHS) = '0') -- no more bytes
or (rbState = stEndReceive) -- partial packet is last
else '0';
OutputRegister: process (RxByteClkHS)
begin
if Rising_Edge(RxByteClkHS) then
if (rbRst = '1') then
rbMAxisTdata <= rbTdataInt;
rbMAxisTkeep <= rbTkeepInt;
rbMAxisTvalidInt <= rbTvalidInt;
rbMAxisTlast <= rbTlastInt;
else
rbMAxisTvalidInt <= rbTvalidInt;
if (rbTvalidInt = '1') then
rbMAxisTdata <= rbTdataInt;
rbMAxisTkeep <= rbTkeepInt;
rbMAxisTlast <= rbTlastInt;
end if;
end if;
end if;
end process;
rbMAxisTvalid <= rbMAxisTvalidInt;
NEXT_STATE_DECODE: process (rbState, rbActiveHS, rbValidHS, rbFull, rbMAxisTready)
begin
rbNstate <= rbState; --default is to stay in current rbState
case (rbState) is
when stReset =>
if (orv(rbFull) = '0') then
rbNstate <= stWaitForReady;
end if;
when stWaitForReady =>
if (orv(rbFull) = '1') then
rbNstate <= stError;
elsif (rbMAxisTready = '1') then
rbNstate <= stIdle;
end if;
when stIdle =>
if (orv(rbFull) = '1') then --deskew overflow
rbNstate <= stError;
elsif (andv(rbActiveHS) = '1') then --when all channels present active
rbNstate <= stWaitForValid;
end if;
when stWaitForValid => -- in High-Speed reception but no data yet
if (andv(rbValidHS) = '1') then -- first full data
rbNstate <= stReceive;
elsif (orv(rbValidHS) = '1') then -- partial data; first is also the last
rbNstate <= stEndReceive;
end if;
when stReceive => -- we are receiving High-Speed data
if (orv(rbValidHS) = '0') then
rbNstate <= stIdle; --no more data
elsif (andv(rbValidHS) = '0') then -- partial data; last packet
rbNstate <= stEndReceive;
end if;
when stEndReceive =>
rbNstate <= stIdle; -- last packet seen
when stError =>
if (orv(rbActiveHS) = '0') then
rbNstate <= stIdle;
end if;
when others =>
rbNstate <= stIdle;
end case;
end process;
end Behavioral;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY pulselut_entity IS
GENERIC(lut_bit_width : integer := 8;
DATA_width: integer := 16
);
PORT(
phase_in : in unsigned(lut_bit_width-1 downto 0);
a_clk : in std_logic;
reset : in std_logic;
DATA : OUT std_logic_vector(15 downto 0)
);
END pulselut_entity;
architecture behav of pulselut_entity is
--LUT
type sine_lut is array (0 to 1) of integer;
constant sinedata:sine_lut:= (-8000,8000);
signal sDATA : std_logic_vector(15 downto 0);
begin
process(a_clk,reset)
variable lutindex : integer range 0 to (2**lut_bit_width)-1 := 0;
begin
if reset = '0' then
DATA <= (others => '0');
lutindex := 0;
elsif rising_edge(a_clk) then
lutindex := to_integer(phase_in);
if lutindex < 128 then
sDATA <= std_logic_vector(to_signed(sinedata(0), DATA_width));
else
sDATA <= std_logic_vector(to_signed(sinedata(1), DATA_width));
end if;
DATA <= sDATA;
end if;
end process;
end behav; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc690.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:03 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00690ent IS
END c03s04b01x00p23n01i00690ent;
ARCHITECTURE c03s04b01x00p23n01i00690arch OF c03s04b01x00p23n01i00690ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
type FilT is file of DISTANCE;
-- Declare the actual file to write.
file FILEV : FilT open write_mode is "iofile.53";
-- Declare a variable.
constant CON : DISTANCE := 1 nm;
variable VAR : DISTANCE := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00690 - The output file will tested by test file s010418.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00690arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc690.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:03 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00690ent IS
END c03s04b01x00p23n01i00690ent;
ARCHITECTURE c03s04b01x00p23n01i00690arch OF c03s04b01x00p23n01i00690ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
type FilT is file of DISTANCE;
-- Declare the actual file to write.
file FILEV : FilT open write_mode is "iofile.53";
-- Declare a variable.
constant CON : DISTANCE := 1 nm;
variable VAR : DISTANCE := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00690 - The output file will tested by test file s010418.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00690arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc690.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:03 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00690ent IS
END c03s04b01x00p23n01i00690ent;
ARCHITECTURE c03s04b01x00p23n01i00690arch OF c03s04b01x00p23n01i00690ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
type FilT is file of DISTANCE;
-- Declare the actual file to write.
file FILEV : FilT open write_mode is "iofile.53";
-- Declare a variable.
constant CON : DISTANCE := 1 nm;
variable VAR : DISTANCE := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00690 - The output file will tested by test file s010418.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00690arch;
|
-------------------------------------------------------------------------------
-- Title : Zybo Board Top Level
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : zybo_top_capture_cotnrol_test.vhd
-- Created : 2016-02-22
-- Last update: 2016-03-25
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: Xilinx Zynq 7000 on a Digilent Zybo Board Top Level Module,
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-22 1.0 ashton Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity zed_uart_top is
port (
--Clock Source
GCLK : in std_logic; -- 100 MHz clock
--LED Outputs
LD0, LD1, LD2, LD3, LD4, LD5, LD6, LD7 : out std_logic;
--Buttons
BTNC, BTND, BTNL, BTNR, BTNU : in std_logic;
--Temporary Data Ouput (JA10-JA7, JA4-JA1)
JA10, JA9, JA8, JA7, JA4, JA3, JA2, JA1 : out std_logic;
--UART SIGNALS
JB4 : in std_logic := 'H'; --RX
JB1 : out std_logic; --TX
--Switches
SW7, SW6, SW5, SW4, SW3, SW2, SW1, SW0 : in std_logic
--Fixed Zync Signals
--DDR_addr : INOUT STD_LOGIC_VECTOR (14 DOWNTO 0);
--DDR_ba : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0);
--DDR_cas_n : INOUT STD_LOGIC;
--DDR_ck_n : INOUT STD_LOGIC;
--DDR_ck_p : INOUT STD_LOGIC;
--DDR_cke : INOUT STD_LOGIC;
--DDR_cs_n : INOUT STD_LOGIC;
--DDR_dm : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
--DDR_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
--DDR_dqs_n : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
--DDR_dqs_p : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
--DDR_odt : INOUT STD_LOGIC;
--DDR_ras_n : INOUT STD_LOGIC;
--DDR_reset_n : INOUT STD_LOGIC;
--DDR_we_n : INOUT STD_LOGIC;
--FIXED_IO_ddr_vrn : INOUT STD_LOGIC;
--FIXED_IO_ddr_vrp : INOUT STD_LOGIC;
--FIXED_IO_mio : INOUT STD_LOGIC_VECTOR (53 DOWNTO 0);
--FIXED_IO_ps_clk : INOUT STD_LOGIC;
--FIXED_IO_ps_porb : INOUT STD_LOGIC;
--FIXED_IO_ps_srstb : INOUT STD_LOGIC;
);
end entity zed_uart_top;
architecture top of zed_uart_top is
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
component Zynq_BD_wrapper is
port (
DDR_addr : inout std_logic_vector (14 downto 0);
DDR_ba : inout std_logic_vector (2 downto 0);
DDR_cas_n : inout std_logic;
DDR_ck_n : inout std_logic;
DDR_ck_p : inout std_logic;
DDR_cke : inout std_logic;
DDR_cs_n : inout std_logic;
DDR_dm : inout std_logic_vector (3 downto 0);
DDR_dq : inout std_logic_vector (31 downto 0);
DDR_dqs_n : inout std_logic_vector (3 downto 0);
DDR_dqs_p : inout std_logic_vector (3 downto 0);
DDR_odt : inout std_logic;
DDR_ras_n : inout std_logic;
DDR_reset_n : inout std_logic;
DDR_we_n : inout std_logic;
FIXED_IO_ddr_vrn : inout std_logic;
FIXED_IO_ddr_vrp : inout std_logic;
FIXED_IO_mio : inout std_logic_vector (53 downto 0);
FIXED_IO_ps_clk : inout std_logic;
FIXED_IO_ps_porb : inout std_logic;
FIXED_IO_ps_srstb : inout std_logic;
UART_rxd : in std_logic;
UART_txd : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant DATA_WIDTH : positive := 32;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal reset, reset_clk_gen : std_logic := '1'; -- reset (async high, sync low)
signal run_clk : std_logic := '0'; -- clock output of the clocking wizard
signal clk_locked : std_logic := '0'; -- indicator if the clocking wizard has locked
signal din : std_logic_vector(DATA_WIDTH-1 downto 0);
signal armed : std_logic;
signal triggered : std_logic;
signal rst_cmd : std_logic := '0';
signal arm_cmd : std_logic;
signal sample_enable : std_logic := '1';
signal sample_cnt_rst : std_logic;
signal delay_cnt_4x : std_logic_vector(16-1 downto 0) := (others => '0');
signal read_cnt_4x : std_logic_vector(16-1 downto 0) := std_logic_vector(to_unsigned(1000, 16));
signal par_trig_msk : std_logic_vector(32-1 downto 0) := X"00_00_00_03";
signal par_trig_val : std_logic_vector(32-1 downto 0) := (others => '1');
signal capture_rdy : std_logic;
signal in_fifo_tdata : std_logic_vector(31 downto 0);
signal in_fifo_tvalid : std_logic;
signal in_fifo_tlast : std_logic;
signal in_fifo_tready : std_logic;
signal in_fifo_tfull : std_logic;
signal in_fifo_tempty : std_logic;
signal in_fifo_tflush : std_logic;
--
signal out_fifo_tdata : std_logic_vector(7 downto 0);
signal out_fifo_tvalid : std_logic;
signal out_fifo_tlast : std_logic;
signal out_fifo_tready : std_logic;
--
signal rx_get_more_data : std_logic;
signal rx_data_ready : std_logic;
signal rx : std_logic;
signal tx_data_sent : std_logic;
-----------------------------------------------------------------------------
-- Aliases
-----------------------------------------------------------------------------
alias reset_btn : std_logic is BTND;
alias CLK : std_logic is GCLK;
alias UART_RX : std_logic is JB4;
alias UART_TX : std_logic is JB1;
begin -- ARCHITECTURE top
LD7 <= out_fifo_tdata(7);
LD6<= out_fifo_tdata(6);
LD5<= out_fifo_tdata(5);
LD4<= out_fifo_tdata(4);
LD3<= out_fifo_tdata(3);
LD2<= out_fifo_tdata(2);
LD1<= out_fifo_tdata(1);
LD0<= out_fifo_tdata(0);
--LED to indicate that the clock is locked
uart_comms_test_blk : entity work.uart_comms
generic map (
baud_rate => 115_200,
clock_freq => 10_000_000)
port map (
clk => run_clk,
rst => reset_clk_gen,
rx_get_more_data => '1',
rx => UART_RX,
tx_data_ready => BTNU,
tx => UART_TX,
data_in => SW7& SW6& SW5& SW4& SW3& SW2& SW1& SW0,
data_out =>out_fifo_tdata);
-----------------------------------------------------------------------------
-- Component Instatiations
-----------------------------------------------------------------------------
-- purpose: this component will generate the desired system clock based on
-- the 125 MHz input clock. Not the output is already downstream of a global
-- clock buffer
-- inputs : clk, reset
-- outputs: clk_locked
run_clk_component : entity work.clock_gen
port map (
-- Clock in ports
clk_in1 => clk,
-- Clock out ports
clk_out1 => run_clk,
-- Status and control signals
reset => reset_clk_gen,
locked => clk_locked
);
-- purpose: this process will reset the system when btn0 is pressed
-- type : combinational
-- inputs : reset_btn, clk, clk_locked
-- outputs: reset
run_clk_reset_proc : process (reset_btn, run_clk) is
variable reset_dly_v : std_logic;
begin -- PROCESS reset_proc
if reset_btn = '1' then
reset <= '1';
reset_dly_v := '1';
elsif rising_edge(run_clk) then
if clk_locked = '1' then
reset <= reset_dly_v;
reset_dly_v := '0';
else
reset <= '1';
reset_dly_v := '1';
end if;
end if;
end process run_clk_reset_proc;
reset_proc : process (reset_btn, clk) is
variable reset_dly_v : std_logic;
begin -- PROCESS reset_proc
if reset_btn = '1' then
reset_clk_gen <= '1';
elsif rising_edge(clk) then
reset_clk_gen <= reset_dly_v;
reset_dly_v := '0';
end if;
end process reset_proc;
--zynq : ENTITY work.Zynq_BD_wrapper
-- PORT MAP (
-- DDR_addr => DDR_addr,
-- DDR_ba => DDR_ba,
-- DDR_cas_n => DDR_cas_n,
-- DDR_ck_n => DDR_ck_n,
-- DDR_ck_p => DDR_ck_p,
-- DDR_cke => DDR_cke,
-- DDR_cs_n => DDR_cs_n,
-- DDR_dm => DDR_dm,
-- DDR_dq => DDR_dq,
-- DDR_dqs_n => DDR_dqs_n,
-- DDR_dqs_p => DDR_dqs_p,
-- DDR_odt => DDR_odt,
-- DDR_ras_n => DDR_ras_n,
-- DDR_reset_n => DDR_reset_n,
-- DDR_we_n => DDR_we_n,
-- FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
-- FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
-- FIXED_IO_mio => FIXED_IO_mio,
-- FIXED_IO_ps_clk => FIXED_IO_ps_clk,
-- FIXED_IO_ps_porb => FIXED_IO_ps_porb,
-- FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
-- UART_rxd => UART_rxd,
-- UART_txd => UART_txd);
end architecture top;
|
entity bar is
end entity bar;
entity \foo\ is
port (test : in bit);
end entity \foo\;
architecture structural of \foo\ is
begin -- architecture structural
end architecture structural;
architecture structural of bar is
signal test : bit;
begin -- architecture structural
foo_1: entity work.\foo\
port map (test => test);
end architecture structural;
|
entity bar is
end entity bar;
entity \foo\ is
port (test : in bit);
end entity \foo\;
architecture structural of \foo\ is
begin -- architecture structural
end architecture structural;
architecture structural of bar is
signal test : bit;
begin -- architecture structural
foo_1: entity work.\foo\
port map (test => test);
end architecture structural;
|
entity bar is
end entity bar;
entity \foo\ is
port (test : in bit);
end entity \foo\;
architecture structural of \foo\ is
begin -- architecture structural
end architecture structural;
architecture structural of bar is
signal test : bit;
begin -- architecture structural
foo_1: entity work.\foo\
port map (test => test);
end architecture structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1822.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01822ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of small_int;
END c07s01b00x00p08n01i01822ent;
ARCHITECTURE c07s01b00x00p08n01i01822arch OF c07s01b00x00p08n01i01822ent IS
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_bus(0) <= small_int'(small_int) after 5 ns; -- type name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01822 - Type names are not permitted as primaries in a qualified expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01822arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1822.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01822ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of small_int;
END c07s01b00x00p08n01i01822ent;
ARCHITECTURE c07s01b00x00p08n01i01822arch OF c07s01b00x00p08n01i01822ent IS
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_bus(0) <= small_int'(small_int) after 5 ns; -- type name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01822 - Type names are not permitted as primaries in a qualified expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01822arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1822.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01822ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of small_int;
END c07s01b00x00p08n01i01822ent;
ARCHITECTURE c07s01b00x00p08n01i01822arch OF c07s01b00x00p08n01i01822ent IS
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_bus(0) <= small_int'(small_int) after 5 ns; -- type name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01822 - Type names are not permitted as primaries in a qualified expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01822arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:47:09 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_hessian_1_0/system_vga_hessian_1_0_stub.vhdl
-- Design : system_vga_hessian_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_hessian_1_0 is
Port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end system_vga_hessian_1_0;
architecture stub of system_vga_hessian_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_x16,active,rst,x_addr[9:0],y_addr[9:0],g_in[7:0],hessian_out[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_hessian,Vivado 2016.4";
begin
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CAM_Wrapper is
Generic (CAM_WIDTH : integer := 8 ;
CAM_DEPTH : integer := 8 ) ;
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we_decoded_row_address : in STD_LOGIC_VECTOR (CAM_DEPTH-1 downto 0);
search_word : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
dont_care_mask : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
decoded_match_address : out STD_LOGIC_VECTOR (CAM_DEPTH-1 downto 0));
end CAM_Wrapper;
architecture Behavioral of CAM_Wrapper is
component CAM_Array is
Generic (CAM_WIDTH : integer := 8 ;
CAM_DEPTH : integer := 4 ) ;
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we_decoded_row_address : in STD_LOGIC_VECTOR(CAM_DEPTH-1 downto 0) ;
search_word : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
dont_care_mask : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
decoded_match_address : out STD_LOGIC_VECTOR (CAM_DEPTH-1 downto 0));
end component ;
signal rst_buffered : STD_LOGIC ;
signal we_decoded_row_address_buffered : STD_LOGIC_VECTOR(CAM_DEPTH-1 downto 0) ;
signal search_word_buffered, dont_care_mask_buffered : STD_LOGIC_VECTOR(CAM_WIDTH-1 downto 0) ;
signal decoded_match_address_sig, decoded_match_address_buffered : STD_LOGIC_VECTOR(CAM_DEPTH-1 downto 0) ;
begin
decoded_match_address <= decoded_match_address_buffered ;
process(clk, rst, we_decoded_row_address, search_word, dont_care_mask, decoded_match_address_sig)
begin
if(clk'event and clk='1')then
rst_buffered <= rst ;
we_decoded_row_address_buffered <= we_decoded_row_address ;
search_word_buffered <= search_word ;
dont_care_mask_buffered <= dont_care_mask ;
decoded_match_address_buffered <= decoded_match_address_sig ;
end if ;
end process ;
CAM_Array_pmX: CAM_Array generic map (
CAM_WIDTH => CAM_WIDTH,
CAM_DEPTH => CAM_DEPTH
)
port map (
clk => clk ,
rst => rst_buffered ,
we_decoded_row_address => we_decoded_row_address_buffered ,
search_word => search_word_buffered ,
dont_care_mask => dont_care_mask_buffered ,
decoded_match_address => decoded_match_address_sig
);
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity Addsub is
port(
a : in vl_logic_vector(15 downto 0);
b : in vl_logic_vector(15 downto 0);
select_add_sub : in vl_logic;
result : out vl_logic_vector(15 downto 0)
);
end Addsub;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PCm2fNIkeE7RqN1Qh8aDBzSz2JZdHrSd39tfvplEdg301UYEYTYTh7LAGuyNl/IWzVtXy/8OLKM2
jEsukhpHyQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RwLRXbOkAb7oBKsdG074UuSXcADZ7XW9e8TFDepVg3T5gHDHlCoCkhWq9htKPblu7CdCqhJ10k/h
vm6kCixqzAf7pRbi6Dd7yD8JkHHpD/JoCpG0CXkR/YkwyGacxzBT1e81vN7QTqojdxa7d/QRyQC+
MewlL03luvuOMVsoYDI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ig+L+aUsv/EyA85z3weCZqReauEsxoUG/dQGRFaaA5NTQinUnMmZKRSCqwqjwKHtQvgCVcrj39nv
BvmgbwrS287dmW0ayl0xVJH1ZBO4m/r6tWMGBH+BqwvlJuYzwDq+XuaVTyGzQsJQEpn3gOGPS37n
by3PiEpwE8sEJJzLmjC0P2WRWiChNAhPX68xR3rPYA1v//HykKkOMZR6FxpbRWStkhoP4ZXtekka
MT+U1HqIsEUXJ3yu9Lv53E1z+hITgeHqLQuoHDZxe/vo1aJp6P7bfmUYBqKcuhtfI1+q/ROLWobm
dwK7BAzmKU9Op6712saAT0JuiaJqDfbDYUHO9A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
lsIBIwPgIXnrlbB1KQUAyK5Bmb+zT58EQeCjYseHbFK6kNgAjElBgxkvBKz1ldl+9Q1yKo9moyZ4
0HyIHRAHS95K/FmwvZR8HN20nLUworQZNn1ZSc4snrj+MuW4LurL7+bP+fn5i/mEoYRMkwf+hLQ2
pxb0CiqXIODA5ZIP5pI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
B4T4vMluttJXNdEAWlnoeDvXFlnigyOiQxAptjffGiB+sVVUpeE4ItUuQIRNPONjqpFlyqMY59aT
BzHfGmB25cZxQOUUdyiY2I51XOBeohLT8+YNLywsTYYY9gjqJGsNoMYGBy1/vYQ1yDSpY5QEuAHL
HcpPLsR9S/YaklUk82wT85wlXBEbo3w1EX2jAIcHHgFKDtVpBBrxw5WWxE9wckGNsaRnIB7WuvM6
U5XE08mbJJz5+nK1bcsOtBfGhk+0ZjdLIH5Pb5sAhVUy9iyG4VfJojcINLmFVH3IsTL+uXTZoTaH
qqG9CnqzsOurHX7xzG3E/qxLQpSyspS9D9m7+A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 49984)
`protect data_block
mEBP0ABPAZMGPygBZ+3A4rrfbcXqoNm9XAESvAWSw2wROhWE1vjZcxWrmMh980Jn//D0gyiz1zHQ
yypszhP6L/3y5GJXoUdl1yQM/8cdPXwRLwtCSeFQSGFegp7gvVbBnYY66DE840VClP3gmYfvdfsf
1/lKB+Xngsa1uSzu4k3q+TpXHySJBkRXpeWBgtX6LsA1Xmn1A0bZJhlD5cmxneLqQnocwsx1Nr/s
+iEwH9W+5VvEM+S951y0F8pYthN0AjbmetzsKxqx5GAYYXf5zTk9Y1QUHsV59QfBUCjIPJvkb3Ux
z5dw/py7kykH66Zx3muyyQ2w+FnxR0fQVUzgeIphIIBOU9FhL1OQXAg6vHeW0K8g3tt29xFRJGHV
R3b+uESIGETq8FLFR7H90FQbQwxYRcXG+QNaBd0N0c9eZL8hqw4Bv0mkk9eo/zGufpkVQhUf+9+G
49GBylNHxrPjrgokQTUEmmGvwZ/viIsi0kv/OXHUODXOZ655XfAjcs5JLKpWGGA1n0TNEIcrMb0B
U7JMrLpPuV2NCH/+yWcyRZF2Sd/IOjxi7nHGTTcxs46qNJ4V96YQk1jZyaMLovPOHNXeOFomkplw
KnlnvjkB47WovM6h6fPfOXf+srjhIvd7LH556cZr42oVUCYKWQsLM8+4YfO/QCidGudZtYt8Zvpi
i7YqZufjmElH71eMwURSPaYKufTN2+pT5uavdsvCcNpoHU08eemyblSkpZGhgdA/7Aq3Lan3thWg
7Fe4gY+cO8YYjNhh7DeoOsqOEOSLdVFYkJGslOVVCQKeb2RUsDL8F3BHfJAZjr68uCglmL2zIhfv
4VPhI3iTT1x3oj0QtF1Aqc72FPPDmpQocmsZMplQcb9qJUFSw1dP1hZ9BhTLOlgGuEeA/5tXjeVR
b06ufNa4aqOfl/bflNrauxN7aiV/nCvVTMbrgagVm+Egk9ve8UH52SBoMU5vhfxJ4TvgPoZ2cP6s
84rBjOPmWhSjoQ1HQ6aso3LbQorkIKwZxHN9+tegEh0YdPLK4uOu1M96bsbZ68GBJheC42WQ+N1J
s7e0fIbe5fjlWslTs+jOxyjLPTAZGR2zaQCE5tNkPn3hvO1HNkExyDHMZE9McXnm0u54gMofmSRt
XBcon/wgOtuYKVxNux2KOkbQMJL2tJT1dUGt430GWigYeK9YAPXgS3Lw0UjDX9jOFxFbhO+lnw0M
BOD2/1/k472EiDAa17tLi0ubeIn2+vvmRo2voq5dqWdIMKLwOV80mXhZsOIANlCpyZZNRGOOOvpw
PHQN4bW0uOfqKZ4Xa4sv5/JrBCub6Q4JVnidDW1SSrn+X+93VRbDQHsIVIxtUaNPmMGoNmEEK22J
LhuVAayTR13iVuICrLnHT5qhqqmYmsUlHF9IAERi+IoroJ7/lJBcDPeRzyVW/ma4bkD/76QoZ/6g
iCxU+ATOZLZnfQpRIGxGsUhTAIBKEUUB3y0dlet1OFQl+vp+/zIAQFgWDwewFQ5E6nZ82c35+ADZ
YBXFEt4cxOxeW6Z+iifmAXd5D4W1VR2wYD+eW+utHqK8ibHBG9cIKGWrcVZr0JLDTIr5aCQBr8Fb
zmXZuakbpTwpQJSnSp4L2u5U8oG//VRdmm8Fb551zOlkN6YzC7bWMNAxLdhrp3KngvRe8S3YHvWN
hQyL1nrotNxkUQCwm/J7loCAfWiopX1gWH+46cjBS6INebNu/+FM0EqW+3Cf6eUyCQIMzliMUAId
PcqSukjT9H1rvaXpZ+JWmckm/jPn2mjDlHkWviUqWUWKHst5J85oRg393M0BI1WOk++DtFpYlkI6
CMe/vKk/i8XGI6qr24bu3d9JiyPLkZh43GNw32eBVEM8SSwDJdT67tpcGUolW7BvZoXOjyz4z1PY
/6WZkYW+LZKcS1ldQZKZsVOI1jq/YKsO7dJPuPKtI1dMo+BO1PKpJUGIelLznSF1sUrCc2aGeT7x
bcSxlDNwyyk9LxCtKX4aOJDg235m8nXmGwn3wBoJYGRAA0iYJaVehAKVbLrH7vlmMynoRvNYVgf1
BZcgQN+wCIZolx+RV35UUrD8vJj+MtJ30napfiAl4Fic5NjmulwcfcyX6FuL4lWvQaXXZ2S8QIVP
uBanJKj+SpgEglmlNJnEAbLwipubUTH5A6w50C/gAONIQcLPNDdSbH/ouUsbRgySSN6mvW/wv1Qf
4OxofA93boSVUQMkjYZQtPk6YJv+sjp2/rpHUAGfIxBsgRI4qlWCx4dFnizt32dOU9QV4yLvP32d
Cu5we3wWPvikND1c/6HEexHz0aObITN1Vw79mXrHl32mEbNGIxTR5Es0GDaC9A4E/Ke6DekD2Uoj
kmT51MzbwPCr4g9OaBQH434gGFyHR0MJQg4OrGnGR9cXgghsexoRjMfv2t+iAn62KqsL2JMow9zc
rOcEqNIHPAtuQnFgl7UzpUcR/XwdkhEXTJHtTJ5b/jvjzPSlhns40PpKm15xdNlQs3OSzk+AnVlV
58fVAQjwmOp+6Zgf9G0G3ZWMXLSHvPFGRmhMDRyz9WaSWvRsrhCJC5ire9+q8UPJ6FkZW+bd1gPG
1+yQEjDO7YKHsPmqevmEOF5dSzxF6kV+Y1quM3AZXzEnFfKUc9P9FkQio9Ikeq0G3fx61h61c/ge
ShGRjpPUE8nQ6cNknkPAlCthCYprbQDT0wGO5CbtbasQR1kuwZwFIHjJk5mmw7Hk7qo+m6o1IXVS
P7xbouV0ffTEsAt6Qn4rDPy/uk06WwHcZ07mOmPKwFRDYS+aQioTUXt4AAau1DyhTKAdnnCsrjEO
03Ej1QDTxWPaAgCW3WREemu0l8szGMTkeHSTLHebUQSawFq/x1ZRwlbTW5mof8eDc8IjHvBGn98m
GiRKC9ltxSmkFKeifhPflz/wquS8dStSoE1GhF5xAt+sYG/DNx39srxrMNKhgjnHc30FXlR2maBR
uajcqBYWafm5Q5fEo4HrhMBC4jYsrpw0laJwevWKmk6qbuzdi+RxD39D7sLAhvgz7cr201fe1cRF
PnljiZ2LC3TPAm4CLAXdwl6s9+FU2B04rhzpc4z7S9lO9E+PIQxoxQSOh23rR5xtTly+xAF1fNVA
9nAIZ8q4dR2zcXSgRNWW6m8IePSrWj5MoiH7KCA3q3QVzpLMiwkJ+GafbOchw/PlM2G+Tg7qpMD9
zdOAdLhhmFjx67zRUzPvvLWWwWrURfqk4Xlg2Q06kWSpO8M3LtAZScrgt9sU7oJ85CcRgvw/maWl
EImhWb65cxBKesP21SeSSKrFRoqwVDPCSnryJlrX5h2mYMWhiHTGDjqHSVS9AACSZNdmDGLgIvgS
NT0iiIg+a289GF5gTRfRTT8IMii5iBWY8OAC31gsp4wDyxXbU7I5Ydiooln8fCBH0N4g/dXETexN
j0fUQ3SI8x9lBCvyJasCUpNIFlathv1kF+p+210+XbaXKXSvxet69rfqWJKyCZyzDVDH9SW13rA1
nHuZ4SSEH6pLe7d1s+x7aJrl6Q8j0m7BfudVmOki8+vXmhoPCtZQZK88s0umzlQJhU6OcVG9+cZU
azwx2RvXGCo1yLi3d2h8GGXJ7/0KbvOcfGFu6ewEOrHyLfGHYQlKPgK57e0t0/731ImweBQl8nQu
6vPER4eJCubBqhRbPDz7cOoNPsRzKSAJIOMNTwzUHyV/2Vg8nsLVXLmbmzqNcULpxEWNwWdBGVtg
A+0lmeLyHOfXUO51K6FKNJH6hSWNJryjqqgBQcaGaTMXu9WWi+ZocTgOplK/0N1crAQW63/iEmMS
AG87ZsL9C58gSKXJl1fFrX0IK1vdSe5tlU4HYtHnYt+BCVlTUHdAbVxIdts/q3KBo8DnNcQE90qE
M/gVaDAXcSKMsz9Ci/zyBjvUTDaK6GpPMlSoUoyMZMjuWxgtnnjDQTcB6gyaVGFtghnqRb/jCVEO
wVryiKYAEfNoL5MLMQJc+pYrfrSdtRJDcgE5B4LkgLmlkb0VDZii/nNBrwr2FKwvIODlx6vrvSUb
UtSjasTXkkAk9JdpW+fA4/+wM9LXyxG3iGb7bDACHWVuwgfm9bbv0lIAXkqzTaeRoPr3+iVLZWmZ
PIn63gB5FODd+KF0YVKXt/59VvqOnBZwktQlX4YJNnh2ohbOgaDD6kU5d0JwIfJemLE35oCFzhh6
BeOcG617ZbdI+7nvlF16HLENsrVlzLKhJNdScSf0PrVdtp5ZbPzZyH15XMeakkhkk43QeJ8KHRh0
0GG3RGeU2a2hXm0jbYVSfNVup4Vb09NPfd21WqWq9Fw/jwXys348AQXUKnVWDhTeCyuRpiBxlo3b
DsYEkpBXe+eI3cXJ0EPaPAZEa404YyIYqsiYTM3/xozoOtK1H8/+XC6yScBr4bOzAh+WV+Phrrih
9AXYFhTN5ZnuRVWCIPeNUmTLfEegp7suRYPnn/8QCU95nOv9A1fawxXgVjKx95Vq6aWRVSWGeowX
/6FDXkLqChsQeNCGGyxOihQtv7fNBGIgUB4wm0Ae7nC0g2GNC9kTMkBVCX3vZrWjmcGG/zQInJTa
5UoDLYQtBkx4HzCQxrwf1TaRBKg7Wq4KQBoYBf4ecTKyrLDlgEzYg5phG+oLsMfj9tcOiKPGqm2P
DGPqpZNIoroJaaA2O6SETObcnHGG5KcKwdMLnJUZ6NUWuTdM7Q/rkaybqHeF8N4CvR1ekKy6Czh7
hJFYTYx4t6ke2kzI5S4RQLZmc72pC61rViG4yVywcSZAGrJ/SniNr4NhlzUJQmL2Vjk6bepHOwWS
qr8ItNmtsEeAj48yF9F5lDO6l4sdwPHOE/Ts4mne4NfMjTw4Gkuurtr4o1TuJCNwjw56nHzG+N52
Yb+if69OYWkPNbBZr4ADqpq8CTzZFa5QnsNrfldmKllMH9cM+KyObDX35SQ+Pini9yxLJtBgILU6
nocoL7/ONYIgFWFC8RBbDEzbbB1Y75OJtxE8EkkBjvscKGUj7krtMwhFDh6WoA92JCTuYKLG+ADQ
PUP1/0fS7rNQZWNoj5AbJ+U90Jy2JggUzwsVCvdXxoig5ekG9nWqxH3yQyNr+yKO10UNikRoEhuU
SK/lOuUktSq5hsChM3rI9tzOwkR08Hch6h6UsGFHgMMDW0Y645SzUy1JiIuYi2tOqKV/SBcBUcSE
fsPhJ74i5Wy5PX1YVwgVp9Aepth9NYY9tQVW60fMWItWa2DTm7Bd8EBSgJliOn3IWigSmPZfhchy
K8yIaabox5luscAXqM2trV2iI3yy7/vFrIfDzIZHT6z0U6gSBeN0DqBtNREkIL/sYAEK2eXc/zDx
ShRhH0kkNalb8PYuxUJe4o5TzKvrEAXby9B/TcQcvDgX/1/EkNBVQSsBBxG9j2opfREvYI5TDwj/
NFzHyrvPO0Ykxxi5Up539MEfxhsn07FdEm/e8NIAWHJf6E6WNoonvCNquTGsMgDGad34Ba2LMo1h
fCpGOhJTsc9MMhNgNMPz2v9fkZWXBvvbycYxfReN4ZSZ4lQWUBvbFaw/h9PKdGqsOxXlNJSbqxAj
DPBXoLUFQjgvhFkRtrrOgJUeochtdXgpB0hIhXcxTiGdH78aO+LdSRHWAiM2Ky8gvBiZWg+k2ay4
c1EEyB9U3ClVuSKhVt+WXxW17bLVYKdYhqhCsW31sNzmy0tAzwRjPmr+I/aDGuH3A9TOxKVqqKTE
W7Qb94X4YGJJxsnO8QSiOLzSVgxupVZw+4/HBJ+G4YyL6+kDbO6qkOVVhD6SZEw5dl2te/ZrSari
+Ai9nwhrfjal0xekmwCQxVrNeL/K9HWCYw6hJ0SUccVLm4BaWglqKQDgHM3KIaLwZjdM5YxQ1B7H
iX0yIyt3cmiptWXsCLMnHn/STH0H1KWyKAwU2VbtbfUx06vJCGN2mkbNccmrlLfp8Kkudg2h371v
FcHv3fGQ6KlsYXWt2J6x5CBCjZBouOq6X2gRKwJUfBPaA+WvU3bHUsmp5ut+W7G0b3r6E5smJ47A
s7QrNKw2wpWBy5CyOZZ0c0yCKt/GBofjrb12TrjbYQj8plC7fzyS1AxzXzNb1RsAlbJ8QpJeh5M9
gTuLKigY8odRWt3z99F1mMbclaS/JUIRvoiHK6mOJElT+55uF6ocKoeAbkSj0fhQLvD8ucG3Y7ob
OfBRIbQ5Gd6/4p8x4kqaeX7lRJj6T7ScXdHhrLuzBD1JLA3CaiXsSgfC2RVNFLPUQU7fhUzOve6T
1DLt29whg83Ve983H1F/DTliUItFVMEgTVfxY2XTBjrgYWlQUhxRvYSUw3DIcUF3mkK+DuNixpFf
mQPZdnoslCiOZnxPHqJGXu//Llt0FBSUMT+/sKcqgdOKsL5WmZS56DAhkxW4xAvhEJ481R83Hn4U
jBwLctI2KS2xS1mwrBtFZvavljU0u1e1D5blHbzmSZXvww48XsZz4m+7sYo7Loeo08WRONzWs3gW
zvH2tW/Ws7ykztRpY0/s1QpyeZcwaWliNMekisstB9mv+4qE9MspYRFLrX44CVKw5UcP+cGdl9Is
R7ofvhx4IFworkq+vyjF1C1YqHULTzq4xyiYImsD4gI7KKuiK8j+GshAtYzEWUFMl10oeQe0swZS
S1HvtOs7Wd9akmqWQwkjICDUNgw9OUT9LKUO7K8UmIZpl5tozBQJvS8T0ztcUl6XBswHkx7JFXN0
oWxEqeePYC978n/zajWC74LDXxfiR6VUERTADbajEjYwyyEfj53W3otHIF6h/k4So/c19A7ThDTr
0pNEXINybhHFJXX24wte7m4VeMZJvknyeHpj2x+1cHphr+Q8wyTV8JT6IgvCbsonB1LyfzzM2dC2
p/etF/M3cZQHza3N7ZYA6VqaH8qNufPsGjsNaxzbKAq3m4zOve0u5fOhZmbbtxzwIvCxQq4g0K5h
zyVdw1NuLpoco+3p+8n7ihLAbBXtDFAPC3URfOW1Feks2/s1YoFdGfcKpkfbPz2F216ofji9lHxg
egx+BhQDWi0IFr4p4Srzcgd8lBThE1gFeLMYjfbJ9rao8VmDk/kAypsJz4StC2lFu4FlPQjTpN3p
KYMPyjUnfXhEe6MlNXIr7ReFiXLGDCteLK/lsRBl4fNr30naOR2N92x0K0w4/L+lFP6yhXnt6hYj
kONaS21rfBOx0GMGpw8jE8cjyb29GJdjc4xk1kWSTinNXrFEIur89G5w4lXvqHbPhe1+vEVz34fj
I7z+081LEYulZeBX0lw+ch8U/YkKjr6UEHHXn7ZsCahlBc8x9DiUZ7Wysm47Vp1ZQI8A/UTCHUnN
061xR535tMQ5yEGd1MJ3qMz2d7L27R6Wq1JKRL29zGGVGcxoRzfGFKMN294aUTVqBvmxQoXx88QO
IB2ytoC4Ajp1dwl4s6ePu6422FCajA1r0QXluKuLv66FTOMxjlLqkKd7zfkU3iRWdgD/xZNX/Dyd
6XAiRnQcza3p1F9qFwI0SCHypM8k8SEgngtMPiaKjX4gzWodN9ORLFX18cEAU7csybSDsFRMnfVp
E1xa3wVo89xZWw7lfrXjM8doH61HDZvKflpRmITwHG12kNO48TP90WY+T4o23Wg8LINQGKHj/P/2
g/eJMr5Fmjc8cVJvGXLJ2yvgfRmq0/crQrQjqeTKjUhreMb+nb2/xeZqP2c/aqpSvA9xgEQulNcA
IzaKpy/Qctm+eTGeBVZynVP2M2LskhBBeroIhy/EzkTrE3bvl2yaBJkM/SU0Zp/wPiXUCksDpivz
41cm1RyH6eP8aJp+A0OBM6/JLnECjLg+iYSZ1UxSrVCfBPvk5zJH1Bt+ziC/u9c8HqH8ft/XdRS8
4bKmJ06eM9VtIpIW+ZF0cI+T1YVo69sYWrkcfLyHdzC3rlEb8Dzm/gdVD26/9MDgqiVo5lIq9YVL
42vWxE8HarcV5HRo8YzLKr597xDkZM9YQdKff5gme/ECWa8pO3p0pOCtxdRWpIvXbV7ECXSUyRTd
mdWnZ3CJ+5Tc8dJ2nSHmT5F/M2GtSZ83Tc2TmAJK1FOW5kvoJDIZSg1BWhevYB2Tb5dAo7QW3cR8
WZ0mko4ZGgi530N7NLxsm8KOmQiW361C9l/ylUhy4DFhPNLhzyZP464xKV9ihj8ZGcEX06j6ev7Y
+oMz8pqRhqKwMisQsj39gKWrhD1iQ6zEby7b4OAFZSQzVmQhIeppJrtLjV21/VdRMgudSFvDjo+E
Q0m/bQV5oREXq2dMVfmIjP89xJSexpSu3RzFJqeYoiT2d7mVkZAfGmFuWl8HoeLKiLEYwC6GPPdu
VTpPBSO9O+lCC2WNRC7YOveWecv/kXdt3OYYHUCnpNvQtnCxswl1aUtwFwvdnqE5KtrReAFzIytJ
mV6I1wNAEPOFdPbaBSjXS70Hg8tqh8VhlxLf1s7BVLkieyOwXpcPowhYcJJ2Foh5zYSFmotL59E+
6vBR1FnKqbc4diqt4Zz6ULVa5SH2CeJFs1wfWaKk/ARoI5nStrdZ8VquaYEH6+ehwPpyeNlx6faY
pBgfPycVvErI/BvrGbKL8HeaYiV72JNix39x+3CG3r178mo7+bHeSRDYdsztaAhD+Re9/hfiB6zs
prVG7qX942RXO0+oUEoWiXCQdzPJqeAwjO8bVVrqL0eTaD0OBLZf6EpaaXoqz8Vj7dXPUdyBu1QS
7p8clsnLeTDrBSQWqArZcaxXc5HC09jSm+ZZCmERhSJucNpoAnSj8JqF6f+pOrn2HbuH9XcopYgP
08+Cb8Y0a6WhYo2lLbLFRQo+Ufn+ypeHIfHWQOLNW4tmnIudWgkUBD+x/1q07EJaddIdTjuHLcK3
rIks2VRmIQIHqizDLWufkxw8Ke/LAKLkJidca3pGIzTd8MgaKqF+ZmUwVJSRq9+l3+z+HNmvfxwV
RhSn1p590xyvFsJCAnCchoDasvizsgNpb5vvuE7cfT8fFyEsmOoMLS2Zg5xldhQ0K1KagdefDIr2
K8ABBoeJJFKkhuDampKLZMo6Gu8NF7IsK95fX8hRWqmTCn57diEu6ZmYZ6GXwW0MASgMpTDRrRoV
xQaCQ4YxRMQ/LJne4V9wsjTizU+8Ghq4GBsyNtiWAuzWWiOTPCyHh1mv44iPO7UTD4SLMLIegrAS
goaoHGTTzBVE0KtmEjM4RtOJmO/uEDcoY+Sgs6biO6aIFMIAuQoo2EpAEmeoRIkqRdcN5wPyRLL7
Ea0it/KDqn663lcNVUwOaVWM8giobK5c5Ynox+U5tUEj3RijyiTwEK2ijN2PdgQL4MF1kesctPL0
gIdrkPkacImrovmDtsyRgzQn5ivJeUR8VL3WA28Jw6Sl6/OM3NPf/UCWLPuiGnvsFkoAgOc9N31r
VxBGJamxsVhDPkj3bTCzoEvjaHdUJTwU6dU3pYDHhzWPG2lzSRltclBnQ7PX76tdKLiBhhHvuBEG
r4Kkhh2jQThNzeM8sScsyebLNrFm20iuRGuuIjosIdsjjnYHOHv9jBU6hOnfvXvaVlq82kn6HCCv
1xca/TDiZNNBqFomg/VUgHsRyeg/uJ2IBRdV9esvvc0IJGrQMubmnsvXgQym4L+41gxv5nzWjhnN
6pZ+K21bv/AgPSMZkz1s/rrIbWBeCgjcoLv82VMb4Js/Z8PotQTvbf/nRcXM1Ad8TpmfcXJG+G3+
vl28Ep2SgFU5o5NGxpxPe0FKqVScAklShByK5j3LhKbsfp0ELfaCArLS8pdXi2MJFRwgG8TIrpzP
OJR/1ayiLGuFH5Wqj7FdQxe1tjPeHcShuzi5k3S9zkQk3PrrGZOJSFc9P5A6hmBly47hfZW5HINw
Lg+uLzQqeQAKpurpjxqQG0YRu88tlDWLM+cQmLd5JhyG68vCPsFo4nGwLvZemuUNFlBVskt15hhK
ZqssQEyxQ4MF3PwY8saKUBe9ZE1AFMo3tv29DfG8tn4Moa16o/j0FQjh3jkXr52NSCJGvwROjh88
ZCeJ0PB7ReHEhopPhRt3NPKpGOCaft+otB0Ez37CwB1Nr/vq//ttN8nnJ/pMQ1LIIu5ybYmi1MRF
1umwqapNjQYngZXMxo+74Udc6Vx9phOrdXw3a7E7f1O6DBlIzfLvIcO2nu3kqK6Ok9LGmhirxH+z
ZPNkDR+9Lm4WCcjZWaFkzqfszfdtXpj1Qz7ac7ZXao1uMOlFVsraOuzyeFsM4hCMhVV0aTLmo6WB
JilyieCmNcMg5Y+bv4tcClQNK58tVUGLyMpHZXOlvix3vmw7HDUyF5DsUmqFbizMv1cPq14BO3iq
/2B7P4pgpkfoYSIoOxAqL/RfKHgl/l032aBtYH1YcmBn/d9QbZnu7JnuDQ7t7zdK5Hq1AFEm0WWM
AMm4L90OXo1xIjYDy+XBCDlk70OU2N9VAPRRgVKMxOFNrE1zD/YqQHDDmruN8CcXaFrZ4wjyUFdr
KEtvjqBpQktU7nK03Az3eSZ2pFlv5cWksMFV5Qj0TtcrIvTblh5dFvjHSiqKLQydoEy+33xLzllS
bWi4elZbE+Iv5nzL6cs5RBdXiCpBtj2QLlJr59GC5G7aejtSQH8CDsIVvILzvqYLi427e4+T523I
O3Jh4JbPc9G+EI9IBRNgCIeK9IihixRcuDHgYQCf/+sG4rqQmXWzeWLctNHD7tDakN7EOXfJO245
sc9yhzdRkfJx4RnocwSUqlfjV6vlJjtiK1/Ze/GeArnIclSHt5+WvdDV8iI9up0S4XRHdNO32hYm
rHuZYdykNPlz5Q7MwprmVy0TOWWybDtdyIGM/MBKrwQebT+yZR1V/oNw2gscOPmbd6uGj0qJgwHW
L1hAQRSwdvHrz7gH31B9xgq1V7Lx3EYXA1iWkXHH5L9qNeae393UaCmVTOq5OKpewD5+89HY3ATg
Hn62YzoFT5umXUukxWNEXE4UzyEXBc0rNhgMIWc4u083nmuPS7DOYxfmFlg3odraaM4ggW2OprKx
I27EC9UksQ1o3lE9Cdhsz2Lf6u8haDj0jiITWtQupPJ28jJkvSoMZS08esSE8FqzLulu0fbNE8Js
E4xU4RyN6ilyRrhh5E1BrvpPzB9ov0lCmIfh/m8S/IdpbWZuN1NNzzGpv7G4eudoZmvU35zRs9yC
TrWEVtGpPlCt6Q0D+GkW4snnkkUl/vjSSxofjTKDVxrcn1dPZVqp8U3CJWvvmvlqmVQ1dR2lOv+h
FI2GPuyxwin1UHX4muJK+jr0NfdgKvAu7AYIKqvYUW1hJtM7RimuRMvuilB00UxcsTjMByEKECI3
zl3YG/jLmIrAKPKNc3CYu6nUT7jg1mXHrIeZuWcbQpzudYvB71FP0Qi4U7shzCEy7MP/y96bINYE
WMQOgkiPYj2LU3uuKhoS4JjyZ69fwCQHF6uhXbbsfFJ5uzbHOWvsnMeBv81Xm9xdZKKDn3xVToXH
7MsDebjvsb5PIElSMWGMQsUCDfUoYjHq2nfzsEK4UhCw2KhEExVDzrFoE86Hy0cfTpJkRD0RY9dx
BDNx8xkhL5g+9dJ2fICF8qjMHjYzgPJRqhsWHl+1AaAhDk7SmzBxv4I9W11hj+QOVMyV5YZj439V
TPvZc7Do34k5klNyAybvs7ja/pYa2nxEZeT7tIA2meeEm74+fumegP37D40PPnarPV68Smmr0zBe
f/USVGLz+vD5lcnG2ND029uf48BG0lOinewM64mN+QbBfpS9hSLc6/ZCmU27z2uzbFQ/3pw1a+D5
mGCEEV1wA/vYagpB9EAGoeg9N17tDhlZhaEo4eCvM+T1TXFKCjlXQWL1qcfNwDldQ1vpKfqUCaAe
TJqmPoZ2XkARKCUfVj/cYSnPmEnofQtegALmnvhPO+VJZP+T3qSr8v8+CsVLGSUcYa1RJTCWZpV4
eRno0yPtNtx4fvTuRXieM5UBvpo/R/N9D6mdh7tI4oR01aLfmXMDTMOtI9XFbJ6dvTsp/XwP0kE3
r0PiujZrJVxO498mWfLuUpIdu2vdVTR/KBoRXy9LaoSSWIFH/ZC8BcDAv0x+ja4QJpZ/HDtlJLHn
s5diCog8n/Oy76RIz1cEOsCwsbt7CzwZDOvxeEv+YdfPJaTzEUY/8L3C/ZyhbbAwHuMUOyxFfbvd
aY+msyhBUYtEgxtvTvsqySkao8ZtC0bZqbzRswNTgEiRXC7gagmViWuVgzners50ssbLir9HOqd3
vIfXXh8nC/ublxhi5o9bZwxulay9R6IgmkLh6PLjzk4DiTqYqKMDFOJet8a69EBTUhjw/1ehuT63
AA6S3Ru+QdD9mNv70oFPWoJMJFOSzOSSPxYsQ/0zUUjh510m6HNCy2TTVRyP3pb9n0uh72NkTNHq
1Ba8XH2gkJrUjRz43QuOgOYVWcX9lxshB5g0ecysw82X6TQKaet9FxXatr3V/uQQMD1u7fSqdB1+
V/t27G3STz4KqSdu2ghxPaGUltrhtCSXaceGYAEPnFzCKl2SJjz1f8yo58uk5bRBH1JSzvqRRgY1
B+53aZlRQP6TkCGLkYMvCBj1QGtN42R9zmPH4rwzyjEDG1d8QJ30mNcda3RpNjbk5DKS+OiCYm+x
jk56kiQW8zOYFjDWcGqtmcI7dxrxZdhb99OhdRcBtfGMyqnZXIRycT5vIbsMkbeDI0/tTu2M4OOv
syFppe4rNdhr86Wl8niEtYAE9uB/svrb4zYlWA6fJo1a3fYVxdCE/6utgjr3pNuzXv7Nr8Abfgjn
LTHWs2YDlMgKazz5fakGFGzWcF6pKUcdr/u0Yon3V+fB0fcKnA384BfEDAw251dWCxi9J3NfYLbm
irka6jb2sFaVYJ+2TIJPr3c2Ny+w0n8OWM2ev/sPoW9Hppj436efhnRW5m4j31Y4OVpajE7hQBQm
Yj8g20DIsvsqk3VvGVZe9tUHLJ7hREZkcXBLUOZv1H6Iykvs8SDwDCkln4KQKD6647TA6Oo9Jd5y
/FlZASGI7Gv8DmA0T37iwHaCgi7qEkA/g0nAXQqL3oylsq7Ie/edvEyX6hU3ajSWLXU1P0SruFUL
kQYYlGVVGTpXJ2Pqyb9fPeeff5HjyKJ7vxTVF7VvxHJZM/Ur+wn5FnvbrYxMTP2Imya5MYgD4gn4
kc5nFXpBer11bLZsIsYqufB0Brv2N8eJWXPZ779f7FrBGEVPHZv5iEnQX5eAmIvaBC0tXQPJ6guL
/Cuj+120/5ZQA7RSIN2BY72ExcFRj132MpTr8sbcuKA+y1vQr16PgzwDyh8zNAUqUrO6tX6hurNc
bpQ9anlshgJjMptSiGcnRu/jx8Pf0ct7nsoBjRn47wypnTD91uSqoqVtP53ly6XfZa9f4f0huBQV
QNeX6WZ7HbMq5I5ccqFTR/iNQARkOJUnvCANEQIQxSKlPzUtIwR5KyStbm9Ryp/Qz/LQ96/ebWlI
Dj6zY6POlidFq5nEU/zOWPLADeAkZosphli+B2A0Mz1sArjcAvOe99P6nQwvw5jxFVRbPvRkH9lE
QERjXttVDV670CZIUdNM60n9dD0dI4c24SnebPFVvGoG9/yK6fiKA6i6uZObW5d5EBaz6QVyU6zX
1+ifTMY3ZzNxCSRhYiGeFE7r5wzA+1Yi5yzUztKYspqu7EwC6hA0HT+v0yiAd7IqigJ1MHPQ4XXR
4frZ8m1gvRI/mndw2+i/WPNS+iyy+UTqUZ0j+OJzIsiIyFBVIRppoNtWGEQ6ihy4AxRNsg32M4yr
CMAw67WxGV9O2fsfbB0NFjrFKAYBChfeshN3yBuHr3EoJ9ohXLq9Tv6DNlgxY+6yJPsaZgWqcO48
fgbPi+1RoAog9HnEGYRp7DqbKNZ3I2PHdqGzR+fX7zndBFD6LiYNqbVomY0xNcdnSJtsRVBcrpks
rMYhpYa1BLUOHgivxkRMH3Jni/3LhbxzX18OC3SC7lDkrp00Rzyk/2bMFR6WHPczp6s+vfFmLvPj
ErGOn2EGQA7xqP0wS3bKYNiQBd9cL7xyjC1HGmsZBfOHxijKA0WrfTJT4IDYHmFZkxgcdyvrkukR
p3X3MgEYFuGlj848fZXHLg7sxT2uu+JKbt4lwni/byj2DuNGSSBGnKBMAZV4TGt0hytCNmpHaHlL
VFpePX3R5l7iYELnxGHIJPUAeiWAhr4xYl3YGnfqV2P4ChIjrEp3L7XE46qTziagjfKFErIl4t0T
0ihy7WDWjEkoEiK+twwa10CNdJt4YBmcHDkmUh7Pxs+m04E7Lxp9KB70T1mxz3xfxQki8v/ZGu6d
Uhky7MMPThHdTBxLna1699xJSbtGAMFz+BKq55PIGzg1XNtHk1H+bLjQQ1tLeU126yzOkAc6Tmmm
jPRVFIhisLU0DcTXkmb5Dk3JqF5pR17UUccr8X9OSHpfBfHamKEJofqwDDUqeO3LQ6iLsi4ek7YV
vPmAFMIr3sCnDGS/RV/w8TWhF/WpxWMvqlHHSER49KmRB+9c7yHcYmKjWiuNmV7kyoCa+zDqjbC9
CbCiMSP73eIz1+UQhxWCdfKL2Akz8gKeH45qAbB3rdFfZjieRtCvzF0oREeTSg3INabRIfiDP73j
4c1DMYY4pj4XAa5/IdPKRoCllOheCESgAGoxuyfXmcrBLndH0lZme9NH6z/G0knrmjnv0OkWVE4S
p2CwG12mUDljjHfKyfi1/RX8Bf3xq1G+RfUM38PMstkDWxF6B+DVUY3V4Cu9CirHO2heSnLaeoRc
XwVZeOeFfsr4QqEnwZDvhNvIh+Fn8V2E2t0+EG8inC3BnjjxW0x9gUDahjP6vwHGnUr9I7YuV0tq
Ac3QwL0bETCnVbSzEP8S1uV51flHJlUPZKGedckcZznzwt5QNN7nPpqKhTxIm7zjpRBptl5ItGlL
tzuRy015mFYOxBBAHSDVAauMO3fAHtWKrYGeyeaIbtgOPO/CPhFlUSvDZefYc4SvcTlvMEFeoe50
18UzrgAkxBHjqW4J6f9kbx1kgLnmWUSp9HX5kl5nfihJZyMxOn8SKDiAmZubXnMP3XMplCbtlHwP
pNTIoYo9q5aWrosZnOKv0BQjjg+QO8MuO3hGzp4AvyIpj3rL+UMKhQhIZgCc/WBwO8pNfTVZOhkw
vtA89HB00hJJ6k0FkUtnBRLi5vXA4CdYV8L7NrOkaI8t32Asfp4oihZhn3V7PO3OW+/lXUWy3Psp
AkH1snrGy5+yIHFcu7fSWTCv8XiLMoZOnQTkxwOQAEJfon30XimlSX/YQB8g/+zY+VgV0u0w9OBJ
m0HdwNhytknfcTd1bh+HB2Ox1TT6XW9xG/NYhWWkdBLPo1nUgouO0GVwn+HjmZ8CNQqsl7G7Wt3S
SnnVm8QsYg8lPmXiwx9G+4E0tlCSxlmeo5oC0YPxaFXL5lUYyisiONTdvtuPb7ew07QkD06Mb9ol
DKh062pmrwijhCHh2Ezm6Gfv/CVHtJwN411qo87fkBgV9y0q9yTKHdlIP7YpiXc+pREh9zAOR9GQ
GQTn2MI4XNQ/5FqzqvjWBF7EMq8xrV4IQYMGoK7wweWRHheBLD7RnmMRO8+23aXi2mfClnJZNdhG
ScSPqdwxkuipB1vfz5YdlPLGkeyK3yphaCWpBVH4vjVBy8rFmelOXc+Kx8evVFP+MXlYSo8iY5BG
V0Gv170eH/y3FHIFnsYxeNYsY21AkuH+SZ60RvnnPa8D1Fta5++JJEHEY34bW2udwZTCpjZ9hbQz
glRS9YfAUPH60wc4EKH+IrXXx67R3BncuCb+GYQYjU/CI5wvMp05uWwowrxQU0PnMlD1CHAfR4gm
WvGAil7Z2PT8FVjTdAxebhEQmdudv4WvuYJ5fsUaRAR3Vdql945OndRFxvjmS+mwu/96zyDuZv9I
Y5xZh09p2FAX5gArebOh80Lg676/4Js3NpnzoYBkGTUtHzD+8jlapS0o7vQEmrXgX+hBBwRoZmhp
cvqxmeUdyYQ7EUPOpSum5GFtHelbpeMtL9+VNfgN9ZLhz7HK9X69Jn66y1BuA0va9eOTEg6g4p4T
wH+G8lYg+nIV6PIK/osj1vtOh5Lo6tFppLDh7/j2tUUqLa2oqdLnOKO42VNa7DTr8ZCM967CHuMK
cXmTidE5+ibyiXK4BYjntMaIB6H6ryNkQljVQ1f6G5vThHFdLgL1stRJXIpf9xY9GQv6Ovku+6py
kYUp51yzFAiUxJz53NtMa7CZqT5py+40CoRU29b6syApwFLJAHPPPQroSsydZzXhArPExEa7HUW+
l4rcX800zuHMjCiwnGREnQcjGDEsQbazbVO7Stm3hlMZLKRaJXUCEw56ZnOq8QJpf4tEKV/PhevE
nYWZdiShUjb+qLfuj4O7JtvCq7XNpmux5k8rLRT6T7MlhgigfKq7t5NosXCbo4dRih9t7Fya7j5m
lY/dinFIUJjPFRszNnwciIuc712xJ6hs2W38IKvQVkhgjurUzGKMkT+4ufEXDwkrI2Da5ArD4yji
jSRuUIhLO7WPBpZ5W9WSTs4ADxM1TKHF81iC/VCg4TMhGgX52GhaKSRhLQuPgjuyfxmMUhyHTsMd
30PPnc0BWh/uEssKud2gTA5wH0Uyt4pGYdzUn7gHLpOknv9i2/6OIqMRtCm0NaINSTzUiCm3gVKG
aTv5zJIHNK7QUfYiXgG6P/oEymwi8962Q/y5CYyxfF7ez5ZhX4vN5DI/+o+9G2OPn2Iegp4/+Ha5
zwKClx/n3nulDokScR9hhe3wk0Bhueiytv8ATk5rFs85rZ7Jc4TVOHnoJImSfZBhjBXdSKbm2Gms
IKt4QnAF+42DMjaAZ03WWJkjjY783OpCXJGVpOC+xNqdJ1G1of7lrP/nwvsrNz9+OR1Y03+6YyB/
0HEOfMDJ/QVT4uvw3UfZKmAIJVJwDeDPAxPz99DSlfiXuavRgXm+SsvkMIJPLyJnHAj1Tdv1yLVL
TdvHDzv6ayiqtOUaHiMOaJzJxxZJbweDSug2cHR6LvTq59uV2cTchforkfTuAiKyV1fJ88i8l0XH
+B22UIfXGo1BBHP42sZ8TNiU4OW1qHOKkuyGN2oedjoAw28gglJ8s2P4CRXIAQ5h7YzUm6BJPllE
qme7PjuBR4C7N2K2D6bVbsf/yDfI84XHMfoLbPpP/0PbMpZ5RWIfr1GAlW3DqVtDGwzsySXCAEwx
cSOdPDv16r0RE7NZxji3UBLzvBSk3jKuhW7nRsv3jNXU9SHtz1q/8DRlxTbH0QHL14n1LGEZ8xN1
cBo9SqZhmgCQ8CGjOuRK0qQCBe3S0TgzA8QbrAZZJal8NVnPpGrmj8pmbkIwUID5KYbg2IMXzSri
mx6Yy1Jcof6NpF5Eee/XVVZvB/6ofWW879SdmMI7nC74rvHPmkZeR6S1MjZR3r6Fh9miEIDgq/xB
G0HfGDJ5t8XKynnT1zsArsQzadCU3W+5VOrpIpeWIAVVqk8owU3I8ftQfi/wVQW/QXYtq4VGiVpn
2E2ianjYoe/SDEUwtKlpwHNs6r8AxuLXcJNL0w7DsYN/3qse+XQHAU0VDZw5HXz1mwsVj73KPhyL
LxD+jgPDv3UYpXiBTI9rrH3glvTO+oxILlZ+JwXujfK9SMk9A6LqOVCTxMeOzOm6y3n0nv0dT6X9
odcwqAVuIKY+imHVtiNc/KeW1TpdyAXtXXzEESNWrORPj2iuU/4EcN87C3BOpSpRK83cKKqUWlK3
lMMClpHmLHktvyKa48h2L3y6JGFCb4qe0AnOA4Z+rNveJg3CSGZQFpYteyj6GPeSDCJQGHJskRU6
8TMCr1549T4yBKKpfa1NPtdv0ZDO/eaOemJWBfXrOG/0jy0ZdO107jVKkPFW1hrMARWjxcqosLfd
JlrEzSpiLyMGIGzZY4DqC3WSP2JNY5LT40D+hRQq8XCiuX94FTj9B5QCoKDKQVC7NKfE41d2SF5V
R7fjW4pFp+PrM34ToC9L8cKnaEIGVfe7pthqAXDNbq4gTuuLD1k9SdFeY3hB48uyWwe1u6nbEF2R
4EtFhMj6mEcGJz9i6ReJDm0gcrSyqfzg66orfH6qKRXlvqxYA/DhEi8aElD+C6ik0K2JW20LL/Ff
Fjaj1ek+yWgVv+8rrVMCam4ECDNlLkNe73PUo1i7o5tXX9RGQ5Xl2G+cZTacaiuNdG3p8fUQAOCJ
VCTgxj5hkaFj4x3EC3LnKoMrdE/keOco8JHdn8ynKnsuhEV8kmmiks3xqF8fljY/HIkVroplH8YK
OZ1hvY5N14qEDCjZIqWFXa5IG1wxofSscqgoY/Sn9JlhvHHCuI7g/Namko4GgN9B1ZC352X8LmfS
PN2+3l5kLDgyeYW3GGDHPMJ5ALzSH3YHY/WYzVIyYCtizco1QXvPV1PNbs1WSoV+CZxFXkNHpSJL
AZsgzj7LyeeqO+VkqxBYXm8SmSa0optVZi4hB50jKg/ReBHGs++x8skfutRpWOrBCKWhqzibTmmd
Z5VRlyqOMDmB+YbXo3ZjRBhiQ2t6lxZ3quwi4rPtsSiboD9Z7J/RCODoSyvMWaGrXt4oAsoXHFCI
necTy7Whfl2NQ/2tM/+PCI8Ljor6BpJD6PU2vjuVptMNHahz0jOvjp+mypUbqFAifVhzNUnnEBhH
RlwaYFRQmcAfxf+YBUQCCqaHr08odAQMYwH61cF8SUI5UDCFhWNRakbQiT9Yg6oYVgAYIhQM22FN
3RxMehJ/XlcypbhhSBI60iKTlUNmrNQHuMuvmxisoUh/9LNJke5KCgaiQuirguI3XVt4PALBUE6g
NTt7kKcYxPaPYk6cJSniU31YIjgqWrkxi4LOXGyF8NpyXroPXlZfx0XAj4BuHTdEbiBKptCl4j0D
8PVwSsMmGcoGhebziKO4WIAUuzoGeVVeVYCvkAZGGJCbz5Rqa8FY1nDrMbwStNzs8PWTv7i9E480
+kod8pOY3beUGvUnuabW0bJKu+a6h5WOJ4Sp1BOZqnNYZRiCtT5GH6KAsTSjVjXBWx3UKwYunJ62
xHWPq8OiQ8cHWYhxVpPB3Ckq55CbhQjq/yMbjyRF2UeBk3t24x1CiwdL6PrYLlozlmEMZfRKhPgF
U8Mbs/5yh0TU3g6NgnhLJ66SocdcyPZsXKsioMuYhS1DnErHvARuHO8GQbZVVdcya49HBi4LbLQe
gFxydAVQ6EugOx1t9erIEwXN5IpFIwPyN9Yq0LiaekdyxsOIme2hcuJUK9dmupp5BZuk0gsaMogM
mfpSU1rqEOl/k8h4g6W1SRAAgsJoUcxCUhOqcsEEpJffGROkK1zJT3sbEeuyuEEuYxambTsU0/2E
aNe7/+K/nz1dcS7Y4d67PgmtpjqBHEiV1F4s+4wTE3110RAoR23eP7d2FbIuozF4Xm7FnEwLFhhT
0wBFvxQiGRWCxADsJbxlskuCq/3qteswheioedpru7Ws0JNj/g/nC/bFwp7LL/9fniqLgWJbECcG
2FRQ7jlCreCAf4fuv6yaNLDXqe85jBOvQ0pih2U3HENRfDX60FM4tyMsEX0W9iXllC0OxIzYSU77
tIu51xDRMFfUW3eULOyz5pRk8bxFinLfgBuYax05GIXn7045BhsfE/z2aJPi6SpsQ8JlrNt7ZScr
eiM9h+vSbyjrgdVH1jS0UB4kcWhqRekED0DGnRiBka7xXhbAQDKSnEbaKnFxUiHYH7e1ObZdFj0S
/CdApqcZYnC+DwANk5AVk4jJ8nJjAg7sAxfixOQKuAGnHiFmPEtR2s6kvw6OU1+J7Fd/yZlNzLJP
Q3t0dw5c3vk3Ny32PP0A+FVKvSJbDIj6sYQMNphGmAUxzsVQ+H1ueXyhDkrzLJW9Kg+sBtb7ksMt
oCP0yWSX7BMQRHRJvUZKfQBxLoNVq/+8xJwMuciU+i2Dg75XH895jdJigsF+YPdzRa/hRpWQ0DTp
qPSxIwcPBUQWEJckFieCZGdVlJtl4DoNwGo8AcgS69kaLjriygYNyyIDg++XdbrsfK7MB4phTf6x
QrwUJwqRlo+VXxZzobuGG227mPyXhC0hjwicfgGFiTZPSOma9vjb/+VrGdDLD1uWTIkfiR1PW2G1
704eDMAtubEH5XGW+L2LmpAB9J7ACvcJ0a6rcapD082VdgYwUvOnaXCQT2xk4dz0QYeVelucQex4
mOjPrfyhVAk1D3THq6Vz7V10vGzDWl/tuwcE2AcwgIbp/c/5qUaqbvURqo0lNynr06lMQzU2wPde
YlmMBnBzrQe+g8b9bc0XIhyvkYb4LTGmZkuazmN9nKLJgLFSomU4RO5kuat4CGzvZLPIBh1yqVFL
FoIJibHzwEBCa2BpkW5U3Dv5qy6paIeGY0LuaOt/+bECynauQesfr82cAACSBpy0nvL4Ys+yFpkr
OfziWOF2R8o9fv3A0lAVX7ZxZZ+tvfw3iAgL0GVx3JfOaewZ0V879H0cHvO/W+y41rE0exvn7OFn
SCBce73PoKxoD/+h08Tea5WU4Npq8yk4r4O3E1NS+kalV+WqMl5PgpHTKKG2EJmRr1pnAZw8/7f4
ck5mYUZZPJM8ltVbxRrg7x3evHSoji1ycY2uUIMTIWx6CsSMwRfE42mt4XWUppwFK1BwsXY5U7Hv
gUx1uSAThUknZR39jjiWa5BjUz/8y/2d64unoKejsH/bSEDJcwcWZEBbMg+WHL5i/OJWqSK8FXoq
8wvazt4SSn00S/DOK4KRR/SMD0d+y4qVBA3lzKsnrOuQDzhbJxB3vN0eR11Z0wOIXXhZnqVLAT3z
TtOZrTFUHN0DvynZ4ZHpBo2VY6//y2VXpNj8HGH/yPt7Nyvx567SMw0ekK7sv1p1OQTBBFNq0Abo
iJuwKil+BKKolfixZ32rcVV6YfWzFRZ1xReGHn/zGu+gKPTwEiRogi4UIgwspTfBCuv6k5tUhOdM
qPS5QXnlcZ3b3fW1v7ljoazcJ3Ysid+vqNeOxY79CU57hyEOssRrzo+LHfMtCdC82m/1xVtNzDol
fNunMJY7suDzeBojXfSDCtVGnMmRKOtRqdzfn8c/jTmvayKK6vJ8gMFZ4K0VHEz7L6lHIsqlSMAo
JCYXBahQtAkfNA79cVGaPvxBsB31uPWOpoFM4uVcmHNEbKMiDpuFEhaman39HPfti1vPvjTod3WK
0ZplZ+TDoF7VpFyZIrlwt3YBfPs0t+7czDMDWT0lVDqg3AW14HInN/NIyqgFExfWBgCcyI6/ZGoF
ksEWaffeIpzS4O/EVkTNhL8JvjX9fFUSd1NAbJKPKUFzhgGEn0J4HjymOVNeQThW8qNwKtg9gbRo
875P1lJ4mvQpxPHCOh0J27FJBtAdKcG058Jtu6xxlhJk+fg9tceoVhlSbj56UHkUVIZ61q4xSYmR
I4nS/s21ZQO/Y4pP9e0cestRNslGWPiRXp0NGGjJ96i9pgnFNW0CFcopc+cy13HHmBJpzh0G5Fy/
+8D7FWJEH/VFDs8OgXyloB6r3Dx2SELb9yoYSum11PjUsRZGNPPCj59+Clj4WsZo7ZJBCcLpJ7Ct
KFu7QSRSd58lky9FzUZhNwKjQHyYr5pUWbsVdSPwTWdJGVu1/D+n2aZb/ncno37+NS6d7B7DnMuJ
z+vwF+HRe4SLqUrgJSdL/CP71cZ3HjRQC1OLjl76xnfdWgopW8ORZmJalx0pU243xMEsDleFbOJ1
hK9V9QnSGP6c+aflbWe/rdGlw0MJfCbjAN18GDxu/tHFMs3lI+3p4MnCXEDzS13GQVT+PWns+lUz
SArVBtXyFgvb9joExFIICblKC6R3HyTPzySaeqHWcjQQVtxT99lwPMh3r4o5jok4nsL2lSs2WL68
fAhJyUTuZ2Cs3+5WT3rdwQTuhv1oY+e8lkrbV50/fGk2Lv4sfex/trDbaYZpsqUmPcyZQUyUDfIF
zG06wGBLE98HD+PeoD6CTO67xwvtcxkvO07GwyNJleuShbONDQAUXOxtm0rGqib0qQnQCww1OoJR
9dQ6yNcVL8xac4xSdLGOE+MjcmoVOcGnPuc2y3iQNEjP751HcuczdfiZXVbvtLixFd/AlvY3n2ZT
HGvkalu5Kq3g1qJ+oAV9DPRE98CvPFIzd3u7RrdDwNqJgT82rPwxOvbSwsXyAuC0Hy+kqkut6wvH
KiZtKh07XuAVrdBV4VsyYFBKL2ADC+92F0zHaDrAKljnX4eH4hRWAj7SlQD3GQNuvXrBQClKetaV
EinTJNr2uZX09pUGFlX6LTI4RsuJS1oV1vvjOaciLTtzFDuww7OUQTfTN0Kzf056uOekL7F70fm2
wzrKBL7LepuBjgUzeYFTT7E8bZxjhljs1CFhvZTA8xV1ae9mfi1wuMd1nw1bSWZtG1YikBxjzN7V
rDFPt+aexvCT1+0EnP6WSx3Hi1e/jxDnQiterODwd+PNiA5fU8rqdx8Yt7vj6kvSdqrq5PkrYTZm
oL8vneE+wy8BioVAmyHZqJQXtDj+ZOdXI9ZUqCOcNuyo9qio0Xj4yOvmwfMGNEtjixlRJKkL0AT5
ePE7nR3hnHqA8gtTaYjByabedW6M06QAt8KkaDx2zy2XeOv03wtrjNbXNoBe7SZcF/ESSJuCiQx/
aThX3DmZbxkdJsbtnYhPkV2vIPmRuAgZLkiBiW6XufB/lslO202xffF2LAPjJviVVixaptW84/NF
5qoE+5DGuqPBAxlFCMeevIsT3eiLUvmeRLkIqAOruQjPQ2veV1feeMZ+8sAsgPsMpr5FEJO2VwhA
si3yHzm0FrXTCW0cVC/CUomOgvIzVJvy48ZRntkpSVBLZ+j0dhA1DhfjnDxpFHeeLNb3GKdZYwUn
Obq3HX2YVqz9C6lKbJUWxijjggYwKH9ctvX24+dtVoP2GA0YWg0oWhMoP39n+ea8jEJVUSvemoYq
Yn/ynffNbRzWOYaaF4EnjyrnpqcLB905SNPrBG1FLtN5wfHXAnCuwEKov4++YhEPrZwBhMU6zpEq
+I1Ds2lco48gyyXmVXhzyGcCfoJPcZajXM7ujljUvjFMJSpXZloQ+o1SG+n7hH3LsqF2zAaxbreT
eT3vc41Q/dzED2Jh0N1YP0/a09t3zWeCtwACvtsz5oViQCBIxPaPDXkkGuCcCIRu0+TWQym+LQqB
BLVS14If5fmXE3aSJLP8kQUlD5cgLXMLHIMUlGc84JyKK4nlougoz1hXQjVJ41se+CNHypPzF2Zs
tsaU0KGoWbIcYTbxRurM1hhzdcxzNrHac9YG469KFu/oaOIH0SP9LfhZf2DSxBPjuq/XlbYjaw82
DUoaQw3mcfAxkisIbD09TawTYQ4R6/vN9FtN7fdQWNuYbfwsyMprjAw/a6hJ/Z4yGOKQulIlouiN
+uW1p9hvbBmtl3Uc5Y1+zBmymW98VKF6zf+OcAvJYVhEikO6CW9LXJdRbiYj6oqUaJKg28sX0M2B
nuD5AH6AQEh5NbDUT7GZ4xT/p/Hlkl/SDL/Y6ubvMV0j89UfwP4US9AHjlOJv1WR6A39ofimvPKr
EyhgmpQTN1PZNoGF0eggw6x1OJE6ixOCjstJshPQxGG86Onkw0RCdNSjSk6YIDxai1JclgORXIBK
UWpGQ/efbXpIiWT6nveaE3vHit25xdI/YWQPYJ5/StqdnbnrSHxWW34v31glDrRfJuUZYRtSHYTv
YaHrJ2u2Sy2275M7gfGPzGPjCcSn9neivylOLY9f6Z4RyiMb/FLjaG7hGaDBwdFp7cl17tjKiFqy
6mE2jnr4N7XFL/J2QMExGrmQtR6X9dhlT2f2i4lyrpoRDN7zkouaDhL/DgHX2AwweZHTbtZ0wjMg
zlF0vJFpnN6jFn1g+cv4Z5+a7Y9COSOs+Zwz1qGOx09q8OzDASap5lYUbiz6uFz4IvdJrlT3InDD
PZTksw8p0xkBnsNLoIwSmjnAFe8FUOkXzSZ44XR3rVXo084vruN46Jl2SquBibadICNWQLv5Jjoy
PkO7hFbKcLplTUaGr0S/jlroKC9wW3xUrCRn9AFN6jmRHg6LWsDzBYhAVLSQG+scqX31AHzQD2V7
54MveES3p3wYo+BNQi0WWhAfKyxOnJMwTN+LRUIvvBxxhmh1xNyMsKHN12QHcdnNPXNOG6thfw2g
Txse+EXg4GI/uwebKqhJBVPjoqKwgdtVOt3ckv3r6+w1PrF3QLVDM5m9/xXWA+prQv+cXLXqM9Ma
e0L8j60plddzAriHc5EXqBeDPFLH334EY72+wGpgjHtf2MJnFpUodwACRfWIJLEnR2Fwlex2wzfL
2xElntH+DGvpcOVwIPSYcXvY4hEXdLWaOTl03UzvPdNZAIosJtwiiIUgPWegi/ho81FCcDezAFtD
PeWsdE58Z8xKYhkQQc45pDqu7CzWYCalolkhzGSLARoB4hY/yl21PHjKkSVqOvFyBTkSaWttFs3m
Vh5TAaBaKZ/X7MdFcF51TydkLlhR2ZH2WxMOpSTLSP0d84mnN/0/YkNjYISwxqsaUi93SKKjZW38
nnZlBOFRNFAVfw/u/HqG2s7T7/aDNwe5bR+SBrNiJPFN+kZYZCGCMiqBvABvEEmwL/RKOOEPDJAD
ID7fdhToJExSBGqSM5Cm+I72qIafCzgegPb8Ny4FcdHeqiXq6uGtXcjSg3z21jl/eSQHRovrzoMW
QWqLMHL268sZz4ybr4czUTEjHSLMl/L3m1YB9/QWtcYCszGZmGw6FU+myQ7wfsxyZpbzTQ7DX5zB
/s/GDhdlymmSevGB2RPxYpwSMT6YSCJdpg+KK8SdOrkauLMcjWooyJ+ezgdeTMGcHLRN2t6vMdY4
Fc3tr7OxnDTu6R4CqjQQS/KGGi9R5tVO59BgiTJr0oq2FYy/75xqP6sPwykgcK2xyn/JZ7ietBJm
ASnlq0WZt3xOjFz7TODmwDvKW4MoCr2QUUUhGg1tHH6RU2vP0P6I79dSkF4LmZweMj26JvT7dXD3
j2PuczN/ftxACGjFejbqvMNeaD7AFlsQHXQmqVJqh5SWVRXIQQZzpR8zb9t+MlzBeWPAC8DYZGGV
Lk5w5W1ViJgCsNNQ3Yv/a5buyNOpFTGerp0tkBH8J8+v5nmirRe8/i26Rp6exp3gXGV5TygxAD5U
jA4DFIY2Qv6Jekb8iErd/bBMuvMGtcuCJ7sz9sarVkia6P7NQoTsBciG6L23D6Uk6gNeAeOKO2GS
Hfq9I1EgM512wBkNYDXIWvHswR9LBFICBnaNz14/2l2M8UAiQao5/WL5as2PmqP7tpApliGFq54l
P6+dOU2zGRNgghlt3tbqw/+rf40FCZ6oA4vTp10a+ivvX3zyLmScdG2Q+1RoZ5xfK5pMuaucW1np
5Z7bSTCLUM75g/pkmAUdrv/tQOcCqfx1y7WBU4iqhg4hESSzmwt0euf879n0F2JviBdR5xEerb+X
N0xKBb0JSyMI6dVBFYKXOoHK1n2mTsCmMKDgYls4zJtnOE7LFZyQHjMQTmohL3e4H+eQSDw5/R0e
PSqMngvA0Mt3UyM3mcNowyjngdZKX1ekKdg/gac/w3syb/U24Dz8SLjjCnvUHcY6OUupI3NG2VfU
jVNF7KPPcguAAUVcHYEOXKolEVmHfwrY0j9pWDS5ldgdSFVP1jtJbbI6/6m2Im/FDL6Y2i4f0kD1
CfVMqdOvoSgrnzHANpedtgCK6tBWgfqSQFx9oeOnhsyhVAvwm6Ave3/wxO8xMkYx0uXpzYFPXvvK
jt38Rg+eGSqy0lfbR9SHODJFc8m3OhJ+8YOgSZLJFDRB6yir2+T15q+rnI8FsG6s2mQrYUObtlYE
yHE/1xjCdcZLIP0+qN0HAGLeWMErauR35S9nADrKv73BVHOvUgtdUPEukER0y1gCtIp9gJk3+F5q
UJrcC/3UTDby+2Z28XiWiLhgMUNReCGMA+Lz4LGSNuKhCia3c08HvzJLpAVfa/A8rY/BXCvFZsvZ
AUvR7uKum3MCAq2iQYo8WZ+88vj5R4iFBBGLQTSK+6FAeT06687RAV4S2z/BddNbWxPnueHdnSHv
qSI87/k4vmW/8fGnN4i4tptqYrFsGrN3vkqOZynvckoXn/pTCwtnmlJgk0I/4DIiGPg5U6JuvAmL
THBgIos9rFn+P3z+s4KFykF3QGOSmJKwhhq7Dd10Yixp25G0SI+nsJtTyZMVos89UcPUzSqKf7Pr
u7G9S+BjflOiCzvdU9YY5ia2/llDe94Su3sdVQyuNZqabiUKyWyu1ngMd6Npels+9ZnlyCqhCKzT
T+3ohKy8UV9pJBVqkG/YDkRNiTFrhU01TGL72yxF0i7JvcvSaO18N92TE1+xOvooc8XetjVWEFhu
jFXe+SLQ68byFF2R0dXacn1n7rQJx39tVL5nE+sppyZx6rpT+lcli4HFoEphVqs/1xco1/Mfyc8U
3mpKpFuKoN1x1yp7mW000m0Ty1SBCDajeA6riOtEGROEJVIHcWfB6SbkABoS9RdOUt/u6UxtmaPb
Fo6xPItfIQcxEwdmjk1KVAvy7ldQpqKl6UV18TP2E7vc4Xvu3DHznwKcc1IcbK9DdqF9IQY+u90n
4FXbf27lZneIYhelMffQzpq2RzgIlXJPl1NDCvpes+RWHC50Gwk6fCTQOLIZcMEypYXDxLstknaM
dne8DCFrd0pP3es3V+CiEPRNniLV8k1jZNMdNUZG0pcLbctyspeTH5nrp1Hub8Id3UwiPet9lLog
EVsNF6cbW2zW4QUVL2OJTaJqXsnaxTgQzA8m8EgdQ82yUdBMOx3qVk2ohMErgRNQJKGQo7lkXber
pp8fJN/IDkYENC5VIVSlwbcGCo3ygeC1B24kQHsA3czBbYkf+Wi7Jc6YCDJtmI51GXEV/PmAxzu4
z5/AcZfx3ij/rsvzK+fbXO9ELyaYvRb32LKOo1STNzsqXfb3ZpDKFhojnicIJQwiesvZBJaTImNZ
I1EEtpH3wLiyUXLkqJNds9moBG5K9jQ56amKcY5rfqFgjco/Na8PYzkxxO+P+mrUIFVFo6IyWhdU
XJnTefWLgir438uUDMtqcglGzKN97Y+hykPaMiR197ws1tJ2lb9hkA3r1ZDzQItE1qO7fZ0KFTmN
s56CobBUwpEzfEjZ1Ce22485B1aIdnAndvziYLMetQ68+J8j/dwJ1JrW5CpV1XLQm6qxev3e5gU5
HQlbIXtW4YUVv0U3TF5JtDpZxR9IGv60TwDij/3tnjBeY+qyKNl4MVKngmPiZXGK88/W01NKbAGl
jHkJUGZJgWF1DxJnHuw3VuTavHztCpk5gHrPNMA6VDU0f/S4t8Gk2fp+eWBOT8FSgpTqWhSa6sIV
mZGVvFKvbT0+VRqZYXObwvG8C3c6gbKMCeW+m8yx25oE8ilVfHc+ucZWBQeqTxX7/G2lLiFcDqNh
g6Kwmd9M+2b6YaXarAObkRn4uOrg73UvieVumYa/Z4dydEDYrtNbE9HG+Hi+tC4oyEtYKYXHkuYp
PfOZCTd68900AFsa2JkWaoyO4x+cf4W8L2+5Xvz1PWfGhX/xiP+W1VvX10lAbYYYXuZ/01VRFh07
QqVFTCew9DO3LZTczVRtdLCIV6h/V5HxGcUryuohtvkpS0bNN3Fl1PcZUXYeowTtLVj15jCbwXzK
Z0R+r6YvAYZZVOD6gQxkc/xpOv+cUx1QB7QtL7Rk/sW22+JX8F8Y8DMAkQSYWOMSdy5c2+he1l9w
pivXNcVWYXPceFRk8VmwXzVd6L9/C46kxAK+lex25sv66MtpGKmEgq6dWvl8m2aCnzeMdBPFKMq5
B8JSibNS0rrNsjz8oW63P/hXqBdwr21RNAxQll06n6J5FSAciHN5GE+jjDQvGVknGXhoKi5DE6NA
mq5ezHTa56rD94psUWUTCffHqkAbvZsaM9aBVSctTKfvWk0EkOjZNIiHC/8y8yozX5bYkswujzA2
Gqt+096LYcRrXiaC1qY9SawbNyq2j0UmvHxzRNolvBQwoP+LCpbXwP9meFf5WKre5M6OEuO6ZfAv
uzVDddlZsNe5o1ChWgNW01sDY6vjGmcZqO5ZwHFBGuHG4I8yzARw/N62GcKY7h3C/KttplolEv7W
U+9K2JY7EkPSYXZoExYVupw2G+E0Pz+VjRiTtfTC/MFewr/U3lsejK8sZvBctvcOeo8/2rUp6sNL
CEwgPYI9ib/yYcIj3ZHrPDbtJz7zpcNBENxl7SQdwVvukj6kc8WUKA5emqkbxi5wfEbKuFjGxs1j
5YH68EzioTu0C46kVjYkZL70rFDXZB22GD3yK31sjE6y6mgfJmdBWxakAuzEmXAHPf/p5CwvRCCS
Tym5VeRGy4h4TJMmszM5vcrg4sNEPClyFDsbUXhWSJXmCThnw1g1zYCO3W8p2SUKwQ2GxiGiWkJY
nma2prBK7t/1UhCAbubMunpKjnhdVdj541jOK45064cDIZmpNSpnjgnN/dUrezohKR88QdXGQqBx
L7uIymEeZU2Md7jONJuA3TNTUq3gaKTqkljeM/lrmFJKpoLdnYKWMbQeqV7hstnapHqbKRdhkoJ5
HFBC76hNFjr/X8t51BfVxQnVTCczvFS/8WZrOycMIbvIOcLHP3ve+mEAUJjfRk1lsQit0slLUaWU
lhxQHshI/EfTTzde9OlZA0Y/79+dFEsqOAOuU3PH170oat7SOMfVbYVDoLSybtSLrfK+GlkPXD4n
SSWgx7FFU15IMPNudZpa07kMSHaIQIqEzVg+5p2GuQh6nA4AgTLGN3HFRsCagM8LPa9Lrpc1UqDy
M2Ox2th/TNLFik8gwTJBUdQ1q+IgPb4L5SmSLZ/te2Jj2Hfq03hfftWqrUE9k0rx1EIp4IB4Jeg9
Xs7ZltN8AEg4Bu8JeZNL+OYQQApoTKV5n6k6aN/nYjXgs4T9QiT43R4wK8Mz+ibdbnjwfneGnmk1
XGj8Lu5yzE0MtC1p6FBt5omj6ut6YXSVHbHzPLjwEJTu3+/rf1cxiKfqMrxIPNauHkF4RcNI5Owx
NoBEhpAYnvylT4ssBtAWr8Q/+OdziDBeVaSI6dya7Bc3FmRPF4gUQih0XJAX3xUyy00tHWXLQcbo
paFTSod8zheD5OVkkqLnAEdpHV5ze1SsiVME2I6ZhHPQVKDCfd355+OMk5NmGv1F+BdrlrDDc3ba
hGMtp+ATmorjXEdAc2u4UWAfTjbGQyW34a9LTgf6gbk2jv/oqCwo4MDhXavmEGiHoQbJ+PTrziRz
u8vXdWhuB3EOu3RwbDU7oX9J/ipN96yoBo6GvaJQ0qgRtY3PLeWDuO3PeBlvPcKkpgAY2AvEZXAT
5uNP7TxejoYd2NxhHjogwV9FS2IvXGcuBelufNsrUYX7hZYuYnf+xlYSLhIPfWmqCqOVbrc5W981
OAHe3hxUz2zuv9toTbgTVP16jiudpqWZFyKhJaQ7M5EppmJcq3fhSRinOeTCx8P8uiMGnOFxoDRD
PxlRToQCziweC9a50aE2pRDJLVm5BR4p8yStEZu4AOu22tfUCLACtegKgFzsLArqjkozGeZorCWy
MILZlqxCQr77yCJgx3DlaNtwf3NfDwzryGVQ5CQhiMIT43RZgHmp0U+eTJsECPgBiHNxRjy/ZKEm
AbGzOzhU1C+Bnp7YIq2hBBDLTEUnVa5nT3RXtMhKJRYYs7dOcV5Jn5ouy3Bez99juc/GOb7u9hBT
OfwkF+SalF4Bd4hOqMOIFOTolOOG4dWXb2JyM1Av96V/lw2oGuDb9ZrIEZ/LyRHI9vnvYWOEFgGT
QmGI1X4r0R/NCM8Adh6DALob0qM/W2rM42M9p4eFSOJGfANgm2/tdW+Oqn2GoJQM6i0vjaF7+jBx
xO9ffDR8U7/MKkPA/aYGj6YLkqnqSyCWBm4Zys3C1/oZx3svVUGCc4dn9hOw4xPfgLHKADlcvi7l
mNXtJa9U/yfd/25ShlUZo3b3KG5s9sv8+Q11uvO2J96+f2oWw+Lab7ClfBC6OJkBR/JWv8hgwaMU
xxn5mOjowuViCcDqtnjUuHqhxopai1QJEzUipKLTAVSipRNFHSr+nKsR6uV3qrPVD1ZK5WIuP7sp
pNhvZ5/UT5NfLfwnuaEZ1QgwNYtN94/xLX+gIydguy16Fp5aCMSqPhvVqpiSLNCIVzxpGaVi8XLA
riFt0htSWFcTRCxY4r+Slyiabt0m01tUBhiFG5EyqcdbM0xrFoaKddo8RxNzAYU23D1zrTUKaJRg
vZojLgXKvp6MzzbtLuUyvUm9bAnCcaPGhNjdAaGn+pT0NxbexrpniPQ1IRgBjtaWQa/pXzqK0lMk
IFjNpHzYy+e6zkUO4/ORBuEnt0Wlpmv/yHvYAQOThsn8GEQB2yPtc3WKrjvSAXT646ZNgK3wno/2
9nZ52c8r6yyeY7/A5oIRVUPkOGa/xeGoP3a/1mNb1xQsYrKNGpgpWlOOeoqkONt7GijdYMhVlYNJ
YEMGuaylmVM4SOGcwdnQmn6p8Ug3Giy838+wGN4YCKZ1spYTI56vqrZd7s0IV6vYHtOkWOnyREHL
9/+v4I6mC0izxOjruyYMISezPhmagM0AS15cgpIWM2O/rbOqRBHQ4B6qc3xSnHrQ8h4LA1vhdE3y
5Q+ykMDng46j6neapfe9XHTMBt80AluX15FVokoUdKcd56kY6fsnHlNoKH+igMIRrE0y37Vp5u97
pyawlFt9BIQTJa3jDHmSECZk2sunITRk9QQJ5irJ3LQ4aiddmOyVGmv9Zv7MxcVAdOvR2VzMt3xc
5st7RwkDqgpfFFIpIOgJLSlRtkgsQ19eGOfrWplZf7+p0rG7xORd7rYypMRA2l4qtVY3CTFtSZ7+
wmNfX42tg68xXaBlegez2IgrhFrhmLyVvFXCLhgAK1L5L2kKrIs4lP2uVKIBuhkfqYU6waWZ9QGb
ItuUP2DAetA+WIHFUMd/l5pkweaLpnO4EMaXW/Q5f9USlxSujYqTdnhQc0S6t8D+wZddfcjMtO7e
/3Wc950nC22oQBI0HVNMnEqn17F7uZ7/9cJ2rZ8izCrzUXMaNREJkYXzu1CFGIlRB/YoLPUNOjGr
gJhEouApqgsTyhuiRYA5lmitEzO/95auWL6m+gh/qJSWNoJ7NHI1ddD9A6sE4ljvduE+G4totBQg
7evN8+SwFYup5kE+W0JYCe5+AfmtdS94iKC/nD3AJAdWRVOwq4QtpJQytxRxbs2/748bESnapTcf
Vz2Rfq9lJEC5v6+o0OZildcAxc4esOnKauXf9rwToyOKwRH7SN0omwT0v9O5QqVEcXjbEpgT+2KD
8vTrmWqiFT2+07566dithMSZMDn0V+RzWOqolPhjl64Aaazf0iVZieFyz3NpARXLoSC0BSvXvmV8
hBMkOBzZFKDKLBjfEz13G/fd8OPVU2aKwy7E1++r36oUZBPA9L+B00sqEuhgw+jazoe14VtmGnij
9Fqvj+VhZO14m8v3OBWXKBnc2IxiipD1P5Ozxblu03uAdBsJoaOuu2p8xQREXxdCkhry2BAFBIal
eZuhDhJbPupYn8cNo0o2s4ZtVV798zBuycGGW703A4UzhdG4tSliKTNjrpQ60STRI28dtdvuRYA3
fd4j4CeXTfnO5loJUWMmrNM3C8yKkSZgrxkBw8a+fB3UfjlvLjGjoNH7HSFvxZvD+fZNpXlDKjux
/R+4Wd+zBHELcOVQ7RU7ZUJKMeXrb4leTVclqEJ8eDL520EDwo+l0GhZRaOcNOgitzTABTy9YRKU
APcWnxWoa0cGp8TJyzsJuagJGE0LGShiAiYD+bruMwEen23dLclllzRU4AuREIwBCd6R6K8QVhcU
0pfDI43uzlUwL6CjxDmCqwkKV+V3+TBRVoPxwKrOFudCtPUE9julkiioj6nyBsW+xC0qqB+Ta8zN
wnedb1UMfjroXceKKxFBdydGXg/Gaob1wU/um2XRZugTk1Y8Kbi5zDFFqurs1K1WRxqLvzaMTjvX
zQOjFHXMnRsdlVuaGbYzTA0T8jUOLvDhc+wbNEeRmor9jFEhNziVrOD1w58JPdsXAeYgFRP/g6AI
wQFxOKEwHdlvmPmb5bo79PKP10zMeilwgAjrRqBcmQi6T0s4jlOaoNiOygHczxISwCsRqECF38Mw
Wprhwa+A7BDP2vDmCmclv+JlHiqPNHfqjF9a30WmIA+oRZGuPn4bBnmM339c+7ZChCRupwQkR1ai
4wCjaKQt7qqLSZ3VMXmRzQkt5LKEjzwJwKTH5zPnr027XzpVyUNNe6P0TSsNJWWM8IX5CivqkVUF
Xsi2uguzj+1eE4cwloqQ953bYb6v2/HKB+jHwi1ZIAICZXnFFQ7Q6fbw/RGjEDLmk/lLsUAM2gx2
eP97KDybnDhsZACugNYhKH85R9tzafL6YC7c0qttboZB/ObRyZ0+H/ChwTvuXftmWrkQiDMpKmBp
51jHl5FTgp3UiiGdPXcOABaEAgnQFvzaywkXZZuos0t3W81LYzVqCWXm6z53k4byn4NwfzVPyyo5
eUexHffYrFTaOwB/BZkJsHBJPfSYhFbJc6cazSAd5arMxYTDcUDv2cZcDnpjN7gqh7doDOqIeACC
oLKEa/99Jbd6dCfoqigvoevrQagDFlk1JdDcpQTAeZ2r/laq5hFdmJejy+C8hvrcw8jgpTuckC4e
PebgwWc4vmjqqDSRwJMl24eXrmkPNqjGUU1xWddizeDyD7wkLS6w6MgpWSjHaJL+YoaLxse3eOjR
b5l5mDgpqH/1c0VKgqkb1Zxyr1ElOM/vl4PDiGpW1xetZfnfOKsd1sTkA3lwR69on44CkrqKYzbN
eEdV0aFg+Cu8LrrdgdAuRPoAhomI4mh+iwY2sZ54T/8Gu9aVBlEfwYd2i15P0JwZUArqwhqrZUXm
ac4Z1vH9mzI62mqyrFAMjfpJz+pnMowL91N5DaKepipXpCjfCB0+UYaoy17iV9qfRFwZw60t6NYV
TfKt5bov4bPk3yn/mXPgzGTgtr/li0aJ9hPAEgVNfDwmZGsYkVKgxsfuorNsay+Xq3hUd9CmLBX4
82hu56YQHgLwUI04sUefpvIMQRgjRN5/OUrKerMEf3Id9P1otAakYNhOlq71Gyk9UIyB2MT1Qw6g
7sSoc3V3i7DSD6TeyUc2CEsggXBntGr+FzCRigIxcwFHaB+cWapqQIlQP8N0JTOs+Qci/SouL0RL
q6l9yx4j1i0txdR8Wt2JXkTQdpVH8LV+q6S0tYm+5oiK+5tALhrqcQ4O/eoOFne9hW9T5M24ytq3
bEf2Ci97O7LvpHTLIR6amWHkgF2jO8S46pyH3xfHfm7/XPLvIhW1UiW0TONGblBn0v8se8K9/nRL
U95zCkKw1Gr/Lk1dRdBiXGc+TZaCbi54pxq56f9T3h9ig7JvzZhOipgD1WkTGqQYZee+1H90V8en
/55RkSGv24O6EWLmM9foXF/bmdPROp+Rl9hA7ssw4/3hyCUkb9LFBrfochxjONpuLXHlweVGbAAP
s2mspEC2Unb3haIt1DxQT14uyP8X5+z0uiXvuZkQQlKgb6hPMiV8+LoCgWpVl+TGrvRNJs6iO8jc
Kq5C5/FOhpVnjs1GdLvE6I/ZVo0+z4LUeMUuGzF1b+5JJi8jA30uRKPfoXhBJjteC4CNv2sCHnQj
VaGyg3xJGokLtXQ1UHCEdd+0xjSLTjbEwaeyNH0Mt4Wx3RJb1Fage+ixt4bSBNWhNYiffOXicWII
spWsnoa7AjJwpd69HnnkI9NBJ7h5I6AxldxS1IuESVyIGSVJhsdH7Zml6yQNpMZs7yYrscJMJOcz
srgmvUjPasehvQvSjg80PEye3CdYmzj+mBVZnGu8RoGefDxERRMkaijuoiL+L+ciwsVvPUQxln1t
IoglvV86vQ0GoBGI2cYDnhk6wJuHT5UkPtOQIzHP6GRPDD1dTrgShYq+85G0OVqHjIYRN0Qt3hrD
JAhatQG6dFGVSAIRg/FC7/9xogU/XezDHqwmhwUzyVCd1d7iKVOMLJEPSezkIGTGphVBp4oNVbvJ
4Em9fOk/0U6lCyYUs8ukR920JHTpYZZd+Egea0fkauajZZ6Tf7hp2UIGdleWdysB5p8kgP+jnboj
Dqi/HbVJiby2VI4dcIYOAPybHTCSEwNFn3QzFfbS022sJHbBmUeml46TOAV4m524o9bXojOS4pL4
PzPn973D9S5hIVtxmZajYPAOMUcGkqLqL/JFWgVqojx2qS/HMRMSz3pi+HPmmwG4HdTFLbnPVljn
azslVxv7ZV2xNCrwcY+SvC80uM8R+r8SD50plId9tRqifUIOCR/Ub3iDgYDZt/yp+mOa0wAOPr+g
rPEURfshuucGwbxr4mJjzFgCvE548WvFijlDt/v0Xm3ZOaUC/XmKKnkA8X7EOkpe6zngbc8uSgzM
F2NcnCIUAsS7uOBtpb36YafIi1kLdeJkcBx0MceUGu2BUSyug7PiHxvfZpWl6D0ZMqxwNEc3nvCj
1TM6ZaE4WNP1BYAxwqzSXdI75wrqZ8E7URfgsUhhWUqkIpoJskLaMn95oBfT2kDW5z1cg4gpMj/x
iK4bWUCli+w1oPuxka5PZb9Ogh20+rRHhutCO4TcCjaT3Wh1hsnBgUH1CbEazfqCvsdCYFUV8aJ6
gE4NLZj6RJqtqeGLLDAC0RyczJG6Th1Kk+4eGH6lQQwRcBYW47iX2Bf0Mz5tyQemUjseGdFsIFUj
WovIuvbKXsLDq2DXL64f1hpKPDNO5HpRdFEUJIIVeYEMJp2b2CRH+Vx5//w5SmEJt0zQxnx+o+Tt
934BPfBdU/ElIaETMRMVK7WjY1pd6Bu6KTGN7NQz5ZJv8Tu6Y8SdmQcq+p4VzWoPU6g7HSfSUj29
D3Gjsnv9xJi+KqWGEu5U/iEhuXZ34jeB9gZ8mF5Em1k5g4GolySduTy8+P9HrUYf2Y8KSHNrq/FO
ANiHjsDL5O6sYLoL8RNXLt4gkCLB/r7rfJXk4f3N9aDL5XVXZBouCXUU1HdE5wUBEJ6mhvx8WmlV
JvM0DDRERrf7X+0YJG2taLvT3CXiGhhN0aBz7/cyrqh/EKaRv0AmnoAKMGkAm5VULaYTZObE/jGX
D3bqnE5/3Iv0G8CZ61HRWBp4cfRLr3R+U1cT+LMggaffAojGrZOyR0vpZpIlY2o5KOhk1NNyzx56
aOfOkCOWLvxd8bZwhNl2hcVytkLJUAVcV0fFtXXh/KbEdqw0gZWiu9wtySR7QJ6Oh4qDPOvHyM9A
UkhjkvmJipxkMy//8gbW71QgU5V/aEdLREwF5Mu95vJvxJ5Qb69jeRWEaaMDwO0+qqJwgx1amrYG
NMdrEkRid3xBhP0PdzZx5px6nNxa3YBsG2wRwBg0P9AsTWuTs3q4xAG2YI5giAB7cOd8lQZbA8Aq
lXvNbTaVOd6zUL6uesmWX0evCaoDEQqXqiRs8qdEziruGpF4GR1X6Qp8MY+vENCx+m/oGIV3yJHv
bjG/d/etdXt425Fq1jE4NRUbT6VUqiQYYSiow9uOg8wiVhr2NkNAqnMRm7gx82tM0cOZGy7Zt7U9
YTooz9eU6VvmjwKKP3hV4IiBYlb8DqYuaM9b6Zt8Cr6+oeRh4rpmnNFP8+FnKrt+4YBCsjapfhM1
o+GPUYNQGMhQSeh13PQhG+8e5kSSMJIyU/te0XeZtiVS4/6oAa2eT3DMDdKG0p7V1vymx33N615J
4N6Z3utLdLCucmA27PUHYoEpOpmXla4UrBZdPVI8/u3JEWY3UmoHcxVMrSoqQb7VTuzvcKOpzK92
t2KKK0APfovzAQjUgDuKpJ86ZiUZU+v/hDC3M+iz91R7C48QcXpAI4oGS9wMQPPhY4G5iuBy5Lzr
qd+B5/zeFtjXXmTq198F+DGXsb/LpuWK+e7Samq47uR6X4b/VnryJz2pj8j3/22iJqdUuMthW4Ek
sucHj4Blgz35A/FUShOB5aMaFGIWI1ad0yY4vRu6XkPnbrA5tVRqSOTTIKqNaflNMJSOpNueD3l7
BvpId9qnQX0hIXnK74xsD70q0Z4QCMhMPx+TIKq3xynmnacMjEvxSpjJDepKU4S6N05QQjoYp1Hc
UEGQ34WONcUIGGdR/HIigdYdKcr5esCsFFvYq4uLvdfM+768KS4vCFJSlMRS1ZiTkwrkxhg552G+
KAcWfCbgzJbYvgTjbcZofhfhCloxVBVpHEWapEO6PireQJ1yGiXDS5gPXpf9kZACpe8BF5SomzYE
tj1wbg84sk0IZB92c4jQRVwBPuTReKuwSIEjijbsxU8IW/2Q7vMyulmIxmbOJarDunh/Fq3T/Yfr
fS/5dbJudP/OUTKwy/LOfFp+CW57aAWziBnDCTnxUgaIvkkKowH723mTdPjzRyGPMKtaIlWRfPKG
75e37ebjble8c6JdJqzKKpCh2+7yohMdmabfzD/vwf+mSX3XjFY4VFglZ8wHM4NWzgDDHjkzkn+r
nI3FiUGaTofYoZTmflLE3+pLlMa6G0sk+Az/zygrt2PtsaNYNlWTR3SqrqwBZOv6JQrvxRkpvFJg
VeqK6miQp8jwbAMdUytzekmxam3obUHUJxjL/sKXlyOi9ZPWZLAjbBY9zXTGh97Qk7xFGtzu9v0b
qjo1TE3BMUBEHL3dqq7nU+0fFlJq7B6LRsdQ2NAc+XepuKyxGINFWQnR9EtYaf46P7c99BR7RN/3
tZgtHEApWcFEPL7m0tH+wl15q0iphjnbOiTAxHaNqxsu8o7mbVK8aC5L6el6H34qDNgHfjClbUiP
FZxlwFLZI4sh6LYwvV7s8CZGSWMvYTazdbwGugXlFdlT0e3yca8iwZrmGsNqO2KtnSd7E2ZpGsIs
a5AcgyJV+i5WzmoPap+SGg3Xz/JmGkxy8/pbZF2Jh99WFay3cixDNcNKDIjh4Afxgxj9nMNpskro
Ra8VdQeTCGNZrKZJpzooPWEI4/QXFc6oJWClrgxdHIJVEVy0pT5Bawan4f58R6pIByQzTJJU9MfM
C7J0By/QfQ0XFVIqq5t/0sU7GT9TFQfRWKZg6QlB527Z6He03cABB80Neey7a0JRiV9+Lu4uZ7No
migXGOtC6MSjwBoLEzB+cWN6S93SjNOsd2N5ufNl1Vl/UFw2754HZV40+mnLUYe+2bNB1Y1jeECL
ake5kr3/ouUZ5FqAt9+MvyhKr2zHf5EUxwTsvX8bZFfb0g/tlhADkIKVj595AaP5d31/goiZ5NvJ
vU+Vm/vNmAU1Qrg1m+rOFD62/PrLr4AReLUHlKbZNdiase3fN6RE157dAQxpe6vte4HLpvkXB262
679nTqMK3/40GF99nQrC2g8KGw0yDUw/qpBOa7uWrec325DyyltUv5TdwaZ7Q9GELL62OlHWZqiD
J1hArUqrnG2btTzuvdVOM92UL6dvCtRx8N0LQn+2WJB+zYs8g2N/psLJsZ4kTU96NtQ8vWjX7WFc
twQzS9gGxGJU+gpgS7mz5cuhcsiuK1uGcSlnSpix2BIUAxM4mSbc5gwBKviA8rTuUjzxbWiITLru
ml3ORQY+v2jAB1rEs90xGkbaXIfsaIeImxEMjjGsBDVrwAQdgNfw9X+R+BJXd5nsyJ7RLd+CCWAn
QRW3HWKIHwlVZP9ofqaAO9k0runi836ndY6C2CbYhjlpY0uX6lSREhe/B/zp8X/P3r398yXii6Wu
Ei8jxfB7F/tpAE16JA2cULWgYHkmJqu5dBBe9awK8B3IQaew0+5U+zpgTbfXGXc+79gXbKS5YXh8
aNa2TbqOGsBwQEXqwTzGMQZnrzhF8Wb3Z3R6w/PXZmNBITvSOtqc9X7yTfukaYrmi4z/G/+b0DlY
n4BtrI9eDC1eiMTDnMSac2NUeiK7InwOX6abrVsdhkcwStg6LvspMuE+3ubZmSalm45XhkRGQSkn
E9l7oVC294YhMmYqiTEy2gYGfc1Fv6L6+uD1SFs9o0RRISlOIRQ/jYy+ErE2fVbhIxcvJCizHGh1
kO4ppxrssWAVcovTkVQ351AeDx1HE/ibdipLEetTlG9CGzM3CibHvLDHOaoxAdCeWTCWmsVMVIMM
ucFeEuC7uYxzuirHZ3pSMJipx7/aVQLRnwkc8i9043VcROMX1ZAI2Ar3gyXm59wWoA+Gh1iMCIxl
Pk1w2rVzk01+y5DxY/+CzAS2UGLjgs6Kk7AzAakX9XT9a90EkvyrTE7OCkONmL7RwCUoN7TJI7n2
xUIlwuHJkRqMtuDLlS+jTy3FMdp8lnUemO8urEKYjxUiAjJgmiU2kmT46U/yY/L386C/47zrLtt0
wKbRVyce1GhpraDOongsnnhdikaqVWK41hhTOp1IhSWli+AKPAxPZURzImAb51upjWdT5jx0erzs
bXain4glqv0xRMHGwNZStzaWqyqZxotWy2dfU52iugTxWs7ArQZTBW9WhEd9dnZ+MhXBL0GlLq9c
AQumg+recJCxFIl6DENPZD7IqTvmPVmw6cWbkzbWfc2Z/gLFmYpJJOZVbgFJ+zmxKSwzk0wEN2I3
CNYYPPUByi/pyzib+tY1hF4IJLbHJsCswLnKPLuwo05tuwzHlHfGm4kEj9hewYiC8KCBa/RN2HZl
lLiqxjCh6mMSKBVMoCIoWmowLJFEoO5cQsxH9Rfb4/YCg4vC/PJv3kaTz9meVRh9GUpIuGVvbyYB
WlIEVe0oQFr1uCznYq6wwbzSvNTg/Ni9tojcZo5RHnCJk5udcKR69jHJlt54BaxeN286+aLw5a7k
Pdx1vmBnPoemSnXNbKvN1I3P8QgsQ7wklSo6Ge2Rte3iSZGcEHxGc9TvHKkK+F+vT9l7/j/eK3Vh
EjPI63zbksCAHYm/bx9370CanxSWwQnfAxZQKaIAs/xDWChz0MniKa107m/oYSh6ehQ5SwExLdE6
HeznG6CbfdbwmeHfcXGMXYpF7jlFhCPHD0H/tWi3ELy7wnj84UdV6DWkITurUQE4cyh+PaEfjU43
qWpQAvwKKModbTEG7+44TckTGhdfjlJmq5R8hHOKTDoyNOdb9Xa4vavZzxOFPjftVjQNi51USe3o
j5K9bJsmb6DV9D9OXJTydbEuuNqI7zCGXHHezWuBtcWI4OKw34yMdEhOBMm6vN4biqG361SYtdNL
5QWZ6Vfj73J/1fz0Vlpmtayqv7CI0IB1UoEuSaOst3AFDC+aCRkqMZFmWHiOJv/9T5KFroxHwW2w
seBd0rsV1dz7mWxC4jqQ52o+UZIcGbZtqSVP2vIIqWHBivxvyqBOpvMHX/YGNot7mwNPVYsLHZ72
0L1fq8Pu/NWg5X1Yrje27EfTYNgeQmMyUCpenhKUG8PB4Go+S8lbmMAFrB0p9XVlmjlM7yBY2/ns
u0Qe1Q3RnsARQsc1yFvZNnLb4k3R0NEFeo10a4Lh3lEcMeHGSwPvOxiyHb57BeURWcIzOnzkXs5j
lYbKT/U+qJu55J9srZ/Fb1HfYnyME2o+Dsubhwxut9CU66ejetfDJ970xVnHIX0H4B8b46toxCUM
HsO/KFQ+MQoBp+s+DJFrkpr6WZtmeQwdF3nLiZ1EkrxCUakwQms9Xd5X4+ONkxEw3WLszT+A10PE
WObzZtU9QOzMfTgJhKnrl06XozoM0VjA5ZkQWcWYxHlUDIPVzvuHZL0Iubpr51uyX7Fjgb58mO9G
NSPNuQNYbaRQotPcDvC+jjpgY1g1P6xhlruiD+rsBfc5U3hb9gh/robOOQ7tJMW4NMNldMe87qny
glXg5UbRPsMbjyTUSfQWnv4ArOhmmzogfXsDXmMNMHJvMW27/JWXCYdYXhtOmmPQqpjTLRqeU8x3
FIWKB7rjKylyxfmPtu6Dih9tcs2kbqzyIOYui0J1N+RAqBgprST5tXsGPUY0z0CjKZ8H2YWzFRWV
ILYUO2Mr1JAjwPNq9jBGRAoHMOUsem3Xr0kqUWqKVrTVfz9vElLz/i97+vAS4xPEU9cqoUf+UcS0
iEMCCZnBRiYZ5GXOZoOlGOp3Dt8SLz3UKThD2LGtIRtnv+R/Tt0R/4F/3UhaVnZxEe+ELbqIQYbn
Su87EWYRy8pCrWSAD80e+SGQ2TxY/zAp0MpGw2DeflBTpX9rxJkpnV62AvtreA/c98768LplksAJ
vyl3GGlb5BiDi7lLd3poRyB+F6+OryR+x02sO94lKEvsaYidpgBRE/leYXqlsj89UBmEmvWz5tYg
uRGjVBgtF93KQRGrUOff7IpOTFHeoN/iu8LAmqcr8lg2YLBSRB+4QiyshMCo+fMeMa7OkNBw79bM
bMt6e2yH0VPxEQutOheqlFcWkNQfvB0U54bBelj/3Fuc5Nr6a76QP2JPXIvSWSugQ65sRpwL15u9
RjZSl2tglSdrakI34j/YP/uTCgp89PoG4P7SQefmOojQPckndEGOkP/qeRRVbQ90uS46yWH/hGCT
5yjmri1L4kltV1arOcIi7ng6mgm87qzwxmihzLzZJLR8lTfw+QXgR/g6lpxIlC33uIhcqKMHHP41
t5CerosRahXlcy70zwOZbne6nSBBXoLJsoOc8i33I1tAet0qdqKD/N3S1wKKdtff9U+awcXDGOKZ
xo+ol21FG/0hR22PYBAwCnuYzJd5C1g4eCElHbsngGPuzuAWfM8SK5iGjTmZao2hmWLLem+Il9Pz
u8m7YOwPkSmUUbItV7yX6b0VOOWl/muErUI9Kbm1pW9dG2e7JsKbTKC+Wk6Mg+c3fOrlFcirjMmy
Ro/4Zy4rKcCMuG9tEJ6VOZ+9DAzvNPuOWFgLceVHJpCb5xNZThpRcJ8MXt/141OHQeQZO+cP4Lvj
oisWzS9Ag5TPoIa1JtCTkC7dJLYNx+RNRF/iD+PJvYd5jch64vwR6BPu4lNxBKbAnkOojinOxaPn
lHHph575prDY4tBTTwfYYfNEM2ob8OBtuxKzw7RrZLKnCME/3C0LHzKYipe/YLeZPuCIjfAn/V33
rnxSNynWIvMxFN6DcfPmjOH4Lh/E+xirbvWF6hrGL3Oj8VwB8Aw7gp8WqdZZw5bU4MCj/VLnYN+r
xFBbtAjAApvPMQpLjRiRyuj/l8cJ9OKkjLgqg6JXrAXZY4jgkaR61PIYHiDYLMyup2DAQGS3ffKq
8nFP4jSjzMjc0wSuBR6wY8x9FySOwY+sCOUJbGRiFE/RDLDKV7npF9vuExd2P/mnfnof7pw8959e
cVkJSaf/Kbf40w31ReanEkScyMw5rn960OQwAp/qFjicEQoy8CQp+syOo/kkh1qMRYN9UpCMDpXt
65bg30RPZTthOT2WsDGJPzMg803YvOTgKdtEZSOEGeM3fWUPhBrMiGz72NtA6f2W7aZ/3lLLQ0Ey
3Y+I9T2SOog6OUgzSF22PVzg/BCEhwudtWf458kgBSyJt9i0O5rGW+Got1v0TFz66rz5PR+flep3
Cxq/3k39zAKTJ1YHuL29kh5W32yGljL9VLh0exXs1eEIm1mul6+zEUzpsgtHjC3BpiDNKWU7YaaG
06nhVg4K4QN2QdVFpzo2MxAJm/3flfV71+cuEQzUJ6/Inqdbd6aZSp4N7rzVdOT5M2vYglHi9V6K
0EdZrA0+nWbq29diECITzbocDnEYYD/6YaNSCgFD/MZVVGkxizMCw1UoDsMueEsLS2iKCKhhA13m
lZ1czCLfdClDOMPL8ZhoWbfEjiEVLQuj+bwAnd2N5gDPz0kK+L+ZmgCrhhv17uNdYh+iBoaS/faG
imx/T7Q3OTvRIeuVcO+/vrA0itQZjT22ozIse5oPxjnno+l1y+rCNyvoPQyOGV3xjerRy1xBBIcv
84yB4crh/F9ksF0O3fdvJqg68WaWKOQfczm1ggwAejzD1CqWTtho7RzqkkFmxBc8rJDS7UHPINcv
RjolRTetClMI3JObwhC4txI7UwxFeS/PQhsPHANwkcyrxLkA+f9WEIvjgjXuXjKpics7HYMhsShX
UBJ9xgXlfbile05w9FkvcITovSxAvQ6nFeDM9Seb0+9LT2fZv7alenKP36VLEUosejMMWde9LObH
56IoqY8yIxcV8sUrF5im+ZML2bIkG3I956qSRJdKVuSInhm58EZpt73cH00nmE6JMnriGAeIZqGM
a+CHkxDwBAZBEr+rg50micgM5GSTL8NKjRwHVYsX7PQr77ieucmlQMZWp+cPdqCQd1HA9jW1NwK2
QxZfEFrKeNMP5imxG9Y9qYVkxafOc64wTDenNnGfxccHNSUh4UryyL8akf5bbgHzEJoaXBa21xxZ
mx51c2p5eyRkFyo/95RDyKq3DmR9UpgfWzyO679bzAoeOuoMnfF5T5kwG9xwLrL4BtEaocf0Lv4j
XplSEQNd27xKb7qprwFMcKsJm69oWWLw6jchU4luRb89R8a2fyAuorzcaO7Irgtnxc8Ugw61IzCJ
xGcXF0YnpN/ostYTWbv8z20x2CMyW5sPxYK5WBRq2WQLDFk9YhOOMlgV20bowjntB5Ijry4RAeRy
B6O7io+43quPdcVPBBQuZJpPi5Z8NBlm6HvDZ4bH0XcTndMNW20kSb0bZrlHK78gs7UAKnOevCSy
+3hKYZZUcyl16VignBy26ZZSRHUYxAeuFE9PdFt5t7pJSu9gAlLQcjeQMaPvH1D7yBsXB3BHmQ2i
F5AOph+ddirFzL1pGTK9zWDlCu2VKBuLoUhvL/S6olaoXpZ7yNg0WpLufFZu20YnbhPDXs/jz2xU
quxoI5TtJJL3sxYwB4Qh+RSfSSAZst9OArvhGcqYhBkZGVqVn3Fh8MmNRh5X13iiSN9I6CQJ3JuV
umeoiZ6oz3y3nmd2ezxR2sbQSMVxGMCZyTXtemlwGqE+8Uia0TiaHqFf17bXckV47Drr+hlY4ZQ6
1eiFj7eJ2yt0feLm9gBnvHeA2x2S8plXswCcQrPQU8GgtOpsgcYp+Bcdma9zJKILpIdtLtgQTieM
A5KGNNRwBrruBaS+4QYyrrBvzYj7Kxjvyo57/9cNdUyXjMTOIEs/OQ/pP7DtitchSzF1+XhMC4v8
umNw5AsZLaGR9nSwf++2zl6wFMiFcDUrgfQNs00hK8QNAufzLioGIVplmI+h0g8gHttRN7kDBY5c
UAMbpn70SXyIHrT76O75aJSOmLKZywy7g/LlZ1wUaPEjNmYcuzcWWdy0L0tIcTeNpDQXEAi7VAfL
gMdhlk3P+xrlprhyk26EhMuoeRnti4qz34LczfW55WLRHRZLx+CN/XL9j8S3h0+m7S8zfE+Z2KnF
Ff2bUZNfa+5Zn92+DlDzmWEqq8ZTJxVDBbruuCGhxhBjgW2TbedGtSexE2U8OaMORBoIlGPZ2z/u
4dO2LTDJRUxXs8eM+Mxwi3R72JxRBGvwPbmF+MbBugG9ptAEpf2moE49EHEn1s69wY/MizEviQMJ
kJW6tDv6eWMbwXTH0TOEHI80ojSn4+DNv4RDbYRgGAOZJR52U9WTcyhlwIyvTY3eerPVadUKLiRB
naHvAEcMVP1HEJ1iBOzZARP4s3OBxFUL5gOU9q6e3lMjeWrGpC6gYMAnZgr0sX+XfLEhWPVymLOj
NURVlFWOd+q6HLBcRCR33JutBuBDjM+dR/Od00AgrM1VtFoPywF6VqwcCOmIdy8jB1TRuW/wNUWN
R8cl+8a6k38ZcUJqAdFppkdiejAAt83qe6RRxDykJYfS1h4XrLreymx1Ob4n6E4BCp8xLBOkEWro
eD32gFW0t2Qft4R2q1MSxKZByNxPz5CnBNufImBm5KR05l8rEpUGZQ81USkAvG1IOCBtdxajvqzB
PT9443vPomEDBCNTaPzXBHo+Zsrm05rb8bJavIpVF/pD2GOh2Lgd+ehdjTSicfmgT7XMccXNBFwY
hgmo4ykCE1S3+o+fRtiuimfbDIDAFZPwplGOkD+h5UQ3mZotVPK9hhWUwAgUFj3VlJk34apoTE9s
e57e4e7PqqQMnhlP8yc+FYPsf5M3rvUKRHbk0jBN08Br+nNsAfv1/5kkBw5GA5eZ0wGuAzDykKus
COcIvfTv1QMza+qlX04GollavVsJLJmjpzIsAhzPqtmyUr8NFsLKeJqlQLd3sVRnytvbdARgH1r4
qm3ZwKBQ11kQBdYUHO37e248kPo8ZwjvugqKqNJopXHPYzgDdxRgJUKIXnush81DiHkvdVDfylEN
5hHIg/LF6mC2IpRnUMjZcae6lbjNvhpxY4o6reVucVvf6u8+fiuW+Jx6RieEb2V4QJ+dWzvXWAUT
CztXHbtfEbvOS1T2myuroiKE8hXqQjJ9fA0vQQBRHTy4UY6yzj0xmX5zZvLUEDUkbvSX6piCTQBN
vTgex2n2kwk2XiXtxDsTXt+fpn1dFGBFIF7ZB9oZPHM1STVVcGVlegPd5fOvvTuvC27JVBXTs47J
HVhzL3klStG4THMR10HithIk5wgwRogkbGkqAv2iHS8a5od7wrbGEBVX4e84NmCbcLDLC3NMvur2
bCVQjV1a/X6HKuSWbCOmn/Wbs0B6Y2u7NDN57u8f/mYEHkkV9CjpTcwhhc/BOqVStGizo6Xcczml
qZLmvANA/e4erGC+ujxV49J/LSz3PaxzB4jaSRETSc9WzFIUdYvb6z6/ofr2Hto6qyXluoy1Rml/
AXhpR31wUpjE7mfE5rxDX+RaxQnsHPUlKSjAa/0Q2hL1c0MAbvUDknKPEMZlsCpjbsu/vMoRXYYG
BExRJcGD8DZN049v9aBEHr2vFb1exPWhhGTNs9iDpFXMi1lq8VEalUG87tis9RTbTxPIUrndI6/B
FuiA+XZ811qyQor6Dt5eKXB16qRhkMMuXJncl6aFFi5yiYGqiTOm2uApoU09cIZakf0jOwCvsMz4
VFMbbBgUUhK9Vv6tn37pe2lOvhFOv1zbyWEH0PVtG3h6qeddtohxmlZzMvny+2kf2v3N314grdnC
Uy/WO9ZKwXVOi1Lt/Nm4lXFPhaITEtS/JWbikDfjd7OkD5EXlkhY3WTAFtzTRAT/LLrQEY88MAsg
jAK6B5OxQkFstMQ5yHBGYuVtDZ/5P5lMqN/rWRDD2irh0jvPQ4FevGAwMyM6GXGwCjLkzQ87+3st
3iVDt3gau7TJOpY9sjbEqe65fLubPdJv8+chHyyTXcElCvtDuh9o1ZtXdOR3IYqWqgt/5JK6I4/M
Q6BNNHXZtqkgHHdhlKJgwvaLt/n3V78ttnHLLrh5LXeFXzz65GgGqgSNLx0JWxZfhAWS3FbnOVbd
dMXudQ+sqNxp+2YwxASR2On4T1htK9GUW55G5fDBOebsEuBQiO4LyPRjS3TNEVLXkUiZqyiowKcb
O6MLqZ8bzjTFJt5DdIwdDfubaTQqFe+PEcaSVbpvJhsmzXSIARmUYDp/OYWYUaSrzA6u1kkyySLr
oDzE2uaPYuQ4VrlK4UdqDqcpieg0pni9aRkhjmZ7fw8CRHQL1nF9M4E8614xte8cCp0SdrvlDHsa
fsZ5dlZS9snxUCo18x3y3gTTAz96e2pPv6kaqMkVLSR/VjUWUY1aWtljppz5YVZ5NdevAHkEv2oV
+oyFobLpQudxM8GuQA17AnV4k5Xm3+3MsSnTtG2psVrU8s4btq77zi5hBxgUlxlkTsOLzbQ+gcEF
ZPxL7RhdbVjePLNpuZHQgDXMP0i3+jmSAp9WTW/nPStFKdQ1fnEmtei70jVw72xG3f0DthzZ1L0Y
EeLiIFrduNLJqaGmgNrui1nDb2QLbge+y7Cw/GXaOD1vt+BUxx9Koj3J6IshUYiCwOme7XBp/Ka7
Id6nnjJ1g5Q6fsxrbF6EEImn1hlh4AoHVnjjAvDKl/1erbfQvX+J+JaztecGhVTR4yoquokYvi8U
Kk+O0vc6HsonGFHg0BDVzBaGsmG7jI7FIiHdl1vT9GJycfBWygNiF1lqJYIBPZ4dSeP2ohSFQPtW
+8c2Qa23zTj5qGBzGjMZzfV5IhlnPL+ehTXJUfP0AmOX0AM25vuhl9jUWiiBtELXMeJ0tbtIABen
kKdgNJHU7u8By9kQYQ2vVdLLF1TSn2cZh//IPLWYKsIK9d0fYsxj2y+YeDqNFGB0poicQYGhM2KH
iOVQCUGiIt9pzNbOXyyWs43g/vo5q0S0uPUCOBkwqsrBPZ+Bxs0D23WHRqyjVKn6YdyKDSvn/lCv
Pn1Fm/GKssR9nqTsV8TruRD4OBgQTRor+Gy4WFaUooAtd6PsEB28gyxsZLpMtzvxygozqyv3VXjI
dfkDfvMb78YTpkuZQrtPpw/69UtzsYlJ93+/QuDaFYCQh1QzWqz/L+PFy1gmULU5rZMb54/stfyQ
dzF2VZaS735vOpfNYCjcYFAkIKq+O7mwhgk3y6NQMmsjXXeUVuV+LU+VGAFzFSGQizm3i5CPOJJN
3dJ7JemAAnjHcACwYRDMOTH8GpcQhZCO5/+YTMQrr26B9GGpOz6TqUlw/lRjE0pkK/H5zLRRcDm/
UplNoEFF8ZMYBuwPTrfUlFTeP4LsaCPwP9yJ6zibGztYRhSU9TkAObVrVZsMd+Oj5eikHbSUm6Sh
03XDroB5DDE5Ga+HU4Mr+RCjVcXUsHjx8Dr6/iWvhfNPwc6lj8//JaOoxjmXvOE69Y1OXi3RVEe5
YTZDFbPmQdVG3nk9sLTsCMv0iMHB/zwfiue6mz41jUObJ+zMRWkMYfcoFg76i7403CDKWo5r+U7l
YbXjNVmGK5ZiJKzD7P2A28c6xaWnz2MO6o7xObVb5rg0FeE4uPW0XZc+q/LPCK6NH0FDloTENKqN
CmAttjY3H1O1KKkJS7bIwAdQ93tjTdlYhT6JpH1EVM1YQL5ZBpSAcIenHQNj+fLS5by9JKaNZVNf
MecllFQC7cBfTccjUXshvaBnekCxOplzV8ckaI7Q/aqagUc/L7V79hEbDE4abRLRLHBLcSc+8og5
sKtLqeNn3u7XZi4tiME8VGyOLC9X0Z+iXpNy7fYIZeRDJS9CMGgbmWoVNa4JYOHHHqPyF5oA6jKU
1qxa+1PSe+2zFgj3wGpgZe00lFd6n31SELoHMTIork7cKGQtMcIADL9Jj2TbJbl96NIiLWSWgXUG
PhwxpB7G7DYLfXbn23AHLuHp6oErJBK0Xlc4R4nF4jPuX9a4bOzWmZuiQF37WjIhPQzjoFaTUZ53
96sLN9+jXCD1Q/sRPPzTH4h2G/lpEaBZ7IMTNVyjlh8cHoa6IBGNYfB439JZ/FIqnC9tfidkNE77
XHVC7z5+b0pkwhXZ36jE3wGTubbbWck4bltIIXTLRCoNfgKAngj1ajM6UTknBSlHNCPViPLhNGE+
TTCJowfi49JJDtelkmaEhzA3eQNfVzzm/qBdFn58NYYHx8QdK2hBAr6b/2nE5I6E/o2G7wrbghKk
Kj9F9A+BK67jEaDQfmCIv+EZ/istkal1M+kVQ/Jy/FHwMD8I/Q5CrDMRd9gcpYWB5Cs/wc3Ubn3Z
E8/FpjkwZe82CWrlUZEpPaqGkHAUQNj5OV3xD1rluGxyRwT0SJnRcXrZYK29/cO36c1u9gRAwCQy
k9Sa6ag0jNL0O3KH/XP/I3osPhLtOGEtgajOmcMRnrzz4YltizYu7wFjWnXm1GUtq6vv6s9/F4W7
ryMvHxs11/zg2V3FAMObYRm2SFNyFnSBwbhrhyg6AbpJq56RNMpkvenoWb5vQgEV2CAHxBuGeJcw
zidCbKQuRwprPuydkZmr5MY9J8ikSYsVEEFq/e8fQRolF6/N45W3GKVJHVkPlIQJJ2IAfrL7HlZq
74IWsao0Bfx1Fb/GuZnZbYyjXZXQk/DOOUT9ClTUlBtWjX4c4l7PVx8iYt7H+YODhuQzakdwsDqK
XSXV2/0+0gtqOrH/efFIFCvx8QLvzbR322heb8uG1TtUxHbgYxvJmMuxTY0Kt+Ck6jZjzGvNE2Iq
gvjpdhAsiAjihLWF4V16bJcDPyqTIruL5dAh6LMq7BR5jWFCuLEK27qS2HbmowhRK2eAiors8K18
t5/yB89hVJiK1VAnmjQP7VUJaTwv0JXIIt5f+egDAT6sMWy4LiX+UnV7wfzwqzCOWcgEjXF/Jecv
kLKaG1HrpF8N4YNegCv1jvLCFqLR37lk6Czxz6YIAP+Sn9HJB00wh2ZVv9NBI9ehaDw5glvVirla
UImOu55H5c6oo9JyHfADjr6Twa57lo6X3mAid5ay7CW+U+GbL2Ks/hvZb/P2bOLx/6jx8EAXxqBu
aEzyxmHnCbktHY5Z8rVvZi2Epj+mk/1sT82OlWtBNB0JEYqCkiiFCTLNcpFJbRTm4hJLLf527uMx
YF8v/kMEdGR4YUj496sNH1jf1kVCa/igONjA9+rQdfbOLicvBvj/m9IoRzgVGiARsL6aTsTYjUbz
iiw5louYy1/C/f+x6fEZ2FkRnzeFt9JWO0e7wlS9jVa6x3gmnmdWEc8MPiNsj4tqK4Er3uU/145B
MvYV5qpfI2SX6Zp+U5qD60aL3pFodgdyU/WmKgK4OGyXJ/AMQ902VyZIjom1/4DalmSz/vWisjbK
IuuLNtmcpjfccnQ1iGElM8l/e8X0t1wz630YBvbcwsldEDcGoX6uPcrAzjO9EEkRzguohgomTJz0
QX/F6gdCbCI+mq0nZgt2a5+Ud9YaKMQte20zaZ71eYiDUqynHh2LgeZmlVtkMWW+XMAivdRcoI/o
0kzwubQf8QkOqdv4U0XlP1cvxeRwlb/BUWsw3tOFNcw5KVYxjBJ02CxJvInKtVkmWKTnf2jDK52x
ysNQrZNGKXShEhrSBQzNGNmNEf7IzfTwTqQ22RI05Ad2fbs4tJ8to28hGG84XxWnO3zl3nNvUh5k
j5+5GB1f9eYY01119MgMAripViorZJK70iqqxy/yjWNngZUMLpCH6nD3f9s9b97VelXy5w/LIRuH
DcDrqzQEIKmLa87TRvUZ6k8HCTOompbHk5128e5AlIpEp0qOhglE9+Zd2m5hFGqQlAGpLrl36CiS
qbHzF/1TcnhQooR54VeoG+aVbbpB7feXRGLyra33nq2aoCmqAAIhyYuPYBSCQAFO1myn2O5129Yy
HSu1CqA6k70D18ZL7B73W68Q7FO41GLtmkiXGzM7SnSyxr7WwhFziBITYWesF2tWN3emTU2BTRqM
9hteLIPwILybEFRwk4/2l0HEWex556xXjM0I+acBVsiZ6zCLAJ/uG26QwtLfMTh2Ij0meyT121SU
q3PMGfhtfbm92EwUiHNqLCl2VQzPEojFR+GirZUfoPdyslYQCW6BSW6bSgs+FkmY+C4Rn6oQndcx
XnP7R66UOwy2EIj2/lVwmlTXeSgJWScUOi76RsekR3d74PRRh4TO00d8MUXFpM+3aS5Y/H+xDMW7
B8tPaIcyxlTPeKHt246lFvHrwPRXk/VPyNFoflVdbosuNHbumgsK2uPl/naJbtXdjq9SYQ1kGZRu
x+e4Q3iwaIemdfOlVF78QQdTb8lg6pd1AoAZQdeWWmBvV82zGwy12YyW3CDnmU8mEqtH0Ba6HVfq
1sOFH040882Iifqr3F9u/X28Xo1bjSCR8pCmo0GDO+I086Vw/W4BmUx57Olm0adXgDQmYj8ssbb4
tlYRknOLFr8b/kzZSSvFV9bPVs0WTetnJ2ePs3dWkc63i2WBI7izE8K3xRfvkPRFyVM4eXJoRQM2
voqgJLdaflRl4ZEJ1TAXY7Qac51nS5VmwKX8wwGnFQ/z8xVkMkpzFM7RF/TwtLkswZXN4uVQYpRA
Pf/4naVasI1hmKBRPApTupGmE9pVttC7oPaZ/q6qMUHskZYJrJy+8DW0FdcJYsSFsgFu5wwVH08J
0dCzKJw9sTG7Dqwkb/i63I7PNme0/oK5r2WihsP+GayLBAmTV7x32h0woMQj6U2qVqMz+BlX5J8N
FTpY1Jw+T4e+xVKcTT+zGfAmNZR0skpouU38ejdKAWbfR53u09Kb/CK1B9vcjtNYWhkB86lkaS07
98UdQ3W9h3rfZCWlD3GViYedfKRp+mn/Tg0onkwplRj2HgYJPKD70pqJVMs+FE63PCTTaPPkKrBq
OvjkAxBcKRpwYIgLv3SRHLwRTXEZ9tPtfVTF4WbD0fHs407uqIjKqAiBPVXlFrstu2ML/WEJRh9y
2++umUVn9M5rgrer+9xcqrcJkIHsOH21eRK90eCoZhl2g2QL/uCQU3MeijkqseCT//XhQieBEmor
5dQBXR7PqO7ibckFaoMPU4J5uxlPhFEsb4ZR30lTdl2xBsRpSIDPBghPb4a0PM4dVXTxSVOTe/3O
NdsNTc3O49EUP8Uy3bqQbf1uDgZksuqih0pr/EvDoT9sQPFy0tb7UQooW79pP3PXt3BtGowMmtlS
3rCpvGzfCZLSJf1Kd4kesXbD/vVhuVXdyghshfA4AzdNA0JEWkamEo8K0V2nGhcY7sZ6iisbsD0v
C7YC/x67E3JqKEAsTBhOrA6DnA6mzYgKsaS0d9EyOK35SZQDf95OruDG6HK/sLo8VS8LYr+77BBO
pH6E22tWKju4qvF65bJc3eXf3k/eLudY3eWK58QaRkXO+2tpR7W7IrUZKpOBmPqakWPTvSgNtyqR
3aaWy5/sOYlUUH4noSOZln01p+A+D+Gl2/z3OscseEcrqXSIPzXAdG9b+Zu9y9zJbJcSuWeWSCYY
4PKOdX2vpLojWVCCs3fPAdqg7Bwfjb6CsVnVMiSVLYJPvyupNMExs+d1bYBYsgraqTH59bRL2jTY
kwmsQ7azj/TGKIsCUtDZLTCCl0rGxYvJbreRO2K/cWYywLLTAtasVTM/ZUE2VriKw9NoPc3pL+8c
CzRL/W+0GUgs0nuapsbW66/RdMDMcHbaeI2ntMIm2+0piwoTf/FRWApRvZJxizp0cso9tzVilbQr
8Hsbqml31RpiiLLuLeJF3Wz4a2IaybWuVXIpUfgOj0F38tlcfj/VOPi4eFttncKetNbO7fL+84id
yn+pRiOuEp9qkzpPycQXUoRrwVj/NFR89kbzf73zNONfIjmwmCUEjMdt6Ds0RgLrnUjAL8vSm8lU
hsjtIxGT8SNZme6hlGKSztsLEmS9Y1JbNOpHRA7cAVcU0BquidEqO76GPaIsP/F830KKLHJOovf0
GypzdmVXOaqdDixhiECboCXTuxFRXNB0beAGIKWPScI8/QIZYy3FDTloS+O+va+KXgCtGwFoFlEn
dt5RrIdF6B2IUpDyIWexqlWFN6IqUKuIAHa0wWV090uXFLrV/D54XPXt39KdJVfpEJo1ooXqBev+
My8HUm53Bg8qXQdQTKE9Xq65W5KjayAMF55Q4yzfmjS7ooB1dkFrDapC/OV8q/kJjc/vHEX0rQKz
b85RE3mFdbjrJwphQxHg2ClietY+EN2FeANip1iXqYrdurJmKXTcj1Q83VUxjCSZpae5vA6vHgQr
bX0c3MvfV5MIzC7oBedBxnHVSxW3xkwn8dk1R68pEgB0yTkjrMvAFSX62MbqvFLtdChGEJq5Upa/
K5Y98TmjNbUie5zBV/Dk7XyAmRBkl8hjVebIx9GuLspiHdpERPMc509LlNVuFXkTEbvcupVaPgUL
vew1IBBegOSdj6Y30HskKRGqGRzN+IQz+bp4GN6wnLTHCbtK3MMXcD+A8AaeYY6bWiPUWVwefjAM
6zVKZ5JOqDrwjALbBAmiv9/JYI6IqlT3eedSJgFNvStSWuorZVE2hbSNJ9SQqDgbawU6r+J0/4r/
+q0SvaPbULGMjOHwY9nmniplbjw1x+tqC01oCbwAqO13R9XoacZLUd+U/D5PlOkA8jF90x1jw5SB
JN6dgnx4Vbg9aZRGcZHrtrdwCHFo9gxlVkZ7ydeihubxj7g6L5twSqGYpP5X61Q7H8dvBuSRGxLw
CljJJGvX1iQ6uDbKgUu1gTmUi527sKAevvShjN7P+QxT7wVb4zSFWTTBtiCDsHRbX/VIZ9ApMG5c
agcte41L9o85Frwm0aFRvd+8WaEb3QYa4BcU2o72yFuBReaekzStftoXOMLE5yBTwRKdNssGZOQV
Fx6bpnuaqe3q5MWFhYW2IOTZu6RApuD58lFkysscEUWmAhIJlFSw3WrvRER6cWaqBDCXyXhU7GjC
RPbu1i+9vlAyK4Alebm0Bv16GZ6Ev379C9AY94WHU3KQVpGN+bkwTzDy0ju3uKeH4HDf5Zuqq9N1
4LOpn87LoD2VGaRbE0bK4G9tFdC00xmSvLegad7pc/sx8gqyXnJdFsfGcRcO7000tYXwio+M4dMi
6y1T35QcAYvz1RTf+NXlU3abXStAsK9Jz+yQ4V/Z3YZSf+IStVfF4uh1fD5zU/pnGQYmCkQhJ+6/
Haw5gsVzfC5cesRHhVMhAJTuJ33dFkfdBuVJKgTXtt4GIHvtM7xZdYEHceuwW/KNR6VEv7BKoRrU
AD54NtYug1RxwpVscb73EgnTQ6SHcME+eaEdXe4Q6HJKORSgVrqViHQamqZqkNRPaFbmUH8tw/7/
GjlJNQEzmj8GCaYRde4ayGkk96xiv+Mju098KBP+zqT0QyLrbq6SiCJTT6+ygdl2u7SxeKMpSWub
Ct1Sm1GUtdfh7qCkgTvmUUZLQh49NuhKaOy1GIkuaSLlkPTa8rZPxz8nqwFGFqjYyrR5jpHbeZxI
IsaZV4HlU/2wLP6iyTbAL5y34q1ufi78U+Cg6KuK40rlXRK9kJr5kCUcU4/Gr0bME1yEqyMcZjeW
i5PMvQDRjye/9SIQQDWtWjjOS/GaOKlL6HuwWz3weN6ShFvsqfRU153qaHSS2h8aFh37qisIF5mC
nY89Gr+u+ljasK2fRxMh8dGu6GwJG/wDf5aE+Kjg79SouXF1jaoDWlxZgD+mwa500sv6bvXFbdil
y8oo/lFpU4rz9O2CtmZaFbO+RGNTUMyEUTvJ2BTONTG7TSlJvl1ytmn38e2ubW8Kj1JSR101yzZJ
fbGJmYAsz3KIt/CY2habpm9A9sz4bO08ILQZXIyKaXzgyB7W/d84Ue+TJmfepweJH3oO5DqV/mbv
xBEg3tbiBJfiZMFrnoir78Rdv5Js6BU5vqsPzrKTI383HzUQ4JA45ewXKyth4GQpKkprxeU/B80w
lFYeguRpdCR9aOHEzBY6LFfXo7PAWXRRsmIAnja0HAsdOmszNlorgBxyxMdnPhN/510sEzJ7Cd+8
JM96NP2W1mYv2lI6oCm2qn4rhp7tOsWWJE/EDrvBvgjGoAyJs0fFknPNj1pUVAhBClUbwS4Qs3qL
sUA4vBNhiAPFKbw5R/klM3j/GHlfo5t2q/rsmUavX2B/stY7KMyQtUmmrroJTgfUx9TrDgSLnNpb
e03Dw8Ho3tzSL1TozAxz3+6DuqNgCZ/xaPC+lO3uWuGmJtrnoxyqEU+TDqu9Ws+P8MUmF33MIA3G
1+RR4k+6ksUAuSrygUQIfUjQx8s8qOdyn5yz0tD9h2tlf3mk1te6Od1C1cLorJyTK1fY9MthJ0t/
oDs37WnQIDGPQfBMnduiyq4ZM9slbfOHzGesNJVVlphbGze23IAL4itwA3nYZrvVft5xmQmwcPzV
7D8qlZUPSLUgD++HDXYw8eT7QKt4lsb6tLkdzb9iNSgrvwl8Hp3LNyQaDslBe/w4PhybDKw1b116
+0jl5+eG2RKdAlq/gc5apKFBrxeN+vxe3fgzTVDTGNQJ+vCevofMRKPczeEyx8J8IZaWBFFN8DSK
7iUkga9cHiRnffHyyAowZ2/wsskZnpyiXsEt2ch8OxsIwrHEscTGLMiL7HAGtTPWgyYlx5hSPhLW
kSFZfMlfOJmsXhqVIOD7QM3zASXEJ5ngM4YDbLRm9oZ/6XTQOSEfMfEFSExmqPUQVP78SX/1wY3Q
l8xxyqsa/YndrROHsFtZqhlMkRJe2GaX1DcO/rdouJsOy1r/+V5NpISM4gZVwaT/448DbmWanBMH
sOekVP2RgkCxuRZp4r0w9uxMpUX9PKHsJe5JqUPuXS5NLBGhjnDBbooFekGgVltoaz3QZ1RNxL+/
y7codRas0VH4qPg3t6FNj1a9rapR6wZLfEjaqYlJ67aqLXWWSA3cxUQZwB3s8Z3ylnpnhtPlYcEt
IQM5A9gfXPhz+ap6pgwPb3KcgzFMXyA5iFZB/D240yxvrvlD4lHA/eyYaTtp4bb+4Z+0cVi7Fy2c
VccrfB73+clM3w5B+TJ5nDEbZ40CJn85EKi6FjVF27qWcELvaCBaIjGKwerN/k6SM7veRA/ErNRv
NJGBPnFjCG+M26AMNc+gzFHM2zrcy3vA+4H+x+xZc2YJVXO+WzZLKoC9+K1wMSCgMXeum45NgogW
Ir0OUo8m2rUJPgG0584Sz+lFSOWDKDEg5XCQKxfkhJvkCUWAiYoHrzrpkDFXjTgALCR2ORmRKGFP
5KwdagljXRtt64iPfAWq/U6cJHfHa8KpkTu5f7vGdsixIMC9TxhHbnQ/C/u6G3u26cZ1h4VjfV+5
dqLrfN/zeKVQbOMt8u6OngF+jZb1TI9NqZMR0/a2Pr/s4qUVvYRw6Hoxrl5BS0yqX2bQZT9iaX3F
nqBjv8IRGJjcTAkv83QJyPYqMhDN4vxkUSelB7rYCF1ycklAl45mNhUSNhYOobeqwT5eJiGS8EbQ
6nIvyPIaOoKydryA0INqDqG7g2VhZIEmEoEwikjZK7w7xuSr/aRgb/8pgRPFxKWUhZ56GJCWrKme
/wPgbIPQFf+fETSgaWfJEWUoCUrGwppuepLd7EPg6QW2L63mNjBSgSOyEPngKIc42tBjEOOWTw7S
6HvDVcYfS5/v4eh43602EZj2DPDK2Aj1h+VW7KIK2LwPPA1ZoIUFhxcAz08V9jSjMcIt/U9oBlX+
JQXIBxMxfY6vjbrEJF1s9AruuNHIxHLX1JyJjlMoGD2q9+Iye4uDNOD0ZHl170UQxYC2mb5eGWCB
vSLS4fhDISEZDpwqcrn7oQiYsvTjdZmUqDyAT+fwhfdCZPgbRDShGTzcWlWSC+TTSYwPQA4z83Bm
Z8oLUlOBmSuHwN/hGX3+E1qqqNMfl+xIO0PoaqCRN1nbYreolEEUgRqdSle82nlN6kiXXiPRwjW+
Ulme3UX8fpAMiUf9hoNKp4sUxuEx6fHlzCGl46DYbB+6Nd7AxZyL9FqYx0KdBhWYcV5YPCHUO2AB
Hb6qtf3QgTPfTkPHPZZTjfvsZprPizYSXob1PRHvAhxlQ3I+xCMnP3qmNrUmutPtwKL7QauaWsUd
pI3wwSOmB/IQvszfvAxU28vB2Zza6CasfHzGZ87yWSnzvNt/TPW+a2JNBhxsi8xnrgXGkTZfMsuE
mvWckI6GTKSS6nX0t5RNpZ5wJvoOK8yvbwK+5c8Gp8AKV8QCzeWCjDf/Yq2v8y/rIsjp5k8UA/n0
7JZS+Aj0K1EyjAh5Cef0UCtcQb/NsSezHMXIliRRg64OJN+quBIUmrtPzOkh/aca4AVig0pfwCeA
qXAUMz7W6LLPEG7D4A44vZdjkPoJDMZrEF3ETgUqluBHxhnNvMW2qg75hPosFuDs++yXlcu6Ya9l
OG1grrLt/z4oyyXyQkCcAWJqGtLJTotxVD91KPUdqQu/B31q/73j8K230odVBm+DN54uqDq/5z+k
snIKW8QQ+qx2xp9r8LfudSItk9linEIulf/FsfK4lQok4/C6MRPOKkkZAwhRoleP8gDSF+GAKv/L
WJUSNnGilkwv3MH9TZU79aU74TlARhiwa6nIYFs8w19sBOx6ZD50wZe3d4c8Osm+MKQxNyR//Xod
ciFf2OM8ObNVHZwlSkenK6hiN1aqmPrh4cknNao7LnoGoVm3MD5EI+yOHanh1KUbymIhX21rk7cn
dW4VaYdl06SBqNuZgzt7SjFI/pPqRnqGGorzscKzl2+Oript6h8/pK+1e6a08lm64iKmAL37wZin
dILeX/g9sFsrAS94YCly9R/j8YHz/k2ValGr+5pAWatBg31f/+csq7D/g4sFLDnqAvqFe+OrLNc+
tsqNqTASqz/PlmNIGbWNeZ7gAgkldHo096G6Bz7AScsIYA/rIgI9vn5mprOyyWfphmlSTSAWvSc9
3/kmxJ4fh4Ayjg4r2nNWQxBUIh+PWP5YEVp0jk/X22Bmdpni8VIZ5jn6fnQQ9xPqZDolvCnA5AHN
qxpd+bFJ4jfhn00SpmH5gwI1HAFw41K3+9IVfh2tYaa0I5QHM3entk72QCB65K+Xh8YJXDvcjpTF
DAoSltmyY8QRMEr5BVEt58BEk8yH+d7c+kpoE6JLjDY/GaN0/BksxcBPQ2iesNJWjY76dlUeEHcW
+vfILjbyXny7FndMOsCPX85hkqepY4y4AYpKMYctFBTjQZIWEVbGMERlm3TK7FNWfv66YOdEW3L9
2FUtHBKldxCXwbFRChGzgrg8VlgEyjwb9svthBzxYpYLuS4jaERhIxp/xvkt0UuK/PgUK91S8ghi
wh2VJDoPCJcR2cXGJ3nm1cL1RlFuzvy1lHch3pMn9EOiXZie61q9thjxxNaV2VKTYFCUViM0FKuX
2fhsT3x8Gz1l5/l9wgfe0QNi5sU687JWtu5r5lbtlxknjliyImqiU3cw+risA9TRVKiFUyUNQ7RX
oHtpJlfKWrhBS3MBJABml/yN3PpMgg4u9SITmRI5ow7B+ozgldzgTuuEeJnEpEf/kN5z+LHQYBuQ
E1dqVVVj0F/8P3mSPEl8I4Q+XU7BZXvWPXzfnOPdCJ2A6XCi6d6keqQ4W0tYEI9wdadwC3cvx5U9
bE6cddBvYqV6vw2NWp1Y3XNlCisYp+Zc+IpbY6qzhTlrTDkuxv4FDZZYE87w+/YylwGt/bJpCEKs
k6Wx6MXr6XCKjsEPhinJ5JdDKCOfbof5tdkArUlx4ZzVfzXY2qq62qzX/cfK0vhD9qMo/f/qAh4k
rK3GYi+Taxiv6QKbBDIxxJfIBjipNW4YAEFGek52gcOfgrJV2yVfOFfqN15pu5vHmbhBaenRp6Y9
dzUoVzSgKYoSpVYDmiwR1aR751LYjhPIl53NKEoZUn6uApVLkKp91yBdDpUlH7zTYMugZ8SlOvI/
n73QY8SAdNjs93r3ybPc02RpRjkEiqOfNeocEQFE23Y2BP+XcrV1PpjGIeRDGjj6T/cijlvil9Vs
5Sk/S8Mj0GogJbMqLRdrAJO01ypDzcnEg1dG0sTe82NWK1yLN3X3mngKU+N/DUSwawXkI7PTCnrr
EzYYVw0fhWGMiMZufio0bi1aVW5rv4ywHMP60s9r4+6BWDpihUcfpnmJGRuB1FipcvesTkq6va1d
apVrqAw3PGhGYqa3z5oLSO8O8BBK9egxisYGiKDzc+AVqOjMUBU77MbsuciOmlCogfh+Dvey3kdw
fuxn3QCH81cJTlB3gGwUtmDqxb40jtJT7+Gu7uL1EpBKJoHxgevmQHFOjSJqQl4Ruy9iJbH5J/fH
W1YN/lrMEx2hJemg7EczoqOL5P+TaoUwb/VipOpJ/PSwq+hHwCp7O9p27jAztEYhqbHcMXGIok0V
Cb/6zrrBpkbjBlEYdnOvXuPAGEQuWGNpYlzzlDbS9APnHkvkD+1lVFR8WzKrjguoHDf8z4dLZJL3
KLEpEIuJ2MwsCYzVH/RT9A0yK2uZ/o1lqvkPJYz2WbFKuRz4JtIXFeV1heeOejp69EqzAoPwd751
4pJ1AsqAQbvLjPvyLCqSUFmnzgq799gMXDRYnz+n5mGKwtOU9NaiK4jSCMvGpkfWVzsYe0t/r0hw
k16VOHR7RxXDoHYXRRL1K7QVPO+IWS/6xdOb8PJyz26MK4s+PfiRv5VuSYfUgAyYFkSbZRtulDR+
EOyGqVL0jmGCOtag27+vnuOki4iOM5p6FkZMs3EToAOOB2+ZUd973xtyD6kII4xTASzap0z/Pu1r
ZWEml30tjzPhiLq5gUM/6TjhusbavVlwHuMasj1tPgFGJEa7AMu5HWT1zwJQ6K6rMUFIgWn0iW3W
KC3fSFyTAp7pKQW5tqW4DBCAHzl8y2lBXlZH0sY9KytLtfU4eYQqAsQ9i1d1hI8yd/wsEGl8mi8z
Joeuj2tSkJmhpruUFnR59iI1gMe2wahTjQAoaboZhkYFdzaPRzeamcAtmNEZpDr6x6CcfXIKkO/+
pMao2lW8zsdfgXwGP81Da3WXpXOZofGx1hR6Bzo1gsQ7nYpY0JhGKS1OQZUgUr0kS8J4vkASgB4b
a4k0c+tML9cjvdZqgw3joc6ymz0j7+Kk12Q3QIk42fHPDePfDbdebBEUp2ExanDIjQ3JjK4OGhaT
hw2pg8CtwxsK2KoAVb+YFlRvaH+3oxfpAIZKDTk4iy90l7k+S3FXvLtieJcxiE059T2oDguZah0m
NqyHiuSm/eaHG/gGxrm1NYipJQmvxjI/O3xgPirxOP6dTudDLiE3T/+X1f6Xn6fwaTpvwVYInw8c
apK7/84F81reLHxuaEKXygzL1LY1Sca41FtKyymfDa5WjXaMtwffUv8HO+C0qwmF2MPD3a4Exr2n
cs3cu9iYFE9wtGWJ5+Ia9pq0giWx3W7l6UNvdzZzSDGtCNs6NXX2TIzndiHYqCkCf0562oTmIlpo
a4fYDE6oRWo1FQdGGgFL8wyD7ryOGyzcNgpWfuZ/TTGxWjZk+VgIBS/oTQME4Anss8TPiugZcZ8j
hw9GmoNSkwzwMcnzUrNliquOX39QkEXdM9XICSi4MmXXE9QdsXr8obvjHuG2NVtVx0KnfMexzqFV
9Ypl7jeCacdrDqXm+eRl/oqr1EjgudeNboTe/Cq5qjRBVFXOXl0Fq+PG4eBjwOO4uxI/rEBWqRaT
0c8WTykVt2ZpHWCdytZmfOZNQzGKTWtglR1XF8wf38z1FklIkNgiaUipjPybj3AqrSjWLqV43O6J
5J0LEOcWl9RsRisLnNkwGzTvbEBBW1fXlmzsVJ2zcyJfdqgD8RVyL0XhaiNSBCkfD9GyDkjO8mV+
TVY0f94VSgEEKzsrTWrVMdGQncyX8xOk8B15EAWpccHY44d8nflzaY2orVUIxYZnkV296TEfuC7I
nv4zWxd1tHxz5f7HUMvYoqGXQQtoS+f7GJV9xvzOCs9uc679YqhbI2kmYVSPPqXjTsgN3yaJ7pRc
O1BHZZIHCsPSzjJY1/j1/B5xqt3lAnQEFRIFXSpa30QQuNEMWmPDRrWU9hfZZ7n1YaqOahW+DAAx
WDol5XYFmdcXOhAy/kt62/0Tm6wkBmvN5WdAQjNGg6rI6B826a5/iFXO4JjEj9VSBq1aMJkgdCu2
3gwDDaxWQwdrrZXwY/ZaIZXRrOrJoAOXuhL6EOOh+rJheSqmwjGkLfpEmrtykF7QMjIt7vOHaX4a
cy6wV1XPKmqLReWf8Mqkoi4v1StV2KQ8BJGhI3x8k+C1uqMrrGgG5KUFuHHAZZvnNu+Hx/Fb408h
bUNHeKiokVGBKHCPON8KT9ODsLvakWTL7k3c2mI+vpSANqROtw5vy/47+zOVJAu4txnq32fGQ8Uq
ezA9a0IvgSYniIJYPJNWOeLoGaCeGBsqFfyS6gAsWynVT+1gUs7nilAHavwXmJsCNs/bSorR/7wC
anTJ6vlID5Dh6pAlwSaXTZVSR2V8sD3If51XCSLGF63xvubPqyeqmmyYuzxjdZZhFyszxPrbgL/Y
j6pbDXXbE4xYWENPQNf6WKGH/UqXbPPiy+ZsCp5CybzZa7e3gZdfnQ6V+LJI6aWyYG2to5fZ+p7I
sUoXv6yr4NBYkyTsax2ziARaZjs6HY9eoelSu1tFRJmHCYfEblhz+BuhkqmS/M4n8dEWDSbOatF1
P7SxGaFDWNG3nh/DEgDNsx03dZJm3gK5r5cK+Xpmu6/Z7uNEiK6cpfFPIHAk7NE5ky9x83NogkK2
dXTi16Qi87AlhvbWtWYtAnEeJmiJjswBGdlaqhDJn7tFiYP23AUrFNdV1QnQWKj4bgZU9yrMBikh
w1LTd8ImD7Ysr3vBJobTTr1/Ekne7nHdPRM3WS5CK/eeqPSDlaoFRV2ik473ANc5bSe2yfyHasZz
m6uIg4Dvx9jwVekXjLgDlfrDSDBdFQTaOUHGQI8tOlLa35F4u/YsGBcsIo6uvzZhDUdyEbG3Rhmc
y03Q6viLmVh9yM4zN0nhZ9/dqH91CoW19R5i9I91NhVUZ70DggS0t1XpGVO7GXOmAMh9Z4ujBXOI
V5wN0cqURAfTsrEWgcqRvPKI4XSuCkLsk8xV1rgTHW5OP7n69PHNP47ENH/EHayMP88cu6xQNcM+
+dIpYL0pKQk4yf7sudqf1Ae+4w871b86k4FBvDvMLmzgzIdqBkJ39jg+YfRX0AmtHPW7/w/clC66
X0CxPGxnQXBk/51OseFMAT/ikKtsDR2IAxCIgGFmJ3J5atgWedgeS1KoFO4BypaKN5CtYqSxJFln
mC3EFyenkFU6sbP9FVCEwE8DRlzqiTfgbaXpDaPz7YO7Yo6x3aCOjxRWJCpqBZH2lJKft91pjrix
WLUst4641XWcv76SKFdAE1XFyHbv1MGS0y9BNtbJZavwP1ISS4cxsYQAtIx3wxycbKbBXjzlIeHr
r8lg1xXcsHytfIwIvlLtiunudoYeif4Y+d67OzXHN7AmiVR4E7Fz25+D6/gf3J4T31le/zJWvCjs
FyuMIEHmr6yXTWXdkIvmSKA9k9xj1JBSjd9TqzIfUoN9jBSL3ykQ7mjbqzViVjEHCuNtbTn3BaSJ
J+MMPi2QzasckyTmJ7zf0WBpBfPWuU/EHyxDpSLMptgfTa/YD3JnJR/2FuN/JLeIETYYW0MYWZCn
GjfsTrJWjUB8Yo01Cr8+3g2rB5l6Xu9hK519VKiZN6laZ1e4CcXE6X0Iv8DychlTLDYYHl08/es6
o5L3j9r8y+JDdAES0ZMCILq1Mq2KNSg1Yzt0BTE2+qx70knp/XTEE9XJ059m9PUvlmJFpyQ23nQH
AKTAIM2nDZFBBTZJPPzIlMQ6g0yeM0/W5FUVhio5IpnDo5yhi1WIDL+++eiu8CoycqZp/PI1KXr9
ppcxO6Qxr44S9CDYS55Si9nzJYQAfLgOP83Gx30IXYMxLp8MAj8BE7fdhn1NGrMq22sQco7GP13/
2GB9ktpXEwBk6bRdvySfuZ8Hgi6BcMVIrEAesHhMnUSfz9jJrN/+fGpThrpVudFIIxRBzQ/NjwaE
5QY0Fd0ZeS4ZTrd9MNNy5atnuFhF2mRggAssaCOsuhjlevaYgc5M8JoQ9LLefg6w7X7jLtFE+u8v
MtEDGql194zmZg4sdwgM3RMrAuUiGVoaE+je1OhtHhNYO4wIGBR59BtNrQMW56vAlniOCI83v59R
D0wIecWICeORR/8e+hjmP92dVrQ71Wgth/EQCu09jClmdY896UxWf36mGxYU9qbHbzW1tMvhRrL8
NauIsf3hpdwnV+6OXzSpUO6WrNIJwZHaV3QuLO95tWeLKK7SER6DELs3Sd5UOZEO+KWAQ8ahG6bG
C0cg5Q60S6ChOIUbHhkN1Vk+MdY4kH0ZtEBG/lv4QgTsTaJ21z5TWVArRE6diBkG8dfBSrcmuIR/
PBIT4ozig91bIr61Sjn4t4fEfC2B84DIPFD+aSUa44+01R90kGVf8+igexzqs1/tB7jDnNAcboXF
wIK8V1inbTQoSEsRRDDKCXrf7a/+WxCEsz9NlM7AJQU3CARIejCHyAYb2ra2xbPjYrXeTOYvxrVv
9fnkbnWiP1oK5HoaJI5LTTTii3unqcTVdZKDpunSwZXMvCS/FCZMKPmNF0hyyu8FYvIl5lyHdZND
Kq+RBgwCHeSEsdtKSk+vULZFh9Y1jj/81P9PIGoN1jpDZaYCTrlfuSSyz6KdN40Y8Fha1oT/HFJ8
lAVpcNAOgG15I8OiTIzn2Pw/8tmxA8PZnpICWTY0+tUhRCv31++QY2tROsY4PhGGtO/FA/6hUyCH
uupQZaoSf1I6hkhanjKjVsELHnGqxbCgHOqW02/RUnKgq4LerFxg3Ouw8MKEtIx2aLlXZUJvEs6e
jrvv34tWOZANflCtN41VYh2DzgjNE7J66QdODm+nzqttHYnqu7pu5bqbmECttfuy6kr0G9S0Ezxo
WzKOg7O8mn/7d3+N+IfwPW0h6Y3KbOoBLpLXIQIEV+u/DaaP5EZrj3KQCAVMPehMIDDEJZDCrgc0
ufrtSwrt6oTSgxmRKnI4oZ0HD9WDwAqUUoormQPqRlXtiWbI5wRW6UpX4zTLN/kpEhKqgNtptMOP
AMyFwJIU9SJdnwHwTp+eDHgLdO4n4R9lG016cV92iBS+q2PeAkwKb1O6dA6ezCQ1vLm76GF8TYwO
3Di2YMk0KYX4bg+Uqr2kIBwtEx4Ipz8zruwSUAkaV8qAPBAFCe4JjpRVqVl6iYe1YjkLdegqnKDh
izm4Dw8FFSvNhNnBQGfjng64a+FzbQH6tWbcpCgAOr91nmvs5/1owL2feyuMnGhZtlSDW04whrSl
z1zqgB0AuN3VkFOt7GaV6NOMC23SkAD9vP49WdIV1ah9WuDp/Afrvc5HEIZKca/DAkPlEJZhUsOp
5VF1DYUNsfNO03A8R+kGrCLAuyeg2+K5/fcaQtl8SrDm4sDjWlgsoqRWQUuOvxtgqULpwRJmrFDe
+tA3bGTh9nzkuCFTO8lJGuxxK+9QWgXvufQ9WJf3m2WI9k3iOPAArB8LU70GNcAIvYnGOMYIbhuJ
LZNuEH+zrt9WLHqUdCGvTNfPNPLZv0G6PqOC12tIQmDtetjH/MNBDCIsrmeUsdRDCfHI9uMZS7cX
FKJ8443uvnpo/pw/FAGW3UJFjYvdUl+b+EmjW3Fafav/VhmS/hTdfkI+MrXiz/FCwht64jTAPfyY
lFdNJnZU6nMkIbSscOm6/P62gU1AWrkAnyPs0QjawUdFQrJSNXYnMPP+ECCeH7YP2DLsELDwjkBi
Rm7oA/XDryTnI8sqJ8io5Neg0O6uqvYAMie2xFX3BuxNqX9T2SXr3Yps4WnK8O0yfc0aLeJTRjIT
wkXLwmKZTWcsmt6x7MufLUAs5DltPed7s1aaefciI4MG/gJBs21Y6K92J1W1bhwEPeSpMC3D9f0o
QRgT1qotbKjBOiTVa6nPoBRxync8SAgQkX/pbskGmeunO+swEghqdqe9vtMI5j8VYLY/BGJ9hwfA
DwNLMF6mztRymRGLeqT8Zl3XvnllPW3EBEVM8a7/dSpOu7IxNSFjtp0pxkfyZ/NJI/3xF2fLqs8x
CNfklwJFtIk50fRaK5DhtHUbmyIgYkGSjWUUP7RuY1YBc2sMmAnM4ZJQBaEwLLnNOqOuZVOXnEz4
Yxz5sD70yyrKxB51wlIIAU8AuPBlQCpD6e7xwB1cdIg8uHef8TMXwiahOHqDvNGpVOXmRG+4Cf8a
NcCCTEWyiMMRdwuZrvDFVMVVHsk60lS+RVJWAZdUe5HjrKnegbglJN6gFEH77y9p0QfLDFEljjsv
IGX5sLb3bBNWmd0b6I42fhdPr8kVv1QWWhJLWm4xxAmuId5qwKFylAwHtp7RoCDhvcS3+qmThJiQ
Cw7YVSkj7ztaT7wqtQGGes8Y2Abn40nLLhtwLnQdPzfiGEo2edxS4Z16/nyJU4aYY6winTb64b0E
DceJ6D6b/ePLI8RchmK/USeGiuVxn+FsXfEug6hlDpy4xrz+ywNnphJqkqZ6qODZJhSf+4vB+Dy+
KdobPJDJdj1VdQeRQ/FK+ZPDZ0HLzKjKwPoQGt3kfgJcEPRrP77ZRIyhcwuIk8Bw8deVjoAgJ7o6
PGYYaHf0VDFaVMXvlQ6ZLZggXvbXBw/qxefQyAJEN/rgjsNZ/wUp7H2BnT3WMx7+SWMgb9wE/fT2
VrRNgC4q7B1iSEj0k40DE337JnLiginPdIu5KQ3ps8Au7q3jMfkI78rdJ7XmZuWqANJ2p1gUMo6K
mdeDCqp5UQ6YiwaXJvmcuhxpV4MUCVAM1unULDYq1CGMU291EA9ga15ZNNDTJuwrdbDJ7p3+BASY
y3112aUcg+e+YwjieTZKlQzT8p+/rB9/mDwlMIqNhjAH3aGFo2CSlX7ZyE5Fpv8SrwoH+Ry4ZL9X
S4JIiD7EzZ1BdoIpl7fEuzMQsORcouNp9KRievSaTRLMJljY5mbOfqGBtaoaMzcO0+MHVrbjfK6E
wg95eSIEQAIMqk/R6STBzChhvrE3g0EyejnVVf/CWIH+cxn7+WP0jAN2MjQ0cQAljKK7Gyhi8gqH
T4bDI+9ap4yqkwNwjJDWCMJDp1kMWbAElQcpTVEbeUkvGNu/wJZj6kL/CrdSbGTMMhEhAJc5nriQ
d5lbzf3YS8mF6FZC35pNTpaC+pqjAyuHBNcFgocmvzPCw+lOETgW7319aXVGVu0l5H7BPz0n1899
ImwHHp4W3KV1MAj2kOH2O8Md82a1nUbgv25CLHtY+va3K9M54ZMoPM1EGEdeyJNK4bPo6TKodUn2
7xMPTtMksr76CKc/u/I+okUSdRp8kXU2Ce43yLtArT3BCi94YzC2kxyE//cGv+PA7AqyahYDUiRP
8QsMFgGB5mI+PZm9ewQFT10IfRQSM6Z3ogVst1SRthI11Q8f5O1ReCm07y2OkfXM7JU/B85OoRJd
J77qDNnIvIXHTYUqT8iEUab4DIL9Dj6Zlzfxvx+fMvM7Rt7kDrHvIz+DeIwWX9d4MO9/fMAfvSpZ
/5sKmaePFfwcv1c2USVYPZFcdo/lUomAJvuZcwlsmOh88ur+WnC0Nm9Gz+a82qQq1NV1x5ydMytv
Z8NladOKFVr9HBa6ZCg8sj/Q5B5dY01Z61Ufxu8Jfty7CGZe07Dkf3WOxLhbJmyUxa9qLsCYZWBU
XLd6sv9qsvCIa0rCXpWDM23yV3lfcdqORu9437b6h2OLcul71YAVgTv+fs+7hvsdoT81YJ/HRFv/
7yw9+2h6PYle5n6vyzEpI8zp+qdv7Oegen3s4lnXgqgOUiYw6RBAd5QsTFFs7x7NlhLD+dAUudIG
xr+6A0EOFAkOW0k1uLOho5gHV3ENol1XK6BVv//ipr9w+PT6yapAgXPZSNJg0GvVWHi6k3M/3TBf
73zgMu/uKnmzDzbKS01eH8qqJwum0zVUV8vXqDFjhlP/LexB5Ffq4S6vYWeI4VsFAfjRUfOTMeKQ
3kUgXsszv/xxHcJKWbSLBscPxnToxS8+cPi6JZ/iDhxud4gKjlaiCdwZ+gzVv5eWhTSpxwgReLQq
E0f22mFkP78EBaG3rmXZsQRF4zGIV49rvcgdRBxjHySlQHzy9tRuMTLQW9y1djMI3Hv7U2pU2i/a
a2o3YHhd1lmxWGGEDegSBvhMUeUgEDTpPnl+ACEShNpkVJTSpX3Bvnc0YKXR4/ZU7PX+vbCkr8lc
4m3diWmXQr0uxHBVsDVa8QzuB9GlsFQxrf1LJW42PS5zvYZ+vRRx+/hW04fAyXGMoTsiKKuz0hg4
wrX9t/Gh7s0+m0GkqfKUg09Ka9Tpr3iXEyHO6YQY1+4is/zm7UZNXtcI7BnWwlQhNB7uTq6jzERM
PL7+82JsnScH418sDuGOK57rBZoLB8KajHox5VjGAkNdPIpiwq/zOiNLU/QbKnF1UK1MpMbJx7rZ
pOTJ+B3SDVVmZde7mCOlJ3IyBsM5/UgR3EWGOoHmCdIAW6JxF5dg+r/3InSOk4OiarbDwBgVts6G
idIPVHWjPY4dre/sY8a4cBrCRzYNerMFqsV7I6jRdVVuaUBWE15Z24Ydr3UQSSEPWSuSCXnBKCaB
rQWhwG34ccHT5iCml6GklQIky/x8mARbsfFwlsbLFTJF9gB24ml0osD4M+Z7q9kFbqarxDkCa/ZO
9mbjty63/UTNAzuibFXnkQiEK1O9TFHKHhTbrKwZr18JKHEW40x5EmxY/H7OI+UZG5WfyWkuqn26
kirjyVfBQdyQkphqQL9mKqZVSyK0o67JzasznRZaiINEpfLYcUgRDxFCPITST6UEe7EknKZlji2B
MuYsnve4qPemDVOV4INbcHNbqL1Fw59f84U9fZxphkzU0YsLBTIPRMzm9mn3kOqeF3RfyzFvOZT6
jTQ5Q/VndPBPl2EIEudqmJdOcdCNMXkWVbp0rp6auGmVEzTS8ic8ouivF9eT7zKUdUCniiIxLELb
VwgnQpMHk21Noy3giSQTLaQ4nU5pzG3qQGywzA4+hVXdQ5AINSyp4+DkUkRFlDxF2GQ5CbBOFAu8
2RWcuOcMkJuCroKIbV6eUPEv9UFgNi5RqjBXapctZiEac7+ZQpNEFx4vDKqcpE7mkLrig0a3k7g9
2KYeVNlED9sy1ILr1shrqA7J9Lv1h0Uqua/kiKrd7FjfvHUCElTOkb83Ea4IGxhRWa/RzEmICnF2
WS59O6FQzw2nC29nBmi1RfkeemvzLcgwqrmp/5GkaFrBS9bZW341aSHPp9B/QxxT7DDhwB0ypK0/
5dMyAWHS3Mkvts3103R8rdi934h0UG5UN6KR9PzFixo2Mjakp3k8EW47M0unqo23onT5ddqIIHq+
4KlE54x/diETv6PW6NV3lUh01L/khwpoE4yp7rLqh46iZFwpe0471MIQb/CBei/4k5KRcXL5xR+F
S0mjTkIVC4Y/L18uLmUEmmTdZoALPrFzBgmBtTZOEt587ZYhBn5lwkAabE/IChTDZoaTD4Qhdw4Y
HTABo94RYB5bbz848mKExD2tqkp7Zan3GY4hYWWJA6XWkmbOKpJSVuu1td8jxZLIBcJkrpMn+iOY
sS2/D/NSy6jaT71A0B/EJ7TzqCpLUkFL2nHm5DfBqvq/YydXASE3ZquJYll5tzHcPAKjdrGAdjS3
mNq6VFqCN0vb2I9TvyYyACsVz1X7gkdFKtv0g7QOe53m77CaEwiDkenGDcSeDfHx6dmwvA==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PCm2fNIkeE7RqN1Qh8aDBzSz2JZdHrSd39tfvplEdg301UYEYTYTh7LAGuyNl/IWzVtXy/8OLKM2
jEsukhpHyQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RwLRXbOkAb7oBKsdG074UuSXcADZ7XW9e8TFDepVg3T5gHDHlCoCkhWq9htKPblu7CdCqhJ10k/h
vm6kCixqzAf7pRbi6Dd7yD8JkHHpD/JoCpG0CXkR/YkwyGacxzBT1e81vN7QTqojdxa7d/QRyQC+
MewlL03luvuOMVsoYDI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ig+L+aUsv/EyA85z3weCZqReauEsxoUG/dQGRFaaA5NTQinUnMmZKRSCqwqjwKHtQvgCVcrj39nv
BvmgbwrS287dmW0ayl0xVJH1ZBO4m/r6tWMGBH+BqwvlJuYzwDq+XuaVTyGzQsJQEpn3gOGPS37n
by3PiEpwE8sEJJzLmjC0P2WRWiChNAhPX68xR3rPYA1v//HykKkOMZR6FxpbRWStkhoP4ZXtekka
MT+U1HqIsEUXJ3yu9Lv53E1z+hITgeHqLQuoHDZxe/vo1aJp6P7bfmUYBqKcuhtfI1+q/ROLWobm
dwK7BAzmKU9Op6712saAT0JuiaJqDfbDYUHO9A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
lsIBIwPgIXnrlbB1KQUAyK5Bmb+zT58EQeCjYseHbFK6kNgAjElBgxkvBKz1ldl+9Q1yKo9moyZ4
0HyIHRAHS95K/FmwvZR8HN20nLUworQZNn1ZSc4snrj+MuW4LurL7+bP+fn5i/mEoYRMkwf+hLQ2
pxb0CiqXIODA5ZIP5pI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
B4T4vMluttJXNdEAWlnoeDvXFlnigyOiQxAptjffGiB+sVVUpeE4ItUuQIRNPONjqpFlyqMY59aT
BzHfGmB25cZxQOUUdyiY2I51XOBeohLT8+YNLywsTYYY9gjqJGsNoMYGBy1/vYQ1yDSpY5QEuAHL
HcpPLsR9S/YaklUk82wT85wlXBEbo3w1EX2jAIcHHgFKDtVpBBrxw5WWxE9wckGNsaRnIB7WuvM6
U5XE08mbJJz5+nK1bcsOtBfGhk+0ZjdLIH5Pb5sAhVUy9iyG4VfJojcINLmFVH3IsTL+uXTZoTaH
qqG9CnqzsOurHX7xzG3E/qxLQpSyspS9D9m7+A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 49984)
`protect data_block
mEBP0ABPAZMGPygBZ+3A4rrfbcXqoNm9XAESvAWSw2wROhWE1vjZcxWrmMh980Jn//D0gyiz1zHQ
yypszhP6L/3y5GJXoUdl1yQM/8cdPXwRLwtCSeFQSGFegp7gvVbBnYY66DE840VClP3gmYfvdfsf
1/lKB+Xngsa1uSzu4k3q+TpXHySJBkRXpeWBgtX6LsA1Xmn1A0bZJhlD5cmxneLqQnocwsx1Nr/s
+iEwH9W+5VvEM+S951y0F8pYthN0AjbmetzsKxqx5GAYYXf5zTk9Y1QUHsV59QfBUCjIPJvkb3Ux
z5dw/py7kykH66Zx3muyyQ2w+FnxR0fQVUzgeIphIIBOU9FhL1OQXAg6vHeW0K8g3tt29xFRJGHV
R3b+uESIGETq8FLFR7H90FQbQwxYRcXG+QNaBd0N0c9eZL8hqw4Bv0mkk9eo/zGufpkVQhUf+9+G
49GBylNHxrPjrgokQTUEmmGvwZ/viIsi0kv/OXHUODXOZ655XfAjcs5JLKpWGGA1n0TNEIcrMb0B
U7JMrLpPuV2NCH/+yWcyRZF2Sd/IOjxi7nHGTTcxs46qNJ4V96YQk1jZyaMLovPOHNXeOFomkplw
KnlnvjkB47WovM6h6fPfOXf+srjhIvd7LH556cZr42oVUCYKWQsLM8+4YfO/QCidGudZtYt8Zvpi
i7YqZufjmElH71eMwURSPaYKufTN2+pT5uavdsvCcNpoHU08eemyblSkpZGhgdA/7Aq3Lan3thWg
7Fe4gY+cO8YYjNhh7DeoOsqOEOSLdVFYkJGslOVVCQKeb2RUsDL8F3BHfJAZjr68uCglmL2zIhfv
4VPhI3iTT1x3oj0QtF1Aqc72FPPDmpQocmsZMplQcb9qJUFSw1dP1hZ9BhTLOlgGuEeA/5tXjeVR
b06ufNa4aqOfl/bflNrauxN7aiV/nCvVTMbrgagVm+Egk9ve8UH52SBoMU5vhfxJ4TvgPoZ2cP6s
84rBjOPmWhSjoQ1HQ6aso3LbQorkIKwZxHN9+tegEh0YdPLK4uOu1M96bsbZ68GBJheC42WQ+N1J
s7e0fIbe5fjlWslTs+jOxyjLPTAZGR2zaQCE5tNkPn3hvO1HNkExyDHMZE9McXnm0u54gMofmSRt
XBcon/wgOtuYKVxNux2KOkbQMJL2tJT1dUGt430GWigYeK9YAPXgS3Lw0UjDX9jOFxFbhO+lnw0M
BOD2/1/k472EiDAa17tLi0ubeIn2+vvmRo2voq5dqWdIMKLwOV80mXhZsOIANlCpyZZNRGOOOvpw
PHQN4bW0uOfqKZ4Xa4sv5/JrBCub6Q4JVnidDW1SSrn+X+93VRbDQHsIVIxtUaNPmMGoNmEEK22J
LhuVAayTR13iVuICrLnHT5qhqqmYmsUlHF9IAERi+IoroJ7/lJBcDPeRzyVW/ma4bkD/76QoZ/6g
iCxU+ATOZLZnfQpRIGxGsUhTAIBKEUUB3y0dlet1OFQl+vp+/zIAQFgWDwewFQ5E6nZ82c35+ADZ
YBXFEt4cxOxeW6Z+iifmAXd5D4W1VR2wYD+eW+utHqK8ibHBG9cIKGWrcVZr0JLDTIr5aCQBr8Fb
zmXZuakbpTwpQJSnSp4L2u5U8oG//VRdmm8Fb551zOlkN6YzC7bWMNAxLdhrp3KngvRe8S3YHvWN
hQyL1nrotNxkUQCwm/J7loCAfWiopX1gWH+46cjBS6INebNu/+FM0EqW+3Cf6eUyCQIMzliMUAId
PcqSukjT9H1rvaXpZ+JWmckm/jPn2mjDlHkWviUqWUWKHst5J85oRg393M0BI1WOk++DtFpYlkI6
CMe/vKk/i8XGI6qr24bu3d9JiyPLkZh43GNw32eBVEM8SSwDJdT67tpcGUolW7BvZoXOjyz4z1PY
/6WZkYW+LZKcS1ldQZKZsVOI1jq/YKsO7dJPuPKtI1dMo+BO1PKpJUGIelLznSF1sUrCc2aGeT7x
bcSxlDNwyyk9LxCtKX4aOJDg235m8nXmGwn3wBoJYGRAA0iYJaVehAKVbLrH7vlmMynoRvNYVgf1
BZcgQN+wCIZolx+RV35UUrD8vJj+MtJ30napfiAl4Fic5NjmulwcfcyX6FuL4lWvQaXXZ2S8QIVP
uBanJKj+SpgEglmlNJnEAbLwipubUTH5A6w50C/gAONIQcLPNDdSbH/ouUsbRgySSN6mvW/wv1Qf
4OxofA93boSVUQMkjYZQtPk6YJv+sjp2/rpHUAGfIxBsgRI4qlWCx4dFnizt32dOU9QV4yLvP32d
Cu5we3wWPvikND1c/6HEexHz0aObITN1Vw79mXrHl32mEbNGIxTR5Es0GDaC9A4E/Ke6DekD2Uoj
kmT51MzbwPCr4g9OaBQH434gGFyHR0MJQg4OrGnGR9cXgghsexoRjMfv2t+iAn62KqsL2JMow9zc
rOcEqNIHPAtuQnFgl7UzpUcR/XwdkhEXTJHtTJ5b/jvjzPSlhns40PpKm15xdNlQs3OSzk+AnVlV
58fVAQjwmOp+6Zgf9G0G3ZWMXLSHvPFGRmhMDRyz9WaSWvRsrhCJC5ire9+q8UPJ6FkZW+bd1gPG
1+yQEjDO7YKHsPmqevmEOF5dSzxF6kV+Y1quM3AZXzEnFfKUc9P9FkQio9Ikeq0G3fx61h61c/ge
ShGRjpPUE8nQ6cNknkPAlCthCYprbQDT0wGO5CbtbasQR1kuwZwFIHjJk5mmw7Hk7qo+m6o1IXVS
P7xbouV0ffTEsAt6Qn4rDPy/uk06WwHcZ07mOmPKwFRDYS+aQioTUXt4AAau1DyhTKAdnnCsrjEO
03Ej1QDTxWPaAgCW3WREemu0l8szGMTkeHSTLHebUQSawFq/x1ZRwlbTW5mof8eDc8IjHvBGn98m
GiRKC9ltxSmkFKeifhPflz/wquS8dStSoE1GhF5xAt+sYG/DNx39srxrMNKhgjnHc30FXlR2maBR
uajcqBYWafm5Q5fEo4HrhMBC4jYsrpw0laJwevWKmk6qbuzdi+RxD39D7sLAhvgz7cr201fe1cRF
PnljiZ2LC3TPAm4CLAXdwl6s9+FU2B04rhzpc4z7S9lO9E+PIQxoxQSOh23rR5xtTly+xAF1fNVA
9nAIZ8q4dR2zcXSgRNWW6m8IePSrWj5MoiH7KCA3q3QVzpLMiwkJ+GafbOchw/PlM2G+Tg7qpMD9
zdOAdLhhmFjx67zRUzPvvLWWwWrURfqk4Xlg2Q06kWSpO8M3LtAZScrgt9sU7oJ85CcRgvw/maWl
EImhWb65cxBKesP21SeSSKrFRoqwVDPCSnryJlrX5h2mYMWhiHTGDjqHSVS9AACSZNdmDGLgIvgS
NT0iiIg+a289GF5gTRfRTT8IMii5iBWY8OAC31gsp4wDyxXbU7I5Ydiooln8fCBH0N4g/dXETexN
j0fUQ3SI8x9lBCvyJasCUpNIFlathv1kF+p+210+XbaXKXSvxet69rfqWJKyCZyzDVDH9SW13rA1
nHuZ4SSEH6pLe7d1s+x7aJrl6Q8j0m7BfudVmOki8+vXmhoPCtZQZK88s0umzlQJhU6OcVG9+cZU
azwx2RvXGCo1yLi3d2h8GGXJ7/0KbvOcfGFu6ewEOrHyLfGHYQlKPgK57e0t0/731ImweBQl8nQu
6vPER4eJCubBqhRbPDz7cOoNPsRzKSAJIOMNTwzUHyV/2Vg8nsLVXLmbmzqNcULpxEWNwWdBGVtg
A+0lmeLyHOfXUO51K6FKNJH6hSWNJryjqqgBQcaGaTMXu9WWi+ZocTgOplK/0N1crAQW63/iEmMS
AG87ZsL9C58gSKXJl1fFrX0IK1vdSe5tlU4HYtHnYt+BCVlTUHdAbVxIdts/q3KBo8DnNcQE90qE
M/gVaDAXcSKMsz9Ci/zyBjvUTDaK6GpPMlSoUoyMZMjuWxgtnnjDQTcB6gyaVGFtghnqRb/jCVEO
wVryiKYAEfNoL5MLMQJc+pYrfrSdtRJDcgE5B4LkgLmlkb0VDZii/nNBrwr2FKwvIODlx6vrvSUb
UtSjasTXkkAk9JdpW+fA4/+wM9LXyxG3iGb7bDACHWVuwgfm9bbv0lIAXkqzTaeRoPr3+iVLZWmZ
PIn63gB5FODd+KF0YVKXt/59VvqOnBZwktQlX4YJNnh2ohbOgaDD6kU5d0JwIfJemLE35oCFzhh6
BeOcG617ZbdI+7nvlF16HLENsrVlzLKhJNdScSf0PrVdtp5ZbPzZyH15XMeakkhkk43QeJ8KHRh0
0GG3RGeU2a2hXm0jbYVSfNVup4Vb09NPfd21WqWq9Fw/jwXys348AQXUKnVWDhTeCyuRpiBxlo3b
DsYEkpBXe+eI3cXJ0EPaPAZEa404YyIYqsiYTM3/xozoOtK1H8/+XC6yScBr4bOzAh+WV+Phrrih
9AXYFhTN5ZnuRVWCIPeNUmTLfEegp7suRYPnn/8QCU95nOv9A1fawxXgVjKx95Vq6aWRVSWGeowX
/6FDXkLqChsQeNCGGyxOihQtv7fNBGIgUB4wm0Ae7nC0g2GNC9kTMkBVCX3vZrWjmcGG/zQInJTa
5UoDLYQtBkx4HzCQxrwf1TaRBKg7Wq4KQBoYBf4ecTKyrLDlgEzYg5phG+oLsMfj9tcOiKPGqm2P
DGPqpZNIoroJaaA2O6SETObcnHGG5KcKwdMLnJUZ6NUWuTdM7Q/rkaybqHeF8N4CvR1ekKy6Czh7
hJFYTYx4t6ke2kzI5S4RQLZmc72pC61rViG4yVywcSZAGrJ/SniNr4NhlzUJQmL2Vjk6bepHOwWS
qr8ItNmtsEeAj48yF9F5lDO6l4sdwPHOE/Ts4mne4NfMjTw4Gkuurtr4o1TuJCNwjw56nHzG+N52
Yb+if69OYWkPNbBZr4ADqpq8CTzZFa5QnsNrfldmKllMH9cM+KyObDX35SQ+Pini9yxLJtBgILU6
nocoL7/ONYIgFWFC8RBbDEzbbB1Y75OJtxE8EkkBjvscKGUj7krtMwhFDh6WoA92JCTuYKLG+ADQ
PUP1/0fS7rNQZWNoj5AbJ+U90Jy2JggUzwsVCvdXxoig5ekG9nWqxH3yQyNr+yKO10UNikRoEhuU
SK/lOuUktSq5hsChM3rI9tzOwkR08Hch6h6UsGFHgMMDW0Y645SzUy1JiIuYi2tOqKV/SBcBUcSE
fsPhJ74i5Wy5PX1YVwgVp9Aepth9NYY9tQVW60fMWItWa2DTm7Bd8EBSgJliOn3IWigSmPZfhchy
K8yIaabox5luscAXqM2trV2iI3yy7/vFrIfDzIZHT6z0U6gSBeN0DqBtNREkIL/sYAEK2eXc/zDx
ShRhH0kkNalb8PYuxUJe4o5TzKvrEAXby9B/TcQcvDgX/1/EkNBVQSsBBxG9j2opfREvYI5TDwj/
NFzHyrvPO0Ykxxi5Up539MEfxhsn07FdEm/e8NIAWHJf6E6WNoonvCNquTGsMgDGad34Ba2LMo1h
fCpGOhJTsc9MMhNgNMPz2v9fkZWXBvvbycYxfReN4ZSZ4lQWUBvbFaw/h9PKdGqsOxXlNJSbqxAj
DPBXoLUFQjgvhFkRtrrOgJUeochtdXgpB0hIhXcxTiGdH78aO+LdSRHWAiM2Ky8gvBiZWg+k2ay4
c1EEyB9U3ClVuSKhVt+WXxW17bLVYKdYhqhCsW31sNzmy0tAzwRjPmr+I/aDGuH3A9TOxKVqqKTE
W7Qb94X4YGJJxsnO8QSiOLzSVgxupVZw+4/HBJ+G4YyL6+kDbO6qkOVVhD6SZEw5dl2te/ZrSari
+Ai9nwhrfjal0xekmwCQxVrNeL/K9HWCYw6hJ0SUccVLm4BaWglqKQDgHM3KIaLwZjdM5YxQ1B7H
iX0yIyt3cmiptWXsCLMnHn/STH0H1KWyKAwU2VbtbfUx06vJCGN2mkbNccmrlLfp8Kkudg2h371v
FcHv3fGQ6KlsYXWt2J6x5CBCjZBouOq6X2gRKwJUfBPaA+WvU3bHUsmp5ut+W7G0b3r6E5smJ47A
s7QrNKw2wpWBy5CyOZZ0c0yCKt/GBofjrb12TrjbYQj8plC7fzyS1AxzXzNb1RsAlbJ8QpJeh5M9
gTuLKigY8odRWt3z99F1mMbclaS/JUIRvoiHK6mOJElT+55uF6ocKoeAbkSj0fhQLvD8ucG3Y7ob
OfBRIbQ5Gd6/4p8x4kqaeX7lRJj6T7ScXdHhrLuzBD1JLA3CaiXsSgfC2RVNFLPUQU7fhUzOve6T
1DLt29whg83Ve983H1F/DTliUItFVMEgTVfxY2XTBjrgYWlQUhxRvYSUw3DIcUF3mkK+DuNixpFf
mQPZdnoslCiOZnxPHqJGXu//Llt0FBSUMT+/sKcqgdOKsL5WmZS56DAhkxW4xAvhEJ481R83Hn4U
jBwLctI2KS2xS1mwrBtFZvavljU0u1e1D5blHbzmSZXvww48XsZz4m+7sYo7Loeo08WRONzWs3gW
zvH2tW/Ws7ykztRpY0/s1QpyeZcwaWliNMekisstB9mv+4qE9MspYRFLrX44CVKw5UcP+cGdl9Is
R7ofvhx4IFworkq+vyjF1C1YqHULTzq4xyiYImsD4gI7KKuiK8j+GshAtYzEWUFMl10oeQe0swZS
S1HvtOs7Wd9akmqWQwkjICDUNgw9OUT9LKUO7K8UmIZpl5tozBQJvS8T0ztcUl6XBswHkx7JFXN0
oWxEqeePYC978n/zajWC74LDXxfiR6VUERTADbajEjYwyyEfj53W3otHIF6h/k4So/c19A7ThDTr
0pNEXINybhHFJXX24wte7m4VeMZJvknyeHpj2x+1cHphr+Q8wyTV8JT6IgvCbsonB1LyfzzM2dC2
p/etF/M3cZQHza3N7ZYA6VqaH8qNufPsGjsNaxzbKAq3m4zOve0u5fOhZmbbtxzwIvCxQq4g0K5h
zyVdw1NuLpoco+3p+8n7ihLAbBXtDFAPC3URfOW1Feks2/s1YoFdGfcKpkfbPz2F216ofji9lHxg
egx+BhQDWi0IFr4p4Srzcgd8lBThE1gFeLMYjfbJ9rao8VmDk/kAypsJz4StC2lFu4FlPQjTpN3p
KYMPyjUnfXhEe6MlNXIr7ReFiXLGDCteLK/lsRBl4fNr30naOR2N92x0K0w4/L+lFP6yhXnt6hYj
kONaS21rfBOx0GMGpw8jE8cjyb29GJdjc4xk1kWSTinNXrFEIur89G5w4lXvqHbPhe1+vEVz34fj
I7z+081LEYulZeBX0lw+ch8U/YkKjr6UEHHXn7ZsCahlBc8x9DiUZ7Wysm47Vp1ZQI8A/UTCHUnN
061xR535tMQ5yEGd1MJ3qMz2d7L27R6Wq1JKRL29zGGVGcxoRzfGFKMN294aUTVqBvmxQoXx88QO
IB2ytoC4Ajp1dwl4s6ePu6422FCajA1r0QXluKuLv66FTOMxjlLqkKd7zfkU3iRWdgD/xZNX/Dyd
6XAiRnQcza3p1F9qFwI0SCHypM8k8SEgngtMPiaKjX4gzWodN9ORLFX18cEAU7csybSDsFRMnfVp
E1xa3wVo89xZWw7lfrXjM8doH61HDZvKflpRmITwHG12kNO48TP90WY+T4o23Wg8LINQGKHj/P/2
g/eJMr5Fmjc8cVJvGXLJ2yvgfRmq0/crQrQjqeTKjUhreMb+nb2/xeZqP2c/aqpSvA9xgEQulNcA
IzaKpy/Qctm+eTGeBVZynVP2M2LskhBBeroIhy/EzkTrE3bvl2yaBJkM/SU0Zp/wPiXUCksDpivz
41cm1RyH6eP8aJp+A0OBM6/JLnECjLg+iYSZ1UxSrVCfBPvk5zJH1Bt+ziC/u9c8HqH8ft/XdRS8
4bKmJ06eM9VtIpIW+ZF0cI+T1YVo69sYWrkcfLyHdzC3rlEb8Dzm/gdVD26/9MDgqiVo5lIq9YVL
42vWxE8HarcV5HRo8YzLKr597xDkZM9YQdKff5gme/ECWa8pO3p0pOCtxdRWpIvXbV7ECXSUyRTd
mdWnZ3CJ+5Tc8dJ2nSHmT5F/M2GtSZ83Tc2TmAJK1FOW5kvoJDIZSg1BWhevYB2Tb5dAo7QW3cR8
WZ0mko4ZGgi530N7NLxsm8KOmQiW361C9l/ylUhy4DFhPNLhzyZP464xKV9ihj8ZGcEX06j6ev7Y
+oMz8pqRhqKwMisQsj39gKWrhD1iQ6zEby7b4OAFZSQzVmQhIeppJrtLjV21/VdRMgudSFvDjo+E
Q0m/bQV5oREXq2dMVfmIjP89xJSexpSu3RzFJqeYoiT2d7mVkZAfGmFuWl8HoeLKiLEYwC6GPPdu
VTpPBSO9O+lCC2WNRC7YOveWecv/kXdt3OYYHUCnpNvQtnCxswl1aUtwFwvdnqE5KtrReAFzIytJ
mV6I1wNAEPOFdPbaBSjXS70Hg8tqh8VhlxLf1s7BVLkieyOwXpcPowhYcJJ2Foh5zYSFmotL59E+
6vBR1FnKqbc4diqt4Zz6ULVa5SH2CeJFs1wfWaKk/ARoI5nStrdZ8VquaYEH6+ehwPpyeNlx6faY
pBgfPycVvErI/BvrGbKL8HeaYiV72JNix39x+3CG3r178mo7+bHeSRDYdsztaAhD+Re9/hfiB6zs
prVG7qX942RXO0+oUEoWiXCQdzPJqeAwjO8bVVrqL0eTaD0OBLZf6EpaaXoqz8Vj7dXPUdyBu1QS
7p8clsnLeTDrBSQWqArZcaxXc5HC09jSm+ZZCmERhSJucNpoAnSj8JqF6f+pOrn2HbuH9XcopYgP
08+Cb8Y0a6WhYo2lLbLFRQo+Ufn+ypeHIfHWQOLNW4tmnIudWgkUBD+x/1q07EJaddIdTjuHLcK3
rIks2VRmIQIHqizDLWufkxw8Ke/LAKLkJidca3pGIzTd8MgaKqF+ZmUwVJSRq9+l3+z+HNmvfxwV
RhSn1p590xyvFsJCAnCchoDasvizsgNpb5vvuE7cfT8fFyEsmOoMLS2Zg5xldhQ0K1KagdefDIr2
K8ABBoeJJFKkhuDampKLZMo6Gu8NF7IsK95fX8hRWqmTCn57diEu6ZmYZ6GXwW0MASgMpTDRrRoV
xQaCQ4YxRMQ/LJne4V9wsjTizU+8Ghq4GBsyNtiWAuzWWiOTPCyHh1mv44iPO7UTD4SLMLIegrAS
goaoHGTTzBVE0KtmEjM4RtOJmO/uEDcoY+Sgs6biO6aIFMIAuQoo2EpAEmeoRIkqRdcN5wPyRLL7
Ea0it/KDqn663lcNVUwOaVWM8giobK5c5Ynox+U5tUEj3RijyiTwEK2ijN2PdgQL4MF1kesctPL0
gIdrkPkacImrovmDtsyRgzQn5ivJeUR8VL3WA28Jw6Sl6/OM3NPf/UCWLPuiGnvsFkoAgOc9N31r
VxBGJamxsVhDPkj3bTCzoEvjaHdUJTwU6dU3pYDHhzWPG2lzSRltclBnQ7PX76tdKLiBhhHvuBEG
r4Kkhh2jQThNzeM8sScsyebLNrFm20iuRGuuIjosIdsjjnYHOHv9jBU6hOnfvXvaVlq82kn6HCCv
1xca/TDiZNNBqFomg/VUgHsRyeg/uJ2IBRdV9esvvc0IJGrQMubmnsvXgQym4L+41gxv5nzWjhnN
6pZ+K21bv/AgPSMZkz1s/rrIbWBeCgjcoLv82VMb4Js/Z8PotQTvbf/nRcXM1Ad8TpmfcXJG+G3+
vl28Ep2SgFU5o5NGxpxPe0FKqVScAklShByK5j3LhKbsfp0ELfaCArLS8pdXi2MJFRwgG8TIrpzP
OJR/1ayiLGuFH5Wqj7FdQxe1tjPeHcShuzi5k3S9zkQk3PrrGZOJSFc9P5A6hmBly47hfZW5HINw
Lg+uLzQqeQAKpurpjxqQG0YRu88tlDWLM+cQmLd5JhyG68vCPsFo4nGwLvZemuUNFlBVskt15hhK
ZqssQEyxQ4MF3PwY8saKUBe9ZE1AFMo3tv29DfG8tn4Moa16o/j0FQjh3jkXr52NSCJGvwROjh88
ZCeJ0PB7ReHEhopPhRt3NPKpGOCaft+otB0Ez37CwB1Nr/vq//ttN8nnJ/pMQ1LIIu5ybYmi1MRF
1umwqapNjQYngZXMxo+74Udc6Vx9phOrdXw3a7E7f1O6DBlIzfLvIcO2nu3kqK6Ok9LGmhirxH+z
ZPNkDR+9Lm4WCcjZWaFkzqfszfdtXpj1Qz7ac7ZXao1uMOlFVsraOuzyeFsM4hCMhVV0aTLmo6WB
JilyieCmNcMg5Y+bv4tcClQNK58tVUGLyMpHZXOlvix3vmw7HDUyF5DsUmqFbizMv1cPq14BO3iq
/2B7P4pgpkfoYSIoOxAqL/RfKHgl/l032aBtYH1YcmBn/d9QbZnu7JnuDQ7t7zdK5Hq1AFEm0WWM
AMm4L90OXo1xIjYDy+XBCDlk70OU2N9VAPRRgVKMxOFNrE1zD/YqQHDDmruN8CcXaFrZ4wjyUFdr
KEtvjqBpQktU7nK03Az3eSZ2pFlv5cWksMFV5Qj0TtcrIvTblh5dFvjHSiqKLQydoEy+33xLzllS
bWi4elZbE+Iv5nzL6cs5RBdXiCpBtj2QLlJr59GC5G7aejtSQH8CDsIVvILzvqYLi427e4+T523I
O3Jh4JbPc9G+EI9IBRNgCIeK9IihixRcuDHgYQCf/+sG4rqQmXWzeWLctNHD7tDakN7EOXfJO245
sc9yhzdRkfJx4RnocwSUqlfjV6vlJjtiK1/Ze/GeArnIclSHt5+WvdDV8iI9up0S4XRHdNO32hYm
rHuZYdykNPlz5Q7MwprmVy0TOWWybDtdyIGM/MBKrwQebT+yZR1V/oNw2gscOPmbd6uGj0qJgwHW
L1hAQRSwdvHrz7gH31B9xgq1V7Lx3EYXA1iWkXHH5L9qNeae393UaCmVTOq5OKpewD5+89HY3ATg
Hn62YzoFT5umXUukxWNEXE4UzyEXBc0rNhgMIWc4u083nmuPS7DOYxfmFlg3odraaM4ggW2OprKx
I27EC9UksQ1o3lE9Cdhsz2Lf6u8haDj0jiITWtQupPJ28jJkvSoMZS08esSE8FqzLulu0fbNE8Js
E4xU4RyN6ilyRrhh5E1BrvpPzB9ov0lCmIfh/m8S/IdpbWZuN1NNzzGpv7G4eudoZmvU35zRs9yC
TrWEVtGpPlCt6Q0D+GkW4snnkkUl/vjSSxofjTKDVxrcn1dPZVqp8U3CJWvvmvlqmVQ1dR2lOv+h
FI2GPuyxwin1UHX4muJK+jr0NfdgKvAu7AYIKqvYUW1hJtM7RimuRMvuilB00UxcsTjMByEKECI3
zl3YG/jLmIrAKPKNc3CYu6nUT7jg1mXHrIeZuWcbQpzudYvB71FP0Qi4U7shzCEy7MP/y96bINYE
WMQOgkiPYj2LU3uuKhoS4JjyZ69fwCQHF6uhXbbsfFJ5uzbHOWvsnMeBv81Xm9xdZKKDn3xVToXH
7MsDebjvsb5PIElSMWGMQsUCDfUoYjHq2nfzsEK4UhCw2KhEExVDzrFoE86Hy0cfTpJkRD0RY9dx
BDNx8xkhL5g+9dJ2fICF8qjMHjYzgPJRqhsWHl+1AaAhDk7SmzBxv4I9W11hj+QOVMyV5YZj439V
TPvZc7Do34k5klNyAybvs7ja/pYa2nxEZeT7tIA2meeEm74+fumegP37D40PPnarPV68Smmr0zBe
f/USVGLz+vD5lcnG2ND029uf48BG0lOinewM64mN+QbBfpS9hSLc6/ZCmU27z2uzbFQ/3pw1a+D5
mGCEEV1wA/vYagpB9EAGoeg9N17tDhlZhaEo4eCvM+T1TXFKCjlXQWL1qcfNwDldQ1vpKfqUCaAe
TJqmPoZ2XkARKCUfVj/cYSnPmEnofQtegALmnvhPO+VJZP+T3qSr8v8+CsVLGSUcYa1RJTCWZpV4
eRno0yPtNtx4fvTuRXieM5UBvpo/R/N9D6mdh7tI4oR01aLfmXMDTMOtI9XFbJ6dvTsp/XwP0kE3
r0PiujZrJVxO498mWfLuUpIdu2vdVTR/KBoRXy9LaoSSWIFH/ZC8BcDAv0x+ja4QJpZ/HDtlJLHn
s5diCog8n/Oy76RIz1cEOsCwsbt7CzwZDOvxeEv+YdfPJaTzEUY/8L3C/ZyhbbAwHuMUOyxFfbvd
aY+msyhBUYtEgxtvTvsqySkao8ZtC0bZqbzRswNTgEiRXC7gagmViWuVgzners50ssbLir9HOqd3
vIfXXh8nC/ublxhi5o9bZwxulay9R6IgmkLh6PLjzk4DiTqYqKMDFOJet8a69EBTUhjw/1ehuT63
AA6S3Ru+QdD9mNv70oFPWoJMJFOSzOSSPxYsQ/0zUUjh510m6HNCy2TTVRyP3pb9n0uh72NkTNHq
1Ba8XH2gkJrUjRz43QuOgOYVWcX9lxshB5g0ecysw82X6TQKaet9FxXatr3V/uQQMD1u7fSqdB1+
V/t27G3STz4KqSdu2ghxPaGUltrhtCSXaceGYAEPnFzCKl2SJjz1f8yo58uk5bRBH1JSzvqRRgY1
B+53aZlRQP6TkCGLkYMvCBj1QGtN42R9zmPH4rwzyjEDG1d8QJ30mNcda3RpNjbk5DKS+OiCYm+x
jk56kiQW8zOYFjDWcGqtmcI7dxrxZdhb99OhdRcBtfGMyqnZXIRycT5vIbsMkbeDI0/tTu2M4OOv
syFppe4rNdhr86Wl8niEtYAE9uB/svrb4zYlWA6fJo1a3fYVxdCE/6utgjr3pNuzXv7Nr8Abfgjn
LTHWs2YDlMgKazz5fakGFGzWcF6pKUcdr/u0Yon3V+fB0fcKnA384BfEDAw251dWCxi9J3NfYLbm
irka6jb2sFaVYJ+2TIJPr3c2Ny+w0n8OWM2ev/sPoW9Hppj436efhnRW5m4j31Y4OVpajE7hQBQm
Yj8g20DIsvsqk3VvGVZe9tUHLJ7hREZkcXBLUOZv1H6Iykvs8SDwDCkln4KQKD6647TA6Oo9Jd5y
/FlZASGI7Gv8DmA0T37iwHaCgi7qEkA/g0nAXQqL3oylsq7Ie/edvEyX6hU3ajSWLXU1P0SruFUL
kQYYlGVVGTpXJ2Pqyb9fPeeff5HjyKJ7vxTVF7VvxHJZM/Ur+wn5FnvbrYxMTP2Imya5MYgD4gn4
kc5nFXpBer11bLZsIsYqufB0Brv2N8eJWXPZ779f7FrBGEVPHZv5iEnQX5eAmIvaBC0tXQPJ6guL
/Cuj+120/5ZQA7RSIN2BY72ExcFRj132MpTr8sbcuKA+y1vQr16PgzwDyh8zNAUqUrO6tX6hurNc
bpQ9anlshgJjMptSiGcnRu/jx8Pf0ct7nsoBjRn47wypnTD91uSqoqVtP53ly6XfZa9f4f0huBQV
QNeX6WZ7HbMq5I5ccqFTR/iNQARkOJUnvCANEQIQxSKlPzUtIwR5KyStbm9Ryp/Qz/LQ96/ebWlI
Dj6zY6POlidFq5nEU/zOWPLADeAkZosphli+B2A0Mz1sArjcAvOe99P6nQwvw5jxFVRbPvRkH9lE
QERjXttVDV670CZIUdNM60n9dD0dI4c24SnebPFVvGoG9/yK6fiKA6i6uZObW5d5EBaz6QVyU6zX
1+ifTMY3ZzNxCSRhYiGeFE7r5wzA+1Yi5yzUztKYspqu7EwC6hA0HT+v0yiAd7IqigJ1MHPQ4XXR
4frZ8m1gvRI/mndw2+i/WPNS+iyy+UTqUZ0j+OJzIsiIyFBVIRppoNtWGEQ6ihy4AxRNsg32M4yr
CMAw67WxGV9O2fsfbB0NFjrFKAYBChfeshN3yBuHr3EoJ9ohXLq9Tv6DNlgxY+6yJPsaZgWqcO48
fgbPi+1RoAog9HnEGYRp7DqbKNZ3I2PHdqGzR+fX7zndBFD6LiYNqbVomY0xNcdnSJtsRVBcrpks
rMYhpYa1BLUOHgivxkRMH3Jni/3LhbxzX18OC3SC7lDkrp00Rzyk/2bMFR6WHPczp6s+vfFmLvPj
ErGOn2EGQA7xqP0wS3bKYNiQBd9cL7xyjC1HGmsZBfOHxijKA0WrfTJT4IDYHmFZkxgcdyvrkukR
p3X3MgEYFuGlj848fZXHLg7sxT2uu+JKbt4lwni/byj2DuNGSSBGnKBMAZV4TGt0hytCNmpHaHlL
VFpePX3R5l7iYELnxGHIJPUAeiWAhr4xYl3YGnfqV2P4ChIjrEp3L7XE46qTziagjfKFErIl4t0T
0ihy7WDWjEkoEiK+twwa10CNdJt4YBmcHDkmUh7Pxs+m04E7Lxp9KB70T1mxz3xfxQki8v/ZGu6d
Uhky7MMPThHdTBxLna1699xJSbtGAMFz+BKq55PIGzg1XNtHk1H+bLjQQ1tLeU126yzOkAc6Tmmm
jPRVFIhisLU0DcTXkmb5Dk3JqF5pR17UUccr8X9OSHpfBfHamKEJofqwDDUqeO3LQ6iLsi4ek7YV
vPmAFMIr3sCnDGS/RV/w8TWhF/WpxWMvqlHHSER49KmRB+9c7yHcYmKjWiuNmV7kyoCa+zDqjbC9
CbCiMSP73eIz1+UQhxWCdfKL2Akz8gKeH45qAbB3rdFfZjieRtCvzF0oREeTSg3INabRIfiDP73j
4c1DMYY4pj4XAa5/IdPKRoCllOheCESgAGoxuyfXmcrBLndH0lZme9NH6z/G0knrmjnv0OkWVE4S
p2CwG12mUDljjHfKyfi1/RX8Bf3xq1G+RfUM38PMstkDWxF6B+DVUY3V4Cu9CirHO2heSnLaeoRc
XwVZeOeFfsr4QqEnwZDvhNvIh+Fn8V2E2t0+EG8inC3BnjjxW0x9gUDahjP6vwHGnUr9I7YuV0tq
Ac3QwL0bETCnVbSzEP8S1uV51flHJlUPZKGedckcZznzwt5QNN7nPpqKhTxIm7zjpRBptl5ItGlL
tzuRy015mFYOxBBAHSDVAauMO3fAHtWKrYGeyeaIbtgOPO/CPhFlUSvDZefYc4SvcTlvMEFeoe50
18UzrgAkxBHjqW4J6f9kbx1kgLnmWUSp9HX5kl5nfihJZyMxOn8SKDiAmZubXnMP3XMplCbtlHwP
pNTIoYo9q5aWrosZnOKv0BQjjg+QO8MuO3hGzp4AvyIpj3rL+UMKhQhIZgCc/WBwO8pNfTVZOhkw
vtA89HB00hJJ6k0FkUtnBRLi5vXA4CdYV8L7NrOkaI8t32Asfp4oihZhn3V7PO3OW+/lXUWy3Psp
AkH1snrGy5+yIHFcu7fSWTCv8XiLMoZOnQTkxwOQAEJfon30XimlSX/YQB8g/+zY+VgV0u0w9OBJ
m0HdwNhytknfcTd1bh+HB2Ox1TT6XW9xG/NYhWWkdBLPo1nUgouO0GVwn+HjmZ8CNQqsl7G7Wt3S
SnnVm8QsYg8lPmXiwx9G+4E0tlCSxlmeo5oC0YPxaFXL5lUYyisiONTdvtuPb7ew07QkD06Mb9ol
DKh062pmrwijhCHh2Ezm6Gfv/CVHtJwN411qo87fkBgV9y0q9yTKHdlIP7YpiXc+pREh9zAOR9GQ
GQTn2MI4XNQ/5FqzqvjWBF7EMq8xrV4IQYMGoK7wweWRHheBLD7RnmMRO8+23aXi2mfClnJZNdhG
ScSPqdwxkuipB1vfz5YdlPLGkeyK3yphaCWpBVH4vjVBy8rFmelOXc+Kx8evVFP+MXlYSo8iY5BG
V0Gv170eH/y3FHIFnsYxeNYsY21AkuH+SZ60RvnnPa8D1Fta5++JJEHEY34bW2udwZTCpjZ9hbQz
glRS9YfAUPH60wc4EKH+IrXXx67R3BncuCb+GYQYjU/CI5wvMp05uWwowrxQU0PnMlD1CHAfR4gm
WvGAil7Z2PT8FVjTdAxebhEQmdudv4WvuYJ5fsUaRAR3Vdql945OndRFxvjmS+mwu/96zyDuZv9I
Y5xZh09p2FAX5gArebOh80Lg676/4Js3NpnzoYBkGTUtHzD+8jlapS0o7vQEmrXgX+hBBwRoZmhp
cvqxmeUdyYQ7EUPOpSum5GFtHelbpeMtL9+VNfgN9ZLhz7HK9X69Jn66y1BuA0va9eOTEg6g4p4T
wH+G8lYg+nIV6PIK/osj1vtOh5Lo6tFppLDh7/j2tUUqLa2oqdLnOKO42VNa7DTr8ZCM967CHuMK
cXmTidE5+ibyiXK4BYjntMaIB6H6ryNkQljVQ1f6G5vThHFdLgL1stRJXIpf9xY9GQv6Ovku+6py
kYUp51yzFAiUxJz53NtMa7CZqT5py+40CoRU29b6syApwFLJAHPPPQroSsydZzXhArPExEa7HUW+
l4rcX800zuHMjCiwnGREnQcjGDEsQbazbVO7Stm3hlMZLKRaJXUCEw56ZnOq8QJpf4tEKV/PhevE
nYWZdiShUjb+qLfuj4O7JtvCq7XNpmux5k8rLRT6T7MlhgigfKq7t5NosXCbo4dRih9t7Fya7j5m
lY/dinFIUJjPFRszNnwciIuc712xJ6hs2W38IKvQVkhgjurUzGKMkT+4ufEXDwkrI2Da5ArD4yji
jSRuUIhLO7WPBpZ5W9WSTs4ADxM1TKHF81iC/VCg4TMhGgX52GhaKSRhLQuPgjuyfxmMUhyHTsMd
30PPnc0BWh/uEssKud2gTA5wH0Uyt4pGYdzUn7gHLpOknv9i2/6OIqMRtCm0NaINSTzUiCm3gVKG
aTv5zJIHNK7QUfYiXgG6P/oEymwi8962Q/y5CYyxfF7ez5ZhX4vN5DI/+o+9G2OPn2Iegp4/+Ha5
zwKClx/n3nulDokScR9hhe3wk0Bhueiytv8ATk5rFs85rZ7Jc4TVOHnoJImSfZBhjBXdSKbm2Gms
IKt4QnAF+42DMjaAZ03WWJkjjY783OpCXJGVpOC+xNqdJ1G1of7lrP/nwvsrNz9+OR1Y03+6YyB/
0HEOfMDJ/QVT4uvw3UfZKmAIJVJwDeDPAxPz99DSlfiXuavRgXm+SsvkMIJPLyJnHAj1Tdv1yLVL
TdvHDzv6ayiqtOUaHiMOaJzJxxZJbweDSug2cHR6LvTq59uV2cTchforkfTuAiKyV1fJ88i8l0XH
+B22UIfXGo1BBHP42sZ8TNiU4OW1qHOKkuyGN2oedjoAw28gglJ8s2P4CRXIAQ5h7YzUm6BJPllE
qme7PjuBR4C7N2K2D6bVbsf/yDfI84XHMfoLbPpP/0PbMpZ5RWIfr1GAlW3DqVtDGwzsySXCAEwx
cSOdPDv16r0RE7NZxji3UBLzvBSk3jKuhW7nRsv3jNXU9SHtz1q/8DRlxTbH0QHL14n1LGEZ8xN1
cBo9SqZhmgCQ8CGjOuRK0qQCBe3S0TgzA8QbrAZZJal8NVnPpGrmj8pmbkIwUID5KYbg2IMXzSri
mx6Yy1Jcof6NpF5Eee/XVVZvB/6ofWW879SdmMI7nC74rvHPmkZeR6S1MjZR3r6Fh9miEIDgq/xB
G0HfGDJ5t8XKynnT1zsArsQzadCU3W+5VOrpIpeWIAVVqk8owU3I8ftQfi/wVQW/QXYtq4VGiVpn
2E2ianjYoe/SDEUwtKlpwHNs6r8AxuLXcJNL0w7DsYN/3qse+XQHAU0VDZw5HXz1mwsVj73KPhyL
LxD+jgPDv3UYpXiBTI9rrH3glvTO+oxILlZ+JwXujfK9SMk9A6LqOVCTxMeOzOm6y3n0nv0dT6X9
odcwqAVuIKY+imHVtiNc/KeW1TpdyAXtXXzEESNWrORPj2iuU/4EcN87C3BOpSpRK83cKKqUWlK3
lMMClpHmLHktvyKa48h2L3y6JGFCb4qe0AnOA4Z+rNveJg3CSGZQFpYteyj6GPeSDCJQGHJskRU6
8TMCr1549T4yBKKpfa1NPtdv0ZDO/eaOemJWBfXrOG/0jy0ZdO107jVKkPFW1hrMARWjxcqosLfd
JlrEzSpiLyMGIGzZY4DqC3WSP2JNY5LT40D+hRQq8XCiuX94FTj9B5QCoKDKQVC7NKfE41d2SF5V
R7fjW4pFp+PrM34ToC9L8cKnaEIGVfe7pthqAXDNbq4gTuuLD1k9SdFeY3hB48uyWwe1u6nbEF2R
4EtFhMj6mEcGJz9i6ReJDm0gcrSyqfzg66orfH6qKRXlvqxYA/DhEi8aElD+C6ik0K2JW20LL/Ff
Fjaj1ek+yWgVv+8rrVMCam4ECDNlLkNe73PUo1i7o5tXX9RGQ5Xl2G+cZTacaiuNdG3p8fUQAOCJ
VCTgxj5hkaFj4x3EC3LnKoMrdE/keOco8JHdn8ynKnsuhEV8kmmiks3xqF8fljY/HIkVroplH8YK
OZ1hvY5N14qEDCjZIqWFXa5IG1wxofSscqgoY/Sn9JlhvHHCuI7g/Namko4GgN9B1ZC352X8LmfS
PN2+3l5kLDgyeYW3GGDHPMJ5ALzSH3YHY/WYzVIyYCtizco1QXvPV1PNbs1WSoV+CZxFXkNHpSJL
AZsgzj7LyeeqO+VkqxBYXm8SmSa0optVZi4hB50jKg/ReBHGs++x8skfutRpWOrBCKWhqzibTmmd
Z5VRlyqOMDmB+YbXo3ZjRBhiQ2t6lxZ3quwi4rPtsSiboD9Z7J/RCODoSyvMWaGrXt4oAsoXHFCI
necTy7Whfl2NQ/2tM/+PCI8Ljor6BpJD6PU2vjuVptMNHahz0jOvjp+mypUbqFAifVhzNUnnEBhH
RlwaYFRQmcAfxf+YBUQCCqaHr08odAQMYwH61cF8SUI5UDCFhWNRakbQiT9Yg6oYVgAYIhQM22FN
3RxMehJ/XlcypbhhSBI60iKTlUNmrNQHuMuvmxisoUh/9LNJke5KCgaiQuirguI3XVt4PALBUE6g
NTt7kKcYxPaPYk6cJSniU31YIjgqWrkxi4LOXGyF8NpyXroPXlZfx0XAj4BuHTdEbiBKptCl4j0D
8PVwSsMmGcoGhebziKO4WIAUuzoGeVVeVYCvkAZGGJCbz5Rqa8FY1nDrMbwStNzs8PWTv7i9E480
+kod8pOY3beUGvUnuabW0bJKu+a6h5WOJ4Sp1BOZqnNYZRiCtT5GH6KAsTSjVjXBWx3UKwYunJ62
xHWPq8OiQ8cHWYhxVpPB3Ckq55CbhQjq/yMbjyRF2UeBk3t24x1CiwdL6PrYLlozlmEMZfRKhPgF
U8Mbs/5yh0TU3g6NgnhLJ66SocdcyPZsXKsioMuYhS1DnErHvARuHO8GQbZVVdcya49HBi4LbLQe
gFxydAVQ6EugOx1t9erIEwXN5IpFIwPyN9Yq0LiaekdyxsOIme2hcuJUK9dmupp5BZuk0gsaMogM
mfpSU1rqEOl/k8h4g6W1SRAAgsJoUcxCUhOqcsEEpJffGROkK1zJT3sbEeuyuEEuYxambTsU0/2E
aNe7/+K/nz1dcS7Y4d67PgmtpjqBHEiV1F4s+4wTE3110RAoR23eP7d2FbIuozF4Xm7FnEwLFhhT
0wBFvxQiGRWCxADsJbxlskuCq/3qteswheioedpru7Ws0JNj/g/nC/bFwp7LL/9fniqLgWJbECcG
2FRQ7jlCreCAf4fuv6yaNLDXqe85jBOvQ0pih2U3HENRfDX60FM4tyMsEX0W9iXllC0OxIzYSU77
tIu51xDRMFfUW3eULOyz5pRk8bxFinLfgBuYax05GIXn7045BhsfE/z2aJPi6SpsQ8JlrNt7ZScr
eiM9h+vSbyjrgdVH1jS0UB4kcWhqRekED0DGnRiBka7xXhbAQDKSnEbaKnFxUiHYH7e1ObZdFj0S
/CdApqcZYnC+DwANk5AVk4jJ8nJjAg7sAxfixOQKuAGnHiFmPEtR2s6kvw6OU1+J7Fd/yZlNzLJP
Q3t0dw5c3vk3Ny32PP0A+FVKvSJbDIj6sYQMNphGmAUxzsVQ+H1ueXyhDkrzLJW9Kg+sBtb7ksMt
oCP0yWSX7BMQRHRJvUZKfQBxLoNVq/+8xJwMuciU+i2Dg75XH895jdJigsF+YPdzRa/hRpWQ0DTp
qPSxIwcPBUQWEJckFieCZGdVlJtl4DoNwGo8AcgS69kaLjriygYNyyIDg++XdbrsfK7MB4phTf6x
QrwUJwqRlo+VXxZzobuGG227mPyXhC0hjwicfgGFiTZPSOma9vjb/+VrGdDLD1uWTIkfiR1PW2G1
704eDMAtubEH5XGW+L2LmpAB9J7ACvcJ0a6rcapD082VdgYwUvOnaXCQT2xk4dz0QYeVelucQex4
mOjPrfyhVAk1D3THq6Vz7V10vGzDWl/tuwcE2AcwgIbp/c/5qUaqbvURqo0lNynr06lMQzU2wPde
YlmMBnBzrQe+g8b9bc0XIhyvkYb4LTGmZkuazmN9nKLJgLFSomU4RO5kuat4CGzvZLPIBh1yqVFL
FoIJibHzwEBCa2BpkW5U3Dv5qy6paIeGY0LuaOt/+bECynauQesfr82cAACSBpy0nvL4Ys+yFpkr
OfziWOF2R8o9fv3A0lAVX7ZxZZ+tvfw3iAgL0GVx3JfOaewZ0V879H0cHvO/W+y41rE0exvn7OFn
SCBce73PoKxoD/+h08Tea5WU4Npq8yk4r4O3E1NS+kalV+WqMl5PgpHTKKG2EJmRr1pnAZw8/7f4
ck5mYUZZPJM8ltVbxRrg7x3evHSoji1ycY2uUIMTIWx6CsSMwRfE42mt4XWUppwFK1BwsXY5U7Hv
gUx1uSAThUknZR39jjiWa5BjUz/8y/2d64unoKejsH/bSEDJcwcWZEBbMg+WHL5i/OJWqSK8FXoq
8wvazt4SSn00S/DOK4KRR/SMD0d+y4qVBA3lzKsnrOuQDzhbJxB3vN0eR11Z0wOIXXhZnqVLAT3z
TtOZrTFUHN0DvynZ4ZHpBo2VY6//y2VXpNj8HGH/yPt7Nyvx567SMw0ekK7sv1p1OQTBBFNq0Abo
iJuwKil+BKKolfixZ32rcVV6YfWzFRZ1xReGHn/zGu+gKPTwEiRogi4UIgwspTfBCuv6k5tUhOdM
qPS5QXnlcZ3b3fW1v7ljoazcJ3Ysid+vqNeOxY79CU57hyEOssRrzo+LHfMtCdC82m/1xVtNzDol
fNunMJY7suDzeBojXfSDCtVGnMmRKOtRqdzfn8c/jTmvayKK6vJ8gMFZ4K0VHEz7L6lHIsqlSMAo
JCYXBahQtAkfNA79cVGaPvxBsB31uPWOpoFM4uVcmHNEbKMiDpuFEhaman39HPfti1vPvjTod3WK
0ZplZ+TDoF7VpFyZIrlwt3YBfPs0t+7czDMDWT0lVDqg3AW14HInN/NIyqgFExfWBgCcyI6/ZGoF
ksEWaffeIpzS4O/EVkTNhL8JvjX9fFUSd1NAbJKPKUFzhgGEn0J4HjymOVNeQThW8qNwKtg9gbRo
875P1lJ4mvQpxPHCOh0J27FJBtAdKcG058Jtu6xxlhJk+fg9tceoVhlSbj56UHkUVIZ61q4xSYmR
I4nS/s21ZQO/Y4pP9e0cestRNslGWPiRXp0NGGjJ96i9pgnFNW0CFcopc+cy13HHmBJpzh0G5Fy/
+8D7FWJEH/VFDs8OgXyloB6r3Dx2SELb9yoYSum11PjUsRZGNPPCj59+Clj4WsZo7ZJBCcLpJ7Ct
KFu7QSRSd58lky9FzUZhNwKjQHyYr5pUWbsVdSPwTWdJGVu1/D+n2aZb/ncno37+NS6d7B7DnMuJ
z+vwF+HRe4SLqUrgJSdL/CP71cZ3HjRQC1OLjl76xnfdWgopW8ORZmJalx0pU243xMEsDleFbOJ1
hK9V9QnSGP6c+aflbWe/rdGlw0MJfCbjAN18GDxu/tHFMs3lI+3p4MnCXEDzS13GQVT+PWns+lUz
SArVBtXyFgvb9joExFIICblKC6R3HyTPzySaeqHWcjQQVtxT99lwPMh3r4o5jok4nsL2lSs2WL68
fAhJyUTuZ2Cs3+5WT3rdwQTuhv1oY+e8lkrbV50/fGk2Lv4sfex/trDbaYZpsqUmPcyZQUyUDfIF
zG06wGBLE98HD+PeoD6CTO67xwvtcxkvO07GwyNJleuShbONDQAUXOxtm0rGqib0qQnQCww1OoJR
9dQ6yNcVL8xac4xSdLGOE+MjcmoVOcGnPuc2y3iQNEjP751HcuczdfiZXVbvtLixFd/AlvY3n2ZT
HGvkalu5Kq3g1qJ+oAV9DPRE98CvPFIzd3u7RrdDwNqJgT82rPwxOvbSwsXyAuC0Hy+kqkut6wvH
KiZtKh07XuAVrdBV4VsyYFBKL2ADC+92F0zHaDrAKljnX4eH4hRWAj7SlQD3GQNuvXrBQClKetaV
EinTJNr2uZX09pUGFlX6LTI4RsuJS1oV1vvjOaciLTtzFDuww7OUQTfTN0Kzf056uOekL7F70fm2
wzrKBL7LepuBjgUzeYFTT7E8bZxjhljs1CFhvZTA8xV1ae9mfi1wuMd1nw1bSWZtG1YikBxjzN7V
rDFPt+aexvCT1+0EnP6WSx3Hi1e/jxDnQiterODwd+PNiA5fU8rqdx8Yt7vj6kvSdqrq5PkrYTZm
oL8vneE+wy8BioVAmyHZqJQXtDj+ZOdXI9ZUqCOcNuyo9qio0Xj4yOvmwfMGNEtjixlRJKkL0AT5
ePE7nR3hnHqA8gtTaYjByabedW6M06QAt8KkaDx2zy2XeOv03wtrjNbXNoBe7SZcF/ESSJuCiQx/
aThX3DmZbxkdJsbtnYhPkV2vIPmRuAgZLkiBiW6XufB/lslO202xffF2LAPjJviVVixaptW84/NF
5qoE+5DGuqPBAxlFCMeevIsT3eiLUvmeRLkIqAOruQjPQ2veV1feeMZ+8sAsgPsMpr5FEJO2VwhA
si3yHzm0FrXTCW0cVC/CUomOgvIzVJvy48ZRntkpSVBLZ+j0dhA1DhfjnDxpFHeeLNb3GKdZYwUn
Obq3HX2YVqz9C6lKbJUWxijjggYwKH9ctvX24+dtVoP2GA0YWg0oWhMoP39n+ea8jEJVUSvemoYq
Yn/ynffNbRzWOYaaF4EnjyrnpqcLB905SNPrBG1FLtN5wfHXAnCuwEKov4++YhEPrZwBhMU6zpEq
+I1Ds2lco48gyyXmVXhzyGcCfoJPcZajXM7ujljUvjFMJSpXZloQ+o1SG+n7hH3LsqF2zAaxbreT
eT3vc41Q/dzED2Jh0N1YP0/a09t3zWeCtwACvtsz5oViQCBIxPaPDXkkGuCcCIRu0+TWQym+LQqB
BLVS14If5fmXE3aSJLP8kQUlD5cgLXMLHIMUlGc84JyKK4nlougoz1hXQjVJ41se+CNHypPzF2Zs
tsaU0KGoWbIcYTbxRurM1hhzdcxzNrHac9YG469KFu/oaOIH0SP9LfhZf2DSxBPjuq/XlbYjaw82
DUoaQw3mcfAxkisIbD09TawTYQ4R6/vN9FtN7fdQWNuYbfwsyMprjAw/a6hJ/Z4yGOKQulIlouiN
+uW1p9hvbBmtl3Uc5Y1+zBmymW98VKF6zf+OcAvJYVhEikO6CW9LXJdRbiYj6oqUaJKg28sX0M2B
nuD5AH6AQEh5NbDUT7GZ4xT/p/Hlkl/SDL/Y6ubvMV0j89UfwP4US9AHjlOJv1WR6A39ofimvPKr
EyhgmpQTN1PZNoGF0eggw6x1OJE6ixOCjstJshPQxGG86Onkw0RCdNSjSk6YIDxai1JclgORXIBK
UWpGQ/efbXpIiWT6nveaE3vHit25xdI/YWQPYJ5/StqdnbnrSHxWW34v31glDrRfJuUZYRtSHYTv
YaHrJ2u2Sy2275M7gfGPzGPjCcSn9neivylOLY9f6Z4RyiMb/FLjaG7hGaDBwdFp7cl17tjKiFqy
6mE2jnr4N7XFL/J2QMExGrmQtR6X9dhlT2f2i4lyrpoRDN7zkouaDhL/DgHX2AwweZHTbtZ0wjMg
zlF0vJFpnN6jFn1g+cv4Z5+a7Y9COSOs+Zwz1qGOx09q8OzDASap5lYUbiz6uFz4IvdJrlT3InDD
PZTksw8p0xkBnsNLoIwSmjnAFe8FUOkXzSZ44XR3rVXo084vruN46Jl2SquBibadICNWQLv5Jjoy
PkO7hFbKcLplTUaGr0S/jlroKC9wW3xUrCRn9AFN6jmRHg6LWsDzBYhAVLSQG+scqX31AHzQD2V7
54MveES3p3wYo+BNQi0WWhAfKyxOnJMwTN+LRUIvvBxxhmh1xNyMsKHN12QHcdnNPXNOG6thfw2g
Txse+EXg4GI/uwebKqhJBVPjoqKwgdtVOt3ckv3r6+w1PrF3QLVDM5m9/xXWA+prQv+cXLXqM9Ma
e0L8j60plddzAriHc5EXqBeDPFLH334EY72+wGpgjHtf2MJnFpUodwACRfWIJLEnR2Fwlex2wzfL
2xElntH+DGvpcOVwIPSYcXvY4hEXdLWaOTl03UzvPdNZAIosJtwiiIUgPWegi/ho81FCcDezAFtD
PeWsdE58Z8xKYhkQQc45pDqu7CzWYCalolkhzGSLARoB4hY/yl21PHjKkSVqOvFyBTkSaWttFs3m
Vh5TAaBaKZ/X7MdFcF51TydkLlhR2ZH2WxMOpSTLSP0d84mnN/0/YkNjYISwxqsaUi93SKKjZW38
nnZlBOFRNFAVfw/u/HqG2s7T7/aDNwe5bR+SBrNiJPFN+kZYZCGCMiqBvABvEEmwL/RKOOEPDJAD
ID7fdhToJExSBGqSM5Cm+I72qIafCzgegPb8Ny4FcdHeqiXq6uGtXcjSg3z21jl/eSQHRovrzoMW
QWqLMHL268sZz4ybr4czUTEjHSLMl/L3m1YB9/QWtcYCszGZmGw6FU+myQ7wfsxyZpbzTQ7DX5zB
/s/GDhdlymmSevGB2RPxYpwSMT6YSCJdpg+KK8SdOrkauLMcjWooyJ+ezgdeTMGcHLRN2t6vMdY4
Fc3tr7OxnDTu6R4CqjQQS/KGGi9R5tVO59BgiTJr0oq2FYy/75xqP6sPwykgcK2xyn/JZ7ietBJm
ASnlq0WZt3xOjFz7TODmwDvKW4MoCr2QUUUhGg1tHH6RU2vP0P6I79dSkF4LmZweMj26JvT7dXD3
j2PuczN/ftxACGjFejbqvMNeaD7AFlsQHXQmqVJqh5SWVRXIQQZzpR8zb9t+MlzBeWPAC8DYZGGV
Lk5w5W1ViJgCsNNQ3Yv/a5buyNOpFTGerp0tkBH8J8+v5nmirRe8/i26Rp6exp3gXGV5TygxAD5U
jA4DFIY2Qv6Jekb8iErd/bBMuvMGtcuCJ7sz9sarVkia6P7NQoTsBciG6L23D6Uk6gNeAeOKO2GS
Hfq9I1EgM512wBkNYDXIWvHswR9LBFICBnaNz14/2l2M8UAiQao5/WL5as2PmqP7tpApliGFq54l
P6+dOU2zGRNgghlt3tbqw/+rf40FCZ6oA4vTp10a+ivvX3zyLmScdG2Q+1RoZ5xfK5pMuaucW1np
5Z7bSTCLUM75g/pkmAUdrv/tQOcCqfx1y7WBU4iqhg4hESSzmwt0euf879n0F2JviBdR5xEerb+X
N0xKBb0JSyMI6dVBFYKXOoHK1n2mTsCmMKDgYls4zJtnOE7LFZyQHjMQTmohL3e4H+eQSDw5/R0e
PSqMngvA0Mt3UyM3mcNowyjngdZKX1ekKdg/gac/w3syb/U24Dz8SLjjCnvUHcY6OUupI3NG2VfU
jVNF7KPPcguAAUVcHYEOXKolEVmHfwrY0j9pWDS5ldgdSFVP1jtJbbI6/6m2Im/FDL6Y2i4f0kD1
CfVMqdOvoSgrnzHANpedtgCK6tBWgfqSQFx9oeOnhsyhVAvwm6Ave3/wxO8xMkYx0uXpzYFPXvvK
jt38Rg+eGSqy0lfbR9SHODJFc8m3OhJ+8YOgSZLJFDRB6yir2+T15q+rnI8FsG6s2mQrYUObtlYE
yHE/1xjCdcZLIP0+qN0HAGLeWMErauR35S9nADrKv73BVHOvUgtdUPEukER0y1gCtIp9gJk3+F5q
UJrcC/3UTDby+2Z28XiWiLhgMUNReCGMA+Lz4LGSNuKhCia3c08HvzJLpAVfa/A8rY/BXCvFZsvZ
AUvR7uKum3MCAq2iQYo8WZ+88vj5R4iFBBGLQTSK+6FAeT06687RAV4S2z/BddNbWxPnueHdnSHv
qSI87/k4vmW/8fGnN4i4tptqYrFsGrN3vkqOZynvckoXn/pTCwtnmlJgk0I/4DIiGPg5U6JuvAmL
THBgIos9rFn+P3z+s4KFykF3QGOSmJKwhhq7Dd10Yixp25G0SI+nsJtTyZMVos89UcPUzSqKf7Pr
u7G9S+BjflOiCzvdU9YY5ia2/llDe94Su3sdVQyuNZqabiUKyWyu1ngMd6Npels+9ZnlyCqhCKzT
T+3ohKy8UV9pJBVqkG/YDkRNiTFrhU01TGL72yxF0i7JvcvSaO18N92TE1+xOvooc8XetjVWEFhu
jFXe+SLQ68byFF2R0dXacn1n7rQJx39tVL5nE+sppyZx6rpT+lcli4HFoEphVqs/1xco1/Mfyc8U
3mpKpFuKoN1x1yp7mW000m0Ty1SBCDajeA6riOtEGROEJVIHcWfB6SbkABoS9RdOUt/u6UxtmaPb
Fo6xPItfIQcxEwdmjk1KVAvy7ldQpqKl6UV18TP2E7vc4Xvu3DHznwKcc1IcbK9DdqF9IQY+u90n
4FXbf27lZneIYhelMffQzpq2RzgIlXJPl1NDCvpes+RWHC50Gwk6fCTQOLIZcMEypYXDxLstknaM
dne8DCFrd0pP3es3V+CiEPRNniLV8k1jZNMdNUZG0pcLbctyspeTH5nrp1Hub8Id3UwiPet9lLog
EVsNF6cbW2zW4QUVL2OJTaJqXsnaxTgQzA8m8EgdQ82yUdBMOx3qVk2ohMErgRNQJKGQo7lkXber
pp8fJN/IDkYENC5VIVSlwbcGCo3ygeC1B24kQHsA3czBbYkf+Wi7Jc6YCDJtmI51GXEV/PmAxzu4
z5/AcZfx3ij/rsvzK+fbXO9ELyaYvRb32LKOo1STNzsqXfb3ZpDKFhojnicIJQwiesvZBJaTImNZ
I1EEtpH3wLiyUXLkqJNds9moBG5K9jQ56amKcY5rfqFgjco/Na8PYzkxxO+P+mrUIFVFo6IyWhdU
XJnTefWLgir438uUDMtqcglGzKN97Y+hykPaMiR197ws1tJ2lb9hkA3r1ZDzQItE1qO7fZ0KFTmN
s56CobBUwpEzfEjZ1Ce22485B1aIdnAndvziYLMetQ68+J8j/dwJ1JrW5CpV1XLQm6qxev3e5gU5
HQlbIXtW4YUVv0U3TF5JtDpZxR9IGv60TwDij/3tnjBeY+qyKNl4MVKngmPiZXGK88/W01NKbAGl
jHkJUGZJgWF1DxJnHuw3VuTavHztCpk5gHrPNMA6VDU0f/S4t8Gk2fp+eWBOT8FSgpTqWhSa6sIV
mZGVvFKvbT0+VRqZYXObwvG8C3c6gbKMCeW+m8yx25oE8ilVfHc+ucZWBQeqTxX7/G2lLiFcDqNh
g6Kwmd9M+2b6YaXarAObkRn4uOrg73UvieVumYa/Z4dydEDYrtNbE9HG+Hi+tC4oyEtYKYXHkuYp
PfOZCTd68900AFsa2JkWaoyO4x+cf4W8L2+5Xvz1PWfGhX/xiP+W1VvX10lAbYYYXuZ/01VRFh07
QqVFTCew9DO3LZTczVRtdLCIV6h/V5HxGcUryuohtvkpS0bNN3Fl1PcZUXYeowTtLVj15jCbwXzK
Z0R+r6YvAYZZVOD6gQxkc/xpOv+cUx1QB7QtL7Rk/sW22+JX8F8Y8DMAkQSYWOMSdy5c2+he1l9w
pivXNcVWYXPceFRk8VmwXzVd6L9/C46kxAK+lex25sv66MtpGKmEgq6dWvl8m2aCnzeMdBPFKMq5
B8JSibNS0rrNsjz8oW63P/hXqBdwr21RNAxQll06n6J5FSAciHN5GE+jjDQvGVknGXhoKi5DE6NA
mq5ezHTa56rD94psUWUTCffHqkAbvZsaM9aBVSctTKfvWk0EkOjZNIiHC/8y8yozX5bYkswujzA2
Gqt+096LYcRrXiaC1qY9SawbNyq2j0UmvHxzRNolvBQwoP+LCpbXwP9meFf5WKre5M6OEuO6ZfAv
uzVDddlZsNe5o1ChWgNW01sDY6vjGmcZqO5ZwHFBGuHG4I8yzARw/N62GcKY7h3C/KttplolEv7W
U+9K2JY7EkPSYXZoExYVupw2G+E0Pz+VjRiTtfTC/MFewr/U3lsejK8sZvBctvcOeo8/2rUp6sNL
CEwgPYI9ib/yYcIj3ZHrPDbtJz7zpcNBENxl7SQdwVvukj6kc8WUKA5emqkbxi5wfEbKuFjGxs1j
5YH68EzioTu0C46kVjYkZL70rFDXZB22GD3yK31sjE6y6mgfJmdBWxakAuzEmXAHPf/p5CwvRCCS
Tym5VeRGy4h4TJMmszM5vcrg4sNEPClyFDsbUXhWSJXmCThnw1g1zYCO3W8p2SUKwQ2GxiGiWkJY
nma2prBK7t/1UhCAbubMunpKjnhdVdj541jOK45064cDIZmpNSpnjgnN/dUrezohKR88QdXGQqBx
L7uIymEeZU2Md7jONJuA3TNTUq3gaKTqkljeM/lrmFJKpoLdnYKWMbQeqV7hstnapHqbKRdhkoJ5
HFBC76hNFjr/X8t51BfVxQnVTCczvFS/8WZrOycMIbvIOcLHP3ve+mEAUJjfRk1lsQit0slLUaWU
lhxQHshI/EfTTzde9OlZA0Y/79+dFEsqOAOuU3PH170oat7SOMfVbYVDoLSybtSLrfK+GlkPXD4n
SSWgx7FFU15IMPNudZpa07kMSHaIQIqEzVg+5p2GuQh6nA4AgTLGN3HFRsCagM8LPa9Lrpc1UqDy
M2Ox2th/TNLFik8gwTJBUdQ1q+IgPb4L5SmSLZ/te2Jj2Hfq03hfftWqrUE9k0rx1EIp4IB4Jeg9
Xs7ZltN8AEg4Bu8JeZNL+OYQQApoTKV5n6k6aN/nYjXgs4T9QiT43R4wK8Mz+ibdbnjwfneGnmk1
XGj8Lu5yzE0MtC1p6FBt5omj6ut6YXSVHbHzPLjwEJTu3+/rf1cxiKfqMrxIPNauHkF4RcNI5Owx
NoBEhpAYnvylT4ssBtAWr8Q/+OdziDBeVaSI6dya7Bc3FmRPF4gUQih0XJAX3xUyy00tHWXLQcbo
paFTSod8zheD5OVkkqLnAEdpHV5ze1SsiVME2I6ZhHPQVKDCfd355+OMk5NmGv1F+BdrlrDDc3ba
hGMtp+ATmorjXEdAc2u4UWAfTjbGQyW34a9LTgf6gbk2jv/oqCwo4MDhXavmEGiHoQbJ+PTrziRz
u8vXdWhuB3EOu3RwbDU7oX9J/ipN96yoBo6GvaJQ0qgRtY3PLeWDuO3PeBlvPcKkpgAY2AvEZXAT
5uNP7TxejoYd2NxhHjogwV9FS2IvXGcuBelufNsrUYX7hZYuYnf+xlYSLhIPfWmqCqOVbrc5W981
OAHe3hxUz2zuv9toTbgTVP16jiudpqWZFyKhJaQ7M5EppmJcq3fhSRinOeTCx8P8uiMGnOFxoDRD
PxlRToQCziweC9a50aE2pRDJLVm5BR4p8yStEZu4AOu22tfUCLACtegKgFzsLArqjkozGeZorCWy
MILZlqxCQr77yCJgx3DlaNtwf3NfDwzryGVQ5CQhiMIT43RZgHmp0U+eTJsECPgBiHNxRjy/ZKEm
AbGzOzhU1C+Bnp7YIq2hBBDLTEUnVa5nT3RXtMhKJRYYs7dOcV5Jn5ouy3Bez99juc/GOb7u9hBT
OfwkF+SalF4Bd4hOqMOIFOTolOOG4dWXb2JyM1Av96V/lw2oGuDb9ZrIEZ/LyRHI9vnvYWOEFgGT
QmGI1X4r0R/NCM8Adh6DALob0qM/W2rM42M9p4eFSOJGfANgm2/tdW+Oqn2GoJQM6i0vjaF7+jBx
xO9ffDR8U7/MKkPA/aYGj6YLkqnqSyCWBm4Zys3C1/oZx3svVUGCc4dn9hOw4xPfgLHKADlcvi7l
mNXtJa9U/yfd/25ShlUZo3b3KG5s9sv8+Q11uvO2J96+f2oWw+Lab7ClfBC6OJkBR/JWv8hgwaMU
xxn5mOjowuViCcDqtnjUuHqhxopai1QJEzUipKLTAVSipRNFHSr+nKsR6uV3qrPVD1ZK5WIuP7sp
pNhvZ5/UT5NfLfwnuaEZ1QgwNYtN94/xLX+gIydguy16Fp5aCMSqPhvVqpiSLNCIVzxpGaVi8XLA
riFt0htSWFcTRCxY4r+Slyiabt0m01tUBhiFG5EyqcdbM0xrFoaKddo8RxNzAYU23D1zrTUKaJRg
vZojLgXKvp6MzzbtLuUyvUm9bAnCcaPGhNjdAaGn+pT0NxbexrpniPQ1IRgBjtaWQa/pXzqK0lMk
IFjNpHzYy+e6zkUO4/ORBuEnt0Wlpmv/yHvYAQOThsn8GEQB2yPtc3WKrjvSAXT646ZNgK3wno/2
9nZ52c8r6yyeY7/A5oIRVUPkOGa/xeGoP3a/1mNb1xQsYrKNGpgpWlOOeoqkONt7GijdYMhVlYNJ
YEMGuaylmVM4SOGcwdnQmn6p8Ug3Giy838+wGN4YCKZ1spYTI56vqrZd7s0IV6vYHtOkWOnyREHL
9/+v4I6mC0izxOjruyYMISezPhmagM0AS15cgpIWM2O/rbOqRBHQ4B6qc3xSnHrQ8h4LA1vhdE3y
5Q+ykMDng46j6neapfe9XHTMBt80AluX15FVokoUdKcd56kY6fsnHlNoKH+igMIRrE0y37Vp5u97
pyawlFt9BIQTJa3jDHmSECZk2sunITRk9QQJ5irJ3LQ4aiddmOyVGmv9Zv7MxcVAdOvR2VzMt3xc
5st7RwkDqgpfFFIpIOgJLSlRtkgsQ19eGOfrWplZf7+p0rG7xORd7rYypMRA2l4qtVY3CTFtSZ7+
wmNfX42tg68xXaBlegez2IgrhFrhmLyVvFXCLhgAK1L5L2kKrIs4lP2uVKIBuhkfqYU6waWZ9QGb
ItuUP2DAetA+WIHFUMd/l5pkweaLpnO4EMaXW/Q5f9USlxSujYqTdnhQc0S6t8D+wZddfcjMtO7e
/3Wc950nC22oQBI0HVNMnEqn17F7uZ7/9cJ2rZ8izCrzUXMaNREJkYXzu1CFGIlRB/YoLPUNOjGr
gJhEouApqgsTyhuiRYA5lmitEzO/95auWL6m+gh/qJSWNoJ7NHI1ddD9A6sE4ljvduE+G4totBQg
7evN8+SwFYup5kE+W0JYCe5+AfmtdS94iKC/nD3AJAdWRVOwq4QtpJQytxRxbs2/748bESnapTcf
Vz2Rfq9lJEC5v6+o0OZildcAxc4esOnKauXf9rwToyOKwRH7SN0omwT0v9O5QqVEcXjbEpgT+2KD
8vTrmWqiFT2+07566dithMSZMDn0V+RzWOqolPhjl64Aaazf0iVZieFyz3NpARXLoSC0BSvXvmV8
hBMkOBzZFKDKLBjfEz13G/fd8OPVU2aKwy7E1++r36oUZBPA9L+B00sqEuhgw+jazoe14VtmGnij
9Fqvj+VhZO14m8v3OBWXKBnc2IxiipD1P5Ozxblu03uAdBsJoaOuu2p8xQREXxdCkhry2BAFBIal
eZuhDhJbPupYn8cNo0o2s4ZtVV798zBuycGGW703A4UzhdG4tSliKTNjrpQ60STRI28dtdvuRYA3
fd4j4CeXTfnO5loJUWMmrNM3C8yKkSZgrxkBw8a+fB3UfjlvLjGjoNH7HSFvxZvD+fZNpXlDKjux
/R+4Wd+zBHELcOVQ7RU7ZUJKMeXrb4leTVclqEJ8eDL520EDwo+l0GhZRaOcNOgitzTABTy9YRKU
APcWnxWoa0cGp8TJyzsJuagJGE0LGShiAiYD+bruMwEen23dLclllzRU4AuREIwBCd6R6K8QVhcU
0pfDI43uzlUwL6CjxDmCqwkKV+V3+TBRVoPxwKrOFudCtPUE9julkiioj6nyBsW+xC0qqB+Ta8zN
wnedb1UMfjroXceKKxFBdydGXg/Gaob1wU/um2XRZugTk1Y8Kbi5zDFFqurs1K1WRxqLvzaMTjvX
zQOjFHXMnRsdlVuaGbYzTA0T8jUOLvDhc+wbNEeRmor9jFEhNziVrOD1w58JPdsXAeYgFRP/g6AI
wQFxOKEwHdlvmPmb5bo79PKP10zMeilwgAjrRqBcmQi6T0s4jlOaoNiOygHczxISwCsRqECF38Mw
Wprhwa+A7BDP2vDmCmclv+JlHiqPNHfqjF9a30WmIA+oRZGuPn4bBnmM339c+7ZChCRupwQkR1ai
4wCjaKQt7qqLSZ3VMXmRzQkt5LKEjzwJwKTH5zPnr027XzpVyUNNe6P0TSsNJWWM8IX5CivqkVUF
Xsi2uguzj+1eE4cwloqQ953bYb6v2/HKB+jHwi1ZIAICZXnFFQ7Q6fbw/RGjEDLmk/lLsUAM2gx2
eP97KDybnDhsZACugNYhKH85R9tzafL6YC7c0qttboZB/ObRyZ0+H/ChwTvuXftmWrkQiDMpKmBp
51jHl5FTgp3UiiGdPXcOABaEAgnQFvzaywkXZZuos0t3W81LYzVqCWXm6z53k4byn4NwfzVPyyo5
eUexHffYrFTaOwB/BZkJsHBJPfSYhFbJc6cazSAd5arMxYTDcUDv2cZcDnpjN7gqh7doDOqIeACC
oLKEa/99Jbd6dCfoqigvoevrQagDFlk1JdDcpQTAeZ2r/laq5hFdmJejy+C8hvrcw8jgpTuckC4e
PebgwWc4vmjqqDSRwJMl24eXrmkPNqjGUU1xWddizeDyD7wkLS6w6MgpWSjHaJL+YoaLxse3eOjR
b5l5mDgpqH/1c0VKgqkb1Zxyr1ElOM/vl4PDiGpW1xetZfnfOKsd1sTkA3lwR69on44CkrqKYzbN
eEdV0aFg+Cu8LrrdgdAuRPoAhomI4mh+iwY2sZ54T/8Gu9aVBlEfwYd2i15P0JwZUArqwhqrZUXm
ac4Z1vH9mzI62mqyrFAMjfpJz+pnMowL91N5DaKepipXpCjfCB0+UYaoy17iV9qfRFwZw60t6NYV
TfKt5bov4bPk3yn/mXPgzGTgtr/li0aJ9hPAEgVNfDwmZGsYkVKgxsfuorNsay+Xq3hUd9CmLBX4
82hu56YQHgLwUI04sUefpvIMQRgjRN5/OUrKerMEf3Id9P1otAakYNhOlq71Gyk9UIyB2MT1Qw6g
7sSoc3V3i7DSD6TeyUc2CEsggXBntGr+FzCRigIxcwFHaB+cWapqQIlQP8N0JTOs+Qci/SouL0RL
q6l9yx4j1i0txdR8Wt2JXkTQdpVH8LV+q6S0tYm+5oiK+5tALhrqcQ4O/eoOFne9hW9T5M24ytq3
bEf2Ci97O7LvpHTLIR6amWHkgF2jO8S46pyH3xfHfm7/XPLvIhW1UiW0TONGblBn0v8se8K9/nRL
U95zCkKw1Gr/Lk1dRdBiXGc+TZaCbi54pxq56f9T3h9ig7JvzZhOipgD1WkTGqQYZee+1H90V8en
/55RkSGv24O6EWLmM9foXF/bmdPROp+Rl9hA7ssw4/3hyCUkb9LFBrfochxjONpuLXHlweVGbAAP
s2mspEC2Unb3haIt1DxQT14uyP8X5+z0uiXvuZkQQlKgb6hPMiV8+LoCgWpVl+TGrvRNJs6iO8jc
Kq5C5/FOhpVnjs1GdLvE6I/ZVo0+z4LUeMUuGzF1b+5JJi8jA30uRKPfoXhBJjteC4CNv2sCHnQj
VaGyg3xJGokLtXQ1UHCEdd+0xjSLTjbEwaeyNH0Mt4Wx3RJb1Fage+ixt4bSBNWhNYiffOXicWII
spWsnoa7AjJwpd69HnnkI9NBJ7h5I6AxldxS1IuESVyIGSVJhsdH7Zml6yQNpMZs7yYrscJMJOcz
srgmvUjPasehvQvSjg80PEye3CdYmzj+mBVZnGu8RoGefDxERRMkaijuoiL+L+ciwsVvPUQxln1t
IoglvV86vQ0GoBGI2cYDnhk6wJuHT5UkPtOQIzHP6GRPDD1dTrgShYq+85G0OVqHjIYRN0Qt3hrD
JAhatQG6dFGVSAIRg/FC7/9xogU/XezDHqwmhwUzyVCd1d7iKVOMLJEPSezkIGTGphVBp4oNVbvJ
4Em9fOk/0U6lCyYUs8ukR920JHTpYZZd+Egea0fkauajZZ6Tf7hp2UIGdleWdysB5p8kgP+jnboj
Dqi/HbVJiby2VI4dcIYOAPybHTCSEwNFn3QzFfbS022sJHbBmUeml46TOAV4m524o9bXojOS4pL4
PzPn973D9S5hIVtxmZajYPAOMUcGkqLqL/JFWgVqojx2qS/HMRMSz3pi+HPmmwG4HdTFLbnPVljn
azslVxv7ZV2xNCrwcY+SvC80uM8R+r8SD50plId9tRqifUIOCR/Ub3iDgYDZt/yp+mOa0wAOPr+g
rPEURfshuucGwbxr4mJjzFgCvE548WvFijlDt/v0Xm3ZOaUC/XmKKnkA8X7EOkpe6zngbc8uSgzM
F2NcnCIUAsS7uOBtpb36YafIi1kLdeJkcBx0MceUGu2BUSyug7PiHxvfZpWl6D0ZMqxwNEc3nvCj
1TM6ZaE4WNP1BYAxwqzSXdI75wrqZ8E7URfgsUhhWUqkIpoJskLaMn95oBfT2kDW5z1cg4gpMj/x
iK4bWUCli+w1oPuxka5PZb9Ogh20+rRHhutCO4TcCjaT3Wh1hsnBgUH1CbEazfqCvsdCYFUV8aJ6
gE4NLZj6RJqtqeGLLDAC0RyczJG6Th1Kk+4eGH6lQQwRcBYW47iX2Bf0Mz5tyQemUjseGdFsIFUj
WovIuvbKXsLDq2DXL64f1hpKPDNO5HpRdFEUJIIVeYEMJp2b2CRH+Vx5//w5SmEJt0zQxnx+o+Tt
934BPfBdU/ElIaETMRMVK7WjY1pd6Bu6KTGN7NQz5ZJv8Tu6Y8SdmQcq+p4VzWoPU6g7HSfSUj29
D3Gjsnv9xJi+KqWGEu5U/iEhuXZ34jeB9gZ8mF5Em1k5g4GolySduTy8+P9HrUYf2Y8KSHNrq/FO
ANiHjsDL5O6sYLoL8RNXLt4gkCLB/r7rfJXk4f3N9aDL5XVXZBouCXUU1HdE5wUBEJ6mhvx8WmlV
JvM0DDRERrf7X+0YJG2taLvT3CXiGhhN0aBz7/cyrqh/EKaRv0AmnoAKMGkAm5VULaYTZObE/jGX
D3bqnE5/3Iv0G8CZ61HRWBp4cfRLr3R+U1cT+LMggaffAojGrZOyR0vpZpIlY2o5KOhk1NNyzx56
aOfOkCOWLvxd8bZwhNl2hcVytkLJUAVcV0fFtXXh/KbEdqw0gZWiu9wtySR7QJ6Oh4qDPOvHyM9A
UkhjkvmJipxkMy//8gbW71QgU5V/aEdLREwF5Mu95vJvxJ5Qb69jeRWEaaMDwO0+qqJwgx1amrYG
NMdrEkRid3xBhP0PdzZx5px6nNxa3YBsG2wRwBg0P9AsTWuTs3q4xAG2YI5giAB7cOd8lQZbA8Aq
lXvNbTaVOd6zUL6uesmWX0evCaoDEQqXqiRs8qdEziruGpF4GR1X6Qp8MY+vENCx+m/oGIV3yJHv
bjG/d/etdXt425Fq1jE4NRUbT6VUqiQYYSiow9uOg8wiVhr2NkNAqnMRm7gx82tM0cOZGy7Zt7U9
YTooz9eU6VvmjwKKP3hV4IiBYlb8DqYuaM9b6Zt8Cr6+oeRh4rpmnNFP8+FnKrt+4YBCsjapfhM1
o+GPUYNQGMhQSeh13PQhG+8e5kSSMJIyU/te0XeZtiVS4/6oAa2eT3DMDdKG0p7V1vymx33N615J
4N6Z3utLdLCucmA27PUHYoEpOpmXla4UrBZdPVI8/u3JEWY3UmoHcxVMrSoqQb7VTuzvcKOpzK92
t2KKK0APfovzAQjUgDuKpJ86ZiUZU+v/hDC3M+iz91R7C48QcXpAI4oGS9wMQPPhY4G5iuBy5Lzr
qd+B5/zeFtjXXmTq198F+DGXsb/LpuWK+e7Samq47uR6X4b/VnryJz2pj8j3/22iJqdUuMthW4Ek
sucHj4Blgz35A/FUShOB5aMaFGIWI1ad0yY4vRu6XkPnbrA5tVRqSOTTIKqNaflNMJSOpNueD3l7
BvpId9qnQX0hIXnK74xsD70q0Z4QCMhMPx+TIKq3xynmnacMjEvxSpjJDepKU4S6N05QQjoYp1Hc
UEGQ34WONcUIGGdR/HIigdYdKcr5esCsFFvYq4uLvdfM+768KS4vCFJSlMRS1ZiTkwrkxhg552G+
KAcWfCbgzJbYvgTjbcZofhfhCloxVBVpHEWapEO6PireQJ1yGiXDS5gPXpf9kZACpe8BF5SomzYE
tj1wbg84sk0IZB92c4jQRVwBPuTReKuwSIEjijbsxU8IW/2Q7vMyulmIxmbOJarDunh/Fq3T/Yfr
fS/5dbJudP/OUTKwy/LOfFp+CW57aAWziBnDCTnxUgaIvkkKowH723mTdPjzRyGPMKtaIlWRfPKG
75e37ebjble8c6JdJqzKKpCh2+7yohMdmabfzD/vwf+mSX3XjFY4VFglZ8wHM4NWzgDDHjkzkn+r
nI3FiUGaTofYoZTmflLE3+pLlMa6G0sk+Az/zygrt2PtsaNYNlWTR3SqrqwBZOv6JQrvxRkpvFJg
VeqK6miQp8jwbAMdUytzekmxam3obUHUJxjL/sKXlyOi9ZPWZLAjbBY9zXTGh97Qk7xFGtzu9v0b
qjo1TE3BMUBEHL3dqq7nU+0fFlJq7B6LRsdQ2NAc+XepuKyxGINFWQnR9EtYaf46P7c99BR7RN/3
tZgtHEApWcFEPL7m0tH+wl15q0iphjnbOiTAxHaNqxsu8o7mbVK8aC5L6el6H34qDNgHfjClbUiP
FZxlwFLZI4sh6LYwvV7s8CZGSWMvYTazdbwGugXlFdlT0e3yca8iwZrmGsNqO2KtnSd7E2ZpGsIs
a5AcgyJV+i5WzmoPap+SGg3Xz/JmGkxy8/pbZF2Jh99WFay3cixDNcNKDIjh4Afxgxj9nMNpskro
Ra8VdQeTCGNZrKZJpzooPWEI4/QXFc6oJWClrgxdHIJVEVy0pT5Bawan4f58R6pIByQzTJJU9MfM
C7J0By/QfQ0XFVIqq5t/0sU7GT9TFQfRWKZg6QlB527Z6He03cABB80Neey7a0JRiV9+Lu4uZ7No
migXGOtC6MSjwBoLEzB+cWN6S93SjNOsd2N5ufNl1Vl/UFw2754HZV40+mnLUYe+2bNB1Y1jeECL
ake5kr3/ouUZ5FqAt9+MvyhKr2zHf5EUxwTsvX8bZFfb0g/tlhADkIKVj595AaP5d31/goiZ5NvJ
vU+Vm/vNmAU1Qrg1m+rOFD62/PrLr4AReLUHlKbZNdiase3fN6RE157dAQxpe6vte4HLpvkXB262
679nTqMK3/40GF99nQrC2g8KGw0yDUw/qpBOa7uWrec325DyyltUv5TdwaZ7Q9GELL62OlHWZqiD
J1hArUqrnG2btTzuvdVOM92UL6dvCtRx8N0LQn+2WJB+zYs8g2N/psLJsZ4kTU96NtQ8vWjX7WFc
twQzS9gGxGJU+gpgS7mz5cuhcsiuK1uGcSlnSpix2BIUAxM4mSbc5gwBKviA8rTuUjzxbWiITLru
ml3ORQY+v2jAB1rEs90xGkbaXIfsaIeImxEMjjGsBDVrwAQdgNfw9X+R+BJXd5nsyJ7RLd+CCWAn
QRW3HWKIHwlVZP9ofqaAO9k0runi836ndY6C2CbYhjlpY0uX6lSREhe/B/zp8X/P3r398yXii6Wu
Ei8jxfB7F/tpAE16JA2cULWgYHkmJqu5dBBe9awK8B3IQaew0+5U+zpgTbfXGXc+79gXbKS5YXh8
aNa2TbqOGsBwQEXqwTzGMQZnrzhF8Wb3Z3R6w/PXZmNBITvSOtqc9X7yTfukaYrmi4z/G/+b0DlY
n4BtrI9eDC1eiMTDnMSac2NUeiK7InwOX6abrVsdhkcwStg6LvspMuE+3ubZmSalm45XhkRGQSkn
E9l7oVC294YhMmYqiTEy2gYGfc1Fv6L6+uD1SFs9o0RRISlOIRQ/jYy+ErE2fVbhIxcvJCizHGh1
kO4ppxrssWAVcovTkVQ351AeDx1HE/ibdipLEetTlG9CGzM3CibHvLDHOaoxAdCeWTCWmsVMVIMM
ucFeEuC7uYxzuirHZ3pSMJipx7/aVQLRnwkc8i9043VcROMX1ZAI2Ar3gyXm59wWoA+Gh1iMCIxl
Pk1w2rVzk01+y5DxY/+CzAS2UGLjgs6Kk7AzAakX9XT9a90EkvyrTE7OCkONmL7RwCUoN7TJI7n2
xUIlwuHJkRqMtuDLlS+jTy3FMdp8lnUemO8urEKYjxUiAjJgmiU2kmT46U/yY/L386C/47zrLtt0
wKbRVyce1GhpraDOongsnnhdikaqVWK41hhTOp1IhSWli+AKPAxPZURzImAb51upjWdT5jx0erzs
bXain4glqv0xRMHGwNZStzaWqyqZxotWy2dfU52iugTxWs7ArQZTBW9WhEd9dnZ+MhXBL0GlLq9c
AQumg+recJCxFIl6DENPZD7IqTvmPVmw6cWbkzbWfc2Z/gLFmYpJJOZVbgFJ+zmxKSwzk0wEN2I3
CNYYPPUByi/pyzib+tY1hF4IJLbHJsCswLnKPLuwo05tuwzHlHfGm4kEj9hewYiC8KCBa/RN2HZl
lLiqxjCh6mMSKBVMoCIoWmowLJFEoO5cQsxH9Rfb4/YCg4vC/PJv3kaTz9meVRh9GUpIuGVvbyYB
WlIEVe0oQFr1uCznYq6wwbzSvNTg/Ni9tojcZo5RHnCJk5udcKR69jHJlt54BaxeN286+aLw5a7k
Pdx1vmBnPoemSnXNbKvN1I3P8QgsQ7wklSo6Ge2Rte3iSZGcEHxGc9TvHKkK+F+vT9l7/j/eK3Vh
EjPI63zbksCAHYm/bx9370CanxSWwQnfAxZQKaIAs/xDWChz0MniKa107m/oYSh6ehQ5SwExLdE6
HeznG6CbfdbwmeHfcXGMXYpF7jlFhCPHD0H/tWi3ELy7wnj84UdV6DWkITurUQE4cyh+PaEfjU43
qWpQAvwKKModbTEG7+44TckTGhdfjlJmq5R8hHOKTDoyNOdb9Xa4vavZzxOFPjftVjQNi51USe3o
j5K9bJsmb6DV9D9OXJTydbEuuNqI7zCGXHHezWuBtcWI4OKw34yMdEhOBMm6vN4biqG361SYtdNL
5QWZ6Vfj73J/1fz0Vlpmtayqv7CI0IB1UoEuSaOst3AFDC+aCRkqMZFmWHiOJv/9T5KFroxHwW2w
seBd0rsV1dz7mWxC4jqQ52o+UZIcGbZtqSVP2vIIqWHBivxvyqBOpvMHX/YGNot7mwNPVYsLHZ72
0L1fq8Pu/NWg5X1Yrje27EfTYNgeQmMyUCpenhKUG8PB4Go+S8lbmMAFrB0p9XVlmjlM7yBY2/ns
u0Qe1Q3RnsARQsc1yFvZNnLb4k3R0NEFeo10a4Lh3lEcMeHGSwPvOxiyHb57BeURWcIzOnzkXs5j
lYbKT/U+qJu55J9srZ/Fb1HfYnyME2o+Dsubhwxut9CU66ejetfDJ970xVnHIX0H4B8b46toxCUM
HsO/KFQ+MQoBp+s+DJFrkpr6WZtmeQwdF3nLiZ1EkrxCUakwQms9Xd5X4+ONkxEw3WLszT+A10PE
WObzZtU9QOzMfTgJhKnrl06XozoM0VjA5ZkQWcWYxHlUDIPVzvuHZL0Iubpr51uyX7Fjgb58mO9G
NSPNuQNYbaRQotPcDvC+jjpgY1g1P6xhlruiD+rsBfc5U3hb9gh/robOOQ7tJMW4NMNldMe87qny
glXg5UbRPsMbjyTUSfQWnv4ArOhmmzogfXsDXmMNMHJvMW27/JWXCYdYXhtOmmPQqpjTLRqeU8x3
FIWKB7rjKylyxfmPtu6Dih9tcs2kbqzyIOYui0J1N+RAqBgprST5tXsGPUY0z0CjKZ8H2YWzFRWV
ILYUO2Mr1JAjwPNq9jBGRAoHMOUsem3Xr0kqUWqKVrTVfz9vElLz/i97+vAS4xPEU9cqoUf+UcS0
iEMCCZnBRiYZ5GXOZoOlGOp3Dt8SLz3UKThD2LGtIRtnv+R/Tt0R/4F/3UhaVnZxEe+ELbqIQYbn
Su87EWYRy8pCrWSAD80e+SGQ2TxY/zAp0MpGw2DeflBTpX9rxJkpnV62AvtreA/c98768LplksAJ
vyl3GGlb5BiDi7lLd3poRyB+F6+OryR+x02sO94lKEvsaYidpgBRE/leYXqlsj89UBmEmvWz5tYg
uRGjVBgtF93KQRGrUOff7IpOTFHeoN/iu8LAmqcr8lg2YLBSRB+4QiyshMCo+fMeMa7OkNBw79bM
bMt6e2yH0VPxEQutOheqlFcWkNQfvB0U54bBelj/3Fuc5Nr6a76QP2JPXIvSWSugQ65sRpwL15u9
RjZSl2tglSdrakI34j/YP/uTCgp89PoG4P7SQefmOojQPckndEGOkP/qeRRVbQ90uS46yWH/hGCT
5yjmri1L4kltV1arOcIi7ng6mgm87qzwxmihzLzZJLR8lTfw+QXgR/g6lpxIlC33uIhcqKMHHP41
t5CerosRahXlcy70zwOZbne6nSBBXoLJsoOc8i33I1tAet0qdqKD/N3S1wKKdtff9U+awcXDGOKZ
xo+ol21FG/0hR22PYBAwCnuYzJd5C1g4eCElHbsngGPuzuAWfM8SK5iGjTmZao2hmWLLem+Il9Pz
u8m7YOwPkSmUUbItV7yX6b0VOOWl/muErUI9Kbm1pW9dG2e7JsKbTKC+Wk6Mg+c3fOrlFcirjMmy
Ro/4Zy4rKcCMuG9tEJ6VOZ+9DAzvNPuOWFgLceVHJpCb5xNZThpRcJ8MXt/141OHQeQZO+cP4Lvj
oisWzS9Ag5TPoIa1JtCTkC7dJLYNx+RNRF/iD+PJvYd5jch64vwR6BPu4lNxBKbAnkOojinOxaPn
lHHph575prDY4tBTTwfYYfNEM2ob8OBtuxKzw7RrZLKnCME/3C0LHzKYipe/YLeZPuCIjfAn/V33
rnxSNynWIvMxFN6DcfPmjOH4Lh/E+xirbvWF6hrGL3Oj8VwB8Aw7gp8WqdZZw5bU4MCj/VLnYN+r
xFBbtAjAApvPMQpLjRiRyuj/l8cJ9OKkjLgqg6JXrAXZY4jgkaR61PIYHiDYLMyup2DAQGS3ffKq
8nFP4jSjzMjc0wSuBR6wY8x9FySOwY+sCOUJbGRiFE/RDLDKV7npF9vuExd2P/mnfnof7pw8959e
cVkJSaf/Kbf40w31ReanEkScyMw5rn960OQwAp/qFjicEQoy8CQp+syOo/kkh1qMRYN9UpCMDpXt
65bg30RPZTthOT2WsDGJPzMg803YvOTgKdtEZSOEGeM3fWUPhBrMiGz72NtA6f2W7aZ/3lLLQ0Ey
3Y+I9T2SOog6OUgzSF22PVzg/BCEhwudtWf458kgBSyJt9i0O5rGW+Got1v0TFz66rz5PR+flep3
Cxq/3k39zAKTJ1YHuL29kh5W32yGljL9VLh0exXs1eEIm1mul6+zEUzpsgtHjC3BpiDNKWU7YaaG
06nhVg4K4QN2QdVFpzo2MxAJm/3flfV71+cuEQzUJ6/Inqdbd6aZSp4N7rzVdOT5M2vYglHi9V6K
0EdZrA0+nWbq29diECITzbocDnEYYD/6YaNSCgFD/MZVVGkxizMCw1UoDsMueEsLS2iKCKhhA13m
lZ1czCLfdClDOMPL8ZhoWbfEjiEVLQuj+bwAnd2N5gDPz0kK+L+ZmgCrhhv17uNdYh+iBoaS/faG
imx/T7Q3OTvRIeuVcO+/vrA0itQZjT22ozIse5oPxjnno+l1y+rCNyvoPQyOGV3xjerRy1xBBIcv
84yB4crh/F9ksF0O3fdvJqg68WaWKOQfczm1ggwAejzD1CqWTtho7RzqkkFmxBc8rJDS7UHPINcv
RjolRTetClMI3JObwhC4txI7UwxFeS/PQhsPHANwkcyrxLkA+f9WEIvjgjXuXjKpics7HYMhsShX
UBJ9xgXlfbile05w9FkvcITovSxAvQ6nFeDM9Seb0+9LT2fZv7alenKP36VLEUosejMMWde9LObH
56IoqY8yIxcV8sUrF5im+ZML2bIkG3I956qSRJdKVuSInhm58EZpt73cH00nmE6JMnriGAeIZqGM
a+CHkxDwBAZBEr+rg50micgM5GSTL8NKjRwHVYsX7PQr77ieucmlQMZWp+cPdqCQd1HA9jW1NwK2
QxZfEFrKeNMP5imxG9Y9qYVkxafOc64wTDenNnGfxccHNSUh4UryyL8akf5bbgHzEJoaXBa21xxZ
mx51c2p5eyRkFyo/95RDyKq3DmR9UpgfWzyO679bzAoeOuoMnfF5T5kwG9xwLrL4BtEaocf0Lv4j
XplSEQNd27xKb7qprwFMcKsJm69oWWLw6jchU4luRb89R8a2fyAuorzcaO7Irgtnxc8Ugw61IzCJ
xGcXF0YnpN/ostYTWbv8z20x2CMyW5sPxYK5WBRq2WQLDFk9YhOOMlgV20bowjntB5Ijry4RAeRy
B6O7io+43quPdcVPBBQuZJpPi5Z8NBlm6HvDZ4bH0XcTndMNW20kSb0bZrlHK78gs7UAKnOevCSy
+3hKYZZUcyl16VignBy26ZZSRHUYxAeuFE9PdFt5t7pJSu9gAlLQcjeQMaPvH1D7yBsXB3BHmQ2i
F5AOph+ddirFzL1pGTK9zWDlCu2VKBuLoUhvL/S6olaoXpZ7yNg0WpLufFZu20YnbhPDXs/jz2xU
quxoI5TtJJL3sxYwB4Qh+RSfSSAZst9OArvhGcqYhBkZGVqVn3Fh8MmNRh5X13iiSN9I6CQJ3JuV
umeoiZ6oz3y3nmd2ezxR2sbQSMVxGMCZyTXtemlwGqE+8Uia0TiaHqFf17bXckV47Drr+hlY4ZQ6
1eiFj7eJ2yt0feLm9gBnvHeA2x2S8plXswCcQrPQU8GgtOpsgcYp+Bcdma9zJKILpIdtLtgQTieM
A5KGNNRwBrruBaS+4QYyrrBvzYj7Kxjvyo57/9cNdUyXjMTOIEs/OQ/pP7DtitchSzF1+XhMC4v8
umNw5AsZLaGR9nSwf++2zl6wFMiFcDUrgfQNs00hK8QNAufzLioGIVplmI+h0g8gHttRN7kDBY5c
UAMbpn70SXyIHrT76O75aJSOmLKZywy7g/LlZ1wUaPEjNmYcuzcWWdy0L0tIcTeNpDQXEAi7VAfL
gMdhlk3P+xrlprhyk26EhMuoeRnti4qz34LczfW55WLRHRZLx+CN/XL9j8S3h0+m7S8zfE+Z2KnF
Ff2bUZNfa+5Zn92+DlDzmWEqq8ZTJxVDBbruuCGhxhBjgW2TbedGtSexE2U8OaMORBoIlGPZ2z/u
4dO2LTDJRUxXs8eM+Mxwi3R72JxRBGvwPbmF+MbBugG9ptAEpf2moE49EHEn1s69wY/MizEviQMJ
kJW6tDv6eWMbwXTH0TOEHI80ojSn4+DNv4RDbYRgGAOZJR52U9WTcyhlwIyvTY3eerPVadUKLiRB
naHvAEcMVP1HEJ1iBOzZARP4s3OBxFUL5gOU9q6e3lMjeWrGpC6gYMAnZgr0sX+XfLEhWPVymLOj
NURVlFWOd+q6HLBcRCR33JutBuBDjM+dR/Od00AgrM1VtFoPywF6VqwcCOmIdy8jB1TRuW/wNUWN
R8cl+8a6k38ZcUJqAdFppkdiejAAt83qe6RRxDykJYfS1h4XrLreymx1Ob4n6E4BCp8xLBOkEWro
eD32gFW0t2Qft4R2q1MSxKZByNxPz5CnBNufImBm5KR05l8rEpUGZQ81USkAvG1IOCBtdxajvqzB
PT9443vPomEDBCNTaPzXBHo+Zsrm05rb8bJavIpVF/pD2GOh2Lgd+ehdjTSicfmgT7XMccXNBFwY
hgmo4ykCE1S3+o+fRtiuimfbDIDAFZPwplGOkD+h5UQ3mZotVPK9hhWUwAgUFj3VlJk34apoTE9s
e57e4e7PqqQMnhlP8yc+FYPsf5M3rvUKRHbk0jBN08Br+nNsAfv1/5kkBw5GA5eZ0wGuAzDykKus
COcIvfTv1QMza+qlX04GollavVsJLJmjpzIsAhzPqtmyUr8NFsLKeJqlQLd3sVRnytvbdARgH1r4
qm3ZwKBQ11kQBdYUHO37e248kPo8ZwjvugqKqNJopXHPYzgDdxRgJUKIXnush81DiHkvdVDfylEN
5hHIg/LF6mC2IpRnUMjZcae6lbjNvhpxY4o6reVucVvf6u8+fiuW+Jx6RieEb2V4QJ+dWzvXWAUT
CztXHbtfEbvOS1T2myuroiKE8hXqQjJ9fA0vQQBRHTy4UY6yzj0xmX5zZvLUEDUkbvSX6piCTQBN
vTgex2n2kwk2XiXtxDsTXt+fpn1dFGBFIF7ZB9oZPHM1STVVcGVlegPd5fOvvTuvC27JVBXTs47J
HVhzL3klStG4THMR10HithIk5wgwRogkbGkqAv2iHS8a5od7wrbGEBVX4e84NmCbcLDLC3NMvur2
bCVQjV1a/X6HKuSWbCOmn/Wbs0B6Y2u7NDN57u8f/mYEHkkV9CjpTcwhhc/BOqVStGizo6Xcczml
qZLmvANA/e4erGC+ujxV49J/LSz3PaxzB4jaSRETSc9WzFIUdYvb6z6/ofr2Hto6qyXluoy1Rml/
AXhpR31wUpjE7mfE5rxDX+RaxQnsHPUlKSjAa/0Q2hL1c0MAbvUDknKPEMZlsCpjbsu/vMoRXYYG
BExRJcGD8DZN049v9aBEHr2vFb1exPWhhGTNs9iDpFXMi1lq8VEalUG87tis9RTbTxPIUrndI6/B
FuiA+XZ811qyQor6Dt5eKXB16qRhkMMuXJncl6aFFi5yiYGqiTOm2uApoU09cIZakf0jOwCvsMz4
VFMbbBgUUhK9Vv6tn37pe2lOvhFOv1zbyWEH0PVtG3h6qeddtohxmlZzMvny+2kf2v3N314grdnC
Uy/WO9ZKwXVOi1Lt/Nm4lXFPhaITEtS/JWbikDfjd7OkD5EXlkhY3WTAFtzTRAT/LLrQEY88MAsg
jAK6B5OxQkFstMQ5yHBGYuVtDZ/5P5lMqN/rWRDD2irh0jvPQ4FevGAwMyM6GXGwCjLkzQ87+3st
3iVDt3gau7TJOpY9sjbEqe65fLubPdJv8+chHyyTXcElCvtDuh9o1ZtXdOR3IYqWqgt/5JK6I4/M
Q6BNNHXZtqkgHHdhlKJgwvaLt/n3V78ttnHLLrh5LXeFXzz65GgGqgSNLx0JWxZfhAWS3FbnOVbd
dMXudQ+sqNxp+2YwxASR2On4T1htK9GUW55G5fDBOebsEuBQiO4LyPRjS3TNEVLXkUiZqyiowKcb
O6MLqZ8bzjTFJt5DdIwdDfubaTQqFe+PEcaSVbpvJhsmzXSIARmUYDp/OYWYUaSrzA6u1kkyySLr
oDzE2uaPYuQ4VrlK4UdqDqcpieg0pni9aRkhjmZ7fw8CRHQL1nF9M4E8614xte8cCp0SdrvlDHsa
fsZ5dlZS9snxUCo18x3y3gTTAz96e2pPv6kaqMkVLSR/VjUWUY1aWtljppz5YVZ5NdevAHkEv2oV
+oyFobLpQudxM8GuQA17AnV4k5Xm3+3MsSnTtG2psVrU8s4btq77zi5hBxgUlxlkTsOLzbQ+gcEF
ZPxL7RhdbVjePLNpuZHQgDXMP0i3+jmSAp9WTW/nPStFKdQ1fnEmtei70jVw72xG3f0DthzZ1L0Y
EeLiIFrduNLJqaGmgNrui1nDb2QLbge+y7Cw/GXaOD1vt+BUxx9Koj3J6IshUYiCwOme7XBp/Ka7
Id6nnjJ1g5Q6fsxrbF6EEImn1hlh4AoHVnjjAvDKl/1erbfQvX+J+JaztecGhVTR4yoquokYvi8U
Kk+O0vc6HsonGFHg0BDVzBaGsmG7jI7FIiHdl1vT9GJycfBWygNiF1lqJYIBPZ4dSeP2ohSFQPtW
+8c2Qa23zTj5qGBzGjMZzfV5IhlnPL+ehTXJUfP0AmOX0AM25vuhl9jUWiiBtELXMeJ0tbtIABen
kKdgNJHU7u8By9kQYQ2vVdLLF1TSn2cZh//IPLWYKsIK9d0fYsxj2y+YeDqNFGB0poicQYGhM2KH
iOVQCUGiIt9pzNbOXyyWs43g/vo5q0S0uPUCOBkwqsrBPZ+Bxs0D23WHRqyjVKn6YdyKDSvn/lCv
Pn1Fm/GKssR9nqTsV8TruRD4OBgQTRor+Gy4WFaUooAtd6PsEB28gyxsZLpMtzvxygozqyv3VXjI
dfkDfvMb78YTpkuZQrtPpw/69UtzsYlJ93+/QuDaFYCQh1QzWqz/L+PFy1gmULU5rZMb54/stfyQ
dzF2VZaS735vOpfNYCjcYFAkIKq+O7mwhgk3y6NQMmsjXXeUVuV+LU+VGAFzFSGQizm3i5CPOJJN
3dJ7JemAAnjHcACwYRDMOTH8GpcQhZCO5/+YTMQrr26B9GGpOz6TqUlw/lRjE0pkK/H5zLRRcDm/
UplNoEFF8ZMYBuwPTrfUlFTeP4LsaCPwP9yJ6zibGztYRhSU9TkAObVrVZsMd+Oj5eikHbSUm6Sh
03XDroB5DDE5Ga+HU4Mr+RCjVcXUsHjx8Dr6/iWvhfNPwc6lj8//JaOoxjmXvOE69Y1OXi3RVEe5
YTZDFbPmQdVG3nk9sLTsCMv0iMHB/zwfiue6mz41jUObJ+zMRWkMYfcoFg76i7403CDKWo5r+U7l
YbXjNVmGK5ZiJKzD7P2A28c6xaWnz2MO6o7xObVb5rg0FeE4uPW0XZc+q/LPCK6NH0FDloTENKqN
CmAttjY3H1O1KKkJS7bIwAdQ93tjTdlYhT6JpH1EVM1YQL5ZBpSAcIenHQNj+fLS5by9JKaNZVNf
MecllFQC7cBfTccjUXshvaBnekCxOplzV8ckaI7Q/aqagUc/L7V79hEbDE4abRLRLHBLcSc+8og5
sKtLqeNn3u7XZi4tiME8VGyOLC9X0Z+iXpNy7fYIZeRDJS9CMGgbmWoVNa4JYOHHHqPyF5oA6jKU
1qxa+1PSe+2zFgj3wGpgZe00lFd6n31SELoHMTIork7cKGQtMcIADL9Jj2TbJbl96NIiLWSWgXUG
PhwxpB7G7DYLfXbn23AHLuHp6oErJBK0Xlc4R4nF4jPuX9a4bOzWmZuiQF37WjIhPQzjoFaTUZ53
96sLN9+jXCD1Q/sRPPzTH4h2G/lpEaBZ7IMTNVyjlh8cHoa6IBGNYfB439JZ/FIqnC9tfidkNE77
XHVC7z5+b0pkwhXZ36jE3wGTubbbWck4bltIIXTLRCoNfgKAngj1ajM6UTknBSlHNCPViPLhNGE+
TTCJowfi49JJDtelkmaEhzA3eQNfVzzm/qBdFn58NYYHx8QdK2hBAr6b/2nE5I6E/o2G7wrbghKk
Kj9F9A+BK67jEaDQfmCIv+EZ/istkal1M+kVQ/Jy/FHwMD8I/Q5CrDMRd9gcpYWB5Cs/wc3Ubn3Z
E8/FpjkwZe82CWrlUZEpPaqGkHAUQNj5OV3xD1rluGxyRwT0SJnRcXrZYK29/cO36c1u9gRAwCQy
k9Sa6ag0jNL0O3KH/XP/I3osPhLtOGEtgajOmcMRnrzz4YltizYu7wFjWnXm1GUtq6vv6s9/F4W7
ryMvHxs11/zg2V3FAMObYRm2SFNyFnSBwbhrhyg6AbpJq56RNMpkvenoWb5vQgEV2CAHxBuGeJcw
zidCbKQuRwprPuydkZmr5MY9J8ikSYsVEEFq/e8fQRolF6/N45W3GKVJHVkPlIQJJ2IAfrL7HlZq
74IWsao0Bfx1Fb/GuZnZbYyjXZXQk/DOOUT9ClTUlBtWjX4c4l7PVx8iYt7H+YODhuQzakdwsDqK
XSXV2/0+0gtqOrH/efFIFCvx8QLvzbR322heb8uG1TtUxHbgYxvJmMuxTY0Kt+Ck6jZjzGvNE2Iq
gvjpdhAsiAjihLWF4V16bJcDPyqTIruL5dAh6LMq7BR5jWFCuLEK27qS2HbmowhRK2eAiors8K18
t5/yB89hVJiK1VAnmjQP7VUJaTwv0JXIIt5f+egDAT6sMWy4LiX+UnV7wfzwqzCOWcgEjXF/Jecv
kLKaG1HrpF8N4YNegCv1jvLCFqLR37lk6Czxz6YIAP+Sn9HJB00wh2ZVv9NBI9ehaDw5glvVirla
UImOu55H5c6oo9JyHfADjr6Twa57lo6X3mAid5ay7CW+U+GbL2Ks/hvZb/P2bOLx/6jx8EAXxqBu
aEzyxmHnCbktHY5Z8rVvZi2Epj+mk/1sT82OlWtBNB0JEYqCkiiFCTLNcpFJbRTm4hJLLf527uMx
YF8v/kMEdGR4YUj496sNH1jf1kVCa/igONjA9+rQdfbOLicvBvj/m9IoRzgVGiARsL6aTsTYjUbz
iiw5louYy1/C/f+x6fEZ2FkRnzeFt9JWO0e7wlS9jVa6x3gmnmdWEc8MPiNsj4tqK4Er3uU/145B
MvYV5qpfI2SX6Zp+U5qD60aL3pFodgdyU/WmKgK4OGyXJ/AMQ902VyZIjom1/4DalmSz/vWisjbK
IuuLNtmcpjfccnQ1iGElM8l/e8X0t1wz630YBvbcwsldEDcGoX6uPcrAzjO9EEkRzguohgomTJz0
QX/F6gdCbCI+mq0nZgt2a5+Ud9YaKMQte20zaZ71eYiDUqynHh2LgeZmlVtkMWW+XMAivdRcoI/o
0kzwubQf8QkOqdv4U0XlP1cvxeRwlb/BUWsw3tOFNcw5KVYxjBJ02CxJvInKtVkmWKTnf2jDK52x
ysNQrZNGKXShEhrSBQzNGNmNEf7IzfTwTqQ22RI05Ad2fbs4tJ8to28hGG84XxWnO3zl3nNvUh5k
j5+5GB1f9eYY01119MgMAripViorZJK70iqqxy/yjWNngZUMLpCH6nD3f9s9b97VelXy5w/LIRuH
DcDrqzQEIKmLa87TRvUZ6k8HCTOompbHk5128e5AlIpEp0qOhglE9+Zd2m5hFGqQlAGpLrl36CiS
qbHzF/1TcnhQooR54VeoG+aVbbpB7feXRGLyra33nq2aoCmqAAIhyYuPYBSCQAFO1myn2O5129Yy
HSu1CqA6k70D18ZL7B73W68Q7FO41GLtmkiXGzM7SnSyxr7WwhFziBITYWesF2tWN3emTU2BTRqM
9hteLIPwILybEFRwk4/2l0HEWex556xXjM0I+acBVsiZ6zCLAJ/uG26QwtLfMTh2Ij0meyT121SU
q3PMGfhtfbm92EwUiHNqLCl2VQzPEojFR+GirZUfoPdyslYQCW6BSW6bSgs+FkmY+C4Rn6oQndcx
XnP7R66UOwy2EIj2/lVwmlTXeSgJWScUOi76RsekR3d74PRRh4TO00d8MUXFpM+3aS5Y/H+xDMW7
B8tPaIcyxlTPeKHt246lFvHrwPRXk/VPyNFoflVdbosuNHbumgsK2uPl/naJbtXdjq9SYQ1kGZRu
x+e4Q3iwaIemdfOlVF78QQdTb8lg6pd1AoAZQdeWWmBvV82zGwy12YyW3CDnmU8mEqtH0Ba6HVfq
1sOFH040882Iifqr3F9u/X28Xo1bjSCR8pCmo0GDO+I086Vw/W4BmUx57Olm0adXgDQmYj8ssbb4
tlYRknOLFr8b/kzZSSvFV9bPVs0WTetnJ2ePs3dWkc63i2WBI7izE8K3xRfvkPRFyVM4eXJoRQM2
voqgJLdaflRl4ZEJ1TAXY7Qac51nS5VmwKX8wwGnFQ/z8xVkMkpzFM7RF/TwtLkswZXN4uVQYpRA
Pf/4naVasI1hmKBRPApTupGmE9pVttC7oPaZ/q6qMUHskZYJrJy+8DW0FdcJYsSFsgFu5wwVH08J
0dCzKJw9sTG7Dqwkb/i63I7PNme0/oK5r2WihsP+GayLBAmTV7x32h0woMQj6U2qVqMz+BlX5J8N
FTpY1Jw+T4e+xVKcTT+zGfAmNZR0skpouU38ejdKAWbfR53u09Kb/CK1B9vcjtNYWhkB86lkaS07
98UdQ3W9h3rfZCWlD3GViYedfKRp+mn/Tg0onkwplRj2HgYJPKD70pqJVMs+FE63PCTTaPPkKrBq
OvjkAxBcKRpwYIgLv3SRHLwRTXEZ9tPtfVTF4WbD0fHs407uqIjKqAiBPVXlFrstu2ML/WEJRh9y
2++umUVn9M5rgrer+9xcqrcJkIHsOH21eRK90eCoZhl2g2QL/uCQU3MeijkqseCT//XhQieBEmor
5dQBXR7PqO7ibckFaoMPU4J5uxlPhFEsb4ZR30lTdl2xBsRpSIDPBghPb4a0PM4dVXTxSVOTe/3O
NdsNTc3O49EUP8Uy3bqQbf1uDgZksuqih0pr/EvDoT9sQPFy0tb7UQooW79pP3PXt3BtGowMmtlS
3rCpvGzfCZLSJf1Kd4kesXbD/vVhuVXdyghshfA4AzdNA0JEWkamEo8K0V2nGhcY7sZ6iisbsD0v
C7YC/x67E3JqKEAsTBhOrA6DnA6mzYgKsaS0d9EyOK35SZQDf95OruDG6HK/sLo8VS8LYr+77BBO
pH6E22tWKju4qvF65bJc3eXf3k/eLudY3eWK58QaRkXO+2tpR7W7IrUZKpOBmPqakWPTvSgNtyqR
3aaWy5/sOYlUUH4noSOZln01p+A+D+Gl2/z3OscseEcrqXSIPzXAdG9b+Zu9y9zJbJcSuWeWSCYY
4PKOdX2vpLojWVCCs3fPAdqg7Bwfjb6CsVnVMiSVLYJPvyupNMExs+d1bYBYsgraqTH59bRL2jTY
kwmsQ7azj/TGKIsCUtDZLTCCl0rGxYvJbreRO2K/cWYywLLTAtasVTM/ZUE2VriKw9NoPc3pL+8c
CzRL/W+0GUgs0nuapsbW66/RdMDMcHbaeI2ntMIm2+0piwoTf/FRWApRvZJxizp0cso9tzVilbQr
8Hsbqml31RpiiLLuLeJF3Wz4a2IaybWuVXIpUfgOj0F38tlcfj/VOPi4eFttncKetNbO7fL+84id
yn+pRiOuEp9qkzpPycQXUoRrwVj/NFR89kbzf73zNONfIjmwmCUEjMdt6Ds0RgLrnUjAL8vSm8lU
hsjtIxGT8SNZme6hlGKSztsLEmS9Y1JbNOpHRA7cAVcU0BquidEqO76GPaIsP/F830KKLHJOovf0
GypzdmVXOaqdDixhiECboCXTuxFRXNB0beAGIKWPScI8/QIZYy3FDTloS+O+va+KXgCtGwFoFlEn
dt5RrIdF6B2IUpDyIWexqlWFN6IqUKuIAHa0wWV090uXFLrV/D54XPXt39KdJVfpEJo1ooXqBev+
My8HUm53Bg8qXQdQTKE9Xq65W5KjayAMF55Q4yzfmjS7ooB1dkFrDapC/OV8q/kJjc/vHEX0rQKz
b85RE3mFdbjrJwphQxHg2ClietY+EN2FeANip1iXqYrdurJmKXTcj1Q83VUxjCSZpae5vA6vHgQr
bX0c3MvfV5MIzC7oBedBxnHVSxW3xkwn8dk1R68pEgB0yTkjrMvAFSX62MbqvFLtdChGEJq5Upa/
K5Y98TmjNbUie5zBV/Dk7XyAmRBkl8hjVebIx9GuLspiHdpERPMc509LlNVuFXkTEbvcupVaPgUL
vew1IBBegOSdj6Y30HskKRGqGRzN+IQz+bp4GN6wnLTHCbtK3MMXcD+A8AaeYY6bWiPUWVwefjAM
6zVKZ5JOqDrwjALbBAmiv9/JYI6IqlT3eedSJgFNvStSWuorZVE2hbSNJ9SQqDgbawU6r+J0/4r/
+q0SvaPbULGMjOHwY9nmniplbjw1x+tqC01oCbwAqO13R9XoacZLUd+U/D5PlOkA8jF90x1jw5SB
JN6dgnx4Vbg9aZRGcZHrtrdwCHFo9gxlVkZ7ydeihubxj7g6L5twSqGYpP5X61Q7H8dvBuSRGxLw
CljJJGvX1iQ6uDbKgUu1gTmUi527sKAevvShjN7P+QxT7wVb4zSFWTTBtiCDsHRbX/VIZ9ApMG5c
agcte41L9o85Frwm0aFRvd+8WaEb3QYa4BcU2o72yFuBReaekzStftoXOMLE5yBTwRKdNssGZOQV
Fx6bpnuaqe3q5MWFhYW2IOTZu6RApuD58lFkysscEUWmAhIJlFSw3WrvRER6cWaqBDCXyXhU7GjC
RPbu1i+9vlAyK4Alebm0Bv16GZ6Ev379C9AY94WHU3KQVpGN+bkwTzDy0ju3uKeH4HDf5Zuqq9N1
4LOpn87LoD2VGaRbE0bK4G9tFdC00xmSvLegad7pc/sx8gqyXnJdFsfGcRcO7000tYXwio+M4dMi
6y1T35QcAYvz1RTf+NXlU3abXStAsK9Jz+yQ4V/Z3YZSf+IStVfF4uh1fD5zU/pnGQYmCkQhJ+6/
Haw5gsVzfC5cesRHhVMhAJTuJ33dFkfdBuVJKgTXtt4GIHvtM7xZdYEHceuwW/KNR6VEv7BKoRrU
AD54NtYug1RxwpVscb73EgnTQ6SHcME+eaEdXe4Q6HJKORSgVrqViHQamqZqkNRPaFbmUH8tw/7/
GjlJNQEzmj8GCaYRde4ayGkk96xiv+Mju098KBP+zqT0QyLrbq6SiCJTT6+ygdl2u7SxeKMpSWub
Ct1Sm1GUtdfh7qCkgTvmUUZLQh49NuhKaOy1GIkuaSLlkPTa8rZPxz8nqwFGFqjYyrR5jpHbeZxI
IsaZV4HlU/2wLP6iyTbAL5y34q1ufi78U+Cg6KuK40rlXRK9kJr5kCUcU4/Gr0bME1yEqyMcZjeW
i5PMvQDRjye/9SIQQDWtWjjOS/GaOKlL6HuwWz3weN6ShFvsqfRU153qaHSS2h8aFh37qisIF5mC
nY89Gr+u+ljasK2fRxMh8dGu6GwJG/wDf5aE+Kjg79SouXF1jaoDWlxZgD+mwa500sv6bvXFbdil
y8oo/lFpU4rz9O2CtmZaFbO+RGNTUMyEUTvJ2BTONTG7TSlJvl1ytmn38e2ubW8Kj1JSR101yzZJ
fbGJmYAsz3KIt/CY2habpm9A9sz4bO08ILQZXIyKaXzgyB7W/d84Ue+TJmfepweJH3oO5DqV/mbv
xBEg3tbiBJfiZMFrnoir78Rdv5Js6BU5vqsPzrKTI383HzUQ4JA45ewXKyth4GQpKkprxeU/B80w
lFYeguRpdCR9aOHEzBY6LFfXo7PAWXRRsmIAnja0HAsdOmszNlorgBxyxMdnPhN/510sEzJ7Cd+8
JM96NP2W1mYv2lI6oCm2qn4rhp7tOsWWJE/EDrvBvgjGoAyJs0fFknPNj1pUVAhBClUbwS4Qs3qL
sUA4vBNhiAPFKbw5R/klM3j/GHlfo5t2q/rsmUavX2B/stY7KMyQtUmmrroJTgfUx9TrDgSLnNpb
e03Dw8Ho3tzSL1TozAxz3+6DuqNgCZ/xaPC+lO3uWuGmJtrnoxyqEU+TDqu9Ws+P8MUmF33MIA3G
1+RR4k+6ksUAuSrygUQIfUjQx8s8qOdyn5yz0tD9h2tlf3mk1te6Od1C1cLorJyTK1fY9MthJ0t/
oDs37WnQIDGPQfBMnduiyq4ZM9slbfOHzGesNJVVlphbGze23IAL4itwA3nYZrvVft5xmQmwcPzV
7D8qlZUPSLUgD++HDXYw8eT7QKt4lsb6tLkdzb9iNSgrvwl8Hp3LNyQaDslBe/w4PhybDKw1b116
+0jl5+eG2RKdAlq/gc5apKFBrxeN+vxe3fgzTVDTGNQJ+vCevofMRKPczeEyx8J8IZaWBFFN8DSK
7iUkga9cHiRnffHyyAowZ2/wsskZnpyiXsEt2ch8OxsIwrHEscTGLMiL7HAGtTPWgyYlx5hSPhLW
kSFZfMlfOJmsXhqVIOD7QM3zASXEJ5ngM4YDbLRm9oZ/6XTQOSEfMfEFSExmqPUQVP78SX/1wY3Q
l8xxyqsa/YndrROHsFtZqhlMkRJe2GaX1DcO/rdouJsOy1r/+V5NpISM4gZVwaT/448DbmWanBMH
sOekVP2RgkCxuRZp4r0w9uxMpUX9PKHsJe5JqUPuXS5NLBGhjnDBbooFekGgVltoaz3QZ1RNxL+/
y7codRas0VH4qPg3t6FNj1a9rapR6wZLfEjaqYlJ67aqLXWWSA3cxUQZwB3s8Z3ylnpnhtPlYcEt
IQM5A9gfXPhz+ap6pgwPb3KcgzFMXyA5iFZB/D240yxvrvlD4lHA/eyYaTtp4bb+4Z+0cVi7Fy2c
VccrfB73+clM3w5B+TJ5nDEbZ40CJn85EKi6FjVF27qWcELvaCBaIjGKwerN/k6SM7veRA/ErNRv
NJGBPnFjCG+M26AMNc+gzFHM2zrcy3vA+4H+x+xZc2YJVXO+WzZLKoC9+K1wMSCgMXeum45NgogW
Ir0OUo8m2rUJPgG0584Sz+lFSOWDKDEg5XCQKxfkhJvkCUWAiYoHrzrpkDFXjTgALCR2ORmRKGFP
5KwdagljXRtt64iPfAWq/U6cJHfHa8KpkTu5f7vGdsixIMC9TxhHbnQ/C/u6G3u26cZ1h4VjfV+5
dqLrfN/zeKVQbOMt8u6OngF+jZb1TI9NqZMR0/a2Pr/s4qUVvYRw6Hoxrl5BS0yqX2bQZT9iaX3F
nqBjv8IRGJjcTAkv83QJyPYqMhDN4vxkUSelB7rYCF1ycklAl45mNhUSNhYOobeqwT5eJiGS8EbQ
6nIvyPIaOoKydryA0INqDqG7g2VhZIEmEoEwikjZK7w7xuSr/aRgb/8pgRPFxKWUhZ56GJCWrKme
/wPgbIPQFf+fETSgaWfJEWUoCUrGwppuepLd7EPg6QW2L63mNjBSgSOyEPngKIc42tBjEOOWTw7S
6HvDVcYfS5/v4eh43602EZj2DPDK2Aj1h+VW7KIK2LwPPA1ZoIUFhxcAz08V9jSjMcIt/U9oBlX+
JQXIBxMxfY6vjbrEJF1s9AruuNHIxHLX1JyJjlMoGD2q9+Iye4uDNOD0ZHl170UQxYC2mb5eGWCB
vSLS4fhDISEZDpwqcrn7oQiYsvTjdZmUqDyAT+fwhfdCZPgbRDShGTzcWlWSC+TTSYwPQA4z83Bm
Z8oLUlOBmSuHwN/hGX3+E1qqqNMfl+xIO0PoaqCRN1nbYreolEEUgRqdSle82nlN6kiXXiPRwjW+
Ulme3UX8fpAMiUf9hoNKp4sUxuEx6fHlzCGl46DYbB+6Nd7AxZyL9FqYx0KdBhWYcV5YPCHUO2AB
Hb6qtf3QgTPfTkPHPZZTjfvsZprPizYSXob1PRHvAhxlQ3I+xCMnP3qmNrUmutPtwKL7QauaWsUd
pI3wwSOmB/IQvszfvAxU28vB2Zza6CasfHzGZ87yWSnzvNt/TPW+a2JNBhxsi8xnrgXGkTZfMsuE
mvWckI6GTKSS6nX0t5RNpZ5wJvoOK8yvbwK+5c8Gp8AKV8QCzeWCjDf/Yq2v8y/rIsjp5k8UA/n0
7JZS+Aj0K1EyjAh5Cef0UCtcQb/NsSezHMXIliRRg64OJN+quBIUmrtPzOkh/aca4AVig0pfwCeA
qXAUMz7W6LLPEG7D4A44vZdjkPoJDMZrEF3ETgUqluBHxhnNvMW2qg75hPosFuDs++yXlcu6Ya9l
OG1grrLt/z4oyyXyQkCcAWJqGtLJTotxVD91KPUdqQu/B31q/73j8K230odVBm+DN54uqDq/5z+k
snIKW8QQ+qx2xp9r8LfudSItk9linEIulf/FsfK4lQok4/C6MRPOKkkZAwhRoleP8gDSF+GAKv/L
WJUSNnGilkwv3MH9TZU79aU74TlARhiwa6nIYFs8w19sBOx6ZD50wZe3d4c8Osm+MKQxNyR//Xod
ciFf2OM8ObNVHZwlSkenK6hiN1aqmPrh4cknNao7LnoGoVm3MD5EI+yOHanh1KUbymIhX21rk7cn
dW4VaYdl06SBqNuZgzt7SjFI/pPqRnqGGorzscKzl2+Oript6h8/pK+1e6a08lm64iKmAL37wZin
dILeX/g9sFsrAS94YCly9R/j8YHz/k2ValGr+5pAWatBg31f/+csq7D/g4sFLDnqAvqFe+OrLNc+
tsqNqTASqz/PlmNIGbWNeZ7gAgkldHo096G6Bz7AScsIYA/rIgI9vn5mprOyyWfphmlSTSAWvSc9
3/kmxJ4fh4Ayjg4r2nNWQxBUIh+PWP5YEVp0jk/X22Bmdpni8VIZ5jn6fnQQ9xPqZDolvCnA5AHN
qxpd+bFJ4jfhn00SpmH5gwI1HAFw41K3+9IVfh2tYaa0I5QHM3entk72QCB65K+Xh8YJXDvcjpTF
DAoSltmyY8QRMEr5BVEt58BEk8yH+d7c+kpoE6JLjDY/GaN0/BksxcBPQ2iesNJWjY76dlUeEHcW
+vfILjbyXny7FndMOsCPX85hkqepY4y4AYpKMYctFBTjQZIWEVbGMERlm3TK7FNWfv66YOdEW3L9
2FUtHBKldxCXwbFRChGzgrg8VlgEyjwb9svthBzxYpYLuS4jaERhIxp/xvkt0UuK/PgUK91S8ghi
wh2VJDoPCJcR2cXGJ3nm1cL1RlFuzvy1lHch3pMn9EOiXZie61q9thjxxNaV2VKTYFCUViM0FKuX
2fhsT3x8Gz1l5/l9wgfe0QNi5sU687JWtu5r5lbtlxknjliyImqiU3cw+risA9TRVKiFUyUNQ7RX
oHtpJlfKWrhBS3MBJABml/yN3PpMgg4u9SITmRI5ow7B+ozgldzgTuuEeJnEpEf/kN5z+LHQYBuQ
E1dqVVVj0F/8P3mSPEl8I4Q+XU7BZXvWPXzfnOPdCJ2A6XCi6d6keqQ4W0tYEI9wdadwC3cvx5U9
bE6cddBvYqV6vw2NWp1Y3XNlCisYp+Zc+IpbY6qzhTlrTDkuxv4FDZZYE87w+/YylwGt/bJpCEKs
k6Wx6MXr6XCKjsEPhinJ5JdDKCOfbof5tdkArUlx4ZzVfzXY2qq62qzX/cfK0vhD9qMo/f/qAh4k
rK3GYi+Taxiv6QKbBDIxxJfIBjipNW4YAEFGek52gcOfgrJV2yVfOFfqN15pu5vHmbhBaenRp6Y9
dzUoVzSgKYoSpVYDmiwR1aR751LYjhPIl53NKEoZUn6uApVLkKp91yBdDpUlH7zTYMugZ8SlOvI/
n73QY8SAdNjs93r3ybPc02RpRjkEiqOfNeocEQFE23Y2BP+XcrV1PpjGIeRDGjj6T/cijlvil9Vs
5Sk/S8Mj0GogJbMqLRdrAJO01ypDzcnEg1dG0sTe82NWK1yLN3X3mngKU+N/DUSwawXkI7PTCnrr
EzYYVw0fhWGMiMZufio0bi1aVW5rv4ywHMP60s9r4+6BWDpihUcfpnmJGRuB1FipcvesTkq6va1d
apVrqAw3PGhGYqa3z5oLSO8O8BBK9egxisYGiKDzc+AVqOjMUBU77MbsuciOmlCogfh+Dvey3kdw
fuxn3QCH81cJTlB3gGwUtmDqxb40jtJT7+Gu7uL1EpBKJoHxgevmQHFOjSJqQl4Ruy9iJbH5J/fH
W1YN/lrMEx2hJemg7EczoqOL5P+TaoUwb/VipOpJ/PSwq+hHwCp7O9p27jAztEYhqbHcMXGIok0V
Cb/6zrrBpkbjBlEYdnOvXuPAGEQuWGNpYlzzlDbS9APnHkvkD+1lVFR8WzKrjguoHDf8z4dLZJL3
KLEpEIuJ2MwsCYzVH/RT9A0yK2uZ/o1lqvkPJYz2WbFKuRz4JtIXFeV1heeOejp69EqzAoPwd751
4pJ1AsqAQbvLjPvyLCqSUFmnzgq799gMXDRYnz+n5mGKwtOU9NaiK4jSCMvGpkfWVzsYe0t/r0hw
k16VOHR7RxXDoHYXRRL1K7QVPO+IWS/6xdOb8PJyz26MK4s+PfiRv5VuSYfUgAyYFkSbZRtulDR+
EOyGqVL0jmGCOtag27+vnuOki4iOM5p6FkZMs3EToAOOB2+ZUd973xtyD6kII4xTASzap0z/Pu1r
ZWEml30tjzPhiLq5gUM/6TjhusbavVlwHuMasj1tPgFGJEa7AMu5HWT1zwJQ6K6rMUFIgWn0iW3W
KC3fSFyTAp7pKQW5tqW4DBCAHzl8y2lBXlZH0sY9KytLtfU4eYQqAsQ9i1d1hI8yd/wsEGl8mi8z
Joeuj2tSkJmhpruUFnR59iI1gMe2wahTjQAoaboZhkYFdzaPRzeamcAtmNEZpDr6x6CcfXIKkO/+
pMao2lW8zsdfgXwGP81Da3WXpXOZofGx1hR6Bzo1gsQ7nYpY0JhGKS1OQZUgUr0kS8J4vkASgB4b
a4k0c+tML9cjvdZqgw3joc6ymz0j7+Kk12Q3QIk42fHPDePfDbdebBEUp2ExanDIjQ3JjK4OGhaT
hw2pg8CtwxsK2KoAVb+YFlRvaH+3oxfpAIZKDTk4iy90l7k+S3FXvLtieJcxiE059T2oDguZah0m
NqyHiuSm/eaHG/gGxrm1NYipJQmvxjI/O3xgPirxOP6dTudDLiE3T/+X1f6Xn6fwaTpvwVYInw8c
apK7/84F81reLHxuaEKXygzL1LY1Sca41FtKyymfDa5WjXaMtwffUv8HO+C0qwmF2MPD3a4Exr2n
cs3cu9iYFE9wtGWJ5+Ia9pq0giWx3W7l6UNvdzZzSDGtCNs6NXX2TIzndiHYqCkCf0562oTmIlpo
a4fYDE6oRWo1FQdGGgFL8wyD7ryOGyzcNgpWfuZ/TTGxWjZk+VgIBS/oTQME4Anss8TPiugZcZ8j
hw9GmoNSkwzwMcnzUrNliquOX39QkEXdM9XICSi4MmXXE9QdsXr8obvjHuG2NVtVx0KnfMexzqFV
9Ypl7jeCacdrDqXm+eRl/oqr1EjgudeNboTe/Cq5qjRBVFXOXl0Fq+PG4eBjwOO4uxI/rEBWqRaT
0c8WTykVt2ZpHWCdytZmfOZNQzGKTWtglR1XF8wf38z1FklIkNgiaUipjPybj3AqrSjWLqV43O6J
5J0LEOcWl9RsRisLnNkwGzTvbEBBW1fXlmzsVJ2zcyJfdqgD8RVyL0XhaiNSBCkfD9GyDkjO8mV+
TVY0f94VSgEEKzsrTWrVMdGQncyX8xOk8B15EAWpccHY44d8nflzaY2orVUIxYZnkV296TEfuC7I
nv4zWxd1tHxz5f7HUMvYoqGXQQtoS+f7GJV9xvzOCs9uc679YqhbI2kmYVSPPqXjTsgN3yaJ7pRc
O1BHZZIHCsPSzjJY1/j1/B5xqt3lAnQEFRIFXSpa30QQuNEMWmPDRrWU9hfZZ7n1YaqOahW+DAAx
WDol5XYFmdcXOhAy/kt62/0Tm6wkBmvN5WdAQjNGg6rI6B826a5/iFXO4JjEj9VSBq1aMJkgdCu2
3gwDDaxWQwdrrZXwY/ZaIZXRrOrJoAOXuhL6EOOh+rJheSqmwjGkLfpEmrtykF7QMjIt7vOHaX4a
cy6wV1XPKmqLReWf8Mqkoi4v1StV2KQ8BJGhI3x8k+C1uqMrrGgG5KUFuHHAZZvnNu+Hx/Fb408h
bUNHeKiokVGBKHCPON8KT9ODsLvakWTL7k3c2mI+vpSANqROtw5vy/47+zOVJAu4txnq32fGQ8Uq
ezA9a0IvgSYniIJYPJNWOeLoGaCeGBsqFfyS6gAsWynVT+1gUs7nilAHavwXmJsCNs/bSorR/7wC
anTJ6vlID5Dh6pAlwSaXTZVSR2V8sD3If51XCSLGF63xvubPqyeqmmyYuzxjdZZhFyszxPrbgL/Y
j6pbDXXbE4xYWENPQNf6WKGH/UqXbPPiy+ZsCp5CybzZa7e3gZdfnQ6V+LJI6aWyYG2to5fZ+p7I
sUoXv6yr4NBYkyTsax2ziARaZjs6HY9eoelSu1tFRJmHCYfEblhz+BuhkqmS/M4n8dEWDSbOatF1
P7SxGaFDWNG3nh/DEgDNsx03dZJm3gK5r5cK+Xpmu6/Z7uNEiK6cpfFPIHAk7NE5ky9x83NogkK2
dXTi16Qi87AlhvbWtWYtAnEeJmiJjswBGdlaqhDJn7tFiYP23AUrFNdV1QnQWKj4bgZU9yrMBikh
w1LTd8ImD7Ysr3vBJobTTr1/Ekne7nHdPRM3WS5CK/eeqPSDlaoFRV2ik473ANc5bSe2yfyHasZz
m6uIg4Dvx9jwVekXjLgDlfrDSDBdFQTaOUHGQI8tOlLa35F4u/YsGBcsIo6uvzZhDUdyEbG3Rhmc
y03Q6viLmVh9yM4zN0nhZ9/dqH91CoW19R5i9I91NhVUZ70DggS0t1XpGVO7GXOmAMh9Z4ujBXOI
V5wN0cqURAfTsrEWgcqRvPKI4XSuCkLsk8xV1rgTHW5OP7n69PHNP47ENH/EHayMP88cu6xQNcM+
+dIpYL0pKQk4yf7sudqf1Ae+4w871b86k4FBvDvMLmzgzIdqBkJ39jg+YfRX0AmtHPW7/w/clC66
X0CxPGxnQXBk/51OseFMAT/ikKtsDR2IAxCIgGFmJ3J5atgWedgeS1KoFO4BypaKN5CtYqSxJFln
mC3EFyenkFU6sbP9FVCEwE8DRlzqiTfgbaXpDaPz7YO7Yo6x3aCOjxRWJCpqBZH2lJKft91pjrix
WLUst4641XWcv76SKFdAE1XFyHbv1MGS0y9BNtbJZavwP1ISS4cxsYQAtIx3wxycbKbBXjzlIeHr
r8lg1xXcsHytfIwIvlLtiunudoYeif4Y+d67OzXHN7AmiVR4E7Fz25+D6/gf3J4T31le/zJWvCjs
FyuMIEHmr6yXTWXdkIvmSKA9k9xj1JBSjd9TqzIfUoN9jBSL3ykQ7mjbqzViVjEHCuNtbTn3BaSJ
J+MMPi2QzasckyTmJ7zf0WBpBfPWuU/EHyxDpSLMptgfTa/YD3JnJR/2FuN/JLeIETYYW0MYWZCn
GjfsTrJWjUB8Yo01Cr8+3g2rB5l6Xu9hK519VKiZN6laZ1e4CcXE6X0Iv8DychlTLDYYHl08/es6
o5L3j9r8y+JDdAES0ZMCILq1Mq2KNSg1Yzt0BTE2+qx70knp/XTEE9XJ059m9PUvlmJFpyQ23nQH
AKTAIM2nDZFBBTZJPPzIlMQ6g0yeM0/W5FUVhio5IpnDo5yhi1WIDL+++eiu8CoycqZp/PI1KXr9
ppcxO6Qxr44S9CDYS55Si9nzJYQAfLgOP83Gx30IXYMxLp8MAj8BE7fdhn1NGrMq22sQco7GP13/
2GB9ktpXEwBk6bRdvySfuZ8Hgi6BcMVIrEAesHhMnUSfz9jJrN/+fGpThrpVudFIIxRBzQ/NjwaE
5QY0Fd0ZeS4ZTrd9MNNy5atnuFhF2mRggAssaCOsuhjlevaYgc5M8JoQ9LLefg6w7X7jLtFE+u8v
MtEDGql194zmZg4sdwgM3RMrAuUiGVoaE+je1OhtHhNYO4wIGBR59BtNrQMW56vAlniOCI83v59R
D0wIecWICeORR/8e+hjmP92dVrQ71Wgth/EQCu09jClmdY896UxWf36mGxYU9qbHbzW1tMvhRrL8
NauIsf3hpdwnV+6OXzSpUO6WrNIJwZHaV3QuLO95tWeLKK7SER6DELs3Sd5UOZEO+KWAQ8ahG6bG
C0cg5Q60S6ChOIUbHhkN1Vk+MdY4kH0ZtEBG/lv4QgTsTaJ21z5TWVArRE6diBkG8dfBSrcmuIR/
PBIT4ozig91bIr61Sjn4t4fEfC2B84DIPFD+aSUa44+01R90kGVf8+igexzqs1/tB7jDnNAcboXF
wIK8V1inbTQoSEsRRDDKCXrf7a/+WxCEsz9NlM7AJQU3CARIejCHyAYb2ra2xbPjYrXeTOYvxrVv
9fnkbnWiP1oK5HoaJI5LTTTii3unqcTVdZKDpunSwZXMvCS/FCZMKPmNF0hyyu8FYvIl5lyHdZND
Kq+RBgwCHeSEsdtKSk+vULZFh9Y1jj/81P9PIGoN1jpDZaYCTrlfuSSyz6KdN40Y8Fha1oT/HFJ8
lAVpcNAOgG15I8OiTIzn2Pw/8tmxA8PZnpICWTY0+tUhRCv31++QY2tROsY4PhGGtO/FA/6hUyCH
uupQZaoSf1I6hkhanjKjVsELHnGqxbCgHOqW02/RUnKgq4LerFxg3Ouw8MKEtIx2aLlXZUJvEs6e
jrvv34tWOZANflCtN41VYh2DzgjNE7J66QdODm+nzqttHYnqu7pu5bqbmECttfuy6kr0G9S0Ezxo
WzKOg7O8mn/7d3+N+IfwPW0h6Y3KbOoBLpLXIQIEV+u/DaaP5EZrj3KQCAVMPehMIDDEJZDCrgc0
ufrtSwrt6oTSgxmRKnI4oZ0HD9WDwAqUUoormQPqRlXtiWbI5wRW6UpX4zTLN/kpEhKqgNtptMOP
AMyFwJIU9SJdnwHwTp+eDHgLdO4n4R9lG016cV92iBS+q2PeAkwKb1O6dA6ezCQ1vLm76GF8TYwO
3Di2YMk0KYX4bg+Uqr2kIBwtEx4Ipz8zruwSUAkaV8qAPBAFCe4JjpRVqVl6iYe1YjkLdegqnKDh
izm4Dw8FFSvNhNnBQGfjng64a+FzbQH6tWbcpCgAOr91nmvs5/1owL2feyuMnGhZtlSDW04whrSl
z1zqgB0AuN3VkFOt7GaV6NOMC23SkAD9vP49WdIV1ah9WuDp/Afrvc5HEIZKca/DAkPlEJZhUsOp
5VF1DYUNsfNO03A8R+kGrCLAuyeg2+K5/fcaQtl8SrDm4sDjWlgsoqRWQUuOvxtgqULpwRJmrFDe
+tA3bGTh9nzkuCFTO8lJGuxxK+9QWgXvufQ9WJf3m2WI9k3iOPAArB8LU70GNcAIvYnGOMYIbhuJ
LZNuEH+zrt9WLHqUdCGvTNfPNPLZv0G6PqOC12tIQmDtetjH/MNBDCIsrmeUsdRDCfHI9uMZS7cX
FKJ8443uvnpo/pw/FAGW3UJFjYvdUl+b+EmjW3Fafav/VhmS/hTdfkI+MrXiz/FCwht64jTAPfyY
lFdNJnZU6nMkIbSscOm6/P62gU1AWrkAnyPs0QjawUdFQrJSNXYnMPP+ECCeH7YP2DLsELDwjkBi
Rm7oA/XDryTnI8sqJ8io5Neg0O6uqvYAMie2xFX3BuxNqX9T2SXr3Yps4WnK8O0yfc0aLeJTRjIT
wkXLwmKZTWcsmt6x7MufLUAs5DltPed7s1aaefciI4MG/gJBs21Y6K92J1W1bhwEPeSpMC3D9f0o
QRgT1qotbKjBOiTVa6nPoBRxync8SAgQkX/pbskGmeunO+swEghqdqe9vtMI5j8VYLY/BGJ9hwfA
DwNLMF6mztRymRGLeqT8Zl3XvnllPW3EBEVM8a7/dSpOu7IxNSFjtp0pxkfyZ/NJI/3xF2fLqs8x
CNfklwJFtIk50fRaK5DhtHUbmyIgYkGSjWUUP7RuY1YBc2sMmAnM4ZJQBaEwLLnNOqOuZVOXnEz4
Yxz5sD70yyrKxB51wlIIAU8AuPBlQCpD6e7xwB1cdIg8uHef8TMXwiahOHqDvNGpVOXmRG+4Cf8a
NcCCTEWyiMMRdwuZrvDFVMVVHsk60lS+RVJWAZdUe5HjrKnegbglJN6gFEH77y9p0QfLDFEljjsv
IGX5sLb3bBNWmd0b6I42fhdPr8kVv1QWWhJLWm4xxAmuId5qwKFylAwHtp7RoCDhvcS3+qmThJiQ
Cw7YVSkj7ztaT7wqtQGGes8Y2Abn40nLLhtwLnQdPzfiGEo2edxS4Z16/nyJU4aYY6winTb64b0E
DceJ6D6b/ePLI8RchmK/USeGiuVxn+FsXfEug6hlDpy4xrz+ywNnphJqkqZ6qODZJhSf+4vB+Dy+
KdobPJDJdj1VdQeRQ/FK+ZPDZ0HLzKjKwPoQGt3kfgJcEPRrP77ZRIyhcwuIk8Bw8deVjoAgJ7o6
PGYYaHf0VDFaVMXvlQ6ZLZggXvbXBw/qxefQyAJEN/rgjsNZ/wUp7H2BnT3WMx7+SWMgb9wE/fT2
VrRNgC4q7B1iSEj0k40DE337JnLiginPdIu5KQ3ps8Au7q3jMfkI78rdJ7XmZuWqANJ2p1gUMo6K
mdeDCqp5UQ6YiwaXJvmcuhxpV4MUCVAM1unULDYq1CGMU291EA9ga15ZNNDTJuwrdbDJ7p3+BASY
y3112aUcg+e+YwjieTZKlQzT8p+/rB9/mDwlMIqNhjAH3aGFo2CSlX7ZyE5Fpv8SrwoH+Ry4ZL9X
S4JIiD7EzZ1BdoIpl7fEuzMQsORcouNp9KRievSaTRLMJljY5mbOfqGBtaoaMzcO0+MHVrbjfK6E
wg95eSIEQAIMqk/R6STBzChhvrE3g0EyejnVVf/CWIH+cxn7+WP0jAN2MjQ0cQAljKK7Gyhi8gqH
T4bDI+9ap4yqkwNwjJDWCMJDp1kMWbAElQcpTVEbeUkvGNu/wJZj6kL/CrdSbGTMMhEhAJc5nriQ
d5lbzf3YS8mF6FZC35pNTpaC+pqjAyuHBNcFgocmvzPCw+lOETgW7319aXVGVu0l5H7BPz0n1899
ImwHHp4W3KV1MAj2kOH2O8Md82a1nUbgv25CLHtY+va3K9M54ZMoPM1EGEdeyJNK4bPo6TKodUn2
7xMPTtMksr76CKc/u/I+okUSdRp8kXU2Ce43yLtArT3BCi94YzC2kxyE//cGv+PA7AqyahYDUiRP
8QsMFgGB5mI+PZm9ewQFT10IfRQSM6Z3ogVst1SRthI11Q8f5O1ReCm07y2OkfXM7JU/B85OoRJd
J77qDNnIvIXHTYUqT8iEUab4DIL9Dj6Zlzfxvx+fMvM7Rt7kDrHvIz+DeIwWX9d4MO9/fMAfvSpZ
/5sKmaePFfwcv1c2USVYPZFcdo/lUomAJvuZcwlsmOh88ur+WnC0Nm9Gz+a82qQq1NV1x5ydMytv
Z8NladOKFVr9HBa6ZCg8sj/Q5B5dY01Z61Ufxu8Jfty7CGZe07Dkf3WOxLhbJmyUxa9qLsCYZWBU
XLd6sv9qsvCIa0rCXpWDM23yV3lfcdqORu9437b6h2OLcul71YAVgTv+fs+7hvsdoT81YJ/HRFv/
7yw9+2h6PYle5n6vyzEpI8zp+qdv7Oegen3s4lnXgqgOUiYw6RBAd5QsTFFs7x7NlhLD+dAUudIG
xr+6A0EOFAkOW0k1uLOho5gHV3ENol1XK6BVv//ipr9w+PT6yapAgXPZSNJg0GvVWHi6k3M/3TBf
73zgMu/uKnmzDzbKS01eH8qqJwum0zVUV8vXqDFjhlP/LexB5Ffq4S6vYWeI4VsFAfjRUfOTMeKQ
3kUgXsszv/xxHcJKWbSLBscPxnToxS8+cPi6JZ/iDhxud4gKjlaiCdwZ+gzVv5eWhTSpxwgReLQq
E0f22mFkP78EBaG3rmXZsQRF4zGIV49rvcgdRBxjHySlQHzy9tRuMTLQW9y1djMI3Hv7U2pU2i/a
a2o3YHhd1lmxWGGEDegSBvhMUeUgEDTpPnl+ACEShNpkVJTSpX3Bvnc0YKXR4/ZU7PX+vbCkr8lc
4m3diWmXQr0uxHBVsDVa8QzuB9GlsFQxrf1LJW42PS5zvYZ+vRRx+/hW04fAyXGMoTsiKKuz0hg4
wrX9t/Gh7s0+m0GkqfKUg09Ka9Tpr3iXEyHO6YQY1+4is/zm7UZNXtcI7BnWwlQhNB7uTq6jzERM
PL7+82JsnScH418sDuGOK57rBZoLB8KajHox5VjGAkNdPIpiwq/zOiNLU/QbKnF1UK1MpMbJx7rZ
pOTJ+B3SDVVmZde7mCOlJ3IyBsM5/UgR3EWGOoHmCdIAW6JxF5dg+r/3InSOk4OiarbDwBgVts6G
idIPVHWjPY4dre/sY8a4cBrCRzYNerMFqsV7I6jRdVVuaUBWE15Z24Ydr3UQSSEPWSuSCXnBKCaB
rQWhwG34ccHT5iCml6GklQIky/x8mARbsfFwlsbLFTJF9gB24ml0osD4M+Z7q9kFbqarxDkCa/ZO
9mbjty63/UTNAzuibFXnkQiEK1O9TFHKHhTbrKwZr18JKHEW40x5EmxY/H7OI+UZG5WfyWkuqn26
kirjyVfBQdyQkphqQL9mKqZVSyK0o67JzasznRZaiINEpfLYcUgRDxFCPITST6UEe7EknKZlji2B
MuYsnve4qPemDVOV4INbcHNbqL1Fw59f84U9fZxphkzU0YsLBTIPRMzm9mn3kOqeF3RfyzFvOZT6
jTQ5Q/VndPBPl2EIEudqmJdOcdCNMXkWVbp0rp6auGmVEzTS8ic8ouivF9eT7zKUdUCniiIxLELb
VwgnQpMHk21Noy3giSQTLaQ4nU5pzG3qQGywzA4+hVXdQ5AINSyp4+DkUkRFlDxF2GQ5CbBOFAu8
2RWcuOcMkJuCroKIbV6eUPEv9UFgNi5RqjBXapctZiEac7+ZQpNEFx4vDKqcpE7mkLrig0a3k7g9
2KYeVNlED9sy1ILr1shrqA7J9Lv1h0Uqua/kiKrd7FjfvHUCElTOkb83Ea4IGxhRWa/RzEmICnF2
WS59O6FQzw2nC29nBmi1RfkeemvzLcgwqrmp/5GkaFrBS9bZW341aSHPp9B/QxxT7DDhwB0ypK0/
5dMyAWHS3Mkvts3103R8rdi934h0UG5UN6KR9PzFixo2Mjakp3k8EW47M0unqo23onT5ddqIIHq+
4KlE54x/diETv6PW6NV3lUh01L/khwpoE4yp7rLqh46iZFwpe0471MIQb/CBei/4k5KRcXL5xR+F
S0mjTkIVC4Y/L18uLmUEmmTdZoALPrFzBgmBtTZOEt587ZYhBn5lwkAabE/IChTDZoaTD4Qhdw4Y
HTABo94RYB5bbz848mKExD2tqkp7Zan3GY4hYWWJA6XWkmbOKpJSVuu1td8jxZLIBcJkrpMn+iOY
sS2/D/NSy6jaT71A0B/EJ7TzqCpLUkFL2nHm5DfBqvq/YydXASE3ZquJYll5tzHcPAKjdrGAdjS3
mNq6VFqCN0vb2I9TvyYyACsVz1X7gkdFKtv0g7QOe53m77CaEwiDkenGDcSeDfHx6dmwvA==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PCm2fNIkeE7RqN1Qh8aDBzSz2JZdHrSd39tfvplEdg301UYEYTYTh7LAGuyNl/IWzVtXy/8OLKM2
jEsukhpHyQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RwLRXbOkAb7oBKsdG074UuSXcADZ7XW9e8TFDepVg3T5gHDHlCoCkhWq9htKPblu7CdCqhJ10k/h
vm6kCixqzAf7pRbi6Dd7yD8JkHHpD/JoCpG0CXkR/YkwyGacxzBT1e81vN7QTqojdxa7d/QRyQC+
MewlL03luvuOMVsoYDI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ig+L+aUsv/EyA85z3weCZqReauEsxoUG/dQGRFaaA5NTQinUnMmZKRSCqwqjwKHtQvgCVcrj39nv
BvmgbwrS287dmW0ayl0xVJH1ZBO4m/r6tWMGBH+BqwvlJuYzwDq+XuaVTyGzQsJQEpn3gOGPS37n
by3PiEpwE8sEJJzLmjC0P2WRWiChNAhPX68xR3rPYA1v//HykKkOMZR6FxpbRWStkhoP4ZXtekka
MT+U1HqIsEUXJ3yu9Lv53E1z+hITgeHqLQuoHDZxe/vo1aJp6P7bfmUYBqKcuhtfI1+q/ROLWobm
dwK7BAzmKU9Op6712saAT0JuiaJqDfbDYUHO9A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
lsIBIwPgIXnrlbB1KQUAyK5Bmb+zT58EQeCjYseHbFK6kNgAjElBgxkvBKz1ldl+9Q1yKo9moyZ4
0HyIHRAHS95K/FmwvZR8HN20nLUworQZNn1ZSc4snrj+MuW4LurL7+bP+fn5i/mEoYRMkwf+hLQ2
pxb0CiqXIODA5ZIP5pI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
B4T4vMluttJXNdEAWlnoeDvXFlnigyOiQxAptjffGiB+sVVUpeE4ItUuQIRNPONjqpFlyqMY59aT
BzHfGmB25cZxQOUUdyiY2I51XOBeohLT8+YNLywsTYYY9gjqJGsNoMYGBy1/vYQ1yDSpY5QEuAHL
HcpPLsR9S/YaklUk82wT85wlXBEbo3w1EX2jAIcHHgFKDtVpBBrxw5WWxE9wckGNsaRnIB7WuvM6
U5XE08mbJJz5+nK1bcsOtBfGhk+0ZjdLIH5Pb5sAhVUy9iyG4VfJojcINLmFVH3IsTL+uXTZoTaH
qqG9CnqzsOurHX7xzG3E/qxLQpSyspS9D9m7+A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 49984)
`protect data_block
mEBP0ABPAZMGPygBZ+3A4rrfbcXqoNm9XAESvAWSw2wROhWE1vjZcxWrmMh980Jn//D0gyiz1zHQ
yypszhP6L/3y5GJXoUdl1yQM/8cdPXwRLwtCSeFQSGFegp7gvVbBnYY66DE840VClP3gmYfvdfsf
1/lKB+Xngsa1uSzu4k3q+TpXHySJBkRXpeWBgtX6LsA1Xmn1A0bZJhlD5cmxneLqQnocwsx1Nr/s
+iEwH9W+5VvEM+S951y0F8pYthN0AjbmetzsKxqx5GAYYXf5zTk9Y1QUHsV59QfBUCjIPJvkb3Ux
z5dw/py7kykH66Zx3muyyQ2w+FnxR0fQVUzgeIphIIBOU9FhL1OQXAg6vHeW0K8g3tt29xFRJGHV
R3b+uESIGETq8FLFR7H90FQbQwxYRcXG+QNaBd0N0c9eZL8hqw4Bv0mkk9eo/zGufpkVQhUf+9+G
49GBylNHxrPjrgokQTUEmmGvwZ/viIsi0kv/OXHUODXOZ655XfAjcs5JLKpWGGA1n0TNEIcrMb0B
U7JMrLpPuV2NCH/+yWcyRZF2Sd/IOjxi7nHGTTcxs46qNJ4V96YQk1jZyaMLovPOHNXeOFomkplw
KnlnvjkB47WovM6h6fPfOXf+srjhIvd7LH556cZr42oVUCYKWQsLM8+4YfO/QCidGudZtYt8Zvpi
i7YqZufjmElH71eMwURSPaYKufTN2+pT5uavdsvCcNpoHU08eemyblSkpZGhgdA/7Aq3Lan3thWg
7Fe4gY+cO8YYjNhh7DeoOsqOEOSLdVFYkJGslOVVCQKeb2RUsDL8F3BHfJAZjr68uCglmL2zIhfv
4VPhI3iTT1x3oj0QtF1Aqc72FPPDmpQocmsZMplQcb9qJUFSw1dP1hZ9BhTLOlgGuEeA/5tXjeVR
b06ufNa4aqOfl/bflNrauxN7aiV/nCvVTMbrgagVm+Egk9ve8UH52SBoMU5vhfxJ4TvgPoZ2cP6s
84rBjOPmWhSjoQ1HQ6aso3LbQorkIKwZxHN9+tegEh0YdPLK4uOu1M96bsbZ68GBJheC42WQ+N1J
s7e0fIbe5fjlWslTs+jOxyjLPTAZGR2zaQCE5tNkPn3hvO1HNkExyDHMZE9McXnm0u54gMofmSRt
XBcon/wgOtuYKVxNux2KOkbQMJL2tJT1dUGt430GWigYeK9YAPXgS3Lw0UjDX9jOFxFbhO+lnw0M
BOD2/1/k472EiDAa17tLi0ubeIn2+vvmRo2voq5dqWdIMKLwOV80mXhZsOIANlCpyZZNRGOOOvpw
PHQN4bW0uOfqKZ4Xa4sv5/JrBCub6Q4JVnidDW1SSrn+X+93VRbDQHsIVIxtUaNPmMGoNmEEK22J
LhuVAayTR13iVuICrLnHT5qhqqmYmsUlHF9IAERi+IoroJ7/lJBcDPeRzyVW/ma4bkD/76QoZ/6g
iCxU+ATOZLZnfQpRIGxGsUhTAIBKEUUB3y0dlet1OFQl+vp+/zIAQFgWDwewFQ5E6nZ82c35+ADZ
YBXFEt4cxOxeW6Z+iifmAXd5D4W1VR2wYD+eW+utHqK8ibHBG9cIKGWrcVZr0JLDTIr5aCQBr8Fb
zmXZuakbpTwpQJSnSp4L2u5U8oG//VRdmm8Fb551zOlkN6YzC7bWMNAxLdhrp3KngvRe8S3YHvWN
hQyL1nrotNxkUQCwm/J7loCAfWiopX1gWH+46cjBS6INebNu/+FM0EqW+3Cf6eUyCQIMzliMUAId
PcqSukjT9H1rvaXpZ+JWmckm/jPn2mjDlHkWviUqWUWKHst5J85oRg393M0BI1WOk++DtFpYlkI6
CMe/vKk/i8XGI6qr24bu3d9JiyPLkZh43GNw32eBVEM8SSwDJdT67tpcGUolW7BvZoXOjyz4z1PY
/6WZkYW+LZKcS1ldQZKZsVOI1jq/YKsO7dJPuPKtI1dMo+BO1PKpJUGIelLznSF1sUrCc2aGeT7x
bcSxlDNwyyk9LxCtKX4aOJDg235m8nXmGwn3wBoJYGRAA0iYJaVehAKVbLrH7vlmMynoRvNYVgf1
BZcgQN+wCIZolx+RV35UUrD8vJj+MtJ30napfiAl4Fic5NjmulwcfcyX6FuL4lWvQaXXZ2S8QIVP
uBanJKj+SpgEglmlNJnEAbLwipubUTH5A6w50C/gAONIQcLPNDdSbH/ouUsbRgySSN6mvW/wv1Qf
4OxofA93boSVUQMkjYZQtPk6YJv+sjp2/rpHUAGfIxBsgRI4qlWCx4dFnizt32dOU9QV4yLvP32d
Cu5we3wWPvikND1c/6HEexHz0aObITN1Vw79mXrHl32mEbNGIxTR5Es0GDaC9A4E/Ke6DekD2Uoj
kmT51MzbwPCr4g9OaBQH434gGFyHR0MJQg4OrGnGR9cXgghsexoRjMfv2t+iAn62KqsL2JMow9zc
rOcEqNIHPAtuQnFgl7UzpUcR/XwdkhEXTJHtTJ5b/jvjzPSlhns40PpKm15xdNlQs3OSzk+AnVlV
58fVAQjwmOp+6Zgf9G0G3ZWMXLSHvPFGRmhMDRyz9WaSWvRsrhCJC5ire9+q8UPJ6FkZW+bd1gPG
1+yQEjDO7YKHsPmqevmEOF5dSzxF6kV+Y1quM3AZXzEnFfKUc9P9FkQio9Ikeq0G3fx61h61c/ge
ShGRjpPUE8nQ6cNknkPAlCthCYprbQDT0wGO5CbtbasQR1kuwZwFIHjJk5mmw7Hk7qo+m6o1IXVS
P7xbouV0ffTEsAt6Qn4rDPy/uk06WwHcZ07mOmPKwFRDYS+aQioTUXt4AAau1DyhTKAdnnCsrjEO
03Ej1QDTxWPaAgCW3WREemu0l8szGMTkeHSTLHebUQSawFq/x1ZRwlbTW5mof8eDc8IjHvBGn98m
GiRKC9ltxSmkFKeifhPflz/wquS8dStSoE1GhF5xAt+sYG/DNx39srxrMNKhgjnHc30FXlR2maBR
uajcqBYWafm5Q5fEo4HrhMBC4jYsrpw0laJwevWKmk6qbuzdi+RxD39D7sLAhvgz7cr201fe1cRF
PnljiZ2LC3TPAm4CLAXdwl6s9+FU2B04rhzpc4z7S9lO9E+PIQxoxQSOh23rR5xtTly+xAF1fNVA
9nAIZ8q4dR2zcXSgRNWW6m8IePSrWj5MoiH7KCA3q3QVzpLMiwkJ+GafbOchw/PlM2G+Tg7qpMD9
zdOAdLhhmFjx67zRUzPvvLWWwWrURfqk4Xlg2Q06kWSpO8M3LtAZScrgt9sU7oJ85CcRgvw/maWl
EImhWb65cxBKesP21SeSSKrFRoqwVDPCSnryJlrX5h2mYMWhiHTGDjqHSVS9AACSZNdmDGLgIvgS
NT0iiIg+a289GF5gTRfRTT8IMii5iBWY8OAC31gsp4wDyxXbU7I5Ydiooln8fCBH0N4g/dXETexN
j0fUQ3SI8x9lBCvyJasCUpNIFlathv1kF+p+210+XbaXKXSvxet69rfqWJKyCZyzDVDH9SW13rA1
nHuZ4SSEH6pLe7d1s+x7aJrl6Q8j0m7BfudVmOki8+vXmhoPCtZQZK88s0umzlQJhU6OcVG9+cZU
azwx2RvXGCo1yLi3d2h8GGXJ7/0KbvOcfGFu6ewEOrHyLfGHYQlKPgK57e0t0/731ImweBQl8nQu
6vPER4eJCubBqhRbPDz7cOoNPsRzKSAJIOMNTwzUHyV/2Vg8nsLVXLmbmzqNcULpxEWNwWdBGVtg
A+0lmeLyHOfXUO51K6FKNJH6hSWNJryjqqgBQcaGaTMXu9WWi+ZocTgOplK/0N1crAQW63/iEmMS
AG87ZsL9C58gSKXJl1fFrX0IK1vdSe5tlU4HYtHnYt+BCVlTUHdAbVxIdts/q3KBo8DnNcQE90qE
M/gVaDAXcSKMsz9Ci/zyBjvUTDaK6GpPMlSoUoyMZMjuWxgtnnjDQTcB6gyaVGFtghnqRb/jCVEO
wVryiKYAEfNoL5MLMQJc+pYrfrSdtRJDcgE5B4LkgLmlkb0VDZii/nNBrwr2FKwvIODlx6vrvSUb
UtSjasTXkkAk9JdpW+fA4/+wM9LXyxG3iGb7bDACHWVuwgfm9bbv0lIAXkqzTaeRoPr3+iVLZWmZ
PIn63gB5FODd+KF0YVKXt/59VvqOnBZwktQlX4YJNnh2ohbOgaDD6kU5d0JwIfJemLE35oCFzhh6
BeOcG617ZbdI+7nvlF16HLENsrVlzLKhJNdScSf0PrVdtp5ZbPzZyH15XMeakkhkk43QeJ8KHRh0
0GG3RGeU2a2hXm0jbYVSfNVup4Vb09NPfd21WqWq9Fw/jwXys348AQXUKnVWDhTeCyuRpiBxlo3b
DsYEkpBXe+eI3cXJ0EPaPAZEa404YyIYqsiYTM3/xozoOtK1H8/+XC6yScBr4bOzAh+WV+Phrrih
9AXYFhTN5ZnuRVWCIPeNUmTLfEegp7suRYPnn/8QCU95nOv9A1fawxXgVjKx95Vq6aWRVSWGeowX
/6FDXkLqChsQeNCGGyxOihQtv7fNBGIgUB4wm0Ae7nC0g2GNC9kTMkBVCX3vZrWjmcGG/zQInJTa
5UoDLYQtBkx4HzCQxrwf1TaRBKg7Wq4KQBoYBf4ecTKyrLDlgEzYg5phG+oLsMfj9tcOiKPGqm2P
DGPqpZNIoroJaaA2O6SETObcnHGG5KcKwdMLnJUZ6NUWuTdM7Q/rkaybqHeF8N4CvR1ekKy6Czh7
hJFYTYx4t6ke2kzI5S4RQLZmc72pC61rViG4yVywcSZAGrJ/SniNr4NhlzUJQmL2Vjk6bepHOwWS
qr8ItNmtsEeAj48yF9F5lDO6l4sdwPHOE/Ts4mne4NfMjTw4Gkuurtr4o1TuJCNwjw56nHzG+N52
Yb+if69OYWkPNbBZr4ADqpq8CTzZFa5QnsNrfldmKllMH9cM+KyObDX35SQ+Pini9yxLJtBgILU6
nocoL7/ONYIgFWFC8RBbDEzbbB1Y75OJtxE8EkkBjvscKGUj7krtMwhFDh6WoA92JCTuYKLG+ADQ
PUP1/0fS7rNQZWNoj5AbJ+U90Jy2JggUzwsVCvdXxoig5ekG9nWqxH3yQyNr+yKO10UNikRoEhuU
SK/lOuUktSq5hsChM3rI9tzOwkR08Hch6h6UsGFHgMMDW0Y645SzUy1JiIuYi2tOqKV/SBcBUcSE
fsPhJ74i5Wy5PX1YVwgVp9Aepth9NYY9tQVW60fMWItWa2DTm7Bd8EBSgJliOn3IWigSmPZfhchy
K8yIaabox5luscAXqM2trV2iI3yy7/vFrIfDzIZHT6z0U6gSBeN0DqBtNREkIL/sYAEK2eXc/zDx
ShRhH0kkNalb8PYuxUJe4o5TzKvrEAXby9B/TcQcvDgX/1/EkNBVQSsBBxG9j2opfREvYI5TDwj/
NFzHyrvPO0Ykxxi5Up539MEfxhsn07FdEm/e8NIAWHJf6E6WNoonvCNquTGsMgDGad34Ba2LMo1h
fCpGOhJTsc9MMhNgNMPz2v9fkZWXBvvbycYxfReN4ZSZ4lQWUBvbFaw/h9PKdGqsOxXlNJSbqxAj
DPBXoLUFQjgvhFkRtrrOgJUeochtdXgpB0hIhXcxTiGdH78aO+LdSRHWAiM2Ky8gvBiZWg+k2ay4
c1EEyB9U3ClVuSKhVt+WXxW17bLVYKdYhqhCsW31sNzmy0tAzwRjPmr+I/aDGuH3A9TOxKVqqKTE
W7Qb94X4YGJJxsnO8QSiOLzSVgxupVZw+4/HBJ+G4YyL6+kDbO6qkOVVhD6SZEw5dl2te/ZrSari
+Ai9nwhrfjal0xekmwCQxVrNeL/K9HWCYw6hJ0SUccVLm4BaWglqKQDgHM3KIaLwZjdM5YxQ1B7H
iX0yIyt3cmiptWXsCLMnHn/STH0H1KWyKAwU2VbtbfUx06vJCGN2mkbNccmrlLfp8Kkudg2h371v
FcHv3fGQ6KlsYXWt2J6x5CBCjZBouOq6X2gRKwJUfBPaA+WvU3bHUsmp5ut+W7G0b3r6E5smJ47A
s7QrNKw2wpWBy5CyOZZ0c0yCKt/GBofjrb12TrjbYQj8plC7fzyS1AxzXzNb1RsAlbJ8QpJeh5M9
gTuLKigY8odRWt3z99F1mMbclaS/JUIRvoiHK6mOJElT+55uF6ocKoeAbkSj0fhQLvD8ucG3Y7ob
OfBRIbQ5Gd6/4p8x4kqaeX7lRJj6T7ScXdHhrLuzBD1JLA3CaiXsSgfC2RVNFLPUQU7fhUzOve6T
1DLt29whg83Ve983H1F/DTliUItFVMEgTVfxY2XTBjrgYWlQUhxRvYSUw3DIcUF3mkK+DuNixpFf
mQPZdnoslCiOZnxPHqJGXu//Llt0FBSUMT+/sKcqgdOKsL5WmZS56DAhkxW4xAvhEJ481R83Hn4U
jBwLctI2KS2xS1mwrBtFZvavljU0u1e1D5blHbzmSZXvww48XsZz4m+7sYo7Loeo08WRONzWs3gW
zvH2tW/Ws7ykztRpY0/s1QpyeZcwaWliNMekisstB9mv+4qE9MspYRFLrX44CVKw5UcP+cGdl9Is
R7ofvhx4IFworkq+vyjF1C1YqHULTzq4xyiYImsD4gI7KKuiK8j+GshAtYzEWUFMl10oeQe0swZS
S1HvtOs7Wd9akmqWQwkjICDUNgw9OUT9LKUO7K8UmIZpl5tozBQJvS8T0ztcUl6XBswHkx7JFXN0
oWxEqeePYC978n/zajWC74LDXxfiR6VUERTADbajEjYwyyEfj53W3otHIF6h/k4So/c19A7ThDTr
0pNEXINybhHFJXX24wte7m4VeMZJvknyeHpj2x+1cHphr+Q8wyTV8JT6IgvCbsonB1LyfzzM2dC2
p/etF/M3cZQHza3N7ZYA6VqaH8qNufPsGjsNaxzbKAq3m4zOve0u5fOhZmbbtxzwIvCxQq4g0K5h
zyVdw1NuLpoco+3p+8n7ihLAbBXtDFAPC3URfOW1Feks2/s1YoFdGfcKpkfbPz2F216ofji9lHxg
egx+BhQDWi0IFr4p4Srzcgd8lBThE1gFeLMYjfbJ9rao8VmDk/kAypsJz4StC2lFu4FlPQjTpN3p
KYMPyjUnfXhEe6MlNXIr7ReFiXLGDCteLK/lsRBl4fNr30naOR2N92x0K0w4/L+lFP6yhXnt6hYj
kONaS21rfBOx0GMGpw8jE8cjyb29GJdjc4xk1kWSTinNXrFEIur89G5w4lXvqHbPhe1+vEVz34fj
I7z+081LEYulZeBX0lw+ch8U/YkKjr6UEHHXn7ZsCahlBc8x9DiUZ7Wysm47Vp1ZQI8A/UTCHUnN
061xR535tMQ5yEGd1MJ3qMz2d7L27R6Wq1JKRL29zGGVGcxoRzfGFKMN294aUTVqBvmxQoXx88QO
IB2ytoC4Ajp1dwl4s6ePu6422FCajA1r0QXluKuLv66FTOMxjlLqkKd7zfkU3iRWdgD/xZNX/Dyd
6XAiRnQcza3p1F9qFwI0SCHypM8k8SEgngtMPiaKjX4gzWodN9ORLFX18cEAU7csybSDsFRMnfVp
E1xa3wVo89xZWw7lfrXjM8doH61HDZvKflpRmITwHG12kNO48TP90WY+T4o23Wg8LINQGKHj/P/2
g/eJMr5Fmjc8cVJvGXLJ2yvgfRmq0/crQrQjqeTKjUhreMb+nb2/xeZqP2c/aqpSvA9xgEQulNcA
IzaKpy/Qctm+eTGeBVZynVP2M2LskhBBeroIhy/EzkTrE3bvl2yaBJkM/SU0Zp/wPiXUCksDpivz
41cm1RyH6eP8aJp+A0OBM6/JLnECjLg+iYSZ1UxSrVCfBPvk5zJH1Bt+ziC/u9c8HqH8ft/XdRS8
4bKmJ06eM9VtIpIW+ZF0cI+T1YVo69sYWrkcfLyHdzC3rlEb8Dzm/gdVD26/9MDgqiVo5lIq9YVL
42vWxE8HarcV5HRo8YzLKr597xDkZM9YQdKff5gme/ECWa8pO3p0pOCtxdRWpIvXbV7ECXSUyRTd
mdWnZ3CJ+5Tc8dJ2nSHmT5F/M2GtSZ83Tc2TmAJK1FOW5kvoJDIZSg1BWhevYB2Tb5dAo7QW3cR8
WZ0mko4ZGgi530N7NLxsm8KOmQiW361C9l/ylUhy4DFhPNLhzyZP464xKV9ihj8ZGcEX06j6ev7Y
+oMz8pqRhqKwMisQsj39gKWrhD1iQ6zEby7b4OAFZSQzVmQhIeppJrtLjV21/VdRMgudSFvDjo+E
Q0m/bQV5oREXq2dMVfmIjP89xJSexpSu3RzFJqeYoiT2d7mVkZAfGmFuWl8HoeLKiLEYwC6GPPdu
VTpPBSO9O+lCC2WNRC7YOveWecv/kXdt3OYYHUCnpNvQtnCxswl1aUtwFwvdnqE5KtrReAFzIytJ
mV6I1wNAEPOFdPbaBSjXS70Hg8tqh8VhlxLf1s7BVLkieyOwXpcPowhYcJJ2Foh5zYSFmotL59E+
6vBR1FnKqbc4diqt4Zz6ULVa5SH2CeJFs1wfWaKk/ARoI5nStrdZ8VquaYEH6+ehwPpyeNlx6faY
pBgfPycVvErI/BvrGbKL8HeaYiV72JNix39x+3CG3r178mo7+bHeSRDYdsztaAhD+Re9/hfiB6zs
prVG7qX942RXO0+oUEoWiXCQdzPJqeAwjO8bVVrqL0eTaD0OBLZf6EpaaXoqz8Vj7dXPUdyBu1QS
7p8clsnLeTDrBSQWqArZcaxXc5HC09jSm+ZZCmERhSJucNpoAnSj8JqF6f+pOrn2HbuH9XcopYgP
08+Cb8Y0a6WhYo2lLbLFRQo+Ufn+ypeHIfHWQOLNW4tmnIudWgkUBD+x/1q07EJaddIdTjuHLcK3
rIks2VRmIQIHqizDLWufkxw8Ke/LAKLkJidca3pGIzTd8MgaKqF+ZmUwVJSRq9+l3+z+HNmvfxwV
RhSn1p590xyvFsJCAnCchoDasvizsgNpb5vvuE7cfT8fFyEsmOoMLS2Zg5xldhQ0K1KagdefDIr2
K8ABBoeJJFKkhuDampKLZMo6Gu8NF7IsK95fX8hRWqmTCn57diEu6ZmYZ6GXwW0MASgMpTDRrRoV
xQaCQ4YxRMQ/LJne4V9wsjTizU+8Ghq4GBsyNtiWAuzWWiOTPCyHh1mv44iPO7UTD4SLMLIegrAS
goaoHGTTzBVE0KtmEjM4RtOJmO/uEDcoY+Sgs6biO6aIFMIAuQoo2EpAEmeoRIkqRdcN5wPyRLL7
Ea0it/KDqn663lcNVUwOaVWM8giobK5c5Ynox+U5tUEj3RijyiTwEK2ijN2PdgQL4MF1kesctPL0
gIdrkPkacImrovmDtsyRgzQn5ivJeUR8VL3WA28Jw6Sl6/OM3NPf/UCWLPuiGnvsFkoAgOc9N31r
VxBGJamxsVhDPkj3bTCzoEvjaHdUJTwU6dU3pYDHhzWPG2lzSRltclBnQ7PX76tdKLiBhhHvuBEG
r4Kkhh2jQThNzeM8sScsyebLNrFm20iuRGuuIjosIdsjjnYHOHv9jBU6hOnfvXvaVlq82kn6HCCv
1xca/TDiZNNBqFomg/VUgHsRyeg/uJ2IBRdV9esvvc0IJGrQMubmnsvXgQym4L+41gxv5nzWjhnN
6pZ+K21bv/AgPSMZkz1s/rrIbWBeCgjcoLv82VMb4Js/Z8PotQTvbf/nRcXM1Ad8TpmfcXJG+G3+
vl28Ep2SgFU5o5NGxpxPe0FKqVScAklShByK5j3LhKbsfp0ELfaCArLS8pdXi2MJFRwgG8TIrpzP
OJR/1ayiLGuFH5Wqj7FdQxe1tjPeHcShuzi5k3S9zkQk3PrrGZOJSFc9P5A6hmBly47hfZW5HINw
Lg+uLzQqeQAKpurpjxqQG0YRu88tlDWLM+cQmLd5JhyG68vCPsFo4nGwLvZemuUNFlBVskt15hhK
ZqssQEyxQ4MF3PwY8saKUBe9ZE1AFMo3tv29DfG8tn4Moa16o/j0FQjh3jkXr52NSCJGvwROjh88
ZCeJ0PB7ReHEhopPhRt3NPKpGOCaft+otB0Ez37CwB1Nr/vq//ttN8nnJ/pMQ1LIIu5ybYmi1MRF
1umwqapNjQYngZXMxo+74Udc6Vx9phOrdXw3a7E7f1O6DBlIzfLvIcO2nu3kqK6Ok9LGmhirxH+z
ZPNkDR+9Lm4WCcjZWaFkzqfszfdtXpj1Qz7ac7ZXao1uMOlFVsraOuzyeFsM4hCMhVV0aTLmo6WB
JilyieCmNcMg5Y+bv4tcClQNK58tVUGLyMpHZXOlvix3vmw7HDUyF5DsUmqFbizMv1cPq14BO3iq
/2B7P4pgpkfoYSIoOxAqL/RfKHgl/l032aBtYH1YcmBn/d9QbZnu7JnuDQ7t7zdK5Hq1AFEm0WWM
AMm4L90OXo1xIjYDy+XBCDlk70OU2N9VAPRRgVKMxOFNrE1zD/YqQHDDmruN8CcXaFrZ4wjyUFdr
KEtvjqBpQktU7nK03Az3eSZ2pFlv5cWksMFV5Qj0TtcrIvTblh5dFvjHSiqKLQydoEy+33xLzllS
bWi4elZbE+Iv5nzL6cs5RBdXiCpBtj2QLlJr59GC5G7aejtSQH8CDsIVvILzvqYLi427e4+T523I
O3Jh4JbPc9G+EI9IBRNgCIeK9IihixRcuDHgYQCf/+sG4rqQmXWzeWLctNHD7tDakN7EOXfJO245
sc9yhzdRkfJx4RnocwSUqlfjV6vlJjtiK1/Ze/GeArnIclSHt5+WvdDV8iI9up0S4XRHdNO32hYm
rHuZYdykNPlz5Q7MwprmVy0TOWWybDtdyIGM/MBKrwQebT+yZR1V/oNw2gscOPmbd6uGj0qJgwHW
L1hAQRSwdvHrz7gH31B9xgq1V7Lx3EYXA1iWkXHH5L9qNeae393UaCmVTOq5OKpewD5+89HY3ATg
Hn62YzoFT5umXUukxWNEXE4UzyEXBc0rNhgMIWc4u083nmuPS7DOYxfmFlg3odraaM4ggW2OprKx
I27EC9UksQ1o3lE9Cdhsz2Lf6u8haDj0jiITWtQupPJ28jJkvSoMZS08esSE8FqzLulu0fbNE8Js
E4xU4RyN6ilyRrhh5E1BrvpPzB9ov0lCmIfh/m8S/IdpbWZuN1NNzzGpv7G4eudoZmvU35zRs9yC
TrWEVtGpPlCt6Q0D+GkW4snnkkUl/vjSSxofjTKDVxrcn1dPZVqp8U3CJWvvmvlqmVQ1dR2lOv+h
FI2GPuyxwin1UHX4muJK+jr0NfdgKvAu7AYIKqvYUW1hJtM7RimuRMvuilB00UxcsTjMByEKECI3
zl3YG/jLmIrAKPKNc3CYu6nUT7jg1mXHrIeZuWcbQpzudYvB71FP0Qi4U7shzCEy7MP/y96bINYE
WMQOgkiPYj2LU3uuKhoS4JjyZ69fwCQHF6uhXbbsfFJ5uzbHOWvsnMeBv81Xm9xdZKKDn3xVToXH
7MsDebjvsb5PIElSMWGMQsUCDfUoYjHq2nfzsEK4UhCw2KhEExVDzrFoE86Hy0cfTpJkRD0RY9dx
BDNx8xkhL5g+9dJ2fICF8qjMHjYzgPJRqhsWHl+1AaAhDk7SmzBxv4I9W11hj+QOVMyV5YZj439V
TPvZc7Do34k5klNyAybvs7ja/pYa2nxEZeT7tIA2meeEm74+fumegP37D40PPnarPV68Smmr0zBe
f/USVGLz+vD5lcnG2ND029uf48BG0lOinewM64mN+QbBfpS9hSLc6/ZCmU27z2uzbFQ/3pw1a+D5
mGCEEV1wA/vYagpB9EAGoeg9N17tDhlZhaEo4eCvM+T1TXFKCjlXQWL1qcfNwDldQ1vpKfqUCaAe
TJqmPoZ2XkARKCUfVj/cYSnPmEnofQtegALmnvhPO+VJZP+T3qSr8v8+CsVLGSUcYa1RJTCWZpV4
eRno0yPtNtx4fvTuRXieM5UBvpo/R/N9D6mdh7tI4oR01aLfmXMDTMOtI9XFbJ6dvTsp/XwP0kE3
r0PiujZrJVxO498mWfLuUpIdu2vdVTR/KBoRXy9LaoSSWIFH/ZC8BcDAv0x+ja4QJpZ/HDtlJLHn
s5diCog8n/Oy76RIz1cEOsCwsbt7CzwZDOvxeEv+YdfPJaTzEUY/8L3C/ZyhbbAwHuMUOyxFfbvd
aY+msyhBUYtEgxtvTvsqySkao8ZtC0bZqbzRswNTgEiRXC7gagmViWuVgzners50ssbLir9HOqd3
vIfXXh8nC/ublxhi5o9bZwxulay9R6IgmkLh6PLjzk4DiTqYqKMDFOJet8a69EBTUhjw/1ehuT63
AA6S3Ru+QdD9mNv70oFPWoJMJFOSzOSSPxYsQ/0zUUjh510m6HNCy2TTVRyP3pb9n0uh72NkTNHq
1Ba8XH2gkJrUjRz43QuOgOYVWcX9lxshB5g0ecysw82X6TQKaet9FxXatr3V/uQQMD1u7fSqdB1+
V/t27G3STz4KqSdu2ghxPaGUltrhtCSXaceGYAEPnFzCKl2SJjz1f8yo58uk5bRBH1JSzvqRRgY1
B+53aZlRQP6TkCGLkYMvCBj1QGtN42R9zmPH4rwzyjEDG1d8QJ30mNcda3RpNjbk5DKS+OiCYm+x
jk56kiQW8zOYFjDWcGqtmcI7dxrxZdhb99OhdRcBtfGMyqnZXIRycT5vIbsMkbeDI0/tTu2M4OOv
syFppe4rNdhr86Wl8niEtYAE9uB/svrb4zYlWA6fJo1a3fYVxdCE/6utgjr3pNuzXv7Nr8Abfgjn
LTHWs2YDlMgKazz5fakGFGzWcF6pKUcdr/u0Yon3V+fB0fcKnA384BfEDAw251dWCxi9J3NfYLbm
irka6jb2sFaVYJ+2TIJPr3c2Ny+w0n8OWM2ev/sPoW9Hppj436efhnRW5m4j31Y4OVpajE7hQBQm
Yj8g20DIsvsqk3VvGVZe9tUHLJ7hREZkcXBLUOZv1H6Iykvs8SDwDCkln4KQKD6647TA6Oo9Jd5y
/FlZASGI7Gv8DmA0T37iwHaCgi7qEkA/g0nAXQqL3oylsq7Ie/edvEyX6hU3ajSWLXU1P0SruFUL
kQYYlGVVGTpXJ2Pqyb9fPeeff5HjyKJ7vxTVF7VvxHJZM/Ur+wn5FnvbrYxMTP2Imya5MYgD4gn4
kc5nFXpBer11bLZsIsYqufB0Brv2N8eJWXPZ779f7FrBGEVPHZv5iEnQX5eAmIvaBC0tXQPJ6guL
/Cuj+120/5ZQA7RSIN2BY72ExcFRj132MpTr8sbcuKA+y1vQr16PgzwDyh8zNAUqUrO6tX6hurNc
bpQ9anlshgJjMptSiGcnRu/jx8Pf0ct7nsoBjRn47wypnTD91uSqoqVtP53ly6XfZa9f4f0huBQV
QNeX6WZ7HbMq5I5ccqFTR/iNQARkOJUnvCANEQIQxSKlPzUtIwR5KyStbm9Ryp/Qz/LQ96/ebWlI
Dj6zY6POlidFq5nEU/zOWPLADeAkZosphli+B2A0Mz1sArjcAvOe99P6nQwvw5jxFVRbPvRkH9lE
QERjXttVDV670CZIUdNM60n9dD0dI4c24SnebPFVvGoG9/yK6fiKA6i6uZObW5d5EBaz6QVyU6zX
1+ifTMY3ZzNxCSRhYiGeFE7r5wzA+1Yi5yzUztKYspqu7EwC6hA0HT+v0yiAd7IqigJ1MHPQ4XXR
4frZ8m1gvRI/mndw2+i/WPNS+iyy+UTqUZ0j+OJzIsiIyFBVIRppoNtWGEQ6ihy4AxRNsg32M4yr
CMAw67WxGV9O2fsfbB0NFjrFKAYBChfeshN3yBuHr3EoJ9ohXLq9Tv6DNlgxY+6yJPsaZgWqcO48
fgbPi+1RoAog9HnEGYRp7DqbKNZ3I2PHdqGzR+fX7zndBFD6LiYNqbVomY0xNcdnSJtsRVBcrpks
rMYhpYa1BLUOHgivxkRMH3Jni/3LhbxzX18OC3SC7lDkrp00Rzyk/2bMFR6WHPczp6s+vfFmLvPj
ErGOn2EGQA7xqP0wS3bKYNiQBd9cL7xyjC1HGmsZBfOHxijKA0WrfTJT4IDYHmFZkxgcdyvrkukR
p3X3MgEYFuGlj848fZXHLg7sxT2uu+JKbt4lwni/byj2DuNGSSBGnKBMAZV4TGt0hytCNmpHaHlL
VFpePX3R5l7iYELnxGHIJPUAeiWAhr4xYl3YGnfqV2P4ChIjrEp3L7XE46qTziagjfKFErIl4t0T
0ihy7WDWjEkoEiK+twwa10CNdJt4YBmcHDkmUh7Pxs+m04E7Lxp9KB70T1mxz3xfxQki8v/ZGu6d
Uhky7MMPThHdTBxLna1699xJSbtGAMFz+BKq55PIGzg1XNtHk1H+bLjQQ1tLeU126yzOkAc6Tmmm
jPRVFIhisLU0DcTXkmb5Dk3JqF5pR17UUccr8X9OSHpfBfHamKEJofqwDDUqeO3LQ6iLsi4ek7YV
vPmAFMIr3sCnDGS/RV/w8TWhF/WpxWMvqlHHSER49KmRB+9c7yHcYmKjWiuNmV7kyoCa+zDqjbC9
CbCiMSP73eIz1+UQhxWCdfKL2Akz8gKeH45qAbB3rdFfZjieRtCvzF0oREeTSg3INabRIfiDP73j
4c1DMYY4pj4XAa5/IdPKRoCllOheCESgAGoxuyfXmcrBLndH0lZme9NH6z/G0knrmjnv0OkWVE4S
p2CwG12mUDljjHfKyfi1/RX8Bf3xq1G+RfUM38PMstkDWxF6B+DVUY3V4Cu9CirHO2heSnLaeoRc
XwVZeOeFfsr4QqEnwZDvhNvIh+Fn8V2E2t0+EG8inC3BnjjxW0x9gUDahjP6vwHGnUr9I7YuV0tq
Ac3QwL0bETCnVbSzEP8S1uV51flHJlUPZKGedckcZznzwt5QNN7nPpqKhTxIm7zjpRBptl5ItGlL
tzuRy015mFYOxBBAHSDVAauMO3fAHtWKrYGeyeaIbtgOPO/CPhFlUSvDZefYc4SvcTlvMEFeoe50
18UzrgAkxBHjqW4J6f9kbx1kgLnmWUSp9HX5kl5nfihJZyMxOn8SKDiAmZubXnMP3XMplCbtlHwP
pNTIoYo9q5aWrosZnOKv0BQjjg+QO8MuO3hGzp4AvyIpj3rL+UMKhQhIZgCc/WBwO8pNfTVZOhkw
vtA89HB00hJJ6k0FkUtnBRLi5vXA4CdYV8L7NrOkaI8t32Asfp4oihZhn3V7PO3OW+/lXUWy3Psp
AkH1snrGy5+yIHFcu7fSWTCv8XiLMoZOnQTkxwOQAEJfon30XimlSX/YQB8g/+zY+VgV0u0w9OBJ
m0HdwNhytknfcTd1bh+HB2Ox1TT6XW9xG/NYhWWkdBLPo1nUgouO0GVwn+HjmZ8CNQqsl7G7Wt3S
SnnVm8QsYg8lPmXiwx9G+4E0tlCSxlmeo5oC0YPxaFXL5lUYyisiONTdvtuPb7ew07QkD06Mb9ol
DKh062pmrwijhCHh2Ezm6Gfv/CVHtJwN411qo87fkBgV9y0q9yTKHdlIP7YpiXc+pREh9zAOR9GQ
GQTn2MI4XNQ/5FqzqvjWBF7EMq8xrV4IQYMGoK7wweWRHheBLD7RnmMRO8+23aXi2mfClnJZNdhG
ScSPqdwxkuipB1vfz5YdlPLGkeyK3yphaCWpBVH4vjVBy8rFmelOXc+Kx8evVFP+MXlYSo8iY5BG
V0Gv170eH/y3FHIFnsYxeNYsY21AkuH+SZ60RvnnPa8D1Fta5++JJEHEY34bW2udwZTCpjZ9hbQz
glRS9YfAUPH60wc4EKH+IrXXx67R3BncuCb+GYQYjU/CI5wvMp05uWwowrxQU0PnMlD1CHAfR4gm
WvGAil7Z2PT8FVjTdAxebhEQmdudv4WvuYJ5fsUaRAR3Vdql945OndRFxvjmS+mwu/96zyDuZv9I
Y5xZh09p2FAX5gArebOh80Lg676/4Js3NpnzoYBkGTUtHzD+8jlapS0o7vQEmrXgX+hBBwRoZmhp
cvqxmeUdyYQ7EUPOpSum5GFtHelbpeMtL9+VNfgN9ZLhz7HK9X69Jn66y1BuA0va9eOTEg6g4p4T
wH+G8lYg+nIV6PIK/osj1vtOh5Lo6tFppLDh7/j2tUUqLa2oqdLnOKO42VNa7DTr8ZCM967CHuMK
cXmTidE5+ibyiXK4BYjntMaIB6H6ryNkQljVQ1f6G5vThHFdLgL1stRJXIpf9xY9GQv6Ovku+6py
kYUp51yzFAiUxJz53NtMa7CZqT5py+40CoRU29b6syApwFLJAHPPPQroSsydZzXhArPExEa7HUW+
l4rcX800zuHMjCiwnGREnQcjGDEsQbazbVO7Stm3hlMZLKRaJXUCEw56ZnOq8QJpf4tEKV/PhevE
nYWZdiShUjb+qLfuj4O7JtvCq7XNpmux5k8rLRT6T7MlhgigfKq7t5NosXCbo4dRih9t7Fya7j5m
lY/dinFIUJjPFRszNnwciIuc712xJ6hs2W38IKvQVkhgjurUzGKMkT+4ufEXDwkrI2Da5ArD4yji
jSRuUIhLO7WPBpZ5W9WSTs4ADxM1TKHF81iC/VCg4TMhGgX52GhaKSRhLQuPgjuyfxmMUhyHTsMd
30PPnc0BWh/uEssKud2gTA5wH0Uyt4pGYdzUn7gHLpOknv9i2/6OIqMRtCm0NaINSTzUiCm3gVKG
aTv5zJIHNK7QUfYiXgG6P/oEymwi8962Q/y5CYyxfF7ez5ZhX4vN5DI/+o+9G2OPn2Iegp4/+Ha5
zwKClx/n3nulDokScR9hhe3wk0Bhueiytv8ATk5rFs85rZ7Jc4TVOHnoJImSfZBhjBXdSKbm2Gms
IKt4QnAF+42DMjaAZ03WWJkjjY783OpCXJGVpOC+xNqdJ1G1of7lrP/nwvsrNz9+OR1Y03+6YyB/
0HEOfMDJ/QVT4uvw3UfZKmAIJVJwDeDPAxPz99DSlfiXuavRgXm+SsvkMIJPLyJnHAj1Tdv1yLVL
TdvHDzv6ayiqtOUaHiMOaJzJxxZJbweDSug2cHR6LvTq59uV2cTchforkfTuAiKyV1fJ88i8l0XH
+B22UIfXGo1BBHP42sZ8TNiU4OW1qHOKkuyGN2oedjoAw28gglJ8s2P4CRXIAQ5h7YzUm6BJPllE
qme7PjuBR4C7N2K2D6bVbsf/yDfI84XHMfoLbPpP/0PbMpZ5RWIfr1GAlW3DqVtDGwzsySXCAEwx
cSOdPDv16r0RE7NZxji3UBLzvBSk3jKuhW7nRsv3jNXU9SHtz1q/8DRlxTbH0QHL14n1LGEZ8xN1
cBo9SqZhmgCQ8CGjOuRK0qQCBe3S0TgzA8QbrAZZJal8NVnPpGrmj8pmbkIwUID5KYbg2IMXzSri
mx6Yy1Jcof6NpF5Eee/XVVZvB/6ofWW879SdmMI7nC74rvHPmkZeR6S1MjZR3r6Fh9miEIDgq/xB
G0HfGDJ5t8XKynnT1zsArsQzadCU3W+5VOrpIpeWIAVVqk8owU3I8ftQfi/wVQW/QXYtq4VGiVpn
2E2ianjYoe/SDEUwtKlpwHNs6r8AxuLXcJNL0w7DsYN/3qse+XQHAU0VDZw5HXz1mwsVj73KPhyL
LxD+jgPDv3UYpXiBTI9rrH3glvTO+oxILlZ+JwXujfK9SMk9A6LqOVCTxMeOzOm6y3n0nv0dT6X9
odcwqAVuIKY+imHVtiNc/KeW1TpdyAXtXXzEESNWrORPj2iuU/4EcN87C3BOpSpRK83cKKqUWlK3
lMMClpHmLHktvyKa48h2L3y6JGFCb4qe0AnOA4Z+rNveJg3CSGZQFpYteyj6GPeSDCJQGHJskRU6
8TMCr1549T4yBKKpfa1NPtdv0ZDO/eaOemJWBfXrOG/0jy0ZdO107jVKkPFW1hrMARWjxcqosLfd
JlrEzSpiLyMGIGzZY4DqC3WSP2JNY5LT40D+hRQq8XCiuX94FTj9B5QCoKDKQVC7NKfE41d2SF5V
R7fjW4pFp+PrM34ToC9L8cKnaEIGVfe7pthqAXDNbq4gTuuLD1k9SdFeY3hB48uyWwe1u6nbEF2R
4EtFhMj6mEcGJz9i6ReJDm0gcrSyqfzg66orfH6qKRXlvqxYA/DhEi8aElD+C6ik0K2JW20LL/Ff
Fjaj1ek+yWgVv+8rrVMCam4ECDNlLkNe73PUo1i7o5tXX9RGQ5Xl2G+cZTacaiuNdG3p8fUQAOCJ
VCTgxj5hkaFj4x3EC3LnKoMrdE/keOco8JHdn8ynKnsuhEV8kmmiks3xqF8fljY/HIkVroplH8YK
OZ1hvY5N14qEDCjZIqWFXa5IG1wxofSscqgoY/Sn9JlhvHHCuI7g/Namko4GgN9B1ZC352X8LmfS
PN2+3l5kLDgyeYW3GGDHPMJ5ALzSH3YHY/WYzVIyYCtizco1QXvPV1PNbs1WSoV+CZxFXkNHpSJL
AZsgzj7LyeeqO+VkqxBYXm8SmSa0optVZi4hB50jKg/ReBHGs++x8skfutRpWOrBCKWhqzibTmmd
Z5VRlyqOMDmB+YbXo3ZjRBhiQ2t6lxZ3quwi4rPtsSiboD9Z7J/RCODoSyvMWaGrXt4oAsoXHFCI
necTy7Whfl2NQ/2tM/+PCI8Ljor6BpJD6PU2vjuVptMNHahz0jOvjp+mypUbqFAifVhzNUnnEBhH
RlwaYFRQmcAfxf+YBUQCCqaHr08odAQMYwH61cF8SUI5UDCFhWNRakbQiT9Yg6oYVgAYIhQM22FN
3RxMehJ/XlcypbhhSBI60iKTlUNmrNQHuMuvmxisoUh/9LNJke5KCgaiQuirguI3XVt4PALBUE6g
NTt7kKcYxPaPYk6cJSniU31YIjgqWrkxi4LOXGyF8NpyXroPXlZfx0XAj4BuHTdEbiBKptCl4j0D
8PVwSsMmGcoGhebziKO4WIAUuzoGeVVeVYCvkAZGGJCbz5Rqa8FY1nDrMbwStNzs8PWTv7i9E480
+kod8pOY3beUGvUnuabW0bJKu+a6h5WOJ4Sp1BOZqnNYZRiCtT5GH6KAsTSjVjXBWx3UKwYunJ62
xHWPq8OiQ8cHWYhxVpPB3Ckq55CbhQjq/yMbjyRF2UeBk3t24x1CiwdL6PrYLlozlmEMZfRKhPgF
U8Mbs/5yh0TU3g6NgnhLJ66SocdcyPZsXKsioMuYhS1DnErHvARuHO8GQbZVVdcya49HBi4LbLQe
gFxydAVQ6EugOx1t9erIEwXN5IpFIwPyN9Yq0LiaekdyxsOIme2hcuJUK9dmupp5BZuk0gsaMogM
mfpSU1rqEOl/k8h4g6W1SRAAgsJoUcxCUhOqcsEEpJffGROkK1zJT3sbEeuyuEEuYxambTsU0/2E
aNe7/+K/nz1dcS7Y4d67PgmtpjqBHEiV1F4s+4wTE3110RAoR23eP7d2FbIuozF4Xm7FnEwLFhhT
0wBFvxQiGRWCxADsJbxlskuCq/3qteswheioedpru7Ws0JNj/g/nC/bFwp7LL/9fniqLgWJbECcG
2FRQ7jlCreCAf4fuv6yaNLDXqe85jBOvQ0pih2U3HENRfDX60FM4tyMsEX0W9iXllC0OxIzYSU77
tIu51xDRMFfUW3eULOyz5pRk8bxFinLfgBuYax05GIXn7045BhsfE/z2aJPi6SpsQ8JlrNt7ZScr
eiM9h+vSbyjrgdVH1jS0UB4kcWhqRekED0DGnRiBka7xXhbAQDKSnEbaKnFxUiHYH7e1ObZdFj0S
/CdApqcZYnC+DwANk5AVk4jJ8nJjAg7sAxfixOQKuAGnHiFmPEtR2s6kvw6OU1+J7Fd/yZlNzLJP
Q3t0dw5c3vk3Ny32PP0A+FVKvSJbDIj6sYQMNphGmAUxzsVQ+H1ueXyhDkrzLJW9Kg+sBtb7ksMt
oCP0yWSX7BMQRHRJvUZKfQBxLoNVq/+8xJwMuciU+i2Dg75XH895jdJigsF+YPdzRa/hRpWQ0DTp
qPSxIwcPBUQWEJckFieCZGdVlJtl4DoNwGo8AcgS69kaLjriygYNyyIDg++XdbrsfK7MB4phTf6x
QrwUJwqRlo+VXxZzobuGG227mPyXhC0hjwicfgGFiTZPSOma9vjb/+VrGdDLD1uWTIkfiR1PW2G1
704eDMAtubEH5XGW+L2LmpAB9J7ACvcJ0a6rcapD082VdgYwUvOnaXCQT2xk4dz0QYeVelucQex4
mOjPrfyhVAk1D3THq6Vz7V10vGzDWl/tuwcE2AcwgIbp/c/5qUaqbvURqo0lNynr06lMQzU2wPde
YlmMBnBzrQe+g8b9bc0XIhyvkYb4LTGmZkuazmN9nKLJgLFSomU4RO5kuat4CGzvZLPIBh1yqVFL
FoIJibHzwEBCa2BpkW5U3Dv5qy6paIeGY0LuaOt/+bECynauQesfr82cAACSBpy0nvL4Ys+yFpkr
OfziWOF2R8o9fv3A0lAVX7ZxZZ+tvfw3iAgL0GVx3JfOaewZ0V879H0cHvO/W+y41rE0exvn7OFn
SCBce73PoKxoD/+h08Tea5WU4Npq8yk4r4O3E1NS+kalV+WqMl5PgpHTKKG2EJmRr1pnAZw8/7f4
ck5mYUZZPJM8ltVbxRrg7x3evHSoji1ycY2uUIMTIWx6CsSMwRfE42mt4XWUppwFK1BwsXY5U7Hv
gUx1uSAThUknZR39jjiWa5BjUz/8y/2d64unoKejsH/bSEDJcwcWZEBbMg+WHL5i/OJWqSK8FXoq
8wvazt4SSn00S/DOK4KRR/SMD0d+y4qVBA3lzKsnrOuQDzhbJxB3vN0eR11Z0wOIXXhZnqVLAT3z
TtOZrTFUHN0DvynZ4ZHpBo2VY6//y2VXpNj8HGH/yPt7Nyvx567SMw0ekK7sv1p1OQTBBFNq0Abo
iJuwKil+BKKolfixZ32rcVV6YfWzFRZ1xReGHn/zGu+gKPTwEiRogi4UIgwspTfBCuv6k5tUhOdM
qPS5QXnlcZ3b3fW1v7ljoazcJ3Ysid+vqNeOxY79CU57hyEOssRrzo+LHfMtCdC82m/1xVtNzDol
fNunMJY7suDzeBojXfSDCtVGnMmRKOtRqdzfn8c/jTmvayKK6vJ8gMFZ4K0VHEz7L6lHIsqlSMAo
JCYXBahQtAkfNA79cVGaPvxBsB31uPWOpoFM4uVcmHNEbKMiDpuFEhaman39HPfti1vPvjTod3WK
0ZplZ+TDoF7VpFyZIrlwt3YBfPs0t+7czDMDWT0lVDqg3AW14HInN/NIyqgFExfWBgCcyI6/ZGoF
ksEWaffeIpzS4O/EVkTNhL8JvjX9fFUSd1NAbJKPKUFzhgGEn0J4HjymOVNeQThW8qNwKtg9gbRo
875P1lJ4mvQpxPHCOh0J27FJBtAdKcG058Jtu6xxlhJk+fg9tceoVhlSbj56UHkUVIZ61q4xSYmR
I4nS/s21ZQO/Y4pP9e0cestRNslGWPiRXp0NGGjJ96i9pgnFNW0CFcopc+cy13HHmBJpzh0G5Fy/
+8D7FWJEH/VFDs8OgXyloB6r3Dx2SELb9yoYSum11PjUsRZGNPPCj59+Clj4WsZo7ZJBCcLpJ7Ct
KFu7QSRSd58lky9FzUZhNwKjQHyYr5pUWbsVdSPwTWdJGVu1/D+n2aZb/ncno37+NS6d7B7DnMuJ
z+vwF+HRe4SLqUrgJSdL/CP71cZ3HjRQC1OLjl76xnfdWgopW8ORZmJalx0pU243xMEsDleFbOJ1
hK9V9QnSGP6c+aflbWe/rdGlw0MJfCbjAN18GDxu/tHFMs3lI+3p4MnCXEDzS13GQVT+PWns+lUz
SArVBtXyFgvb9joExFIICblKC6R3HyTPzySaeqHWcjQQVtxT99lwPMh3r4o5jok4nsL2lSs2WL68
fAhJyUTuZ2Cs3+5WT3rdwQTuhv1oY+e8lkrbV50/fGk2Lv4sfex/trDbaYZpsqUmPcyZQUyUDfIF
zG06wGBLE98HD+PeoD6CTO67xwvtcxkvO07GwyNJleuShbONDQAUXOxtm0rGqib0qQnQCww1OoJR
9dQ6yNcVL8xac4xSdLGOE+MjcmoVOcGnPuc2y3iQNEjP751HcuczdfiZXVbvtLixFd/AlvY3n2ZT
HGvkalu5Kq3g1qJ+oAV9DPRE98CvPFIzd3u7RrdDwNqJgT82rPwxOvbSwsXyAuC0Hy+kqkut6wvH
KiZtKh07XuAVrdBV4VsyYFBKL2ADC+92F0zHaDrAKljnX4eH4hRWAj7SlQD3GQNuvXrBQClKetaV
EinTJNr2uZX09pUGFlX6LTI4RsuJS1oV1vvjOaciLTtzFDuww7OUQTfTN0Kzf056uOekL7F70fm2
wzrKBL7LepuBjgUzeYFTT7E8bZxjhljs1CFhvZTA8xV1ae9mfi1wuMd1nw1bSWZtG1YikBxjzN7V
rDFPt+aexvCT1+0EnP6WSx3Hi1e/jxDnQiterODwd+PNiA5fU8rqdx8Yt7vj6kvSdqrq5PkrYTZm
oL8vneE+wy8BioVAmyHZqJQXtDj+ZOdXI9ZUqCOcNuyo9qio0Xj4yOvmwfMGNEtjixlRJKkL0AT5
ePE7nR3hnHqA8gtTaYjByabedW6M06QAt8KkaDx2zy2XeOv03wtrjNbXNoBe7SZcF/ESSJuCiQx/
aThX3DmZbxkdJsbtnYhPkV2vIPmRuAgZLkiBiW6XufB/lslO202xffF2LAPjJviVVixaptW84/NF
5qoE+5DGuqPBAxlFCMeevIsT3eiLUvmeRLkIqAOruQjPQ2veV1feeMZ+8sAsgPsMpr5FEJO2VwhA
si3yHzm0FrXTCW0cVC/CUomOgvIzVJvy48ZRntkpSVBLZ+j0dhA1DhfjnDxpFHeeLNb3GKdZYwUn
Obq3HX2YVqz9C6lKbJUWxijjggYwKH9ctvX24+dtVoP2GA0YWg0oWhMoP39n+ea8jEJVUSvemoYq
Yn/ynffNbRzWOYaaF4EnjyrnpqcLB905SNPrBG1FLtN5wfHXAnCuwEKov4++YhEPrZwBhMU6zpEq
+I1Ds2lco48gyyXmVXhzyGcCfoJPcZajXM7ujljUvjFMJSpXZloQ+o1SG+n7hH3LsqF2zAaxbreT
eT3vc41Q/dzED2Jh0N1YP0/a09t3zWeCtwACvtsz5oViQCBIxPaPDXkkGuCcCIRu0+TWQym+LQqB
BLVS14If5fmXE3aSJLP8kQUlD5cgLXMLHIMUlGc84JyKK4nlougoz1hXQjVJ41se+CNHypPzF2Zs
tsaU0KGoWbIcYTbxRurM1hhzdcxzNrHac9YG469KFu/oaOIH0SP9LfhZf2DSxBPjuq/XlbYjaw82
DUoaQw3mcfAxkisIbD09TawTYQ4R6/vN9FtN7fdQWNuYbfwsyMprjAw/a6hJ/Z4yGOKQulIlouiN
+uW1p9hvbBmtl3Uc5Y1+zBmymW98VKF6zf+OcAvJYVhEikO6CW9LXJdRbiYj6oqUaJKg28sX0M2B
nuD5AH6AQEh5NbDUT7GZ4xT/p/Hlkl/SDL/Y6ubvMV0j89UfwP4US9AHjlOJv1WR6A39ofimvPKr
EyhgmpQTN1PZNoGF0eggw6x1OJE6ixOCjstJshPQxGG86Onkw0RCdNSjSk6YIDxai1JclgORXIBK
UWpGQ/efbXpIiWT6nveaE3vHit25xdI/YWQPYJ5/StqdnbnrSHxWW34v31glDrRfJuUZYRtSHYTv
YaHrJ2u2Sy2275M7gfGPzGPjCcSn9neivylOLY9f6Z4RyiMb/FLjaG7hGaDBwdFp7cl17tjKiFqy
6mE2jnr4N7XFL/J2QMExGrmQtR6X9dhlT2f2i4lyrpoRDN7zkouaDhL/DgHX2AwweZHTbtZ0wjMg
zlF0vJFpnN6jFn1g+cv4Z5+a7Y9COSOs+Zwz1qGOx09q8OzDASap5lYUbiz6uFz4IvdJrlT3InDD
PZTksw8p0xkBnsNLoIwSmjnAFe8FUOkXzSZ44XR3rVXo084vruN46Jl2SquBibadICNWQLv5Jjoy
PkO7hFbKcLplTUaGr0S/jlroKC9wW3xUrCRn9AFN6jmRHg6LWsDzBYhAVLSQG+scqX31AHzQD2V7
54MveES3p3wYo+BNQi0WWhAfKyxOnJMwTN+LRUIvvBxxhmh1xNyMsKHN12QHcdnNPXNOG6thfw2g
Txse+EXg4GI/uwebKqhJBVPjoqKwgdtVOt3ckv3r6+w1PrF3QLVDM5m9/xXWA+prQv+cXLXqM9Ma
e0L8j60plddzAriHc5EXqBeDPFLH334EY72+wGpgjHtf2MJnFpUodwACRfWIJLEnR2Fwlex2wzfL
2xElntH+DGvpcOVwIPSYcXvY4hEXdLWaOTl03UzvPdNZAIosJtwiiIUgPWegi/ho81FCcDezAFtD
PeWsdE58Z8xKYhkQQc45pDqu7CzWYCalolkhzGSLARoB4hY/yl21PHjKkSVqOvFyBTkSaWttFs3m
Vh5TAaBaKZ/X7MdFcF51TydkLlhR2ZH2WxMOpSTLSP0d84mnN/0/YkNjYISwxqsaUi93SKKjZW38
nnZlBOFRNFAVfw/u/HqG2s7T7/aDNwe5bR+SBrNiJPFN+kZYZCGCMiqBvABvEEmwL/RKOOEPDJAD
ID7fdhToJExSBGqSM5Cm+I72qIafCzgegPb8Ny4FcdHeqiXq6uGtXcjSg3z21jl/eSQHRovrzoMW
QWqLMHL268sZz4ybr4czUTEjHSLMl/L3m1YB9/QWtcYCszGZmGw6FU+myQ7wfsxyZpbzTQ7DX5zB
/s/GDhdlymmSevGB2RPxYpwSMT6YSCJdpg+KK8SdOrkauLMcjWooyJ+ezgdeTMGcHLRN2t6vMdY4
Fc3tr7OxnDTu6R4CqjQQS/KGGi9R5tVO59BgiTJr0oq2FYy/75xqP6sPwykgcK2xyn/JZ7ietBJm
ASnlq0WZt3xOjFz7TODmwDvKW4MoCr2QUUUhGg1tHH6RU2vP0P6I79dSkF4LmZweMj26JvT7dXD3
j2PuczN/ftxACGjFejbqvMNeaD7AFlsQHXQmqVJqh5SWVRXIQQZzpR8zb9t+MlzBeWPAC8DYZGGV
Lk5w5W1ViJgCsNNQ3Yv/a5buyNOpFTGerp0tkBH8J8+v5nmirRe8/i26Rp6exp3gXGV5TygxAD5U
jA4DFIY2Qv6Jekb8iErd/bBMuvMGtcuCJ7sz9sarVkia6P7NQoTsBciG6L23D6Uk6gNeAeOKO2GS
Hfq9I1EgM512wBkNYDXIWvHswR9LBFICBnaNz14/2l2M8UAiQao5/WL5as2PmqP7tpApliGFq54l
P6+dOU2zGRNgghlt3tbqw/+rf40FCZ6oA4vTp10a+ivvX3zyLmScdG2Q+1RoZ5xfK5pMuaucW1np
5Z7bSTCLUM75g/pkmAUdrv/tQOcCqfx1y7WBU4iqhg4hESSzmwt0euf879n0F2JviBdR5xEerb+X
N0xKBb0JSyMI6dVBFYKXOoHK1n2mTsCmMKDgYls4zJtnOE7LFZyQHjMQTmohL3e4H+eQSDw5/R0e
PSqMngvA0Mt3UyM3mcNowyjngdZKX1ekKdg/gac/w3syb/U24Dz8SLjjCnvUHcY6OUupI3NG2VfU
jVNF7KPPcguAAUVcHYEOXKolEVmHfwrY0j9pWDS5ldgdSFVP1jtJbbI6/6m2Im/FDL6Y2i4f0kD1
CfVMqdOvoSgrnzHANpedtgCK6tBWgfqSQFx9oeOnhsyhVAvwm6Ave3/wxO8xMkYx0uXpzYFPXvvK
jt38Rg+eGSqy0lfbR9SHODJFc8m3OhJ+8YOgSZLJFDRB6yir2+T15q+rnI8FsG6s2mQrYUObtlYE
yHE/1xjCdcZLIP0+qN0HAGLeWMErauR35S9nADrKv73BVHOvUgtdUPEukER0y1gCtIp9gJk3+F5q
UJrcC/3UTDby+2Z28XiWiLhgMUNReCGMA+Lz4LGSNuKhCia3c08HvzJLpAVfa/A8rY/BXCvFZsvZ
AUvR7uKum3MCAq2iQYo8WZ+88vj5R4iFBBGLQTSK+6FAeT06687RAV4S2z/BddNbWxPnueHdnSHv
qSI87/k4vmW/8fGnN4i4tptqYrFsGrN3vkqOZynvckoXn/pTCwtnmlJgk0I/4DIiGPg5U6JuvAmL
THBgIos9rFn+P3z+s4KFykF3QGOSmJKwhhq7Dd10Yixp25G0SI+nsJtTyZMVos89UcPUzSqKf7Pr
u7G9S+BjflOiCzvdU9YY5ia2/llDe94Su3sdVQyuNZqabiUKyWyu1ngMd6Npels+9ZnlyCqhCKzT
T+3ohKy8UV9pJBVqkG/YDkRNiTFrhU01TGL72yxF0i7JvcvSaO18N92TE1+xOvooc8XetjVWEFhu
jFXe+SLQ68byFF2R0dXacn1n7rQJx39tVL5nE+sppyZx6rpT+lcli4HFoEphVqs/1xco1/Mfyc8U
3mpKpFuKoN1x1yp7mW000m0Ty1SBCDajeA6riOtEGROEJVIHcWfB6SbkABoS9RdOUt/u6UxtmaPb
Fo6xPItfIQcxEwdmjk1KVAvy7ldQpqKl6UV18TP2E7vc4Xvu3DHznwKcc1IcbK9DdqF9IQY+u90n
4FXbf27lZneIYhelMffQzpq2RzgIlXJPl1NDCvpes+RWHC50Gwk6fCTQOLIZcMEypYXDxLstknaM
dne8DCFrd0pP3es3V+CiEPRNniLV8k1jZNMdNUZG0pcLbctyspeTH5nrp1Hub8Id3UwiPet9lLog
EVsNF6cbW2zW4QUVL2OJTaJqXsnaxTgQzA8m8EgdQ82yUdBMOx3qVk2ohMErgRNQJKGQo7lkXber
pp8fJN/IDkYENC5VIVSlwbcGCo3ygeC1B24kQHsA3czBbYkf+Wi7Jc6YCDJtmI51GXEV/PmAxzu4
z5/AcZfx3ij/rsvzK+fbXO9ELyaYvRb32LKOo1STNzsqXfb3ZpDKFhojnicIJQwiesvZBJaTImNZ
I1EEtpH3wLiyUXLkqJNds9moBG5K9jQ56amKcY5rfqFgjco/Na8PYzkxxO+P+mrUIFVFo6IyWhdU
XJnTefWLgir438uUDMtqcglGzKN97Y+hykPaMiR197ws1tJ2lb9hkA3r1ZDzQItE1qO7fZ0KFTmN
s56CobBUwpEzfEjZ1Ce22485B1aIdnAndvziYLMetQ68+J8j/dwJ1JrW5CpV1XLQm6qxev3e5gU5
HQlbIXtW4YUVv0U3TF5JtDpZxR9IGv60TwDij/3tnjBeY+qyKNl4MVKngmPiZXGK88/W01NKbAGl
jHkJUGZJgWF1DxJnHuw3VuTavHztCpk5gHrPNMA6VDU0f/S4t8Gk2fp+eWBOT8FSgpTqWhSa6sIV
mZGVvFKvbT0+VRqZYXObwvG8C3c6gbKMCeW+m8yx25oE8ilVfHc+ucZWBQeqTxX7/G2lLiFcDqNh
g6Kwmd9M+2b6YaXarAObkRn4uOrg73UvieVumYa/Z4dydEDYrtNbE9HG+Hi+tC4oyEtYKYXHkuYp
PfOZCTd68900AFsa2JkWaoyO4x+cf4W8L2+5Xvz1PWfGhX/xiP+W1VvX10lAbYYYXuZ/01VRFh07
QqVFTCew9DO3LZTczVRtdLCIV6h/V5HxGcUryuohtvkpS0bNN3Fl1PcZUXYeowTtLVj15jCbwXzK
Z0R+r6YvAYZZVOD6gQxkc/xpOv+cUx1QB7QtL7Rk/sW22+JX8F8Y8DMAkQSYWOMSdy5c2+he1l9w
pivXNcVWYXPceFRk8VmwXzVd6L9/C46kxAK+lex25sv66MtpGKmEgq6dWvl8m2aCnzeMdBPFKMq5
B8JSibNS0rrNsjz8oW63P/hXqBdwr21RNAxQll06n6J5FSAciHN5GE+jjDQvGVknGXhoKi5DE6NA
mq5ezHTa56rD94psUWUTCffHqkAbvZsaM9aBVSctTKfvWk0EkOjZNIiHC/8y8yozX5bYkswujzA2
Gqt+096LYcRrXiaC1qY9SawbNyq2j0UmvHxzRNolvBQwoP+LCpbXwP9meFf5WKre5M6OEuO6ZfAv
uzVDddlZsNe5o1ChWgNW01sDY6vjGmcZqO5ZwHFBGuHG4I8yzARw/N62GcKY7h3C/KttplolEv7W
U+9K2JY7EkPSYXZoExYVupw2G+E0Pz+VjRiTtfTC/MFewr/U3lsejK8sZvBctvcOeo8/2rUp6sNL
CEwgPYI9ib/yYcIj3ZHrPDbtJz7zpcNBENxl7SQdwVvukj6kc8WUKA5emqkbxi5wfEbKuFjGxs1j
5YH68EzioTu0C46kVjYkZL70rFDXZB22GD3yK31sjE6y6mgfJmdBWxakAuzEmXAHPf/p5CwvRCCS
Tym5VeRGy4h4TJMmszM5vcrg4sNEPClyFDsbUXhWSJXmCThnw1g1zYCO3W8p2SUKwQ2GxiGiWkJY
nma2prBK7t/1UhCAbubMunpKjnhdVdj541jOK45064cDIZmpNSpnjgnN/dUrezohKR88QdXGQqBx
L7uIymEeZU2Md7jONJuA3TNTUq3gaKTqkljeM/lrmFJKpoLdnYKWMbQeqV7hstnapHqbKRdhkoJ5
HFBC76hNFjr/X8t51BfVxQnVTCczvFS/8WZrOycMIbvIOcLHP3ve+mEAUJjfRk1lsQit0slLUaWU
lhxQHshI/EfTTzde9OlZA0Y/79+dFEsqOAOuU3PH170oat7SOMfVbYVDoLSybtSLrfK+GlkPXD4n
SSWgx7FFU15IMPNudZpa07kMSHaIQIqEzVg+5p2GuQh6nA4AgTLGN3HFRsCagM8LPa9Lrpc1UqDy
M2Ox2th/TNLFik8gwTJBUdQ1q+IgPb4L5SmSLZ/te2Jj2Hfq03hfftWqrUE9k0rx1EIp4IB4Jeg9
Xs7ZltN8AEg4Bu8JeZNL+OYQQApoTKV5n6k6aN/nYjXgs4T9QiT43R4wK8Mz+ibdbnjwfneGnmk1
XGj8Lu5yzE0MtC1p6FBt5omj6ut6YXSVHbHzPLjwEJTu3+/rf1cxiKfqMrxIPNauHkF4RcNI5Owx
NoBEhpAYnvylT4ssBtAWr8Q/+OdziDBeVaSI6dya7Bc3FmRPF4gUQih0XJAX3xUyy00tHWXLQcbo
paFTSod8zheD5OVkkqLnAEdpHV5ze1SsiVME2I6ZhHPQVKDCfd355+OMk5NmGv1F+BdrlrDDc3ba
hGMtp+ATmorjXEdAc2u4UWAfTjbGQyW34a9LTgf6gbk2jv/oqCwo4MDhXavmEGiHoQbJ+PTrziRz
u8vXdWhuB3EOu3RwbDU7oX9J/ipN96yoBo6GvaJQ0qgRtY3PLeWDuO3PeBlvPcKkpgAY2AvEZXAT
5uNP7TxejoYd2NxhHjogwV9FS2IvXGcuBelufNsrUYX7hZYuYnf+xlYSLhIPfWmqCqOVbrc5W981
OAHe3hxUz2zuv9toTbgTVP16jiudpqWZFyKhJaQ7M5EppmJcq3fhSRinOeTCx8P8uiMGnOFxoDRD
PxlRToQCziweC9a50aE2pRDJLVm5BR4p8yStEZu4AOu22tfUCLACtegKgFzsLArqjkozGeZorCWy
MILZlqxCQr77yCJgx3DlaNtwf3NfDwzryGVQ5CQhiMIT43RZgHmp0U+eTJsECPgBiHNxRjy/ZKEm
AbGzOzhU1C+Bnp7YIq2hBBDLTEUnVa5nT3RXtMhKJRYYs7dOcV5Jn5ouy3Bez99juc/GOb7u9hBT
OfwkF+SalF4Bd4hOqMOIFOTolOOG4dWXb2JyM1Av96V/lw2oGuDb9ZrIEZ/LyRHI9vnvYWOEFgGT
QmGI1X4r0R/NCM8Adh6DALob0qM/W2rM42M9p4eFSOJGfANgm2/tdW+Oqn2GoJQM6i0vjaF7+jBx
xO9ffDR8U7/MKkPA/aYGj6YLkqnqSyCWBm4Zys3C1/oZx3svVUGCc4dn9hOw4xPfgLHKADlcvi7l
mNXtJa9U/yfd/25ShlUZo3b3KG5s9sv8+Q11uvO2J96+f2oWw+Lab7ClfBC6OJkBR/JWv8hgwaMU
xxn5mOjowuViCcDqtnjUuHqhxopai1QJEzUipKLTAVSipRNFHSr+nKsR6uV3qrPVD1ZK5WIuP7sp
pNhvZ5/UT5NfLfwnuaEZ1QgwNYtN94/xLX+gIydguy16Fp5aCMSqPhvVqpiSLNCIVzxpGaVi8XLA
riFt0htSWFcTRCxY4r+Slyiabt0m01tUBhiFG5EyqcdbM0xrFoaKddo8RxNzAYU23D1zrTUKaJRg
vZojLgXKvp6MzzbtLuUyvUm9bAnCcaPGhNjdAaGn+pT0NxbexrpniPQ1IRgBjtaWQa/pXzqK0lMk
IFjNpHzYy+e6zkUO4/ORBuEnt0Wlpmv/yHvYAQOThsn8GEQB2yPtc3WKrjvSAXT646ZNgK3wno/2
9nZ52c8r6yyeY7/A5oIRVUPkOGa/xeGoP3a/1mNb1xQsYrKNGpgpWlOOeoqkONt7GijdYMhVlYNJ
YEMGuaylmVM4SOGcwdnQmn6p8Ug3Giy838+wGN4YCKZ1spYTI56vqrZd7s0IV6vYHtOkWOnyREHL
9/+v4I6mC0izxOjruyYMISezPhmagM0AS15cgpIWM2O/rbOqRBHQ4B6qc3xSnHrQ8h4LA1vhdE3y
5Q+ykMDng46j6neapfe9XHTMBt80AluX15FVokoUdKcd56kY6fsnHlNoKH+igMIRrE0y37Vp5u97
pyawlFt9BIQTJa3jDHmSECZk2sunITRk9QQJ5irJ3LQ4aiddmOyVGmv9Zv7MxcVAdOvR2VzMt3xc
5st7RwkDqgpfFFIpIOgJLSlRtkgsQ19eGOfrWplZf7+p0rG7xORd7rYypMRA2l4qtVY3CTFtSZ7+
wmNfX42tg68xXaBlegez2IgrhFrhmLyVvFXCLhgAK1L5L2kKrIs4lP2uVKIBuhkfqYU6waWZ9QGb
ItuUP2DAetA+WIHFUMd/l5pkweaLpnO4EMaXW/Q5f9USlxSujYqTdnhQc0S6t8D+wZddfcjMtO7e
/3Wc950nC22oQBI0HVNMnEqn17F7uZ7/9cJ2rZ8izCrzUXMaNREJkYXzu1CFGIlRB/YoLPUNOjGr
gJhEouApqgsTyhuiRYA5lmitEzO/95auWL6m+gh/qJSWNoJ7NHI1ddD9A6sE4ljvduE+G4totBQg
7evN8+SwFYup5kE+W0JYCe5+AfmtdS94iKC/nD3AJAdWRVOwq4QtpJQytxRxbs2/748bESnapTcf
Vz2Rfq9lJEC5v6+o0OZildcAxc4esOnKauXf9rwToyOKwRH7SN0omwT0v9O5QqVEcXjbEpgT+2KD
8vTrmWqiFT2+07566dithMSZMDn0V+RzWOqolPhjl64Aaazf0iVZieFyz3NpARXLoSC0BSvXvmV8
hBMkOBzZFKDKLBjfEz13G/fd8OPVU2aKwy7E1++r36oUZBPA9L+B00sqEuhgw+jazoe14VtmGnij
9Fqvj+VhZO14m8v3OBWXKBnc2IxiipD1P5Ozxblu03uAdBsJoaOuu2p8xQREXxdCkhry2BAFBIal
eZuhDhJbPupYn8cNo0o2s4ZtVV798zBuycGGW703A4UzhdG4tSliKTNjrpQ60STRI28dtdvuRYA3
fd4j4CeXTfnO5loJUWMmrNM3C8yKkSZgrxkBw8a+fB3UfjlvLjGjoNH7HSFvxZvD+fZNpXlDKjux
/R+4Wd+zBHELcOVQ7RU7ZUJKMeXrb4leTVclqEJ8eDL520EDwo+l0GhZRaOcNOgitzTABTy9YRKU
APcWnxWoa0cGp8TJyzsJuagJGE0LGShiAiYD+bruMwEen23dLclllzRU4AuREIwBCd6R6K8QVhcU
0pfDI43uzlUwL6CjxDmCqwkKV+V3+TBRVoPxwKrOFudCtPUE9julkiioj6nyBsW+xC0qqB+Ta8zN
wnedb1UMfjroXceKKxFBdydGXg/Gaob1wU/um2XRZugTk1Y8Kbi5zDFFqurs1K1WRxqLvzaMTjvX
zQOjFHXMnRsdlVuaGbYzTA0T8jUOLvDhc+wbNEeRmor9jFEhNziVrOD1w58JPdsXAeYgFRP/g6AI
wQFxOKEwHdlvmPmb5bo79PKP10zMeilwgAjrRqBcmQi6T0s4jlOaoNiOygHczxISwCsRqECF38Mw
Wprhwa+A7BDP2vDmCmclv+JlHiqPNHfqjF9a30WmIA+oRZGuPn4bBnmM339c+7ZChCRupwQkR1ai
4wCjaKQt7qqLSZ3VMXmRzQkt5LKEjzwJwKTH5zPnr027XzpVyUNNe6P0TSsNJWWM8IX5CivqkVUF
Xsi2uguzj+1eE4cwloqQ953bYb6v2/HKB+jHwi1ZIAICZXnFFQ7Q6fbw/RGjEDLmk/lLsUAM2gx2
eP97KDybnDhsZACugNYhKH85R9tzafL6YC7c0qttboZB/ObRyZ0+H/ChwTvuXftmWrkQiDMpKmBp
51jHl5FTgp3UiiGdPXcOABaEAgnQFvzaywkXZZuos0t3W81LYzVqCWXm6z53k4byn4NwfzVPyyo5
eUexHffYrFTaOwB/BZkJsHBJPfSYhFbJc6cazSAd5arMxYTDcUDv2cZcDnpjN7gqh7doDOqIeACC
oLKEa/99Jbd6dCfoqigvoevrQagDFlk1JdDcpQTAeZ2r/laq5hFdmJejy+C8hvrcw8jgpTuckC4e
PebgwWc4vmjqqDSRwJMl24eXrmkPNqjGUU1xWddizeDyD7wkLS6w6MgpWSjHaJL+YoaLxse3eOjR
b5l5mDgpqH/1c0VKgqkb1Zxyr1ElOM/vl4PDiGpW1xetZfnfOKsd1sTkA3lwR69on44CkrqKYzbN
eEdV0aFg+Cu8LrrdgdAuRPoAhomI4mh+iwY2sZ54T/8Gu9aVBlEfwYd2i15P0JwZUArqwhqrZUXm
ac4Z1vH9mzI62mqyrFAMjfpJz+pnMowL91N5DaKepipXpCjfCB0+UYaoy17iV9qfRFwZw60t6NYV
TfKt5bov4bPk3yn/mXPgzGTgtr/li0aJ9hPAEgVNfDwmZGsYkVKgxsfuorNsay+Xq3hUd9CmLBX4
82hu56YQHgLwUI04sUefpvIMQRgjRN5/OUrKerMEf3Id9P1otAakYNhOlq71Gyk9UIyB2MT1Qw6g
7sSoc3V3i7DSD6TeyUc2CEsggXBntGr+FzCRigIxcwFHaB+cWapqQIlQP8N0JTOs+Qci/SouL0RL
q6l9yx4j1i0txdR8Wt2JXkTQdpVH8LV+q6S0tYm+5oiK+5tALhrqcQ4O/eoOFne9hW9T5M24ytq3
bEf2Ci97O7LvpHTLIR6amWHkgF2jO8S46pyH3xfHfm7/XPLvIhW1UiW0TONGblBn0v8se8K9/nRL
U95zCkKw1Gr/Lk1dRdBiXGc+TZaCbi54pxq56f9T3h9ig7JvzZhOipgD1WkTGqQYZee+1H90V8en
/55RkSGv24O6EWLmM9foXF/bmdPROp+Rl9hA7ssw4/3hyCUkb9LFBrfochxjONpuLXHlweVGbAAP
s2mspEC2Unb3haIt1DxQT14uyP8X5+z0uiXvuZkQQlKgb6hPMiV8+LoCgWpVl+TGrvRNJs6iO8jc
Kq5C5/FOhpVnjs1GdLvE6I/ZVo0+z4LUeMUuGzF1b+5JJi8jA30uRKPfoXhBJjteC4CNv2sCHnQj
VaGyg3xJGokLtXQ1UHCEdd+0xjSLTjbEwaeyNH0Mt4Wx3RJb1Fage+ixt4bSBNWhNYiffOXicWII
spWsnoa7AjJwpd69HnnkI9NBJ7h5I6AxldxS1IuESVyIGSVJhsdH7Zml6yQNpMZs7yYrscJMJOcz
srgmvUjPasehvQvSjg80PEye3CdYmzj+mBVZnGu8RoGefDxERRMkaijuoiL+L+ciwsVvPUQxln1t
IoglvV86vQ0GoBGI2cYDnhk6wJuHT5UkPtOQIzHP6GRPDD1dTrgShYq+85G0OVqHjIYRN0Qt3hrD
JAhatQG6dFGVSAIRg/FC7/9xogU/XezDHqwmhwUzyVCd1d7iKVOMLJEPSezkIGTGphVBp4oNVbvJ
4Em9fOk/0U6lCyYUs8ukR920JHTpYZZd+Egea0fkauajZZ6Tf7hp2UIGdleWdysB5p8kgP+jnboj
Dqi/HbVJiby2VI4dcIYOAPybHTCSEwNFn3QzFfbS022sJHbBmUeml46TOAV4m524o9bXojOS4pL4
PzPn973D9S5hIVtxmZajYPAOMUcGkqLqL/JFWgVqojx2qS/HMRMSz3pi+HPmmwG4HdTFLbnPVljn
azslVxv7ZV2xNCrwcY+SvC80uM8R+r8SD50plId9tRqifUIOCR/Ub3iDgYDZt/yp+mOa0wAOPr+g
rPEURfshuucGwbxr4mJjzFgCvE548WvFijlDt/v0Xm3ZOaUC/XmKKnkA8X7EOkpe6zngbc8uSgzM
F2NcnCIUAsS7uOBtpb36YafIi1kLdeJkcBx0MceUGu2BUSyug7PiHxvfZpWl6D0ZMqxwNEc3nvCj
1TM6ZaE4WNP1BYAxwqzSXdI75wrqZ8E7URfgsUhhWUqkIpoJskLaMn95oBfT2kDW5z1cg4gpMj/x
iK4bWUCli+w1oPuxka5PZb9Ogh20+rRHhutCO4TcCjaT3Wh1hsnBgUH1CbEazfqCvsdCYFUV8aJ6
gE4NLZj6RJqtqeGLLDAC0RyczJG6Th1Kk+4eGH6lQQwRcBYW47iX2Bf0Mz5tyQemUjseGdFsIFUj
WovIuvbKXsLDq2DXL64f1hpKPDNO5HpRdFEUJIIVeYEMJp2b2CRH+Vx5//w5SmEJt0zQxnx+o+Tt
934BPfBdU/ElIaETMRMVK7WjY1pd6Bu6KTGN7NQz5ZJv8Tu6Y8SdmQcq+p4VzWoPU6g7HSfSUj29
D3Gjsnv9xJi+KqWGEu5U/iEhuXZ34jeB9gZ8mF5Em1k5g4GolySduTy8+P9HrUYf2Y8KSHNrq/FO
ANiHjsDL5O6sYLoL8RNXLt4gkCLB/r7rfJXk4f3N9aDL5XVXZBouCXUU1HdE5wUBEJ6mhvx8WmlV
JvM0DDRERrf7X+0YJG2taLvT3CXiGhhN0aBz7/cyrqh/EKaRv0AmnoAKMGkAm5VULaYTZObE/jGX
D3bqnE5/3Iv0G8CZ61HRWBp4cfRLr3R+U1cT+LMggaffAojGrZOyR0vpZpIlY2o5KOhk1NNyzx56
aOfOkCOWLvxd8bZwhNl2hcVytkLJUAVcV0fFtXXh/KbEdqw0gZWiu9wtySR7QJ6Oh4qDPOvHyM9A
UkhjkvmJipxkMy//8gbW71QgU5V/aEdLREwF5Mu95vJvxJ5Qb69jeRWEaaMDwO0+qqJwgx1amrYG
NMdrEkRid3xBhP0PdzZx5px6nNxa3YBsG2wRwBg0P9AsTWuTs3q4xAG2YI5giAB7cOd8lQZbA8Aq
lXvNbTaVOd6zUL6uesmWX0evCaoDEQqXqiRs8qdEziruGpF4GR1X6Qp8MY+vENCx+m/oGIV3yJHv
bjG/d/etdXt425Fq1jE4NRUbT6VUqiQYYSiow9uOg8wiVhr2NkNAqnMRm7gx82tM0cOZGy7Zt7U9
YTooz9eU6VvmjwKKP3hV4IiBYlb8DqYuaM9b6Zt8Cr6+oeRh4rpmnNFP8+FnKrt+4YBCsjapfhM1
o+GPUYNQGMhQSeh13PQhG+8e5kSSMJIyU/te0XeZtiVS4/6oAa2eT3DMDdKG0p7V1vymx33N615J
4N6Z3utLdLCucmA27PUHYoEpOpmXla4UrBZdPVI8/u3JEWY3UmoHcxVMrSoqQb7VTuzvcKOpzK92
t2KKK0APfovzAQjUgDuKpJ86ZiUZU+v/hDC3M+iz91R7C48QcXpAI4oGS9wMQPPhY4G5iuBy5Lzr
qd+B5/zeFtjXXmTq198F+DGXsb/LpuWK+e7Samq47uR6X4b/VnryJz2pj8j3/22iJqdUuMthW4Ek
sucHj4Blgz35A/FUShOB5aMaFGIWI1ad0yY4vRu6XkPnbrA5tVRqSOTTIKqNaflNMJSOpNueD3l7
BvpId9qnQX0hIXnK74xsD70q0Z4QCMhMPx+TIKq3xynmnacMjEvxSpjJDepKU4S6N05QQjoYp1Hc
UEGQ34WONcUIGGdR/HIigdYdKcr5esCsFFvYq4uLvdfM+768KS4vCFJSlMRS1ZiTkwrkxhg552G+
KAcWfCbgzJbYvgTjbcZofhfhCloxVBVpHEWapEO6PireQJ1yGiXDS5gPXpf9kZACpe8BF5SomzYE
tj1wbg84sk0IZB92c4jQRVwBPuTReKuwSIEjijbsxU8IW/2Q7vMyulmIxmbOJarDunh/Fq3T/Yfr
fS/5dbJudP/OUTKwy/LOfFp+CW57aAWziBnDCTnxUgaIvkkKowH723mTdPjzRyGPMKtaIlWRfPKG
75e37ebjble8c6JdJqzKKpCh2+7yohMdmabfzD/vwf+mSX3XjFY4VFglZ8wHM4NWzgDDHjkzkn+r
nI3FiUGaTofYoZTmflLE3+pLlMa6G0sk+Az/zygrt2PtsaNYNlWTR3SqrqwBZOv6JQrvxRkpvFJg
VeqK6miQp8jwbAMdUytzekmxam3obUHUJxjL/sKXlyOi9ZPWZLAjbBY9zXTGh97Qk7xFGtzu9v0b
qjo1TE3BMUBEHL3dqq7nU+0fFlJq7B6LRsdQ2NAc+XepuKyxGINFWQnR9EtYaf46P7c99BR7RN/3
tZgtHEApWcFEPL7m0tH+wl15q0iphjnbOiTAxHaNqxsu8o7mbVK8aC5L6el6H34qDNgHfjClbUiP
FZxlwFLZI4sh6LYwvV7s8CZGSWMvYTazdbwGugXlFdlT0e3yca8iwZrmGsNqO2KtnSd7E2ZpGsIs
a5AcgyJV+i5WzmoPap+SGg3Xz/JmGkxy8/pbZF2Jh99WFay3cixDNcNKDIjh4Afxgxj9nMNpskro
Ra8VdQeTCGNZrKZJpzooPWEI4/QXFc6oJWClrgxdHIJVEVy0pT5Bawan4f58R6pIByQzTJJU9MfM
C7J0By/QfQ0XFVIqq5t/0sU7GT9TFQfRWKZg6QlB527Z6He03cABB80Neey7a0JRiV9+Lu4uZ7No
migXGOtC6MSjwBoLEzB+cWN6S93SjNOsd2N5ufNl1Vl/UFw2754HZV40+mnLUYe+2bNB1Y1jeECL
ake5kr3/ouUZ5FqAt9+MvyhKr2zHf5EUxwTsvX8bZFfb0g/tlhADkIKVj595AaP5d31/goiZ5NvJ
vU+Vm/vNmAU1Qrg1m+rOFD62/PrLr4AReLUHlKbZNdiase3fN6RE157dAQxpe6vte4HLpvkXB262
679nTqMK3/40GF99nQrC2g8KGw0yDUw/qpBOa7uWrec325DyyltUv5TdwaZ7Q9GELL62OlHWZqiD
J1hArUqrnG2btTzuvdVOM92UL6dvCtRx8N0LQn+2WJB+zYs8g2N/psLJsZ4kTU96NtQ8vWjX7WFc
twQzS9gGxGJU+gpgS7mz5cuhcsiuK1uGcSlnSpix2BIUAxM4mSbc5gwBKviA8rTuUjzxbWiITLru
ml3ORQY+v2jAB1rEs90xGkbaXIfsaIeImxEMjjGsBDVrwAQdgNfw9X+R+BJXd5nsyJ7RLd+CCWAn
QRW3HWKIHwlVZP9ofqaAO9k0runi836ndY6C2CbYhjlpY0uX6lSREhe/B/zp8X/P3r398yXii6Wu
Ei8jxfB7F/tpAE16JA2cULWgYHkmJqu5dBBe9awK8B3IQaew0+5U+zpgTbfXGXc+79gXbKS5YXh8
aNa2TbqOGsBwQEXqwTzGMQZnrzhF8Wb3Z3R6w/PXZmNBITvSOtqc9X7yTfukaYrmi4z/G/+b0DlY
n4BtrI9eDC1eiMTDnMSac2NUeiK7InwOX6abrVsdhkcwStg6LvspMuE+3ubZmSalm45XhkRGQSkn
E9l7oVC294YhMmYqiTEy2gYGfc1Fv6L6+uD1SFs9o0RRISlOIRQ/jYy+ErE2fVbhIxcvJCizHGh1
kO4ppxrssWAVcovTkVQ351AeDx1HE/ibdipLEetTlG9CGzM3CibHvLDHOaoxAdCeWTCWmsVMVIMM
ucFeEuC7uYxzuirHZ3pSMJipx7/aVQLRnwkc8i9043VcROMX1ZAI2Ar3gyXm59wWoA+Gh1iMCIxl
Pk1w2rVzk01+y5DxY/+CzAS2UGLjgs6Kk7AzAakX9XT9a90EkvyrTE7OCkONmL7RwCUoN7TJI7n2
xUIlwuHJkRqMtuDLlS+jTy3FMdp8lnUemO8urEKYjxUiAjJgmiU2kmT46U/yY/L386C/47zrLtt0
wKbRVyce1GhpraDOongsnnhdikaqVWK41hhTOp1IhSWli+AKPAxPZURzImAb51upjWdT5jx0erzs
bXain4glqv0xRMHGwNZStzaWqyqZxotWy2dfU52iugTxWs7ArQZTBW9WhEd9dnZ+MhXBL0GlLq9c
AQumg+recJCxFIl6DENPZD7IqTvmPVmw6cWbkzbWfc2Z/gLFmYpJJOZVbgFJ+zmxKSwzk0wEN2I3
CNYYPPUByi/pyzib+tY1hF4IJLbHJsCswLnKPLuwo05tuwzHlHfGm4kEj9hewYiC8KCBa/RN2HZl
lLiqxjCh6mMSKBVMoCIoWmowLJFEoO5cQsxH9Rfb4/YCg4vC/PJv3kaTz9meVRh9GUpIuGVvbyYB
WlIEVe0oQFr1uCznYq6wwbzSvNTg/Ni9tojcZo5RHnCJk5udcKR69jHJlt54BaxeN286+aLw5a7k
Pdx1vmBnPoemSnXNbKvN1I3P8QgsQ7wklSo6Ge2Rte3iSZGcEHxGc9TvHKkK+F+vT9l7/j/eK3Vh
EjPI63zbksCAHYm/bx9370CanxSWwQnfAxZQKaIAs/xDWChz0MniKa107m/oYSh6ehQ5SwExLdE6
HeznG6CbfdbwmeHfcXGMXYpF7jlFhCPHD0H/tWi3ELy7wnj84UdV6DWkITurUQE4cyh+PaEfjU43
qWpQAvwKKModbTEG7+44TckTGhdfjlJmq5R8hHOKTDoyNOdb9Xa4vavZzxOFPjftVjQNi51USe3o
j5K9bJsmb6DV9D9OXJTydbEuuNqI7zCGXHHezWuBtcWI4OKw34yMdEhOBMm6vN4biqG361SYtdNL
5QWZ6Vfj73J/1fz0Vlpmtayqv7CI0IB1UoEuSaOst3AFDC+aCRkqMZFmWHiOJv/9T5KFroxHwW2w
seBd0rsV1dz7mWxC4jqQ52o+UZIcGbZtqSVP2vIIqWHBivxvyqBOpvMHX/YGNot7mwNPVYsLHZ72
0L1fq8Pu/NWg5X1Yrje27EfTYNgeQmMyUCpenhKUG8PB4Go+S8lbmMAFrB0p9XVlmjlM7yBY2/ns
u0Qe1Q3RnsARQsc1yFvZNnLb4k3R0NEFeo10a4Lh3lEcMeHGSwPvOxiyHb57BeURWcIzOnzkXs5j
lYbKT/U+qJu55J9srZ/Fb1HfYnyME2o+Dsubhwxut9CU66ejetfDJ970xVnHIX0H4B8b46toxCUM
HsO/KFQ+MQoBp+s+DJFrkpr6WZtmeQwdF3nLiZ1EkrxCUakwQms9Xd5X4+ONkxEw3WLszT+A10PE
WObzZtU9QOzMfTgJhKnrl06XozoM0VjA5ZkQWcWYxHlUDIPVzvuHZL0Iubpr51uyX7Fjgb58mO9G
NSPNuQNYbaRQotPcDvC+jjpgY1g1P6xhlruiD+rsBfc5U3hb9gh/robOOQ7tJMW4NMNldMe87qny
glXg5UbRPsMbjyTUSfQWnv4ArOhmmzogfXsDXmMNMHJvMW27/JWXCYdYXhtOmmPQqpjTLRqeU8x3
FIWKB7rjKylyxfmPtu6Dih9tcs2kbqzyIOYui0J1N+RAqBgprST5tXsGPUY0z0CjKZ8H2YWzFRWV
ILYUO2Mr1JAjwPNq9jBGRAoHMOUsem3Xr0kqUWqKVrTVfz9vElLz/i97+vAS4xPEU9cqoUf+UcS0
iEMCCZnBRiYZ5GXOZoOlGOp3Dt8SLz3UKThD2LGtIRtnv+R/Tt0R/4F/3UhaVnZxEe+ELbqIQYbn
Su87EWYRy8pCrWSAD80e+SGQ2TxY/zAp0MpGw2DeflBTpX9rxJkpnV62AvtreA/c98768LplksAJ
vyl3GGlb5BiDi7lLd3poRyB+F6+OryR+x02sO94lKEvsaYidpgBRE/leYXqlsj89UBmEmvWz5tYg
uRGjVBgtF93KQRGrUOff7IpOTFHeoN/iu8LAmqcr8lg2YLBSRB+4QiyshMCo+fMeMa7OkNBw79bM
bMt6e2yH0VPxEQutOheqlFcWkNQfvB0U54bBelj/3Fuc5Nr6a76QP2JPXIvSWSugQ65sRpwL15u9
RjZSl2tglSdrakI34j/YP/uTCgp89PoG4P7SQefmOojQPckndEGOkP/qeRRVbQ90uS46yWH/hGCT
5yjmri1L4kltV1arOcIi7ng6mgm87qzwxmihzLzZJLR8lTfw+QXgR/g6lpxIlC33uIhcqKMHHP41
t5CerosRahXlcy70zwOZbne6nSBBXoLJsoOc8i33I1tAet0qdqKD/N3S1wKKdtff9U+awcXDGOKZ
xo+ol21FG/0hR22PYBAwCnuYzJd5C1g4eCElHbsngGPuzuAWfM8SK5iGjTmZao2hmWLLem+Il9Pz
u8m7YOwPkSmUUbItV7yX6b0VOOWl/muErUI9Kbm1pW9dG2e7JsKbTKC+Wk6Mg+c3fOrlFcirjMmy
Ro/4Zy4rKcCMuG9tEJ6VOZ+9DAzvNPuOWFgLceVHJpCb5xNZThpRcJ8MXt/141OHQeQZO+cP4Lvj
oisWzS9Ag5TPoIa1JtCTkC7dJLYNx+RNRF/iD+PJvYd5jch64vwR6BPu4lNxBKbAnkOojinOxaPn
lHHph575prDY4tBTTwfYYfNEM2ob8OBtuxKzw7RrZLKnCME/3C0LHzKYipe/YLeZPuCIjfAn/V33
rnxSNynWIvMxFN6DcfPmjOH4Lh/E+xirbvWF6hrGL3Oj8VwB8Aw7gp8WqdZZw5bU4MCj/VLnYN+r
xFBbtAjAApvPMQpLjRiRyuj/l8cJ9OKkjLgqg6JXrAXZY4jgkaR61PIYHiDYLMyup2DAQGS3ffKq
8nFP4jSjzMjc0wSuBR6wY8x9FySOwY+sCOUJbGRiFE/RDLDKV7npF9vuExd2P/mnfnof7pw8959e
cVkJSaf/Kbf40w31ReanEkScyMw5rn960OQwAp/qFjicEQoy8CQp+syOo/kkh1qMRYN9UpCMDpXt
65bg30RPZTthOT2WsDGJPzMg803YvOTgKdtEZSOEGeM3fWUPhBrMiGz72NtA6f2W7aZ/3lLLQ0Ey
3Y+I9T2SOog6OUgzSF22PVzg/BCEhwudtWf458kgBSyJt9i0O5rGW+Got1v0TFz66rz5PR+flep3
Cxq/3k39zAKTJ1YHuL29kh5W32yGljL9VLh0exXs1eEIm1mul6+zEUzpsgtHjC3BpiDNKWU7YaaG
06nhVg4K4QN2QdVFpzo2MxAJm/3flfV71+cuEQzUJ6/Inqdbd6aZSp4N7rzVdOT5M2vYglHi9V6K
0EdZrA0+nWbq29diECITzbocDnEYYD/6YaNSCgFD/MZVVGkxizMCw1UoDsMueEsLS2iKCKhhA13m
lZ1czCLfdClDOMPL8ZhoWbfEjiEVLQuj+bwAnd2N5gDPz0kK+L+ZmgCrhhv17uNdYh+iBoaS/faG
imx/T7Q3OTvRIeuVcO+/vrA0itQZjT22ozIse5oPxjnno+l1y+rCNyvoPQyOGV3xjerRy1xBBIcv
84yB4crh/F9ksF0O3fdvJqg68WaWKOQfczm1ggwAejzD1CqWTtho7RzqkkFmxBc8rJDS7UHPINcv
RjolRTetClMI3JObwhC4txI7UwxFeS/PQhsPHANwkcyrxLkA+f9WEIvjgjXuXjKpics7HYMhsShX
UBJ9xgXlfbile05w9FkvcITovSxAvQ6nFeDM9Seb0+9LT2fZv7alenKP36VLEUosejMMWde9LObH
56IoqY8yIxcV8sUrF5im+ZML2bIkG3I956qSRJdKVuSInhm58EZpt73cH00nmE6JMnriGAeIZqGM
a+CHkxDwBAZBEr+rg50micgM5GSTL8NKjRwHVYsX7PQr77ieucmlQMZWp+cPdqCQd1HA9jW1NwK2
QxZfEFrKeNMP5imxG9Y9qYVkxafOc64wTDenNnGfxccHNSUh4UryyL8akf5bbgHzEJoaXBa21xxZ
mx51c2p5eyRkFyo/95RDyKq3DmR9UpgfWzyO679bzAoeOuoMnfF5T5kwG9xwLrL4BtEaocf0Lv4j
XplSEQNd27xKb7qprwFMcKsJm69oWWLw6jchU4luRb89R8a2fyAuorzcaO7Irgtnxc8Ugw61IzCJ
xGcXF0YnpN/ostYTWbv8z20x2CMyW5sPxYK5WBRq2WQLDFk9YhOOMlgV20bowjntB5Ijry4RAeRy
B6O7io+43quPdcVPBBQuZJpPi5Z8NBlm6HvDZ4bH0XcTndMNW20kSb0bZrlHK78gs7UAKnOevCSy
+3hKYZZUcyl16VignBy26ZZSRHUYxAeuFE9PdFt5t7pJSu9gAlLQcjeQMaPvH1D7yBsXB3BHmQ2i
F5AOph+ddirFzL1pGTK9zWDlCu2VKBuLoUhvL/S6olaoXpZ7yNg0WpLufFZu20YnbhPDXs/jz2xU
quxoI5TtJJL3sxYwB4Qh+RSfSSAZst9OArvhGcqYhBkZGVqVn3Fh8MmNRh5X13iiSN9I6CQJ3JuV
umeoiZ6oz3y3nmd2ezxR2sbQSMVxGMCZyTXtemlwGqE+8Uia0TiaHqFf17bXckV47Drr+hlY4ZQ6
1eiFj7eJ2yt0feLm9gBnvHeA2x2S8plXswCcQrPQU8GgtOpsgcYp+Bcdma9zJKILpIdtLtgQTieM
A5KGNNRwBrruBaS+4QYyrrBvzYj7Kxjvyo57/9cNdUyXjMTOIEs/OQ/pP7DtitchSzF1+XhMC4v8
umNw5AsZLaGR9nSwf++2zl6wFMiFcDUrgfQNs00hK8QNAufzLioGIVplmI+h0g8gHttRN7kDBY5c
UAMbpn70SXyIHrT76O75aJSOmLKZywy7g/LlZ1wUaPEjNmYcuzcWWdy0L0tIcTeNpDQXEAi7VAfL
gMdhlk3P+xrlprhyk26EhMuoeRnti4qz34LczfW55WLRHRZLx+CN/XL9j8S3h0+m7S8zfE+Z2KnF
Ff2bUZNfa+5Zn92+DlDzmWEqq8ZTJxVDBbruuCGhxhBjgW2TbedGtSexE2U8OaMORBoIlGPZ2z/u
4dO2LTDJRUxXs8eM+Mxwi3R72JxRBGvwPbmF+MbBugG9ptAEpf2moE49EHEn1s69wY/MizEviQMJ
kJW6tDv6eWMbwXTH0TOEHI80ojSn4+DNv4RDbYRgGAOZJR52U9WTcyhlwIyvTY3eerPVadUKLiRB
naHvAEcMVP1HEJ1iBOzZARP4s3OBxFUL5gOU9q6e3lMjeWrGpC6gYMAnZgr0sX+XfLEhWPVymLOj
NURVlFWOd+q6HLBcRCR33JutBuBDjM+dR/Od00AgrM1VtFoPywF6VqwcCOmIdy8jB1TRuW/wNUWN
R8cl+8a6k38ZcUJqAdFppkdiejAAt83qe6RRxDykJYfS1h4XrLreymx1Ob4n6E4BCp8xLBOkEWro
eD32gFW0t2Qft4R2q1MSxKZByNxPz5CnBNufImBm5KR05l8rEpUGZQ81USkAvG1IOCBtdxajvqzB
PT9443vPomEDBCNTaPzXBHo+Zsrm05rb8bJavIpVF/pD2GOh2Lgd+ehdjTSicfmgT7XMccXNBFwY
hgmo4ykCE1S3+o+fRtiuimfbDIDAFZPwplGOkD+h5UQ3mZotVPK9hhWUwAgUFj3VlJk34apoTE9s
e57e4e7PqqQMnhlP8yc+FYPsf5M3rvUKRHbk0jBN08Br+nNsAfv1/5kkBw5GA5eZ0wGuAzDykKus
COcIvfTv1QMza+qlX04GollavVsJLJmjpzIsAhzPqtmyUr8NFsLKeJqlQLd3sVRnytvbdARgH1r4
qm3ZwKBQ11kQBdYUHO37e248kPo8ZwjvugqKqNJopXHPYzgDdxRgJUKIXnush81DiHkvdVDfylEN
5hHIg/LF6mC2IpRnUMjZcae6lbjNvhpxY4o6reVucVvf6u8+fiuW+Jx6RieEb2V4QJ+dWzvXWAUT
CztXHbtfEbvOS1T2myuroiKE8hXqQjJ9fA0vQQBRHTy4UY6yzj0xmX5zZvLUEDUkbvSX6piCTQBN
vTgex2n2kwk2XiXtxDsTXt+fpn1dFGBFIF7ZB9oZPHM1STVVcGVlegPd5fOvvTuvC27JVBXTs47J
HVhzL3klStG4THMR10HithIk5wgwRogkbGkqAv2iHS8a5od7wrbGEBVX4e84NmCbcLDLC3NMvur2
bCVQjV1a/X6HKuSWbCOmn/Wbs0B6Y2u7NDN57u8f/mYEHkkV9CjpTcwhhc/BOqVStGizo6Xcczml
qZLmvANA/e4erGC+ujxV49J/LSz3PaxzB4jaSRETSc9WzFIUdYvb6z6/ofr2Hto6qyXluoy1Rml/
AXhpR31wUpjE7mfE5rxDX+RaxQnsHPUlKSjAa/0Q2hL1c0MAbvUDknKPEMZlsCpjbsu/vMoRXYYG
BExRJcGD8DZN049v9aBEHr2vFb1exPWhhGTNs9iDpFXMi1lq8VEalUG87tis9RTbTxPIUrndI6/B
FuiA+XZ811qyQor6Dt5eKXB16qRhkMMuXJncl6aFFi5yiYGqiTOm2uApoU09cIZakf0jOwCvsMz4
VFMbbBgUUhK9Vv6tn37pe2lOvhFOv1zbyWEH0PVtG3h6qeddtohxmlZzMvny+2kf2v3N314grdnC
Uy/WO9ZKwXVOi1Lt/Nm4lXFPhaITEtS/JWbikDfjd7OkD5EXlkhY3WTAFtzTRAT/LLrQEY88MAsg
jAK6B5OxQkFstMQ5yHBGYuVtDZ/5P5lMqN/rWRDD2irh0jvPQ4FevGAwMyM6GXGwCjLkzQ87+3st
3iVDt3gau7TJOpY9sjbEqe65fLubPdJv8+chHyyTXcElCvtDuh9o1ZtXdOR3IYqWqgt/5JK6I4/M
Q6BNNHXZtqkgHHdhlKJgwvaLt/n3V78ttnHLLrh5LXeFXzz65GgGqgSNLx0JWxZfhAWS3FbnOVbd
dMXudQ+sqNxp+2YwxASR2On4T1htK9GUW55G5fDBOebsEuBQiO4LyPRjS3TNEVLXkUiZqyiowKcb
O6MLqZ8bzjTFJt5DdIwdDfubaTQqFe+PEcaSVbpvJhsmzXSIARmUYDp/OYWYUaSrzA6u1kkyySLr
oDzE2uaPYuQ4VrlK4UdqDqcpieg0pni9aRkhjmZ7fw8CRHQL1nF9M4E8614xte8cCp0SdrvlDHsa
fsZ5dlZS9snxUCo18x3y3gTTAz96e2pPv6kaqMkVLSR/VjUWUY1aWtljppz5YVZ5NdevAHkEv2oV
+oyFobLpQudxM8GuQA17AnV4k5Xm3+3MsSnTtG2psVrU8s4btq77zi5hBxgUlxlkTsOLzbQ+gcEF
ZPxL7RhdbVjePLNpuZHQgDXMP0i3+jmSAp9WTW/nPStFKdQ1fnEmtei70jVw72xG3f0DthzZ1L0Y
EeLiIFrduNLJqaGmgNrui1nDb2QLbge+y7Cw/GXaOD1vt+BUxx9Koj3J6IshUYiCwOme7XBp/Ka7
Id6nnjJ1g5Q6fsxrbF6EEImn1hlh4AoHVnjjAvDKl/1erbfQvX+J+JaztecGhVTR4yoquokYvi8U
Kk+O0vc6HsonGFHg0BDVzBaGsmG7jI7FIiHdl1vT9GJycfBWygNiF1lqJYIBPZ4dSeP2ohSFQPtW
+8c2Qa23zTj5qGBzGjMZzfV5IhlnPL+ehTXJUfP0AmOX0AM25vuhl9jUWiiBtELXMeJ0tbtIABen
kKdgNJHU7u8By9kQYQ2vVdLLF1TSn2cZh//IPLWYKsIK9d0fYsxj2y+YeDqNFGB0poicQYGhM2KH
iOVQCUGiIt9pzNbOXyyWs43g/vo5q0S0uPUCOBkwqsrBPZ+Bxs0D23WHRqyjVKn6YdyKDSvn/lCv
Pn1Fm/GKssR9nqTsV8TruRD4OBgQTRor+Gy4WFaUooAtd6PsEB28gyxsZLpMtzvxygozqyv3VXjI
dfkDfvMb78YTpkuZQrtPpw/69UtzsYlJ93+/QuDaFYCQh1QzWqz/L+PFy1gmULU5rZMb54/stfyQ
dzF2VZaS735vOpfNYCjcYFAkIKq+O7mwhgk3y6NQMmsjXXeUVuV+LU+VGAFzFSGQizm3i5CPOJJN
3dJ7JemAAnjHcACwYRDMOTH8GpcQhZCO5/+YTMQrr26B9GGpOz6TqUlw/lRjE0pkK/H5zLRRcDm/
UplNoEFF8ZMYBuwPTrfUlFTeP4LsaCPwP9yJ6zibGztYRhSU9TkAObVrVZsMd+Oj5eikHbSUm6Sh
03XDroB5DDE5Ga+HU4Mr+RCjVcXUsHjx8Dr6/iWvhfNPwc6lj8//JaOoxjmXvOE69Y1OXi3RVEe5
YTZDFbPmQdVG3nk9sLTsCMv0iMHB/zwfiue6mz41jUObJ+zMRWkMYfcoFg76i7403CDKWo5r+U7l
YbXjNVmGK5ZiJKzD7P2A28c6xaWnz2MO6o7xObVb5rg0FeE4uPW0XZc+q/LPCK6NH0FDloTENKqN
CmAttjY3H1O1KKkJS7bIwAdQ93tjTdlYhT6JpH1EVM1YQL5ZBpSAcIenHQNj+fLS5by9JKaNZVNf
MecllFQC7cBfTccjUXshvaBnekCxOplzV8ckaI7Q/aqagUc/L7V79hEbDE4abRLRLHBLcSc+8og5
sKtLqeNn3u7XZi4tiME8VGyOLC9X0Z+iXpNy7fYIZeRDJS9CMGgbmWoVNa4JYOHHHqPyF5oA6jKU
1qxa+1PSe+2zFgj3wGpgZe00lFd6n31SELoHMTIork7cKGQtMcIADL9Jj2TbJbl96NIiLWSWgXUG
PhwxpB7G7DYLfXbn23AHLuHp6oErJBK0Xlc4R4nF4jPuX9a4bOzWmZuiQF37WjIhPQzjoFaTUZ53
96sLN9+jXCD1Q/sRPPzTH4h2G/lpEaBZ7IMTNVyjlh8cHoa6IBGNYfB439JZ/FIqnC9tfidkNE77
XHVC7z5+b0pkwhXZ36jE3wGTubbbWck4bltIIXTLRCoNfgKAngj1ajM6UTknBSlHNCPViPLhNGE+
TTCJowfi49JJDtelkmaEhzA3eQNfVzzm/qBdFn58NYYHx8QdK2hBAr6b/2nE5I6E/o2G7wrbghKk
Kj9F9A+BK67jEaDQfmCIv+EZ/istkal1M+kVQ/Jy/FHwMD8I/Q5CrDMRd9gcpYWB5Cs/wc3Ubn3Z
E8/FpjkwZe82CWrlUZEpPaqGkHAUQNj5OV3xD1rluGxyRwT0SJnRcXrZYK29/cO36c1u9gRAwCQy
k9Sa6ag0jNL0O3KH/XP/I3osPhLtOGEtgajOmcMRnrzz4YltizYu7wFjWnXm1GUtq6vv6s9/F4W7
ryMvHxs11/zg2V3FAMObYRm2SFNyFnSBwbhrhyg6AbpJq56RNMpkvenoWb5vQgEV2CAHxBuGeJcw
zidCbKQuRwprPuydkZmr5MY9J8ikSYsVEEFq/e8fQRolF6/N45W3GKVJHVkPlIQJJ2IAfrL7HlZq
74IWsao0Bfx1Fb/GuZnZbYyjXZXQk/DOOUT9ClTUlBtWjX4c4l7PVx8iYt7H+YODhuQzakdwsDqK
XSXV2/0+0gtqOrH/efFIFCvx8QLvzbR322heb8uG1TtUxHbgYxvJmMuxTY0Kt+Ck6jZjzGvNE2Iq
gvjpdhAsiAjihLWF4V16bJcDPyqTIruL5dAh6LMq7BR5jWFCuLEK27qS2HbmowhRK2eAiors8K18
t5/yB89hVJiK1VAnmjQP7VUJaTwv0JXIIt5f+egDAT6sMWy4LiX+UnV7wfzwqzCOWcgEjXF/Jecv
kLKaG1HrpF8N4YNegCv1jvLCFqLR37lk6Czxz6YIAP+Sn9HJB00wh2ZVv9NBI9ehaDw5glvVirla
UImOu55H5c6oo9JyHfADjr6Twa57lo6X3mAid5ay7CW+U+GbL2Ks/hvZb/P2bOLx/6jx8EAXxqBu
aEzyxmHnCbktHY5Z8rVvZi2Epj+mk/1sT82OlWtBNB0JEYqCkiiFCTLNcpFJbRTm4hJLLf527uMx
YF8v/kMEdGR4YUj496sNH1jf1kVCa/igONjA9+rQdfbOLicvBvj/m9IoRzgVGiARsL6aTsTYjUbz
iiw5louYy1/C/f+x6fEZ2FkRnzeFt9JWO0e7wlS9jVa6x3gmnmdWEc8MPiNsj4tqK4Er3uU/145B
MvYV5qpfI2SX6Zp+U5qD60aL3pFodgdyU/WmKgK4OGyXJ/AMQ902VyZIjom1/4DalmSz/vWisjbK
IuuLNtmcpjfccnQ1iGElM8l/e8X0t1wz630YBvbcwsldEDcGoX6uPcrAzjO9EEkRzguohgomTJz0
QX/F6gdCbCI+mq0nZgt2a5+Ud9YaKMQte20zaZ71eYiDUqynHh2LgeZmlVtkMWW+XMAivdRcoI/o
0kzwubQf8QkOqdv4U0XlP1cvxeRwlb/BUWsw3tOFNcw5KVYxjBJ02CxJvInKtVkmWKTnf2jDK52x
ysNQrZNGKXShEhrSBQzNGNmNEf7IzfTwTqQ22RI05Ad2fbs4tJ8to28hGG84XxWnO3zl3nNvUh5k
j5+5GB1f9eYY01119MgMAripViorZJK70iqqxy/yjWNngZUMLpCH6nD3f9s9b97VelXy5w/LIRuH
DcDrqzQEIKmLa87TRvUZ6k8HCTOompbHk5128e5AlIpEp0qOhglE9+Zd2m5hFGqQlAGpLrl36CiS
qbHzF/1TcnhQooR54VeoG+aVbbpB7feXRGLyra33nq2aoCmqAAIhyYuPYBSCQAFO1myn2O5129Yy
HSu1CqA6k70D18ZL7B73W68Q7FO41GLtmkiXGzM7SnSyxr7WwhFziBITYWesF2tWN3emTU2BTRqM
9hteLIPwILybEFRwk4/2l0HEWex556xXjM0I+acBVsiZ6zCLAJ/uG26QwtLfMTh2Ij0meyT121SU
q3PMGfhtfbm92EwUiHNqLCl2VQzPEojFR+GirZUfoPdyslYQCW6BSW6bSgs+FkmY+C4Rn6oQndcx
XnP7R66UOwy2EIj2/lVwmlTXeSgJWScUOi76RsekR3d74PRRh4TO00d8MUXFpM+3aS5Y/H+xDMW7
B8tPaIcyxlTPeKHt246lFvHrwPRXk/VPyNFoflVdbosuNHbumgsK2uPl/naJbtXdjq9SYQ1kGZRu
x+e4Q3iwaIemdfOlVF78QQdTb8lg6pd1AoAZQdeWWmBvV82zGwy12YyW3CDnmU8mEqtH0Ba6HVfq
1sOFH040882Iifqr3F9u/X28Xo1bjSCR8pCmo0GDO+I086Vw/W4BmUx57Olm0adXgDQmYj8ssbb4
tlYRknOLFr8b/kzZSSvFV9bPVs0WTetnJ2ePs3dWkc63i2WBI7izE8K3xRfvkPRFyVM4eXJoRQM2
voqgJLdaflRl4ZEJ1TAXY7Qac51nS5VmwKX8wwGnFQ/z8xVkMkpzFM7RF/TwtLkswZXN4uVQYpRA
Pf/4naVasI1hmKBRPApTupGmE9pVttC7oPaZ/q6qMUHskZYJrJy+8DW0FdcJYsSFsgFu5wwVH08J
0dCzKJw9sTG7Dqwkb/i63I7PNme0/oK5r2WihsP+GayLBAmTV7x32h0woMQj6U2qVqMz+BlX5J8N
FTpY1Jw+T4e+xVKcTT+zGfAmNZR0skpouU38ejdKAWbfR53u09Kb/CK1B9vcjtNYWhkB86lkaS07
98UdQ3W9h3rfZCWlD3GViYedfKRp+mn/Tg0onkwplRj2HgYJPKD70pqJVMs+FE63PCTTaPPkKrBq
OvjkAxBcKRpwYIgLv3SRHLwRTXEZ9tPtfVTF4WbD0fHs407uqIjKqAiBPVXlFrstu2ML/WEJRh9y
2++umUVn9M5rgrer+9xcqrcJkIHsOH21eRK90eCoZhl2g2QL/uCQU3MeijkqseCT//XhQieBEmor
5dQBXR7PqO7ibckFaoMPU4J5uxlPhFEsb4ZR30lTdl2xBsRpSIDPBghPb4a0PM4dVXTxSVOTe/3O
NdsNTc3O49EUP8Uy3bqQbf1uDgZksuqih0pr/EvDoT9sQPFy0tb7UQooW79pP3PXt3BtGowMmtlS
3rCpvGzfCZLSJf1Kd4kesXbD/vVhuVXdyghshfA4AzdNA0JEWkamEo8K0V2nGhcY7sZ6iisbsD0v
C7YC/x67E3JqKEAsTBhOrA6DnA6mzYgKsaS0d9EyOK35SZQDf95OruDG6HK/sLo8VS8LYr+77BBO
pH6E22tWKju4qvF65bJc3eXf3k/eLudY3eWK58QaRkXO+2tpR7W7IrUZKpOBmPqakWPTvSgNtyqR
3aaWy5/sOYlUUH4noSOZln01p+A+D+Gl2/z3OscseEcrqXSIPzXAdG9b+Zu9y9zJbJcSuWeWSCYY
4PKOdX2vpLojWVCCs3fPAdqg7Bwfjb6CsVnVMiSVLYJPvyupNMExs+d1bYBYsgraqTH59bRL2jTY
kwmsQ7azj/TGKIsCUtDZLTCCl0rGxYvJbreRO2K/cWYywLLTAtasVTM/ZUE2VriKw9NoPc3pL+8c
CzRL/W+0GUgs0nuapsbW66/RdMDMcHbaeI2ntMIm2+0piwoTf/FRWApRvZJxizp0cso9tzVilbQr
8Hsbqml31RpiiLLuLeJF3Wz4a2IaybWuVXIpUfgOj0F38tlcfj/VOPi4eFttncKetNbO7fL+84id
yn+pRiOuEp9qkzpPycQXUoRrwVj/NFR89kbzf73zNONfIjmwmCUEjMdt6Ds0RgLrnUjAL8vSm8lU
hsjtIxGT8SNZme6hlGKSztsLEmS9Y1JbNOpHRA7cAVcU0BquidEqO76GPaIsP/F830KKLHJOovf0
GypzdmVXOaqdDixhiECboCXTuxFRXNB0beAGIKWPScI8/QIZYy3FDTloS+O+va+KXgCtGwFoFlEn
dt5RrIdF6B2IUpDyIWexqlWFN6IqUKuIAHa0wWV090uXFLrV/D54XPXt39KdJVfpEJo1ooXqBev+
My8HUm53Bg8qXQdQTKE9Xq65W5KjayAMF55Q4yzfmjS7ooB1dkFrDapC/OV8q/kJjc/vHEX0rQKz
b85RE3mFdbjrJwphQxHg2ClietY+EN2FeANip1iXqYrdurJmKXTcj1Q83VUxjCSZpae5vA6vHgQr
bX0c3MvfV5MIzC7oBedBxnHVSxW3xkwn8dk1R68pEgB0yTkjrMvAFSX62MbqvFLtdChGEJq5Upa/
K5Y98TmjNbUie5zBV/Dk7XyAmRBkl8hjVebIx9GuLspiHdpERPMc509LlNVuFXkTEbvcupVaPgUL
vew1IBBegOSdj6Y30HskKRGqGRzN+IQz+bp4GN6wnLTHCbtK3MMXcD+A8AaeYY6bWiPUWVwefjAM
6zVKZ5JOqDrwjALbBAmiv9/JYI6IqlT3eedSJgFNvStSWuorZVE2hbSNJ9SQqDgbawU6r+J0/4r/
+q0SvaPbULGMjOHwY9nmniplbjw1x+tqC01oCbwAqO13R9XoacZLUd+U/D5PlOkA8jF90x1jw5SB
JN6dgnx4Vbg9aZRGcZHrtrdwCHFo9gxlVkZ7ydeihubxj7g6L5twSqGYpP5X61Q7H8dvBuSRGxLw
CljJJGvX1iQ6uDbKgUu1gTmUi527sKAevvShjN7P+QxT7wVb4zSFWTTBtiCDsHRbX/VIZ9ApMG5c
agcte41L9o85Frwm0aFRvd+8WaEb3QYa4BcU2o72yFuBReaekzStftoXOMLE5yBTwRKdNssGZOQV
Fx6bpnuaqe3q5MWFhYW2IOTZu6RApuD58lFkysscEUWmAhIJlFSw3WrvRER6cWaqBDCXyXhU7GjC
RPbu1i+9vlAyK4Alebm0Bv16GZ6Ev379C9AY94WHU3KQVpGN+bkwTzDy0ju3uKeH4HDf5Zuqq9N1
4LOpn87LoD2VGaRbE0bK4G9tFdC00xmSvLegad7pc/sx8gqyXnJdFsfGcRcO7000tYXwio+M4dMi
6y1T35QcAYvz1RTf+NXlU3abXStAsK9Jz+yQ4V/Z3YZSf+IStVfF4uh1fD5zU/pnGQYmCkQhJ+6/
Haw5gsVzfC5cesRHhVMhAJTuJ33dFkfdBuVJKgTXtt4GIHvtM7xZdYEHceuwW/KNR6VEv7BKoRrU
AD54NtYug1RxwpVscb73EgnTQ6SHcME+eaEdXe4Q6HJKORSgVrqViHQamqZqkNRPaFbmUH8tw/7/
GjlJNQEzmj8GCaYRde4ayGkk96xiv+Mju098KBP+zqT0QyLrbq6SiCJTT6+ygdl2u7SxeKMpSWub
Ct1Sm1GUtdfh7qCkgTvmUUZLQh49NuhKaOy1GIkuaSLlkPTa8rZPxz8nqwFGFqjYyrR5jpHbeZxI
IsaZV4HlU/2wLP6iyTbAL5y34q1ufi78U+Cg6KuK40rlXRK9kJr5kCUcU4/Gr0bME1yEqyMcZjeW
i5PMvQDRjye/9SIQQDWtWjjOS/GaOKlL6HuwWz3weN6ShFvsqfRU153qaHSS2h8aFh37qisIF5mC
nY89Gr+u+ljasK2fRxMh8dGu6GwJG/wDf5aE+Kjg79SouXF1jaoDWlxZgD+mwa500sv6bvXFbdil
y8oo/lFpU4rz9O2CtmZaFbO+RGNTUMyEUTvJ2BTONTG7TSlJvl1ytmn38e2ubW8Kj1JSR101yzZJ
fbGJmYAsz3KIt/CY2habpm9A9sz4bO08ILQZXIyKaXzgyB7W/d84Ue+TJmfepweJH3oO5DqV/mbv
xBEg3tbiBJfiZMFrnoir78Rdv5Js6BU5vqsPzrKTI383HzUQ4JA45ewXKyth4GQpKkprxeU/B80w
lFYeguRpdCR9aOHEzBY6LFfXo7PAWXRRsmIAnja0HAsdOmszNlorgBxyxMdnPhN/510sEzJ7Cd+8
JM96NP2W1mYv2lI6oCm2qn4rhp7tOsWWJE/EDrvBvgjGoAyJs0fFknPNj1pUVAhBClUbwS4Qs3qL
sUA4vBNhiAPFKbw5R/klM3j/GHlfo5t2q/rsmUavX2B/stY7KMyQtUmmrroJTgfUx9TrDgSLnNpb
e03Dw8Ho3tzSL1TozAxz3+6DuqNgCZ/xaPC+lO3uWuGmJtrnoxyqEU+TDqu9Ws+P8MUmF33MIA3G
1+RR4k+6ksUAuSrygUQIfUjQx8s8qOdyn5yz0tD9h2tlf3mk1te6Od1C1cLorJyTK1fY9MthJ0t/
oDs37WnQIDGPQfBMnduiyq4ZM9slbfOHzGesNJVVlphbGze23IAL4itwA3nYZrvVft5xmQmwcPzV
7D8qlZUPSLUgD++HDXYw8eT7QKt4lsb6tLkdzb9iNSgrvwl8Hp3LNyQaDslBe/w4PhybDKw1b116
+0jl5+eG2RKdAlq/gc5apKFBrxeN+vxe3fgzTVDTGNQJ+vCevofMRKPczeEyx8J8IZaWBFFN8DSK
7iUkga9cHiRnffHyyAowZ2/wsskZnpyiXsEt2ch8OxsIwrHEscTGLMiL7HAGtTPWgyYlx5hSPhLW
kSFZfMlfOJmsXhqVIOD7QM3zASXEJ5ngM4YDbLRm9oZ/6XTQOSEfMfEFSExmqPUQVP78SX/1wY3Q
l8xxyqsa/YndrROHsFtZqhlMkRJe2GaX1DcO/rdouJsOy1r/+V5NpISM4gZVwaT/448DbmWanBMH
sOekVP2RgkCxuRZp4r0w9uxMpUX9PKHsJe5JqUPuXS5NLBGhjnDBbooFekGgVltoaz3QZ1RNxL+/
y7codRas0VH4qPg3t6FNj1a9rapR6wZLfEjaqYlJ67aqLXWWSA3cxUQZwB3s8Z3ylnpnhtPlYcEt
IQM5A9gfXPhz+ap6pgwPb3KcgzFMXyA5iFZB/D240yxvrvlD4lHA/eyYaTtp4bb+4Z+0cVi7Fy2c
VccrfB73+clM3w5B+TJ5nDEbZ40CJn85EKi6FjVF27qWcELvaCBaIjGKwerN/k6SM7veRA/ErNRv
NJGBPnFjCG+M26AMNc+gzFHM2zrcy3vA+4H+x+xZc2YJVXO+WzZLKoC9+K1wMSCgMXeum45NgogW
Ir0OUo8m2rUJPgG0584Sz+lFSOWDKDEg5XCQKxfkhJvkCUWAiYoHrzrpkDFXjTgALCR2ORmRKGFP
5KwdagljXRtt64iPfAWq/U6cJHfHa8KpkTu5f7vGdsixIMC9TxhHbnQ/C/u6G3u26cZ1h4VjfV+5
dqLrfN/zeKVQbOMt8u6OngF+jZb1TI9NqZMR0/a2Pr/s4qUVvYRw6Hoxrl5BS0yqX2bQZT9iaX3F
nqBjv8IRGJjcTAkv83QJyPYqMhDN4vxkUSelB7rYCF1ycklAl45mNhUSNhYOobeqwT5eJiGS8EbQ
6nIvyPIaOoKydryA0INqDqG7g2VhZIEmEoEwikjZK7w7xuSr/aRgb/8pgRPFxKWUhZ56GJCWrKme
/wPgbIPQFf+fETSgaWfJEWUoCUrGwppuepLd7EPg6QW2L63mNjBSgSOyEPngKIc42tBjEOOWTw7S
6HvDVcYfS5/v4eh43602EZj2DPDK2Aj1h+VW7KIK2LwPPA1ZoIUFhxcAz08V9jSjMcIt/U9oBlX+
JQXIBxMxfY6vjbrEJF1s9AruuNHIxHLX1JyJjlMoGD2q9+Iye4uDNOD0ZHl170UQxYC2mb5eGWCB
vSLS4fhDISEZDpwqcrn7oQiYsvTjdZmUqDyAT+fwhfdCZPgbRDShGTzcWlWSC+TTSYwPQA4z83Bm
Z8oLUlOBmSuHwN/hGX3+E1qqqNMfl+xIO0PoaqCRN1nbYreolEEUgRqdSle82nlN6kiXXiPRwjW+
Ulme3UX8fpAMiUf9hoNKp4sUxuEx6fHlzCGl46DYbB+6Nd7AxZyL9FqYx0KdBhWYcV5YPCHUO2AB
Hb6qtf3QgTPfTkPHPZZTjfvsZprPizYSXob1PRHvAhxlQ3I+xCMnP3qmNrUmutPtwKL7QauaWsUd
pI3wwSOmB/IQvszfvAxU28vB2Zza6CasfHzGZ87yWSnzvNt/TPW+a2JNBhxsi8xnrgXGkTZfMsuE
mvWckI6GTKSS6nX0t5RNpZ5wJvoOK8yvbwK+5c8Gp8AKV8QCzeWCjDf/Yq2v8y/rIsjp5k8UA/n0
7JZS+Aj0K1EyjAh5Cef0UCtcQb/NsSezHMXIliRRg64OJN+quBIUmrtPzOkh/aca4AVig0pfwCeA
qXAUMz7W6LLPEG7D4A44vZdjkPoJDMZrEF3ETgUqluBHxhnNvMW2qg75hPosFuDs++yXlcu6Ya9l
OG1grrLt/z4oyyXyQkCcAWJqGtLJTotxVD91KPUdqQu/B31q/73j8K230odVBm+DN54uqDq/5z+k
snIKW8QQ+qx2xp9r8LfudSItk9linEIulf/FsfK4lQok4/C6MRPOKkkZAwhRoleP8gDSF+GAKv/L
WJUSNnGilkwv3MH9TZU79aU74TlARhiwa6nIYFs8w19sBOx6ZD50wZe3d4c8Osm+MKQxNyR//Xod
ciFf2OM8ObNVHZwlSkenK6hiN1aqmPrh4cknNao7LnoGoVm3MD5EI+yOHanh1KUbymIhX21rk7cn
dW4VaYdl06SBqNuZgzt7SjFI/pPqRnqGGorzscKzl2+Oript6h8/pK+1e6a08lm64iKmAL37wZin
dILeX/g9sFsrAS94YCly9R/j8YHz/k2ValGr+5pAWatBg31f/+csq7D/g4sFLDnqAvqFe+OrLNc+
tsqNqTASqz/PlmNIGbWNeZ7gAgkldHo096G6Bz7AScsIYA/rIgI9vn5mprOyyWfphmlSTSAWvSc9
3/kmxJ4fh4Ayjg4r2nNWQxBUIh+PWP5YEVp0jk/X22Bmdpni8VIZ5jn6fnQQ9xPqZDolvCnA5AHN
qxpd+bFJ4jfhn00SpmH5gwI1HAFw41K3+9IVfh2tYaa0I5QHM3entk72QCB65K+Xh8YJXDvcjpTF
DAoSltmyY8QRMEr5BVEt58BEk8yH+d7c+kpoE6JLjDY/GaN0/BksxcBPQ2iesNJWjY76dlUeEHcW
+vfILjbyXny7FndMOsCPX85hkqepY4y4AYpKMYctFBTjQZIWEVbGMERlm3TK7FNWfv66YOdEW3L9
2FUtHBKldxCXwbFRChGzgrg8VlgEyjwb9svthBzxYpYLuS4jaERhIxp/xvkt0UuK/PgUK91S8ghi
wh2VJDoPCJcR2cXGJ3nm1cL1RlFuzvy1lHch3pMn9EOiXZie61q9thjxxNaV2VKTYFCUViM0FKuX
2fhsT3x8Gz1l5/l9wgfe0QNi5sU687JWtu5r5lbtlxknjliyImqiU3cw+risA9TRVKiFUyUNQ7RX
oHtpJlfKWrhBS3MBJABml/yN3PpMgg4u9SITmRI5ow7B+ozgldzgTuuEeJnEpEf/kN5z+LHQYBuQ
E1dqVVVj0F/8P3mSPEl8I4Q+XU7BZXvWPXzfnOPdCJ2A6XCi6d6keqQ4W0tYEI9wdadwC3cvx5U9
bE6cddBvYqV6vw2NWp1Y3XNlCisYp+Zc+IpbY6qzhTlrTDkuxv4FDZZYE87w+/YylwGt/bJpCEKs
k6Wx6MXr6XCKjsEPhinJ5JdDKCOfbof5tdkArUlx4ZzVfzXY2qq62qzX/cfK0vhD9qMo/f/qAh4k
rK3GYi+Taxiv6QKbBDIxxJfIBjipNW4YAEFGek52gcOfgrJV2yVfOFfqN15pu5vHmbhBaenRp6Y9
dzUoVzSgKYoSpVYDmiwR1aR751LYjhPIl53NKEoZUn6uApVLkKp91yBdDpUlH7zTYMugZ8SlOvI/
n73QY8SAdNjs93r3ybPc02RpRjkEiqOfNeocEQFE23Y2BP+XcrV1PpjGIeRDGjj6T/cijlvil9Vs
5Sk/S8Mj0GogJbMqLRdrAJO01ypDzcnEg1dG0sTe82NWK1yLN3X3mngKU+N/DUSwawXkI7PTCnrr
EzYYVw0fhWGMiMZufio0bi1aVW5rv4ywHMP60s9r4+6BWDpihUcfpnmJGRuB1FipcvesTkq6va1d
apVrqAw3PGhGYqa3z5oLSO8O8BBK9egxisYGiKDzc+AVqOjMUBU77MbsuciOmlCogfh+Dvey3kdw
fuxn3QCH81cJTlB3gGwUtmDqxb40jtJT7+Gu7uL1EpBKJoHxgevmQHFOjSJqQl4Ruy9iJbH5J/fH
W1YN/lrMEx2hJemg7EczoqOL5P+TaoUwb/VipOpJ/PSwq+hHwCp7O9p27jAztEYhqbHcMXGIok0V
Cb/6zrrBpkbjBlEYdnOvXuPAGEQuWGNpYlzzlDbS9APnHkvkD+1lVFR8WzKrjguoHDf8z4dLZJL3
KLEpEIuJ2MwsCYzVH/RT9A0yK2uZ/o1lqvkPJYz2WbFKuRz4JtIXFeV1heeOejp69EqzAoPwd751
4pJ1AsqAQbvLjPvyLCqSUFmnzgq799gMXDRYnz+n5mGKwtOU9NaiK4jSCMvGpkfWVzsYe0t/r0hw
k16VOHR7RxXDoHYXRRL1K7QVPO+IWS/6xdOb8PJyz26MK4s+PfiRv5VuSYfUgAyYFkSbZRtulDR+
EOyGqVL0jmGCOtag27+vnuOki4iOM5p6FkZMs3EToAOOB2+ZUd973xtyD6kII4xTASzap0z/Pu1r
ZWEml30tjzPhiLq5gUM/6TjhusbavVlwHuMasj1tPgFGJEa7AMu5HWT1zwJQ6K6rMUFIgWn0iW3W
KC3fSFyTAp7pKQW5tqW4DBCAHzl8y2lBXlZH0sY9KytLtfU4eYQqAsQ9i1d1hI8yd/wsEGl8mi8z
Joeuj2tSkJmhpruUFnR59iI1gMe2wahTjQAoaboZhkYFdzaPRzeamcAtmNEZpDr6x6CcfXIKkO/+
pMao2lW8zsdfgXwGP81Da3WXpXOZofGx1hR6Bzo1gsQ7nYpY0JhGKS1OQZUgUr0kS8J4vkASgB4b
a4k0c+tML9cjvdZqgw3joc6ymz0j7+Kk12Q3QIk42fHPDePfDbdebBEUp2ExanDIjQ3JjK4OGhaT
hw2pg8CtwxsK2KoAVb+YFlRvaH+3oxfpAIZKDTk4iy90l7k+S3FXvLtieJcxiE059T2oDguZah0m
NqyHiuSm/eaHG/gGxrm1NYipJQmvxjI/O3xgPirxOP6dTudDLiE3T/+X1f6Xn6fwaTpvwVYInw8c
apK7/84F81reLHxuaEKXygzL1LY1Sca41FtKyymfDa5WjXaMtwffUv8HO+C0qwmF2MPD3a4Exr2n
cs3cu9iYFE9wtGWJ5+Ia9pq0giWx3W7l6UNvdzZzSDGtCNs6NXX2TIzndiHYqCkCf0562oTmIlpo
a4fYDE6oRWo1FQdGGgFL8wyD7ryOGyzcNgpWfuZ/TTGxWjZk+VgIBS/oTQME4Anss8TPiugZcZ8j
hw9GmoNSkwzwMcnzUrNliquOX39QkEXdM9XICSi4MmXXE9QdsXr8obvjHuG2NVtVx0KnfMexzqFV
9Ypl7jeCacdrDqXm+eRl/oqr1EjgudeNboTe/Cq5qjRBVFXOXl0Fq+PG4eBjwOO4uxI/rEBWqRaT
0c8WTykVt2ZpHWCdytZmfOZNQzGKTWtglR1XF8wf38z1FklIkNgiaUipjPybj3AqrSjWLqV43O6J
5J0LEOcWl9RsRisLnNkwGzTvbEBBW1fXlmzsVJ2zcyJfdqgD8RVyL0XhaiNSBCkfD9GyDkjO8mV+
TVY0f94VSgEEKzsrTWrVMdGQncyX8xOk8B15EAWpccHY44d8nflzaY2orVUIxYZnkV296TEfuC7I
nv4zWxd1tHxz5f7HUMvYoqGXQQtoS+f7GJV9xvzOCs9uc679YqhbI2kmYVSPPqXjTsgN3yaJ7pRc
O1BHZZIHCsPSzjJY1/j1/B5xqt3lAnQEFRIFXSpa30QQuNEMWmPDRrWU9hfZZ7n1YaqOahW+DAAx
WDol5XYFmdcXOhAy/kt62/0Tm6wkBmvN5WdAQjNGg6rI6B826a5/iFXO4JjEj9VSBq1aMJkgdCu2
3gwDDaxWQwdrrZXwY/ZaIZXRrOrJoAOXuhL6EOOh+rJheSqmwjGkLfpEmrtykF7QMjIt7vOHaX4a
cy6wV1XPKmqLReWf8Mqkoi4v1StV2KQ8BJGhI3x8k+C1uqMrrGgG5KUFuHHAZZvnNu+Hx/Fb408h
bUNHeKiokVGBKHCPON8KT9ODsLvakWTL7k3c2mI+vpSANqROtw5vy/47+zOVJAu4txnq32fGQ8Uq
ezA9a0IvgSYniIJYPJNWOeLoGaCeGBsqFfyS6gAsWynVT+1gUs7nilAHavwXmJsCNs/bSorR/7wC
anTJ6vlID5Dh6pAlwSaXTZVSR2V8sD3If51XCSLGF63xvubPqyeqmmyYuzxjdZZhFyszxPrbgL/Y
j6pbDXXbE4xYWENPQNf6WKGH/UqXbPPiy+ZsCp5CybzZa7e3gZdfnQ6V+LJI6aWyYG2to5fZ+p7I
sUoXv6yr4NBYkyTsax2ziARaZjs6HY9eoelSu1tFRJmHCYfEblhz+BuhkqmS/M4n8dEWDSbOatF1
P7SxGaFDWNG3nh/DEgDNsx03dZJm3gK5r5cK+Xpmu6/Z7uNEiK6cpfFPIHAk7NE5ky9x83NogkK2
dXTi16Qi87AlhvbWtWYtAnEeJmiJjswBGdlaqhDJn7tFiYP23AUrFNdV1QnQWKj4bgZU9yrMBikh
w1LTd8ImD7Ysr3vBJobTTr1/Ekne7nHdPRM3WS5CK/eeqPSDlaoFRV2ik473ANc5bSe2yfyHasZz
m6uIg4Dvx9jwVekXjLgDlfrDSDBdFQTaOUHGQI8tOlLa35F4u/YsGBcsIo6uvzZhDUdyEbG3Rhmc
y03Q6viLmVh9yM4zN0nhZ9/dqH91CoW19R5i9I91NhVUZ70DggS0t1XpGVO7GXOmAMh9Z4ujBXOI
V5wN0cqURAfTsrEWgcqRvPKI4XSuCkLsk8xV1rgTHW5OP7n69PHNP47ENH/EHayMP88cu6xQNcM+
+dIpYL0pKQk4yf7sudqf1Ae+4w871b86k4FBvDvMLmzgzIdqBkJ39jg+YfRX0AmtHPW7/w/clC66
X0CxPGxnQXBk/51OseFMAT/ikKtsDR2IAxCIgGFmJ3J5atgWedgeS1KoFO4BypaKN5CtYqSxJFln
mC3EFyenkFU6sbP9FVCEwE8DRlzqiTfgbaXpDaPz7YO7Yo6x3aCOjxRWJCpqBZH2lJKft91pjrix
WLUst4641XWcv76SKFdAE1XFyHbv1MGS0y9BNtbJZavwP1ISS4cxsYQAtIx3wxycbKbBXjzlIeHr
r8lg1xXcsHytfIwIvlLtiunudoYeif4Y+d67OzXHN7AmiVR4E7Fz25+D6/gf3J4T31le/zJWvCjs
FyuMIEHmr6yXTWXdkIvmSKA9k9xj1JBSjd9TqzIfUoN9jBSL3ykQ7mjbqzViVjEHCuNtbTn3BaSJ
J+MMPi2QzasckyTmJ7zf0WBpBfPWuU/EHyxDpSLMptgfTa/YD3JnJR/2FuN/JLeIETYYW0MYWZCn
GjfsTrJWjUB8Yo01Cr8+3g2rB5l6Xu9hK519VKiZN6laZ1e4CcXE6X0Iv8DychlTLDYYHl08/es6
o5L3j9r8y+JDdAES0ZMCILq1Mq2KNSg1Yzt0BTE2+qx70knp/XTEE9XJ059m9PUvlmJFpyQ23nQH
AKTAIM2nDZFBBTZJPPzIlMQ6g0yeM0/W5FUVhio5IpnDo5yhi1WIDL+++eiu8CoycqZp/PI1KXr9
ppcxO6Qxr44S9CDYS55Si9nzJYQAfLgOP83Gx30IXYMxLp8MAj8BE7fdhn1NGrMq22sQco7GP13/
2GB9ktpXEwBk6bRdvySfuZ8Hgi6BcMVIrEAesHhMnUSfz9jJrN/+fGpThrpVudFIIxRBzQ/NjwaE
5QY0Fd0ZeS4ZTrd9MNNy5atnuFhF2mRggAssaCOsuhjlevaYgc5M8JoQ9LLefg6w7X7jLtFE+u8v
MtEDGql194zmZg4sdwgM3RMrAuUiGVoaE+je1OhtHhNYO4wIGBR59BtNrQMW56vAlniOCI83v59R
D0wIecWICeORR/8e+hjmP92dVrQ71Wgth/EQCu09jClmdY896UxWf36mGxYU9qbHbzW1tMvhRrL8
NauIsf3hpdwnV+6OXzSpUO6WrNIJwZHaV3QuLO95tWeLKK7SER6DELs3Sd5UOZEO+KWAQ8ahG6bG
C0cg5Q60S6ChOIUbHhkN1Vk+MdY4kH0ZtEBG/lv4QgTsTaJ21z5TWVArRE6diBkG8dfBSrcmuIR/
PBIT4ozig91bIr61Sjn4t4fEfC2B84DIPFD+aSUa44+01R90kGVf8+igexzqs1/tB7jDnNAcboXF
wIK8V1inbTQoSEsRRDDKCXrf7a/+WxCEsz9NlM7AJQU3CARIejCHyAYb2ra2xbPjYrXeTOYvxrVv
9fnkbnWiP1oK5HoaJI5LTTTii3unqcTVdZKDpunSwZXMvCS/FCZMKPmNF0hyyu8FYvIl5lyHdZND
Kq+RBgwCHeSEsdtKSk+vULZFh9Y1jj/81P9PIGoN1jpDZaYCTrlfuSSyz6KdN40Y8Fha1oT/HFJ8
lAVpcNAOgG15I8OiTIzn2Pw/8tmxA8PZnpICWTY0+tUhRCv31++QY2tROsY4PhGGtO/FA/6hUyCH
uupQZaoSf1I6hkhanjKjVsELHnGqxbCgHOqW02/RUnKgq4LerFxg3Ouw8MKEtIx2aLlXZUJvEs6e
jrvv34tWOZANflCtN41VYh2DzgjNE7J66QdODm+nzqttHYnqu7pu5bqbmECttfuy6kr0G9S0Ezxo
WzKOg7O8mn/7d3+N+IfwPW0h6Y3KbOoBLpLXIQIEV+u/DaaP5EZrj3KQCAVMPehMIDDEJZDCrgc0
ufrtSwrt6oTSgxmRKnI4oZ0HD9WDwAqUUoormQPqRlXtiWbI5wRW6UpX4zTLN/kpEhKqgNtptMOP
AMyFwJIU9SJdnwHwTp+eDHgLdO4n4R9lG016cV92iBS+q2PeAkwKb1O6dA6ezCQ1vLm76GF8TYwO
3Di2YMk0KYX4bg+Uqr2kIBwtEx4Ipz8zruwSUAkaV8qAPBAFCe4JjpRVqVl6iYe1YjkLdegqnKDh
izm4Dw8FFSvNhNnBQGfjng64a+FzbQH6tWbcpCgAOr91nmvs5/1owL2feyuMnGhZtlSDW04whrSl
z1zqgB0AuN3VkFOt7GaV6NOMC23SkAD9vP49WdIV1ah9WuDp/Afrvc5HEIZKca/DAkPlEJZhUsOp
5VF1DYUNsfNO03A8R+kGrCLAuyeg2+K5/fcaQtl8SrDm4sDjWlgsoqRWQUuOvxtgqULpwRJmrFDe
+tA3bGTh9nzkuCFTO8lJGuxxK+9QWgXvufQ9WJf3m2WI9k3iOPAArB8LU70GNcAIvYnGOMYIbhuJ
LZNuEH+zrt9WLHqUdCGvTNfPNPLZv0G6PqOC12tIQmDtetjH/MNBDCIsrmeUsdRDCfHI9uMZS7cX
FKJ8443uvnpo/pw/FAGW3UJFjYvdUl+b+EmjW3Fafav/VhmS/hTdfkI+MrXiz/FCwht64jTAPfyY
lFdNJnZU6nMkIbSscOm6/P62gU1AWrkAnyPs0QjawUdFQrJSNXYnMPP+ECCeH7YP2DLsELDwjkBi
Rm7oA/XDryTnI8sqJ8io5Neg0O6uqvYAMie2xFX3BuxNqX9T2SXr3Yps4WnK8O0yfc0aLeJTRjIT
wkXLwmKZTWcsmt6x7MufLUAs5DltPed7s1aaefciI4MG/gJBs21Y6K92J1W1bhwEPeSpMC3D9f0o
QRgT1qotbKjBOiTVa6nPoBRxync8SAgQkX/pbskGmeunO+swEghqdqe9vtMI5j8VYLY/BGJ9hwfA
DwNLMF6mztRymRGLeqT8Zl3XvnllPW3EBEVM8a7/dSpOu7IxNSFjtp0pxkfyZ/NJI/3xF2fLqs8x
CNfklwJFtIk50fRaK5DhtHUbmyIgYkGSjWUUP7RuY1YBc2sMmAnM4ZJQBaEwLLnNOqOuZVOXnEz4
Yxz5sD70yyrKxB51wlIIAU8AuPBlQCpD6e7xwB1cdIg8uHef8TMXwiahOHqDvNGpVOXmRG+4Cf8a
NcCCTEWyiMMRdwuZrvDFVMVVHsk60lS+RVJWAZdUe5HjrKnegbglJN6gFEH77y9p0QfLDFEljjsv
IGX5sLb3bBNWmd0b6I42fhdPr8kVv1QWWhJLWm4xxAmuId5qwKFylAwHtp7RoCDhvcS3+qmThJiQ
Cw7YVSkj7ztaT7wqtQGGes8Y2Abn40nLLhtwLnQdPzfiGEo2edxS4Z16/nyJU4aYY6winTb64b0E
DceJ6D6b/ePLI8RchmK/USeGiuVxn+FsXfEug6hlDpy4xrz+ywNnphJqkqZ6qODZJhSf+4vB+Dy+
KdobPJDJdj1VdQeRQ/FK+ZPDZ0HLzKjKwPoQGt3kfgJcEPRrP77ZRIyhcwuIk8Bw8deVjoAgJ7o6
PGYYaHf0VDFaVMXvlQ6ZLZggXvbXBw/qxefQyAJEN/rgjsNZ/wUp7H2BnT3WMx7+SWMgb9wE/fT2
VrRNgC4q7B1iSEj0k40DE337JnLiginPdIu5KQ3ps8Au7q3jMfkI78rdJ7XmZuWqANJ2p1gUMo6K
mdeDCqp5UQ6YiwaXJvmcuhxpV4MUCVAM1unULDYq1CGMU291EA9ga15ZNNDTJuwrdbDJ7p3+BASY
y3112aUcg+e+YwjieTZKlQzT8p+/rB9/mDwlMIqNhjAH3aGFo2CSlX7ZyE5Fpv8SrwoH+Ry4ZL9X
S4JIiD7EzZ1BdoIpl7fEuzMQsORcouNp9KRievSaTRLMJljY5mbOfqGBtaoaMzcO0+MHVrbjfK6E
wg95eSIEQAIMqk/R6STBzChhvrE3g0EyejnVVf/CWIH+cxn7+WP0jAN2MjQ0cQAljKK7Gyhi8gqH
T4bDI+9ap4yqkwNwjJDWCMJDp1kMWbAElQcpTVEbeUkvGNu/wJZj6kL/CrdSbGTMMhEhAJc5nriQ
d5lbzf3YS8mF6FZC35pNTpaC+pqjAyuHBNcFgocmvzPCw+lOETgW7319aXVGVu0l5H7BPz0n1899
ImwHHp4W3KV1MAj2kOH2O8Md82a1nUbgv25CLHtY+va3K9M54ZMoPM1EGEdeyJNK4bPo6TKodUn2
7xMPTtMksr76CKc/u/I+okUSdRp8kXU2Ce43yLtArT3BCi94YzC2kxyE//cGv+PA7AqyahYDUiRP
8QsMFgGB5mI+PZm9ewQFT10IfRQSM6Z3ogVst1SRthI11Q8f5O1ReCm07y2OkfXM7JU/B85OoRJd
J77qDNnIvIXHTYUqT8iEUab4DIL9Dj6Zlzfxvx+fMvM7Rt7kDrHvIz+DeIwWX9d4MO9/fMAfvSpZ
/5sKmaePFfwcv1c2USVYPZFcdo/lUomAJvuZcwlsmOh88ur+WnC0Nm9Gz+a82qQq1NV1x5ydMytv
Z8NladOKFVr9HBa6ZCg8sj/Q5B5dY01Z61Ufxu8Jfty7CGZe07Dkf3WOxLhbJmyUxa9qLsCYZWBU
XLd6sv9qsvCIa0rCXpWDM23yV3lfcdqORu9437b6h2OLcul71YAVgTv+fs+7hvsdoT81YJ/HRFv/
7yw9+2h6PYle5n6vyzEpI8zp+qdv7Oegen3s4lnXgqgOUiYw6RBAd5QsTFFs7x7NlhLD+dAUudIG
xr+6A0EOFAkOW0k1uLOho5gHV3ENol1XK6BVv//ipr9w+PT6yapAgXPZSNJg0GvVWHi6k3M/3TBf
73zgMu/uKnmzDzbKS01eH8qqJwum0zVUV8vXqDFjhlP/LexB5Ffq4S6vYWeI4VsFAfjRUfOTMeKQ
3kUgXsszv/xxHcJKWbSLBscPxnToxS8+cPi6JZ/iDhxud4gKjlaiCdwZ+gzVv5eWhTSpxwgReLQq
E0f22mFkP78EBaG3rmXZsQRF4zGIV49rvcgdRBxjHySlQHzy9tRuMTLQW9y1djMI3Hv7U2pU2i/a
a2o3YHhd1lmxWGGEDegSBvhMUeUgEDTpPnl+ACEShNpkVJTSpX3Bvnc0YKXR4/ZU7PX+vbCkr8lc
4m3diWmXQr0uxHBVsDVa8QzuB9GlsFQxrf1LJW42PS5zvYZ+vRRx+/hW04fAyXGMoTsiKKuz0hg4
wrX9t/Gh7s0+m0GkqfKUg09Ka9Tpr3iXEyHO6YQY1+4is/zm7UZNXtcI7BnWwlQhNB7uTq6jzERM
PL7+82JsnScH418sDuGOK57rBZoLB8KajHox5VjGAkNdPIpiwq/zOiNLU/QbKnF1UK1MpMbJx7rZ
pOTJ+B3SDVVmZde7mCOlJ3IyBsM5/UgR3EWGOoHmCdIAW6JxF5dg+r/3InSOk4OiarbDwBgVts6G
idIPVHWjPY4dre/sY8a4cBrCRzYNerMFqsV7I6jRdVVuaUBWE15Z24Ydr3UQSSEPWSuSCXnBKCaB
rQWhwG34ccHT5iCml6GklQIky/x8mARbsfFwlsbLFTJF9gB24ml0osD4M+Z7q9kFbqarxDkCa/ZO
9mbjty63/UTNAzuibFXnkQiEK1O9TFHKHhTbrKwZr18JKHEW40x5EmxY/H7OI+UZG5WfyWkuqn26
kirjyVfBQdyQkphqQL9mKqZVSyK0o67JzasznRZaiINEpfLYcUgRDxFCPITST6UEe7EknKZlji2B
MuYsnve4qPemDVOV4INbcHNbqL1Fw59f84U9fZxphkzU0YsLBTIPRMzm9mn3kOqeF3RfyzFvOZT6
jTQ5Q/VndPBPl2EIEudqmJdOcdCNMXkWVbp0rp6auGmVEzTS8ic8ouivF9eT7zKUdUCniiIxLELb
VwgnQpMHk21Noy3giSQTLaQ4nU5pzG3qQGywzA4+hVXdQ5AINSyp4+DkUkRFlDxF2GQ5CbBOFAu8
2RWcuOcMkJuCroKIbV6eUPEv9UFgNi5RqjBXapctZiEac7+ZQpNEFx4vDKqcpE7mkLrig0a3k7g9
2KYeVNlED9sy1ILr1shrqA7J9Lv1h0Uqua/kiKrd7FjfvHUCElTOkb83Ea4IGxhRWa/RzEmICnF2
WS59O6FQzw2nC29nBmi1RfkeemvzLcgwqrmp/5GkaFrBS9bZW341aSHPp9B/QxxT7DDhwB0ypK0/
5dMyAWHS3Mkvts3103R8rdi934h0UG5UN6KR9PzFixo2Mjakp3k8EW47M0unqo23onT5ddqIIHq+
4KlE54x/diETv6PW6NV3lUh01L/khwpoE4yp7rLqh46iZFwpe0471MIQb/CBei/4k5KRcXL5xR+F
S0mjTkIVC4Y/L18uLmUEmmTdZoALPrFzBgmBtTZOEt587ZYhBn5lwkAabE/IChTDZoaTD4Qhdw4Y
HTABo94RYB5bbz848mKExD2tqkp7Zan3GY4hYWWJA6XWkmbOKpJSVuu1td8jxZLIBcJkrpMn+iOY
sS2/D/NSy6jaT71A0B/EJ7TzqCpLUkFL2nHm5DfBqvq/YydXASE3ZquJYll5tzHcPAKjdrGAdjS3
mNq6VFqCN0vb2I9TvyYyACsVz1X7gkdFKtv0g7QOe53m77CaEwiDkenGDcSeDfHx6dmwvA==
`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cpu_1x3 is
generic (
PROGRAM_00 : string := "input.prg";
PROGRAM_01 : string := "passthrough.prg";
PROGRAM_02 : string := "output.prg");
port (
I_clk : in std_logic;
I_reset : in std_logic);
end cpu_1x3;
architecture Behavioral of cpu_1x3 is
component ben is
Generic (PROGRAM_FILENAME : string);
Port ( I_clk, I_reset : in STD_LOGIC;
I_puw_dataValid : in STD_LOGIC;
I_pdw_dataValid : in STD_LOGIC;
I_plw_dataValid : in STD_LOGIC;
I_prw_dataValid : in STD_LOGIC;
I_pur_dataValid : in STD_LOGIC;
I_pdr_dataValid : in STD_LOGIC;
I_plr_dataValid : in STD_LOGIC;
I_prr_dataValid : in STD_LOGIC;
I_pur_data : in STD_LOGIC_VECTOR (15 downto 0);
I_pdr_data : in STD_LOGIC_VECTOR (15 downto 0);
I_plr_data : in STD_LOGIC_VECTOR (15 downto 0);
I_prr_data : in STD_LOGIC_VECTOR (15 downto 0);
O_puw_writeEnable : out STD_LOGIC;
O_pdw_writeEnable : out STD_LOGIC;
O_plw_writeEnable : out STD_LOGIC;
O_prw_writeEnable : out STD_LOGIC;
O_puw_data : out STD_LOGIC_VECTOR (15 downto 0);
O_pdw_data : out STD_LOGIC_VECTOR (15 downto 0);
O_plw_data : out STD_LOGIC_VECTOR (15 downto 0);
O_prw_data : out STD_LOGIC_VECTOR (15 downto 0);
O_pur_readEnable : out STD_LOGIC;
O_pdr_readEnable : out STD_LOGIC;
O_plr_readEnable : out STD_LOGIC;
O_prr_readEnable : out STD_LOGIC);
end component;
component node_port is
generic (WIDTH: integer := 8);
port ( I_clk : in STD_LOGIC;
I_reset : in STD_LOGIC;
I_writeEnable: in STD_LOGIC;
I_readEnable: in STD_LOGIC;
I_dataIn : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataOut : out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataOutValid : out STD_LOGIC); -- TODO: Check if this is actually needed. We can reset the O_dataOut(0) to Z or U instead.
end component;
signal inputWriteMainRead_writeEnable : STD_LOGIC := '0';
signal inputWriteMainRead_readEnable : STD_LOGIC := '0';
signal input_dataOut : STD_LOGIC_VECTOR (15 downto 0) := X"0000";
signal main_dataIn : STD_LOGIC_VECTOR (15 downto 0) := X"0000";
signal main_dataInValid : STD_LOGIC := '0';
signal mainWriteOutputRead_writeEnable : STD_LOGIC := '0';
signal mainWriteOutputRead_readEnable : STD_LOGIC := '0';
signal main_dataOut : STD_LOGIC_VECTOR (15 downto 0) := X"0000";
signal output_dataIn : STD_LOGIC_VECTOR (15 downto 0) := X"0000";
signal output_dataInValid : STD_LOGIC := '0';
begin
inputWriteMainRead : node_port
generic map(WIDTH => 16)
port map(
I_clk => I_clk,
I_reset => I_reset,
I_writeEnable => inputWriteMainRead_writeEnable,
I_readEnable => inputWriteMainRead_readEnable,
I_dataIn => input_dataOut,
O_dataOut => main_dataIn,
O_dataOutValid => main_dataInValid);
mainWriteOutputRead: node_port
generic map(WIDTH => 16)
port map(
I_clk => I_clk,
I_reset => I_reset,
I_writeEnable => mainWriteOutputRead_writeEnable,
I_readEnable => mainWriteOutputRead_readEnable,
I_dataIn => main_dataOut,
O_dataOut => output_dataIn,
O_dataOutValid => output_dataInValid);
-- Input BEN
inputBEN: ben
generic map(PROGRAM_FILENAME => PROGRAM_00)
port map(
I_clk => I_clk,
I_reset => I_reset,
-- Read
-- Input BENs should not read anything
I_pur_dataValid => '0',
I_pdr_dataValid => '0',
I_plr_dataValid => '0',
I_prr_dataValid => '0',
I_pur_data => X"0000",
I_pdr_data => X"0000",
I_plr_data => X"0000",
I_prr_data => X"0000",
O_pur_readEnable => open,
O_pdr_readEnable => open,
O_plr_readEnable => open,
O_prr_readEnable => open,
-- Write
I_puw_dataValid => '0',
I_pdw_dataValid => main_dataInValid,
I_plw_dataValid => '0',
I_prw_dataValid => '0',
O_puw_writeEnable => open,
O_pdw_writeEnable => inputWriteMainRead_writeEnable,
O_plw_writeEnable => open,
O_prw_writeEnable => open,
O_puw_data => open,
O_pdw_data => input_dataOut,
O_plw_data => open,
O_prw_data => open);
-- Main BEN
mainBEN: ben
generic map(PROGRAM_FILENAME => PROGRAM_01)
port map(
I_clk => I_clk,
I_reset => I_reset,
-- Read
I_pur_dataValid => main_dataInValid,
I_pdr_dataValid => '0',
I_plr_dataValid => '0',
I_prr_dataValid => '0',
I_pur_data => main_dataIn,
I_pdr_data => X"0000",
I_plr_data => X"0000",
I_prr_data => X"0000",
O_pur_readEnable => inputWriteMainRead_readEnable,
O_pdr_readEnable => open,
O_plr_readEnable => open,
O_prr_readEnable => open,
-- Write
I_puw_dataValid => '0', -- Don't write to input BENs
I_pdw_dataValid => output_dataInValid,
I_plw_dataValid => '0', -- No left BEN
I_prw_dataValid => '0', -- No right BEN
O_puw_writeEnable => open, -- Don't write to input BENs
O_pdw_writeEnable => mainWriteOutputRead_writeEnable,
O_plw_writeEnable => open, -- No left BEN
O_prw_writeEnable => open, -- No right BEN
O_puw_data => open, -- Don't write to input BENs
O_pdw_data => main_dataOut,
O_plw_data => open, -- No left BEN
O_prw_data => open); -- No right BEN
-- Output BEN
outputBEN: ben
generic map(PROGRAM_FILENAME => PROGRAM_02)
port map(
I_clk => I_clk,
I_reset => I_reset,
-- Read
I_pur_dataValid => output_dataInValid,
I_pdr_dataValid => '0',
I_plr_dataValid => '0',
I_prr_dataValid => '0',
I_pur_data => output_dataIn,
I_pdr_data => X"0000",
I_plr_data => X"0000",
I_prr_data => X"0000",
O_pur_readEnable => mainWriteOutputRead_readEnable,
O_pdr_readEnable => open,
O_plr_readEnable => open,
O_prr_readEnable => open,
-- Write
-- Output BENs should not write anything
I_puw_dataValid => '0',
I_pdw_dataValid => '0',
I_plw_dataValid => '0',
I_prw_dataValid => '0',
O_puw_writeEnable => open,
O_pdw_writeEnable => open,
O_plw_writeEnable => open,
O_prw_writeEnable => open,
O_puw_data => open,
O_pdw_data => open,
O_plw_data => open,
O_prw_data => open);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
ENTITY INTERFACE_COMB_1 IS
PORT (
inp : IN custom32_in_type;
outp : OUT custom32_out_type
);
END;
ARCHITECTURE RTL OF INTERFACE_COMB_1 IS
-------------------------------------------------------------------------
-- PRAGMA BEGIN DECLARATION
COMPONENT Q16_8_DECISION
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT Q16_8_FullXorMin
PORT (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT START_32b
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT STOP_32b
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
-- PRAGMA END DECLARATION
-------------------------------------------------------------------------
SIGNAL sINPUT_1 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL sINPUT_2 : STD_LOGIC_VECTOR(31 downto 0);
-------------------------------------------------------------------------
-- PRAGMA BEGIN SIGNAL
SIGNAL RESULT_1 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_2 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_3 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_4 : STD_LOGIC_VECTOR(31 downto 0);
-- PRAGMA END SIGNAL
-------------------------------------------------------------------------
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) INTERFACE_COMB_1 : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
sINPUT_1 <= inp.op1(31 downto 0);
sINPUT_2 <= inp.op2(31 downto 0);
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- synthesis translate_off
-- PROCESS(inp.instr, inp.op1(31 downto 0), sINPUT_2, RESULT_7)
-- variable op : std_logic_vector(1 downto 0);
-- variable op2 : std_logic_vector(2 downto 0);
-- variable op3 : std_logic_vector(5 downto 0);
-- BEGIN
-- op := inp.instr(31 downto 30);
-- op2 := inp.instr(24 downto 22);
-- op3 := inp.instr(24 downto 19);
-- if( op = "10" ) THEN
-- if( op3 = "001001" ) THEN
-- if( inp.instr(13 downto 5) = "001000000" ) THEN
-- printmsg("(PGDC) ===> FIXED POINT SUB A : (" & to_int_str(inp.op1 (15 downto 0),6) & ")...");
-- printmsg("(PGDC) ===> FIXED POINT SUB B : (" & to_int_str(RESULT_7(15 downto 0),6) & ")...");
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN INSTANCIATION
RESOURCE_1 : Q16_8_DECISION PORT MAP (inp.op1(31 downto 0), RESULT_1);
RESOURCE_2 : Q16_8_FullXorMin PORT MAP (inp.op1(31 downto 0), inp.op2(31 downto 0), RESULT_2);
RESOURCE_3 : START_32b PORT MAP (inp.op1(31 downto 0), RESULT_3);
RESOURCE_4 : STOP_32b PORT MAP (inp.op1(31 downto 0), RESULT_4);
-- PRAGMA END INSTANCIATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN RESULT SELECTION
WITH inp.instr(13 downto 5) SELECT
outp.result <=
RESULT_1 WHEN "000000001",
RESULT_2 WHEN "000000010",
RESULT_3 WHEN "000000100",
RESULT_4 WHEN OTHERS;
-- PRAGMA END RESULT SELECTION
-------------------------------------------------------------------------
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
-- RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 : in STD_LOGIC_VECTOR (3 downto 0);
RA1 : in STD_LOGIC_VECTOR (3 downto 0);
RA2 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB0 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB1 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB2 : in STD_LOGIC_VECTOR (3 downto 0);
-- OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC_VECTOR (1 downto 0));
-- OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
end DC_CTL;
architecture Combinational of DC_CTL is
signal OP1 : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
begin
OP1_SEL <= OP1;
-- with OPC select OP1_SEL <=
-- "00" when "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
-- OP1 when OTHERS;
-- with OPC select OP2_SEL <=
-- "00" when "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
-- OP2 when OTHERS;
--
-- OP1 <= "00";
process(RA, RA0, RA1, RA2)
begin
-- if(CLK'event) then
if (RA = RA0) then
OP1 <= "01";
elsif (RA = RA1) then
OP1 <= "10";
elsif (RA = RA2) then
OP1 <= "11";
else
OP1 <= "00";
end if;
-- if (RB = RA0) then
-- OP2 <= "01";
-- elsif (RB = RA1) then
-- OP2 <= "10";
-- elsif (RB = RA2) then
-- OP2 <= "11";
-- else
-- OP2 <= "00";
-- end if;
-- end if;
-- OP1_SEL <= OP1;
end process;
end Combinational;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:44:56 06/01/2014
-- Design Name:
-- Module Name: toplevel - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity toplevel is
Port ( clk : in STD_LOGIC;
ledred : out STD_LOGIC;
ledgreen : out STD_LOGIC);
end toplevel;
architecture Behavioral of toplevel is
signal counter : unsigned(25 downto 0) := (others => '0');
begin
ledred <= counter(25);
ledgreen <= counter(24);
process(clk)
begin
if clk'event and clk='1' then
counter <= counter + 1;
end if;
end process;
end Behavioral;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
-- Date : Tue Jun 30 17:04:32 2015
-- Host : Vangelis-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Instructions/Instructions_funcsim.vhdl
-- Design : Instructions
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Instructions_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 17 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Instructions_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end Instructions_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of Instructions_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 4) => addra(9 downto 0),
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000044000044000044000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"003C000007F0000007F000000000000000000000000000000000000000000000",
INIT_1B => X"1E3C00001E3C00001E3C000007FC000007FC0000003C0000003C0000003C0000",
INIT_1C => X"000000000000000000000000000000000000000007FC000007FC00001E3C0000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized10\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized10\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized10\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"4400000000000000111177777777770000000000000000000000000000000000",
INITP_02 => X"99DDDDBB111100000221111FFFFFFFFFFFFFF000000000000000448888CCCCCC",
INITP_03 => X"0448888CCCCCC4400000000000000FFFF777777FFDD444400000000000CCBBBB",
INITP_04 => X"0000088999999999999990000000000000003377773333331100000000000000",
INITP_05 => X"0000000221111333333333333330000000000000007766666666665544440000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"00000000000000000000000000555566666666EEEE666666666666AAAA999900",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"01C3870F01C3870F01C3870F01C3870F01C381FC01C381FC0000000000000000",
INIT_0D => X"003C01FC003C01FC00FF070000FF070001C3870001C3870001C387FF01C387FF",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"7F00000F7F00000F000000030000000300000003000000030000000000000000",
INIT_10 => X"E0000003E0000003FFC00003FFC00003E1C00003E1C00003E1C00003E1C00003",
INIT_11 => X"000000000000000000000000000000007F0000007F000000E0000003E0000003",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"E1C38700E1C38700E1C38700FF00FF00FF00FF00000000000000000000000000",
INIT_14 => X"E1C0FF00E1C38700E1C38700E1C38700E1C38700E1C38700E1C38700E1C38700",
INIT_15 => X"000000000003FE000003FE0000000700000007000000070000000700E1C0FF00",
INIT_16 => X"000001C0000001C0000001C0000001C000000000000000000000000000000000",
INIT_17 => X"E0FF01C0E0FF01C0E1C001C0E1C001C0E1C001C0E1C001C080FF87FF80FF87FF",
INIT_18 => X"0000000000000000E1FF00FFE1FF00FFE00381C0E00381C0E00381C0E00381C0",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"E1C3870F81FF01FC81FF01FC01C0000001C0000001C0000001C0000000000000",
INIT_1B => X"E1C3870001C3870001C3870001C387FF01C387FF01C3870F01C3870FE1C3870F",
INIT_1C => X"000000000000000000000000000000000000000081C381FC81C381FCE1C38700",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"FFC0000FE1C0000FE1C0000FE1C0000FE1C0000F7F00000F7F00000F00000000",
INIT_1F => X"000000007F0000037F000003E0000003E0000003E000000FE000000FFFC0000F",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"00FF07FC00FF07FC000000000000000000000000000000000000000000000000",
INIT_22 => X"01C3870F01C3870F00FF870F00FF870F0003870F0003870F0003870F0003870F",
INIT_23 => X"0000000000000000000000000000000000FF870F00FF870F01C3870F01C3870F",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"E000070FE000070FE000070FE00001FCE00001FC000000000000000000000000",
INIT_26 => X"800001FCE000070FE000070FE000070FE000070FE000070FE000070FE000070F",
INIT_27 => X"00000000000000000000000000000000000000008000000080000000800001FC",
INIT_28 => X"01C0000001C0000001C000F001C000F0000000F0000000F00000000000000000",
INIT_29 => X"01C380F001C380F001C380F001C380F001C380F001C380F001FF07F001FF07F0",
INIT_2A => X"000000000000000001C387FF01C387FF01C380F001C380F001C380F001C380F0",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0003870F0000FF030000FF030000000000000000000000000000000000000000",
INIT_2D => X"0003870F0003870F0003870F0003870F0003870F0003870F0003870F0003870F",
INIT_2E => X"0003FE00000007000000070000000700000007000000FF030000FF030003870F",
INIT_2F => X"000000000000000000000000000000000000000000000000000000000003FE00",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"FE00FE03FE00FE03E0001FFFE0001FFFE0001FFFE0001FFF0000000000000000",
INIT_39 => X"1FC0FE001FC0FE001FC0FE031FC0FE031FC0FE031FC0FE03FE00FE03FE00FE03",
INIT_3A => X"FFC0FE00FFC0FE001FC0FE001FC0FE001FC0FE001FC0FE001FC0FE001FC0FE00",
INIT_3B => X"1FC0FE031FC0FE031FC0FE031FC0FE031FC0FE031FC0FE03FFC0FE00FFC0FE00",
INIT_3C => X"00000000000000001FC01FFF1FC01FFF1FC01FFF1FC01FFF1FC0FE031FC0FE03",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized11\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized11\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized11\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"1100000000000000880000880022880000000000000000000000000000000000",
INITP_02 => X"0022000000220000000000055555555555555445511000000000550000110000",
INITP_03 => X"05555555555555511554400000000AA0000220000AA000000000000000000000",
INITP_04 => X"0110000AA0000000000AA000000000000000220000000000AA00000000000000",
INITP_05 => X"000000000000055444444444455444400000000000AA0000AA0000AA00000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"00000000000000000000000000DDDD999999999999DDDD999999998888CCCC00",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"1E3F00001E3F00001E3CF8001E3CF800F83C7800F83C78000000000000000000",
INIT_0D => X"F83C0000F83C0000003C0000003C0000003C0000003C0000FE3C0000FE3C0000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"1E3C1FF01E3C1FF01E3C00001E3C00001E3C00001E3C00000000000000000000",
INIT_10 => X"1E3C00F01E3C00F01E3C1FC01E3C1FC01E3C78001E3C78001E3C78001E3C7800",
INIT_11 => X"0000000000000000000000000000000007F07FC007F07FC01E3C00F01E3C00F0",
INIT_12 => X"0700070000000700000007000000000000000000000000000000000000000000",
INIT_13 => X"0700070007000700070007001FFC7F001FFC7F00070000000700000007000700",
INIT_14 => X"01FC7FF007000700070007000700070007000700070007000700070007000700",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000001FC7FF0",
INIT_16 => X"000F0000000F00000003F8000003F80000000000000000000000000000000000",
INIT_17 => X"000F003F000F003F003FF800003FF800000F0000000F0000000F003F000F003F",
INIT_18 => X"0000000000000000000F003F000F003F000F00F0000F00F0000F00F0000F00F0",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"1E0078F0F80FE03FF80FE03F0000000000000000000000000000000000000000",
INIT_1B => X"1E3C78F01E3C78F01E3C78F01E0FF8F01E0FF8F01E0078F01E0078F01E0078F0",
INIT_1C => X"0000000000000000000000000000000000000000F80FF83FF80FF83F1E3C78F0",
INIT_1D => X"0000070001C07F0001C07F0001C0000001C00000000000000000000000000000",
INIT_1E => X"01C0070001C0070001C0070001C0070001C007001FC007001FC0070000000700",
INIT_1F => X"000000001FFC7FF01FFC7FF001C0070001C0070001C0070001C0070001C00700",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"F83FF800F83FF800000F0000000F0000000F0000000F00000000000000000000",
INIT_22 => X"1E0F00001E0F00001E0F00001E0F00001E0F00001E0F00001E0F00001E0F0000",
INIT_23 => X"000000000000000000000000000000001E03F8001E03F8001E0F00001E0F0000",
INIT_24 => X"000F000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"1E0F00F01E0F00F01E0F00F0F83FF8F0F83FF8F0000F0000000F0000000F0000",
INIT_26 => X"F803F83F1E0F00F01E0F00F01E0F00F01E0F00F01E0F00F01E0F00F01E0F00F0",
INIT_27 => X"00000000000001FC000001FC0000000F0000000F0000000300000003F803F83F",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"FE0FE000FE0FE0001E3C00001E3C00001E3C00001E3C0000F80FF800F80FF800",
INIT_2A => X"0000000000000000F83FE000F83FE00000007800000078000000780000007800",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"070078F01FFC1FC01FFC1FC00700000007000000070000000700000000000000",
INIT_2D => X"070078F0070078F0070078F0070078F0070078F0070078F0070078F0070078F0",
INIT_2E => X"000000000000000000000000000000000000000001FC1FC001FC1FC0070078F0",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"80FF00FF80FF00FFFFF0000FFFF0000FFFF0000FFFF0000F0000000000000000",
INIT_39 => X"80FF07F080FF07F080FF07F080FF07F080FF07F080FF07F080FF00FF80FF00FF",
INIT_3A => X"80FF07FF80FF07FFFFF007F0FFF007F0FFF007F0FFF007F080FF07F080FF07F0",
INIT_3B => X"80FF07F080FF07F080FF07F080FF07F080FF07F080FF07F080FF07FF80FF07FF",
INIT_3C => X"0000000000000000FFF007F0FFF007F0FFF007F0FFF007F080FF07F080FF07F0",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized12\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized12\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized12\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"888888000022000066FFFF777777770000000000000000000000000000000000",
INITP_02 => X"FFFFFFEE000000000000000FF111111111155110000000000000000000000000",
INITP_03 => X"08899999999999911110000000000EEEEEEAAEEFFFF8888000000000002266EE",
INITP_04 => X"000000077BBBBFFFFFF7700000000000000077CCCCCCCCCC6600000000000000",
INITP_05 => X"0000000000000CC4444CCCCEEEE00000000000000066DDDDEEEEEE7700000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000088888CCCCCEEEEECCCCC888880000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"01C3870F01C3870F01C3870F01C3870F7F0387037F0387030000000000000000",
INIT_0D => X"7FC0FE037FC0FE03E1C3870FE1C3870FE1C3870FE1C3870F7FC3870F7FC3870F",
INIT_0E => X"0000000000000000000FE000000FE000000078000000780000001E0000001E00",
INIT_0F => X"8000000080000000800000008000000080000000800000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"00000000000000000000000000000000003F0000003F0000003F0000003F0000",
INIT_12 => X"003C00FF003C0000003C00000000000000000000000000000000000000000000",
INIT_13 => X"003C07FF003C01C0003C01C001FC01C001FC01C0000001C0000001C0003C00FF",
INIT_14 => X"E1FF81C0003C01C0003C01C0003C01C0003C01C0003C01C0003C01C0003C07FF",
INIT_15 => X"00000000000000000000000000000000000000000000000000000000E1FF81C0",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"E1C3FF00E1C3FF00E1C38700E1C38700E1C38700E1C38700E1C0FE00E1C0FE00",
INIT_18 => X"00000000000000001E00FE001E00FE007F0380007F038000E1C38000E1C38000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"E1C39F0FE1C38703E1C38703E0000000E0000000E0000000E000000000000000",
INIT_1B => X"E1C3800FE703800FE703800FFE03800FFE03800FE703E00FE703E00FE1C39F0F",
INIT_1C => X"0000000000000000000000000000000000000000E1C38003E1C38003E1C3800F",
INIT_1D => X"000001C0000001C0000001C00000000000000000000000000000000000000000",
INIT_1E => X"E00001C0E00001C0E00001C0E00001C0E00001C0800007FF800007FF000001C0",
INIT_1F => X"00000000E00000FFE00000FFE00001C0E00001C0E00001C0E00001C0E00001C0",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"7F03F80F7F03F80F000000000000000000007800000078000000780000007800",
INIT_22 => X"E1C0780FE1C0780FE1C0780FE1C0780FE1C0780FE1C0780FE1C0780FE1C0780F",
INIT_23 => X"000000000000000000000000000000007F03FF0F7F03FF0FE1C0780FE1C0780F",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"E1C399CFE1C399CFE1C399CF7F03FF0F7F03FF0F000000000000000000000000",
INIT_26 => X"7F0381CFE00399CFE00399CFE00399CFE00399CFFFC399CFFFC399CFE1C399CF",
INIT_27 => X"000000000000000F0000000F0000000F0000000F0000000F0000000F7F0381CF",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"E1C0FE0FE1C0FE0FE1C3800FE1C3800FE1C3800FE1C3800F7F00FF037F00FF03",
INIT_2A => X"00000000000000007F03FE037F03FE03E1C0070FE1C0070FE1C0070FE1C0070F",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"E1CF800081C3800081C380000000000000000000000000000000000000000000",
INIT_2D => X"01C0000001C0000001C00000E1C00000E1C00000E1F00000E1F00000E1CF8000",
INIT_2E => X"000000000000000000000000000000000000000081C0000081C0000001C00000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000003F0000003F0000003F0000003F0000003F0000003F0000000000000000",
INIT_39 => X"FFFC003FFFF0003FFFE0003FFF80003FFF00003FFC00003FF000003FC000003F",
INIT_3A => X"FFFC003FFFFF003FFFFF803FFFFF803FFFFF803FFFFF803FFFFF803FFFFF003F",
INIT_3B => X"0000003FC000003FF000003FFC00003FFF00003FFF80003FFFE0003FFFF8003F",
INIT_3C => X"00000000000000000000003F0000003F0000003F0000003F0000003F0000003F",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized13\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized13\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized13\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"8800000000000000551111111111551111000000000000000000000000000000",
INITP_02 => X"0000005500000000000000088880000000000000000000000000880000880022",
INITP_03 => X"0880000880000880000000000000055000000000055000000000000000110000",
INITP_04 => X"0000000000000000000440000000000000001100000000001100000000000000",
INITP_05 => X"0000000002222AA0000880000880000000000000001111111111111111110000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"00007F0000007F00000000000000000000000000000000000000000000000000",
INIT_0C => X"1E3C07001E3C07001E3C07001E3C07001FF007001FF007000000070000000700",
INIT_0D => X"1FF07FF01FF07FF01E3C07001E3C07001E3C07001E3C07001E3C07001E3C0700",
INIT_0E => X"00000000000000001E0000001E0000001E0000001E0000001E0000001E000000",
INIT_0F => X"F83C7803F83C78030000000F0000000F0000000F0000000F0000000000000000",
INIT_10 => X"003C0000003C0000FE3C0000FE3C00001E3F00001E3F00001E3CF80F1E3CF80F",
INIT_11 => X"00000000000000000000000000000000F83C0000F83C0000003C0000003C0000",
INIT_12 => X"000000F000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"000000F0000000F0000000F0000000F0000000F0000000F0000000F0000000F0",
INIT_14 => X"F80000FFF80000F0F80000F0000000F0000000F0000000F0000000F0000000F0",
INIT_15 => X"00000000000000000000000000000000000000000000000000000000F80000FF",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"1ECF78F01ECF78F01ECF78F01ECF78F01ECF78F01ECF78F01FFC1FC01FFC1FC0",
INIT_18 => X"00000000000000001E0F1FC01E0F1FC01ECF78F01ECF78F01ECF78F01ECF78F0",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"1E3C78F007F01FC007F01FC00000000000000000000000000000000000000000",
INIT_1B => X"1E3C78F01E3C78001E3C78001E3C78001E3C78001E3C78001E3C78001E3C78F0",
INIT_1C => X"000000000000000000000000000000000000000007F01FC007F01FC01E3C78F0",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"F800003F00000000000000000000000000000000FE00003FFE00003F00000000",
INIT_1F => X"00000000F800003FF800003F1E0000F01E0000F01E0000F01E0000F0F800003F",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"00007FC000007FC0000000000000000000000000000000000000000000000000",
INIT_22 => X"000078F0000078F0000078F0000078F0000078F0000078F0000078F0000078F0",
INIT_23 => X"0000780000007800000078000000780000007FC000007FC0000078F0000078F0",
INIT_24 => X"0000000000000000000000000000000000000000000000000000780000007800",
INIT_25 => X"1E3C00001E3C00001E3C00001FF000001FF00000000000000000000000000000",
INIT_26 => X"1E3C00001E3C00001E3C00001E3C00001E3C00001E3C00001E3C00001E3C0000",
INIT_27 => X"000000000000000000000000000000000000000000000000000000001E3C0000",
INIT_28 => X"000007000000070000007F0000007F0000000000000000000000000000000000",
INIT_29 => X"0000070000000700000007000000070000000700000007000000070000000700",
INIT_2A => X"000000000000000000007FF000007FF000000700000007000000070000000700",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"1E3C78F0F83C783FF83C783F0000000000000000000000000000000000000000",
INIT_2D => X"1E3C78F01E3C78F01E3C78F0FE3C78FFFE3C78FF1E3C78F01E3C78F01E3C78F0",
INIT_2E => X"00FF000000038000000380000000E0000000E000FE0FE03FFE0FE03F1E3C78F0",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000FF0000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000007F0000007E0000007C0000004000000000000000000000000000000000",
INIT_39 => X"0000007F0000007F0000007F0000007F0000007F0000007F0000007F0000007F",
INIT_3A => X"0000007F0000007F0000007F0000007F0000007F0000007F0000007F0000007F",
INIT_3B => X"0000007F0000007F0000007F0000007F0000007F0000007F0000007F0000007F",
INIT_3C => X"0000000000000000000000000000000000000000000000400000007C0000007F",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized14\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized14\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized14\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"6600000000000000664400001122666600000000000000000000000000000000",
INITP_02 => X"EEEEEEEE000000000000000662222333333EE00000000022222266BBBBFFFFFF",
INITP_03 => X"077BBBBFFFFFF660000000000000099999999999999888800000000000AAEEEE",
INITP_04 => X"0000000999999990000990000000000000009999999900009900000000000000",
INITP_05 => X"0000000888888FFCCCCCCCCCCCC0022000000000007777777777775544440000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"00FF000000FF0000000000000000000000000000000000000000000000000000",
INIT_0C => X"000F07FF000F07FF000380000003800001C3800001C3800001C3800001C38000",
INIT_0D => X"01FF800001FF800001C0000001C0000000F0000000F00000003C0000003C0000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"7F03FE037F03FE03000000000000000000000000000000000000000000000000",
INIT_10 => X"E003870FE003870FFFC3870FFFC3870FE1C3870FE1C3870FE1C3870FE1C3870F",
INIT_11 => X"000380000003800000038000000380007F03FE037F03FE03E003870FE003870F",
INIT_12 => X"7800000000000000000000000000000000000000000000000003800000038000",
INIT_13 => X"780387007803870078038700FFC0FE00FFC0FE00780000007800000078000000",
INIT_14 => X"1FC0FE00780380007803800078038000780380007803FF007803FF0078038700",
INIT_15 => X"000000000000000000000000000000000000000000000000000000001FC0FE00",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"E1C38000E1C38000E1C38000E1C38000E1C38000E1C3800081C3800081C38000",
INIT_18 => X"000000000000000080FF800080FF8000E1C38000E1C38000E1C38000E1C38000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"8000070F800001FC800001FC8000000080000000800000008000000000000000",
INIT_1B => X"8000070F8000070080000700800007008000070080000700800007008000070F",
INIT_1C => X"0000000000000000000000000000000000000000800001FC800001FC8000070F",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"FFC38703E1C3870FE1C3870FE1C3870FE1C3870F7F03FE037F03FE0300000000",
INIT_1F => X"000000007F03870F7F03870FE0038700E0038700E0038700E0038700FFC38703",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"E00001FCE00001FC000000000000000000000000000000000000000000000000",
INIT_22 => X"E000070FE000070F800001FF800001FF0000000F0000000F0000000F0000000F",
INIT_23 => X"00000000000000000000000000000000800001FF800001FFE000070FE000070F",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000F0000000F0000000FE00001FCE00001FC000000000000000000000000",
INIT_26 => X"800001FFE000070FE000070FE000070FE000070F800001FF800001FF0000000F",
INIT_27 => X"00000000000000000000000000000000000000000000000000000000800001FF",
INIT_28 => X"01C0000001C0000001C0000001C0000000000000000000000000000000000000",
INIT_29 => X"01C387FF01C387FF01C3870F01C3870F01C3870F01C3870F01FF01FC01FF01FC",
INIT_2A => X"000000000000000001C381FC01C381FC01C3870001C3870001C3870001C38700",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"E1C07800FF007803FF00780300007800000078000003F8000003F80000000000",
INIT_2D => X"E1C0780FE1C0780FE1C0780FE1C07803E1C07803E1C07800E1C07800E1C07800",
INIT_2E => X"E0000000E0000000E0000000E0000000E0000000FF03FF03FF03FF03E1C0780F",
INIT_2F => X"00000000000000000000000000000000000000000000000000000000E0000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized15\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized15\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized15\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized15\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"1100000000000000220000220000220000000000000000000000000000000000",
INITP_02 => X"0000000000000000044000055000011000055000000000000000554400110000",
INITP_03 => X"0550000000000550000000000000022000022220000002200000002222220000",
INITP_04 => X"0000000880000880000AA000000000000000AA0000880000AA00000000000000",
INITP_05 => X"0000000000000444444444444444444000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"00007800000078000000780000007800000FE000000FE0000000000000000000",
INIT_0D => X"000FF800000FF800003C7800003C7800003C7800003C7800000FF800000FF800",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"1E0F1FC01E0F1FC0000000000000000000000000000000000000000000000000",
INIT_10 => X"1ECF78001ECF78001ECF7FF01ECF7FF01ECF78F01ECF78F01ECF78F01ECF78F0",
INIT_11 => X"00000000000000000000000000000000073C1FC0073C1FC0073C7800073C7800",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"1E3C00F01E3C00F01E3C00F007FC1FC007FC1FC0000000000000000000000000",
INIT_14 => X"07FC1FF01E3C78F01E3C78F01E3C78F01E3C78F01E3C1FF01E3C1FF01E3C00F0",
INIT_15 => X"000000001FF000001FF00000003C0000003C0000003C0000003C000007FC1FF0",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"003C78F0003C78F0003C78F0003C78F0003C78F0003C78F0003C783F003C783F",
INIT_18 => X"0000E0000000E000000FE03F000FE03F003C78F0003C78F0003C78F0003C78F0",
INIT_19 => X"0000000000000000000000000000000000FF000000FF00000003800000038000",
INIT_1A => X"003F7803003C78FF003C78FF003C780F003C780F000FE003000FE00300000000",
INIT_1B => X"003C7803003C7803003C7803003CF803003CF803000FE003000FE003003F7803",
INIT_1C => X"0000000000000000000000000000000000000000000FE003000FE003003C7803",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"1E3C78F01E3C78F01E3C78F01E3C78F01E3C78F007F07FC007F07FC000000000",
INIT_1F => X"0000780007F07FC007F07FC01E3C78F01E3C78F01E3C78F01E3C78F01E3C78F0",
INIT_20 => X"0000000000000000000000000000780000007800000078000000780000007800",
INIT_21 => X"F83FF83FF83FF83F000F0000000F0000000F0000000F00000000000000000000",
INIT_22 => X"000F0000000F0000FE0F003FFE0F003F1E0F00F01E0F00F01E0F00F01E0F00F0",
INIT_23 => X"00000000000000000000000000000000F803F8FFF803F8FF000F0000000F0000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"1E3C78F01E3C78F01E3C78F0F83FE03FF83FE03F000000000000000000000000",
INIT_26 => X"F83C78FF003C7800003C7800003C7800003C7800FE3C783FFE3C783F1E3C78F0",
INIT_27 => X"00000000000000000000000000000000000000000000000000000000F83C78FF",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"070000001FFC00001FFC00000700000007000000070000000700000000000000",
INIT_2D => X"0700000007000000070000000700000007000000070000000700000007000000",
INIT_2E => X"000000000000000000000000000000000000000001FC000001FC000007000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized16\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized16\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized16\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized16\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"9900000000000000EE1111222222BB0000000000000000000000000000000000",
INITP_02 => X"EEEEEE770000000000000009988EEEEEEEEFF00000000000000099CCCCFFFFFF",
INITP_03 => X"0CC4444CCCCEEEE00000000000000AAAAAABBBBFFEE000000000000000669999",
INITP_04 => X"022222266FFFFFFFFFF660000000002211113333333333333300000000000000",
INITP_05 => X"0000000000000DD4444555577770000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"1E0000001E0000001E0000001E00000000000000000000000000000000000000",
INIT_0C => X"1E0380001E0380001E0380001E038000FE00FF00FE00FF000000000000000000",
INIT_0D => X"FFC3FE00FFC3FE001E0007001E0007001E0007001E0007001E00FE001E00FE00",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"80FF01FF80FF01FF000000000000000000000000000000000000000000000000",
INIT_10 => X"E1C0000FE1C0000FE1FF81FCE1FF81FCE1C38700E1C38700E1C38700E1C38700",
INIT_11 => X"00000000000000000000000000000000E0FF07FCE0FF07FCE1C0000FE1C0000F",
INIT_12 => X"000000F0000000F0000000F00000000000000000000000000000000000000000",
INIT_13 => X"E1C380F0E1C380F0E1C380F081C387F081C387F00000000000000000000000F0",
INIT_14 => X"E03C07FFE0FF00F0E0FF00F0E1C380F0E1C380F0E1C380F0E1C380F0E1C380F0",
INIT_15 => X"00000000000000000000000000000000000000000000000000000000E03C07FF",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"FFC0FE00FFC0FE00E1C38000E1C38000E1C38000E1C380007F00FF007F00FF00",
INIT_18 => X"00000000000000007F03FE007F03FE00E0000700E0000700E0000700E0000700",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"E7C38700E1C0FE00E1C0FE000000000000000000000000000000000000000000",
INIT_1B => X"E0038000E0038000E0038000E003FF00E003FF00F8038700F8038700E7C38700",
INIT_1C => X"0000000000000000000000000000000000000000E000FE00E000FE00E0038000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"E1C00000E1F00000E1F00000E1CF8000E1CF800081C3800081C3800000000000",
INIT_1F => X"0000000081C0000081C0000001C0000001C0000001C0000001C00000E1C00000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000FF030000FF03000000000000000000000000000000000000000000000000",
INIT_22 => X"0003870F0003870F0003870F0003870F0003870F0003870F0003870F0003870F",
INIT_23 => X"000007000000070000000700000007000000FF030000FF030003870F0003870F",
INIT_24 => X"0000000000000000000000000000000000000000000000000003FE000003FE00",
INIT_25 => X"E1C3870FE1C3870FE1C3870F7F03FE037F03FE03000000000000000000000000",
INIT_26 => X"7F03FE03E1C3870FE1C3870FE1C3870FE1C3870FE1C3870FE1C3870FE1C3870F",
INIT_27 => X"000000000003800000038000000380000003800000038000000380007F03FE03",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"01CF870001C381FF01C381FF0000000000000000000000000000000000000000",
INIT_2D => X"01C0000F01C0000F01C0000F01C001FC01C001FC01F0070001F0070001CF8700",
INIT_2E => X"0000000000000000000000000000000000000000E1C007FCE1C007FC01C0000F",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized17\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized17\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized17\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized17\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"EE44662200000000440000440000440000000000000000000000000000000000",
INITP_02 => X"DD99884400000000000000000000000000022000000000000000666666666666",
INITP_03 => X"2AA0000880000880000000000000011000011000011000000000000000CC8899",
INITP_04 => X"0000000440000440000440000000000000001100001100005500000000000222",
INITP_05 => X"0000000000000000000002200000022000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"1E0000001E0000001E0000001E00000007FC000007FC00000000000000000000",
INIT_0D => X"1FF000001FF00000003C0000003C0000003C0000003C000007F0000007F00000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"9F3F80FF9F3F80FF070000000700000007038000070380000003800000038000",
INIT_10 => X"070380F0070380F0670380F0670380F0670380F0670380F0670380F0670380F0",
INIT_11 => X"00000000000000000000000000000000073FF8F0073FF8F0070380F0070380F0",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"003C7800003C7800003C7800003FE03F003FE03F000000000000000000000000",
INIT_14 => X"003C783F003C78F0003C78F0003C78F0003C78F0003C783F003C783F003C7800",
INIT_15 => X"00000000000000000000000000000000000000000000000000000000003C783F",
INIT_16 => X"0000780000007800000078000000780000000000000000000000000000000000",
INIT_17 => X"87FC7F0087FC7F00803C79C0803C79C0803C78F0803C78F007F078F007F078F0",
INIT_18 => X"000000000000000087FC78F087FC78F09E3C78F09E3C78F09E3C79C09E3C79C0",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"000000F000001FC000001FC00000000000000000000000000000000000000000",
INIT_1B => X"000078F0000078F0000078F000001FF000001FF0000000F0000000F0000000F0",
INIT_1C => X"000000000000000000000000000000000000000000001FF000001FF0000078F0",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"FE3C78FF1E3C78F01E3C78F01E3C78F01E3C78F0F83C783FF83C783F00000000",
INIT_1F => X"0000E000FE0FE03FFE0FE03F1E3C78F01E3C78F01E3C78F01E3C78F0FE3C78FF",
INIT_20 => X"00000000000000000000000000FF000000FF000000038000000380000000E000",
INIT_21 => X"1FF01FC01FF01FC01E0000001E0000001E0000001E0000000000000000000000",
INIT_22 => X"1E3C78001E3C78001E3C7FF01E3C7FF01E3C78F01E3C78F01E3C78F01E3C78F0",
INIT_23 => X"000000000000000000000000000000001E3C1FC01E3C1FC01E3C78001E3C7800",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"1E3C00001E3C00001E3C000007F0000007F00000000000000000000000000000",
INIT_26 => X"07F000001E0000001E0000001E0000001E0000001FFC00001FFC00001E3C0000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000007F00000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000F00000000000000000000000000000000000000000000000000000000",
INIT_2C => X"000F000F000F00FF000F00FF000F0000000F00000003F80F0003F80F0000000F",
INIT_2D => X"000F000F000F000F000F000F000F000F000F000F003FF80F003FF80F000F000F",
INIT_2E => X"0000000000000000000000000000000000000000000F00FF000F00FF000F000F",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized18\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized18\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized18\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized18\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000007766666666665544CC000000000000000000000000000000",
INITP_02 => X"11111111000000000000000663333333333EE000000000000000000000000000",
INITP_03 => X"8FFCCCCCCCCCCCC00220000000000DD5555DDDDFFFF000000000000000111111",
INITP_04 => X"0000000111111119911111199000000000000000000000000000000000088888",
INITP_05 => X"0000000000000EEEEEEFFFFFFEE8888000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"E1C000F0E1C000F0000000F0000000F000000000000000000000000000000000",
INIT_0C => X"01C380F001C380F001C380F001C380F001FF07F001FF07F001C0000001C00000",
INIT_0D => X"01C387FF01C387FF01C380F001C380F001C380F001C380F001C380F001C380F0",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"00007E0F00007E0F0000780F0000780F00001E0F00001E0F0000000000000000",
INIT_10 => X"0000000F0000000F0000000F0000000F0000000F0000000F00007E0F00007E0F",
INIT_11 => X"000000000000000000000000000000000000000F0000000F0000000F0000000F",
INIT_12 => X"7800000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"780387007803870078038700FFC0FE00FFC0FE00780000007800000078000000",
INIT_14 => X"1FC0FE0078038700780387007803870078038700780387007803870078038700",
INIT_15 => X"000000000000000000000000000000000000000000000000000000001FC0FE00",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"000007330000073300000733000007330000073300000733000007FF000007FF",
INIT_18 => X"0000000000000000000007030000070300000733000007330000073300000733",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"E1CF870F81C381FC81C381FC0000000000000000000000000000000000000000",
INIT_1B => X"01C0070001C0070001C00700E1C007FFE1C007FFE1F0070FE1F0070FE1CF870F",
INIT_1C => X"000000000000000000000000000000000000000081C001FC81C001FC01C00700",
INIT_1D => X"000078000003F8000003F8000000000000000000000000000000000000000000",
INIT_1E => X"E1C07803E1C07800E1C07800E1C07800E1C07800FF007803FF00780300007800",
INIT_1F => X"E0000000FF03FF03FF03FF03E1C0780FE1C0780FE1C0780FE1C0780FE1C07803",
INIT_20 => X"000000000000000000000000E0000000E0000000E0000000E0000000E0000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"E000070000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"E000070F0000070F0000070F000007FC000007FC0000070000000700E0000700",
INIT_26 => X"0000070F0000070F0000070F0000070F0000070F0000070F0000070FE000070F",
INIT_27 => X"000000000000000000000000000000000000000000000000000000000000070F",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"E1C38700FF00FE00FF00FE00E0000000E0000000E0000000E000000000000000",
INIT_2D => X"E1C38000E1C38000E1C38000E1C3FF00E1C3FF00E1C38700E1C38700E1C38700",
INIT_2E => X"0000000000000000000000000000000000000000E1C0FE00E1C0FE00E1C38000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized19\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized19\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized19\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized19\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"00000000000000000000000000000888888888888AA888800000000000000000",
INITP_04 => X"0000000222222222222222222000000000000000000000000000000000000000",
INITP_05 => X"0000000000000111111111111111111000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"000000FF000000FF000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000F0000000F0000000F0000000F0000000F0000000F0000000F0000000F",
INIT_0D => X"0000000F0000000F0000000F0000000F0000000F0000000F0000000F0000000F",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"E03C78F0E03FE03FE03FE03FE03C0000E03C0000FE3C0000FE3C000000000000",
INIT_1B => X"E03C78F0E03C78F0E03C78F0E03C78FFE03C78FFE03C78F0E03C78F0E03C78F0",
INIT_1C => X"0000000000000000000000000000000000000000E03C783FE03C783FE03C78F0",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"000FE00F00000000000000000000000000000000000000000000000000000000",
INIT_25 => X"000380FF0003803C0003803C0003803C0003803C0003803C0003803C000FE00F",
INIT_26 => X"000FE03C0003803C0003803C0003803C0003803C0003803C0003803C000380FF",
INIT_27 => X"00000000000000000000000000000000000000000000000000000000000FE03C",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"000007000000070000000700000007000000070000007FF000007FF000000000",
INIT_2D => X"0000070000000700000007000000070000000700000007000000070000000700",
INIT_2E => X"0000000000000000000000000000000000000000000007000000070000000700",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000004444666666880000000000000000000000000000000000",
INITP_02 => X"00000000000000000000000CC444444888844000000000000000000000000000",
INITP_03 => X"444440000000000000000000000008800000066000000AA00000000000000000",
INITP_04 => X"0000000884444666666000000000000000000000000000000000000000000004",
INITP_05 => X"0000000000000CC44444488AA662200000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"79C3800079C3800079C3800079C38000E0FF0000E0FF00000000000000000000",
INIT_0D => X"78FF000078FF000079C0000079C0000079C0000079C0000079FF800079FF8000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"E0000000E0000000E00000007FC000007FC00000000000000000000000000000",
INIT_14 => X"FF00000001C0000001C0000001C0000001C000007F0000007F000000E0000000",
INIT_15 => X"00000000000000000000000000000000000000000000000000000000FF000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"00F0000000F0000000F0000000F0000000F00000803F8000803F800000000000",
INIT_1B => X"00F0000000F0000000F0000000F0000000F0000001FF800001FF800000F00000",
INIT_1C => X"000000000000000000000000000000000000000080F0000080F0000000F00000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"070000001F0000001F0000001F0000001F000000000000000000000000000000",
INIT_20 => X"00000000000000000000000000000000000000001E0000001E00000007000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"01C3800001C3800001C3800000FF000000FF0000000000000000000000000000",
INIT_26 => X"E0FF00FC01C000FC01C000FC01C0000001C0000001FF800001FF800001C38000",
INIT_27 => X"000000000000000000000000000000F0000000F00000003C0000003CE0FF00FC",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"E000FE007FC0FE007FC0FE000000FE000000FE00000078000000780000000000",
INIT_2D => X"01C0780001C0000001C000007F0078007F007800E0007800E0007800E000FE00",
INIT_2E => X"0000000000000000000000000000000000000000FF007800FF00780001C07800",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized20\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized20\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized20\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized20\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"00000000000000000000000000000000000000000000000F0000000F00000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized21\ is
port (
douta : out STD_LOGIC_VECTOR ( 25 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized21\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized21\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized21\ is
signal \n_12_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_20_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_21_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_28_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_4_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_5_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_69_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_71_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31) => \n_4_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(30) => \n_5_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(29 downto 24) => douta(25 downto 20),
DOADO(23) => \n_12_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(22 downto 16) => douta(19 downto 13),
DOADO(15) => \n_20_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(14) => \n_21_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(13 downto 8) => douta(12 downto 7),
DOADO(7) => \n_28_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(6 downto 0) => douta(6 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => \n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPADOP(2) => \n_69_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPADOP(1) => \n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPADOP(0) => \n_71_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"5500000000880000AA0000220000AA0000000000000000000000000000000000",
INITP_02 => X"0000008800000000000000011000011000055000000000000000110000110000",
INITP_03 => X"0440000000000550000000000000088880000000000000000000000000AA2200",
INITP_04 => X"0000000AAAAAAAAAAAAAA88AA220000000008888000000000000000000000000",
INITP_05 => X"00000000000004444CCCCCCCCDD0044440000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"1E0078F31E0078F31E0078F31E0078F3FE0FE0FFFE0FE0FF0000000000000000",
INIT_0D => X"FE0FF8F0FE0FF8F01E3C78F31E3C78F31E3C78F31E3C78F31E0FF8F31E0FF8F3",
INIT_0E => X"0000000000000000F8000000F80000001E0000001E0000001E0000001E000000",
INIT_0F => X"1FF01FF01FF01FF0000000000000000000000000000000000000000000000000",
INIT_10 => X"1E3C00F01E3C00F01E3C1FC01E3C1FC01E3C78001E3C78001E3C78001E3C7800",
INIT_11 => X"000000000000000000000000000000001E3C7FC01E3C7FC01E3C00F01E3C00F0",
INIT_12 => X"1E00000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"1E3C78F01E3C78F01E3C78F01FF01FC01FF01FC01E0000001E0000001E000000",
INIT_14 => X"1E3C1FC01E3C78001E3C78001E3C78001E3C78001E3C7FF01E3C7FF01E3C78F0",
INIT_15 => X"000000000000000000000000000000000000000000000000000000001E3C1FC0",
INIT_16 => X"1E0000001E0000001E0000001E00000000000000000000000000000000000000",
INIT_17 => X"1E0000001E0000001E0000001E0000001E0000001E000000FE000000FE000000",
INIT_18 => X"0000000000000000FE03E000FE03E0001E03E0001E03E0001E0000001E000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000F0000000F0000000F0000000F0000000F0000003F0000003F00000000",
INIT_1B => X"F800000F0000000F0000000F0000000F0000000F0000000F0000000F0000000F",
INIT_1C => X"0000000000000000000000000000000000000000F800003FF800003FF800000F",
INIT_1D => X"0000780000007800000078000000000000000000000000000000000000000000",
INIT_1E => X"1E0078F01E0078F01E0078F01E3C78F01E3C78F007F07FC007F07FC000007800",
INIT_1F => X"0000000007F078F007F078F01E3C78F01E3C78F01E0078F01E0078F01E0078F0",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"00000000000000000000000000000000F8000000F8000000F8000000F8000000",
INIT_24 => X"800380FF00038000000380000000000000000000000000000000000000000000",
INIT_25 => X"8003800F8003800F8003800FFE3F800FFE3F800F8000000F8000000F800380FF",
INIT_26 => X"FE3FF8FF8003800F8003800F8003800F8003800F8003800F8003800F8003800F",
INIT_27 => X"00000000000000000000000000000000000000000000000000000000FE3FF8FF",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"01C0000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"81C078F09FC07FC09FC07FC0000000000000000001C0000001C0000001C00000",
INIT_2D => X"01C078F081C078F081C078F081C078F081C078F081C078F081C078F081C078F0",
INIT_2E => X"00000000000000000000000000000000000000001FFC78F01FFC78F001C078F0",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"FF00000000000000448888CCCCCC440000000000000000000000000000000000",
INITP_02 => X"8888CCEE000000000000000BB111111111177000000000000000BB1111111111",
INITP_03 => X"01177777766EE9900000000000000FFFFFFFFFFFFFF111100000000000BB8888",
INITP_04 => X"000000044CCCCCCCCCC44444400000000000FF3333333333AA00000000000000",
INITP_05 => X"0000000000000999999991111990000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"E1C0000FE1C0000FE1C0000FE1C0000F7F0000037F0000030000000000000000",
INIT_0D => X"7F0000037F000003E000000FE000000FE000000FE000000FFFC0000FFFC0000F",
INIT_0E => X"00000000000000000000000F0000000F00000000000000000000000000000000",
INIT_0F => X"E1FF81FCE1FF81FC00F0000000F0000000F0000000F000000000000000000000",
INIT_10 => X"00F0070F00F0070F00F0070F00F0070F00F0070F00F0070F00F0070F00F0070F",
INIT_11 => X"00000000000000000000000000000000E03F81FCE03F81FC00F0070F00F0070F",
INIT_12 => X"00F0000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"00F0070000F0070F00F0070F01FF81FC01FF81FC00F0000000F0000000F00000",
INIT_14 => X"E03F81FC00F0070F00F0070F00F0070000F0070000F0070000F0070000F00700",
INIT_15 => X"00000000000000000000000000000000000000000000000000000000E03F81FC",
INIT_16 => X"0000000000000000000078000000780000007800000078000000000000000000",
INIT_17 => X"E000780FE000780FF800780FF800780FE7C0780FE7C0780FE1C3F803E1C3F803",
INIT_18 => X"0000000000000000E003FF03E003FF03E000780FE000780FE000780FE000780F",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"E1C38700FF00FF00FF00FF000000070000000700000007000000070000000000",
INIT_1B => X"E1C38700E1C38700E1C38700E1C38700E1C38700E1C38700E1C38700E1C38700",
INIT_1C => X"0000000000000000000000000000000000000000E1C0FF00E1C0FF00E1C38700",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"01C381FF01C3800F01C3800FE1C3800FE1C3800FE0FF01FCE0FF01FC00000000",
INIT_1F => X"0000000000FF01FF00FF01FF01C3870F01C3870F01C3870F01C3870F01C381FF",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"FE03FE00FE03FE0000000000000000001E0000001E0000001E0000001E000000",
INIT_22 => X"1E0387001E0387001E0387001E0387001E0387001E0387001E0387001E038700",
INIT_23 => X"00000000000000000000000000000000FFC38700FFC387001E0387001E038700",
INIT_24 => X"01C0000300000000000000000000000000000000000000000000000000000000",
INIT_25 => X"E1C00003E1C00003E1C000037FC0000F7FC0000F01C0000301C0000301C00003",
INIT_26 => X"7FC00000E1C00003E1C00003E1C00003E1C00003E1C00003E1C00003E1C00003",
INIT_27 => X"000000000000000000000000000000000000000000000000000000007FC00000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"00000733E0000703E00007030000000000000000000000000000000000000000",
INIT_2D => X"E00001CFE0000733E00007338000073380000733000007330000073300000733",
INIT_2E => X"0000000000000000000000000000000000000000800001CF800001CFE00001CF",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"8800000000000000444444444444554444000000000000000000000000000000",
INITP_02 => X"00000011000000000000000880022AA222288000000000000000AA0000000000",
INITP_03 => X"0880022222200880000000000000055000000000044000000000110000110000",
INITP_04 => X"0000000110000114400110000000004400005500001100005500000000000000",
INITP_05 => X"0000000000000220000000000AA0000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0700780007007800000000000000000000000000000000000000000000000000",
INIT_0C => X"070078F0070078F0070078F0070078F01FFC7FC01FFC7FC00700780007007800",
INIT_0D => X"01FC78F001FC78F0070078F0070078F0070078F0070078F0070078F0070078F0",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"F83C78FFF83C78FF0000003C0000003C0000003C0000003C0000000000000000",
INIT_10 => X"1E3C783C1E3C783C1E3C783C1E3C783C1E3C783C1E3C783C1E3C783C1E3C783C",
INIT_11 => X"00000000000000000000000000000000F80FF80FF80FF80F1E3C783C1E3C783C",
INIT_12 => X"0000000F0000000F0000000F0000000000000000000000000000000000000000",
INIT_13 => X"003C9E0F003C9E0F003C9E0FFE3C1EFFFE3C1EFF00000000000000000000000F",
INIT_14 => X"F80F78FF1E0F780F1E0F780F1E3C9E0F1E3C9E0FF83C9E0FF83C9E0F003C9E0F",
INIT_15 => X"00000000000000000000000000000000000000000000000000000000F80F78FF",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"000078F0000078F0000078F0000078F0000078F0000078F000001FF000001FF0",
INIT_18 => X"000000F0000000F000001FF000001FF0000078F0000078F0000078F0000078F0",
INIT_19 => X"0000000000000000000000000000000000007FC000007FC0000000F0000000F0",
INIT_1A => X"1E3C78F007F078F007F078F00000000000000000000000000000000000000000",
INIT_1B => X"1E3C78F01E3C78F01E3C78F01E3C78F01E3C78F01E3C78F01E3C78F01E3C78F0",
INIT_1C => X"000000000000000000000000000000000000000007F01FF007F01FF01E3C78F0",
INIT_1D => X"003C0000003C0000003C00000000000000000000000000000000000000000000",
INIT_1E => X"003F80F0003CE0FC003CE0FC1E3C78F31E3C78F3F83C78F0F83C78F0003C0000",
INIT_1F => X"00000000F83C78F0F83C78F01E3C78F01E3C78F0003CE0F0003CE0F0003F80F0",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"07FC1FC007FC1FC0000000000000000000000000000000000000000000000000",
INIT_22 => X"1E3C78F01E3C78F01E3C1FF01E3C1FF01E3C00F01E3C00F01E3C00F01E3C00F0",
INIT_23 => X"003C0000003C0000003C0000003C000007FC1FF007FC1FF01E3C78F01E3C78F0",
INIT_24 => X"0000000000000000000000000000000000000000000000001FF000001FF00000",
INIT_25 => X"1F0078F01EFC78F01EFC78F01E3C1FC01E3C1FC0000000000000000000000000",
INIT_26 => X"1E001FC01E0078001E0078001E0078001E0078001E007FF01E007FF01F0078F0",
INIT_27 => X"000000000000000000000000000000000000000000000000000000001E001FC0",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"1E0F00F0F83FF83FF83FF83F000F0000000F0000000F0000000F000000000000",
INIT_2D => X"1E0F00001E0F00001E0F00001E0F003F1E0F003F1E0F00F01E0F00F01E0F00F0",
INIT_2E => X"00000000000000000000000000000000000000001E03F8FF1E03F8FF1E0F0000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"CC8888000000000088888888EE88880022000000000000000000000000000000",
INITP_02 => X"777777DD44440000000000088888888CCCCCCCCCC00000000000CCCCCCCCCCCC",
INITP_03 => X"066FFBBBBBBFF660000000000000099111199999999110000000000000FF7777",
INITP_04 => X"0000000557777777777DD4444000000000009999999900009900000000000000",
INITP_05 => X"000000000000077CCCCCCCCCC660000000000000008888000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"003F8000003F8000000000000000000000000000000000000000000000000000",
INIT_0C => X"E1FF8000E1FF8000E0F00000E0F0000080F0000080F0000000F0000000F00000",
INIT_0D => X"80F0000080F00000E0F00000E0F00000E0F00000E0F00000E0F00000E0F00000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"FF00000FFF00000FE000000FE000000FE000000FE000000F0000000000000000",
INIT_10 => X"E1C0000FE1C0000FE1C0000FE1C0000FE1C0000FE1C0000FE1C0000FE1C0000F",
INIT_11 => X"00000000000000000000000000000000E1C0000FE1C0000FE1C0000FE1C0000F",
INIT_12 => X"FF00000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"FF00000FE1C0000FE1C0000FE1C00003E1C00003E1C00000E1C00000FF000000",
INIT_14 => X"E000000FE0000000E0000000E0000000E0000000E0000003E0000003FF00000F",
INIT_15 => X"00000000000000000000000000000000000000000000000000000000E000000F",
INIT_16 => X"01C0000001C0000001C0000001C0000000000000000000000000000000000000",
INIT_17 => X"01C387FF01C387FF01C3870F01C3870F01C3870F01C3870FE1FF01FCE1FF01FC",
INIT_18 => X"0000000000000000E1C381FCE1C381FC01C3870001C3870001C3870001C38700",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"E00001C0800001C0800001C0000001C0000001C0000000FF000000FF00000000",
INIT_1B => X"000001C0000001C0000001C0E00001C0E00001C0E00007FFE00007FFE00001C0",
INIT_1C => X"0000000000000000000000000000000000000000800001C0800001C0000001C0",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"E003870FE003870FE003870FE1C3870FE1C3870F7F00FE037F00FE0300000000",
INIT_1F => X"000000007F00FE037F00FE03E1C3870FE1C3870FE003870FE003870FE003870F",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"E00001FCE00001FC000000000000000000000000000000000000000000000000",
INIT_22 => X"E000070FE000070F800001FF800001FF0000000F0000000F0000000F0000000F",
INIT_23 => X"00000000000000000000000000000000800001FF800001FFE000070FE000070F",
INIT_24 => X"01C0000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"79C3870F79C3870F79C3870FE1FF01FCE1FF01FC01C0000001C0000001C00000",
INIT_26 => X"79FF01FC79C3870079C3870079C3870079C3870079C387FF79C387FF79C3870F",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000079FF01FC",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000800000008000000080000000800000000000000000000000",
INIT_2B => X"0000780000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"E1C0780F7F03F80F7F03F80F0000000000000000000078000000780000007800",
INIT_2D => X"E1C0780FE1C0780FE1C0780FE1C0780FE1C0780FE1C0780FE1C0780FE1C0780F",
INIT_2E => X"00000000000000000000000000000000000000007F03FF0F7F03FF0FE1C0780F",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized7\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized7\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized7\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"1100000000000000000000000000880000000000000000000000000000000000",
INITP_02 => X"0000008800000000000000055111111111111115500000000000550000110000",
INITP_03 => X"0440000440000440000000000000022000000000022000000000000000000000",
INITP_04 => X"000000022000000000088000000000002222AA00008800008800000000000000",
INITP_05 => X"0000000000000110000000000110000000000000000000000088002200000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"1E0000F01E0000F01E0000F01E0000F0F800003FF800003F0000000000000000",
INIT_0D => X"1E00003F1E00003F1E0000F01E0000F01E0000F01E0000F01E0000F01E0000F0",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"1E3C1FF01E3C1FF0000000000000000000000000000000000000000000000000",
INIT_10 => X"1E3C00F01E3C00F01E3C1FC01E3C1FC01E3C78001E3C78001E3C78001E3C7800",
INIT_11 => X"0000000000000000000000000000000007FC7FC007FC7FC01E3C00F01E3C00F0",
INIT_12 => X"1FC01FC000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"1E3C07001E3C07001E3C07001E3C07001E3C07001EF007001EF007001FC01FC0",
INIT_14 => X"1FC01FC01EF007001EF007001E3C07001E3C07001E3C07001E3C07001E3C0700",
INIT_15 => X"000000000000000000000000000000000000000000000000000000001FC01FC0",
INIT_16 => X"0000003C0000003C0000003C0000003C00000000000000000000000000000000",
INIT_17 => X"1E00003C1E00003C1E00003C1E00003C1E00003C1E00003CF80000FFF80000FF",
INIT_18 => X"00000000000000001E00000F1E00000F1E00003C1E00003C1E00003C1E00003C",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"003C78F0003FE03F003FE03F003C0000003C0000003C0000003C000000000000",
INIT_1B => X"003C78F0003C78F0003C78F0003C78FF003C78FF003C78F0003C78F0003C78F0",
INIT_1C => X"0000000000000000000000000000000000000000003FE03F003FE03F003C78F0",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"07FC0000003C0000003C0000003C0000003C000007F0000007F0000000000000",
INIT_1F => X"0000000007FC000007FC00001E3C00001E3C00001E3C00001E3C000007FC0000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"F83C783FF83C783F000000000000000000000000000000000000000000000000",
INIT_22 => X"1E3C78001E3C7800FE3C783FFE3C783F1E3C78F01E3C78F01E3C78F01E3C78F0",
INIT_23 => X"00038000000380000000E0000000E000FE0FE0FFFE0FE0FF1E3C78001E3C7800",
INIT_24 => X"00000000000000000000000000000000000000000000000000FF000000FF0000",
INIT_25 => X"1E3C78F31E3C78F31E3C78F3F83C78FFF83C78FF000000000000000000000000",
INIT_26 => X"1E0FF8F01E3C78F31E3C78F31E3C78F31E3C78F31E3C78F31E3C78F31E3C78F3",
INIT_27 => X"000000000000000000000000000000000000000000000000000000001E0FF8F0",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"003C7800003C7800803C7800803C78007E3C78007E3C78001E3FE0001E3FE000",
INIT_2A => X"0000000000000000003C780F003C780F003C780F003C780F003C7800003C7800",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"000078F000007FC000007FC00000000000000000000000000000000000000000",
INIT_2D => X"000078F0000078F0000078F0000078F0000078F0000078F0000078F0000078F0",
INIT_2E => X"000078000000780000007800000078000000780000007FC000007FC0000078F0",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000007800",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized8\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized8\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized8\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"9900000000000000EE3333333333AA0000000000000000000000000000000000",
INITP_02 => X"0000002200000000000000088CCCCEEEEEE88000000000111111991111999999",
INITP_03 => X"0EE6666666666CC44440000000000663333333333EE000000000000000330000",
INITP_04 => X"000000044CCCC44444444000000000888888FFCCCCCCCCCCCC00220000000000",
INITP_05 => X"000000000000022226666222233000000000000000773333333333FF00000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"1E0000001E0000001E0000001E00000000000000000000000000000000000000",
INIT_0C => X"1E03870F1E03870F1E03870F1E03870FFE00FE0FFE00FE0F0000000000000000",
INIT_0D => X"FFC0FE0FFFC0FE0F1E03870F1E03870F1E03870F1E03870F1E03870F1E03870F",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"800007FC800007FC000000000000000000000000000000000000000000000000",
INIT_10 => X"0000070F0000070FE000070FE000070FE000070FE000070FE000070FE000070F",
INIT_11 => X"00000700000007000000070000000700800007FC800007FC0000070F0000070F",
INIT_12 => X"0000000000000000000000000000000000000000000000000000070000000700",
INIT_13 => X"E1C38000E1C38000E1C3800080FF000080FF0000000000000000000000000000",
INIT_14 => X"E0FF0000E1C00000E1C00000E1C00000E1C00000E1FF8000E1FF8000E1C38000",
INIT_15 => X"00000000000000000000000000000000000000000000000000000000E0FF0000",
INIT_16 => X"0000000000000000000078000000780000007800000078000000000000000000",
INIT_17 => X"0000780F0000780F0000780F0000780F0000780F0000780F0003F80F0003F80F",
INIT_18 => X"00000000000000000003FF0F0003FF0F0000780F0000780F0000780F0000780F",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"78038700FFC0FE00FFC0FE007800000078000000780000007800000000000000",
INIT_1B => X"7803870078038700780387007803870078038700780387007803870078038700",
INIT_1C => X"00000000000000000000000000000000000000001FC0FE001FC0FE0078038700",
INIT_1D => X"01C0000001C0000001C000000000000000000000000000000000000000000000",
INIT_1E => X"01C3800001C3800001C3800001C3800001C38000E1FF0000E1FF000001C00000",
INIT_1F => X"00000000E1C38000E1C3800001C3800001C3800001C3800001C3800001C38000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"FF007803FF00780300007800000078000003F8000003F8000000000000000000",
INIT_22 => X"E1C0780FE1C0780FE1C07803E1C07803E1C07800E1C07800E1C07800E1C07800",
INIT_23 => X"E0000000E0000000E0000000E0000000FF03FF03FF03FF03E1C0780FE1C0780F",
INIT_24 => X"000000000000000000000000000000000000000000000000E0000000E0000000",
INIT_25 => X"01C0000F01C0000F01C0000F7F00000F7F00000F000000000000000000000000",
INIT_26 => X"7FC0000FE1C0000FE1C0000FE1C0000FE1C0000F7FC0000F7FC0000F01C0000F",
INIT_27 => X"000000000000000000000000000000000000000000000000000000007FC0000F",
INIT_28 => X"7800000078000000780000007800000000000000000000000000000000000000",
INIT_29 => X"7803870F7803870F7803870F7803870F7803870F7803870FFFC3870FFFC3870F",
INIT_2A => X"00000000000000001FC0FF0F1FC0FF0F7803870F7803870F7803870F7803870F",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"00F3803C00F387FC00F387FC00F000FC00F000FC00F0003C00F0003C00000000",
INIT_2D => X"0003803C01FFE03C01FFE03C01C3803C01C3803C00F3803C00F3803C00F3803C",
INIT_2E => X"00000000000000000000000000000000000000000003803C0003803C0003803C",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_wrapper_init__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized9\ : entity is "blk_mem_gen_prim_wrapper_init";
end \Instructions_blk_mem_gen_prim_wrapper_init__parameterized9\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_wrapper_init__parameterized9\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"AA88880000000000110000114400110000000000000000000000000000000000",
INITP_02 => X"4400114400000000000000022000000000022000000000000000888888888888",
INITP_03 => X"0AAAA66666666660022220000000044000044000044000000000000000440000",
INITP_04 => X"0000000000000004400000000000000000004400000000004400000000000000",
INITP_05 => X"0000000000000AA0000880000AA0000000000000004400004400004400000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"00000000000000000000000000AAAAAAAABBBB333333333333BBBBAAAAAAAA00",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"1F0078001F0078001EFC78001EFC78001E3C1FF01E3C1FF00000000000000000",
INIT_0D => X"1E007FC01E007FC01E0000F01E0000F01E0000F01E0000F01E001FC01E001FC0",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"FE3FE03FFE3FE03F803C0000803C0000803C0000803C00000000000000000000",
INIT_10 => X"803C78F0803C78F0803C78FF803C78FF803C78F0803C78F0803C78F0803C78F0",
INIT_11 => X"00000000000000000000000000000000FE3C783FFE3C783F803C78F0803C78F0",
INIT_12 => X"000F00F000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"000F00F0000F00F0000F00F0003FF8FF003FF8FF000F00F0000F00F0000F00F0",
INIT_14 => X"0003F8F0000F00F0000F00F0000F00F0000F00F0000F00F0000F00F0000F00F0",
INIT_15 => X"000000000000000000000000000000000000000000000000000000000003F8F0",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"1FFC78001FFC78001E3C7E001E3C7E001E3C79F01E3C79F007F078F007F078F0",
INIT_18 => X"000000000000000007F0780007F078001E0078001E0078001E0078001E007800",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"1E00000007FC000007FC00000000000000000000000000000000000000000000",
INIT_1B => X"003C0000003C0000003C000007F0000007F000001E0000001E0000001E000000",
INIT_1C => X"00000000000000000000000000000000000000001FF000001FF00000003C0000",
INIT_1D => X"0000003C0003803C0003803C0003800000038000000000000000000000000000",
INIT_1E => X"6703803C6703803C6703803C6703803C6703803C073F80FF073F80FF0000003C",
INIT_1F => X"000000009E3FF80F9E3FF80F9E03803C9E03803C6703803C6703803C6703803C",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"07FC000007FC0000003C0000003C0000003C0000003C00000000000000000000",
INIT_22 => X"1E3C00001E3C00001E3C00001E3C00001E3C00001E3C00001E3C00001E3C0000",
INIT_23 => X"0000000000000000000000000000000007FC000007FC00001E3C00001E3C0000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"1F0000001EFC00001EFC00001E3C00001E3C0000000000000000000000000000",
INIT_26 => X"1E0000001E0000001E0000001E0000001E0000001E0000001E0000001F000000",
INIT_27 => X"000000000000000000000000000000000000000000000000000000001E000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"07F0000007F000001E0000001E0000001E0000001E00000007FC000007FC0000",
INIT_2A => X"00000000000000001FF000001FF00000003C0000003C0000003C0000003C0000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"1E0F0000F83FF800F83FF800000F0000000F0000000F0000000F000000000000",
INIT_2D => X"000F0000000F0000000F0000FE0F0000FE0F00001E0F00001E0F00001E0F0000",
INIT_2E => X"0000000000000000000000000000000000000000F803F800F803F800000F0000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"F83F80FFF83F80FF803F80FF803F80FF803F80FF803F80FF0000000000000000",
INIT_39 => X"003F87F0003F87F0F83F87F0F83F87F0F83F87F0F83F87F0F83F80FFF83F80FF",
INIT_3A => X"003F87F0003F87F0003FFF00003FFF00003FFF00003FFF00003F87F0003F87F0",
INIT_3B => X"F83F80FFF83F80FFF83F87F0F83F87F0F83F87F0F83F87F0003F87F0003F87F0",
INIT_3C => X"0000000000000000803F80FF803F80FF803F80FF803F80FFF83F80FFF83F80FF",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Instructions_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 17 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Instructions_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end Instructions_blk_mem_gen_prim_width;
architecture STRUCTURE of Instructions_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.Instructions_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(17 downto 0) => douta(17 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized10\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized11\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized12\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized12\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized13\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized13\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized14\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized15\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized15\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized15\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized15\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized15\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized16\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized16\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized16\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized16\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized16\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized17\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized17\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized17\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized17\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized17\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized18\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized18\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized18\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized18\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized18\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized19\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized19\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized19\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized19\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized19\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized20\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized20\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized20\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized20\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized20\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized21\ is
port (
douta : out STD_LOGIC_VECTOR ( 25 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized21\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized21\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized21\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized21\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(25 downto 0) => douta(25 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized7\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized8\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_prim_width__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \Instructions_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \Instructions_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_init.ram\: entity work.\Instructions_blk_mem_gen_prim_wrapper_init__parameterized9\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Instructions_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Instructions_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end Instructions_blk_mem_gen_generic_cstr;
architecture STRUCTURE of Instructions_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.Instructions_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(17 downto 0) => douta(17 downto 0)
);
\ramloop[10].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized9\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(377 downto 342)
);
\ramloop[11].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized10\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(413 downto 378)
);
\ramloop[12].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized11\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(449 downto 414)
);
\ramloop[13].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized12\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(485 downto 450)
);
\ramloop[14].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized13\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(521 downto 486)
);
\ramloop[15].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized14\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(557 downto 522)
);
\ramloop[16].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized15\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(593 downto 558)
);
\ramloop[17].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized16\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(629 downto 594)
);
\ramloop[18].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized17\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(665 downto 630)
);
\ramloop[19].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized18\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(701 downto 666)
);
\ramloop[1].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized0\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(53 downto 18)
);
\ramloop[20].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized19\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(737 downto 702)
);
\ramloop[21].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized20\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(773 downto 738)
);
\ramloop[22].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized21\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(25 downto 0) => douta(799 downto 774)
);
\ramloop[2].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized1\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(89 downto 54)
);
\ramloop[3].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized2\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(125 downto 90)
);
\ramloop[4].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized3\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(161 downto 126)
);
\ramloop[5].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized4\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(197 downto 162)
);
\ramloop[6].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized5\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(233 downto 198)
);
\ramloop[7].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized6\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(269 downto 234)
);
\ramloop[8].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized7\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(305 downto 270)
);
\ramloop[9].ram.r\: entity work.\Instructions_blk_mem_gen_prim_width__parameterized8\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(341 downto 306)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Instructions_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Instructions_blk_mem_gen_top : entity is "blk_mem_gen_top";
end Instructions_blk_mem_gen_top;
architecture STRUCTURE of Instructions_blk_mem_gen_top is
begin
\valid.cstr\: entity work.Instructions_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(799 downto 0) => douta(799 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Instructions_blk_mem_gen_v8_2_synth is
port (
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Instructions_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end Instructions_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of Instructions_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.Instructions_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(799 downto 0) => douta(799 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Instructions_blk_mem_gen_v8_2__parameterized0\ is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 799 downto 0 );
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 799 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 799 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 799 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 799 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
attribute C_FAMILY : string;
attribute C_FAMILY of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "artix7";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "artix7";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "./";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 4;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 3;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "Instructions.mif";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "Instructions.mem";
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 10;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 10;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "22";
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "1";
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 60.4532 mW";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \Instructions_blk_mem_gen_v8_2__parameterized0\ : entity is "yes";
end \Instructions_blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \Instructions_blk_mem_gen_v8_2__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(799) <= \<const0>\;
doutb(798) <= \<const0>\;
doutb(797) <= \<const0>\;
doutb(796) <= \<const0>\;
doutb(795) <= \<const0>\;
doutb(794) <= \<const0>\;
doutb(793) <= \<const0>\;
doutb(792) <= \<const0>\;
doutb(791) <= \<const0>\;
doutb(790) <= \<const0>\;
doutb(789) <= \<const0>\;
doutb(788) <= \<const0>\;
doutb(787) <= \<const0>\;
doutb(786) <= \<const0>\;
doutb(785) <= \<const0>\;
doutb(784) <= \<const0>\;
doutb(783) <= \<const0>\;
doutb(782) <= \<const0>\;
doutb(781) <= \<const0>\;
doutb(780) <= \<const0>\;
doutb(779) <= \<const0>\;
doutb(778) <= \<const0>\;
doutb(777) <= \<const0>\;
doutb(776) <= \<const0>\;
doutb(775) <= \<const0>\;
doutb(774) <= \<const0>\;
doutb(773) <= \<const0>\;
doutb(772) <= \<const0>\;
doutb(771) <= \<const0>\;
doutb(770) <= \<const0>\;
doutb(769) <= \<const0>\;
doutb(768) <= \<const0>\;
doutb(767) <= \<const0>\;
doutb(766) <= \<const0>\;
doutb(765) <= \<const0>\;
doutb(764) <= \<const0>\;
doutb(763) <= \<const0>\;
doutb(762) <= \<const0>\;
doutb(761) <= \<const0>\;
doutb(760) <= \<const0>\;
doutb(759) <= \<const0>\;
doutb(758) <= \<const0>\;
doutb(757) <= \<const0>\;
doutb(756) <= \<const0>\;
doutb(755) <= \<const0>\;
doutb(754) <= \<const0>\;
doutb(753) <= \<const0>\;
doutb(752) <= \<const0>\;
doutb(751) <= \<const0>\;
doutb(750) <= \<const0>\;
doutb(749) <= \<const0>\;
doutb(748) <= \<const0>\;
doutb(747) <= \<const0>\;
doutb(746) <= \<const0>\;
doutb(745) <= \<const0>\;
doutb(744) <= \<const0>\;
doutb(743) <= \<const0>\;
doutb(742) <= \<const0>\;
doutb(741) <= \<const0>\;
doutb(740) <= \<const0>\;
doutb(739) <= \<const0>\;
doutb(738) <= \<const0>\;
doutb(737) <= \<const0>\;
doutb(736) <= \<const0>\;
doutb(735) <= \<const0>\;
doutb(734) <= \<const0>\;
doutb(733) <= \<const0>\;
doutb(732) <= \<const0>\;
doutb(731) <= \<const0>\;
doutb(730) <= \<const0>\;
doutb(729) <= \<const0>\;
doutb(728) <= \<const0>\;
doutb(727) <= \<const0>\;
doutb(726) <= \<const0>\;
doutb(725) <= \<const0>\;
doutb(724) <= \<const0>\;
doutb(723) <= \<const0>\;
doutb(722) <= \<const0>\;
doutb(721) <= \<const0>\;
doutb(720) <= \<const0>\;
doutb(719) <= \<const0>\;
doutb(718) <= \<const0>\;
doutb(717) <= \<const0>\;
doutb(716) <= \<const0>\;
doutb(715) <= \<const0>\;
doutb(714) <= \<const0>\;
doutb(713) <= \<const0>\;
doutb(712) <= \<const0>\;
doutb(711) <= \<const0>\;
doutb(710) <= \<const0>\;
doutb(709) <= \<const0>\;
doutb(708) <= \<const0>\;
doutb(707) <= \<const0>\;
doutb(706) <= \<const0>\;
doutb(705) <= \<const0>\;
doutb(704) <= \<const0>\;
doutb(703) <= \<const0>\;
doutb(702) <= \<const0>\;
doutb(701) <= \<const0>\;
doutb(700) <= \<const0>\;
doutb(699) <= \<const0>\;
doutb(698) <= \<const0>\;
doutb(697) <= \<const0>\;
doutb(696) <= \<const0>\;
doutb(695) <= \<const0>\;
doutb(694) <= \<const0>\;
doutb(693) <= \<const0>\;
doutb(692) <= \<const0>\;
doutb(691) <= \<const0>\;
doutb(690) <= \<const0>\;
doutb(689) <= \<const0>\;
doutb(688) <= \<const0>\;
doutb(687) <= \<const0>\;
doutb(686) <= \<const0>\;
doutb(685) <= \<const0>\;
doutb(684) <= \<const0>\;
doutb(683) <= \<const0>\;
doutb(682) <= \<const0>\;
doutb(681) <= \<const0>\;
doutb(680) <= \<const0>\;
doutb(679) <= \<const0>\;
doutb(678) <= \<const0>\;
doutb(677) <= \<const0>\;
doutb(676) <= \<const0>\;
doutb(675) <= \<const0>\;
doutb(674) <= \<const0>\;
doutb(673) <= \<const0>\;
doutb(672) <= \<const0>\;
doutb(671) <= \<const0>\;
doutb(670) <= \<const0>\;
doutb(669) <= \<const0>\;
doutb(668) <= \<const0>\;
doutb(667) <= \<const0>\;
doutb(666) <= \<const0>\;
doutb(665) <= \<const0>\;
doutb(664) <= \<const0>\;
doutb(663) <= \<const0>\;
doutb(662) <= \<const0>\;
doutb(661) <= \<const0>\;
doutb(660) <= \<const0>\;
doutb(659) <= \<const0>\;
doutb(658) <= \<const0>\;
doutb(657) <= \<const0>\;
doutb(656) <= \<const0>\;
doutb(655) <= \<const0>\;
doutb(654) <= \<const0>\;
doutb(653) <= \<const0>\;
doutb(652) <= \<const0>\;
doutb(651) <= \<const0>\;
doutb(650) <= \<const0>\;
doutb(649) <= \<const0>\;
doutb(648) <= \<const0>\;
doutb(647) <= \<const0>\;
doutb(646) <= \<const0>\;
doutb(645) <= \<const0>\;
doutb(644) <= \<const0>\;
doutb(643) <= \<const0>\;
doutb(642) <= \<const0>\;
doutb(641) <= \<const0>\;
doutb(640) <= \<const0>\;
doutb(639) <= \<const0>\;
doutb(638) <= \<const0>\;
doutb(637) <= \<const0>\;
doutb(636) <= \<const0>\;
doutb(635) <= \<const0>\;
doutb(634) <= \<const0>\;
doutb(633) <= \<const0>\;
doutb(632) <= \<const0>\;
doutb(631) <= \<const0>\;
doutb(630) <= \<const0>\;
doutb(629) <= \<const0>\;
doutb(628) <= \<const0>\;
doutb(627) <= \<const0>\;
doutb(626) <= \<const0>\;
doutb(625) <= \<const0>\;
doutb(624) <= \<const0>\;
doutb(623) <= \<const0>\;
doutb(622) <= \<const0>\;
doutb(621) <= \<const0>\;
doutb(620) <= \<const0>\;
doutb(619) <= \<const0>\;
doutb(618) <= \<const0>\;
doutb(617) <= \<const0>\;
doutb(616) <= \<const0>\;
doutb(615) <= \<const0>\;
doutb(614) <= \<const0>\;
doutb(613) <= \<const0>\;
doutb(612) <= \<const0>\;
doutb(611) <= \<const0>\;
doutb(610) <= \<const0>\;
doutb(609) <= \<const0>\;
doutb(608) <= \<const0>\;
doutb(607) <= \<const0>\;
doutb(606) <= \<const0>\;
doutb(605) <= \<const0>\;
doutb(604) <= \<const0>\;
doutb(603) <= \<const0>\;
doutb(602) <= \<const0>\;
doutb(601) <= \<const0>\;
doutb(600) <= \<const0>\;
doutb(599) <= \<const0>\;
doutb(598) <= \<const0>\;
doutb(597) <= \<const0>\;
doutb(596) <= \<const0>\;
doutb(595) <= \<const0>\;
doutb(594) <= \<const0>\;
doutb(593) <= \<const0>\;
doutb(592) <= \<const0>\;
doutb(591) <= \<const0>\;
doutb(590) <= \<const0>\;
doutb(589) <= \<const0>\;
doutb(588) <= \<const0>\;
doutb(587) <= \<const0>\;
doutb(586) <= \<const0>\;
doutb(585) <= \<const0>\;
doutb(584) <= \<const0>\;
doutb(583) <= \<const0>\;
doutb(582) <= \<const0>\;
doutb(581) <= \<const0>\;
doutb(580) <= \<const0>\;
doutb(579) <= \<const0>\;
doutb(578) <= \<const0>\;
doutb(577) <= \<const0>\;
doutb(576) <= \<const0>\;
doutb(575) <= \<const0>\;
doutb(574) <= \<const0>\;
doutb(573) <= \<const0>\;
doutb(572) <= \<const0>\;
doutb(571) <= \<const0>\;
doutb(570) <= \<const0>\;
doutb(569) <= \<const0>\;
doutb(568) <= \<const0>\;
doutb(567) <= \<const0>\;
doutb(566) <= \<const0>\;
doutb(565) <= \<const0>\;
doutb(564) <= \<const0>\;
doutb(563) <= \<const0>\;
doutb(562) <= \<const0>\;
doutb(561) <= \<const0>\;
doutb(560) <= \<const0>\;
doutb(559) <= \<const0>\;
doutb(558) <= \<const0>\;
doutb(557) <= \<const0>\;
doutb(556) <= \<const0>\;
doutb(555) <= \<const0>\;
doutb(554) <= \<const0>\;
doutb(553) <= \<const0>\;
doutb(552) <= \<const0>\;
doutb(551) <= \<const0>\;
doutb(550) <= \<const0>\;
doutb(549) <= \<const0>\;
doutb(548) <= \<const0>\;
doutb(547) <= \<const0>\;
doutb(546) <= \<const0>\;
doutb(545) <= \<const0>\;
doutb(544) <= \<const0>\;
doutb(543) <= \<const0>\;
doutb(542) <= \<const0>\;
doutb(541) <= \<const0>\;
doutb(540) <= \<const0>\;
doutb(539) <= \<const0>\;
doutb(538) <= \<const0>\;
doutb(537) <= \<const0>\;
doutb(536) <= \<const0>\;
doutb(535) <= \<const0>\;
doutb(534) <= \<const0>\;
doutb(533) <= \<const0>\;
doutb(532) <= \<const0>\;
doutb(531) <= \<const0>\;
doutb(530) <= \<const0>\;
doutb(529) <= \<const0>\;
doutb(528) <= \<const0>\;
doutb(527) <= \<const0>\;
doutb(526) <= \<const0>\;
doutb(525) <= \<const0>\;
doutb(524) <= \<const0>\;
doutb(523) <= \<const0>\;
doutb(522) <= \<const0>\;
doutb(521) <= \<const0>\;
doutb(520) <= \<const0>\;
doutb(519) <= \<const0>\;
doutb(518) <= \<const0>\;
doutb(517) <= \<const0>\;
doutb(516) <= \<const0>\;
doutb(515) <= \<const0>\;
doutb(514) <= \<const0>\;
doutb(513) <= \<const0>\;
doutb(512) <= \<const0>\;
doutb(511) <= \<const0>\;
doutb(510) <= \<const0>\;
doutb(509) <= \<const0>\;
doutb(508) <= \<const0>\;
doutb(507) <= \<const0>\;
doutb(506) <= \<const0>\;
doutb(505) <= \<const0>\;
doutb(504) <= \<const0>\;
doutb(503) <= \<const0>\;
doutb(502) <= \<const0>\;
doutb(501) <= \<const0>\;
doutb(500) <= \<const0>\;
doutb(499) <= \<const0>\;
doutb(498) <= \<const0>\;
doutb(497) <= \<const0>\;
doutb(496) <= \<const0>\;
doutb(495) <= \<const0>\;
doutb(494) <= \<const0>\;
doutb(493) <= \<const0>\;
doutb(492) <= \<const0>\;
doutb(491) <= \<const0>\;
doutb(490) <= \<const0>\;
doutb(489) <= \<const0>\;
doutb(488) <= \<const0>\;
doutb(487) <= \<const0>\;
doutb(486) <= \<const0>\;
doutb(485) <= \<const0>\;
doutb(484) <= \<const0>\;
doutb(483) <= \<const0>\;
doutb(482) <= \<const0>\;
doutb(481) <= \<const0>\;
doutb(480) <= \<const0>\;
doutb(479) <= \<const0>\;
doutb(478) <= \<const0>\;
doutb(477) <= \<const0>\;
doutb(476) <= \<const0>\;
doutb(475) <= \<const0>\;
doutb(474) <= \<const0>\;
doutb(473) <= \<const0>\;
doutb(472) <= \<const0>\;
doutb(471) <= \<const0>\;
doutb(470) <= \<const0>\;
doutb(469) <= \<const0>\;
doutb(468) <= \<const0>\;
doutb(467) <= \<const0>\;
doutb(466) <= \<const0>\;
doutb(465) <= \<const0>\;
doutb(464) <= \<const0>\;
doutb(463) <= \<const0>\;
doutb(462) <= \<const0>\;
doutb(461) <= \<const0>\;
doutb(460) <= \<const0>\;
doutb(459) <= \<const0>\;
doutb(458) <= \<const0>\;
doutb(457) <= \<const0>\;
doutb(456) <= \<const0>\;
doutb(455) <= \<const0>\;
doutb(454) <= \<const0>\;
doutb(453) <= \<const0>\;
doutb(452) <= \<const0>\;
doutb(451) <= \<const0>\;
doutb(450) <= \<const0>\;
doutb(449) <= \<const0>\;
doutb(448) <= \<const0>\;
doutb(447) <= \<const0>\;
doutb(446) <= \<const0>\;
doutb(445) <= \<const0>\;
doutb(444) <= \<const0>\;
doutb(443) <= \<const0>\;
doutb(442) <= \<const0>\;
doutb(441) <= \<const0>\;
doutb(440) <= \<const0>\;
doutb(439) <= \<const0>\;
doutb(438) <= \<const0>\;
doutb(437) <= \<const0>\;
doutb(436) <= \<const0>\;
doutb(435) <= \<const0>\;
doutb(434) <= \<const0>\;
doutb(433) <= \<const0>\;
doutb(432) <= \<const0>\;
doutb(431) <= \<const0>\;
doutb(430) <= \<const0>\;
doutb(429) <= \<const0>\;
doutb(428) <= \<const0>\;
doutb(427) <= \<const0>\;
doutb(426) <= \<const0>\;
doutb(425) <= \<const0>\;
doutb(424) <= \<const0>\;
doutb(423) <= \<const0>\;
doutb(422) <= \<const0>\;
doutb(421) <= \<const0>\;
doutb(420) <= \<const0>\;
doutb(419) <= \<const0>\;
doutb(418) <= \<const0>\;
doutb(417) <= \<const0>\;
doutb(416) <= \<const0>\;
doutb(415) <= \<const0>\;
doutb(414) <= \<const0>\;
doutb(413) <= \<const0>\;
doutb(412) <= \<const0>\;
doutb(411) <= \<const0>\;
doutb(410) <= \<const0>\;
doutb(409) <= \<const0>\;
doutb(408) <= \<const0>\;
doutb(407) <= \<const0>\;
doutb(406) <= \<const0>\;
doutb(405) <= \<const0>\;
doutb(404) <= \<const0>\;
doutb(403) <= \<const0>\;
doutb(402) <= \<const0>\;
doutb(401) <= \<const0>\;
doutb(400) <= \<const0>\;
doutb(399) <= \<const0>\;
doutb(398) <= \<const0>\;
doutb(397) <= \<const0>\;
doutb(396) <= \<const0>\;
doutb(395) <= \<const0>\;
doutb(394) <= \<const0>\;
doutb(393) <= \<const0>\;
doutb(392) <= \<const0>\;
doutb(391) <= \<const0>\;
doutb(390) <= \<const0>\;
doutb(389) <= \<const0>\;
doutb(388) <= \<const0>\;
doutb(387) <= \<const0>\;
doutb(386) <= \<const0>\;
doutb(385) <= \<const0>\;
doutb(384) <= \<const0>\;
doutb(383) <= \<const0>\;
doutb(382) <= \<const0>\;
doutb(381) <= \<const0>\;
doutb(380) <= \<const0>\;
doutb(379) <= \<const0>\;
doutb(378) <= \<const0>\;
doutb(377) <= \<const0>\;
doutb(376) <= \<const0>\;
doutb(375) <= \<const0>\;
doutb(374) <= \<const0>\;
doutb(373) <= \<const0>\;
doutb(372) <= \<const0>\;
doutb(371) <= \<const0>\;
doutb(370) <= \<const0>\;
doutb(369) <= \<const0>\;
doutb(368) <= \<const0>\;
doutb(367) <= \<const0>\;
doutb(366) <= \<const0>\;
doutb(365) <= \<const0>\;
doutb(364) <= \<const0>\;
doutb(363) <= \<const0>\;
doutb(362) <= \<const0>\;
doutb(361) <= \<const0>\;
doutb(360) <= \<const0>\;
doutb(359) <= \<const0>\;
doutb(358) <= \<const0>\;
doutb(357) <= \<const0>\;
doutb(356) <= \<const0>\;
doutb(355) <= \<const0>\;
doutb(354) <= \<const0>\;
doutb(353) <= \<const0>\;
doutb(352) <= \<const0>\;
doutb(351) <= \<const0>\;
doutb(350) <= \<const0>\;
doutb(349) <= \<const0>\;
doutb(348) <= \<const0>\;
doutb(347) <= \<const0>\;
doutb(346) <= \<const0>\;
doutb(345) <= \<const0>\;
doutb(344) <= \<const0>\;
doutb(343) <= \<const0>\;
doutb(342) <= \<const0>\;
doutb(341) <= \<const0>\;
doutb(340) <= \<const0>\;
doutb(339) <= \<const0>\;
doutb(338) <= \<const0>\;
doutb(337) <= \<const0>\;
doutb(336) <= \<const0>\;
doutb(335) <= \<const0>\;
doutb(334) <= \<const0>\;
doutb(333) <= \<const0>\;
doutb(332) <= \<const0>\;
doutb(331) <= \<const0>\;
doutb(330) <= \<const0>\;
doutb(329) <= \<const0>\;
doutb(328) <= \<const0>\;
doutb(327) <= \<const0>\;
doutb(326) <= \<const0>\;
doutb(325) <= \<const0>\;
doutb(324) <= \<const0>\;
doutb(323) <= \<const0>\;
doutb(322) <= \<const0>\;
doutb(321) <= \<const0>\;
doutb(320) <= \<const0>\;
doutb(319) <= \<const0>\;
doutb(318) <= \<const0>\;
doutb(317) <= \<const0>\;
doutb(316) <= \<const0>\;
doutb(315) <= \<const0>\;
doutb(314) <= \<const0>\;
doutb(313) <= \<const0>\;
doutb(312) <= \<const0>\;
doutb(311) <= \<const0>\;
doutb(310) <= \<const0>\;
doutb(309) <= \<const0>\;
doutb(308) <= \<const0>\;
doutb(307) <= \<const0>\;
doutb(306) <= \<const0>\;
doutb(305) <= \<const0>\;
doutb(304) <= \<const0>\;
doutb(303) <= \<const0>\;
doutb(302) <= \<const0>\;
doutb(301) <= \<const0>\;
doutb(300) <= \<const0>\;
doutb(299) <= \<const0>\;
doutb(298) <= \<const0>\;
doutb(297) <= \<const0>\;
doutb(296) <= \<const0>\;
doutb(295) <= \<const0>\;
doutb(294) <= \<const0>\;
doutb(293) <= \<const0>\;
doutb(292) <= \<const0>\;
doutb(291) <= \<const0>\;
doutb(290) <= \<const0>\;
doutb(289) <= \<const0>\;
doutb(288) <= \<const0>\;
doutb(287) <= \<const0>\;
doutb(286) <= \<const0>\;
doutb(285) <= \<const0>\;
doutb(284) <= \<const0>\;
doutb(283) <= \<const0>\;
doutb(282) <= \<const0>\;
doutb(281) <= \<const0>\;
doutb(280) <= \<const0>\;
doutb(279) <= \<const0>\;
doutb(278) <= \<const0>\;
doutb(277) <= \<const0>\;
doutb(276) <= \<const0>\;
doutb(275) <= \<const0>\;
doutb(274) <= \<const0>\;
doutb(273) <= \<const0>\;
doutb(272) <= \<const0>\;
doutb(271) <= \<const0>\;
doutb(270) <= \<const0>\;
doutb(269) <= \<const0>\;
doutb(268) <= \<const0>\;
doutb(267) <= \<const0>\;
doutb(266) <= \<const0>\;
doutb(265) <= \<const0>\;
doutb(264) <= \<const0>\;
doutb(263) <= \<const0>\;
doutb(262) <= \<const0>\;
doutb(261) <= \<const0>\;
doutb(260) <= \<const0>\;
doutb(259) <= \<const0>\;
doutb(258) <= \<const0>\;
doutb(257) <= \<const0>\;
doutb(256) <= \<const0>\;
doutb(255) <= \<const0>\;
doutb(254) <= \<const0>\;
doutb(253) <= \<const0>\;
doutb(252) <= \<const0>\;
doutb(251) <= \<const0>\;
doutb(250) <= \<const0>\;
doutb(249) <= \<const0>\;
doutb(248) <= \<const0>\;
doutb(247) <= \<const0>\;
doutb(246) <= \<const0>\;
doutb(245) <= \<const0>\;
doutb(244) <= \<const0>\;
doutb(243) <= \<const0>\;
doutb(242) <= \<const0>\;
doutb(241) <= \<const0>\;
doutb(240) <= \<const0>\;
doutb(239) <= \<const0>\;
doutb(238) <= \<const0>\;
doutb(237) <= \<const0>\;
doutb(236) <= \<const0>\;
doutb(235) <= \<const0>\;
doutb(234) <= \<const0>\;
doutb(233) <= \<const0>\;
doutb(232) <= \<const0>\;
doutb(231) <= \<const0>\;
doutb(230) <= \<const0>\;
doutb(229) <= \<const0>\;
doutb(228) <= \<const0>\;
doutb(227) <= \<const0>\;
doutb(226) <= \<const0>\;
doutb(225) <= \<const0>\;
doutb(224) <= \<const0>\;
doutb(223) <= \<const0>\;
doutb(222) <= \<const0>\;
doutb(221) <= \<const0>\;
doutb(220) <= \<const0>\;
doutb(219) <= \<const0>\;
doutb(218) <= \<const0>\;
doutb(217) <= \<const0>\;
doutb(216) <= \<const0>\;
doutb(215) <= \<const0>\;
doutb(214) <= \<const0>\;
doutb(213) <= \<const0>\;
doutb(212) <= \<const0>\;
doutb(211) <= \<const0>\;
doutb(210) <= \<const0>\;
doutb(209) <= \<const0>\;
doutb(208) <= \<const0>\;
doutb(207) <= \<const0>\;
doutb(206) <= \<const0>\;
doutb(205) <= \<const0>\;
doutb(204) <= \<const0>\;
doutb(203) <= \<const0>\;
doutb(202) <= \<const0>\;
doutb(201) <= \<const0>\;
doutb(200) <= \<const0>\;
doutb(199) <= \<const0>\;
doutb(198) <= \<const0>\;
doutb(197) <= \<const0>\;
doutb(196) <= \<const0>\;
doutb(195) <= \<const0>\;
doutb(194) <= \<const0>\;
doutb(193) <= \<const0>\;
doutb(192) <= \<const0>\;
doutb(191) <= \<const0>\;
doutb(190) <= \<const0>\;
doutb(189) <= \<const0>\;
doutb(188) <= \<const0>\;
doutb(187) <= \<const0>\;
doutb(186) <= \<const0>\;
doutb(185) <= \<const0>\;
doutb(184) <= \<const0>\;
doutb(183) <= \<const0>\;
doutb(182) <= \<const0>\;
doutb(181) <= \<const0>\;
doutb(180) <= \<const0>\;
doutb(179) <= \<const0>\;
doutb(178) <= \<const0>\;
doutb(177) <= \<const0>\;
doutb(176) <= \<const0>\;
doutb(175) <= \<const0>\;
doutb(174) <= \<const0>\;
doutb(173) <= \<const0>\;
doutb(172) <= \<const0>\;
doutb(171) <= \<const0>\;
doutb(170) <= \<const0>\;
doutb(169) <= \<const0>\;
doutb(168) <= \<const0>\;
doutb(167) <= \<const0>\;
doutb(166) <= \<const0>\;
doutb(165) <= \<const0>\;
doutb(164) <= \<const0>\;
doutb(163) <= \<const0>\;
doutb(162) <= \<const0>\;
doutb(161) <= \<const0>\;
doutb(160) <= \<const0>\;
doutb(159) <= \<const0>\;
doutb(158) <= \<const0>\;
doutb(157) <= \<const0>\;
doutb(156) <= \<const0>\;
doutb(155) <= \<const0>\;
doutb(154) <= \<const0>\;
doutb(153) <= \<const0>\;
doutb(152) <= \<const0>\;
doutb(151) <= \<const0>\;
doutb(150) <= \<const0>\;
doutb(149) <= \<const0>\;
doutb(148) <= \<const0>\;
doutb(147) <= \<const0>\;
doutb(146) <= \<const0>\;
doutb(145) <= \<const0>\;
doutb(144) <= \<const0>\;
doutb(143) <= \<const0>\;
doutb(142) <= \<const0>\;
doutb(141) <= \<const0>\;
doutb(140) <= \<const0>\;
doutb(139) <= \<const0>\;
doutb(138) <= \<const0>\;
doutb(137) <= \<const0>\;
doutb(136) <= \<const0>\;
doutb(135) <= \<const0>\;
doutb(134) <= \<const0>\;
doutb(133) <= \<const0>\;
doutb(132) <= \<const0>\;
doutb(131) <= \<const0>\;
doutb(130) <= \<const0>\;
doutb(129) <= \<const0>\;
doutb(128) <= \<const0>\;
doutb(127) <= \<const0>\;
doutb(126) <= \<const0>\;
doutb(125) <= \<const0>\;
doutb(124) <= \<const0>\;
doutb(123) <= \<const0>\;
doutb(122) <= \<const0>\;
doutb(121) <= \<const0>\;
doutb(120) <= \<const0>\;
doutb(119) <= \<const0>\;
doutb(118) <= \<const0>\;
doutb(117) <= \<const0>\;
doutb(116) <= \<const0>\;
doutb(115) <= \<const0>\;
doutb(114) <= \<const0>\;
doutb(113) <= \<const0>\;
doutb(112) <= \<const0>\;
doutb(111) <= \<const0>\;
doutb(110) <= \<const0>\;
doutb(109) <= \<const0>\;
doutb(108) <= \<const0>\;
doutb(107) <= \<const0>\;
doutb(106) <= \<const0>\;
doutb(105) <= \<const0>\;
doutb(104) <= \<const0>\;
doutb(103) <= \<const0>\;
doutb(102) <= \<const0>\;
doutb(101) <= \<const0>\;
doutb(100) <= \<const0>\;
doutb(99) <= \<const0>\;
doutb(98) <= \<const0>\;
doutb(97) <= \<const0>\;
doutb(96) <= \<const0>\;
doutb(95) <= \<const0>\;
doutb(94) <= \<const0>\;
doutb(93) <= \<const0>\;
doutb(92) <= \<const0>\;
doutb(91) <= \<const0>\;
doutb(90) <= \<const0>\;
doutb(89) <= \<const0>\;
doutb(88) <= \<const0>\;
doutb(87) <= \<const0>\;
doutb(86) <= \<const0>\;
doutb(85) <= \<const0>\;
doutb(84) <= \<const0>\;
doutb(83) <= \<const0>\;
doutb(82) <= \<const0>\;
doutb(81) <= \<const0>\;
doutb(80) <= \<const0>\;
doutb(79) <= \<const0>\;
doutb(78) <= \<const0>\;
doutb(77) <= \<const0>\;
doutb(76) <= \<const0>\;
doutb(75) <= \<const0>\;
doutb(74) <= \<const0>\;
doutb(73) <= \<const0>\;
doutb(72) <= \<const0>\;
doutb(71) <= \<const0>\;
doutb(70) <= \<const0>\;
doutb(69) <= \<const0>\;
doutb(68) <= \<const0>\;
doutb(67) <= \<const0>\;
doutb(66) <= \<const0>\;
doutb(65) <= \<const0>\;
doutb(64) <= \<const0>\;
doutb(63) <= \<const0>\;
doutb(62) <= \<const0>\;
doutb(61) <= \<const0>\;
doutb(60) <= \<const0>\;
doutb(59) <= \<const0>\;
doutb(58) <= \<const0>\;
doutb(57) <= \<const0>\;
doutb(56) <= \<const0>\;
doutb(55) <= \<const0>\;
doutb(54) <= \<const0>\;
doutb(53) <= \<const0>\;
doutb(52) <= \<const0>\;
doutb(51) <= \<const0>\;
doutb(50) <= \<const0>\;
doutb(49) <= \<const0>\;
doutb(48) <= \<const0>\;
doutb(47) <= \<const0>\;
doutb(46) <= \<const0>\;
doutb(45) <= \<const0>\;
doutb(44) <= \<const0>\;
doutb(43) <= \<const0>\;
doutb(42) <= \<const0>\;
doutb(41) <= \<const0>\;
doutb(40) <= \<const0>\;
doutb(39) <= \<const0>\;
doutb(38) <= \<const0>\;
doutb(37) <= \<const0>\;
doutb(36) <= \<const0>\;
doutb(35) <= \<const0>\;
doutb(34) <= \<const0>\;
doutb(33) <= \<const0>\;
doutb(32) <= \<const0>\;
doutb(31) <= \<const0>\;
doutb(30) <= \<const0>\;
doutb(29) <= \<const0>\;
doutb(28) <= \<const0>\;
doutb(27) <= \<const0>\;
doutb(26) <= \<const0>\;
doutb(25) <= \<const0>\;
doutb(24) <= \<const0>\;
doutb(23) <= \<const0>\;
doutb(22) <= \<const0>\;
doutb(21) <= \<const0>\;
doutb(20) <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(799) <= \<const0>\;
s_axi_rdata(798) <= \<const0>\;
s_axi_rdata(797) <= \<const0>\;
s_axi_rdata(796) <= \<const0>\;
s_axi_rdata(795) <= \<const0>\;
s_axi_rdata(794) <= \<const0>\;
s_axi_rdata(793) <= \<const0>\;
s_axi_rdata(792) <= \<const0>\;
s_axi_rdata(791) <= \<const0>\;
s_axi_rdata(790) <= \<const0>\;
s_axi_rdata(789) <= \<const0>\;
s_axi_rdata(788) <= \<const0>\;
s_axi_rdata(787) <= \<const0>\;
s_axi_rdata(786) <= \<const0>\;
s_axi_rdata(785) <= \<const0>\;
s_axi_rdata(784) <= \<const0>\;
s_axi_rdata(783) <= \<const0>\;
s_axi_rdata(782) <= \<const0>\;
s_axi_rdata(781) <= \<const0>\;
s_axi_rdata(780) <= \<const0>\;
s_axi_rdata(779) <= \<const0>\;
s_axi_rdata(778) <= \<const0>\;
s_axi_rdata(777) <= \<const0>\;
s_axi_rdata(776) <= \<const0>\;
s_axi_rdata(775) <= \<const0>\;
s_axi_rdata(774) <= \<const0>\;
s_axi_rdata(773) <= \<const0>\;
s_axi_rdata(772) <= \<const0>\;
s_axi_rdata(771) <= \<const0>\;
s_axi_rdata(770) <= \<const0>\;
s_axi_rdata(769) <= \<const0>\;
s_axi_rdata(768) <= \<const0>\;
s_axi_rdata(767) <= \<const0>\;
s_axi_rdata(766) <= \<const0>\;
s_axi_rdata(765) <= \<const0>\;
s_axi_rdata(764) <= \<const0>\;
s_axi_rdata(763) <= \<const0>\;
s_axi_rdata(762) <= \<const0>\;
s_axi_rdata(761) <= \<const0>\;
s_axi_rdata(760) <= \<const0>\;
s_axi_rdata(759) <= \<const0>\;
s_axi_rdata(758) <= \<const0>\;
s_axi_rdata(757) <= \<const0>\;
s_axi_rdata(756) <= \<const0>\;
s_axi_rdata(755) <= \<const0>\;
s_axi_rdata(754) <= \<const0>\;
s_axi_rdata(753) <= \<const0>\;
s_axi_rdata(752) <= \<const0>\;
s_axi_rdata(751) <= \<const0>\;
s_axi_rdata(750) <= \<const0>\;
s_axi_rdata(749) <= \<const0>\;
s_axi_rdata(748) <= \<const0>\;
s_axi_rdata(747) <= \<const0>\;
s_axi_rdata(746) <= \<const0>\;
s_axi_rdata(745) <= \<const0>\;
s_axi_rdata(744) <= \<const0>\;
s_axi_rdata(743) <= \<const0>\;
s_axi_rdata(742) <= \<const0>\;
s_axi_rdata(741) <= \<const0>\;
s_axi_rdata(740) <= \<const0>\;
s_axi_rdata(739) <= \<const0>\;
s_axi_rdata(738) <= \<const0>\;
s_axi_rdata(737) <= \<const0>\;
s_axi_rdata(736) <= \<const0>\;
s_axi_rdata(735) <= \<const0>\;
s_axi_rdata(734) <= \<const0>\;
s_axi_rdata(733) <= \<const0>\;
s_axi_rdata(732) <= \<const0>\;
s_axi_rdata(731) <= \<const0>\;
s_axi_rdata(730) <= \<const0>\;
s_axi_rdata(729) <= \<const0>\;
s_axi_rdata(728) <= \<const0>\;
s_axi_rdata(727) <= \<const0>\;
s_axi_rdata(726) <= \<const0>\;
s_axi_rdata(725) <= \<const0>\;
s_axi_rdata(724) <= \<const0>\;
s_axi_rdata(723) <= \<const0>\;
s_axi_rdata(722) <= \<const0>\;
s_axi_rdata(721) <= \<const0>\;
s_axi_rdata(720) <= \<const0>\;
s_axi_rdata(719) <= \<const0>\;
s_axi_rdata(718) <= \<const0>\;
s_axi_rdata(717) <= \<const0>\;
s_axi_rdata(716) <= \<const0>\;
s_axi_rdata(715) <= \<const0>\;
s_axi_rdata(714) <= \<const0>\;
s_axi_rdata(713) <= \<const0>\;
s_axi_rdata(712) <= \<const0>\;
s_axi_rdata(711) <= \<const0>\;
s_axi_rdata(710) <= \<const0>\;
s_axi_rdata(709) <= \<const0>\;
s_axi_rdata(708) <= \<const0>\;
s_axi_rdata(707) <= \<const0>\;
s_axi_rdata(706) <= \<const0>\;
s_axi_rdata(705) <= \<const0>\;
s_axi_rdata(704) <= \<const0>\;
s_axi_rdata(703) <= \<const0>\;
s_axi_rdata(702) <= \<const0>\;
s_axi_rdata(701) <= \<const0>\;
s_axi_rdata(700) <= \<const0>\;
s_axi_rdata(699) <= \<const0>\;
s_axi_rdata(698) <= \<const0>\;
s_axi_rdata(697) <= \<const0>\;
s_axi_rdata(696) <= \<const0>\;
s_axi_rdata(695) <= \<const0>\;
s_axi_rdata(694) <= \<const0>\;
s_axi_rdata(693) <= \<const0>\;
s_axi_rdata(692) <= \<const0>\;
s_axi_rdata(691) <= \<const0>\;
s_axi_rdata(690) <= \<const0>\;
s_axi_rdata(689) <= \<const0>\;
s_axi_rdata(688) <= \<const0>\;
s_axi_rdata(687) <= \<const0>\;
s_axi_rdata(686) <= \<const0>\;
s_axi_rdata(685) <= \<const0>\;
s_axi_rdata(684) <= \<const0>\;
s_axi_rdata(683) <= \<const0>\;
s_axi_rdata(682) <= \<const0>\;
s_axi_rdata(681) <= \<const0>\;
s_axi_rdata(680) <= \<const0>\;
s_axi_rdata(679) <= \<const0>\;
s_axi_rdata(678) <= \<const0>\;
s_axi_rdata(677) <= \<const0>\;
s_axi_rdata(676) <= \<const0>\;
s_axi_rdata(675) <= \<const0>\;
s_axi_rdata(674) <= \<const0>\;
s_axi_rdata(673) <= \<const0>\;
s_axi_rdata(672) <= \<const0>\;
s_axi_rdata(671) <= \<const0>\;
s_axi_rdata(670) <= \<const0>\;
s_axi_rdata(669) <= \<const0>\;
s_axi_rdata(668) <= \<const0>\;
s_axi_rdata(667) <= \<const0>\;
s_axi_rdata(666) <= \<const0>\;
s_axi_rdata(665) <= \<const0>\;
s_axi_rdata(664) <= \<const0>\;
s_axi_rdata(663) <= \<const0>\;
s_axi_rdata(662) <= \<const0>\;
s_axi_rdata(661) <= \<const0>\;
s_axi_rdata(660) <= \<const0>\;
s_axi_rdata(659) <= \<const0>\;
s_axi_rdata(658) <= \<const0>\;
s_axi_rdata(657) <= \<const0>\;
s_axi_rdata(656) <= \<const0>\;
s_axi_rdata(655) <= \<const0>\;
s_axi_rdata(654) <= \<const0>\;
s_axi_rdata(653) <= \<const0>\;
s_axi_rdata(652) <= \<const0>\;
s_axi_rdata(651) <= \<const0>\;
s_axi_rdata(650) <= \<const0>\;
s_axi_rdata(649) <= \<const0>\;
s_axi_rdata(648) <= \<const0>\;
s_axi_rdata(647) <= \<const0>\;
s_axi_rdata(646) <= \<const0>\;
s_axi_rdata(645) <= \<const0>\;
s_axi_rdata(644) <= \<const0>\;
s_axi_rdata(643) <= \<const0>\;
s_axi_rdata(642) <= \<const0>\;
s_axi_rdata(641) <= \<const0>\;
s_axi_rdata(640) <= \<const0>\;
s_axi_rdata(639) <= \<const0>\;
s_axi_rdata(638) <= \<const0>\;
s_axi_rdata(637) <= \<const0>\;
s_axi_rdata(636) <= \<const0>\;
s_axi_rdata(635) <= \<const0>\;
s_axi_rdata(634) <= \<const0>\;
s_axi_rdata(633) <= \<const0>\;
s_axi_rdata(632) <= \<const0>\;
s_axi_rdata(631) <= \<const0>\;
s_axi_rdata(630) <= \<const0>\;
s_axi_rdata(629) <= \<const0>\;
s_axi_rdata(628) <= \<const0>\;
s_axi_rdata(627) <= \<const0>\;
s_axi_rdata(626) <= \<const0>\;
s_axi_rdata(625) <= \<const0>\;
s_axi_rdata(624) <= \<const0>\;
s_axi_rdata(623) <= \<const0>\;
s_axi_rdata(622) <= \<const0>\;
s_axi_rdata(621) <= \<const0>\;
s_axi_rdata(620) <= \<const0>\;
s_axi_rdata(619) <= \<const0>\;
s_axi_rdata(618) <= \<const0>\;
s_axi_rdata(617) <= \<const0>\;
s_axi_rdata(616) <= \<const0>\;
s_axi_rdata(615) <= \<const0>\;
s_axi_rdata(614) <= \<const0>\;
s_axi_rdata(613) <= \<const0>\;
s_axi_rdata(612) <= \<const0>\;
s_axi_rdata(611) <= \<const0>\;
s_axi_rdata(610) <= \<const0>\;
s_axi_rdata(609) <= \<const0>\;
s_axi_rdata(608) <= \<const0>\;
s_axi_rdata(607) <= \<const0>\;
s_axi_rdata(606) <= \<const0>\;
s_axi_rdata(605) <= \<const0>\;
s_axi_rdata(604) <= \<const0>\;
s_axi_rdata(603) <= \<const0>\;
s_axi_rdata(602) <= \<const0>\;
s_axi_rdata(601) <= \<const0>\;
s_axi_rdata(600) <= \<const0>\;
s_axi_rdata(599) <= \<const0>\;
s_axi_rdata(598) <= \<const0>\;
s_axi_rdata(597) <= \<const0>\;
s_axi_rdata(596) <= \<const0>\;
s_axi_rdata(595) <= \<const0>\;
s_axi_rdata(594) <= \<const0>\;
s_axi_rdata(593) <= \<const0>\;
s_axi_rdata(592) <= \<const0>\;
s_axi_rdata(591) <= \<const0>\;
s_axi_rdata(590) <= \<const0>\;
s_axi_rdata(589) <= \<const0>\;
s_axi_rdata(588) <= \<const0>\;
s_axi_rdata(587) <= \<const0>\;
s_axi_rdata(586) <= \<const0>\;
s_axi_rdata(585) <= \<const0>\;
s_axi_rdata(584) <= \<const0>\;
s_axi_rdata(583) <= \<const0>\;
s_axi_rdata(582) <= \<const0>\;
s_axi_rdata(581) <= \<const0>\;
s_axi_rdata(580) <= \<const0>\;
s_axi_rdata(579) <= \<const0>\;
s_axi_rdata(578) <= \<const0>\;
s_axi_rdata(577) <= \<const0>\;
s_axi_rdata(576) <= \<const0>\;
s_axi_rdata(575) <= \<const0>\;
s_axi_rdata(574) <= \<const0>\;
s_axi_rdata(573) <= \<const0>\;
s_axi_rdata(572) <= \<const0>\;
s_axi_rdata(571) <= \<const0>\;
s_axi_rdata(570) <= \<const0>\;
s_axi_rdata(569) <= \<const0>\;
s_axi_rdata(568) <= \<const0>\;
s_axi_rdata(567) <= \<const0>\;
s_axi_rdata(566) <= \<const0>\;
s_axi_rdata(565) <= \<const0>\;
s_axi_rdata(564) <= \<const0>\;
s_axi_rdata(563) <= \<const0>\;
s_axi_rdata(562) <= \<const0>\;
s_axi_rdata(561) <= \<const0>\;
s_axi_rdata(560) <= \<const0>\;
s_axi_rdata(559) <= \<const0>\;
s_axi_rdata(558) <= \<const0>\;
s_axi_rdata(557) <= \<const0>\;
s_axi_rdata(556) <= \<const0>\;
s_axi_rdata(555) <= \<const0>\;
s_axi_rdata(554) <= \<const0>\;
s_axi_rdata(553) <= \<const0>\;
s_axi_rdata(552) <= \<const0>\;
s_axi_rdata(551) <= \<const0>\;
s_axi_rdata(550) <= \<const0>\;
s_axi_rdata(549) <= \<const0>\;
s_axi_rdata(548) <= \<const0>\;
s_axi_rdata(547) <= \<const0>\;
s_axi_rdata(546) <= \<const0>\;
s_axi_rdata(545) <= \<const0>\;
s_axi_rdata(544) <= \<const0>\;
s_axi_rdata(543) <= \<const0>\;
s_axi_rdata(542) <= \<const0>\;
s_axi_rdata(541) <= \<const0>\;
s_axi_rdata(540) <= \<const0>\;
s_axi_rdata(539) <= \<const0>\;
s_axi_rdata(538) <= \<const0>\;
s_axi_rdata(537) <= \<const0>\;
s_axi_rdata(536) <= \<const0>\;
s_axi_rdata(535) <= \<const0>\;
s_axi_rdata(534) <= \<const0>\;
s_axi_rdata(533) <= \<const0>\;
s_axi_rdata(532) <= \<const0>\;
s_axi_rdata(531) <= \<const0>\;
s_axi_rdata(530) <= \<const0>\;
s_axi_rdata(529) <= \<const0>\;
s_axi_rdata(528) <= \<const0>\;
s_axi_rdata(527) <= \<const0>\;
s_axi_rdata(526) <= \<const0>\;
s_axi_rdata(525) <= \<const0>\;
s_axi_rdata(524) <= \<const0>\;
s_axi_rdata(523) <= \<const0>\;
s_axi_rdata(522) <= \<const0>\;
s_axi_rdata(521) <= \<const0>\;
s_axi_rdata(520) <= \<const0>\;
s_axi_rdata(519) <= \<const0>\;
s_axi_rdata(518) <= \<const0>\;
s_axi_rdata(517) <= \<const0>\;
s_axi_rdata(516) <= \<const0>\;
s_axi_rdata(515) <= \<const0>\;
s_axi_rdata(514) <= \<const0>\;
s_axi_rdata(513) <= \<const0>\;
s_axi_rdata(512) <= \<const0>\;
s_axi_rdata(511) <= \<const0>\;
s_axi_rdata(510) <= \<const0>\;
s_axi_rdata(509) <= \<const0>\;
s_axi_rdata(508) <= \<const0>\;
s_axi_rdata(507) <= \<const0>\;
s_axi_rdata(506) <= \<const0>\;
s_axi_rdata(505) <= \<const0>\;
s_axi_rdata(504) <= \<const0>\;
s_axi_rdata(503) <= \<const0>\;
s_axi_rdata(502) <= \<const0>\;
s_axi_rdata(501) <= \<const0>\;
s_axi_rdata(500) <= \<const0>\;
s_axi_rdata(499) <= \<const0>\;
s_axi_rdata(498) <= \<const0>\;
s_axi_rdata(497) <= \<const0>\;
s_axi_rdata(496) <= \<const0>\;
s_axi_rdata(495) <= \<const0>\;
s_axi_rdata(494) <= \<const0>\;
s_axi_rdata(493) <= \<const0>\;
s_axi_rdata(492) <= \<const0>\;
s_axi_rdata(491) <= \<const0>\;
s_axi_rdata(490) <= \<const0>\;
s_axi_rdata(489) <= \<const0>\;
s_axi_rdata(488) <= \<const0>\;
s_axi_rdata(487) <= \<const0>\;
s_axi_rdata(486) <= \<const0>\;
s_axi_rdata(485) <= \<const0>\;
s_axi_rdata(484) <= \<const0>\;
s_axi_rdata(483) <= \<const0>\;
s_axi_rdata(482) <= \<const0>\;
s_axi_rdata(481) <= \<const0>\;
s_axi_rdata(480) <= \<const0>\;
s_axi_rdata(479) <= \<const0>\;
s_axi_rdata(478) <= \<const0>\;
s_axi_rdata(477) <= \<const0>\;
s_axi_rdata(476) <= \<const0>\;
s_axi_rdata(475) <= \<const0>\;
s_axi_rdata(474) <= \<const0>\;
s_axi_rdata(473) <= \<const0>\;
s_axi_rdata(472) <= \<const0>\;
s_axi_rdata(471) <= \<const0>\;
s_axi_rdata(470) <= \<const0>\;
s_axi_rdata(469) <= \<const0>\;
s_axi_rdata(468) <= \<const0>\;
s_axi_rdata(467) <= \<const0>\;
s_axi_rdata(466) <= \<const0>\;
s_axi_rdata(465) <= \<const0>\;
s_axi_rdata(464) <= \<const0>\;
s_axi_rdata(463) <= \<const0>\;
s_axi_rdata(462) <= \<const0>\;
s_axi_rdata(461) <= \<const0>\;
s_axi_rdata(460) <= \<const0>\;
s_axi_rdata(459) <= \<const0>\;
s_axi_rdata(458) <= \<const0>\;
s_axi_rdata(457) <= \<const0>\;
s_axi_rdata(456) <= \<const0>\;
s_axi_rdata(455) <= \<const0>\;
s_axi_rdata(454) <= \<const0>\;
s_axi_rdata(453) <= \<const0>\;
s_axi_rdata(452) <= \<const0>\;
s_axi_rdata(451) <= \<const0>\;
s_axi_rdata(450) <= \<const0>\;
s_axi_rdata(449) <= \<const0>\;
s_axi_rdata(448) <= \<const0>\;
s_axi_rdata(447) <= \<const0>\;
s_axi_rdata(446) <= \<const0>\;
s_axi_rdata(445) <= \<const0>\;
s_axi_rdata(444) <= \<const0>\;
s_axi_rdata(443) <= \<const0>\;
s_axi_rdata(442) <= \<const0>\;
s_axi_rdata(441) <= \<const0>\;
s_axi_rdata(440) <= \<const0>\;
s_axi_rdata(439) <= \<const0>\;
s_axi_rdata(438) <= \<const0>\;
s_axi_rdata(437) <= \<const0>\;
s_axi_rdata(436) <= \<const0>\;
s_axi_rdata(435) <= \<const0>\;
s_axi_rdata(434) <= \<const0>\;
s_axi_rdata(433) <= \<const0>\;
s_axi_rdata(432) <= \<const0>\;
s_axi_rdata(431) <= \<const0>\;
s_axi_rdata(430) <= \<const0>\;
s_axi_rdata(429) <= \<const0>\;
s_axi_rdata(428) <= \<const0>\;
s_axi_rdata(427) <= \<const0>\;
s_axi_rdata(426) <= \<const0>\;
s_axi_rdata(425) <= \<const0>\;
s_axi_rdata(424) <= \<const0>\;
s_axi_rdata(423) <= \<const0>\;
s_axi_rdata(422) <= \<const0>\;
s_axi_rdata(421) <= \<const0>\;
s_axi_rdata(420) <= \<const0>\;
s_axi_rdata(419) <= \<const0>\;
s_axi_rdata(418) <= \<const0>\;
s_axi_rdata(417) <= \<const0>\;
s_axi_rdata(416) <= \<const0>\;
s_axi_rdata(415) <= \<const0>\;
s_axi_rdata(414) <= \<const0>\;
s_axi_rdata(413) <= \<const0>\;
s_axi_rdata(412) <= \<const0>\;
s_axi_rdata(411) <= \<const0>\;
s_axi_rdata(410) <= \<const0>\;
s_axi_rdata(409) <= \<const0>\;
s_axi_rdata(408) <= \<const0>\;
s_axi_rdata(407) <= \<const0>\;
s_axi_rdata(406) <= \<const0>\;
s_axi_rdata(405) <= \<const0>\;
s_axi_rdata(404) <= \<const0>\;
s_axi_rdata(403) <= \<const0>\;
s_axi_rdata(402) <= \<const0>\;
s_axi_rdata(401) <= \<const0>\;
s_axi_rdata(400) <= \<const0>\;
s_axi_rdata(399) <= \<const0>\;
s_axi_rdata(398) <= \<const0>\;
s_axi_rdata(397) <= \<const0>\;
s_axi_rdata(396) <= \<const0>\;
s_axi_rdata(395) <= \<const0>\;
s_axi_rdata(394) <= \<const0>\;
s_axi_rdata(393) <= \<const0>\;
s_axi_rdata(392) <= \<const0>\;
s_axi_rdata(391) <= \<const0>\;
s_axi_rdata(390) <= \<const0>\;
s_axi_rdata(389) <= \<const0>\;
s_axi_rdata(388) <= \<const0>\;
s_axi_rdata(387) <= \<const0>\;
s_axi_rdata(386) <= \<const0>\;
s_axi_rdata(385) <= \<const0>\;
s_axi_rdata(384) <= \<const0>\;
s_axi_rdata(383) <= \<const0>\;
s_axi_rdata(382) <= \<const0>\;
s_axi_rdata(381) <= \<const0>\;
s_axi_rdata(380) <= \<const0>\;
s_axi_rdata(379) <= \<const0>\;
s_axi_rdata(378) <= \<const0>\;
s_axi_rdata(377) <= \<const0>\;
s_axi_rdata(376) <= \<const0>\;
s_axi_rdata(375) <= \<const0>\;
s_axi_rdata(374) <= \<const0>\;
s_axi_rdata(373) <= \<const0>\;
s_axi_rdata(372) <= \<const0>\;
s_axi_rdata(371) <= \<const0>\;
s_axi_rdata(370) <= \<const0>\;
s_axi_rdata(369) <= \<const0>\;
s_axi_rdata(368) <= \<const0>\;
s_axi_rdata(367) <= \<const0>\;
s_axi_rdata(366) <= \<const0>\;
s_axi_rdata(365) <= \<const0>\;
s_axi_rdata(364) <= \<const0>\;
s_axi_rdata(363) <= \<const0>\;
s_axi_rdata(362) <= \<const0>\;
s_axi_rdata(361) <= \<const0>\;
s_axi_rdata(360) <= \<const0>\;
s_axi_rdata(359) <= \<const0>\;
s_axi_rdata(358) <= \<const0>\;
s_axi_rdata(357) <= \<const0>\;
s_axi_rdata(356) <= \<const0>\;
s_axi_rdata(355) <= \<const0>\;
s_axi_rdata(354) <= \<const0>\;
s_axi_rdata(353) <= \<const0>\;
s_axi_rdata(352) <= \<const0>\;
s_axi_rdata(351) <= \<const0>\;
s_axi_rdata(350) <= \<const0>\;
s_axi_rdata(349) <= \<const0>\;
s_axi_rdata(348) <= \<const0>\;
s_axi_rdata(347) <= \<const0>\;
s_axi_rdata(346) <= \<const0>\;
s_axi_rdata(345) <= \<const0>\;
s_axi_rdata(344) <= \<const0>\;
s_axi_rdata(343) <= \<const0>\;
s_axi_rdata(342) <= \<const0>\;
s_axi_rdata(341) <= \<const0>\;
s_axi_rdata(340) <= \<const0>\;
s_axi_rdata(339) <= \<const0>\;
s_axi_rdata(338) <= \<const0>\;
s_axi_rdata(337) <= \<const0>\;
s_axi_rdata(336) <= \<const0>\;
s_axi_rdata(335) <= \<const0>\;
s_axi_rdata(334) <= \<const0>\;
s_axi_rdata(333) <= \<const0>\;
s_axi_rdata(332) <= \<const0>\;
s_axi_rdata(331) <= \<const0>\;
s_axi_rdata(330) <= \<const0>\;
s_axi_rdata(329) <= \<const0>\;
s_axi_rdata(328) <= \<const0>\;
s_axi_rdata(327) <= \<const0>\;
s_axi_rdata(326) <= \<const0>\;
s_axi_rdata(325) <= \<const0>\;
s_axi_rdata(324) <= \<const0>\;
s_axi_rdata(323) <= \<const0>\;
s_axi_rdata(322) <= \<const0>\;
s_axi_rdata(321) <= \<const0>\;
s_axi_rdata(320) <= \<const0>\;
s_axi_rdata(319) <= \<const0>\;
s_axi_rdata(318) <= \<const0>\;
s_axi_rdata(317) <= \<const0>\;
s_axi_rdata(316) <= \<const0>\;
s_axi_rdata(315) <= \<const0>\;
s_axi_rdata(314) <= \<const0>\;
s_axi_rdata(313) <= \<const0>\;
s_axi_rdata(312) <= \<const0>\;
s_axi_rdata(311) <= \<const0>\;
s_axi_rdata(310) <= \<const0>\;
s_axi_rdata(309) <= \<const0>\;
s_axi_rdata(308) <= \<const0>\;
s_axi_rdata(307) <= \<const0>\;
s_axi_rdata(306) <= \<const0>\;
s_axi_rdata(305) <= \<const0>\;
s_axi_rdata(304) <= \<const0>\;
s_axi_rdata(303) <= \<const0>\;
s_axi_rdata(302) <= \<const0>\;
s_axi_rdata(301) <= \<const0>\;
s_axi_rdata(300) <= \<const0>\;
s_axi_rdata(299) <= \<const0>\;
s_axi_rdata(298) <= \<const0>\;
s_axi_rdata(297) <= \<const0>\;
s_axi_rdata(296) <= \<const0>\;
s_axi_rdata(295) <= \<const0>\;
s_axi_rdata(294) <= \<const0>\;
s_axi_rdata(293) <= \<const0>\;
s_axi_rdata(292) <= \<const0>\;
s_axi_rdata(291) <= \<const0>\;
s_axi_rdata(290) <= \<const0>\;
s_axi_rdata(289) <= \<const0>\;
s_axi_rdata(288) <= \<const0>\;
s_axi_rdata(287) <= \<const0>\;
s_axi_rdata(286) <= \<const0>\;
s_axi_rdata(285) <= \<const0>\;
s_axi_rdata(284) <= \<const0>\;
s_axi_rdata(283) <= \<const0>\;
s_axi_rdata(282) <= \<const0>\;
s_axi_rdata(281) <= \<const0>\;
s_axi_rdata(280) <= \<const0>\;
s_axi_rdata(279) <= \<const0>\;
s_axi_rdata(278) <= \<const0>\;
s_axi_rdata(277) <= \<const0>\;
s_axi_rdata(276) <= \<const0>\;
s_axi_rdata(275) <= \<const0>\;
s_axi_rdata(274) <= \<const0>\;
s_axi_rdata(273) <= \<const0>\;
s_axi_rdata(272) <= \<const0>\;
s_axi_rdata(271) <= \<const0>\;
s_axi_rdata(270) <= \<const0>\;
s_axi_rdata(269) <= \<const0>\;
s_axi_rdata(268) <= \<const0>\;
s_axi_rdata(267) <= \<const0>\;
s_axi_rdata(266) <= \<const0>\;
s_axi_rdata(265) <= \<const0>\;
s_axi_rdata(264) <= \<const0>\;
s_axi_rdata(263) <= \<const0>\;
s_axi_rdata(262) <= \<const0>\;
s_axi_rdata(261) <= \<const0>\;
s_axi_rdata(260) <= \<const0>\;
s_axi_rdata(259) <= \<const0>\;
s_axi_rdata(258) <= \<const0>\;
s_axi_rdata(257) <= \<const0>\;
s_axi_rdata(256) <= \<const0>\;
s_axi_rdata(255) <= \<const0>\;
s_axi_rdata(254) <= \<const0>\;
s_axi_rdata(253) <= \<const0>\;
s_axi_rdata(252) <= \<const0>\;
s_axi_rdata(251) <= \<const0>\;
s_axi_rdata(250) <= \<const0>\;
s_axi_rdata(249) <= \<const0>\;
s_axi_rdata(248) <= \<const0>\;
s_axi_rdata(247) <= \<const0>\;
s_axi_rdata(246) <= \<const0>\;
s_axi_rdata(245) <= \<const0>\;
s_axi_rdata(244) <= \<const0>\;
s_axi_rdata(243) <= \<const0>\;
s_axi_rdata(242) <= \<const0>\;
s_axi_rdata(241) <= \<const0>\;
s_axi_rdata(240) <= \<const0>\;
s_axi_rdata(239) <= \<const0>\;
s_axi_rdata(238) <= \<const0>\;
s_axi_rdata(237) <= \<const0>\;
s_axi_rdata(236) <= \<const0>\;
s_axi_rdata(235) <= \<const0>\;
s_axi_rdata(234) <= \<const0>\;
s_axi_rdata(233) <= \<const0>\;
s_axi_rdata(232) <= \<const0>\;
s_axi_rdata(231) <= \<const0>\;
s_axi_rdata(230) <= \<const0>\;
s_axi_rdata(229) <= \<const0>\;
s_axi_rdata(228) <= \<const0>\;
s_axi_rdata(227) <= \<const0>\;
s_axi_rdata(226) <= \<const0>\;
s_axi_rdata(225) <= \<const0>\;
s_axi_rdata(224) <= \<const0>\;
s_axi_rdata(223) <= \<const0>\;
s_axi_rdata(222) <= \<const0>\;
s_axi_rdata(221) <= \<const0>\;
s_axi_rdata(220) <= \<const0>\;
s_axi_rdata(219) <= \<const0>\;
s_axi_rdata(218) <= \<const0>\;
s_axi_rdata(217) <= \<const0>\;
s_axi_rdata(216) <= \<const0>\;
s_axi_rdata(215) <= \<const0>\;
s_axi_rdata(214) <= \<const0>\;
s_axi_rdata(213) <= \<const0>\;
s_axi_rdata(212) <= \<const0>\;
s_axi_rdata(211) <= \<const0>\;
s_axi_rdata(210) <= \<const0>\;
s_axi_rdata(209) <= \<const0>\;
s_axi_rdata(208) <= \<const0>\;
s_axi_rdata(207) <= \<const0>\;
s_axi_rdata(206) <= \<const0>\;
s_axi_rdata(205) <= \<const0>\;
s_axi_rdata(204) <= \<const0>\;
s_axi_rdata(203) <= \<const0>\;
s_axi_rdata(202) <= \<const0>\;
s_axi_rdata(201) <= \<const0>\;
s_axi_rdata(200) <= \<const0>\;
s_axi_rdata(199) <= \<const0>\;
s_axi_rdata(198) <= \<const0>\;
s_axi_rdata(197) <= \<const0>\;
s_axi_rdata(196) <= \<const0>\;
s_axi_rdata(195) <= \<const0>\;
s_axi_rdata(194) <= \<const0>\;
s_axi_rdata(193) <= \<const0>\;
s_axi_rdata(192) <= \<const0>\;
s_axi_rdata(191) <= \<const0>\;
s_axi_rdata(190) <= \<const0>\;
s_axi_rdata(189) <= \<const0>\;
s_axi_rdata(188) <= \<const0>\;
s_axi_rdata(187) <= \<const0>\;
s_axi_rdata(186) <= \<const0>\;
s_axi_rdata(185) <= \<const0>\;
s_axi_rdata(184) <= \<const0>\;
s_axi_rdata(183) <= \<const0>\;
s_axi_rdata(182) <= \<const0>\;
s_axi_rdata(181) <= \<const0>\;
s_axi_rdata(180) <= \<const0>\;
s_axi_rdata(179) <= \<const0>\;
s_axi_rdata(178) <= \<const0>\;
s_axi_rdata(177) <= \<const0>\;
s_axi_rdata(176) <= \<const0>\;
s_axi_rdata(175) <= \<const0>\;
s_axi_rdata(174) <= \<const0>\;
s_axi_rdata(173) <= \<const0>\;
s_axi_rdata(172) <= \<const0>\;
s_axi_rdata(171) <= \<const0>\;
s_axi_rdata(170) <= \<const0>\;
s_axi_rdata(169) <= \<const0>\;
s_axi_rdata(168) <= \<const0>\;
s_axi_rdata(167) <= \<const0>\;
s_axi_rdata(166) <= \<const0>\;
s_axi_rdata(165) <= \<const0>\;
s_axi_rdata(164) <= \<const0>\;
s_axi_rdata(163) <= \<const0>\;
s_axi_rdata(162) <= \<const0>\;
s_axi_rdata(161) <= \<const0>\;
s_axi_rdata(160) <= \<const0>\;
s_axi_rdata(159) <= \<const0>\;
s_axi_rdata(158) <= \<const0>\;
s_axi_rdata(157) <= \<const0>\;
s_axi_rdata(156) <= \<const0>\;
s_axi_rdata(155) <= \<const0>\;
s_axi_rdata(154) <= \<const0>\;
s_axi_rdata(153) <= \<const0>\;
s_axi_rdata(152) <= \<const0>\;
s_axi_rdata(151) <= \<const0>\;
s_axi_rdata(150) <= \<const0>\;
s_axi_rdata(149) <= \<const0>\;
s_axi_rdata(148) <= \<const0>\;
s_axi_rdata(147) <= \<const0>\;
s_axi_rdata(146) <= \<const0>\;
s_axi_rdata(145) <= \<const0>\;
s_axi_rdata(144) <= \<const0>\;
s_axi_rdata(143) <= \<const0>\;
s_axi_rdata(142) <= \<const0>\;
s_axi_rdata(141) <= \<const0>\;
s_axi_rdata(140) <= \<const0>\;
s_axi_rdata(139) <= \<const0>\;
s_axi_rdata(138) <= \<const0>\;
s_axi_rdata(137) <= \<const0>\;
s_axi_rdata(136) <= \<const0>\;
s_axi_rdata(135) <= \<const0>\;
s_axi_rdata(134) <= \<const0>\;
s_axi_rdata(133) <= \<const0>\;
s_axi_rdata(132) <= \<const0>\;
s_axi_rdata(131) <= \<const0>\;
s_axi_rdata(130) <= \<const0>\;
s_axi_rdata(129) <= \<const0>\;
s_axi_rdata(128) <= \<const0>\;
s_axi_rdata(127) <= \<const0>\;
s_axi_rdata(126) <= \<const0>\;
s_axi_rdata(125) <= \<const0>\;
s_axi_rdata(124) <= \<const0>\;
s_axi_rdata(123) <= \<const0>\;
s_axi_rdata(122) <= \<const0>\;
s_axi_rdata(121) <= \<const0>\;
s_axi_rdata(120) <= \<const0>\;
s_axi_rdata(119) <= \<const0>\;
s_axi_rdata(118) <= \<const0>\;
s_axi_rdata(117) <= \<const0>\;
s_axi_rdata(116) <= \<const0>\;
s_axi_rdata(115) <= \<const0>\;
s_axi_rdata(114) <= \<const0>\;
s_axi_rdata(113) <= \<const0>\;
s_axi_rdata(112) <= \<const0>\;
s_axi_rdata(111) <= \<const0>\;
s_axi_rdata(110) <= \<const0>\;
s_axi_rdata(109) <= \<const0>\;
s_axi_rdata(108) <= \<const0>\;
s_axi_rdata(107) <= \<const0>\;
s_axi_rdata(106) <= \<const0>\;
s_axi_rdata(105) <= \<const0>\;
s_axi_rdata(104) <= \<const0>\;
s_axi_rdata(103) <= \<const0>\;
s_axi_rdata(102) <= \<const0>\;
s_axi_rdata(101) <= \<const0>\;
s_axi_rdata(100) <= \<const0>\;
s_axi_rdata(99) <= \<const0>\;
s_axi_rdata(98) <= \<const0>\;
s_axi_rdata(97) <= \<const0>\;
s_axi_rdata(96) <= \<const0>\;
s_axi_rdata(95) <= \<const0>\;
s_axi_rdata(94) <= \<const0>\;
s_axi_rdata(93) <= \<const0>\;
s_axi_rdata(92) <= \<const0>\;
s_axi_rdata(91) <= \<const0>\;
s_axi_rdata(90) <= \<const0>\;
s_axi_rdata(89) <= \<const0>\;
s_axi_rdata(88) <= \<const0>\;
s_axi_rdata(87) <= \<const0>\;
s_axi_rdata(86) <= \<const0>\;
s_axi_rdata(85) <= \<const0>\;
s_axi_rdata(84) <= \<const0>\;
s_axi_rdata(83) <= \<const0>\;
s_axi_rdata(82) <= \<const0>\;
s_axi_rdata(81) <= \<const0>\;
s_axi_rdata(80) <= \<const0>\;
s_axi_rdata(79) <= \<const0>\;
s_axi_rdata(78) <= \<const0>\;
s_axi_rdata(77) <= \<const0>\;
s_axi_rdata(76) <= \<const0>\;
s_axi_rdata(75) <= \<const0>\;
s_axi_rdata(74) <= \<const0>\;
s_axi_rdata(73) <= \<const0>\;
s_axi_rdata(72) <= \<const0>\;
s_axi_rdata(71) <= \<const0>\;
s_axi_rdata(70) <= \<const0>\;
s_axi_rdata(69) <= \<const0>\;
s_axi_rdata(68) <= \<const0>\;
s_axi_rdata(67) <= \<const0>\;
s_axi_rdata(66) <= \<const0>\;
s_axi_rdata(65) <= \<const0>\;
s_axi_rdata(64) <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.Instructions_blk_mem_gen_v8_2_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(799 downto 0) => douta(799 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Instructions is
port (
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
douta : out STD_LOGIC_VECTOR ( 799 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of Instructions : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of Instructions : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of Instructions : entity is "blk_mem_gen_v8_2,Vivado 2014.4";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of Instructions : entity is "Instructions,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of Instructions : entity is "Instructions,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=Instructions.mif,C_INIT_FILE=Instructions.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=800,C_READ_WIDTH_A=800,C_WRITE_DEPTH_A=600,C_READ_DEPTH_A=600,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=800,C_READ_WIDTH_B=800,C_WRITE_DEPTH_B=600,C_READ_DEPTH_B=600,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=22,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 60.4532 mW}";
end Instructions;
architecture STRUCTURE of Instructions is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 799 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 799 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "22";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 60.4532 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "Instructions.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "Instructions.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 3;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 600;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 600;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 800;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 800;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 600;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 600;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 800;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 800;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\Instructions_blk_mem_gen_v8_2__parameterized0\
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9) => '0',
addrb(8) => '0',
addrb(7) => '0',
addrb(6) => '0',
addrb(5) => '0',
addrb(4) => '0',
addrb(3) => '0',
addrb(2) => '0',
addrb(1) => '0',
addrb(0) => '0',
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
dina(799) => '0',
dina(798) => '0',
dina(797) => '0',
dina(796) => '0',
dina(795) => '0',
dina(794) => '0',
dina(793) => '0',
dina(792) => '0',
dina(791) => '0',
dina(790) => '0',
dina(789) => '0',
dina(788) => '0',
dina(787) => '0',
dina(786) => '0',
dina(785) => '0',
dina(784) => '0',
dina(783) => '0',
dina(782) => '0',
dina(781) => '0',
dina(780) => '0',
dina(779) => '0',
dina(778) => '0',
dina(777) => '0',
dina(776) => '0',
dina(775) => '0',
dina(774) => '0',
dina(773) => '0',
dina(772) => '0',
dina(771) => '0',
dina(770) => '0',
dina(769) => '0',
dina(768) => '0',
dina(767) => '0',
dina(766) => '0',
dina(765) => '0',
dina(764) => '0',
dina(763) => '0',
dina(762) => '0',
dina(761) => '0',
dina(760) => '0',
dina(759) => '0',
dina(758) => '0',
dina(757) => '0',
dina(756) => '0',
dina(755) => '0',
dina(754) => '0',
dina(753) => '0',
dina(752) => '0',
dina(751) => '0',
dina(750) => '0',
dina(749) => '0',
dina(748) => '0',
dina(747) => '0',
dina(746) => '0',
dina(745) => '0',
dina(744) => '0',
dina(743) => '0',
dina(742) => '0',
dina(741) => '0',
dina(740) => '0',
dina(739) => '0',
dina(738) => '0',
dina(737) => '0',
dina(736) => '0',
dina(735) => '0',
dina(734) => '0',
dina(733) => '0',
dina(732) => '0',
dina(731) => '0',
dina(730) => '0',
dina(729) => '0',
dina(728) => '0',
dina(727) => '0',
dina(726) => '0',
dina(725) => '0',
dina(724) => '0',
dina(723) => '0',
dina(722) => '0',
dina(721) => '0',
dina(720) => '0',
dina(719) => '0',
dina(718) => '0',
dina(717) => '0',
dina(716) => '0',
dina(715) => '0',
dina(714) => '0',
dina(713) => '0',
dina(712) => '0',
dina(711) => '0',
dina(710) => '0',
dina(709) => '0',
dina(708) => '0',
dina(707) => '0',
dina(706) => '0',
dina(705) => '0',
dina(704) => '0',
dina(703) => '0',
dina(702) => '0',
dina(701) => '0',
dina(700) => '0',
dina(699) => '0',
dina(698) => '0',
dina(697) => '0',
dina(696) => '0',
dina(695) => '0',
dina(694) => '0',
dina(693) => '0',
dina(692) => '0',
dina(691) => '0',
dina(690) => '0',
dina(689) => '0',
dina(688) => '0',
dina(687) => '0',
dina(686) => '0',
dina(685) => '0',
dina(684) => '0',
dina(683) => '0',
dina(682) => '0',
dina(681) => '0',
dina(680) => '0',
dina(679) => '0',
dina(678) => '0',
dina(677) => '0',
dina(676) => '0',
dina(675) => '0',
dina(674) => '0',
dina(673) => '0',
dina(672) => '0',
dina(671) => '0',
dina(670) => '0',
dina(669) => '0',
dina(668) => '0',
dina(667) => '0',
dina(666) => '0',
dina(665) => '0',
dina(664) => '0',
dina(663) => '0',
dina(662) => '0',
dina(661) => '0',
dina(660) => '0',
dina(659) => '0',
dina(658) => '0',
dina(657) => '0',
dina(656) => '0',
dina(655) => '0',
dina(654) => '0',
dina(653) => '0',
dina(652) => '0',
dina(651) => '0',
dina(650) => '0',
dina(649) => '0',
dina(648) => '0',
dina(647) => '0',
dina(646) => '0',
dina(645) => '0',
dina(644) => '0',
dina(643) => '0',
dina(642) => '0',
dina(641) => '0',
dina(640) => '0',
dina(639) => '0',
dina(638) => '0',
dina(637) => '0',
dina(636) => '0',
dina(635) => '0',
dina(634) => '0',
dina(633) => '0',
dina(632) => '0',
dina(631) => '0',
dina(630) => '0',
dina(629) => '0',
dina(628) => '0',
dina(627) => '0',
dina(626) => '0',
dina(625) => '0',
dina(624) => '0',
dina(623) => '0',
dina(622) => '0',
dina(621) => '0',
dina(620) => '0',
dina(619) => '0',
dina(618) => '0',
dina(617) => '0',
dina(616) => '0',
dina(615) => '0',
dina(614) => '0',
dina(613) => '0',
dina(612) => '0',
dina(611) => '0',
dina(610) => '0',
dina(609) => '0',
dina(608) => '0',
dina(607) => '0',
dina(606) => '0',
dina(605) => '0',
dina(604) => '0',
dina(603) => '0',
dina(602) => '0',
dina(601) => '0',
dina(600) => '0',
dina(599) => '0',
dina(598) => '0',
dina(597) => '0',
dina(596) => '0',
dina(595) => '0',
dina(594) => '0',
dina(593) => '0',
dina(592) => '0',
dina(591) => '0',
dina(590) => '0',
dina(589) => '0',
dina(588) => '0',
dina(587) => '0',
dina(586) => '0',
dina(585) => '0',
dina(584) => '0',
dina(583) => '0',
dina(582) => '0',
dina(581) => '0',
dina(580) => '0',
dina(579) => '0',
dina(578) => '0',
dina(577) => '0',
dina(576) => '0',
dina(575) => '0',
dina(574) => '0',
dina(573) => '0',
dina(572) => '0',
dina(571) => '0',
dina(570) => '0',
dina(569) => '0',
dina(568) => '0',
dina(567) => '0',
dina(566) => '0',
dina(565) => '0',
dina(564) => '0',
dina(563) => '0',
dina(562) => '0',
dina(561) => '0',
dina(560) => '0',
dina(559) => '0',
dina(558) => '0',
dina(557) => '0',
dina(556) => '0',
dina(555) => '0',
dina(554) => '0',
dina(553) => '0',
dina(552) => '0',
dina(551) => '0',
dina(550) => '0',
dina(549) => '0',
dina(548) => '0',
dina(547) => '0',
dina(546) => '0',
dina(545) => '0',
dina(544) => '0',
dina(543) => '0',
dina(542) => '0',
dina(541) => '0',
dina(540) => '0',
dina(539) => '0',
dina(538) => '0',
dina(537) => '0',
dina(536) => '0',
dina(535) => '0',
dina(534) => '0',
dina(533) => '0',
dina(532) => '0',
dina(531) => '0',
dina(530) => '0',
dina(529) => '0',
dina(528) => '0',
dina(527) => '0',
dina(526) => '0',
dina(525) => '0',
dina(524) => '0',
dina(523) => '0',
dina(522) => '0',
dina(521) => '0',
dina(520) => '0',
dina(519) => '0',
dina(518) => '0',
dina(517) => '0',
dina(516) => '0',
dina(515) => '0',
dina(514) => '0',
dina(513) => '0',
dina(512) => '0',
dina(511) => '0',
dina(510) => '0',
dina(509) => '0',
dina(508) => '0',
dina(507) => '0',
dina(506) => '0',
dina(505) => '0',
dina(504) => '0',
dina(503) => '0',
dina(502) => '0',
dina(501) => '0',
dina(500) => '0',
dina(499) => '0',
dina(498) => '0',
dina(497) => '0',
dina(496) => '0',
dina(495) => '0',
dina(494) => '0',
dina(493) => '0',
dina(492) => '0',
dina(491) => '0',
dina(490) => '0',
dina(489) => '0',
dina(488) => '0',
dina(487) => '0',
dina(486) => '0',
dina(485) => '0',
dina(484) => '0',
dina(483) => '0',
dina(482) => '0',
dina(481) => '0',
dina(480) => '0',
dina(479) => '0',
dina(478) => '0',
dina(477) => '0',
dina(476) => '0',
dina(475) => '0',
dina(474) => '0',
dina(473) => '0',
dina(472) => '0',
dina(471) => '0',
dina(470) => '0',
dina(469) => '0',
dina(468) => '0',
dina(467) => '0',
dina(466) => '0',
dina(465) => '0',
dina(464) => '0',
dina(463) => '0',
dina(462) => '0',
dina(461) => '0',
dina(460) => '0',
dina(459) => '0',
dina(458) => '0',
dina(457) => '0',
dina(456) => '0',
dina(455) => '0',
dina(454) => '0',
dina(453) => '0',
dina(452) => '0',
dina(451) => '0',
dina(450) => '0',
dina(449) => '0',
dina(448) => '0',
dina(447) => '0',
dina(446) => '0',
dina(445) => '0',
dina(444) => '0',
dina(443) => '0',
dina(442) => '0',
dina(441) => '0',
dina(440) => '0',
dina(439) => '0',
dina(438) => '0',
dina(437) => '0',
dina(436) => '0',
dina(435) => '0',
dina(434) => '0',
dina(433) => '0',
dina(432) => '0',
dina(431) => '0',
dina(430) => '0',
dina(429) => '0',
dina(428) => '0',
dina(427) => '0',
dina(426) => '0',
dina(425) => '0',
dina(424) => '0',
dina(423) => '0',
dina(422) => '0',
dina(421) => '0',
dina(420) => '0',
dina(419) => '0',
dina(418) => '0',
dina(417) => '0',
dina(416) => '0',
dina(415) => '0',
dina(414) => '0',
dina(413) => '0',
dina(412) => '0',
dina(411) => '0',
dina(410) => '0',
dina(409) => '0',
dina(408) => '0',
dina(407) => '0',
dina(406) => '0',
dina(405) => '0',
dina(404) => '0',
dina(403) => '0',
dina(402) => '0',
dina(401) => '0',
dina(400) => '0',
dina(399) => '0',
dina(398) => '0',
dina(397) => '0',
dina(396) => '0',
dina(395) => '0',
dina(394) => '0',
dina(393) => '0',
dina(392) => '0',
dina(391) => '0',
dina(390) => '0',
dina(389) => '0',
dina(388) => '0',
dina(387) => '0',
dina(386) => '0',
dina(385) => '0',
dina(384) => '0',
dina(383) => '0',
dina(382) => '0',
dina(381) => '0',
dina(380) => '0',
dina(379) => '0',
dina(378) => '0',
dina(377) => '0',
dina(376) => '0',
dina(375) => '0',
dina(374) => '0',
dina(373) => '0',
dina(372) => '0',
dina(371) => '0',
dina(370) => '0',
dina(369) => '0',
dina(368) => '0',
dina(367) => '0',
dina(366) => '0',
dina(365) => '0',
dina(364) => '0',
dina(363) => '0',
dina(362) => '0',
dina(361) => '0',
dina(360) => '0',
dina(359) => '0',
dina(358) => '0',
dina(357) => '0',
dina(356) => '0',
dina(355) => '0',
dina(354) => '0',
dina(353) => '0',
dina(352) => '0',
dina(351) => '0',
dina(350) => '0',
dina(349) => '0',
dina(348) => '0',
dina(347) => '0',
dina(346) => '0',
dina(345) => '0',
dina(344) => '0',
dina(343) => '0',
dina(342) => '0',
dina(341) => '0',
dina(340) => '0',
dina(339) => '0',
dina(338) => '0',
dina(337) => '0',
dina(336) => '0',
dina(335) => '0',
dina(334) => '0',
dina(333) => '0',
dina(332) => '0',
dina(331) => '0',
dina(330) => '0',
dina(329) => '0',
dina(328) => '0',
dina(327) => '0',
dina(326) => '0',
dina(325) => '0',
dina(324) => '0',
dina(323) => '0',
dina(322) => '0',
dina(321) => '0',
dina(320) => '0',
dina(319) => '0',
dina(318) => '0',
dina(317) => '0',
dina(316) => '0',
dina(315) => '0',
dina(314) => '0',
dina(313) => '0',
dina(312) => '0',
dina(311) => '0',
dina(310) => '0',
dina(309) => '0',
dina(308) => '0',
dina(307) => '0',
dina(306) => '0',
dina(305) => '0',
dina(304) => '0',
dina(303) => '0',
dina(302) => '0',
dina(301) => '0',
dina(300) => '0',
dina(299) => '0',
dina(298) => '0',
dina(297) => '0',
dina(296) => '0',
dina(295) => '0',
dina(294) => '0',
dina(293) => '0',
dina(292) => '0',
dina(291) => '0',
dina(290) => '0',
dina(289) => '0',
dina(288) => '0',
dina(287) => '0',
dina(286) => '0',
dina(285) => '0',
dina(284) => '0',
dina(283) => '0',
dina(282) => '0',
dina(281) => '0',
dina(280) => '0',
dina(279) => '0',
dina(278) => '0',
dina(277) => '0',
dina(276) => '0',
dina(275) => '0',
dina(274) => '0',
dina(273) => '0',
dina(272) => '0',
dina(271) => '0',
dina(270) => '0',
dina(269) => '0',
dina(268) => '0',
dina(267) => '0',
dina(266) => '0',
dina(265) => '0',
dina(264) => '0',
dina(263) => '0',
dina(262) => '0',
dina(261) => '0',
dina(260) => '0',
dina(259) => '0',
dina(258) => '0',
dina(257) => '0',
dina(256) => '0',
dina(255) => '0',
dina(254) => '0',
dina(253) => '0',
dina(252) => '0',
dina(251) => '0',
dina(250) => '0',
dina(249) => '0',
dina(248) => '0',
dina(247) => '0',
dina(246) => '0',
dina(245) => '0',
dina(244) => '0',
dina(243) => '0',
dina(242) => '0',
dina(241) => '0',
dina(240) => '0',
dina(239) => '0',
dina(238) => '0',
dina(237) => '0',
dina(236) => '0',
dina(235) => '0',
dina(234) => '0',
dina(233) => '0',
dina(232) => '0',
dina(231) => '0',
dina(230) => '0',
dina(229) => '0',
dina(228) => '0',
dina(227) => '0',
dina(226) => '0',
dina(225) => '0',
dina(224) => '0',
dina(223) => '0',
dina(222) => '0',
dina(221) => '0',
dina(220) => '0',
dina(219) => '0',
dina(218) => '0',
dina(217) => '0',
dina(216) => '0',
dina(215) => '0',
dina(214) => '0',
dina(213) => '0',
dina(212) => '0',
dina(211) => '0',
dina(210) => '0',
dina(209) => '0',
dina(208) => '0',
dina(207) => '0',
dina(206) => '0',
dina(205) => '0',
dina(204) => '0',
dina(203) => '0',
dina(202) => '0',
dina(201) => '0',
dina(200) => '0',
dina(199) => '0',
dina(198) => '0',
dina(197) => '0',
dina(196) => '0',
dina(195) => '0',
dina(194) => '0',
dina(193) => '0',
dina(192) => '0',
dina(191) => '0',
dina(190) => '0',
dina(189) => '0',
dina(188) => '0',
dina(187) => '0',
dina(186) => '0',
dina(185) => '0',
dina(184) => '0',
dina(183) => '0',
dina(182) => '0',
dina(181) => '0',
dina(180) => '0',
dina(179) => '0',
dina(178) => '0',
dina(177) => '0',
dina(176) => '0',
dina(175) => '0',
dina(174) => '0',
dina(173) => '0',
dina(172) => '0',
dina(171) => '0',
dina(170) => '0',
dina(169) => '0',
dina(168) => '0',
dina(167) => '0',
dina(166) => '0',
dina(165) => '0',
dina(164) => '0',
dina(163) => '0',
dina(162) => '0',
dina(161) => '0',
dina(160) => '0',
dina(159) => '0',
dina(158) => '0',
dina(157) => '0',
dina(156) => '0',
dina(155) => '0',
dina(154) => '0',
dina(153) => '0',
dina(152) => '0',
dina(151) => '0',
dina(150) => '0',
dina(149) => '0',
dina(148) => '0',
dina(147) => '0',
dina(146) => '0',
dina(145) => '0',
dina(144) => '0',
dina(143) => '0',
dina(142) => '0',
dina(141) => '0',
dina(140) => '0',
dina(139) => '0',
dina(138) => '0',
dina(137) => '0',
dina(136) => '0',
dina(135) => '0',
dina(134) => '0',
dina(133) => '0',
dina(132) => '0',
dina(131) => '0',
dina(130) => '0',
dina(129) => '0',
dina(128) => '0',
dina(127) => '0',
dina(126) => '0',
dina(125) => '0',
dina(124) => '0',
dina(123) => '0',
dina(122) => '0',
dina(121) => '0',
dina(120) => '0',
dina(119) => '0',
dina(118) => '0',
dina(117) => '0',
dina(116) => '0',
dina(115) => '0',
dina(114) => '0',
dina(113) => '0',
dina(112) => '0',
dina(111) => '0',
dina(110) => '0',
dina(109) => '0',
dina(108) => '0',
dina(107) => '0',
dina(106) => '0',
dina(105) => '0',
dina(104) => '0',
dina(103) => '0',
dina(102) => '0',
dina(101) => '0',
dina(100) => '0',
dina(99) => '0',
dina(98) => '0',
dina(97) => '0',
dina(96) => '0',
dina(95) => '0',
dina(94) => '0',
dina(93) => '0',
dina(92) => '0',
dina(91) => '0',
dina(90) => '0',
dina(89) => '0',
dina(88) => '0',
dina(87) => '0',
dina(86) => '0',
dina(85) => '0',
dina(84) => '0',
dina(83) => '0',
dina(82) => '0',
dina(81) => '0',
dina(80) => '0',
dina(79) => '0',
dina(78) => '0',
dina(77) => '0',
dina(76) => '0',
dina(75) => '0',
dina(74) => '0',
dina(73) => '0',
dina(72) => '0',
dina(71) => '0',
dina(70) => '0',
dina(69) => '0',
dina(68) => '0',
dina(67) => '0',
dina(66) => '0',
dina(65) => '0',
dina(64) => '0',
dina(63) => '0',
dina(62) => '0',
dina(61) => '0',
dina(60) => '0',
dina(59) => '0',
dina(58) => '0',
dina(57) => '0',
dina(56) => '0',
dina(55) => '0',
dina(54) => '0',
dina(53) => '0',
dina(52) => '0',
dina(51) => '0',
dina(50) => '0',
dina(49) => '0',
dina(48) => '0',
dina(47) => '0',
dina(46) => '0',
dina(45) => '0',
dina(44) => '0',
dina(43) => '0',
dina(42) => '0',
dina(41) => '0',
dina(40) => '0',
dina(39) => '0',
dina(38) => '0',
dina(37) => '0',
dina(36) => '0',
dina(35) => '0',
dina(34) => '0',
dina(33) => '0',
dina(32) => '0',
dina(31) => '0',
dina(30) => '0',
dina(29) => '0',
dina(28) => '0',
dina(27) => '0',
dina(26) => '0',
dina(25) => '0',
dina(24) => '0',
dina(23) => '0',
dina(22) => '0',
dina(21) => '0',
dina(20) => '0',
dina(19) => '0',
dina(18) => '0',
dina(17) => '0',
dina(16) => '0',
dina(15) => '0',
dina(14) => '0',
dina(13) => '0',
dina(12) => '0',
dina(11) => '0',
dina(10) => '0',
dina(9) => '0',
dina(8) => '0',
dina(7) => '0',
dina(6) => '0',
dina(5) => '0',
dina(4) => '0',
dina(3) => '0',
dina(2) => '0',
dina(1) => '0',
dina(0) => '0',
dinb(799) => '0',
dinb(798) => '0',
dinb(797) => '0',
dinb(796) => '0',
dinb(795) => '0',
dinb(794) => '0',
dinb(793) => '0',
dinb(792) => '0',
dinb(791) => '0',
dinb(790) => '0',
dinb(789) => '0',
dinb(788) => '0',
dinb(787) => '0',
dinb(786) => '0',
dinb(785) => '0',
dinb(784) => '0',
dinb(783) => '0',
dinb(782) => '0',
dinb(781) => '0',
dinb(780) => '0',
dinb(779) => '0',
dinb(778) => '0',
dinb(777) => '0',
dinb(776) => '0',
dinb(775) => '0',
dinb(774) => '0',
dinb(773) => '0',
dinb(772) => '0',
dinb(771) => '0',
dinb(770) => '0',
dinb(769) => '0',
dinb(768) => '0',
dinb(767) => '0',
dinb(766) => '0',
dinb(765) => '0',
dinb(764) => '0',
dinb(763) => '0',
dinb(762) => '0',
dinb(761) => '0',
dinb(760) => '0',
dinb(759) => '0',
dinb(758) => '0',
dinb(757) => '0',
dinb(756) => '0',
dinb(755) => '0',
dinb(754) => '0',
dinb(753) => '0',
dinb(752) => '0',
dinb(751) => '0',
dinb(750) => '0',
dinb(749) => '0',
dinb(748) => '0',
dinb(747) => '0',
dinb(746) => '0',
dinb(745) => '0',
dinb(744) => '0',
dinb(743) => '0',
dinb(742) => '0',
dinb(741) => '0',
dinb(740) => '0',
dinb(739) => '0',
dinb(738) => '0',
dinb(737) => '0',
dinb(736) => '0',
dinb(735) => '0',
dinb(734) => '0',
dinb(733) => '0',
dinb(732) => '0',
dinb(731) => '0',
dinb(730) => '0',
dinb(729) => '0',
dinb(728) => '0',
dinb(727) => '0',
dinb(726) => '0',
dinb(725) => '0',
dinb(724) => '0',
dinb(723) => '0',
dinb(722) => '0',
dinb(721) => '0',
dinb(720) => '0',
dinb(719) => '0',
dinb(718) => '0',
dinb(717) => '0',
dinb(716) => '0',
dinb(715) => '0',
dinb(714) => '0',
dinb(713) => '0',
dinb(712) => '0',
dinb(711) => '0',
dinb(710) => '0',
dinb(709) => '0',
dinb(708) => '0',
dinb(707) => '0',
dinb(706) => '0',
dinb(705) => '0',
dinb(704) => '0',
dinb(703) => '0',
dinb(702) => '0',
dinb(701) => '0',
dinb(700) => '0',
dinb(699) => '0',
dinb(698) => '0',
dinb(697) => '0',
dinb(696) => '0',
dinb(695) => '0',
dinb(694) => '0',
dinb(693) => '0',
dinb(692) => '0',
dinb(691) => '0',
dinb(690) => '0',
dinb(689) => '0',
dinb(688) => '0',
dinb(687) => '0',
dinb(686) => '0',
dinb(685) => '0',
dinb(684) => '0',
dinb(683) => '0',
dinb(682) => '0',
dinb(681) => '0',
dinb(680) => '0',
dinb(679) => '0',
dinb(678) => '0',
dinb(677) => '0',
dinb(676) => '0',
dinb(675) => '0',
dinb(674) => '0',
dinb(673) => '0',
dinb(672) => '0',
dinb(671) => '0',
dinb(670) => '0',
dinb(669) => '0',
dinb(668) => '0',
dinb(667) => '0',
dinb(666) => '0',
dinb(665) => '0',
dinb(664) => '0',
dinb(663) => '0',
dinb(662) => '0',
dinb(661) => '0',
dinb(660) => '0',
dinb(659) => '0',
dinb(658) => '0',
dinb(657) => '0',
dinb(656) => '0',
dinb(655) => '0',
dinb(654) => '0',
dinb(653) => '0',
dinb(652) => '0',
dinb(651) => '0',
dinb(650) => '0',
dinb(649) => '0',
dinb(648) => '0',
dinb(647) => '0',
dinb(646) => '0',
dinb(645) => '0',
dinb(644) => '0',
dinb(643) => '0',
dinb(642) => '0',
dinb(641) => '0',
dinb(640) => '0',
dinb(639) => '0',
dinb(638) => '0',
dinb(637) => '0',
dinb(636) => '0',
dinb(635) => '0',
dinb(634) => '0',
dinb(633) => '0',
dinb(632) => '0',
dinb(631) => '0',
dinb(630) => '0',
dinb(629) => '0',
dinb(628) => '0',
dinb(627) => '0',
dinb(626) => '0',
dinb(625) => '0',
dinb(624) => '0',
dinb(623) => '0',
dinb(622) => '0',
dinb(621) => '0',
dinb(620) => '0',
dinb(619) => '0',
dinb(618) => '0',
dinb(617) => '0',
dinb(616) => '0',
dinb(615) => '0',
dinb(614) => '0',
dinb(613) => '0',
dinb(612) => '0',
dinb(611) => '0',
dinb(610) => '0',
dinb(609) => '0',
dinb(608) => '0',
dinb(607) => '0',
dinb(606) => '0',
dinb(605) => '0',
dinb(604) => '0',
dinb(603) => '0',
dinb(602) => '0',
dinb(601) => '0',
dinb(600) => '0',
dinb(599) => '0',
dinb(598) => '0',
dinb(597) => '0',
dinb(596) => '0',
dinb(595) => '0',
dinb(594) => '0',
dinb(593) => '0',
dinb(592) => '0',
dinb(591) => '0',
dinb(590) => '0',
dinb(589) => '0',
dinb(588) => '0',
dinb(587) => '0',
dinb(586) => '0',
dinb(585) => '0',
dinb(584) => '0',
dinb(583) => '0',
dinb(582) => '0',
dinb(581) => '0',
dinb(580) => '0',
dinb(579) => '0',
dinb(578) => '0',
dinb(577) => '0',
dinb(576) => '0',
dinb(575) => '0',
dinb(574) => '0',
dinb(573) => '0',
dinb(572) => '0',
dinb(571) => '0',
dinb(570) => '0',
dinb(569) => '0',
dinb(568) => '0',
dinb(567) => '0',
dinb(566) => '0',
dinb(565) => '0',
dinb(564) => '0',
dinb(563) => '0',
dinb(562) => '0',
dinb(561) => '0',
dinb(560) => '0',
dinb(559) => '0',
dinb(558) => '0',
dinb(557) => '0',
dinb(556) => '0',
dinb(555) => '0',
dinb(554) => '0',
dinb(553) => '0',
dinb(552) => '0',
dinb(551) => '0',
dinb(550) => '0',
dinb(549) => '0',
dinb(548) => '0',
dinb(547) => '0',
dinb(546) => '0',
dinb(545) => '0',
dinb(544) => '0',
dinb(543) => '0',
dinb(542) => '0',
dinb(541) => '0',
dinb(540) => '0',
dinb(539) => '0',
dinb(538) => '0',
dinb(537) => '0',
dinb(536) => '0',
dinb(535) => '0',
dinb(534) => '0',
dinb(533) => '0',
dinb(532) => '0',
dinb(531) => '0',
dinb(530) => '0',
dinb(529) => '0',
dinb(528) => '0',
dinb(527) => '0',
dinb(526) => '0',
dinb(525) => '0',
dinb(524) => '0',
dinb(523) => '0',
dinb(522) => '0',
dinb(521) => '0',
dinb(520) => '0',
dinb(519) => '0',
dinb(518) => '0',
dinb(517) => '0',
dinb(516) => '0',
dinb(515) => '0',
dinb(514) => '0',
dinb(513) => '0',
dinb(512) => '0',
dinb(511) => '0',
dinb(510) => '0',
dinb(509) => '0',
dinb(508) => '0',
dinb(507) => '0',
dinb(506) => '0',
dinb(505) => '0',
dinb(504) => '0',
dinb(503) => '0',
dinb(502) => '0',
dinb(501) => '0',
dinb(500) => '0',
dinb(499) => '0',
dinb(498) => '0',
dinb(497) => '0',
dinb(496) => '0',
dinb(495) => '0',
dinb(494) => '0',
dinb(493) => '0',
dinb(492) => '0',
dinb(491) => '0',
dinb(490) => '0',
dinb(489) => '0',
dinb(488) => '0',
dinb(487) => '0',
dinb(486) => '0',
dinb(485) => '0',
dinb(484) => '0',
dinb(483) => '0',
dinb(482) => '0',
dinb(481) => '0',
dinb(480) => '0',
dinb(479) => '0',
dinb(478) => '0',
dinb(477) => '0',
dinb(476) => '0',
dinb(475) => '0',
dinb(474) => '0',
dinb(473) => '0',
dinb(472) => '0',
dinb(471) => '0',
dinb(470) => '0',
dinb(469) => '0',
dinb(468) => '0',
dinb(467) => '0',
dinb(466) => '0',
dinb(465) => '0',
dinb(464) => '0',
dinb(463) => '0',
dinb(462) => '0',
dinb(461) => '0',
dinb(460) => '0',
dinb(459) => '0',
dinb(458) => '0',
dinb(457) => '0',
dinb(456) => '0',
dinb(455) => '0',
dinb(454) => '0',
dinb(453) => '0',
dinb(452) => '0',
dinb(451) => '0',
dinb(450) => '0',
dinb(449) => '0',
dinb(448) => '0',
dinb(447) => '0',
dinb(446) => '0',
dinb(445) => '0',
dinb(444) => '0',
dinb(443) => '0',
dinb(442) => '0',
dinb(441) => '0',
dinb(440) => '0',
dinb(439) => '0',
dinb(438) => '0',
dinb(437) => '0',
dinb(436) => '0',
dinb(435) => '0',
dinb(434) => '0',
dinb(433) => '0',
dinb(432) => '0',
dinb(431) => '0',
dinb(430) => '0',
dinb(429) => '0',
dinb(428) => '0',
dinb(427) => '0',
dinb(426) => '0',
dinb(425) => '0',
dinb(424) => '0',
dinb(423) => '0',
dinb(422) => '0',
dinb(421) => '0',
dinb(420) => '0',
dinb(419) => '0',
dinb(418) => '0',
dinb(417) => '0',
dinb(416) => '0',
dinb(415) => '0',
dinb(414) => '0',
dinb(413) => '0',
dinb(412) => '0',
dinb(411) => '0',
dinb(410) => '0',
dinb(409) => '0',
dinb(408) => '0',
dinb(407) => '0',
dinb(406) => '0',
dinb(405) => '0',
dinb(404) => '0',
dinb(403) => '0',
dinb(402) => '0',
dinb(401) => '0',
dinb(400) => '0',
dinb(399) => '0',
dinb(398) => '0',
dinb(397) => '0',
dinb(396) => '0',
dinb(395) => '0',
dinb(394) => '0',
dinb(393) => '0',
dinb(392) => '0',
dinb(391) => '0',
dinb(390) => '0',
dinb(389) => '0',
dinb(388) => '0',
dinb(387) => '0',
dinb(386) => '0',
dinb(385) => '0',
dinb(384) => '0',
dinb(383) => '0',
dinb(382) => '0',
dinb(381) => '0',
dinb(380) => '0',
dinb(379) => '0',
dinb(378) => '0',
dinb(377) => '0',
dinb(376) => '0',
dinb(375) => '0',
dinb(374) => '0',
dinb(373) => '0',
dinb(372) => '0',
dinb(371) => '0',
dinb(370) => '0',
dinb(369) => '0',
dinb(368) => '0',
dinb(367) => '0',
dinb(366) => '0',
dinb(365) => '0',
dinb(364) => '0',
dinb(363) => '0',
dinb(362) => '0',
dinb(361) => '0',
dinb(360) => '0',
dinb(359) => '0',
dinb(358) => '0',
dinb(357) => '0',
dinb(356) => '0',
dinb(355) => '0',
dinb(354) => '0',
dinb(353) => '0',
dinb(352) => '0',
dinb(351) => '0',
dinb(350) => '0',
dinb(349) => '0',
dinb(348) => '0',
dinb(347) => '0',
dinb(346) => '0',
dinb(345) => '0',
dinb(344) => '0',
dinb(343) => '0',
dinb(342) => '0',
dinb(341) => '0',
dinb(340) => '0',
dinb(339) => '0',
dinb(338) => '0',
dinb(337) => '0',
dinb(336) => '0',
dinb(335) => '0',
dinb(334) => '0',
dinb(333) => '0',
dinb(332) => '0',
dinb(331) => '0',
dinb(330) => '0',
dinb(329) => '0',
dinb(328) => '0',
dinb(327) => '0',
dinb(326) => '0',
dinb(325) => '0',
dinb(324) => '0',
dinb(323) => '0',
dinb(322) => '0',
dinb(321) => '0',
dinb(320) => '0',
dinb(319) => '0',
dinb(318) => '0',
dinb(317) => '0',
dinb(316) => '0',
dinb(315) => '0',
dinb(314) => '0',
dinb(313) => '0',
dinb(312) => '0',
dinb(311) => '0',
dinb(310) => '0',
dinb(309) => '0',
dinb(308) => '0',
dinb(307) => '0',
dinb(306) => '0',
dinb(305) => '0',
dinb(304) => '0',
dinb(303) => '0',
dinb(302) => '0',
dinb(301) => '0',
dinb(300) => '0',
dinb(299) => '0',
dinb(298) => '0',
dinb(297) => '0',
dinb(296) => '0',
dinb(295) => '0',
dinb(294) => '0',
dinb(293) => '0',
dinb(292) => '0',
dinb(291) => '0',
dinb(290) => '0',
dinb(289) => '0',
dinb(288) => '0',
dinb(287) => '0',
dinb(286) => '0',
dinb(285) => '0',
dinb(284) => '0',
dinb(283) => '0',
dinb(282) => '0',
dinb(281) => '0',
dinb(280) => '0',
dinb(279) => '0',
dinb(278) => '0',
dinb(277) => '0',
dinb(276) => '0',
dinb(275) => '0',
dinb(274) => '0',
dinb(273) => '0',
dinb(272) => '0',
dinb(271) => '0',
dinb(270) => '0',
dinb(269) => '0',
dinb(268) => '0',
dinb(267) => '0',
dinb(266) => '0',
dinb(265) => '0',
dinb(264) => '0',
dinb(263) => '0',
dinb(262) => '0',
dinb(261) => '0',
dinb(260) => '0',
dinb(259) => '0',
dinb(258) => '0',
dinb(257) => '0',
dinb(256) => '0',
dinb(255) => '0',
dinb(254) => '0',
dinb(253) => '0',
dinb(252) => '0',
dinb(251) => '0',
dinb(250) => '0',
dinb(249) => '0',
dinb(248) => '0',
dinb(247) => '0',
dinb(246) => '0',
dinb(245) => '0',
dinb(244) => '0',
dinb(243) => '0',
dinb(242) => '0',
dinb(241) => '0',
dinb(240) => '0',
dinb(239) => '0',
dinb(238) => '0',
dinb(237) => '0',
dinb(236) => '0',
dinb(235) => '0',
dinb(234) => '0',
dinb(233) => '0',
dinb(232) => '0',
dinb(231) => '0',
dinb(230) => '0',
dinb(229) => '0',
dinb(228) => '0',
dinb(227) => '0',
dinb(226) => '0',
dinb(225) => '0',
dinb(224) => '0',
dinb(223) => '0',
dinb(222) => '0',
dinb(221) => '0',
dinb(220) => '0',
dinb(219) => '0',
dinb(218) => '0',
dinb(217) => '0',
dinb(216) => '0',
dinb(215) => '0',
dinb(214) => '0',
dinb(213) => '0',
dinb(212) => '0',
dinb(211) => '0',
dinb(210) => '0',
dinb(209) => '0',
dinb(208) => '0',
dinb(207) => '0',
dinb(206) => '0',
dinb(205) => '0',
dinb(204) => '0',
dinb(203) => '0',
dinb(202) => '0',
dinb(201) => '0',
dinb(200) => '0',
dinb(199) => '0',
dinb(198) => '0',
dinb(197) => '0',
dinb(196) => '0',
dinb(195) => '0',
dinb(194) => '0',
dinb(193) => '0',
dinb(192) => '0',
dinb(191) => '0',
dinb(190) => '0',
dinb(189) => '0',
dinb(188) => '0',
dinb(187) => '0',
dinb(186) => '0',
dinb(185) => '0',
dinb(184) => '0',
dinb(183) => '0',
dinb(182) => '0',
dinb(181) => '0',
dinb(180) => '0',
dinb(179) => '0',
dinb(178) => '0',
dinb(177) => '0',
dinb(176) => '0',
dinb(175) => '0',
dinb(174) => '0',
dinb(173) => '0',
dinb(172) => '0',
dinb(171) => '0',
dinb(170) => '0',
dinb(169) => '0',
dinb(168) => '0',
dinb(167) => '0',
dinb(166) => '0',
dinb(165) => '0',
dinb(164) => '0',
dinb(163) => '0',
dinb(162) => '0',
dinb(161) => '0',
dinb(160) => '0',
dinb(159) => '0',
dinb(158) => '0',
dinb(157) => '0',
dinb(156) => '0',
dinb(155) => '0',
dinb(154) => '0',
dinb(153) => '0',
dinb(152) => '0',
dinb(151) => '0',
dinb(150) => '0',
dinb(149) => '0',
dinb(148) => '0',
dinb(147) => '0',
dinb(146) => '0',
dinb(145) => '0',
dinb(144) => '0',
dinb(143) => '0',
dinb(142) => '0',
dinb(141) => '0',
dinb(140) => '0',
dinb(139) => '0',
dinb(138) => '0',
dinb(137) => '0',
dinb(136) => '0',
dinb(135) => '0',
dinb(134) => '0',
dinb(133) => '0',
dinb(132) => '0',
dinb(131) => '0',
dinb(130) => '0',
dinb(129) => '0',
dinb(128) => '0',
dinb(127) => '0',
dinb(126) => '0',
dinb(125) => '0',
dinb(124) => '0',
dinb(123) => '0',
dinb(122) => '0',
dinb(121) => '0',
dinb(120) => '0',
dinb(119) => '0',
dinb(118) => '0',
dinb(117) => '0',
dinb(116) => '0',
dinb(115) => '0',
dinb(114) => '0',
dinb(113) => '0',
dinb(112) => '0',
dinb(111) => '0',
dinb(110) => '0',
dinb(109) => '0',
dinb(108) => '0',
dinb(107) => '0',
dinb(106) => '0',
dinb(105) => '0',
dinb(104) => '0',
dinb(103) => '0',
dinb(102) => '0',
dinb(101) => '0',
dinb(100) => '0',
dinb(99) => '0',
dinb(98) => '0',
dinb(97) => '0',
dinb(96) => '0',
dinb(95) => '0',
dinb(94) => '0',
dinb(93) => '0',
dinb(92) => '0',
dinb(91) => '0',
dinb(90) => '0',
dinb(89) => '0',
dinb(88) => '0',
dinb(87) => '0',
dinb(86) => '0',
dinb(85) => '0',
dinb(84) => '0',
dinb(83) => '0',
dinb(82) => '0',
dinb(81) => '0',
dinb(80) => '0',
dinb(79) => '0',
dinb(78) => '0',
dinb(77) => '0',
dinb(76) => '0',
dinb(75) => '0',
dinb(74) => '0',
dinb(73) => '0',
dinb(72) => '0',
dinb(71) => '0',
dinb(70) => '0',
dinb(69) => '0',
dinb(68) => '0',
dinb(67) => '0',
dinb(66) => '0',
dinb(65) => '0',
dinb(64) => '0',
dinb(63) => '0',
dinb(62) => '0',
dinb(61) => '0',
dinb(60) => '0',
dinb(59) => '0',
dinb(58) => '0',
dinb(57) => '0',
dinb(56) => '0',
dinb(55) => '0',
dinb(54) => '0',
dinb(53) => '0',
dinb(52) => '0',
dinb(51) => '0',
dinb(50) => '0',
dinb(49) => '0',
dinb(48) => '0',
dinb(47) => '0',
dinb(46) => '0',
dinb(45) => '0',
dinb(44) => '0',
dinb(43) => '0',
dinb(42) => '0',
dinb(41) => '0',
dinb(40) => '0',
dinb(39) => '0',
dinb(38) => '0',
dinb(37) => '0',
dinb(36) => '0',
dinb(35) => '0',
dinb(34) => '0',
dinb(33) => '0',
dinb(32) => '0',
dinb(31) => '0',
dinb(30) => '0',
dinb(29) => '0',
dinb(28) => '0',
dinb(27) => '0',
dinb(26) => '0',
dinb(25) => '0',
dinb(24) => '0',
dinb(23) => '0',
dinb(22) => '0',
dinb(21) => '0',
dinb(20) => '0',
dinb(19) => '0',
dinb(18) => '0',
dinb(17) => '0',
dinb(16) => '0',
dinb(15) => '0',
dinb(14) => '0',
dinb(13) => '0',
dinb(12) => '0',
dinb(11) => '0',
dinb(10) => '0',
dinb(9) => '0',
dinb(8) => '0',
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(799 downto 0) => douta(799 downto 0),
doutb(799 downto 0) => NLW_U0_doutb_UNCONNECTED(799 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(799 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(799 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(799) => '0',
s_axi_wdata(798) => '0',
s_axi_wdata(797) => '0',
s_axi_wdata(796) => '0',
s_axi_wdata(795) => '0',
s_axi_wdata(794) => '0',
s_axi_wdata(793) => '0',
s_axi_wdata(792) => '0',
s_axi_wdata(791) => '0',
s_axi_wdata(790) => '0',
s_axi_wdata(789) => '0',
s_axi_wdata(788) => '0',
s_axi_wdata(787) => '0',
s_axi_wdata(786) => '0',
s_axi_wdata(785) => '0',
s_axi_wdata(784) => '0',
s_axi_wdata(783) => '0',
s_axi_wdata(782) => '0',
s_axi_wdata(781) => '0',
s_axi_wdata(780) => '0',
s_axi_wdata(779) => '0',
s_axi_wdata(778) => '0',
s_axi_wdata(777) => '0',
s_axi_wdata(776) => '0',
s_axi_wdata(775) => '0',
s_axi_wdata(774) => '0',
s_axi_wdata(773) => '0',
s_axi_wdata(772) => '0',
s_axi_wdata(771) => '0',
s_axi_wdata(770) => '0',
s_axi_wdata(769) => '0',
s_axi_wdata(768) => '0',
s_axi_wdata(767) => '0',
s_axi_wdata(766) => '0',
s_axi_wdata(765) => '0',
s_axi_wdata(764) => '0',
s_axi_wdata(763) => '0',
s_axi_wdata(762) => '0',
s_axi_wdata(761) => '0',
s_axi_wdata(760) => '0',
s_axi_wdata(759) => '0',
s_axi_wdata(758) => '0',
s_axi_wdata(757) => '0',
s_axi_wdata(756) => '0',
s_axi_wdata(755) => '0',
s_axi_wdata(754) => '0',
s_axi_wdata(753) => '0',
s_axi_wdata(752) => '0',
s_axi_wdata(751) => '0',
s_axi_wdata(750) => '0',
s_axi_wdata(749) => '0',
s_axi_wdata(748) => '0',
s_axi_wdata(747) => '0',
s_axi_wdata(746) => '0',
s_axi_wdata(745) => '0',
s_axi_wdata(744) => '0',
s_axi_wdata(743) => '0',
s_axi_wdata(742) => '0',
s_axi_wdata(741) => '0',
s_axi_wdata(740) => '0',
s_axi_wdata(739) => '0',
s_axi_wdata(738) => '0',
s_axi_wdata(737) => '0',
s_axi_wdata(736) => '0',
s_axi_wdata(735) => '0',
s_axi_wdata(734) => '0',
s_axi_wdata(733) => '0',
s_axi_wdata(732) => '0',
s_axi_wdata(731) => '0',
s_axi_wdata(730) => '0',
s_axi_wdata(729) => '0',
s_axi_wdata(728) => '0',
s_axi_wdata(727) => '0',
s_axi_wdata(726) => '0',
s_axi_wdata(725) => '0',
s_axi_wdata(724) => '0',
s_axi_wdata(723) => '0',
s_axi_wdata(722) => '0',
s_axi_wdata(721) => '0',
s_axi_wdata(720) => '0',
s_axi_wdata(719) => '0',
s_axi_wdata(718) => '0',
s_axi_wdata(717) => '0',
s_axi_wdata(716) => '0',
s_axi_wdata(715) => '0',
s_axi_wdata(714) => '0',
s_axi_wdata(713) => '0',
s_axi_wdata(712) => '0',
s_axi_wdata(711) => '0',
s_axi_wdata(710) => '0',
s_axi_wdata(709) => '0',
s_axi_wdata(708) => '0',
s_axi_wdata(707) => '0',
s_axi_wdata(706) => '0',
s_axi_wdata(705) => '0',
s_axi_wdata(704) => '0',
s_axi_wdata(703) => '0',
s_axi_wdata(702) => '0',
s_axi_wdata(701) => '0',
s_axi_wdata(700) => '0',
s_axi_wdata(699) => '0',
s_axi_wdata(698) => '0',
s_axi_wdata(697) => '0',
s_axi_wdata(696) => '0',
s_axi_wdata(695) => '0',
s_axi_wdata(694) => '0',
s_axi_wdata(693) => '0',
s_axi_wdata(692) => '0',
s_axi_wdata(691) => '0',
s_axi_wdata(690) => '0',
s_axi_wdata(689) => '0',
s_axi_wdata(688) => '0',
s_axi_wdata(687) => '0',
s_axi_wdata(686) => '0',
s_axi_wdata(685) => '0',
s_axi_wdata(684) => '0',
s_axi_wdata(683) => '0',
s_axi_wdata(682) => '0',
s_axi_wdata(681) => '0',
s_axi_wdata(680) => '0',
s_axi_wdata(679) => '0',
s_axi_wdata(678) => '0',
s_axi_wdata(677) => '0',
s_axi_wdata(676) => '0',
s_axi_wdata(675) => '0',
s_axi_wdata(674) => '0',
s_axi_wdata(673) => '0',
s_axi_wdata(672) => '0',
s_axi_wdata(671) => '0',
s_axi_wdata(670) => '0',
s_axi_wdata(669) => '0',
s_axi_wdata(668) => '0',
s_axi_wdata(667) => '0',
s_axi_wdata(666) => '0',
s_axi_wdata(665) => '0',
s_axi_wdata(664) => '0',
s_axi_wdata(663) => '0',
s_axi_wdata(662) => '0',
s_axi_wdata(661) => '0',
s_axi_wdata(660) => '0',
s_axi_wdata(659) => '0',
s_axi_wdata(658) => '0',
s_axi_wdata(657) => '0',
s_axi_wdata(656) => '0',
s_axi_wdata(655) => '0',
s_axi_wdata(654) => '0',
s_axi_wdata(653) => '0',
s_axi_wdata(652) => '0',
s_axi_wdata(651) => '0',
s_axi_wdata(650) => '0',
s_axi_wdata(649) => '0',
s_axi_wdata(648) => '0',
s_axi_wdata(647) => '0',
s_axi_wdata(646) => '0',
s_axi_wdata(645) => '0',
s_axi_wdata(644) => '0',
s_axi_wdata(643) => '0',
s_axi_wdata(642) => '0',
s_axi_wdata(641) => '0',
s_axi_wdata(640) => '0',
s_axi_wdata(639) => '0',
s_axi_wdata(638) => '0',
s_axi_wdata(637) => '0',
s_axi_wdata(636) => '0',
s_axi_wdata(635) => '0',
s_axi_wdata(634) => '0',
s_axi_wdata(633) => '0',
s_axi_wdata(632) => '0',
s_axi_wdata(631) => '0',
s_axi_wdata(630) => '0',
s_axi_wdata(629) => '0',
s_axi_wdata(628) => '0',
s_axi_wdata(627) => '0',
s_axi_wdata(626) => '0',
s_axi_wdata(625) => '0',
s_axi_wdata(624) => '0',
s_axi_wdata(623) => '0',
s_axi_wdata(622) => '0',
s_axi_wdata(621) => '0',
s_axi_wdata(620) => '0',
s_axi_wdata(619) => '0',
s_axi_wdata(618) => '0',
s_axi_wdata(617) => '0',
s_axi_wdata(616) => '0',
s_axi_wdata(615) => '0',
s_axi_wdata(614) => '0',
s_axi_wdata(613) => '0',
s_axi_wdata(612) => '0',
s_axi_wdata(611) => '0',
s_axi_wdata(610) => '0',
s_axi_wdata(609) => '0',
s_axi_wdata(608) => '0',
s_axi_wdata(607) => '0',
s_axi_wdata(606) => '0',
s_axi_wdata(605) => '0',
s_axi_wdata(604) => '0',
s_axi_wdata(603) => '0',
s_axi_wdata(602) => '0',
s_axi_wdata(601) => '0',
s_axi_wdata(600) => '0',
s_axi_wdata(599) => '0',
s_axi_wdata(598) => '0',
s_axi_wdata(597) => '0',
s_axi_wdata(596) => '0',
s_axi_wdata(595) => '0',
s_axi_wdata(594) => '0',
s_axi_wdata(593) => '0',
s_axi_wdata(592) => '0',
s_axi_wdata(591) => '0',
s_axi_wdata(590) => '0',
s_axi_wdata(589) => '0',
s_axi_wdata(588) => '0',
s_axi_wdata(587) => '0',
s_axi_wdata(586) => '0',
s_axi_wdata(585) => '0',
s_axi_wdata(584) => '0',
s_axi_wdata(583) => '0',
s_axi_wdata(582) => '0',
s_axi_wdata(581) => '0',
s_axi_wdata(580) => '0',
s_axi_wdata(579) => '0',
s_axi_wdata(578) => '0',
s_axi_wdata(577) => '0',
s_axi_wdata(576) => '0',
s_axi_wdata(575) => '0',
s_axi_wdata(574) => '0',
s_axi_wdata(573) => '0',
s_axi_wdata(572) => '0',
s_axi_wdata(571) => '0',
s_axi_wdata(570) => '0',
s_axi_wdata(569) => '0',
s_axi_wdata(568) => '0',
s_axi_wdata(567) => '0',
s_axi_wdata(566) => '0',
s_axi_wdata(565) => '0',
s_axi_wdata(564) => '0',
s_axi_wdata(563) => '0',
s_axi_wdata(562) => '0',
s_axi_wdata(561) => '0',
s_axi_wdata(560) => '0',
s_axi_wdata(559) => '0',
s_axi_wdata(558) => '0',
s_axi_wdata(557) => '0',
s_axi_wdata(556) => '0',
s_axi_wdata(555) => '0',
s_axi_wdata(554) => '0',
s_axi_wdata(553) => '0',
s_axi_wdata(552) => '0',
s_axi_wdata(551) => '0',
s_axi_wdata(550) => '0',
s_axi_wdata(549) => '0',
s_axi_wdata(548) => '0',
s_axi_wdata(547) => '0',
s_axi_wdata(546) => '0',
s_axi_wdata(545) => '0',
s_axi_wdata(544) => '0',
s_axi_wdata(543) => '0',
s_axi_wdata(542) => '0',
s_axi_wdata(541) => '0',
s_axi_wdata(540) => '0',
s_axi_wdata(539) => '0',
s_axi_wdata(538) => '0',
s_axi_wdata(537) => '0',
s_axi_wdata(536) => '0',
s_axi_wdata(535) => '0',
s_axi_wdata(534) => '0',
s_axi_wdata(533) => '0',
s_axi_wdata(532) => '0',
s_axi_wdata(531) => '0',
s_axi_wdata(530) => '0',
s_axi_wdata(529) => '0',
s_axi_wdata(528) => '0',
s_axi_wdata(527) => '0',
s_axi_wdata(526) => '0',
s_axi_wdata(525) => '0',
s_axi_wdata(524) => '0',
s_axi_wdata(523) => '0',
s_axi_wdata(522) => '0',
s_axi_wdata(521) => '0',
s_axi_wdata(520) => '0',
s_axi_wdata(519) => '0',
s_axi_wdata(518) => '0',
s_axi_wdata(517) => '0',
s_axi_wdata(516) => '0',
s_axi_wdata(515) => '0',
s_axi_wdata(514) => '0',
s_axi_wdata(513) => '0',
s_axi_wdata(512) => '0',
s_axi_wdata(511) => '0',
s_axi_wdata(510) => '0',
s_axi_wdata(509) => '0',
s_axi_wdata(508) => '0',
s_axi_wdata(507) => '0',
s_axi_wdata(506) => '0',
s_axi_wdata(505) => '0',
s_axi_wdata(504) => '0',
s_axi_wdata(503) => '0',
s_axi_wdata(502) => '0',
s_axi_wdata(501) => '0',
s_axi_wdata(500) => '0',
s_axi_wdata(499) => '0',
s_axi_wdata(498) => '0',
s_axi_wdata(497) => '0',
s_axi_wdata(496) => '0',
s_axi_wdata(495) => '0',
s_axi_wdata(494) => '0',
s_axi_wdata(493) => '0',
s_axi_wdata(492) => '0',
s_axi_wdata(491) => '0',
s_axi_wdata(490) => '0',
s_axi_wdata(489) => '0',
s_axi_wdata(488) => '0',
s_axi_wdata(487) => '0',
s_axi_wdata(486) => '0',
s_axi_wdata(485) => '0',
s_axi_wdata(484) => '0',
s_axi_wdata(483) => '0',
s_axi_wdata(482) => '0',
s_axi_wdata(481) => '0',
s_axi_wdata(480) => '0',
s_axi_wdata(479) => '0',
s_axi_wdata(478) => '0',
s_axi_wdata(477) => '0',
s_axi_wdata(476) => '0',
s_axi_wdata(475) => '0',
s_axi_wdata(474) => '0',
s_axi_wdata(473) => '0',
s_axi_wdata(472) => '0',
s_axi_wdata(471) => '0',
s_axi_wdata(470) => '0',
s_axi_wdata(469) => '0',
s_axi_wdata(468) => '0',
s_axi_wdata(467) => '0',
s_axi_wdata(466) => '0',
s_axi_wdata(465) => '0',
s_axi_wdata(464) => '0',
s_axi_wdata(463) => '0',
s_axi_wdata(462) => '0',
s_axi_wdata(461) => '0',
s_axi_wdata(460) => '0',
s_axi_wdata(459) => '0',
s_axi_wdata(458) => '0',
s_axi_wdata(457) => '0',
s_axi_wdata(456) => '0',
s_axi_wdata(455) => '0',
s_axi_wdata(454) => '0',
s_axi_wdata(453) => '0',
s_axi_wdata(452) => '0',
s_axi_wdata(451) => '0',
s_axi_wdata(450) => '0',
s_axi_wdata(449) => '0',
s_axi_wdata(448) => '0',
s_axi_wdata(447) => '0',
s_axi_wdata(446) => '0',
s_axi_wdata(445) => '0',
s_axi_wdata(444) => '0',
s_axi_wdata(443) => '0',
s_axi_wdata(442) => '0',
s_axi_wdata(441) => '0',
s_axi_wdata(440) => '0',
s_axi_wdata(439) => '0',
s_axi_wdata(438) => '0',
s_axi_wdata(437) => '0',
s_axi_wdata(436) => '0',
s_axi_wdata(435) => '0',
s_axi_wdata(434) => '0',
s_axi_wdata(433) => '0',
s_axi_wdata(432) => '0',
s_axi_wdata(431) => '0',
s_axi_wdata(430) => '0',
s_axi_wdata(429) => '0',
s_axi_wdata(428) => '0',
s_axi_wdata(427) => '0',
s_axi_wdata(426) => '0',
s_axi_wdata(425) => '0',
s_axi_wdata(424) => '0',
s_axi_wdata(423) => '0',
s_axi_wdata(422) => '0',
s_axi_wdata(421) => '0',
s_axi_wdata(420) => '0',
s_axi_wdata(419) => '0',
s_axi_wdata(418) => '0',
s_axi_wdata(417) => '0',
s_axi_wdata(416) => '0',
s_axi_wdata(415) => '0',
s_axi_wdata(414) => '0',
s_axi_wdata(413) => '0',
s_axi_wdata(412) => '0',
s_axi_wdata(411) => '0',
s_axi_wdata(410) => '0',
s_axi_wdata(409) => '0',
s_axi_wdata(408) => '0',
s_axi_wdata(407) => '0',
s_axi_wdata(406) => '0',
s_axi_wdata(405) => '0',
s_axi_wdata(404) => '0',
s_axi_wdata(403) => '0',
s_axi_wdata(402) => '0',
s_axi_wdata(401) => '0',
s_axi_wdata(400) => '0',
s_axi_wdata(399) => '0',
s_axi_wdata(398) => '0',
s_axi_wdata(397) => '0',
s_axi_wdata(396) => '0',
s_axi_wdata(395) => '0',
s_axi_wdata(394) => '0',
s_axi_wdata(393) => '0',
s_axi_wdata(392) => '0',
s_axi_wdata(391) => '0',
s_axi_wdata(390) => '0',
s_axi_wdata(389) => '0',
s_axi_wdata(388) => '0',
s_axi_wdata(387) => '0',
s_axi_wdata(386) => '0',
s_axi_wdata(385) => '0',
s_axi_wdata(384) => '0',
s_axi_wdata(383) => '0',
s_axi_wdata(382) => '0',
s_axi_wdata(381) => '0',
s_axi_wdata(380) => '0',
s_axi_wdata(379) => '0',
s_axi_wdata(378) => '0',
s_axi_wdata(377) => '0',
s_axi_wdata(376) => '0',
s_axi_wdata(375) => '0',
s_axi_wdata(374) => '0',
s_axi_wdata(373) => '0',
s_axi_wdata(372) => '0',
s_axi_wdata(371) => '0',
s_axi_wdata(370) => '0',
s_axi_wdata(369) => '0',
s_axi_wdata(368) => '0',
s_axi_wdata(367) => '0',
s_axi_wdata(366) => '0',
s_axi_wdata(365) => '0',
s_axi_wdata(364) => '0',
s_axi_wdata(363) => '0',
s_axi_wdata(362) => '0',
s_axi_wdata(361) => '0',
s_axi_wdata(360) => '0',
s_axi_wdata(359) => '0',
s_axi_wdata(358) => '0',
s_axi_wdata(357) => '0',
s_axi_wdata(356) => '0',
s_axi_wdata(355) => '0',
s_axi_wdata(354) => '0',
s_axi_wdata(353) => '0',
s_axi_wdata(352) => '0',
s_axi_wdata(351) => '0',
s_axi_wdata(350) => '0',
s_axi_wdata(349) => '0',
s_axi_wdata(348) => '0',
s_axi_wdata(347) => '0',
s_axi_wdata(346) => '0',
s_axi_wdata(345) => '0',
s_axi_wdata(344) => '0',
s_axi_wdata(343) => '0',
s_axi_wdata(342) => '0',
s_axi_wdata(341) => '0',
s_axi_wdata(340) => '0',
s_axi_wdata(339) => '0',
s_axi_wdata(338) => '0',
s_axi_wdata(337) => '0',
s_axi_wdata(336) => '0',
s_axi_wdata(335) => '0',
s_axi_wdata(334) => '0',
s_axi_wdata(333) => '0',
s_axi_wdata(332) => '0',
s_axi_wdata(331) => '0',
s_axi_wdata(330) => '0',
s_axi_wdata(329) => '0',
s_axi_wdata(328) => '0',
s_axi_wdata(327) => '0',
s_axi_wdata(326) => '0',
s_axi_wdata(325) => '0',
s_axi_wdata(324) => '0',
s_axi_wdata(323) => '0',
s_axi_wdata(322) => '0',
s_axi_wdata(321) => '0',
s_axi_wdata(320) => '0',
s_axi_wdata(319) => '0',
s_axi_wdata(318) => '0',
s_axi_wdata(317) => '0',
s_axi_wdata(316) => '0',
s_axi_wdata(315) => '0',
s_axi_wdata(314) => '0',
s_axi_wdata(313) => '0',
s_axi_wdata(312) => '0',
s_axi_wdata(311) => '0',
s_axi_wdata(310) => '0',
s_axi_wdata(309) => '0',
s_axi_wdata(308) => '0',
s_axi_wdata(307) => '0',
s_axi_wdata(306) => '0',
s_axi_wdata(305) => '0',
s_axi_wdata(304) => '0',
s_axi_wdata(303) => '0',
s_axi_wdata(302) => '0',
s_axi_wdata(301) => '0',
s_axi_wdata(300) => '0',
s_axi_wdata(299) => '0',
s_axi_wdata(298) => '0',
s_axi_wdata(297) => '0',
s_axi_wdata(296) => '0',
s_axi_wdata(295) => '0',
s_axi_wdata(294) => '0',
s_axi_wdata(293) => '0',
s_axi_wdata(292) => '0',
s_axi_wdata(291) => '0',
s_axi_wdata(290) => '0',
s_axi_wdata(289) => '0',
s_axi_wdata(288) => '0',
s_axi_wdata(287) => '0',
s_axi_wdata(286) => '0',
s_axi_wdata(285) => '0',
s_axi_wdata(284) => '0',
s_axi_wdata(283) => '0',
s_axi_wdata(282) => '0',
s_axi_wdata(281) => '0',
s_axi_wdata(280) => '0',
s_axi_wdata(279) => '0',
s_axi_wdata(278) => '0',
s_axi_wdata(277) => '0',
s_axi_wdata(276) => '0',
s_axi_wdata(275) => '0',
s_axi_wdata(274) => '0',
s_axi_wdata(273) => '0',
s_axi_wdata(272) => '0',
s_axi_wdata(271) => '0',
s_axi_wdata(270) => '0',
s_axi_wdata(269) => '0',
s_axi_wdata(268) => '0',
s_axi_wdata(267) => '0',
s_axi_wdata(266) => '0',
s_axi_wdata(265) => '0',
s_axi_wdata(264) => '0',
s_axi_wdata(263) => '0',
s_axi_wdata(262) => '0',
s_axi_wdata(261) => '0',
s_axi_wdata(260) => '0',
s_axi_wdata(259) => '0',
s_axi_wdata(258) => '0',
s_axi_wdata(257) => '0',
s_axi_wdata(256) => '0',
s_axi_wdata(255) => '0',
s_axi_wdata(254) => '0',
s_axi_wdata(253) => '0',
s_axi_wdata(252) => '0',
s_axi_wdata(251) => '0',
s_axi_wdata(250) => '0',
s_axi_wdata(249) => '0',
s_axi_wdata(248) => '0',
s_axi_wdata(247) => '0',
s_axi_wdata(246) => '0',
s_axi_wdata(245) => '0',
s_axi_wdata(244) => '0',
s_axi_wdata(243) => '0',
s_axi_wdata(242) => '0',
s_axi_wdata(241) => '0',
s_axi_wdata(240) => '0',
s_axi_wdata(239) => '0',
s_axi_wdata(238) => '0',
s_axi_wdata(237) => '0',
s_axi_wdata(236) => '0',
s_axi_wdata(235) => '0',
s_axi_wdata(234) => '0',
s_axi_wdata(233) => '0',
s_axi_wdata(232) => '0',
s_axi_wdata(231) => '0',
s_axi_wdata(230) => '0',
s_axi_wdata(229) => '0',
s_axi_wdata(228) => '0',
s_axi_wdata(227) => '0',
s_axi_wdata(226) => '0',
s_axi_wdata(225) => '0',
s_axi_wdata(224) => '0',
s_axi_wdata(223) => '0',
s_axi_wdata(222) => '0',
s_axi_wdata(221) => '0',
s_axi_wdata(220) => '0',
s_axi_wdata(219) => '0',
s_axi_wdata(218) => '0',
s_axi_wdata(217) => '0',
s_axi_wdata(216) => '0',
s_axi_wdata(215) => '0',
s_axi_wdata(214) => '0',
s_axi_wdata(213) => '0',
s_axi_wdata(212) => '0',
s_axi_wdata(211) => '0',
s_axi_wdata(210) => '0',
s_axi_wdata(209) => '0',
s_axi_wdata(208) => '0',
s_axi_wdata(207) => '0',
s_axi_wdata(206) => '0',
s_axi_wdata(205) => '0',
s_axi_wdata(204) => '0',
s_axi_wdata(203) => '0',
s_axi_wdata(202) => '0',
s_axi_wdata(201) => '0',
s_axi_wdata(200) => '0',
s_axi_wdata(199) => '0',
s_axi_wdata(198) => '0',
s_axi_wdata(197) => '0',
s_axi_wdata(196) => '0',
s_axi_wdata(195) => '0',
s_axi_wdata(194) => '0',
s_axi_wdata(193) => '0',
s_axi_wdata(192) => '0',
s_axi_wdata(191) => '0',
s_axi_wdata(190) => '0',
s_axi_wdata(189) => '0',
s_axi_wdata(188) => '0',
s_axi_wdata(187) => '0',
s_axi_wdata(186) => '0',
s_axi_wdata(185) => '0',
s_axi_wdata(184) => '0',
s_axi_wdata(183) => '0',
s_axi_wdata(182) => '0',
s_axi_wdata(181) => '0',
s_axi_wdata(180) => '0',
s_axi_wdata(179) => '0',
s_axi_wdata(178) => '0',
s_axi_wdata(177) => '0',
s_axi_wdata(176) => '0',
s_axi_wdata(175) => '0',
s_axi_wdata(174) => '0',
s_axi_wdata(173) => '0',
s_axi_wdata(172) => '0',
s_axi_wdata(171) => '0',
s_axi_wdata(170) => '0',
s_axi_wdata(169) => '0',
s_axi_wdata(168) => '0',
s_axi_wdata(167) => '0',
s_axi_wdata(166) => '0',
s_axi_wdata(165) => '0',
s_axi_wdata(164) => '0',
s_axi_wdata(163) => '0',
s_axi_wdata(162) => '0',
s_axi_wdata(161) => '0',
s_axi_wdata(160) => '0',
s_axi_wdata(159) => '0',
s_axi_wdata(158) => '0',
s_axi_wdata(157) => '0',
s_axi_wdata(156) => '0',
s_axi_wdata(155) => '0',
s_axi_wdata(154) => '0',
s_axi_wdata(153) => '0',
s_axi_wdata(152) => '0',
s_axi_wdata(151) => '0',
s_axi_wdata(150) => '0',
s_axi_wdata(149) => '0',
s_axi_wdata(148) => '0',
s_axi_wdata(147) => '0',
s_axi_wdata(146) => '0',
s_axi_wdata(145) => '0',
s_axi_wdata(144) => '0',
s_axi_wdata(143) => '0',
s_axi_wdata(142) => '0',
s_axi_wdata(141) => '0',
s_axi_wdata(140) => '0',
s_axi_wdata(139) => '0',
s_axi_wdata(138) => '0',
s_axi_wdata(137) => '0',
s_axi_wdata(136) => '0',
s_axi_wdata(135) => '0',
s_axi_wdata(134) => '0',
s_axi_wdata(133) => '0',
s_axi_wdata(132) => '0',
s_axi_wdata(131) => '0',
s_axi_wdata(130) => '0',
s_axi_wdata(129) => '0',
s_axi_wdata(128) => '0',
s_axi_wdata(127) => '0',
s_axi_wdata(126) => '0',
s_axi_wdata(125) => '0',
s_axi_wdata(124) => '0',
s_axi_wdata(123) => '0',
s_axi_wdata(122) => '0',
s_axi_wdata(121) => '0',
s_axi_wdata(120) => '0',
s_axi_wdata(119) => '0',
s_axi_wdata(118) => '0',
s_axi_wdata(117) => '0',
s_axi_wdata(116) => '0',
s_axi_wdata(115) => '0',
s_axi_wdata(114) => '0',
s_axi_wdata(113) => '0',
s_axi_wdata(112) => '0',
s_axi_wdata(111) => '0',
s_axi_wdata(110) => '0',
s_axi_wdata(109) => '0',
s_axi_wdata(108) => '0',
s_axi_wdata(107) => '0',
s_axi_wdata(106) => '0',
s_axi_wdata(105) => '0',
s_axi_wdata(104) => '0',
s_axi_wdata(103) => '0',
s_axi_wdata(102) => '0',
s_axi_wdata(101) => '0',
s_axi_wdata(100) => '0',
s_axi_wdata(99) => '0',
s_axi_wdata(98) => '0',
s_axi_wdata(97) => '0',
s_axi_wdata(96) => '0',
s_axi_wdata(95) => '0',
s_axi_wdata(94) => '0',
s_axi_wdata(93) => '0',
s_axi_wdata(92) => '0',
s_axi_wdata(91) => '0',
s_axi_wdata(90) => '0',
s_axi_wdata(89) => '0',
s_axi_wdata(88) => '0',
s_axi_wdata(87) => '0',
s_axi_wdata(86) => '0',
s_axi_wdata(85) => '0',
s_axi_wdata(84) => '0',
s_axi_wdata(83) => '0',
s_axi_wdata(82) => '0',
s_axi_wdata(81) => '0',
s_axi_wdata(80) => '0',
s_axi_wdata(79) => '0',
s_axi_wdata(78) => '0',
s_axi_wdata(77) => '0',
s_axi_wdata(76) => '0',
s_axi_wdata(75) => '0',
s_axi_wdata(74) => '0',
s_axi_wdata(73) => '0',
s_axi_wdata(72) => '0',
s_axi_wdata(71) => '0',
s_axi_wdata(70) => '0',
s_axi_wdata(69) => '0',
s_axi_wdata(68) => '0',
s_axi_wdata(67) => '0',
s_axi_wdata(66) => '0',
s_axi_wdata(65) => '0',
s_axi_wdata(64) => '0',
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
wea(0) => '0',
web(0) => '0'
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
-- Company: Digilent RO
-- Engineer: Kovacs Laszlo - Attila
--
-- Create Date: 12:53:59 01/11/08
-- Module Name: Memory - Behavioral
-- Project Name: StreamIO
-- Description:
-- Implements dualport synchronous memory with separate read and write ports.
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Memory is
Port (
IFCLK : in std_logic;
RST : in std_logic;
DOWNBSY : out std_logic;
DOWNWR : in std_logic;
DOWNACK : out std_logic;
DOWNDATA : in std_logic_vector(7 downto 0);
UPBSY : out std_logic;
UPRD : in std_logic;
UPACK : out std_logic;
UPDATA : out std_logic_vector(7 downto 0));
end Memory;
architecture Behavioral of Memory is
constant MEMSIZE : integer := 8192;
type MEMType is array (0 to MEMSIZE - 1) of std_logic_vector(7 downto 0);
signal MEMData : MEMType;
signal adrDownload, adrUpload, adrUpload2 : integer range 0 to MEMSIZE - 1;
begin
-- The Busy and Acknowledge signals are not used by this module.
DOWNBSY <= '0';
UPBSY <= '0';
DOWNACK <= '1';
UPACK <= '1';
-- The read port of the synchronous memory is advanced when the read
-- signal is active. This way on the next clock cycle will output the
-- data from the next address.
adrUpload2 <= adrUpload + 1 when UPRD = '1' else adrUpload;
process (IFCLK)
begin
if rising_edge(IFCLK) then
-- Download address counter incremented while write signal is active.
if RST = '0' then
adrDownload <= 0;
elsif DOWNWR = '1' then
adrDownload <= adrDownload + 1;
end if;
-- Upload address counter incremented while read signal is active.
if RST = '0' then
adrUpload <= 0;
elsif UPRD = '1' then
adrUpload <= adrUpload + 1;
end if;
-- When write signal is active write the input data to the download
-- address.
if DOWNWR = '1' then
MEMData(adrDownload) <= DOWNDATA;
end if;
UPDATA <= MEMData(adrUpload2);
end if;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY HLS_accel_ap_faddfsub_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END HLS_accel_ap_faddfsub_3_full_dsp_32;
ARCHITECTURE HLS_accel_ap_faddfsub_3_full_dsp_32_arch OF HLS_accel_ap_faddfsub_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF HLS_accel_ap_faddfsub_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF HLS_accel_ap_faddfsub_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF HLS_accel_ap_faddfsub_3_full_dsp_32_arch : ARCHITECTURE IS "HLS_accel_ap_faddfsub_3_full_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF HLS_accel_ap_faddfsub_3_full_dsp_32_arch: ARCHITECTURE IS "HLS_accel_ap_faddfsub_3_full_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=1,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 1,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => s_axis_operation_tvalid,
s_axis_operation_tdata => s_axis_operation_tdata,
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END HLS_accel_ap_faddfsub_3_full_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY HLS_accel_ap_faddfsub_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END HLS_accel_ap_faddfsub_3_full_dsp_32;
ARCHITECTURE HLS_accel_ap_faddfsub_3_full_dsp_32_arch OF HLS_accel_ap_faddfsub_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF HLS_accel_ap_faddfsub_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF HLS_accel_ap_faddfsub_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF HLS_accel_ap_faddfsub_3_full_dsp_32_arch : ARCHITECTURE IS "HLS_accel_ap_faddfsub_3_full_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF HLS_accel_ap_faddfsub_3_full_dsp_32_arch: ARCHITECTURE IS "HLS_accel_ap_faddfsub_3_full_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=1,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 1,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => s_axis_operation_tvalid,
s_axis_operation_tdata => s_axis_operation_tdata,
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END HLS_accel_ap_faddfsub_3_full_dsp_32_arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
jVsAzLxgpQmm7+ojrYqXIidYnylvtv4kbTBSP8M9gok6/Xzgvc8DzYfj8xNjRkq0CCH+AL0SPAkL
t18NVNr1Ig==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
M5QLG1PaO+LyJ54ceRUavK5y3nmwtpxY+SC+6MI8E2/0/iV0q9Ea2KVgTcjiRGQ25pkI1ImL+JsL
mK8k0QEmrrsNG67HwHXT+hsRTR7G2B8/SoVDJlSrpjKZBmVWjsnIQi7RMwaQ6UwgoSNWQ7Nwdjov
aYoC/YqBmFOGnOKdEWY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pU5zPVr7Br9ZqC5qPZAAJSgBQYbA2VEf9Xxm3EDpiIwofFp2czxnjQlk4xbLuwVcvlAcOwJGqBOE
AJOmI1E3f/Af1zsy1n96wHI8AXm/xlSyFB+dZXef+RbxVp+HgT1EGm1KIqk2uymX1d7+QYCncm+j
yVGYSxT9aW982v+W+4iMep4fkpLdZ6Daxzj/qbrRSrL/G1FvX8CjIFq4gKjBl3ojH7GWELGakRlu
ThvbvPjfBGfQDwK0wL5Vxq552swlCN1l8RBSW2oovHb6cyVN06kluBIkYeh7bHmZumd3AlunZ0tC
yAc4ZESLwodNeQ++lO+AG6ifgOVSXlFZTsLAJQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
j8fUKCQEQiQh32P/IRFTF2lAmggcxfWzyQK/ncxCF/zCg2W3MVTcPKjhNLMFbBbvBaij46u8sjb3
sbaBo6dykfCSUcEtQgoDG1vfuVvZUw6/LqZ5vfwAiLGhe2unL1TXp3b9q/WFhlhTf8MMIEg+TwUC
pdWFaTvZ32zaWqGMLd8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
EnHa/6N/dhrMHr5CqFcQJ2vL0CW5JMDMZhWd5RO8a5u70uTKIwWqE/NxtrLg5y26CUlbjvJZoi4K
Pfnuek0rarHRhR0mYT8RfuO2GScmeoRjd/nQOThKVDkdc81QM3Si0oFrg+UlET/QvWEqOfwDMk3e
pW9nC/2z01hjEOzZXKXqpmZ75xqB+DvVkSK4lnuSJoKFiqUlgfyuTam9NT9u7yZsiazCXKQStN92
5tKO45Vo1LwDdYabBpX7ylrf1Nw39Gb7X8VmRFEs8GHUuZ4O4Zdrd/XfOGL141R0uS4x76swTaNq
o7n7Pyb1uahsHvg+oJftHQdUMYzIHucUIPKEpw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6304)
`protect data_block
OPfUPyN5lgj3kQbRUQ7lLhLN2X2q4aExhZ79CPmtI8tPSMWsybo9u+7Woeta971sVrKE8lffub5E
wmxgvCGhDHccJPaNCXwUEcg8J9Oux8pYd2gjbfAhe44PhaUcvTnN3jiYVeH54L5nyXS3Hxean+5D
IB/HaIHc5FHCrtlhB1OdfcaSUY9ldY45ymOah40g29gKTYboaOM0uzTBNu1yzQOOwlmwGyth5tRB
w+qxV95JlYZrASEu7ZyQSZm65nRnarlvQnDaOv/EfHBbZgl2guShgswygdZ7r4+6zpx9fD38XV7B
mgVHYy/3bTBbXniL5Ivw+3RqgEzl5USZm8MsBm0DXt+PTig06s4atbSU6MZEBaXgERt7S9u1HgmQ
xe3suyKZ9xET1tWKo3m5weKCT38AAD5ZI/mzxspkCyVcmSDiu44klyUjptZ7wlTVwedwPZDB85b3
/k0kvsdM+MGcdkc8clQxncTs8Ef7cfBT+REkX2wVReP7MIfBp5ixK6W3LGYDJtC6yiffpFtnGJFn
1MDWyS+mGg2cK3iNMiChaivQ9LHpZO2mJ3nbyYUvgDGKWaKxWqugnqUutoYyWOlNInv05XLDi/QQ
7IrpoZX3MRpaZTzm61JPP+2MmLv1V6u7WjEm+4Rw3KauO+d5cI8ZCPM8Y/5y1bxkqBXkqV8gMrfA
VQkXF1cTPVjcJLMbXt76wl5+w+n5FCNZs2DPrB2Mn5ETJhqjYfdIZmybz3YAPfbjBFgC4r+MJLF+
Z19LPHEmSTrEXDoUcH3xXaxWOgeMSd2SuwcXlCH8GLiiB7iUUIGSxXfV0M+8CetcDwq0FurEmVyD
FCr9RyVWIVqG4wLMSfuEQY6RDbsQdjI3UAuAJ8/TNBbx6M31NEAQRYtQxN/xHQ9wgsMRNbhrQGUd
SsajwVFYRAoNM6g2WvksAAkZDE/E0LVWEIP2e6jCrs9jMrkKUUZ4upAGGDLbkPJn1Gr7KPVD/i+Q
N9VfuYoDPstlR00jJPX965yKeLMbyH1gCcFjKZ9whlyll+agAhjW6XfhQoZPP3IPBprRyhB8kE0m
R/TP7z6+gqApum9PnGPXiEeScX4sD62OABpxM0XwqZqs9ihRp5UV+Jbc6CdR2bJaRdrB8j3Qj79s
8UFQNTVdv2Yy4uxarXe7inOi99RFnpAMAbuknLTNQW4a8lcfmcsGna7Lli32/ZmJYv8enkeQNL1Y
95zRNtC18ImUCluErs3v8qNStnaJXFsppESojDQpSno9O0mOFd1C27ipCQUxXJM+XGkXFDCEZpj1
a88FU6t5h+tB1V8NadyV78auu0RpGt0cjtYmvl3YKiDAo7tBOXoXu0BUs5oBxZGBOKkSTW+QhAic
vBXJV793ifMWm9v8Ef0Q98kHDmXqD2O9i6+Q26nHKRexveC6I4+qYWaMUsCWHXc08rCgLAere1JO
0lr+N0v7MY+5HIvXFeveb8tTlWEpualRta1TnRKaQKjMwmYSR4g/jeegSqaepF36/8KGB6l/HG2P
ONB7praU8JXHpQOu4/j2mb9pm81RMAH5Lll/ePY8k0p463YSnwEya1LbpJV2oM5AALbdKuVSFHZM
OhAPTJC50hggrUz0eaNvpe1bgwSKhgw5wAsYl9p0gl9RjHyOZNIps6lW/qlRd9GeqMrNixZva38X
6Ny9x5jDeLkO9hb5VFQQyYwWIPltS4HBX2UNyWRnrnkZj03A77wpyoJQWz3I7nfgHEsE8d4UW1RG
ZETWSUQ2DIthUcOINvWRy9uvYMnJQV5ei6hNYNfwqJMvXuLUnxuZLs9EK4QyZuU1Vo2LGE9Lh5AP
3yUDPJYZrv47cZvwP5u9Y7Xlr7lEV5+w6wdsQxl6uF74VzYB/c9cVmplOL+QKNUD7rYirepWnMzL
Ix5UDGfn3ZtsY6//tE6DSjyBa2uwymljeRfuWJC+HABl5tRcn7g8vfxf3WpEThYlhi4J6AwE0rEE
tCsEB+37ODYmi+uEpN4Qrz7adZTfLu91uJKEGjLznFPQLPVh7ct1Xa3a3v3V5UY44xNE6auawhCj
qn98JOiEPA9NhThGADlOqaKcsoeoHf/sPuHrARav9s3tKkUHQByOEZW/lqHo4kPAO1RWh6EXaQlJ
Jp4xoOhIDaXUd6n6pdNTWHPJ1xYwOz8R1gcy+heDi5RhwGvsSaMJMvrs7E8+r7GLJykPnLJLz5HW
0EFNyL0xk/prAKV693Wt8F+6Ns7ZY7S9VNr8wzohtOxtmlc0RDX89oGx7RCOcluiOX/lPUT9XwGM
6ew0GY+nXB6PrIKLyiKyaDsGWqF5R1o9oABZpqegXHtPEnBR02PSrRiZHKBxIZryu7r5Qb6/7XpU
j7e1XeoNNHrottNsm9uH2+DNpN4lU7yiwoyiM0zalsFD+s92tGnYkAy3wKeQfYBX9JO4aJDe4RIM
Ep8OZFwq21T80LA4Xt8ZPJ0UZoNZTAwaromMEHIt/kZ7tp+xROeFghSJJ/3obO4PJ65r470L2Dul
BHo+eiCG1pP6r+nlEdlM7uw72Ha3fQwq0bCEUVkgZJEp/+/qczBjLVG/WM9qDhyYUs79dEtEeRPJ
uPPTdLFgra1ODshaNgSzB9UP994b/rdXFpmM4rCl7+Vc2asp1RHKZ2/lk6GvVVzM841ZaemQFTch
6sVYmAPPR2XYvoDZw5HDa/gEUrSenzFUpeverYuuy57gq02KCniYXDLIcjgSex5MqtB4ZNnCspm8
3WbRsJdaJ93X6xNr8uOYEkvz0Rg3s9tSs49216D56ukXViZBYsMpwWl9lRJbre6xqrMztCQqhlNn
b+s2NJg9bkV0G1Pr+933sNUb5msr5Y4dNl4DF4ah6klIDlKIuwmfq2D9Wn8S3Ct+ZzkJ4CCFraTQ
sfNtWdn+DAyoV2XwcsznbfHXeQHnoa2NIIF7zdDIHrewhdEsUIDYjZkEM9pWWmFBYFgIXED+EAgx
Ft3FUYMZXFLXgrudbEBF2RGnQQeh7A+B+3RlixBLRCXPR1+4IZkSSEik3AZdJP/lFfO1fAYn/lLw
1OIiyRADk+DXE6dVF3A3AQLqhV+RwocO4viujuRDlj9x56BKc0a1gRR5l2kJqiZT2TLDNZKll3Q7
poBv+GU7kcJlsVbD5pXu+TdJfvV9dgPFo67GxnRe9PZrKzSvCeYgiqLVkx5ZMqQi0CWK+3yq4uaL
CpX7QtjmagEdZtCRcPCmqZTLETRI0Csf9RvSmNdRdjW8yXUutkwPwskxSemDjCp2vjrevWn+HKvR
afCNaKeHqZbjfWi0NWyJ9nsUAA9pdlfKubpoDJO04YA/3PT0s/L0XagA2rqtRLZGh/avk4rftYJk
b8Gz4w7Rbg2aqrhP3PmE1KRdgLgQERKuJvzUZHzUAi6s2tQ/zzUALtbuG3ukmnaP7jIuQS7ox1mG
EKAcnjTEj2bi/M2Uwhm+L8znmXwpO8Zhwtmfr0ol6fClgRQSlrkQenJTACmkkY0wXOF8G3tktEp9
NBOKO1cK1xhPQfXILWOT8ns3iLYJg4hmwGwMlGp2gBeuySkA+9iNPozqJSWXE/ebeQif6GgUhbyN
hoTwTZ5Hp0uYud75wydc6SJaEc2YBQxsNEFtcixWF5Z62+L5N+Ayq1lLTNYGo+g7Us0MxkO3t5oN
mzDqUuKqnlMiAyMEz67qaJ50jol1OpKD9FmlaGQuZ+DPMw3XjRXigP/A6cwmrp1EnDlbXKMqMumq
vL8K+16ipHf7DhhyoJHiPPicdZrH3D3mo+NRTnS5sdasNdR/1cess/nbZGrBa3CH0HscUHVsZHwL
HPTeK1lT7zBXQm4yuPd6Li6WK3jCiKOyDhaOlJZ5Q89GdZfvQ5ad2jHzIiyIyehBK2O7MCajTan3
Uq+xtv2RdKWqh+AeqGeej/F2XJYo0MxPRKqGM96fOyd4do5KLON6KsBlAzw1ewBRQ+2Je/7IALNW
ntsd8VKy9iwV/VFLo8gRGWVa4swHX0pNWvya31hkaqe5CILPhV308th6D4oY+7wKtZ1oR3Pj++dh
amst5nxXGT3D1byiu0fvVnRQ4ccOhzHvD7gEvo4dQwd6jNGOt3GOsclWnyk9gTvQD76cMaC2pbN6
3A8ykVUaO3WGPcPkfQIe4JbMP7k68NIs9Wex1R5AZjZH+AraM5tmTbw/PwEKREhYTu16FgkxxohY
id0tBeYKVCbk+yw8vlVX2yfvHh9TbcbGB33pAuyrIUexJETquDWvKoD0233ZI7z6PKk6WdnzS3hb
7bWztrkgkAufzA9vq//+qD2fqHCs9HKx+KvJ9jdrJddzNvdkDy4ZKFT25U7x214WDDwxtDRW+VHH
V1jcVE2XsJ6tVIOQ9oDuZqpTxzdiLruyu+Dq0l3RMJNrt++ysfjiJl+oVY92ZFs715+Quo8NcJXe
Opc+pezKzMxPbx8IVgfW+fgsfXw2nBfeEpFCguL62JTePoKc5OJcCF9MfD3Z2xJGqxO5K0t/rVh1
/W6Q2dmWVUjZ/a3LER2l8k1/IofiMPtgX1RTomFk7nTcdC6rXBTllAar8NG5FyGl7H7kYR1p7T0y
XSL5mvy/GmbS7c1VQxonLhkU2+W9hF8wVgSbi66Nzdc2KWBlOTsTw4JAgKqeFVfFyia5WKM2SnET
a4E5DGAyLC5aj/O5L+zL1zj2m9F9L4PZA3OOxXW5oSRfrT1FWa2SXAPfotslGunspnkNEhlofdIx
bIvUcEGcziTtD0WccgZOOaZ3hZg2nEDsTu00C5aDrJUNpEEoHmoYhnuTjXw+Up/1p3l3gSPFQvs6
y5gIiKObgHY5e2oVWYseWxrWM5YYbuI77bB75YBtnVv2pffrzWe53cVU60waOHbAsQPwM3542A2M
mSHRA4nLS16Z09AYWJrv4OuBMSza7U5LgHADta64HMZC2FYOM91UqNhQEGvgiwlCCRNnpewWfvK/
pt1xBrVkv+f0jR7aApSV8EuyscqS1Fh4zRQgAonNCPTZaGsHHjtavLCiL10UvdmdcBUN49+3anfn
HCX4If2KIhgcT5NS0T24a+hB4t+h8OZVotjXBuSXd07vaUWZ6RFPzVVffBN831soReyHttDX63q6
qPxDRMOtZDM06O7wRvFWF4cZ5cDdwMRxxnDb19GfMPiRXkZmaJufw76S0+YgNUoW3SJxz2iTX51+
vPLQYRvqVanHeaR2nmddTq8sBzPd7yYNrEjXHyknqb0SzVymv+n6KTdA8p0FwFkLQHImQoIet+e5
WSYdXD33uIqdK56My0NheXjEhMf672MG+ruQleJg+K+uJAgEniebu9TJRadb40deNXOCpr0kUXs3
HJk6NDPQnuKYXi40m+VFbS9/AwjxgzvOfIrqU/B428nxRxLDeMc+vb1OfAJ8HXQl5scFYFDU0OmQ
Zps9OGwUgTxQdPtLRcUyjBQKLV8bGCKnsZGcWp/clYJmWNV0k9d+KFZYir/bYLogGyEFrwiJiD+c
hINuk4/vrua0fv9bYyGg1CsgsF61ZpcqPTLPD3jSAfkqNQHvyRiQ5ctBl2GmEUMdKNm6wjt4ADg5
R9phacWbrpLA9S3srC3zHrz995LLYQKzHCyB5aW5RBeymtqklahKZdI8/gv4n0EvW4RFykQcwndZ
EIDd58JYHkU3ZoGfUiqVSFUdI/5RjCZv538pu5AwK+D4davZlM7keU55Bfc2K0d19/32d1jqnohc
ytyw11+OuBTN1lRWBg+tSu6BFaEk7cyrw8wdU3zcBAbOcBs4v39XJYNLL1SMHOqktrLvT5xOVrBv
92/rFyWyAYPdoNhRrXBd7zyX11xt64vQgRagRgz2wvVl7RRUas1zuN2xAjKekPF3MVtwI7IW9gC2
mbDSpBejx5UbrnsEpYyySbYIn+SCOhUWTp4mqTHHenTtNU/RgECCQ8HsmSf/MY7GHVHc1mawFnlD
Lz7xWpEqU8JkyzgxI/cABmD6k2X9s9PhIVO53whquDEd8FHlttrVQbBVYL9YZDkEkDwRbZIizOUQ
SfctJMLRFAUwu14D1LFrPcZhY7uje9n+MxetIJ5liHcugAwzoPOgZZ7uCul4Dw7TA4uNddhSEsNU
VHcRr2NdjVJs7Cc7alSq+ZdeExDJ2jE0cMhttwJtAg+XC87OnoiT0Swi2y6PaKXPDnIxnU04n2kM
e+rxfXo86CUakswX1HW3apnkY8w+VUMncjjsroqIlHkj2rShi6Yw0AJAW2r+7Gc5TcC+ils8Q2GE
hMcVoK2R6k3OSAZfuoN/N4JE7s7W7n8VnheBjMkX12cfrEi7dJzIvS1S9NyLZ7gDnBSmM1WjBFE+
/1MIy4qX6pWTd+IE6afDjj+p6TustmrL/74mK4QnO5tgpQfen5FhNSfbKUaJyhsJlNi4tAMzRBhr
znbNMjC2W4Q5a/+AEPEgMFz46D8JMbF0uXypurh9UZ7zbShDbDSO0JIUO2n10M35n/PmkEI3mKYI
l4Nu/VIyWkR9FdcuRTAbcBs/q6kFtWaB/zxcoGcfljFUvxwZat1Om3g7A/k6yn9vTu9WP5kU1387
xjyU+9ivpEbsqsJWtTHS7Udc6fVbh7zwIcGZUrqAaX9V8AsmYsOvNedyiNoK+7XTQcpIQco88azd
cfLlvFxzmhvZVF9h/1PQtQW4sCbGQn2q3eqWVScB+HQCvHsT5CBIrfeHhFiSHvXSVv5NxlF0nTlc
rKwcORUGMueZXo5Snftu7vaoAZqqmlmImQA51FizGVuZPoG9bKRic3llKwihA5NRa8kAmSSRQsd3
PrckC4rbECxX1Qgloag0p24dkVDyxXZEwvh3vxYEajT4rmq6mCMnDBOYyU9a//Uru5CT8DhimX7d
eyxdLdZM2dwKwgpH3sGKy+XTYj9M/trLRP3fg9r9sAxbws5oru+2rFut4rw/vqyRlcjbuxU088yQ
Mgo5lyXfg1hrqcoM+mltseJt4DznIF5u65z4PtVIHyRbRSNuFrpWD77atkh3yfh+o3MOn+ZY8tK7
SmWEHVaKBmnbgPYZdWU36nGi7EEor0ozHsQTL0LM3hSfZ/r4470ZvqSsqW7AdmF0nMQrMy0ar2Kd
8rhWyRHeIFT6xogzifQYEilCgYVumfjgJdhUPU9ytAjF/y9CCzA0f9sSnlv/GD39XNyV8cJa+FpP
cfIi4TTGgACdZVTobaUNp2thkenQflKS+jQJV1iy9JkE722az0PhQghiKfR+wC592ZI+PVJzQI5D
ySZ9pQWBzb5wPqqLKpOOEdYlT2aO98kpARiddij+Qg3VNcdz3oAI6769/DNjFtxFFaeXepdWUJJl
ZovCWKPdpJhYN8rT/z/Xm6bO2A/TKD8qA3eqrhux2ALGkRxsWkNSwrtXv7Ww30O27eDLXZFpiEOg
AXOzlqT1wL+yAunedezWHxpW6YDTM1A7HA0LstYantJ7uFQIlni5BbuZ+duGqkg/IYl312rWPv5W
BRYZOv6ThCibkMclk35ggnrgBOIoGxA6blKJgioOH2m3kmMs9g2KC5o62dmr9csizC6aavN/8SAd
MyBPemtEOk1pFmOfaKv+0tjedjbc3d9JQfSdCUAE6O31El2KXD7Nj94EDSocdGSQdeDbbq1diqMl
l4uRuE5q2VqDFkm1mt+16iI1rl3TGqZJNwMnLAOv4ix16tCtSPJwrXy/YElN0K3MyRS4nSR33Er6
pzGA5Ui80l9ZLqlMIqVCdYnyZeUfhSLbrnli1axvIt0jfIyztBLhfGVtBAihwnyEwgsvPYvCg+Un
Qvsnd7n3XhBhShy5ogrEJ3zfNd81XfNozfwpvXUatUbzR6rV/FlpCm/2SdP0ilrSmdwWeQqy5rF1
FyKDVmRAZ21Cnk715VzvKnBdiPzaTmb+MgQKCiEM/4ULRsCxPPZh0P+VyFwCHe+KEaKH/eZkGGzb
UE42NksZ88R0NWnVShAAsNH1rB1XMTeRCfOB5lqWokKg96lyh85Wlm9PuEs33DAQo4Sd39/PfmEl
aSRhmbfSnG8OVyZZh7ZC/AdmgVr3hFGReoEso16FFfG/CySs5IAEVTAJ8oDVKUJBfDk+m1+nv6LT
xSY8dtGKqnHPbZALHbv60VZOF60h375f4caf/LmpvEBQZlTKm8tc9+7/Yo1KJcxGVaCCnRYi4mRK
NJPCUrklDg0h+6lugE6qOzFy619cHa8di78RIlVUBqktH/j2N+95b3fqNyIDk7iOCtN+/nk8r/th
EJJZMufyfROTo/l6SMVXScnJ/WSRvbVqUNTqFMTwDhW+P6i+4xkDOII7HZzB+SAAtK5m+FEVOS04
AsGz1D6YRn7zYX5sr2F1+I3+kfthuh+K5WUE5HWwVM0aj1O0oR3EJagNUYPNHpj/P6n4U5m4s/qq
j3SOa1DxgdaOrSknNzmKvCP3hSFjAB2bVt2ToHdXMh/IBw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
jVsAzLxgpQmm7+ojrYqXIidYnylvtv4kbTBSP8M9gok6/Xzgvc8DzYfj8xNjRkq0CCH+AL0SPAkL
t18NVNr1Ig==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
M5QLG1PaO+LyJ54ceRUavK5y3nmwtpxY+SC+6MI8E2/0/iV0q9Ea2KVgTcjiRGQ25pkI1ImL+JsL
mK8k0QEmrrsNG67HwHXT+hsRTR7G2B8/SoVDJlSrpjKZBmVWjsnIQi7RMwaQ6UwgoSNWQ7Nwdjov
aYoC/YqBmFOGnOKdEWY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pU5zPVr7Br9ZqC5qPZAAJSgBQYbA2VEf9Xxm3EDpiIwofFp2czxnjQlk4xbLuwVcvlAcOwJGqBOE
AJOmI1E3f/Af1zsy1n96wHI8AXm/xlSyFB+dZXef+RbxVp+HgT1EGm1KIqk2uymX1d7+QYCncm+j
yVGYSxT9aW982v+W+4iMep4fkpLdZ6Daxzj/qbrRSrL/G1FvX8CjIFq4gKjBl3ojH7GWELGakRlu
ThvbvPjfBGfQDwK0wL5Vxq552swlCN1l8RBSW2oovHb6cyVN06kluBIkYeh7bHmZumd3AlunZ0tC
yAc4ZESLwodNeQ++lO+AG6ifgOVSXlFZTsLAJQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
j8fUKCQEQiQh32P/IRFTF2lAmggcxfWzyQK/ncxCF/zCg2W3MVTcPKjhNLMFbBbvBaij46u8sjb3
sbaBo6dykfCSUcEtQgoDG1vfuVvZUw6/LqZ5vfwAiLGhe2unL1TXp3b9q/WFhlhTf8MMIEg+TwUC
pdWFaTvZ32zaWqGMLd8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
EnHa/6N/dhrMHr5CqFcQJ2vL0CW5JMDMZhWd5RO8a5u70uTKIwWqE/NxtrLg5y26CUlbjvJZoi4K
Pfnuek0rarHRhR0mYT8RfuO2GScmeoRjd/nQOThKVDkdc81QM3Si0oFrg+UlET/QvWEqOfwDMk3e
pW9nC/2z01hjEOzZXKXqpmZ75xqB+DvVkSK4lnuSJoKFiqUlgfyuTam9NT9u7yZsiazCXKQStN92
5tKO45Vo1LwDdYabBpX7ylrf1Nw39Gb7X8VmRFEs8GHUuZ4O4Zdrd/XfOGL141R0uS4x76swTaNq
o7n7Pyb1uahsHvg+oJftHQdUMYzIHucUIPKEpw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6304)
`protect data_block
OPfUPyN5lgj3kQbRUQ7lLhLN2X2q4aExhZ79CPmtI8tPSMWsybo9u+7Woeta971sVrKE8lffub5E
wmxgvCGhDHccJPaNCXwUEcg8J9Oux8pYd2gjbfAhe44PhaUcvTnN3jiYVeH54L5nyXS3Hxean+5D
IB/HaIHc5FHCrtlhB1OdfcaSUY9ldY45ymOah40g29gKTYboaOM0uzTBNu1yzQOOwlmwGyth5tRB
w+qxV95JlYZrASEu7ZyQSZm65nRnarlvQnDaOv/EfHBbZgl2guShgswygdZ7r4+6zpx9fD38XV7B
mgVHYy/3bTBbXniL5Ivw+3RqgEzl5USZm8MsBm0DXt+PTig06s4atbSU6MZEBaXgERt7S9u1HgmQ
xe3suyKZ9xET1tWKo3m5weKCT38AAD5ZI/mzxspkCyVcmSDiu44klyUjptZ7wlTVwedwPZDB85b3
/k0kvsdM+MGcdkc8clQxncTs8Ef7cfBT+REkX2wVReP7MIfBp5ixK6W3LGYDJtC6yiffpFtnGJFn
1MDWyS+mGg2cK3iNMiChaivQ9LHpZO2mJ3nbyYUvgDGKWaKxWqugnqUutoYyWOlNInv05XLDi/QQ
7IrpoZX3MRpaZTzm61JPP+2MmLv1V6u7WjEm+4Rw3KauO+d5cI8ZCPM8Y/5y1bxkqBXkqV8gMrfA
VQkXF1cTPVjcJLMbXt76wl5+w+n5FCNZs2DPrB2Mn5ETJhqjYfdIZmybz3YAPfbjBFgC4r+MJLF+
Z19LPHEmSTrEXDoUcH3xXaxWOgeMSd2SuwcXlCH8GLiiB7iUUIGSxXfV0M+8CetcDwq0FurEmVyD
FCr9RyVWIVqG4wLMSfuEQY6RDbsQdjI3UAuAJ8/TNBbx6M31NEAQRYtQxN/xHQ9wgsMRNbhrQGUd
SsajwVFYRAoNM6g2WvksAAkZDE/E0LVWEIP2e6jCrs9jMrkKUUZ4upAGGDLbkPJn1Gr7KPVD/i+Q
N9VfuYoDPstlR00jJPX965yKeLMbyH1gCcFjKZ9whlyll+agAhjW6XfhQoZPP3IPBprRyhB8kE0m
R/TP7z6+gqApum9PnGPXiEeScX4sD62OABpxM0XwqZqs9ihRp5UV+Jbc6CdR2bJaRdrB8j3Qj79s
8UFQNTVdv2Yy4uxarXe7inOi99RFnpAMAbuknLTNQW4a8lcfmcsGna7Lli32/ZmJYv8enkeQNL1Y
95zRNtC18ImUCluErs3v8qNStnaJXFsppESojDQpSno9O0mOFd1C27ipCQUxXJM+XGkXFDCEZpj1
a88FU6t5h+tB1V8NadyV78auu0RpGt0cjtYmvl3YKiDAo7tBOXoXu0BUs5oBxZGBOKkSTW+QhAic
vBXJV793ifMWm9v8Ef0Q98kHDmXqD2O9i6+Q26nHKRexveC6I4+qYWaMUsCWHXc08rCgLAere1JO
0lr+N0v7MY+5HIvXFeveb8tTlWEpualRta1TnRKaQKjMwmYSR4g/jeegSqaepF36/8KGB6l/HG2P
ONB7praU8JXHpQOu4/j2mb9pm81RMAH5Lll/ePY8k0p463YSnwEya1LbpJV2oM5AALbdKuVSFHZM
OhAPTJC50hggrUz0eaNvpe1bgwSKhgw5wAsYl9p0gl9RjHyOZNIps6lW/qlRd9GeqMrNixZva38X
6Ny9x5jDeLkO9hb5VFQQyYwWIPltS4HBX2UNyWRnrnkZj03A77wpyoJQWz3I7nfgHEsE8d4UW1RG
ZETWSUQ2DIthUcOINvWRy9uvYMnJQV5ei6hNYNfwqJMvXuLUnxuZLs9EK4QyZuU1Vo2LGE9Lh5AP
3yUDPJYZrv47cZvwP5u9Y7Xlr7lEV5+w6wdsQxl6uF74VzYB/c9cVmplOL+QKNUD7rYirepWnMzL
Ix5UDGfn3ZtsY6//tE6DSjyBa2uwymljeRfuWJC+HABl5tRcn7g8vfxf3WpEThYlhi4J6AwE0rEE
tCsEB+37ODYmi+uEpN4Qrz7adZTfLu91uJKEGjLznFPQLPVh7ct1Xa3a3v3V5UY44xNE6auawhCj
qn98JOiEPA9NhThGADlOqaKcsoeoHf/sPuHrARav9s3tKkUHQByOEZW/lqHo4kPAO1RWh6EXaQlJ
Jp4xoOhIDaXUd6n6pdNTWHPJ1xYwOz8R1gcy+heDi5RhwGvsSaMJMvrs7E8+r7GLJykPnLJLz5HW
0EFNyL0xk/prAKV693Wt8F+6Ns7ZY7S9VNr8wzohtOxtmlc0RDX89oGx7RCOcluiOX/lPUT9XwGM
6ew0GY+nXB6PrIKLyiKyaDsGWqF5R1o9oABZpqegXHtPEnBR02PSrRiZHKBxIZryu7r5Qb6/7XpU
j7e1XeoNNHrottNsm9uH2+DNpN4lU7yiwoyiM0zalsFD+s92tGnYkAy3wKeQfYBX9JO4aJDe4RIM
Ep8OZFwq21T80LA4Xt8ZPJ0UZoNZTAwaromMEHIt/kZ7tp+xROeFghSJJ/3obO4PJ65r470L2Dul
BHo+eiCG1pP6r+nlEdlM7uw72Ha3fQwq0bCEUVkgZJEp/+/qczBjLVG/WM9qDhyYUs79dEtEeRPJ
uPPTdLFgra1ODshaNgSzB9UP994b/rdXFpmM4rCl7+Vc2asp1RHKZ2/lk6GvVVzM841ZaemQFTch
6sVYmAPPR2XYvoDZw5HDa/gEUrSenzFUpeverYuuy57gq02KCniYXDLIcjgSex5MqtB4ZNnCspm8
3WbRsJdaJ93X6xNr8uOYEkvz0Rg3s9tSs49216D56ukXViZBYsMpwWl9lRJbre6xqrMztCQqhlNn
b+s2NJg9bkV0G1Pr+933sNUb5msr5Y4dNl4DF4ah6klIDlKIuwmfq2D9Wn8S3Ct+ZzkJ4CCFraTQ
sfNtWdn+DAyoV2XwcsznbfHXeQHnoa2NIIF7zdDIHrewhdEsUIDYjZkEM9pWWmFBYFgIXED+EAgx
Ft3FUYMZXFLXgrudbEBF2RGnQQeh7A+B+3RlixBLRCXPR1+4IZkSSEik3AZdJP/lFfO1fAYn/lLw
1OIiyRADk+DXE6dVF3A3AQLqhV+RwocO4viujuRDlj9x56BKc0a1gRR5l2kJqiZT2TLDNZKll3Q7
poBv+GU7kcJlsVbD5pXu+TdJfvV9dgPFo67GxnRe9PZrKzSvCeYgiqLVkx5ZMqQi0CWK+3yq4uaL
CpX7QtjmagEdZtCRcPCmqZTLETRI0Csf9RvSmNdRdjW8yXUutkwPwskxSemDjCp2vjrevWn+HKvR
afCNaKeHqZbjfWi0NWyJ9nsUAA9pdlfKubpoDJO04YA/3PT0s/L0XagA2rqtRLZGh/avk4rftYJk
b8Gz4w7Rbg2aqrhP3PmE1KRdgLgQERKuJvzUZHzUAi6s2tQ/zzUALtbuG3ukmnaP7jIuQS7ox1mG
EKAcnjTEj2bi/M2Uwhm+L8znmXwpO8Zhwtmfr0ol6fClgRQSlrkQenJTACmkkY0wXOF8G3tktEp9
NBOKO1cK1xhPQfXILWOT8ns3iLYJg4hmwGwMlGp2gBeuySkA+9iNPozqJSWXE/ebeQif6GgUhbyN
hoTwTZ5Hp0uYud75wydc6SJaEc2YBQxsNEFtcixWF5Z62+L5N+Ayq1lLTNYGo+g7Us0MxkO3t5oN
mzDqUuKqnlMiAyMEz67qaJ50jol1OpKD9FmlaGQuZ+DPMw3XjRXigP/A6cwmrp1EnDlbXKMqMumq
vL8K+16ipHf7DhhyoJHiPPicdZrH3D3mo+NRTnS5sdasNdR/1cess/nbZGrBa3CH0HscUHVsZHwL
HPTeK1lT7zBXQm4yuPd6Li6WK3jCiKOyDhaOlJZ5Q89GdZfvQ5ad2jHzIiyIyehBK2O7MCajTan3
Uq+xtv2RdKWqh+AeqGeej/F2XJYo0MxPRKqGM96fOyd4do5KLON6KsBlAzw1ewBRQ+2Je/7IALNW
ntsd8VKy9iwV/VFLo8gRGWVa4swHX0pNWvya31hkaqe5CILPhV308th6D4oY+7wKtZ1oR3Pj++dh
amst5nxXGT3D1byiu0fvVnRQ4ccOhzHvD7gEvo4dQwd6jNGOt3GOsclWnyk9gTvQD76cMaC2pbN6
3A8ykVUaO3WGPcPkfQIe4JbMP7k68NIs9Wex1R5AZjZH+AraM5tmTbw/PwEKREhYTu16FgkxxohY
id0tBeYKVCbk+yw8vlVX2yfvHh9TbcbGB33pAuyrIUexJETquDWvKoD0233ZI7z6PKk6WdnzS3hb
7bWztrkgkAufzA9vq//+qD2fqHCs9HKx+KvJ9jdrJddzNvdkDy4ZKFT25U7x214WDDwxtDRW+VHH
V1jcVE2XsJ6tVIOQ9oDuZqpTxzdiLruyu+Dq0l3RMJNrt++ysfjiJl+oVY92ZFs715+Quo8NcJXe
Opc+pezKzMxPbx8IVgfW+fgsfXw2nBfeEpFCguL62JTePoKc5OJcCF9MfD3Z2xJGqxO5K0t/rVh1
/W6Q2dmWVUjZ/a3LER2l8k1/IofiMPtgX1RTomFk7nTcdC6rXBTllAar8NG5FyGl7H7kYR1p7T0y
XSL5mvy/GmbS7c1VQxonLhkU2+W9hF8wVgSbi66Nzdc2KWBlOTsTw4JAgKqeFVfFyia5WKM2SnET
a4E5DGAyLC5aj/O5L+zL1zj2m9F9L4PZA3OOxXW5oSRfrT1FWa2SXAPfotslGunspnkNEhlofdIx
bIvUcEGcziTtD0WccgZOOaZ3hZg2nEDsTu00C5aDrJUNpEEoHmoYhnuTjXw+Up/1p3l3gSPFQvs6
y5gIiKObgHY5e2oVWYseWxrWM5YYbuI77bB75YBtnVv2pffrzWe53cVU60waOHbAsQPwM3542A2M
mSHRA4nLS16Z09AYWJrv4OuBMSza7U5LgHADta64HMZC2FYOM91UqNhQEGvgiwlCCRNnpewWfvK/
pt1xBrVkv+f0jR7aApSV8EuyscqS1Fh4zRQgAonNCPTZaGsHHjtavLCiL10UvdmdcBUN49+3anfn
HCX4If2KIhgcT5NS0T24a+hB4t+h8OZVotjXBuSXd07vaUWZ6RFPzVVffBN831soReyHttDX63q6
qPxDRMOtZDM06O7wRvFWF4cZ5cDdwMRxxnDb19GfMPiRXkZmaJufw76S0+YgNUoW3SJxz2iTX51+
vPLQYRvqVanHeaR2nmddTq8sBzPd7yYNrEjXHyknqb0SzVymv+n6KTdA8p0FwFkLQHImQoIet+e5
WSYdXD33uIqdK56My0NheXjEhMf672MG+ruQleJg+K+uJAgEniebu9TJRadb40deNXOCpr0kUXs3
HJk6NDPQnuKYXi40m+VFbS9/AwjxgzvOfIrqU/B428nxRxLDeMc+vb1OfAJ8HXQl5scFYFDU0OmQ
Zps9OGwUgTxQdPtLRcUyjBQKLV8bGCKnsZGcWp/clYJmWNV0k9d+KFZYir/bYLogGyEFrwiJiD+c
hINuk4/vrua0fv9bYyGg1CsgsF61ZpcqPTLPD3jSAfkqNQHvyRiQ5ctBl2GmEUMdKNm6wjt4ADg5
R9phacWbrpLA9S3srC3zHrz995LLYQKzHCyB5aW5RBeymtqklahKZdI8/gv4n0EvW4RFykQcwndZ
EIDd58JYHkU3ZoGfUiqVSFUdI/5RjCZv538pu5AwK+D4davZlM7keU55Bfc2K0d19/32d1jqnohc
ytyw11+OuBTN1lRWBg+tSu6BFaEk7cyrw8wdU3zcBAbOcBs4v39XJYNLL1SMHOqktrLvT5xOVrBv
92/rFyWyAYPdoNhRrXBd7zyX11xt64vQgRagRgz2wvVl7RRUas1zuN2xAjKekPF3MVtwI7IW9gC2
mbDSpBejx5UbrnsEpYyySbYIn+SCOhUWTp4mqTHHenTtNU/RgECCQ8HsmSf/MY7GHVHc1mawFnlD
Lz7xWpEqU8JkyzgxI/cABmD6k2X9s9PhIVO53whquDEd8FHlttrVQbBVYL9YZDkEkDwRbZIizOUQ
SfctJMLRFAUwu14D1LFrPcZhY7uje9n+MxetIJ5liHcugAwzoPOgZZ7uCul4Dw7TA4uNddhSEsNU
VHcRr2NdjVJs7Cc7alSq+ZdeExDJ2jE0cMhttwJtAg+XC87OnoiT0Swi2y6PaKXPDnIxnU04n2kM
e+rxfXo86CUakswX1HW3apnkY8w+VUMncjjsroqIlHkj2rShi6Yw0AJAW2r+7Gc5TcC+ils8Q2GE
hMcVoK2R6k3OSAZfuoN/N4JE7s7W7n8VnheBjMkX12cfrEi7dJzIvS1S9NyLZ7gDnBSmM1WjBFE+
/1MIy4qX6pWTd+IE6afDjj+p6TustmrL/74mK4QnO5tgpQfen5FhNSfbKUaJyhsJlNi4tAMzRBhr
znbNMjC2W4Q5a/+AEPEgMFz46D8JMbF0uXypurh9UZ7zbShDbDSO0JIUO2n10M35n/PmkEI3mKYI
l4Nu/VIyWkR9FdcuRTAbcBs/q6kFtWaB/zxcoGcfljFUvxwZat1Om3g7A/k6yn9vTu9WP5kU1387
xjyU+9ivpEbsqsJWtTHS7Udc6fVbh7zwIcGZUrqAaX9V8AsmYsOvNedyiNoK+7XTQcpIQco88azd
cfLlvFxzmhvZVF9h/1PQtQW4sCbGQn2q3eqWVScB+HQCvHsT5CBIrfeHhFiSHvXSVv5NxlF0nTlc
rKwcORUGMueZXo5Snftu7vaoAZqqmlmImQA51FizGVuZPoG9bKRic3llKwihA5NRa8kAmSSRQsd3
PrckC4rbECxX1Qgloag0p24dkVDyxXZEwvh3vxYEajT4rmq6mCMnDBOYyU9a//Uru5CT8DhimX7d
eyxdLdZM2dwKwgpH3sGKy+XTYj9M/trLRP3fg9r9sAxbws5oru+2rFut4rw/vqyRlcjbuxU088yQ
Mgo5lyXfg1hrqcoM+mltseJt4DznIF5u65z4PtVIHyRbRSNuFrpWD77atkh3yfh+o3MOn+ZY8tK7
SmWEHVaKBmnbgPYZdWU36nGi7EEor0ozHsQTL0LM3hSfZ/r4470ZvqSsqW7AdmF0nMQrMy0ar2Kd
8rhWyRHeIFT6xogzifQYEilCgYVumfjgJdhUPU9ytAjF/y9CCzA0f9sSnlv/GD39XNyV8cJa+FpP
cfIi4TTGgACdZVTobaUNp2thkenQflKS+jQJV1iy9JkE722az0PhQghiKfR+wC592ZI+PVJzQI5D
ySZ9pQWBzb5wPqqLKpOOEdYlT2aO98kpARiddij+Qg3VNcdz3oAI6769/DNjFtxFFaeXepdWUJJl
ZovCWKPdpJhYN8rT/z/Xm6bO2A/TKD8qA3eqrhux2ALGkRxsWkNSwrtXv7Ww30O27eDLXZFpiEOg
AXOzlqT1wL+yAunedezWHxpW6YDTM1A7HA0LstYantJ7uFQIlni5BbuZ+duGqkg/IYl312rWPv5W
BRYZOv6ThCibkMclk35ggnrgBOIoGxA6blKJgioOH2m3kmMs9g2KC5o62dmr9csizC6aavN/8SAd
MyBPemtEOk1pFmOfaKv+0tjedjbc3d9JQfSdCUAE6O31El2KXD7Nj94EDSocdGSQdeDbbq1diqMl
l4uRuE5q2VqDFkm1mt+16iI1rl3TGqZJNwMnLAOv4ix16tCtSPJwrXy/YElN0K3MyRS4nSR33Er6
pzGA5Ui80l9ZLqlMIqVCdYnyZeUfhSLbrnli1axvIt0jfIyztBLhfGVtBAihwnyEwgsvPYvCg+Un
Qvsnd7n3XhBhShy5ogrEJ3zfNd81XfNozfwpvXUatUbzR6rV/FlpCm/2SdP0ilrSmdwWeQqy5rF1
FyKDVmRAZ21Cnk715VzvKnBdiPzaTmb+MgQKCiEM/4ULRsCxPPZh0P+VyFwCHe+KEaKH/eZkGGzb
UE42NksZ88R0NWnVShAAsNH1rB1XMTeRCfOB5lqWokKg96lyh85Wlm9PuEs33DAQo4Sd39/PfmEl
aSRhmbfSnG8OVyZZh7ZC/AdmgVr3hFGReoEso16FFfG/CySs5IAEVTAJ8oDVKUJBfDk+m1+nv6LT
xSY8dtGKqnHPbZALHbv60VZOF60h375f4caf/LmpvEBQZlTKm8tc9+7/Yo1KJcxGVaCCnRYi4mRK
NJPCUrklDg0h+6lugE6qOzFy619cHa8di78RIlVUBqktH/j2N+95b3fqNyIDk7iOCtN+/nk8r/th
EJJZMufyfROTo/l6SMVXScnJ/WSRvbVqUNTqFMTwDhW+P6i+4xkDOII7HZzB+SAAtK5m+FEVOS04
AsGz1D6YRn7zYX5sr2F1+I3+kfthuh+K5WUE5HWwVM0aj1O0oR3EJagNUYPNHpj/P6n4U5m4s/qq
j3SOa1DxgdaOrSknNzmKvCP3hSFjAB2bVt2ToHdXMh/IBw==
`protect end_protected
|
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: valid_be.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- valid_be - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: valid_be.vhd
-- Version: v1.00a
-- Description: Determines valid OPB access for memory devices
--
-------------------------------------------------------------------------------
-- Structure:
--
-- valid_be.vhd
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- ALS 09/21/01 -- First version
-- ^^^^^^
-- First version of valid_be created from BLT's file, valid_access. Made
-- modifications to support a target data bus width and a host data bus
-- width.
-- ~~~~~~
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity valid_be is
generic (
C_HOST_DW : integer range 8 to 256 := 32;
C_TARGET_DW : integer range 8 to 32 := 32
);
port (
OPB_BE_Reg : in std_logic_vector(0 to C_HOST_DW/8-1);
Valid : out std_logic
);
end entity valid_be;
architecture implementation of valid_be is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant HOST_LOGVAL : integer := log2(C_HOST_DW/8); -- log value for host bus
constant TAR_LOGVAL : integer := log2(C_TARGET_DW/8); -- log value for target bus
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- VALID_ACCESS_PROCESS: this is a general purpose process that returns
-- whether or not a particular byte enable code is valid for a particular host
-- bus size and target bus size. The byte enable bus can be up to 32 bits wide,
-- supporting host bus widths up to 256 bits.
--
-- Example:
-- HOST BUS SIZE(OPB) TARGET BUS SIZE (SRAM) Valid BE
-- ----------------- ---------------------- --------
-- 8 8 '1'
-- 16 8 "01"
-- "10"
-- 16 16 "01"
-- "10"
-- "11"
-- 32 8 "0001"
-- "0010"
-- "0100"
-- "1000"
-- 32 16 "0001"
-- "0010"
-- "0100"
-- "1000"
-- "0011"
-- "1100"
-- 32 32 "0001"
-- "0010"
-- "0100"
-- "1000"
-- "0011"
-- "1100"
-- "1111"
-------------------------------------------------------------------------------
VALID_ACCESS_PROCESS: process (OPB_BE_Reg) is
variable compare_Val : integer := 0;
begin
Valid <= '0';
for i in 0 to TAR_LOGVAL loop -- loop for bits in target data bus
compare_Val := pwr(2,pwr(2,i))-1;
for j in 0 to pwr(2,HOST_LOGVAL-i) loop
if Conv_integer('0' & OPB_BE_Reg) = compare_Val then Valid <= '1'; end if;
compare_Val := compare_Val*pwr(2,pwr(2,i));
end loop;
end loop;
end process VALID_ACCESS_PROCESS;
end architecture implementation;
|
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: valid_be.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- valid_be - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: valid_be.vhd
-- Version: v1.00a
-- Description: Determines valid OPB access for memory devices
--
-------------------------------------------------------------------------------
-- Structure:
--
-- valid_be.vhd
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- ALS 09/21/01 -- First version
-- ^^^^^^
-- First version of valid_be created from BLT's file, valid_access. Made
-- modifications to support a target data bus width and a host data bus
-- width.
-- ~~~~~~
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity valid_be is
generic (
C_HOST_DW : integer range 8 to 256 := 32;
C_TARGET_DW : integer range 8 to 32 := 32
);
port (
OPB_BE_Reg : in std_logic_vector(0 to C_HOST_DW/8-1);
Valid : out std_logic
);
end entity valid_be;
architecture implementation of valid_be is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant HOST_LOGVAL : integer := log2(C_HOST_DW/8); -- log value for host bus
constant TAR_LOGVAL : integer := log2(C_TARGET_DW/8); -- log value for target bus
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- VALID_ACCESS_PROCESS: this is a general purpose process that returns
-- whether or not a particular byte enable code is valid for a particular host
-- bus size and target bus size. The byte enable bus can be up to 32 bits wide,
-- supporting host bus widths up to 256 bits.
--
-- Example:
-- HOST BUS SIZE(OPB) TARGET BUS SIZE (SRAM) Valid BE
-- ----------------- ---------------------- --------
-- 8 8 '1'
-- 16 8 "01"
-- "10"
-- 16 16 "01"
-- "10"
-- "11"
-- 32 8 "0001"
-- "0010"
-- "0100"
-- "1000"
-- 32 16 "0001"
-- "0010"
-- "0100"
-- "1000"
-- "0011"
-- "1100"
-- 32 32 "0001"
-- "0010"
-- "0100"
-- "1000"
-- "0011"
-- "1100"
-- "1111"
-------------------------------------------------------------------------------
VALID_ACCESS_PROCESS: process (OPB_BE_Reg) is
variable compare_Val : integer := 0;
begin
Valid <= '0';
for i in 0 to TAR_LOGVAL loop -- loop for bits in target data bus
compare_Val := pwr(2,pwr(2,i))-1;
for j in 0 to pwr(2,HOST_LOGVAL-i) loop
if Conv_integer('0' & OPB_BE_Reg) = compare_Val then Valid <= '1'; end if;
compare_Val := compare_Val*pwr(2,pwr(2,i));
end loop;
end loop;
end process VALID_ACCESS_PROCESS;
end architecture implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reconos_hwt_idle is
port (
-- OSIF FIFO ports
OSIF_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_Sw2Hw_Empty : in std_logic;
OSIF_Sw2Hw_RE : out std_logic;
OSIF_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_Hw2Sw_Full : in std_logic;
OSIF_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_Hwt2Mem_Full : in std_logic;
MEMIF_Hwt2Mem_WE : out std_logic;
MEMIF_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_Mem2Hwt_Empty : in std_logic;
MEMIF_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic;
HWT_Signal : in std_logic
);
end entity reconos_hwt_idle;
architecture imp of reconos_hwt_idle is
-- Declare port attributes for the Vivado IP Packager
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of HWT_Clk: SIGNAL is "xilinx.com:signal:clock:1.0 HWT_Clk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER of HWT_Clk: SIGNAL is "ASSOCIATED_RESET HWT_Rst, ASSOCIATED_BUSIF OSIF_Sw2Hw:OSIF_Hw2Sw:MEMIF_Hwt2Mem:MEMIF_Mem2Hwt";
ATTRIBUTE X_INTERFACE_INFO of HWT_Rst: SIGNAL is "xilinx.com:signal:reset:1.0 HWT_Rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER of HWT_Rst: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO of OSIF_Sw2Hw_Data: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 OSIF_Sw2Hw FIFO_S_Data";
ATTRIBUTE X_INTERFACE_INFO of OSIF_Sw2Hw_Empty: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 OSIF_Sw2Hw FIFO_S_Empty";
ATTRIBUTE X_INTERFACE_INFO of OSIF_Sw2Hw_RE: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 OSIF_Sw2Hw FIFO_S_RE";
ATTRIBUTE X_INTERFACE_INFO of OSIF_Hw2Sw_Data: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 OSIF_Hw2Sw FIFO_M_Data";
ATTRIBUTE X_INTERFACE_INFO of OSIF_Hw2Sw_Full: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 OSIF_Hw2Sw FIFO_M_Full";
ATTRIBUTE X_INTERFACE_INFO of OSIF_Hw2Sw_WE: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 OSIF_Hw2Sw FIFO_M_WE";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Hwt2Mem_Data: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 MEMIF_Hwt2Mem FIFO_M_Data";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Hwt2Mem_Full: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 MEMIF_Hwt2Mem FIFO_M_Full";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Hwt2Mem_WE: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 MEMIF_Hwt2Mem FIFO_M_WE";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Mem2Hwt_Data: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 MEMIF_Mem2Hwt FIFO_S_Data";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Mem2Hwt_Empty: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 MEMIF_Mem2Hwt FIFO_S_Empty";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Mem2Hwt_RE: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 MEMIF_Mem2Hwt FIFO_S_RE";
begin
OSIF_FIFO_Sw2Hw_RE <= '0';
OSIF_FIFO_Hw2Sw_WE <= '0';
OSIF_FIFO_Hw2Sw_Data <= (others => '0');
MEMIF_FIFO_Mem2Hwt_RE <= '0';
MEMIF_FIFO_Hwt2Mem_WE <= '0';
MEMIF_FIFO_Hwt2Mem_Data <= (others => '0');
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2996.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s05b00x00p02n01i02996pkg is
port (PT : BOOLEAN); -- Failure_here
-- ERROR: PORT DECLARATIONS ARE NOT ALLOWED IN PACKAGES
type INIT_2 is range 1 to 10;
end c02s05b00x00p02n01i02996pkg;
ENTITY c02s05b00x00p02n01i02996ent IS
END c02s05b00x00p02n01i02996ent;
ARCHITECTURE c02s05b00x00p02n01i02996arch OF c02s05b00x00p02n01i02996ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s05b00x00p02n01i02996 - Port declarations are not allowed in packages."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s05b00x00p02n01i02996arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2996.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s05b00x00p02n01i02996pkg is
port (PT : BOOLEAN); -- Failure_here
-- ERROR: PORT DECLARATIONS ARE NOT ALLOWED IN PACKAGES
type INIT_2 is range 1 to 10;
end c02s05b00x00p02n01i02996pkg;
ENTITY c02s05b00x00p02n01i02996ent IS
END c02s05b00x00p02n01i02996ent;
ARCHITECTURE c02s05b00x00p02n01i02996arch OF c02s05b00x00p02n01i02996ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s05b00x00p02n01i02996 - Port declarations are not allowed in packages."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s05b00x00p02n01i02996arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2996.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s05b00x00p02n01i02996pkg is
port (PT : BOOLEAN); -- Failure_here
-- ERROR: PORT DECLARATIONS ARE NOT ALLOWED IN PACKAGES
type INIT_2 is range 1 to 10;
end c02s05b00x00p02n01i02996pkg;
ENTITY c02s05b00x00p02n01i02996ent IS
END c02s05b00x00p02n01i02996ent;
ARCHITECTURE c02s05b00x00p02n01i02996arch OF c02s05b00x00p02n01i02996ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s05b00x00p02n01i02996 - Port declarations are not allowed in packages."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s05b00x00p02n01i02996arch;
|
--------------------------------------------------------------------------------
-- After input has been loaded, run calcs to fill up entire message digest
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sha1_pkg.all;
entity sha1_process_input is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in w_input;
load_i : in std_ulogic;
dat_w_o : out w_full;
valid_o : out std_ulogic
);
end sha1_process_input;
architecture RTL of sha1_process_input is
signal w: w_full;
signal w_con: w_full;
signal w_hold: w_input;
-- synthesis translate_off
signal test_word_1: std_ulogic_vector(0 to 31);
signal test_word_2: std_ulogic_vector(0 to 31);
signal test_word_3: std_ulogic_vector(0 to 31);
signal test_word_4: std_ulogic_vector(0 to 31);
signal test_word_5: std_ulogic_vector(0 to 31);
-- synthesis translate_on
signal i : integer range 0 to 79;
begin
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
i <= 0;
--Todo: decide if reset is even wanted
--for x in 0 to 15 loop
-- w_hold(x) <= "00000000000000000000000000000000";
--end loop;
else
if load_i = '1' then
--Alt: Type-casting instead of using loop
for x in 0 to 15 loop
w(x) <= w_hold(x);
end loop;
i <= 16; --i + 1;
valid_o <= '0';
elsif i < 16 then
i <= i + 1;
valid_o <= '0';
else
w(i) <= (w_con(i - 3)(1 to 31) & w_con(i - 3)(0)) XOR
(w_con(i - 8)(1 to 31) & w_con(i - 8)(0)) XOR
(w_con(i - 14)(1 to 31) & w_con(i - 14)(0)) XOR
(w_con(i - 16)(1 to 31) & w_con(i - 16)(0));
if i = 79 then
i <= 0;
--valid_o <= '1';
elsif i = 16 then
i <= i + 1;
valid_o <= '1';
else
i <= i + 1;
valid_o <= '0';
end if;
end if;
end if;
end if;
end process;
--Alt: merge functions of dat_w_o and w_con using inout port
dat_w_o <= w;
w_hold <= dat_i;
w_con <= w;
-- synthesis translate_off
test_word_1 <= w_con(16);
test_word_2 <= w_con(17);
test_word_3 <= w_con(18);
test_word_4 <= w_con(78);
test_word_5 <= w_con(79);
-- synthesis translate_on
end RTL; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc74.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p09n02i00074ent IS
END c04s03b01x02p09n02i00074ent;
ARCHITECTURE c04s03b01x02p09n02i00074arch OF c04s03b01x02p09n02i00074ent IS
signal s1 : bit bus; -- Failure_here
-- a guarded signal, but is not a resolved signal.
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x02p09n02i00074 - Guarded signal should be a resolved signal."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x02p09n02i00074arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc74.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p09n02i00074ent IS
END c04s03b01x02p09n02i00074ent;
ARCHITECTURE c04s03b01x02p09n02i00074arch OF c04s03b01x02p09n02i00074ent IS
signal s1 : bit bus; -- Failure_here
-- a guarded signal, but is not a resolved signal.
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x02p09n02i00074 - Guarded signal should be a resolved signal."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x02p09n02i00074arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc74.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p09n02i00074ent IS
END c04s03b01x02p09n02i00074ent;
ARCHITECTURE c04s03b01x02p09n02i00074arch OF c04s03b01x02p09n02i00074ent IS
signal s1 : bit bus; -- Failure_here
-- a guarded signal, but is not a resolved signal.
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x02p09n02i00074 - Guarded signal should be a resolved signal."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x02p09n02i00074arch;
|
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture ARCH00001_Test_Bench of ENT00001_Test_Bench is
type t_int1 is range 0 to 100 ;
subtype st_int1 is t_int1 range 8 to 60 ;
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr2_range1 is integer range 1 to 10 ;
subtype t_arr2_range2 is boolean range false to true ;
subtype t_arr1_range1 is integer range 1 to 10 ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
type t_rec1 is record
f1 : integer range 0 to 1000 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
subtype st_rec1 is t_rec1 ;
type t_rec2 is record
f1 : boolean;
f2 : st_rec1;
f3 : time ;
end record ;
subtype st_rec2 is t_rec2 ;
type t_rec3 is record
f1 : boolean;
f2 : st_rec2;
f3 : st_arr2;
end record ;
signal s1 : t_rec1;
begin
main: process
variable a : t_int1;
variable b : st_int1;
-- variable c : t_arr1;
variable d : t_arr2_range1;
variable e : t_arr2_range2;
variable r1 : t_rec1;
variable r2 : t_rec2;
variable r3 : t_rec3;
begin
report "Process in the architecture of the entity.";
wait;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity VGA3BitTestPattern is
port (
RstN : in bit1;
Clk : in bit1;
--
Button : in word(3-1 downto 0);
--
HSync : out bit1;
VSync : out bit1;
VgaRed : out word(3-1 downto 0);
VgaGreen : out word(3-1 downto 0);
VgaBlue : out word(3-1 downto 0)
);
end entity;
architecture rtl of VGA3BitTestPattern is
signal ButtonDB, Button_N, Button_D : word(Button'length-1 downto 0);
signal Blue_D, Red_D, Green_D : word(3-1 downto 0);
signal Blue_N, Red_N, Green_N : word(3-1 downto 0);
signal InView : bit1;
begin
Db0 : entity work.Debounce
port map (
Clk => Clk,
x => Button(0),
DBx => ButtonDB(0)
);
Db1 : entity work.Debounce
port map (
Clk => Clk,
x => Button(1),
DBx => ButtonDB(1)
);
Db2 : entity work.Debounce
port map (
Clk => Clk,
x => Button(2),
DBx => ButtonDB(2)
);
Sync : process (RstN, Clk)
begin
if RstN = '0' then
Button_D <= (others => '1');
Red_D <= (others => '0');
Blue_D <= (others => '0');
Green_D <= (others => '0');
elsif rising_edge(Clk) then
Button_D <= Button_N;
Red_D <= Red_N;
Green_D <= Green_N;
Blue_D <= Blue_N;
end if;
end process;
AsyncProc : process (Green_D, Blue_D, Red_D, Button_D, ButtonDB)
begin
Red_N <= Red_D;
Green_N <= Green_D;
Blue_N <= Blue_D;
Button_N <= ButtonDB;
if (ButtonDB(0) = '0' and Button_D(0) = '1') then
Red_N <= Red_D + 1;
end if;
if (ButtonDB(1) = '0' and Button_D(1) = '1') then
Blue_N <= Blue_D + 1;
end if;
if (ButtonDB(2) = '0' and Button_D(2) = '1') then
Green_N <= Green_D + 1;
end if;
end process;
VgaRed <= Red_D when inView = '1' else (others => '0');
VgaBlue <= Blue_D when inView = '1' else (others => '0');
VgaGreen <= Green_D when inView = '1' else (others => '0');
VgaGen : entity work.VGAGen
generic map (
ClkDiv => true
)
port map (
RstN => RstN,
Clk => Clk,
--
HSync => HSync,
VSync => VSync,
RedOut => open,
GreenOut => open,
BlueOut => open,
--
InView => InView
);
end architecture rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:09:59 09/30/2014
-- Design Name:
-- Module Name: ADCS7476_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADCS7476_ctrl is
generic(clk_period_ns : positive := 10;
sclk_period_ns : positive := 40;
time_between_sample_ns : positive :=20_833);
port(
clk, resetn : in std_logic;
sclk, ss : out std_logic ;
miso : in std_logic ;
sample_out : out std_logic_vector(11 downto 0);
sample_valid : out std_logic
);
end ADCS7476_ctrl;
architecture Behavioral of ADCS7476_ctrl is
constant divider_modulo : positive := ((sclk_period_ns/clk_period_ns)/2)-1 ;
constant tick_between_samples : positive := (time_between_sample_ns/sclk_period_ns);
type com_state is (WAIT_SAMPLE, ASSERT_SS, SCLK_LOW, SCLK_HIGH, DEASSERT_SS);
signal cur_state, next_state : com_state ;
signal bit_counter : std_logic_vector(15 downto 0);
signal bit_counter_en, bit_counter_reset : std_logic ;
signal clk_divider : std_logic_vector(15 downto 0);
signal end_divider : std_logic ;
signal shift_in : std_logic ;
signal data_reg : std_logic_vector(15 downto 0);
signal ss_comb, sclk_comb, miso_latched : std_logic ;
begin
process(clk, resetn)
begin
if resetn = '0' then
clk_divider <= std_logic_vector(to_unsigned(divider_modulo, 16));
elsif clk'event and clk = '1' then
if clk_divider = 0 then
clk_divider <= std_logic_vector(to_unsigned(divider_modulo, 16));
else
clk_divider <= clk_divider - 1 ;
end if ;
end if;
end process ;
end_divider <= '1' when clk_divider = 0 else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
bit_counter <= (others => '0');
elsif clk'event and clk = '1' then
if bit_counter_reset = '1' then
bit_counter <= (others => '0');
elsif bit_counter_en = '1' then
bit_counter <= bit_counter + 1;
end if ;
end if;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
cur_state <= WAIT_SAMPLE;
elsif clk'event and clk = '1' then
cur_state <= next_state;
end if ;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
data_reg <= (others => '0');
elsif clk'event and clk = '1' then
if shift_in = '1' then
data_reg(15 downto 1) <= data_reg(14 downto 0);
data_reg(0) <= miso_latched ;
end if ;
end if;
end process ;
process(cur_state, bit_counter, end_divider)
begin
next_state <= cur_state ;
case cur_state is
when WAIT_SAMPLE =>
if bit_counter = tick_between_samples and end_divider = '1' then
next_state <= ASSERT_SS ;
end if ;
when ASSERT_SS =>
if bit_counter = 1 and end_divider = '1' then
next_state <= SCLK_LOW ;
end if ;
when SCLK_LOW =>
if end_divider = '1' then
next_state <= SCLK_HIGH ;
end if ;
when SCLK_HIGH =>
if bit_counter = 15 and end_divider = '1' then
next_state <= DEASSERT_SS ;
elsif end_divider = '1' then
next_state <= SCLK_LOW ;
end if ;
when DEASSERT_SS =>
if bit_counter = 1 and end_divider = '1' then
next_state <= WAIT_SAMPLE ;
end if ;
when others => next_state <= WAIT_SAMPLE ;
end case;
end process ;
with cur_state select
bit_counter_en <= end_divider when SCLK_HIGH,
'0' when SCLK_LOW,
end_divider when others ;
bit_counter_reset <= '1' when cur_state = ASSERT_SS and next_state = SCLK_LOW else
'1' when cur_state = WAIT_SAMPLE and next_state = ASSERT_SS else
'1' when cur_state = SCLK_HIGH and next_state = DEASSERT_SS else
'1' when cur_state = DEASSERT_SS and next_state = WAIT_SAMPLE else
'0';
shift_in <= '1' when cur_state = SCLK_LOW and next_state = SCLK_HIGH else
'0' ;
sample_valid <= '1' when cur_state = SCLK_HIGH and next_state = DEASSERT_SS else
'0' ;
sample_out <= data_reg(12 downto 1);
ss_comb <= '1' when cur_state = WAIT_SAMPLE else
'1' when cur_state = DEASSERT_SS else
'0' ;
with cur_state select
sclk_comb <= '0' when SCLK_LOW,
'1' when others ;
process(clk, resetn)
begin
if resetn = '0' then
ss <= '1' ;
sclk <= '1' ;
miso_latched <= '0' ;
elsif clk'event and clk = '1' then
ss <= ss_comb;
sclk <= sclk_comb ;
miso_latched <= miso ;
end if;
end process ;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:09:59 09/30/2014
-- Design Name:
-- Module Name: ADCS7476_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADCS7476_ctrl is
generic(clk_period_ns : positive := 10;
sclk_period_ns : positive := 40;
time_between_sample_ns : positive :=20_833);
port(
clk, resetn : in std_logic;
sclk, ss : out std_logic ;
miso : in std_logic ;
sample_out : out std_logic_vector(11 downto 0);
sample_valid : out std_logic
);
end ADCS7476_ctrl;
architecture Behavioral of ADCS7476_ctrl is
constant divider_modulo : positive := ((sclk_period_ns/clk_period_ns)/2)-1 ;
constant tick_between_samples : positive := (time_between_sample_ns/sclk_period_ns);
type com_state is (WAIT_SAMPLE, ASSERT_SS, SCLK_LOW, SCLK_HIGH, DEASSERT_SS);
signal cur_state, next_state : com_state ;
signal bit_counter : std_logic_vector(15 downto 0);
signal bit_counter_en, bit_counter_reset : std_logic ;
signal clk_divider : std_logic_vector(15 downto 0);
signal end_divider : std_logic ;
signal shift_in : std_logic ;
signal data_reg : std_logic_vector(15 downto 0);
signal ss_comb, sclk_comb, miso_latched : std_logic ;
begin
process(clk, resetn)
begin
if resetn = '0' then
clk_divider <= std_logic_vector(to_unsigned(divider_modulo, 16));
elsif clk'event and clk = '1' then
if clk_divider = 0 then
clk_divider <= std_logic_vector(to_unsigned(divider_modulo, 16));
else
clk_divider <= clk_divider - 1 ;
end if ;
end if;
end process ;
end_divider <= '1' when clk_divider = 0 else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
bit_counter <= (others => '0');
elsif clk'event and clk = '1' then
if bit_counter_reset = '1' then
bit_counter <= (others => '0');
elsif bit_counter_en = '1' then
bit_counter <= bit_counter + 1;
end if ;
end if;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
cur_state <= WAIT_SAMPLE;
elsif clk'event and clk = '1' then
cur_state <= next_state;
end if ;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
data_reg <= (others => '0');
elsif clk'event and clk = '1' then
if shift_in = '1' then
data_reg(15 downto 1) <= data_reg(14 downto 0);
data_reg(0) <= miso_latched ;
end if ;
end if;
end process ;
process(cur_state, bit_counter, end_divider)
begin
next_state <= cur_state ;
case cur_state is
when WAIT_SAMPLE =>
if bit_counter = tick_between_samples and end_divider = '1' then
next_state <= ASSERT_SS ;
end if ;
when ASSERT_SS =>
if bit_counter = 1 and end_divider = '1' then
next_state <= SCLK_LOW ;
end if ;
when SCLK_LOW =>
if end_divider = '1' then
next_state <= SCLK_HIGH ;
end if ;
when SCLK_HIGH =>
if bit_counter = 15 and end_divider = '1' then
next_state <= DEASSERT_SS ;
elsif end_divider = '1' then
next_state <= SCLK_LOW ;
end if ;
when DEASSERT_SS =>
if bit_counter = 1 and end_divider = '1' then
next_state <= WAIT_SAMPLE ;
end if ;
when others => next_state <= WAIT_SAMPLE ;
end case;
end process ;
with cur_state select
bit_counter_en <= end_divider when SCLK_HIGH,
'0' when SCLK_LOW,
end_divider when others ;
bit_counter_reset <= '1' when cur_state = ASSERT_SS and next_state = SCLK_LOW else
'1' when cur_state = WAIT_SAMPLE and next_state = ASSERT_SS else
'1' when cur_state = SCLK_HIGH and next_state = DEASSERT_SS else
'1' when cur_state = DEASSERT_SS and next_state = WAIT_SAMPLE else
'0';
shift_in <= '1' when cur_state = SCLK_LOW and next_state = SCLK_HIGH else
'0' ;
sample_valid <= '1' when cur_state = SCLK_HIGH and next_state = DEASSERT_SS else
'0' ;
sample_out <= data_reg(12 downto 1);
ss_comb <= '1' when cur_state = WAIT_SAMPLE else
'1' when cur_state = DEASSERT_SS else
'0' ;
with cur_state select
sclk_comb <= '0' when SCLK_LOW,
'1' when others ;
process(clk, resetn)
begin
if resetn = '0' then
ss <= '1' ;
sclk <= '1' ;
miso_latched <= '0' ;
elsif clk'event and clk = '1' then
ss <= ss_comb;
sclk <= sclk_comb ;
miso_latched <= miso ;
end if;
end process ;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU_Toplevel is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG : out STD_LOGIC_VECTOR (3 downto 0);
LDST_DAT : out STD_LOGIC_VECTOR (15 downto 0);
LDST_ADR : out STD_LOGIC_VECTOR (15 downto 0));
end ALU_Toplevel;
architecture Structural of ALU_Toplevel is
signal ARITH : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_AR : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LOGIC : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_LG : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal SHIFT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_SH : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LD_MEM : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
begin
arith_unit: entity work.arith_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
AR_OUT => ARITH);
logical_unit: entity work.logical_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
LOG_OUT => LOGIC,
SREG_OUT => SREG_LG);
shift_unit: entity work.shift_unit
port map( RA => RA,
SHIFT => RB(7 downto 0),
OP => OP(3),
SHIFT_OUT => SHIFT,
SREG_OUT => SREG_SH);
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD (ARITHMETIC)
ARITH when "0001", -- SUB (ARITHMETIC)
LOGIC when "0010", -- AND (LOGICAL)
LOGIC when "0011", -- OR (LOGICAL)
LOGIC when "0100", -- MOV (LOGICAL)
ARITH when "0101", -- ADDI (ARITHMETIC)
LOGIC when "0110",--, -- ANDI (LOGICAL)
SHIFT when "0111", -- SL (SHIFT)
SHIFT when "1000",--, -- SR (SHIFT)
--"" when "1001", -- LW (WORD)
--"" when "1010"; -- SW (WORD)
RA when OTHERS;
end Structural;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_16 is
end entity ch_05_16;
----------------------------------------------------------------
architecture test of ch_05_16 is
constant Tpd_01 : time := 800 ps;
constant Tpd_10 : time := 500 ps;
signal a, z : bit;
begin
-- code from book:
asym_delay : z <= transport a after Tpd_01 when a = '1' else
a after Tpd_10;
-- end of code from book
----------------
stimulus : process is
begin
a <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_16 is
end entity ch_05_16;
----------------------------------------------------------------
architecture test of ch_05_16 is
constant Tpd_01 : time := 800 ps;
constant Tpd_10 : time := 500 ps;
signal a, z : bit;
begin
-- code from book:
asym_delay : z <= transport a after Tpd_01 when a = '1' else
a after Tpd_10;
-- end of code from book
----------------
stimulus : process is
begin
a <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_16 is
end entity ch_05_16;
----------------------------------------------------------------
architecture test of ch_05_16 is
constant Tpd_01 : time := 800 ps;
constant Tpd_10 : time := 500 ps;
signal a, z : bit;
begin
-- code from book:
asym_delay : z <= transport a after Tpd_01 when a = '1' else
a after Tpd_10;
-- end of code from book
----------------
stimulus : process is
begin
a <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps;
wait;
end process stimulus;
end architecture test;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:52:04 05/20/2016
-- Design Name:
-- Module Name: ADDR_calculator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.CONSTANTS.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADDR_calculator is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_write : in STD_LOGIC;
endcalcul : in STD_LOGIC;
ADDRout : out STD_LOGIC_VECTOR (ADDR_BIT_MUX-1 downto 0));
end ADDR_calculator;
architecture Behavioral of ADDR_calculator is
Signal ADDR : unsigned(ADDR_BIT_MUX-1 downto 0);
begin
ADDRmanagement : process(clk,reset, data_write, endcalcul)
begin
if reset='1' then
ADDR<=(others=>'0'); --to_unsigned(15999, 14);
elsif rising_edge(clk) then
if endcalcul='1' then
ADDR<=(others=>'0');
else
if data_write = '1' then
if ADDR = NBR_PIXEL then
ADDR<=(others=>'0');
else
ADDR<=ADDR+1;
end if;
end if;
end if;
end if;
end process;
ADDRout<=std_logic_vector(ADDR);
end Behavioral;
|
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_IO_STBX : in std_logic;
MCU_LCD_WRX : in std_logic;
MCU_ADDR : in std_logic;
MCU_LCD_TE : out std_logic;
MCU_P2_8 : in std_logic;
MCU_LCD_RDX : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(15 downto 0);
LCD_TE : in std_logic;
LCD_BACKLIGHT : out std_logic
);
end top;
architecture rtl of top is
signal switches : std_logic_vector(7 downto 0);
type data_direction_t is (from_mcu, to_mcu);
signal data_dir : data_direction_t;
signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
signal mcu_data_out_io : std_logic_vector(7 downto 0);
signal mcu_data_out : std_logic_vector(7 downto 0);
signal mcu_data_in : std_logic_vector(7 downto 0);
signal lcd_data_in : std_logic_vector(15 downto 0);
signal lcd_data_in_mux : std_logic_vector(7 downto 0);
signal lcd_data_out : std_logic_vector(15 downto 0);
signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_reset_q : std_logic := '1';
signal lcd_backlight_q : std_logic := '0';
signal dir_read : boolean;
signal dir_write : boolean;
signal lcd_read_strobe : boolean;
signal lcd_write_strobe : boolean;
signal lcd_write : boolean;
signal io_strobe : boolean;
signal io_read_strobe : boolean;
signal io_write_strobe : boolean;
begin
-- I/O data
switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
LCD_BACKLIGHT <= lcd_backlight_q;
MCU_LCD_TE <= LCD_TE;
-- State management
data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
dir_read <= (data_dir = to_mcu);
dir_write <= (data_dir = from_mcu);
io_strobe <= (MCU_IO_STBX = '0');
io_read_strobe <= io_strobe and dir_read;
lcd_read_strobe <= (MCU_LCD_RDX = '0');
lcd_write <= not lcd_read_strobe;
-- LCD interface
LCD_RS <= MCU_ADDR;
LCD_RDX <= MCU_LCD_RDX;
LCD_WRX <= MCU_LCD_WRX;
lcd_data_out <= lcd_data_out_q & mcu_data_in;
lcd_data_in <= LCD_DB;
LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
LCD_RESETX <= not lcd_reset_q;
-- MCU interface
mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
mcu_data_out_io <= switches;
mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
mcu_data_in <= MCU_D;
MCU_D <= mcu_data_out when dir_read else (others => 'Z');
-- Synchronous behaviors:
-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
process(MCU_LCD_WRX, mcu_data_in)
begin
if falling_edge(MCU_LCD_WRX) then
lcd_data_out_q <= mcu_data_in;
end if;
end process;
-- LCD read: Capture LCD low byte on LCD_RD falling edge.
process(MCU_LCD_RDX, lcd_data_in)
begin
if rising_edge(MCU_LCD_RDX) then
lcd_data_in_q <= lcd_data_in(7 downto 0);
end if;
end process;
-- I/O write (to resistive touch panel): Capture data from
-- MCU and hold on TP pins until further notice.
process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
begin
if rising_edge(MCU_IO_STBX) and dir_write then
if MCU_ADDR = '0' then
tp_q <= mcu_data_in;
else
lcd_reset_q <= mcu_data_in(0);
lcd_backlight_q <= mcu_data_in(7);
end if;
end if;
end process;
end rtl;
|
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_IO_STBX : in std_logic;
MCU_LCD_WRX : in std_logic;
MCU_ADDR : in std_logic;
MCU_LCD_TE : out std_logic;
MCU_P2_8 : in std_logic;
MCU_LCD_RDX : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(15 downto 0);
LCD_TE : in std_logic;
LCD_BACKLIGHT : out std_logic
);
end top;
architecture rtl of top is
signal switches : std_logic_vector(7 downto 0);
type data_direction_t is (from_mcu, to_mcu);
signal data_dir : data_direction_t;
signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
signal mcu_data_out_io : std_logic_vector(7 downto 0);
signal mcu_data_out : std_logic_vector(7 downto 0);
signal mcu_data_in : std_logic_vector(7 downto 0);
signal lcd_data_in : std_logic_vector(15 downto 0);
signal lcd_data_in_mux : std_logic_vector(7 downto 0);
signal lcd_data_out : std_logic_vector(15 downto 0);
signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_reset_q : std_logic := '1';
signal lcd_backlight_q : std_logic := '0';
signal dir_read : boolean;
signal dir_write : boolean;
signal lcd_read_strobe : boolean;
signal lcd_write_strobe : boolean;
signal lcd_write : boolean;
signal io_strobe : boolean;
signal io_read_strobe : boolean;
signal io_write_strobe : boolean;
begin
-- I/O data
switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
LCD_BACKLIGHT <= lcd_backlight_q;
MCU_LCD_TE <= LCD_TE;
-- State management
data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
dir_read <= (data_dir = to_mcu);
dir_write <= (data_dir = from_mcu);
io_strobe <= (MCU_IO_STBX = '0');
io_read_strobe <= io_strobe and dir_read;
lcd_read_strobe <= (MCU_LCD_RDX = '0');
lcd_write <= not lcd_read_strobe;
-- LCD interface
LCD_RS <= MCU_ADDR;
LCD_RDX <= MCU_LCD_RDX;
LCD_WRX <= MCU_LCD_WRX;
lcd_data_out <= lcd_data_out_q & mcu_data_in;
lcd_data_in <= LCD_DB;
LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
LCD_RESETX <= not lcd_reset_q;
-- MCU interface
mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
mcu_data_out_io <= switches;
mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
mcu_data_in <= MCU_D;
MCU_D <= mcu_data_out when dir_read else (others => 'Z');
-- Synchronous behaviors:
-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
process(MCU_LCD_WRX, mcu_data_in)
begin
if falling_edge(MCU_LCD_WRX) then
lcd_data_out_q <= mcu_data_in;
end if;
end process;
-- LCD read: Capture LCD low byte on LCD_RD falling edge.
process(MCU_LCD_RDX, lcd_data_in)
begin
if rising_edge(MCU_LCD_RDX) then
lcd_data_in_q <= lcd_data_in(7 downto 0);
end if;
end process;
-- I/O write (to resistive touch panel): Capture data from
-- MCU and hold on TP pins until further notice.
process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
begin
if rising_edge(MCU_IO_STBX) and dir_write then
if MCU_ADDR = '0' then
tp_q <= mcu_data_in;
else
lcd_reset_q <= mcu_data_in(0);
lcd_backlight_q <= mcu_data_in(7);
end if;
end if;
end process;
end rtl;
|
-- NEED RESULT: ARCH00412.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00412: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00412: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00412: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00412: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00412
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00412(ARCH00412)
-- ENT00412_Test_Bench(ARCH00412_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00412 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00412 ;
--
--
architecture ARCH00412 of ENT00412 is
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec3_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_2.f3(lowb,true) after 10 ns,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00412.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_1.f3(lowb,true) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00412" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_1.f3(lowb,true) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00412" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00412" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00412" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00412" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3.f3(lowb,true)'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec3.f3(lowb,true) <=
c_st_rec3_2.f3(lowb,true) after 10 ns,
c_st_rec3_1.f3(lowb,true) after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1.f3(lowb,true) after 5 ns
when st_rec3_select = 3 else
--
c_st_rec3_1.f3(lowb,true) after 100 ns
when st_rec3_select = 4 else
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when st_rec3_select = 5 else
--
-- Last transaction above is marked
c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
end ARCH00412 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00412_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00412_Test_Bench ;
--
--
architecture ARCH00412_Test_Bench of ENT00412_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00412 ( ARCH00412 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00412_Test_Bench ;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for 'range, 'left and 'right attributes in VHDL subprograms.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package range_func_pkg is
function negator (word_i : std_logic_vector(3 downto 0)) return std_logic_vector;
function reverse (word_i : std_logic_vector(3 downto 0)) return std_logic_vector;
end range_func_pkg;
package body range_func_pkg is
function negator (word_i : std_logic_vector(3 downto 0)) return std_logic_vector is
variable neg : std_logic_vector(word_i'left downto word_i'right);
begin
for I in word_i'range loop
neg (I) := not word_i(I);
end loop;
return neg;
end function;
function reverse (word_i : std_logic_vector(3 downto 0)) return std_logic_vector is
variable rev : std_logic_vector(3 downto 0);
begin
for I in word_i'right to word_i'left loop
rev (rev'left - I) := word_i(I);
end loop;
return rev;
end function;
end range_func_pkg;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for 'range, 'left and 'right attributes in VHDL subprograms.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package range_func_pkg is
function negator (word_i : std_logic_vector(3 downto 0)) return std_logic_vector;
function reverse (word_i : std_logic_vector(3 downto 0)) return std_logic_vector;
end range_func_pkg;
package body range_func_pkg is
function negator (word_i : std_logic_vector(3 downto 0)) return std_logic_vector is
variable neg : std_logic_vector(word_i'left downto word_i'right);
begin
for I in word_i'range loop
neg (I) := not word_i(I);
end loop;
return neg;
end function;
function reverse (word_i : std_logic_vector(3 downto 0)) return std_logic_vector is
variable rev : std_logic_vector(3 downto 0);
begin
for I in word_i'right to word_i'left loop
rev (rev'left - I) := word_i(I);
end loop;
return rev;
end function;
end range_func_pkg;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for 'range, 'left and 'right attributes in VHDL subprograms.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package range_func_pkg is
function negator (word_i : std_logic_vector(3 downto 0)) return std_logic_vector;
function reverse (word_i : std_logic_vector(3 downto 0)) return std_logic_vector;
end range_func_pkg;
package body range_func_pkg is
function negator (word_i : std_logic_vector(3 downto 0)) return std_logic_vector is
variable neg : std_logic_vector(word_i'left downto word_i'right);
begin
for I in word_i'range loop
neg (I) := not word_i(I);
end loop;
return neg;
end function;
function reverse (word_i : std_logic_vector(3 downto 0)) return std_logic_vector is
variable rev : std_logic_vector(3 downto 0);
begin
for I in word_i'right to word_i'left loop
rev (rev'left - I) := word_i(I);
end loop;
return rev;
end function;
end range_func_pkg;
|
-- (c) EMARD
-- LICENSE=BSD
-- generic (vendor-agnostic) serializer
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY serializer_generic IS
GENERIC
(
C_channel_bits: integer := 10; -- number of bits per channel
C_output_bits: integer := 1; -- output bits per channel
C_channels: integer := 3 -- number of channels to serialize
);
PORT
(
tx_in : IN STD_LOGIC_VECTOR(C_channel_bits*C_channels-1 DOWNTO 0);
tx_inclock : IN STD_LOGIC; -- 10x tx_syncclock
tx_syncclock : IN STD_LOGIC;
tx_out : OUT STD_LOGIC_VECTOR((C_channels+1)*C_output_bits-1 DOWNTO 0) -- one more channel for clock
);
END;
ARCHITECTURE SYN OF serializer_generic IS
signal R_tx_latch: std_logic_vector(C_channel_bits*C_channels-1 downto 0);
signal S_tx_clock: std_logic_vector(C_channel_bits-1 downto 0);
type T_channel_shift is array(0 to C_channels) of std_logic_vector(C_channel_bits-1 downto 0); -- -- one channel more for clock
signal S_channel_latch, R_channel_shift: T_channel_shift;
signal R_pixel_clock_toggle, R_prev_pixel_clock_toggle: std_logic;
signal R_clock_edge: std_logic;
constant C_shift_pad: std_logic_vector(C_output_bits-1 downto 0) := (others => '0');
BEGIN
process(tx_syncclock) -- pixel clock
begin
if rising_edge(tx_syncclock) then
R_tx_latch <= tx_in; -- add the clock to be shifted to the channels
end if;
end process;
-- rename - separate to shifted 4 channels
separate_channels:
for i in 0 to C_channels-1 generate
reverse_bits:
for j in 0 to C_channel_bits-1 generate
S_channel_latch(i)(j) <= R_tx_latch(C_channel_bits*(i+1)-j-1);
end generate;
end generate;
S_channel_latch(3) <= "1111100000"; -- the clock pattern
process(tx_syncclock)
begin
if rising_edge(tx_syncclock) then
R_pixel_clock_toggle <= not R_pixel_clock_toggle;
end if;
end process;
-- shift-synchronous pixel clock edge detection
process(tx_inclock) -- pixel shift clock (250 MHz)
begin
if rising_edge(tx_inclock) then -- pixel clock (25 MHz)
R_prev_pixel_clock_toggle <= R_pixel_clock_toggle;
R_clock_edge <= R_pixel_clock_toggle xor R_prev_pixel_clock_toggle;
end if;
end process;
-- fixme: initial state issue (clock shifting?)
process(tx_inclock) -- pixel shift clock
begin
if rising_edge(tx_inclock) then
if R_clock_edge='1' then -- rising edge detection
R_channel_shift(0) <= S_channel_latch(0);
R_channel_shift(1) <= S_channel_latch(1);
R_channel_shift(2) <= S_channel_latch(2);
R_channel_shift(3) <= S_channel_latch(3);
else
R_channel_shift(0) <= C_shift_pad & R_channel_shift(0)(C_channel_bits-1 downto C_output_bits);
R_channel_shift(1) <= C_shift_pad & R_channel_shift(1)(C_channel_bits-1 downto C_output_bits);
R_channel_shift(2) <= C_shift_pad & R_channel_shift(2)(C_channel_bits-1 downto C_output_bits);
R_channel_shift(3) <= C_shift_pad & R_channel_shift(3)(C_channel_bits-1 downto C_output_bits);
end if;
end if;
end process;
tx_out <= R_channel_shift(3)(C_output_bits-1 downto 0)
& R_channel_shift(2)(C_output_bits-1 downto 0)
& R_channel_shift(1)(C_output_bits-1 downto 0)
& R_channel_shift(0)(C_output_bits-1 downto 0);
END SYN;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1276.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01276ent IS
END c08s04b00x00p04n01i01276ent;
ARCHITECTURE c08s04b00x00p04n01i01276arch OF c08s04b00x00p04n01i01276ent IS
signal S1,S2,S3 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
S1 and S2 <= S3;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01276 - Logical expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01276arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1276.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01276ent IS
END c08s04b00x00p04n01i01276ent;
ARCHITECTURE c08s04b00x00p04n01i01276arch OF c08s04b00x00p04n01i01276ent IS
signal S1,S2,S3 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
S1 and S2 <= S3;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01276 - Logical expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01276arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1276.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01276ent IS
END c08s04b00x00p04n01i01276ent;
ARCHITECTURE c08s04b00x00p04n01i01276arch OF c08s04b00x00p04n01i01276ent IS
signal S1,S2,S3 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
S1 and S2 <= S3;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01276 - Logical expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01276arch;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 16-03-2017
-- Module Name: memory.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity memory is
generic (blocksize : integer := 1024);
port (clk, readmem, writemem : in std_logic;
addressbus: in std_logic_vector (15 downto 0);
databus : inout std_logic_vector (15 downto 0);
memdataready : out std_logic);
end entity memory;
architecture behavioral of memory is
type mem is array (0 to blocksize - 1) of std_logic_vector (15 downto 0);
begin
process (clk)
variable buffermem : mem := (others => (others => '0'));
variable ad : integer;
variable init : boolean := true;
begin
if init = true then
-- some initiation
buffermem(0) := "0000000000000000";
init := false;
end if;
memdataready <= '0';
if clk'event and clk = '1' then
ad := to_integer(unsigned(addressbus));
if readmem = '1' then -- Readiing :)
memdataready <= '1';
if ad >= blocksize then
databus <= (others => 'Z');
else
databus <= buffermem(ad);
end if;
elsif writemem = '1' then -- Writing :)
memdataready <= '1';
if ad < blocksize then
buffermem(ad) := databus;
end if;
elsif readmem = '0' then
databus <= (others => 'Z');
end if;
end if;
end process;
end architecture behavioral;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 97
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
-- system_xadc_wiz_0_0_xadc_core_drp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010, 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
-------------------------------------------------------------------------------
-- File : system_xadc_wiz_0_0_xadc_core_drp.vhd
-- Version : v1.00.a
-- Description : XADC for AXI bus on new FPGA devices.
-- This file containts actual interface between the core
-- and XADC hard macro.
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_xadc.vhd
-- -system_xadc_wiz_0_0_xadc_core_drp.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_arith.unsigned;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.or_reduce;
use IEEE.numeric_std.all;
library work;
use work.system_xadc_wiz_0_0_ipif_pkg.all;
use work.system_xadc_wiz_0_0_proc_common_pkg.all;
Library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- un-comment below line if testing locally with BLH or UNISIM model
--use unisim.XADC;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- AXI4 Slave Single block generics
-------------------------------------------------------------------------------
-- C_S_AXI_ADDR_WIDTH -- AXI4 address bus width
-- C_S_AXI_DATA_WIDTH -- AXI4 Slave bus width
--
-------------------------------------------------------------------------------
-- XADC Specific Generics
-------------------------------------------------------------------------------
-- C_SIM_MONITOR_FILE -- stimuli file
-- CE_NUMBERS -- read/write chip enble no.
-- IP_INTR_NUM -- interrupt signals no.
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- AXI Slave Interface -- INPUT/OUTPUT Signals
-------------------------------------------------------------------------------
-- Bus2IP_Clk -- bus clock
-- Bus2IP_Rst -- bus reset
-- -- Bus 2 IP IPIC interface
-- Bus2IP_RdCE -- bus read chip enable signals
-- Bus2IP_WrCE -- bus write chip enable signals
-- Bus2IP_Addr -- bus address bits
-- Bus2IP_Data -- bus to ip data
-- -- IP 2 Bus IPIC interface
-- Sysmon_IP2Bus_Data -- data from sysmon
-- Sysmon_IP2Bus_WrAck -- write ack from sysmon
-- Sysmon_IP2Bus_RdAck -- read ack from sysmon
-------------------------------------------------------------------------------
-- XADC EXTERNAL INTERFACE -- INPUT Signals
-------------------------------------------------------------------------------
-- VAUXN -- user selectable differential inputs
-- VAUXP -- user selectable differential inputs
-- CONVST -- Conversion start signal for event-driven
-- sampling mode
-------------------------------------------------------------------------------
-- XADC Interrupt -- OUTPUT Signal to Interrupt Module
-------------------------------------------------------------------------------
-- Interrupt_status -- interrupt from the sysmon core
-- ALARM -- XADC alarm output signals of the hard macro
-------------------------------------------------------------------------------
entity system_xadc_wiz_0_0_xadc_core_drp is
generic
(
----------------
C_S_AXI_ADDR_WIDTH : integer;
C_S_AXI_DATA_WIDTH : integer;
C_FAMILY : string;
----------------
CE_NUMBERS : integer;
IP_INTR_NUM : integer;
C_SIM_MONITOR_FILE : string ;
----------------
MUX_ADDR_NO : integer
);
port
(
-- IP Interconnect (IPIC) port signals ---------
Bus2IP_Clk : in std_logic;
Bus2IP_Rst : in std_logic;
-- Bus 2 IP IPIC interface
Bus2IP_RdCE : in std_logic_vector(0 to CE_NUMBERS-1);
Bus2IP_WrCE : in std_logic_vector(0 to CE_NUMBERS-1);
Bus2IP_Addr : in std_logic_vector(0 to (C_S_AXI_ADDR_WIDTH-1));
Bus2IP_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- IP 2 Bus IPIC interface
Sysmon_IP2Bus_Data : out std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
Sysmon_IP2Bus_WrAck : out std_logic;
Sysmon_IP2Bus_RdAck : out std_logic;
---------------- interrupt interface with the system -----------
Interrupt_status : out std_logic_vector(0 to IP_INTR_NUM-1);
---------------- sysmon macro interface -------------------
vauxp0 : in STD_LOGIC; -- Auxiliary Channel 0
vauxn0 : in STD_LOGIC;
vauxp1 : in STD_LOGIC; -- Auxiliary Channel 1
vauxn1 : in STD_LOGIC;
vauxp2 : in STD_LOGIC; -- Auxiliary Channel 2
vauxn2 : in STD_LOGIC;
vauxp4 : in STD_LOGIC; -- Auxiliary Channel 4
vauxn4 : in STD_LOGIC;
vauxp5 : in STD_LOGIC; -- Auxiliary Channel 5
vauxn5 : in STD_LOGIC;
vauxp6 : in STD_LOGIC; -- Auxiliary Channel 6
vauxn6 : in STD_LOGIC;
vauxp7 : in STD_LOGIC; -- Auxiliary Channel 7
vauxn7 : in STD_LOGIC;
vauxp9 : in STD_LOGIC; -- Auxiliary Channel 9
vauxn9 : in STD_LOGIC;
vauxp10 : in STD_LOGIC; -- Auxiliary Channel 10
vauxn10 : in STD_LOGIC;
vauxp12 : in STD_LOGIC; -- Auxiliary Channel 12
vauxn12 : in STD_LOGIC;
vauxp13 : in STD_LOGIC; -- Auxiliary Channel 13
vauxn13 : in STD_LOGIC;
vauxp14 : in STD_LOGIC; -- Auxiliary Channel 14
vauxn14 : in STD_LOGIC;
vauxp15 : in STD_LOGIC; -- Auxiliary Channel 15
vauxn15 : in STD_LOGIC;
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
alarm_out : out STD_LOGIC_VECTOR (7 downto 0);
temp_out : out std_logic_vector(11 downto 0);
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
end entity system_xadc_wiz_0_0_xadc_core_drp;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of system_xadc_wiz_0_0_xadc_core_drp is
component temperature_update
port (
reset : in std_logic;
clk : in std_logic;
temp_bus_update : in std_logic;
wait_cycle : in std_logic_vector(15 downto 0);
temp_out : out std_logic_vector(11 downto 0);
-- DRP signals for Arbiter
daddr_o : out std_logic_vector(7 downto 0);
den_o : out std_logic;
di_o : out std_logic_vector(15 downto 0);
dwe_o : out std_logic;
do_i : in std_logic_vector(15 downto 0);
drdy_i : in std_logic;
busy_o : out std_logic
);
end component;
component drp_arbiter
port (
reset : in std_logic;
clk : in std_logic; -- input clock
jtaglocked: in std_logic; -- input clock
bgrant_A : out std_logic; -- bus grant
bgrant_B : out std_logic; -- bus grant
bbusy_A : in std_logic; -- bus busy
bbusy_B : in std_logic := '0'; -- bus busy
daddr_A : in std_logic_vector(7 downto 0);
den_A : in std_logic;
di_A : in std_logic_vector(15 downto 0);
dwe_A : in std_logic;
do_A : out std_logic_vector(15 downto 0);
drdy_A : out std_logic;
daddr_B : in std_logic_vector(7 downto 0);
den_B : in std_logic;
di_B : in std_logic_vector(15 downto 0);
dwe_B : in std_logic;
do_B : out std_logic_vector(15 downto 0);
drdy_B : out std_logic;
daddr_C : out std_logic_vector(7 downto 0);
den_C : out std_logic;
di_C : out std_logic_vector(15 downto 0);
dwe_C : out std_logic;
do_C : in std_logic_vector(15 downto 0);
drdy_C : in std_logic
);
end component;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant DATA_SIZE_DRP : integer := 16;
constant ADDR_SIZE_DRP : integer := 7;
constant CHANNEL_NO : integer := 5;
constant ALARM_NO : integer := 8; -- updated from 3 to 8 for XADC
constant ALARM_REG_LENGTH : integer := 9;-- internal constant-- updated from 4 to 9 for XADC
constant STATUS_REG_LENGTH : integer := 11;--internal constant
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal daddr_i : std_logic_vector(ADDR_SIZE_DRP-1 downto 0);
signal alm_i : std_logic_vector(ALARM_NO-1 downto 0);
signal channel_i : std_logic_vector(CHANNEL_NO-1 downto 0);
signal mux_addr_no_i : std_logic_vector(MUX_ADDR_NO-1 downto 0);-- added for XADC
signal do_i : std_logic_vector(DATA_SIZE_DRP-1 downto 0);
signal di_i : std_logic_vector(DATA_SIZE_DRP-1 downto 0);
signal den_i : std_logic;
signal dwe_i : std_logic;
signal busy_i : std_logic;
signal drdy_i : std_logic;
signal eoc_i : std_logic;
signal eos_i : std_logic;
signal ot_i : std_logic;
signal daddr_C : std_logic_vector(7 downto 0);
signal den_C : std_logic;
signal di_C : std_logic_vector(15 downto 0);
signal dwe_C : std_logic;
signal do_C : std_logic_vector(15 downto 0);
signal drdy_C : std_logic;
signal bgrant_B : std_logic;
signal daddr_i_int : std_logic_vector(ADDR_SIZE_DRP downto 0);
signal temp_bus_update: std_logic := '0';
signal temp_rd_wait_cycle_reg : std_logic_vector(15 downto 0) := X"03E8";
-- JTAG related signals
signal jtaglocked_i : std_logic;
signal jtagbusy_i : std_logic;
signal jtagmodified_i : std_logic;
signal jtagmodified_d1 : std_logic;
signal jtag_modified_info: std_logic;
-------------------------------------------------------------------------------
-- Following signals are used as internal signals
signal do_reg : std_logic_vector(DATA_SIZE_DRP-1 downto 0);
signal alarm_reg : std_logic_vector(ALARM_REG_LENGTH-1 downto 0);
signal status_reg : std_logic_vector(STATUS_REG_LENGTH-1 downto 0);
-------------------------------------------------------------------------------
signal convst_rst_wrce_or_reduce : std_logic;
signal local_rdce_or_reduce : std_logic;
signal register_rdce_select : std_logic_vector(0 to 2);
signal convst_reset_wrce_select : std_logic_vector(0 to 1);
-------------------------------------------------------------------------------
signal eoc_d1 : std_logic;
signal eos_d1 : std_logic;
signal eoc_info : std_logic;
signal eos_info : std_logic;
-------------------------------------------------------------------------------
signal convst_reg : std_logic := '0';
signal hard_macro_rst_reg : std_logic;
signal sysmon_hard_block_reset : std_logic;
-------------------------------------------------------------------------------
signal local_reg_rdack_final : std_logic;
signal status_reg_rdack : std_logic;
signal status_reg_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
signal local_reg_wrack : std_logic;
signal local_reg_wrack_d1 : std_logic;
signal local_reg_rdack : std_logic;
signal local_reg_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
signal sysmon_IP2Bus_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-------------------------------------------------------------------------------
signal drdy_rd_ack_i : std_logic;
signal drdy_wr_ack_i : std_logic;
signal drdy_rd_ack_i_d1 : std_logic;
signal drdy_rd_ack_i_d2 : std_logic;
signal drdy_wr_ack_i_d1 : std_logic;
signal drdy_wr_ack_i_d2 : std_logic;
signal convst_d1 : std_logic;
-------------------------------------------------------------------------------
signal convst_reg_input : std_logic;
signal den_d1 : std_logic;
signal den_actual : std_logic;
signal dwe_d1 : std_logic;
signal dwe_actual : std_logic;
-------------------------------------------------------------------------------
-- The following signals are locally declared signals and will not be connected
-- to any where from XADC hard macro. EDK has dedicated VN/VP ports and these
-- are connected to the board like power supply pins, so it is not required
-- that these ports to be listed in the port list of the core.
-- in simulation these signals will show as un-initialised.
-------------------------------------------------------------------------------
--following signals are added for providing the falling edge interrupt detection
signal ot_d1 : std_logic;
signal ot_falling_edge : std_logic;
--
signal alarm_0_d1 : std_logic;
signal alarm_0_falling_edge : std_logic;
--
signal alarm_3_d1 : std_logic;
signal vbram_alarm_3_falling_edge : std_logic;
--
signal alarm_4_d1 : std_logic;
signal vccpint_alarm_4_falling_edge : std_logic;
--
signal aux_channel_p : std_logic_vector (15 downto 0);
signal aux_channel_n : std_logic_vector (15 downto 0);
signal daddr_A : std_logic_vector(7 downto 0);
signal den_A : std_logic;
signal di_A : std_logic_vector(15 downto 0);
signal dwe_A : std_logic;
signal do_A : std_logic_vector(15 downto 0);
signal drdy_A : std_logic;
signal bbusy_A : std_logic;
signal drp_addr : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Assign temporary internal signal to separate out Addr bit 23 to Addr bit 29
-- from PLB address lines
-- As the addresses for XADC are word aligned, it is required to trim the
-- address bit 30 and 31. The incoming address from PLB is word aligned.
-- The internal register file interface are at sequential address like
-- 0x00h, 0x01h...etc
-------------------------------------------------------------------------------
-- daddr_i <= Bus2IP_Addr(23 to 29);
daddr_i <= Bus2IP_Addr(2 to 8);
-------------------------------------------------------------------------------
-- Data from PLB will be assigned to the DI port of DRP
-- Assign the last half word (bit 16 to 31)data from PLB DATA Bus to the
-- internal signal
-------------------------------------------------------------------------------
di_i <= Bus2IP_Data((C_S_AXI_DATA_WIDTH/2) to C_S_AXI_DATA_WIDTH-1);
-------------------------------------------------------------------------------
-- If jtaglocked_i output from XADC goes high, it prevents read/write access
-- to DRP port
-------------------------------------------------------------------------------
-- JTAGLOCKED_RD_PROCESS
------------------------
-- generate enable signal for DRP. the enable signal is logical AND of
-- chip enable for the address range of REG_FILE_BASEADDR
-------------------------------------------------------------------------------
JTAGLOCKED_RD_PROCESS: process(jtaglocked_i,
Bus2IP_RdCE(CE_NUMBERS-1),
Bus2IP_WrCE(CE_NUMBERS-1)
) is
begin
if (jtaglocked_i ='1') then
den_i <= '0';
else
den_i <= (
Bus2IP_RdCE(CE_NUMBERS-1)
or
Bus2IP_WrCE(CE_NUMBERS-1)
);
end if;
end process JTAGLOCKED_RD_PROCESS;
-------------------------------------------------------------------------------
-- DEN_REG_PROCESS
------------------------
-- generate enable signal for DRP for "Single Clock Cycle" only.
-------------------------------------------------------------------------------
DEN_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
den_d1 <= den_i;
end if;
end process DEN_REG_PROCESS;
den_actual <= den_i and (not den_d1);
-------------------------------------------------------------------------------
-- JTAGLOCKED_WR_PROCESS
------------------------
-- This signal will be interfaced with DWE port of XADC
-------------------------------------------------------------------------------
JTAGLOCKED_WR_PROCESS: process(jtaglocked_i,
Bus2IP_WrCE(CE_NUMBERS-1)
) is
begin
if (jtaglocked_i ='1') then
dwe_i <= '0';
else
dwe_i <= Bus2IP_WrCE(CE_NUMBERS-1);
end if;
end process JTAGLOCKED_WR_PROCESS;
DWE_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
dwe_d1 <= dwe_i;
end if;
end process DWE_REG_PROCESS;
dwe_actual <= dwe_i and (not dwe_d1);
-------------------------------------------------------------------------------
-- JTAGLOCKED_WR_ACK_PROCESS
----------------------------
-- Generate the internal register write_ack, when the DRDY from XADC is high
-- as well as the WrCE(5) signal from PLB is high.
-- This Write Ack is only when PLB accesses DRP port.
-- _____|--------|____ WrCE
-- ___________|--|__ DRDY is active for 1 clock cycle = one clock width ack
-- DRDY will go high after the 4th clock cycle when the data, address, control
-- signals are present on the interface.
-- Delayed the ACK generated when jtaglock='1'.
-------------------------------------------------------------------------------
JTAGLOCKED_WR_ACK_PROCESS:process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if(Bus2IP_Rst = RESET_ACTIVE) then
drdy_wr_ack_i <= '0';
drdy_wr_ack_i_d1 <= '0';
drdy_wr_ack_i_d2 <= '0';
elsif (jtaglocked_i ='1') then
drdy_wr_ack_i_d1 <= Bus2IP_WrCE(CE_NUMBERS-1);
drdy_wr_ack_i_d2 <= drdy_wr_ack_i_d1;
drdy_wr_ack_i <= drdy_wr_ack_i_d1 and (not drdy_wr_ack_i_d2);
else
drdy_wr_ack_i <= drdy_i and Bus2IP_WrCE(CE_NUMBERS-1);
end if;
end if;
end process JTAGLOCKED_WR_ACK_PROCESS;
-------------------------------------------------------------------------------
-- JTAGLOCKED_RD_ACK_PROCESS
----------------------------
-- Generate the internal read_ack, when the DRDY from XADC is high as well as
-- the RdCE(5) signal from PLB is high
-- This Read Ack is only when PLB accesses DRP port.
-- Delayed the ACK generated when jtaglock='1'.
-------------------------------------------------------------------------------
JTAGLOCKED_RD_ACK_PROCESS:process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if(Bus2IP_Rst = RESET_ACTIVE) then
drdy_rd_ack_i <= '0';
drdy_rd_ack_i_d1 <= '0';
drdy_rd_ack_i_d2 <= '0';
elsif (jtaglocked_i ='1') then
drdy_rd_ack_i_d1 <= Bus2IP_RdCE(CE_NUMBERS-1);
drdy_rd_ack_i_d2 <= drdy_rd_ack_i_d1;
drdy_rd_ack_i <= drdy_rd_ack_i_d1 and (not drdy_rd_ack_i_d2);
else
drdy_rd_ack_i <= drdy_i and Bus2IP_RdCE(CE_NUMBERS-1);
end if;
end if;
end process JTAGLOCKED_RD_ACK_PROCESS;
-------------------------------------------------------------------------------
-- It is required to register the DRDY as well as DO ports of the XADC .
-- This will delay the ACK generation by one clock cycle.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- DO_REG_PROCESS
-----------------
-- This process is used to register the DO port of DRP in the
-- local register. If JTAG access is going on, then core need to wait till the
-- JTAG access ends. Once the JTAG access is over the Bus2IP_Addr, DEN are
-- presented to the DRP, then DO of DRP put the data as per the DADDR by making
-- the DRDY high for 1 clock cycle.
-------------------------------------------------------------------------------
DO_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(Bus2IP_Rst = RESET_ACTIVE) then
do_reg <= (others => '0');
elsif (jtaglocked_i ='1') then
do_reg <= (others => '0');
else
do_reg <= do_i;
end if;
end if;
end process DO_REG_PROCESS;
-------------------------------------------------------------------------------
-- combine for CONVST and reset macro write chip enable signals
-------------------------------------------------------------------------------
convst_reset_wrce_select <= Bus2IP_WrCE(3) & Bus2IP_WrCE(4);
-------------------------------------------------------------------------------
-- CONVST_RST_PROCESS:
----------------------
-- This process is used to register the CONVST and XADC RST signals
-- The bit 31st Bus2IP_Data is used along with the Bus2IP_WrCE(3 to 4)
-- to start the conversion or to reset the sysmon through software.
-------------------------------------------------------------------------------
CONVST_RST_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
convst_reg_input <= '0';
hard_macro_rst_reg <= '0';
temp_bus_update <= '0';
temp_rd_wait_cycle_reg <= X"03E8";
else
case convst_reset_wrce_select is
when "10" => convst_reg_input <= Bus2IP_Data(31);
temp_bus_update <= '1';
temp_rd_wait_cycle_reg <= Bus2IP_Data(14 to 29);
when "01" => hard_macro_rst_reg <= Bus2IP_Data(31);
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process CONVST_RST_PROCESS;
-- Generate the WRITE ACK back to PLB
Sysmon_IP2Bus_WrAck <= (drdy_wr_ack_i or local_reg_wrack) ;
-- Generate the READ ACK back to PLB
Sysmon_IP2Bus_RdAck <= (drdy_rd_ack_i or local_reg_rdack_final);
-------------------------------------------------------------------------------
-- Bus reset as well as the hard macro register reset
-------------------------------------------------------------------------------
-- XADC Reset Register (SYSMONRR)
-------------------------------------------------------------------------------
sysmon_hard_block_reset<= Bus2IP_Rst or hard_macro_rst_reg;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- EOC_REG_EXTEND_PROCESS
-------------------------
-- Extend the EOC signal which is active high for 1 clock cycle till the
-- PLB reads the status register.
-- _____|--|__________ one clock width EOC
-- _____|--------|____ extended EOC
-------------------------------------------------------------------------------
EOC_REG_EXTEND_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
eoc_d1 <= '0';
elsif(eoc_i = '1') then
eoc_d1 <= '1';
elsif(status_reg_rdack = '1')then
eoc_d1 <= '0';
end if;
end if;
end process EOC_REG_EXTEND_PROCESS;
eoc_info <= eoc_d1 or eoc_i;
-------------------------------------------------------------------------------
-- EOS_REG_EXTEND_PROCESS
-------------------------
-- Extend the EOS signal which is active high for 1 clock cycle till the
-- PLB reads the status register.
-- _____|--|__________ one clock width EOS
-- _____|--------|____ extended EOS
-------------------------------------------------------------------------------
EOS_REG_EXTEND_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
eos_d1 <= '0';
elsif(eos_i = '1') then
eos_d1 <= '1';
elsif(status_reg_rdack = '1')then
eos_d1 <= '0';
end if;
end if;
end process EOS_REG_EXTEND_PROCESS;
eos_info <= eos_d1 or eos_i;
-------------------------------------------------------------------------------
-- JTAGMODIFIED_EXTEND_PROCESS
-------------------------
-- Extend the JTAGMODIFIED signal which is active high till the DRP read is
-- performed
-- __________|------ RDCE to DRP
-- _____|----|_____ JTAGMODIFIED
-- _______|------|____ extended JTAGMODIFIED
-- _____|--------|____ jtag_modified_info
-------------------------------------------------------------------------------
JTAGMODIFIED_EXTEND_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE or drdy_rd_ack_i = '1') then
jtagmodified_d1 <= '0';
elsif(jtagmodified_i = '1') then
jtagmodified_d1 <= '1';
end if;
end if;
end process JTAGMODIFIED_EXTEND_PROCESS;
jtag_modified_info <= jtagmodified_i or jtagmodified_d1;
-------------------------------------------------------------------------------
-- STATUS_REG_PROCESS
---------------------
-- This process is used to register the JTAG, BUSY, EOC, EOS,
-- & Channel bits in internal register
-------------------------------------------------------------------------------
STATUS_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
status_reg <= (others => '0');
else
status_reg(10) <= jtagbusy_i;
status_reg(9) <= jtag_modified_info;
status_reg(8) <= jtaglocked_i;
status_reg(7) <= busy_i;
status_reg(6) <= eos_info;
status_reg(5) <= eoc_info;
status_reg(4) <= channel_i(4);
status_reg(3) <= channel_i(3);
status_reg(2) <= channel_i(2);
status_reg(1) <= channel_i(1);
status_reg(0) <= channel_i(0);
end if;
end if;
end process STATUS_REG_PROCESS;
busy_out <= busy_i;
channel_out <= channel_i;
eoc_out <= eoc_i;
eos_out <= eos_i;
-------------------------------------------------------------------------------
-- ALARM_REG_PROCESS (ALARM OUTPUT STATUS REGISTER - AOSR)
-----------------------------------------------------------
-- This process is used to register the ALARM, OT bits in internal register
-------------------------------------------------------------------------------
ALARM_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
alarm_reg <= (others => '0');
else
alarm_reg(8) <= alm_i(7);-- added for XADC
alarm_reg(7) <= alm_i(6);
alarm_reg(6) <= alm_i(5);
alarm_reg(5) <= alm_i(4);
alarm_reg(4) <= alm_i(3);-- added for XADC
alarm_reg(3) <= alm_i(2);
alarm_reg(2) <= alm_i(1);
alarm_reg(1) <= alm_i(0);
alarm_reg(0) <= ot_i;
end if;
end if;
end process ALARM_REG_PROCESS;
--------------------------
-- OT_FALLING_EDGE_DETECT: this process is used to register the OT.
--------------------------
-- ____|-------|________ ot_i
-- ______|-------|______ ot_d1
-- ____________|-|______ ot_falling_edge
----------------------------------------
OT_FALLING_EDGE_DETECT: process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
ot_d1 <= ot_i;
end if;
end process OT_FALLING_EDGE_DETECT;
ot_falling_edge <= ot_d1 and (not ot_i);
------------------------------
-- ALARM_0_FALLING_EDGE_DETECT: User temperature settings interrupt falling edge
------------------------------ detection logic
-- ____|-------|________ alm_i(0)
-- ______|-------|______ alm_i(0)_d1
-- ____________|-|______ alarm_0_falling_edge
---------------------------------------------
ALARM_0_FALLING_EDGE_DETECT: process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
alarm_0_d1 <= alm_i(0);
end if;
end process ALARM_0_FALLING_EDGE_DETECT;
alarm_0_falling_edge <= alarm_0_d1 and (not alm_i(0));
------------------------------
-- ALARM_3_FALLING_EDGE_DETECT: VBRM settings interrupt falling edge
------------------------------ detection logic
-- ____|-------|________ alm_i(3)
-- ______|-------|______ alm_i(3)_d1
-- ____________|-|______ vbram_alarm_3_falling_edge
---------------------------------------------
--ALARM_3_FALLING_EDGE_DETECT: process (Bus2IP_Clk) is
--begin
-- if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- alarm_3_d1 <= alm_i(3);
-- end if;
--end process ALARM_3_FALLING_EDGE_DETECT;
--vbram_alarm_3_falling_edge <= alarm_3_d1 and (not alm_i(3));
------------------------------
-- ALARM_4_FALLING_EDGE_DETECT: VCCPINT settings interrupt falling edge
------------------------------ detection logic
-- ____|-------|________ alm_i(4)
-- ______|-------|______ alm_i(4)_d1
-- ____________|-|______ vccpint_alarm_4_falling_edge
---------------------------------------------
--ALARM_4_FALLING_EDGE_DETECT: process (Bus2IP_Clk) is
--begin
-- if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- alarm_4_d1 <= alm_i(4);
-- end if;
--end process ALARM_4_FALLING_EDGE_DETECT;
--vccpint_alarm_4_falling_edge <= alarm_4_d1 and (not alm_i(4));
-------------------------------------------------------------------------------
-- dont register any interrupt signal and just pass
-- it on to the interrupt controller
-------------------------------------------------------------------------------
Interrupt_status(0) <= ot_i;
Interrupt_status(1) <= alm_i(0);
Interrupt_status(2) <= alm_i(1);
Interrupt_status(3) <= alm_i(2);
Interrupt_status(4) <= eos_i;
Interrupt_status(5) <= eoc_i;
Interrupt_status(6) <= jtaglocked_i;
Interrupt_status(7) <= jtagmodified_i;
Interrupt_status(8) <= ot_falling_edge;
Interrupt_status(9) <= alarm_0_falling_edge;
Interrupt_status(10) <= alm_i(3);-- Added for XADC VccBram sensor o/p
Interrupt_status(11) <= alm_i(4); -- XADC VCCPint sensor o/p for Zynq
Interrupt_status(12) <= alm_i(5); -- XADC VCCPaux sensor o/p for Zynq
Interrupt_status(13) <= alm_i(6); -- XADC VCCddro sensor o/p for Zynq
Interrupt_status(14) <= '0';
Interrupt_status(15) <= '0';
Interrupt_status(16) <= '0';
-------------------------------------------------------------------------------
-- Status Register, Alarm Reg and DRP Register File Interface (RFI) can be READ
-------------------------------------------------------------------------------
register_rdce_select <= Bus2IP_RdCE(1) & -- Status Register
Bus2IP_RdCE(2) & -- AOSR
Bus2IP_RdCE(CE_NUMBERS-1);-- DPR
-------------------------------------------------------------------------------
-- The upper bits are always '0'.
-------------------------------------------------------------------------------
sysmon_IP2Bus_Data_i(0 to 13)<=(others => '0');
-------------------------------------------------------------------------------
-- LOCAL_REG_READ_PROCESS
-------------------------
LOCAL_REG_READ_PROCESS: process (register_rdce_select,
status_reg,
alarm_reg,
do_reg,
jtag_modified_info,
jtaglocked_i) is
begin
case register_rdce_select is
-- bus2ip_rdce(1,2,8)
when "100" =>
sysmon_IP2Bus_Data_i(14 to 31) <= "0000000" & status_reg;
when "010" =>
sysmon_IP2Bus_Data_i(14 to 31) <= "000000000" & alarm_reg;
when "001" =>
sysmon_IP2Bus_Data_i(14 to 31) <= jtag_modified_info &
jtaglocked_i &
do_reg;
-- coverage off
when others =>
sysmon_IP2Bus_Data_i(14 to 31) <= (others => '0');
-- coverage on
end case;
end process LOCAL_REG_READ_PROCESS;
-------------------------------------------------------------------------------
-- STATUS_REG_READ_ACK_GEN_PROCESS
----------------------------------
-- To generate the RdAck for status registers, use RdCE
-------------------------------------------------------------------------------
-- _____|-----|_______ rdce
-- ________|--|__________ rd_ack from local registers i.e. status register
-------------------------------------------------------------------------------
STATUS_REG_READ_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
status_reg_rdack_d1 <= '0';
status_reg_rdack <= '0';
else
status_reg_rdack_d1 <= Bus2IP_RdCE(1);
status_reg_rdack <= Bus2IP_RdCE(1) and (not status_reg_rdack_d1);
end if;
end if;
end process STATUS_REG_READ_ACK_GEN_PROCESS;
-------------------------------------------------------------------------------
-- For register which are just write-only a read ack is required for completing
-- the transaction.
-------------------------------------------------------------------------------
local_rdce_or_reduce <= or_reduce(Bus2IP_RdCE(2 to 4));
-------------------------------------------------------------------------------
-- LOCAL_REG_READ_ACK_GEN_PROCESS
---------------------------------
-- To generate the RdAck for alarm,CONVST,XADC Hard Macro registers,
-- use RdCE
-------------------------------------------------------------------------------
-- _____|-----|_______ rdce
-- ________|--|__________ rd_ack from local registers
-------------------------------------------------------------------------------
LOCAL_REG_READ_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
local_reg_rdack_d1 <= '0';
local_reg_rdack <= '0';
else
local_reg_rdack_d1 <= local_rdce_or_reduce;
local_reg_rdack <= local_rdce_or_reduce and (not local_reg_rdack_d1);
end if;
end if;
end process LOCAL_REG_READ_ACK_GEN_PROCESS;
local_reg_rdack_final <= status_reg_rdack or local_reg_rdack;
-------------------------------------------------------------------------------
-- For register which are just read-only a write ack is required for completing
-- the transaction.
-------------------------------------------------------------------------------
convst_rst_wrce_or_reduce <= or_reduce(Bus2IP_WrCE(1 to 4));
-------------------------------------------------------------------------------
-- LOCAL_REG_WRITE_ACK_GEN_PROCESS
----------------------------------
-- To generate the WrAck for local registers, use WrCE
-------------------------------------------------------------------------------
-- _____|-----|_______ wrce
-- ________|--|__________ wr_ack from local registers
-- i.e. convst,reset register
-------------------------------------------------------------------------------
LOCAL_REG_WRITE_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
local_reg_wrack_d1 <= '0';
local_reg_wrack <= '0';
else
local_reg_wrack_d1 <= convst_rst_wrce_or_reduce;
local_reg_wrack <= convst_rst_wrce_or_reduce and
(not local_reg_wrack_d1);
end if;
end if;
end process LOCAL_REG_WRITE_ACK_GEN_PROCESS;
-------------------------------------------------------------------------------
-- All the signals listed here are FROM IP to PLB IPIF INTERFACE
-------------------------------------------------------------------------------
-- Present the DRP data to Sysmon_IP2Bus_Data
Sysmon_IP2Bus_Data <= sysmon_IP2Bus_Data_i;
-------------------------------------------------------------------------------
-- Added interface to ALARM signals from the XADC macro to core ports.
------------------------------------------------------------------------
alarm_out <= alarm_reg(8 downto 1);-- updated from 2 downto 1 to 8 downto 1 for XADC
------------------------------------------------------------------------
daddr_i_int <= '0' & daddr_i;
-- Instantiate the temperature_update and arbiter
temperature_update_inst: temperature_update port map (
reset => sysmon_hard_block_reset,
clk => Bus2IP_Clk,
wait_cycle => temp_rd_wait_cycle_reg,
temp_out => temp_out,
temp_bus_update => temp_bus_update,
daddr_o => daddr_A,
den_o => den_A,
di_o => di_A,
dwe_o => dwe_A,
do_i => do_A,
drdy_i => drdy_A,
busy_o => bbusy_A
);
Inst_drp_arbiter: drp_arbiter port map (
reset => sysmon_hard_block_reset,
clk => Bus2IP_Clk ,
jtaglocked => jtaglocked_i,
bgrant_A => open ,
bgrant_B => bgrant_B,
bbusy_A => bbusy_A,
bbusy_B => '0',
daddr_A => daddr_A,
den_A => den_A,
di_A => di_A,
dwe_A => dwe_A,
do_A => do_A,
drdy_A => drdy_A,
daddr_B => daddr_i_int,
den_B => den_actual,
di_B => di_i,
dwe_B => dwe_actual,
do_B => do_i,
drdy_B => drdy_i,
daddr_C => daddr_C,
den_C => den_C,
di_C => di_C,
dwe_C => dwe_C,
do_C => do_C,
drdy_C => drdy_C
);
-- Added interface to MUX ADDRESS for external address multiplexer from the
-- XADC macro to core ports.
-------------------------------------------------------------------------------
-- == XADC INTERFACE -- OUTPUT Signals ==
-------------------------------------------------------------------------------
-- BUSY -- ADC busy signal
-- DRDY -- Data ready signal for Dynamic Reconfigurable Port
-- EOC -- End of conversion for ADC
-- EOS -- End of sequence used in auto sequence mode
-- JTAGBUSY -- Used to indicate that the JTAG DRP is doing transaction
-- JTAGLOCKED -- Used to indicate the DRP port lock is requested
-- JTAGMODIFIED -- Used to indicate that the JTAG write to JTAG is happened
-- OT -- Signal for Over Temperature alarm
-- ALM -- Sysmon Alarm outputs
-- CHANNEL -- Channel selection outputs
-- DO -- Output data bus for Dynamic Reconfigurable Port
-------------------------------------------------------------------------------
-- == XADC INTERFACE -- INPUT Signals ==
-------------------------------------------------------------------------------
-- VN -- High Bandwidth Dedicated analog input pair
-- VP which provides differential analog input. These pins are
-- just like dedicated suply pins and user dont have control
-- over these pins.
-- CONVST -- Conversion start input used in event driven sampling
-- CONVSTCLK -- Conversion start clock input
-- DCLK -- Clock input for Dynamic Reconfigurable Port
-- DEN -- Enable signal for Dynamic Reconfigurable Port
-- DWE -- Write Enable signal for Dynamic Reconfigurable Port
-- RESET -- External hard Reset input
-- DADDR -- Address bus for Dynamic Reconfigurable Port
-- DI -- Input data bus for Dynamic Reconfigurable Port
-- VAUXN -- Low Bandwidth, Sixteen auxiliary analog input pairs
-- VAUXP which provides differential analog inputs
-- MUXADDR -- External address multiplexer driven by Channel selection
-- Registers
aux_channel_p(0) <= vauxp0;
aux_channel_n(0) <= vauxn0;
aux_channel_p(1) <= vauxp1;
aux_channel_n(1) <= vauxn1;
aux_channel_p(2) <= vauxp2;
aux_channel_n(2) <= vauxn2;
aux_channel_p(3) <= '0';
aux_channel_n(3) <= '0';
aux_channel_p(4) <= vauxp4;
aux_channel_n(4) <= vauxn4;
aux_channel_p(5) <= vauxp5;
aux_channel_n(5) <= vauxn5;
aux_channel_p(6) <= vauxp6;
aux_channel_n(6) <= vauxn6;
aux_channel_p(7) <= vauxp7;
aux_channel_n(7) <= vauxn7;
aux_channel_p(8) <= '0';
aux_channel_n(8) <= '0';
aux_channel_p(9) <= vauxp9;
aux_channel_n(9) <= vauxn9;
aux_channel_p(10) <= vauxp10;
aux_channel_n(10) <= vauxn10;
aux_channel_p(11) <= '0';
aux_channel_n(11) <= '0';
aux_channel_p(12) <= vauxp12;
aux_channel_n(12) <= vauxn12;
aux_channel_p(13) <= vauxp13;
aux_channel_n(13) <= vauxn13;
aux_channel_p(14) <= vauxp14;
aux_channel_n(14) <= vauxn14;
aux_channel_p(15) <= vauxp15;
aux_channel_n(15) <= vauxn15;
XADC_INST : XADC
generic map(
INIT_40 => X"0000", -- config reg 0
INIT_41 => X"21A1", -- config reg 1
INIT_42 => X"0400", -- config reg 2
INIT_48 => X"0900", -- Sequencer channel selection
INIT_49 => X"F6F7", -- Sequencer channel selection
INIT_4A => X"0000", -- Sequencer Average selection
INIT_4B => X"0000", -- Sequencer Average selection
INIT_4C => X"0000", -- Sequencer Bipolar selection
INIT_4D => X"0000", -- Sequencer Bipolar selection
INIT_4E => X"0000", -- Sequencer Acq time selection
INIT_4F => X"0000", -- Sequencer Acq time selection
INIT_50 => X"B5ED", -- Temp alarm trigger
INIT_51 => X"53A0", -- Vccint upper alarm limit
INIT_52 => X"A147", -- Vccaux upper alarm limit
INIT_53 => X"CA33", -- Temp alarm OT upper
INIT_54 => X"A93A", -- Temp alarm reset
INIT_55 => X"5111", -- Vccint lower alarm limit
INIT_56 => X"9555", -- Vccaux lower alarm limit
INIT_57 => X"AE4E", -- Temp alarm OT reset
INIT_58 => X"5999", -- Vccbram upper alarm limit
INIT_5C => X"5111", -- Vccbram lower alarm limit
SIM_DEVICE => "7SERIES",
SIM_MONITOR_FILE => "design.txt"
)
port map (
CONVST => '0',
CONVSTCLK => '0',
DADDR => daddr_C(6 downto 0), --: in (6 downto 0)
DCLK => Bus2IP_Clk, --: in
DEN => den_C, --: in
DI => di_C, --: in (15 downto 0)
DWE => dwe_C, --: in
RESET => sysmon_hard_block_reset, --: in
VAUXN(15 downto 0) => aux_channel_n(15 downto 0),
VAUXP(15 downto 0) => aux_channel_p(15 downto 0),
ALM => alm_i,
BUSY => busy_i, --: out
CHANNEL => channel_i, --: out (4 downto 0)
DO => do_C, --: out (15 downto 0)
DRDY => drdy_C, --: out
EOC => eoc_i, --: out
EOS => eos_i, --: out
JTAGLOCKED => jtaglocked_i, --: out
JTAGBUSY => jtagbusy_i, --: out
JTAGMODIFIED => jtagmodified_i, --: out
OT => ot_i, --: out
VN => vn_in,
VP => vp_in
);
end architecture imp;
--------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: jtag
-- File: jtag.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package jtag is
-- JTAG manufacturer IDs
constant JTAG_MANF_ID_GR : integer range 0 to 2047 := 804;
-- JTAG part numbers
-- Do NOT select an existing part number for your custom design!
--
-- For your design, please select a JTAG ID that starts with 16#a--#
-- and notify Aeroflex Gaisler (in case do not change the manufacturer
-- ID to your own ID).
constant JTAG_EXAMPLE_PART : integer range 0 to 65535 := 16#300#;
component ahbjtag
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
scantest : integer := 0;
oepol : integer := 1;
tcknen : integer := 0;
versel : integer range 0 to 1 := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapi_tdo : in std_ulogic;
trst : in std_ulogic := '1';
tdoen : out std_ulogic;
tckn : in std_ulogic := '0';
tapo_tckn : out std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic
);
end component;
component ahbjtag_bsd
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
asel : in std_ulogic;
dsel : in std_ulogic;
tck : in std_ulogic;
regi : in std_ulogic;
shift : in std_ulogic;
rego : out std_ulogic
);
end component;
component bscanctrl
generic (
spinst: integer := 5; -- sample/preload
etinst: integer := 6; -- extest
itinst: integer := 7; --intest
hzinst: integer := 8; -- highz
clinst: integer := 10; -- clamp
mbist : integer := 11; -- mbist
testx1: integer := 12; -- generic test command
scantest : integer := 0
);
port (
trst : in std_ulogic;
tapo_tck : in std_ulogic;
tapo_tckn : in std_ulogic;
tapo_tdi : in std_ulogic;
tapo_ninst : in std_logic_vector(7 downto 0);
tapo_iupd : in std_ulogic;
tapo_rst : in std_ulogic;
tapo_capt : in std_ulogic;
tapo_shft : in std_ulogic;
tapo_upd : in std_ulogic;
tapi_tdo : out std_ulogic;
chain_tdi : out std_ulogic;
chain_tdo : in std_ulogic;
bsshft : out std_ulogic;
bscapt : out std_ulogic;
bsupdi : out std_ulogic;
bsupdo : out std_ulogic;
bsdrive : out std_ulogic;
bshighz : out std_ulogic;
bsmbist : out std_ulogic;
bstestx1 : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
bypass_tdo : out std_ulogic;
mbist_tdo : in std_ulogic := '0'
);
end component;
component bscanregs
generic (
tech: integer := 0;
nsigs: integer range 1 to 30 := 8;
dirmask: integer := 2#00000000#;
enable: integer range 0 to 1 := 1
);
port (
sigi: in std_logic_vector(nsigs-1 downto 0);
sigo: out std_logic_vector(nsigs-1 downto 0);
tck: in std_ulogic;
tckn:in std_ulogic;
tdi: in std_ulogic;
tdo: out std_ulogic;
bsshft: in std_ulogic;
bscapt: in std_ulogic;
bsupdi: in std_ulogic;
bsupdo: in std_ulogic;
bsdrive: in std_ulogic;
bshighz: in std_ulogic
);
end component;
component bscanregsbd
generic (
tech: integer:= 0;
nsigs: integer := 8;
enable: integer range 0 to 1 := 1;
hzsup: integer range 0 to 1 := 1
);
port (
pado : out std_logic_vector(nsigs-1 downto 0);
padoen : out std_logic_vector(nsigs-1 downto 0);
padi : in std_logic_vector(nsigs-1 downto 0);
coreo : in std_logic_vector(nsigs-1 downto 0);
coreoen : in std_logic_vector(nsigs-1 downto 0);
corei : out std_logic_vector(nsigs-1 downto 0);
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive outdata regs to pad,
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
bshighz : in std_ulogic -- tri-state output if hzsup, sample 1 on input
);
end component;
end;
|
------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2axi
-- File: ahb2axi.vhd
-- Author: Jiri Gaisler (edited by Martin George)
--
-- AHB/AXI bridge for Cyclone V SoC FPGA to HPS bridge
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2axi is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
idsize : integer := 8;
lensize : integer := 4;
addrsize : integer := 32
);
port(
rstn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
m_axi_araddr : out std_logic_vector ( addrsize-1 downto 0 );
m_axi_arburst : out std_logic_vector ( 1 downto 0 );
m_axi_arcache : out std_logic_vector ( 3 downto 0 );
m_axi_arid : out std_logic_vector ( idsize-1 downto 0 );
m_axi_arlen : out std_logic_vector ( lensize-1 downto 0 );
m_axi_arlock : out std_logic_vector (1 downto 0);
m_axi_arprot : out std_logic_vector ( 2 downto 0 );
m_axi_arqos : out std_logic_vector ( 3 downto 0 );
m_axi_arready : in std_logic;
m_axi_arsize : out std_logic_vector ( 2 downto 0 );
m_axi_arvalid : out std_logic;
m_axi_awaddr : out std_logic_vector ( addrsize-1 downto 0 );
m_axi_awburst : out std_logic_vector ( 1 downto 0 );
m_axi_awcache : out std_logic_vector ( 3 downto 0 );
m_axi_awid : out std_logic_vector ( idsize-1 downto 0 );
m_axi_awlen : out std_logic_vector ( lensize-1 downto 0 );
m_axi_awlock : out std_logic_vector (1 downto 0);
m_axi_awprot : out std_logic_vector ( 2 downto 0 );
m_axi_awqos : out std_logic_vector ( 3 downto 0 );
m_axi_awready : in std_logic;
m_axi_awsize : out std_logic_vector ( 2 downto 0 );
m_axi_awvalid : out std_logic;
m_axi_bid : in std_logic_vector ( idsize-1 downto 0 );
m_axi_bready : out std_logic;
m_axi_bresp : in std_logic_vector ( 1 downto 0 );
m_axi_bvalid : in std_logic;
m_axi_rdata : in std_logic_vector ( 31 downto 0 );
m_axi_rid : in std_logic_vector ( idsize-1 downto 0 );
m_axi_rlast : in std_logic;
m_axi_rready : out std_logic;
m_axi_rresp : in std_logic_vector ( 1 downto 0 );
m_axi_rvalid : in std_logic;
m_axi_wdata : out std_logic_vector ( 31 downto 0 );
m_axi_wid : out std_logic_vector ( idsize-1 downto 0 );
m_axi_wlast : out std_logic;
m_axi_wready : in std_logic;
m_axi_wstrb : out std_logic_vector ( 3 downto 0 );
m_axi_wvalid : out std_logic
);
end;
architecture rtl of ahb2axi is
type bstate_type is (idle, read1, read2, read3, write1, write2, write3);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHB2AXI, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type reg_type is record
bstate : bstate_type;
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
m_axi_arlen : std_logic_vector (lensize-1 downto 0 );
m_axi_rdata : std_logic_vector (31 downto 0 );
m_axi_arvalid : std_logic;
m_axi_awvalid : std_logic;
m_axi_rready : std_logic;
m_axi_wstrb : std_logic_vector (3 downto 0 );
m_axi_bready : std_logic;
m_axi_wvalid : std_logic;
m_axi_wlast : std_logic;
m_axi_bresp : std_logic_vector (1 downto 0 );
m_axi_awaddr : std_logic_vector (addrsize-1 downto 0 );
end record;
signal r, rin : reg_type;
begin
comb: process( rstn, r, ahbsi, m_axi_arready, m_axi_rlast, m_axi_rvalid,
m_axi_awready, m_axi_wready, m_axi_bvalid, m_axi_bresp, m_axi_rdata )
variable v : reg_type;
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector (3 downto 0 );
begin
v := r;
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1';
v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
v.haddr := ahbsi.haddr;
else
v.hsel := '0';
v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
case r.hsize(1 downto 0) is
when "00" => wstrb := decode(not r.haddr(1 downto 0));
when "01" =>
if r.haddr(1) = '1' then
wstrb := "0011";
else
wstrb := "1100";
end if;
when others =>
wstrb := "1111";
end case;
case r.bstate is
when idle =>
if v.hsel = '1' then
if v.hwrite = '1' then
v.bstate := write1;
v.hready := '1';
else
v.bstate := read1;
v.m_axi_arvalid := '1';
end if;
end if;
when read1 =>
if m_axi_arready = '1' then
v.m_axi_arvalid := '0';
v.bstate := read2;
v.m_axi_rready := '1';
end if;
when read2 =>
v.hready := '0';
if m_axi_rvalid = '1' then
v.m_axi_rdata := m_axi_rdata;
v.hready := '1';
end if;
if (r.hready = '1') and (ahbsi.htrans /= "11") then
v.bstate := read3;
if v.hsel = '1' then
v.hready := '0';
end if;
end if;
if (m_axi_rlast = '1') and (m_axi_rvalid = '1') then
v.bstate := idle;
v.m_axi_rready := '0';
end if;
when read3 =>
if (m_axi_rlast = '1') and (m_axi_rvalid = '1') then
v.bstate := idle;
v.m_axi_rready := '0';
end if;
when write2 =>
if m_axi_awready = '1' then
v.m_axi_awvalid := '0';
v.bstate := write3;
v.m_axi_wvalid := '1';
v.m_axi_wlast := '1';
end if;
when write3 =>
if m_axi_wready = '1' then
v.m_axi_wlast := '0';
v.bstate := idle;
v.m_axi_wvalid := '0';
v.m_axi_wlast := '0';
end if;
when write1 =>
v.m_axi_awvalid := '1';
v.m_axi_awaddr := r.haddr(addrsize-1 downto 2) & "00";
v.m_axi_wstrb := wstrb;
v.hwdata := ahbsi.hwdata;
v.bstate := write2;
end case;
if (m_axi_bvalid = '1') and (r.m_axi_bresp = "00") then
v.m_axi_bresp := m_axi_bresp;
end if;
if rstn = '0' then
v.bstate := idle; v.hready := '1';
v.m_axi_arvalid := '0';
v.m_axi_rready := '0';
v.m_axi_rready := '0';
v.m_axi_wstrb := (others => '0');
v.m_axi_bready := '0';
v.m_axi_wvalid := '0';
v.m_axi_wlast := '0';
v.m_axi_bresp := "00";
v.m_axi_awvalid := '0';
end if;
rin <= v;
end process;
m_axi_araddr <= r.haddr(addrsize-1 downto 2) & "00";
m_axi_awaddr <= r.m_axi_awaddr(addrsize-1 downto 0);
m_axi_arburst <= "01";
m_axi_arcache <= "0011";
m_axi_arid <= (others => '0');
m_axi_arlen <= (others => '0');
m_axi_arlock <= (others => '0');
m_axi_arprot <= "001";
m_axi_arsize <= "010";
m_axi_arvalid <= r.m_axi_arvalid;
m_axi_rready <= r.m_axi_rready;
m_axi_arqos <= (others => '0');
m_axi_awburst <= "01";
m_axi_awcache <= "0011";
m_axi_awid <= (others => '0');
m_axi_awlen <= (others => '0');
m_axi_awlock <= (others => '0');
m_axi_awprot <= "001";
m_axi_awsize <= "010";
m_axi_awvalid <= r.m_axi_awvalid;
m_axi_awqos <= (others => '0');
m_axi_rready <= r.m_axi_rready;
m_axi_wstrb <= r.m_axi_wstrb;
m_axi_bready <= '1';
m_axi_wvalid <= r.m_axi_wvalid;
m_axi_wlast <= r.m_axi_wlast;
m_axi_wdata <= r.hwdata;
m_axi_wid <= (others => '0');
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.m_axi_rdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
----------------------------------------------------------------------------------
-- Company: RAT Technologies (a subdivision of Cal Poly CENG)
-- Engineer: Various RAT rats
--
-- Create Date: 02/03/2017
-- Module Name: RAT_wrapper - Behavioral
-- Target Devices: Basys3
-- Description: Wrapper for RAT CPU. This model provides a template to interfaces
-- the RAT CPU to the Basys3 development board.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAT_Basys3_wrapper is
Port ( LEDS : out STD_LOGIC_VECTOR (7 downto 0);
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC);
end RAT_Basys3_wrapper;
architecture Behavioral of RAT_Basys3_wrapper is
-- INPUT PORT IDS -------------------------------------------------------------
-- Right now, the only possible inputs are the switches
-- In future labs you can add more port IDs, and you'll have
-- to add constants here for the mux below
CONSTANT SWITCHES_ID : STD_LOGIC_VECTOR (7 downto 0) := X"20";
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- OUTPUT PORT IDS ------------------------------------------------------------
-- In future labs you can add more port IDs
CONSTANT LEDS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"40";
-------------------------------------------------------------------------------
-- Declare RAT_CPU ------------------------------------------------------------
component RAT_wrapper
Port ( IN_PORT : in STD_LOGIC_VECTOR (7 downto 0);
OUT_PORT : out STD_LOGIC_VECTOR (7 downto 0);
PORT_ID : out STD_LOGIC_VECTOR (7 downto 0);
INT_IN : in STD_LOGIC_VECTOR (0 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC);
end component RAT_wrapper;
-------------------------------------------------------------------------------
-- Signals for connecting RAT_CPU to RAT_wrapper -------------------------------
signal s_input_port : std_logic_vector (7 downto 0);
signal s_output_port : std_logic_vector (7 downto 0);
signal s_port_id : std_logic_vector (7 downto 0);
--signal s_interrupt : std_logic; -- not yet used
-- Register definitions for output devices ------------------------------------
-- add signals for any added outputs
signal r_LEDS : std_logic_vector (7 downto 0);
-------------------------------------------------------------------------------
begin
-- Instantiate RAT_CPU --------------------------------------------------------
CPU: RAT_wrapper
port map( IN_PORT => s_input_port,
OUT_PORT => s_output_port,
PORT_ID => s_port_id,
INT_IN => "0", -- s_interrupt
CLK => CLK,
RST => '0');
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- MUX for selecting what input to read ---------------------------------------
-- add conditions and connections for any added PORT IDs
-------------------------------------------------------------------------------
inputs: process(s_port_id, SWITCHES)
begin
if (s_port_id = SWITCHES_ID) then
s_input_port <= SWITCHES;
else
s_input_port <= x"00";
end if;
end process inputs;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- MUX for updating output registers ------------------------------------------
-- Register updates depend on rising clock edge and asserted load signal
-- add conditions and connections for any added PORT IDs
-------------------------------------------------------------------------------
outputs: process(CLK)
begin
if (rising_edge(CLK)) then
-- the register definition for the LEDS
if (s_port_id = LEDS_ID) then
r_LEDS <= s_output_port;
end if;
end if;
end process outputs;
-------------------------------------------------------------------------------
-- Register Interface Assignments ---------------------------------------------
-- add all outputs that you added to this design
LEDS <= r_LEDS;
end Behavioral;
|
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: fifo_test_1.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 132 02/25/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fifo_test_1 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END fifo_test_1;
ARCHITECTURE SYN OF fifo_test_1 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
rdreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
full : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
q <= sub_wire1(15 DOWNTO 0);
full <= sub_wire2;
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "ON",
intended_device_family => "Cyclone III",
lpm_hint => "RAM_BLOCK_TYPE=M9K",
lpm_numwords => 32,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => 16,
lpm_widthu => 5,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
rdreq => rdreq,
clock => clock,
wrreq => wrreq,
data => data,
empty => sub_wire0,
q => sub_wire1,
full => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "32"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "16"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "16"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_test_1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_test_1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_test_1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_test_1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_test_1_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_test_1_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_test_1_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
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